[PATCH v6 0/6] drm/i915/dp: Support for DP YCbCr4:2:0 outputs

[PATCH v6 0/6] drm/i915/dp: Support for DP YCbCr4:2:0 outputs

[Gwan-gyeong Mun]

On Gen 11 platform, to enable resolutions like 5K@120 (or higher) we need
to use DSC (DP 1.4) or YCbCr4:2:0 (DP 1.3 or 1.4) on DP.
In order to support YCbCr4:2:0 on DP we need to program YCBCR 4:2:0
to MSA and VSC SDP.
And Link M/N values are calculated and applied based on the Full Clock
forYCbCr420.
The Bit per Pixel needs to be adjusted for YUV420 mode as it requires only
half of the RGB case.
 - Link M/N values are calculated and applied based on the Full Clock
 - Data M/N values needs to be calculated considering the data is half
   due to subsampling

These patches add a VSC structure for handling Pixel Encoding/Colorimetry
Formats and program YCBCR 4:2:0 to MSA and VSC SDP. And it changes a link
bandwidth computation for DP.

These patches tested on below test environment.
Test Environment: 
 - Tested System: Gen11 platform
 - Monitor: Wasabi Mango UHD430 REAL4K HDMI 2.0 Slim HDR DUAL DP i20
            (This monitor supports HDMI YCbCr 4:2:0)
 - DP to HDMI Adaptor (Dongle) : Club3D CAC-1080 (This dongle supports
                                 DP YCbCr 4:2:0 pass through feature.)
 - To enable DP YCbCr 4:2:0 forcely, test enviromnent uses work arounds
   patches. You can find these on
   https://gitlab.freedesktop.org/elongbug/drm-tip/tree/dp_ycbcr420_work

The idea of a scaling (RGB -> YCbCr4:4:4 -> YCbCr 4:2:0) is to follow the
same approach used in YCbCr 4:2:0 on HDMI.

v2: Addressed Maarten's review comments, fixed minor coding and block comment
style. And reordered a first patch  ("drm/i915/dp: Support DP ports
YUV 4:2:0 output to GEN11") as a last patch.

v3: Addressed Ville's review comments.
Style fixed with few naming.
If lscon is active, it makes not to call intel_dp_ycbcr420_config() to avoid
to clobber of lspcon_ycbcr420_config() routine.
And it move the 420_only check into the intel_dp_ycbcr420_config().
Remove a changing of pipe_bpp on intel_ddi_set_pipe_settings().
Because the pipe is running at the full bpp, keep pipe_bpp as RGB even though
YCbCr 4:2:0 output format is used.
Add a link bandwidth computation for YCbCr4:2:0 output format.

v4: Fix uninitialized return value which is reported by Dan Carpenter.

v5: Addressed reivew comments from Ville.
In order to make codes simple, it adds and uses intel_dp_output_bpp() function.
In order to avoid the extra indentation, it inverts if-clause on
intel_dp_ycbcr420_config().
Remove the error print where no errors print are allowed.

v6:
Link M/N values are calculated and applied based on the Full Clock for
YCbCr420. The Bit per Pixel needs to be adjusted for YUV420 mode as it
requires only half of the RGB case.
 - Link M/N values are calculated and applied based on the Full Clock
 - Data M/N values needs to be calculated considering the data is half due
   to subsampling
Remove a doubling of pixel clock on a dot clock calculator for DP YCbCr 4:2:0.
Rebase and remove a duplicate setting of vsc_sdp.DB17.
Add a setting of dynamic range bit to  vsc_sdp.DB17.
Change Content Type bit to "Graphics" from "Not defined".
Change a dividing of pipe_bpp to muliplying to constant values on a switch-case
statement.
Fix an wrong setting of MSA MISC1 fields for Pixel Encoding/Colorimetry
Format indication. As per DP 1.4a spec Table 2-96 [MSA MISC1 and MISC0
Fields for Pixel Encoding/Colorimetry Format Indication] When MISC1, bit 6,
is Set to 1, a Source device uses a VSC SDP to indicate the Pixel
Encoding/Colorimetry Format. On the wrong version it set a bit 5 of MISC1,
now it set a bit 6 of MISC1.

References: https://patchwork.freedesktop.org/series/56059/

Gwan-gyeong Mun (6):
  drm/i915/dp: Add a config function for YCBCR420 outputs
  drm: Add a VSC structure for handling Pixel Encoding/Colorimetry
    Formats
  drm/i915/dp: Program VSC Header and DB for Pixel Encoding/Colorimetry
    Format
  drm/i915/dp: Add a support of YCBCR 4:2:0 to DP MSA
  drm/i915/dp: Change a link bandwidth computation for DP
  drm/i915/dp: Support DP ports YUV 4:2:0 output to GEN11

 drivers/gpu/drm/i915/i915_reg.h  |   1 +
 drivers/gpu/drm/i915/intel_ddi.c |  12 ++-
 drivers/gpu/drm/i915/intel_dp.c  | 149 ++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_drv.h |   2 +
 include/drm/drm_dp_helper.h      |  17 ++++
 5 files changed, 178 insertions(+), 3 deletions(-)

-- 
2.21.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v6 1/6] drm/i915/dp: Add a config function for YCBCR420 outputs

[Gwan-gyeong Mun]

This patch checks a support of YCBCR420 outputs on an encoder level.
If the input mode is YCBCR420-only mode then it prepares DP as an YCBCR420
output, else it continues with RGB output mode.
It set output_format to INTEL_OUTPUT_FORMAT_YCBCR420 in order to using
a pipe scaler as RGB to YCbCr 4:4:4.

v2:
  Addressed review comments from Ville.
  Style fixed with few naming.
  %s/config/crtc_state/
  %s/intel_crtc/crtc/
  If lscon is active, it makes not to call intel_dp_ycbcr420_config()
  to avoid to clobber of lspcon_ycbcr420_config() routine.
  And it move the 420_only check into the intel_dp_ycbcr420_config().

v3: Fix uninitialized return value and it is reported by Dan Carpenter.

v4:
  Addressed review comments from Ville.
  In order to avoid the extra indentation, it inverts if-clause on
  intel_dp_ycbcr420_config().
  Remove the error print where no errors print are allowed.

v6: Rebase

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 35 ++++++++++++++++++++++++++++++++-
 1 file changed, 34 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 53cc4afea256..06a3417a88d1 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2085,6 +2085,34 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
 	return 0;
 }
 
+static int
+intel_dp_ycbcr420_config(struct drm_connector *connector,
+			 struct intel_crtc_state *crtc_state)
+{
+	const struct drm_display_info *info = &connector->display_info;
+	const struct drm_display_mode *adjusted_mode =
+		&crtc_state->base.adjusted_mode;
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	int ret;
+
+	if (!drm_mode_is_420_only(info, adjusted_mode) ||
+	    !connector->ycbcr_420_allowed)
+		return 0;
+
+	crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
+
+	/* YCBCR 420 output conversion needs a scaler */
+	ret = skl_update_scaler_crtc(crtc_state);
+	if (ret) {
+		DRM_DEBUG_KMS("Scaler allocation for output failed\n");
+		return ret;
+	}
+
+	intel_pch_panel_fitting(crtc, crtc_state, DRM_MODE_SCALE_FULLSCREEN);
+
+	return 0;
+}
+
 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
 				  const struct drm_connector_state *conn_state)
 {
@@ -2124,7 +2152,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 		to_intel_digital_connector_state(conn_state);
 	bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
 					   DP_DPCD_QUIRK_CONSTANT_N);
-	int ret, output_bpp;
+	int ret = 0, output_bpp;
 
 	if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
 		pipe_config->has_pch_encoder = true;
@@ -2132,6 +2160,11 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 	if (lspcon->active)
 		lspcon_ycbcr420_config(&intel_connector->base, pipe_config);
+	else
+		ret = intel_dp_ycbcr420_config(&intel_connector->base, pipe_config);
+
+	if (ret)
+		return ret;
 
 	pipe_config->has_drrs = false;
 	if (IS_G4X(dev_priv) || port == PORT_A)
-- 
2.21.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v6 2/6] drm: Add a VSC structure for handling Pixel Encoding/Colorimetry Formats

[Gwan-gyeong Mun]

SDP VSC Header and Data Block follow DP 1.4a spec, section 2.2.5.7.5,
chapter "VSC SDP Payload for Pixel Encoding/Colorimetry Format".

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 include/drm/drm_dp_helper.h | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 97ce790a5b5a..3793bea7b7fe 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1096,6 +1096,23 @@ struct edp_vsc_psr {
 	u8 DB8_31[24]; /* Reserved */
 } __packed;
 
+struct dp_vsc_sdp {
+	struct dp_sdp_header sdp_header;
+	u8 DB0; /* Stereo Interface */
+	u8 DB1; /* 0 - PSR State; 1 - Update RFB; 2 - CRC Valid */
+	u8 DB2; /* CRC value bits 7:0 of the R or Cr component */
+	u8 DB3; /* CRC value bits 15:8 of the R or Cr component */
+	u8 DB4; /* CRC value bits 7:0 of the G or Y component */
+	u8 DB5; /* CRC value bits 15:8 of the G or Y component */
+	u8 DB6; /* CRC value bits 7:0 of the B or Cb component */
+	u8 DB7; /* CRC value bits 15:8 of the B or Cb component */
+	u8 DB8_15[8];  /* Reserved */
+	u8 DB16; /* Pixel Encoding and Colorimetry Formats */
+	u8 DB17; /* Dynamic Range and Component Bit Depth */
+	u8 DB18; /* Content Type */
+	u8 DB19_31[13]; /* Reserved */
+} __packed;
+
 #define EDP_VSC_PSR_STATE_ACTIVE	(1<<0)
 #define EDP_VSC_PSR_UPDATE_RFB		(1<<1)
 #define EDP_VSC_PSR_CRC_VALUES_VALID	(1<<2)
-- 
2.21.0

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH v6 3/6] drm/i915/dp: Program VSC Header and DB for Pixel Encoding/Colorimetry Format

[Gwan-gyeong Mun]

Function intel_pixel_encoding_setup_vsc handles vsc header and data block
setup for pixel encoding / colorimetry format.

Setup VSC header and data block in function intel_pixel_encoding_setup_vsc
for pixel encoding / colorimetry format as per dp 1.4a spec,
section 2.2.5.7.1, table 2-119: VSC SDP Header Bytes, section 2.2.5.7.5,
table 2-120:VSC SDP Payload for DB16 through DB18.

v2:
  Minor style fix. [Maarten]
  Refer to commit ids instead of patchwork. [Maarten]

v6: Rebase

Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c |  1 +
 drivers/gpu/drm/i915/intel_dp.c  | 73 ++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h |  2 +
 3 files changed, 76 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index cd5277d98b03..2f1688ea5a2c 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3391,6 +3391,7 @@ static void intel_enable_ddi_dp(struct intel_encoder *encoder,
 
 	intel_edp_backlight_on(crtc_state, conn_state);
 	intel_psr_enable(intel_dp, crtc_state);
+	intel_dp_ycbcr_420_enable(intel_dp, crtc_state);
 	intel_edp_drrs_enable(intel_dp, crtc_state);
 
 	if (crtc_state->has_audio)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 06a3417a88d1..74aad8830a80 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4394,6 +4394,79 @@ u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
 	return 0;
 }
 
+static void
+intel_pixel_encoding_setup_vsc(struct intel_dp *intel_dp,
+			       const struct intel_crtc_state *crtc_state)
+{
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct dp_vsc_sdp vsc_sdp;
+
+	if (!intel_dp->attached_connector->base.ycbcr_420_allowed)
+		return;
+
+	/* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 */
+	memset(&vsc_sdp, 0, sizeof(vsc_sdp));
+	vsc_sdp.sdp_header.HB0 = 0;
+	vsc_sdp.sdp_header.HB1 = 0x7;
+
+	/* VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
+	 * Colorimetry Format indication. A DP Source device is allowed
+	 * to indicate the pixel encoding/colorimetry format to the DP Sink
+	 * device with VSC SDP only when the DP Sink device supports it
+	 * (i.e., VSC_SDP_EXTENSION_FOR_COLORIMETRY_SUPPORTED bit in the register
+	 * DPRX_FEATURE_ENUMERATION_LIST (DPCD Address 02210h, bit 3) is set to 1)
+	 */
+	vsc_sdp.sdp_header.HB2 = 0x5;
+
+	/* VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/
+	 * Colorimetry Format indication (HB2 = 05h).
+	 */
+	vsc_sdp.sdp_header.HB3 = 0x13;
+	/* YCbCr 420 = 3h DB16[7:4] ITU-R BT.601 = 0h, ITU-R BT.709 = 1h
+	 * DB16[3:0] DP 1.4a spec, Table 2-120
+	 */
+
+	/* Commit id (25edf91501b8 "drm/i915: prepare csc unit for YCBCR420 output")
+	 * uses the BT.709 color space to perform RGB->YCBCR conversion.
+	 */
+	vsc_sdp.DB16 = 0x3 << 4; /* 0x3 << 4 , YCbCr 420*/
+	vsc_sdp.DB16 |= 0x1; /* 0x1, ITU-R BT.709 */
+
+	/* For pixel encoding formats YCbCr444, YCbCr422, YCbCr420, and Y Only,
+	 * the following Component Bit Depth values are defined:
+	 * 001b = 8bpc.
+	 * 010b = 10bpc.
+	 * 011b = 12bpc.
+	 * 100b = 16bpc.
+	 */
+	vsc_sdp.DB17 = 0x1;
+
+	/*
+	 * Content Type (Bits 2:0)
+	 * 000b = Not defined.
+	 * 001b = Graphics.
+	 * 010b = Photo.
+	 * 011b = Video.
+	 * 100b = Game
+	 * All other values are RESERVED.
+	 * Note: See CTA-861-G for the definition and expected
+	 * processing by a stream sink for the above contect types.
+	 */
+	vsc_sdp.DB18 = 0;
+
+	intel_dig_port->write_infoframe(&intel_dig_port->base,
+			crtc_state, DP_SDP_VSC, &vsc_sdp, sizeof(vsc_sdp));
+}
+
+void intel_dp_ycbcr_420_enable(struct intel_dp *intel_dp,
+			       const struct intel_crtc_state *crtc_state)
+{
+	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420)
+		return;
+
+	intel_pixel_encoding_setup_vsc(intel_dp, crtc_state);
+}
+
 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
 {
 	int status = 0;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 247893ed1543..5d1845526cf8 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1576,6 +1576,8 @@ void intel_dp_get_m_n(struct intel_crtc *crtc,
 		      struct intel_crtc_state *pipe_config);
 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
 		      enum link_m_n_set m_n);
+void intel_dp_ycbcr_420_enable(struct intel_dp *intel_dp,
+			       const struct intel_crtc_state *crtc_state);
 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
 			struct dpll *best_clock);
-- 
2.21.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v6 4/6] drm/i915/dp: Add a support of YCBCR 4:2:0 to DP MSA

[Gwan-gyeong Mun]

When YCBCR 4:2:0 outputs is used for DP, we should program YCBCR 4:2:0 to
MSA and VSC SDP.

As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication of Color
Encoding Format and Content Color Gamut] while sending YCBCR 420 signals
we should program MSA MISC1 fields which indicate VSC SDP for the Pixel
Encoding/Colorimetry Format.

v2: Block comment style fix.
v6:
  Fix an wrong setting of MSA MISC1 fields for Pixel Encoding/Colorimetry
  Format indication. As per DP 1.4a spec Table 2-96 [MSA MISC1 and MISC0
  Fields for Pixel Encoding/Colorimetry Format Indication]
  When MISC1, bit 6, is Set to 1, a Source device uses a VSC SDP to
  indicate the Pixel Encoding/Colorimetry Format. On the wrong version
  it set a bit 5 of MISC1, now it set a bit 6 of MISC1.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  | 1 +
 drivers/gpu/drm/i915/intel_ddi.c | 8 ++++++++
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e97c47fca645..2ad98e62034f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9524,6 +9524,7 @@ enum skl_power_gate {
 #define  TRANS_MSA_12_BPC		(3 << 5)
 #define  TRANS_MSA_16_BPC		(4 << 5)
 #define  TRANS_MSA_CEA_RANGE		(1 << 3)
+#define  TRANS_MSA_USE_VSC_SDP		(1 << 14)
 
 /* LCPLL Control */
 #define LCPLL_CTL			_MMIO(0x130040)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 2f1688ea5a2c..4441c5ba71fb 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1717,6 +1717,14 @@ void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
 	 */
 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
 		temp |= TRANS_MSA_SAMPLING_444 | TRANS_MSA_CLRSP_YCBCR;
+	/*
+	 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
+	 * of Color Encoding Format and Content Color Gamut] while sending
+	 * YCBCR 420 signals we should program MSA MISC1 fields which
+	 * indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
+	 */
+	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+		temp |= TRANS_MSA_USE_VSC_SDP;
 	I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
 }
 
-- 
2.21.0

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH v6 5/6] drm/i915/dp: Change a link bandwidth computation for DP

[Gwan-gyeong Mun]

Data M/N calculations were assumed a bpp as RGB format. But when we are
using YCbCr 4:2:0 output format on DP, we should change bpp calculations
as YCbCr 4:2:0 format. The pipe_bpp value was assumed RGB format,
therefore, it was multiplied with 3. But YCbCr 4:2:0 requires a multiplier
value to 1.5.
Therefore we need to divide pipe_bpp to 2 while DP output uses YCbCr4:2:0
format.
 - RGB format bpp = bpc x 3
 - YCbCr 4:2:0 format bpp = bpc x 1.5

But Link M/N values are calculated and applied based on the Full Clock for
YCbCr 4:2:0. And DP YCbCr 4:2:0 does not need to pixel clock double for
a dotclock caluation. Only for HDMI YCbCr 4:2:0 needs to pixel clock double
for a dot clock calculation.

And it adds missed bpc values for a programming of VSC Header.
It only affects dp and edp port which use YCbCr 4:2:0 output format.
And for now, it does not consider a use case of DSC + YCbCr 4:2:0.

v2:
  Addressed review comments from Ville.
  Remove a changing of pipe_bpp on intel_ddi_set_pipe_settings().
  Because the pipe is running at the full bpp, keep pipe_bpp as RGB
  even though YCbCr 4:2:0 output format is used.
  Add a link bandwidth computation for YCbCr4:2:0 output format.

v3:
  Addressed reivew comments from Ville.
  In order to make codes simple, it adds and uses intel_dp_output_bpp()
  function.

v6:
  Link M/N values are calculated and applied based on the Full Clock for
  YCbCr420. The Bit per Pixel needs to be adjusted for YUV420 mode as it
  requires only half of the RGB case.
    - Link M/N values are calculated and applied based on the Full Clock
    - Data M/N values needs to be calculated considering the data is half
      due to subsampling
  Remove a doubling of pixel clock on a dot clock calculator for
  DP YCbCr 4:2:0.
  Rebase and remove a duplicate setting of vsc_sdp.DB17.
  Add a setting of dynamic range bit to  vsc_sdp.DB17.
  Change Content Type bit to "Graphics" from "Not defined".
  Change a dividing of pipe_bpp to muliplying to constant values on a
  switch-case statement.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c |  3 ++-
 drivers/gpu/drm/i915/intel_dp.c  | 42 +++++++++++++++++++++++++++++---
 2 files changed, 41 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 4441c5ba71fb..e22a0898b957 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1457,7 +1457,8 @@ static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
 	else
 		dotclock = pipe_config->port_clock;
 
-	if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+	if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
+	    !intel_crtc_has_dp_encoder(pipe_config))
 		dotclock *= 2;
 
 	if (pipe_config->pixel_multiplier)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 74aad8830a80..c75e2bbe612a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1842,6 +1842,19 @@ intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
 	}
 }
 
+static int intel_dp_output_bpp(const struct intel_crtc_state *crtc_state, int bpp)
+{
+	/*
+	 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
+	 * format of the number of bytes per pixel will be half the number
+	 * of bytes of RGB pixel.
+	 */
+	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+		bpp /= 2;
+
+	return bpp;
+}
+
 /* Optimize link config in order: max bpp, min clock, min lanes */
 static int
 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
@@ -2212,7 +2225,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	if (pipe_config->dsc_params.compression_enable)
 		output_bpp = pipe_config->dsc_params.compressed_bpp;
 	else
-		output_bpp = pipe_config->pipe_bpp;
+		output_bpp = intel_dp_output_bpp(pipe_config, pipe_config->pipe_bpp);
 
 	intel_link_compute_m_n(output_bpp,
 			       pipe_config->lane_count,
@@ -4439,7 +4452,30 @@ intel_pixel_encoding_setup_vsc(struct intel_dp *intel_dp,
 	 * 011b = 12bpc.
 	 * 100b = 16bpc.
 	 */
-	vsc_sdp.DB17 = 0x1;
+	switch (crtc_state->pipe_bpp) {
+	case 24: /* 8bpc */
+		vsc_sdp.DB17 = 0x1;
+		break;
+	case 30: /* 10bpc */
+		vsc_sdp.DB17 = 0x2;
+		break;
+	case 36: /* 12bpc */
+		vsc_sdp.DB17 = 0x3;
+		break;
+	case 48: /* 16bpc */
+		vsc_sdp.DB17 = 0x4;
+		break;
+	default:
+		DRM_DEBUG_KMS("Invalid bpp value '%d'\n", crtc_state->pipe_bpp);
+		break;
+	}
+
+	/*
+	 * Dynamic Range (Bit 7)
+	 * 0 = VESA range, 1 = CTA range.
+	 * all YCbCr are always limited range
+	 */
+	vsc_sdp.DB17 |= 0x80;
 
 	/*
 	 * Content Type (Bits 2:0)
@@ -4452,7 +4488,7 @@ intel_pixel_encoding_setup_vsc(struct intel_dp *intel_dp,
 	 * Note: See CTA-861-G for the definition and expected
 	 * processing by a stream sink for the above contect types.
 	 */
-	vsc_sdp.DB18 = 0;
+	vsc_sdp.DB18 = 0x1;
 
 	intel_dig_port->write_infoframe(&intel_dig_port->base,
 			crtc_state, DP_SDP_VSC, &vsc_sdp, sizeof(vsc_sdp));
-- 
2.21.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v6 6/6] drm/i915/dp: Support DP ports YUV 4:2:0 output to GEN11

[Gwan-gyeong Mun]

Bspec describes that GEN10 only supports capability of YUV 4:2:0 output to
HDMI port and GEN11 supports capability of YUV 4:2:0 output to both DP and
HDMI ports.

v2: Minor style fix.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c75e2bbe612a..9b3724cd37cd 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -7378,6 +7378,9 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 		connector->interlace_allowed = true;
 	connector->doublescan_allowed = 0;
 
+	if (INTEL_GEN(dev_priv) >= 11)
+		connector->ycbcr_420_allowed = true;
+
 	intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
 
 	intel_dp_aux_init(intel_dp);
-- 
2.21.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.BAT: success for drm/i915/dp: Support for DP YCbCr4:2:0 outputs

[Patchwork]

== Series Details ==

Series: drm/i915/dp: Support for DP YCbCr4:2:0 outputs
URL   : https://patchwork.freedesktop.org/series/60404/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6063 -> Patchwork_12983
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/

Known issues
------------

  Here are the changes found in Patchwork_12983 that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@gem_exec_basic@readonly-render:
    - {fi-icl-y}:         [INCOMPLETE][1] ([fdo#107713]) -> [PASS][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/fi-icl-y/igt@gem_exec_basic@readonly-render.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/fi-icl-y/igt@gem_exec_basic@readonly-render.html

  
#### Warnings ####

  * igt@i915_selftest@live_hangcheck:
    - fi-apl-guc:         [INCOMPLETE][3] ([fdo#103927]) -> [INCOMPLETE][4] ([fdo#103927] / [fdo#110624])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/fi-apl-guc/igt@i915_selftest@live_hangcheck.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/fi-apl-guc/igt@i915_selftest@live_hangcheck.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#110624]: https://bugs.freedesktop.org/show_bug.cgi?id=110624


Participating hosts (53 -> 45)
------------------------------

  Missing    (8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_6063 -> Patchwork_12983

  CI_DRM_6063: 44ae4003d35743cbc7883825c5fe777d136b5247 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4972: f052e49a43cc9704ea5f240df15dd9d3dfed68ab @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12983: a902ce4da59ae0f2543950e07ed2678808966a5c @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

a902ce4da59a drm/i915/dp: Support DP ports YUV 4:2:0 output to GEN11
1472073c7d9d drm/i915/dp: Change a link bandwidth computation for DP
8bf6ac92cc19 drm/i915/dp: Add a support of YCBCR 4:2:0 to DP MSA
c0865d08f8ad drm/i915/dp: Program VSC Header and DB for Pixel Encoding/Colorimetry Format
3189eb1879bc drm: Add a VSC structure for handling Pixel Encoding/Colorimetry Formats
e1fd5f42e42e drm/i915/dp: Add a config function for YCBCR420 outputs

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.IGT: success for drm/i915/dp: Support for DP YCbCr4:2:0 outputs

[Patchwork]

== Series Details ==

Series: drm/i915/dp: Support for DP YCbCr4:2:0 outputs
URL   : https://patchwork.freedesktop.org/series/60404/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6063_full -> Patchwork_12983_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_12983_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_workarounds@suspend-resume-context:
    - shard-apl:          [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +6 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-apl6/igt@gem_workarounds@suspend-resume-context.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/shard-apl2/igt@gem_workarounds@suspend-resume-context.html

  * igt@kms_cursor_crc@cursor-128x128-suspend:
    - shard-skl:          [PASS][3] -> [INCOMPLETE][4] ([fdo#104108])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-skl6/igt@kms_cursor_crc@cursor-128x128-suspend.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/shard-skl8/igt@kms_cursor_crc@cursor-128x128-suspend.html

  * igt@kms_draw_crc@draw-method-xrgb8888-render-xtiled:
    - shard-skl:          [PASS][5] -> [FAIL][6] ([fdo#103184] / [fdo#103232])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-skl4/igt@kms_draw_crc@draw-method-xrgb8888-render-xtiled.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/shard-skl1/igt@kms_draw_crc@draw-method-xrgb8888-render-xtiled.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-skl:          [PASS][7] -> [INCOMPLETE][8] ([fdo#104108] / [fdo#107773])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-skl9/igt@kms_fbcon_fbt@fbc-suspend.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/shard-skl10/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_flip@2x-modeset-vs-vblank-race-interruptible:
    - shard-glk:          [PASS][9] -> [FAIL][10] ([fdo#103060])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-glk1/igt@kms_flip@2x-modeset-vs-vblank-race-interruptible.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/shard-glk4/igt@kms_flip@2x-modeset-vs-vblank-race-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-skl:          [PASS][11] -> [FAIL][12] ([fdo#105363])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/shard-skl10/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-move:
    - shard-hsw:          [PASS][13] -> [SKIP][14] ([fdo#109271]) +1 similar issue
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-hsw8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-move.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/shard-hsw6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbc-tilingchange:
    - shard-iclb:         [PASS][15] -> [FAIL][16] ([fdo#103167]) +3 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-tilingchange.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-tilingchange.html

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          [PASS][17] -> [FAIL][18] ([fdo#108145] / [fdo#110403])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html

  * igt@kms_plane_lowres@pipe-a-tiling-x:
    - shard-iclb:         [PASS][19] -> [FAIL][20] ([fdo#103166])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-iclb1/igt@kms_plane_lowres@pipe-a-tiling-x.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/shard-iclb7/igt@kms_plane_lowres@pipe-a-tiling-x.html

  * igt@kms_plane_scaling@pipe-a-scaler-with-pixel-format:
    - shard-glk:          [PASS][21] -> [SKIP][22] ([fdo#109271] / [fdo#109278]) +1 similar issue
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-glk9/igt@kms_plane_scaling@pipe-a-scaler-with-pixel-format.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/shard-glk5/igt@kms_plane_scaling@pipe-a-scaler-with-pixel-format.html

  * igt@kms_psr@psr2_sprite_blt:
    - shard-iclb:         [PASS][23] -> [SKIP][24] ([fdo#109441])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/shard-iclb6/igt@kms_psr@psr2_sprite_blt.html

  * igt@kms_setmode@basic:
    - shard-apl:          [PASS][25] -> [FAIL][26] ([fdo#99912])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-apl6/igt@kms_setmode@basic.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/shard-apl2/igt@kms_setmode@basic.html

  
#### Possible fixes ####

  * igt@gem_ctx_isolation@vecs0-s3:
    - shard-kbl:          [DMESG-WARN][27] ([fdo#108566]) -> [PASS][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-kbl1/igt@gem_ctx_isolation@vecs0-s3.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/shard-kbl5/igt@gem_ctx_isolation@vecs0-s3.html

  * igt@gem_eio@reset-stress:
    - shard-skl:          [FAIL][29] ([fdo#105957]) -> [PASS][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-skl2/igt@gem_eio@reset-stress.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/shard-skl1/igt@gem_eio@reset-stress.html

  * igt@gem_softpin@noreloc-s3:
    - shard-skl:          [INCOMPLETE][31] ([fdo#104108] / [fdo#107773]) -> [PASS][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-skl7/igt@gem_softpin@noreloc-s3.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/shard-skl6/igt@gem_softpin@noreloc-s3.html

  * igt@i915_pm_rpm@i2c:
    - shard-iclb:         [FAIL][33] ([fdo#104097]) -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-iclb1/igt@i915_pm_rpm@i2c.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/shard-iclb7/igt@i915_pm_rpm@i2c.html

  * igt@i915_pm_rpm@sysfs-read:
    - shard-skl:          [INCOMPLETE][35] ([fdo#107807]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-skl1/igt@i915_pm_rpm@sysfs-read.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/shard-skl4/igt@i915_pm_rpm@sysfs-read.html

  * igt@i915_suspend@sysfs-reader:
    - shard-apl:          [DMESG-WARN][37] ([fdo#108566]) -> [PASS][38] +6 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-apl4/igt@i915_suspend@sysfs-reader.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/shard-apl8/igt@i915_suspend@sysfs-reader.html

  * igt@kms_cursor_crc@cursor-64x21-onscreen:
    - shard-apl:          [INCOMPLETE][39] ([fdo#103927]) -> [PASS][40] +2 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-apl4/igt@kms_cursor_crc@cursor-64x21-onscreen.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/shard-apl2/igt@kms_cursor_crc@cursor-64x21-onscreen.html

  * igt@kms_cursor_edge_walk@pipe-b-128x128-right-edge:
    - shard-snb:          [SKIP][41] ([fdo#109271] / [fdo#109278]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-snb2/igt@kms_cursor_edge_walk@pipe-b-128x128-right-edge.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/shard-snb1/igt@kms_cursor_edge_walk@pipe-b-128x128-right-edge.html

  * igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
    - shard-glk:          [FAIL][43] ([fdo#107409]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-glk9/igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/shard-glk5/igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
    - shard-glk:          [FAIL][45] ([fdo#106509] / [fdo#107409]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-glk2/igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/shard-glk2/igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move:
    - shard-iclb:         [FAIL][47] ([fdo#103167]) -> [PASS][48] +6 similar issues
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-rte:
    - shard-iclb:         [FAIL][49] ([fdo#103167] / [fdo#110378]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-rte.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-rte.html

  * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
    - shard-glk:          [SKIP][51] ([fdo#109271]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-glk1/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/shard-glk9/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html

  * igt@kms_plane_scaling@pipe-a-scaler-with-clipping-clamping:
    - shard-glk:          [SKIP][53] ([fdo#109271] / [fdo#109278]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-glk7/igt@kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/shard-glk9/igt@kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html

  * igt@kms_psr@psr2_cursor_plane_onoff:
    - shard-iclb:         [SKIP][55] ([fdo#109441]) -> [PASS][56] +3 similar issues
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-iclb7/igt@kms_psr@psr2_cursor_plane_onoff.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html

  * igt@kms_rotation_crc@multiplane-rotation-cropping-top:
    - shard-kbl:          [FAIL][57] ([fdo#109016]) -> [PASS][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-kbl7/igt@kms_rotation_crc@multiplane-rotation-cropping-top.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/shard-kbl2/igt@kms_rotation_crc@multiplane-rotation-cropping-top.html

  * igt@kms_setmode@basic:
    - shard-kbl:          [FAIL][59] ([fdo#99912]) -> [PASS][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-kbl2/igt@kms_setmode@basic.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/shard-kbl1/igt@kms_setmode@basic.html

  
#### Warnings ####

  * igt@kms_flip@flip-vs-suspend:
    - shard-apl:          [FAIL][61] ([fdo#103375]) -> [DMESG-WARN][62] ([fdo#108566])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-apl3/igt@kms_flip@flip-vs-suspend.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/shard-apl5/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt:
    - shard-skl:          [FAIL][63] ([fdo#108040]) -> [FAIL][64] ([fdo#103167])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6063/shard-skl4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/shard-skl1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt.html

  
  [fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#104097]: https://bugs.freedesktop.org/show_bug.cgi?id=104097
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#105957]: https://bugs.freedesktop.org/show_bug.cgi?id=105957
  [fdo#106509]: https://bugs.freedesktop.org/show_bug.cgi?id=106509
  [fdo#107409]: https://bugs.freedesktop.org/show_bug.cgi?id=107409
  [fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
  [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
  [fdo#108040]: https://bugs.freedesktop.org/show_bug.cgi?id=108040
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#109016]: https://bugs.freedesktop.org/show_bug.cgi?id=109016
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#110378]: https://bugs.freedesktop.org/show_bug.cgi?id=110378
  [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_6063 -> Patchwork_12983

  CI_DRM_6063: 44ae4003d35743cbc7883825c5fe777d136b5247 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4972: f052e49a43cc9704ea5f240df15dd9d3dfed68ab @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12983: a902ce4da59ae0f2543950e07ed2678808966a5c @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12983/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v6 2/6] drm: Add a VSC structure for handling Pixel Encoding/Colorimetry Formats

[Ville Syrjälä]

On Wed, May 08, 2019 at 11:17:53AM +0300, Gwan-gyeong Mun wrote:
> SDP VSC Header and Data Block follow DP 1.4a spec, section 2.2.5.7.5,
> chapter "VSC SDP Payload for Pixel Encoding/Colorimetry Format".
> 
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> ---
>  include/drm/drm_dp_helper.h | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 97ce790a5b5a..3793bea7b7fe 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -1096,6 +1096,23 @@ struct edp_vsc_psr {
>  	u8 DB8_31[24]; /* Reserved */
>  } __packed;
>  
> +struct dp_vsc_sdp {
> +	struct dp_sdp_header sdp_header;
> +	u8 DB0; /* Stereo Interface */
> +	u8 DB1; /* 0 - PSR State; 1 - Update RFB; 2 - CRC Valid */
> +	u8 DB2; /* CRC value bits 7:0 of the R or Cr component */
> +	u8 DB3; /* CRC value bits 15:8 of the R or Cr component */
> +	u8 DB4; /* CRC value bits 7:0 of the G or Y component */
> +	u8 DB5; /* CRC value bits 15:8 of the G or Y component */
> +	u8 DB6; /* CRC value bits 7:0 of the B or Cb component */
> +	u8 DB7; /* CRC value bits 15:8 of the B or Cb component */
> +	u8 DB8_15[8];  /* Reserved */
> +	u8 DB16; /* Pixel Encoding and Colorimetry Formats */
> +	u8 DB17; /* Dynamic Range and Component Bit Depth */
> +	u8 DB18; /* Content Type */
> +	u8 DB19_31[13]; /* Reserved */
> +} __packed;

Isn't this the same thing we have for edp already? Just rename the edp
struct and add the missing stuff?

> +
>  #define EDP_VSC_PSR_STATE_ACTIVE	(1<<0)
>  #define EDP_VSC_PSR_UPDATE_RFB		(1<<1)
>  #define EDP_VSC_PSR_CRC_VALUES_VALID	(1<<2)
> -- 
> 2.21.0

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v6 3/6] drm/i915/dp: Program VSC Header and DB for Pixel Encoding/Colorimetry Format

[Ville Syrjälä]

On Wed, May 08, 2019 at 11:17:54AM +0300, Gwan-gyeong Mun wrote:
> Function intel_pixel_encoding_setup_vsc handles vsc header and data block
> setup for pixel encoding / colorimetry format.
> 
> Setup VSC header and data block in function intel_pixel_encoding_setup_vsc
> for pixel encoding / colorimetry format as per dp 1.4a spec,
> section 2.2.5.7.1, table 2-119: VSC SDP Header Bytes, section 2.2.5.7.5,
> table 2-120:VSC SDP Payload for DB16 through DB18.
> 
> v2:
>   Minor style fix. [Maarten]
>   Refer to commit ids instead of patchwork. [Maarten]
> 
> v6: Rebase
> 
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c |  1 +
>  drivers/gpu/drm/i915/intel_dp.c  | 73 ++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_drv.h |  2 +
>  3 files changed, 76 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index cd5277d98b03..2f1688ea5a2c 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -3391,6 +3391,7 @@ static void intel_enable_ddi_dp(struct intel_encoder *encoder,
>  
>  	intel_edp_backlight_on(crtc_state, conn_state);
>  	intel_psr_enable(intel_dp, crtc_state);
> +	intel_dp_ycbcr_420_enable(intel_dp, crtc_state);

I wonder if this is a bit too late. But we do it for PSR here, so I
guess we should think about this for both cases. We should actually
add full readout + state checker for the VSC SDP for both cases as
well. But that can be done later.

>  	intel_edp_drrs_enable(intel_dp, crtc_state);
>  
>  	if (crtc_state->has_audio)
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 06a3417a88d1..74aad8830a80 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4394,6 +4394,79 @@ u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
>  	return 0;
>  }
>  
> +static void
> +intel_pixel_encoding_setup_vsc(struct intel_dp *intel_dp,
> +			       const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> +	struct dp_vsc_sdp vsc_sdp;
> +
> +	if (!intel_dp->attached_connector->base.ycbcr_420_allowed)
> +		return;
> +
> +	/* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 */
> +	memset(&vsc_sdp, 0, sizeof(vsc_sdp));

Can be replaced with '= {}' in the declaration.

> +	vsc_sdp.sdp_header.HB0 = 0;
> +	vsc_sdp.sdp_header.HB1 = 0x7;
> +
> +	/* VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> +	 * Colorimetry Format indication. A DP Source device is allowed
> +	 * to indicate the pixel encoding/colorimetry format to the DP Sink
> +	 * device with VSC SDP only when the DP Sink device supports it
> +	 * (i.e., VSC_SDP_EXTENSION_FOR_COLORIMETRY_SUPPORTED bit in the register
> +	 * DPRX_FEATURE_ENUMERATION_LIST (DPCD Address 02210h, bit 3) is set to 1)
> +	 */

Are we checking that bit somewhere? I suppose the sink might a bit nuts
if it declares 420_only modes without that set, but maybe it should be
checked anyway.

Also non-standard comment format all over. Should be
/*
 * blah
 */

> +	vsc_sdp.sdp_header.HB2 = 0x5;
> +
> +	/* VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/
> +	 * Colorimetry Format indication (HB2 = 05h).
> +	 */
> +	vsc_sdp.sdp_header.HB3 = 0x13;
> +	/* YCbCr 420 = 3h DB16[7:4] ITU-R BT.601 = 0h, ITU-R BT.709 = 1h
> +	 * DB16[3:0] DP 1.4a spec, Table 2-120
> +	 */
> +
> +	/* Commit id (25edf91501b8 "drm/i915: prepare csc unit for YCBCR420 output")
> +	 * uses the BT.709 color space to perform RGB->YCBCR conversion.
> +	 */

I don't think referring to specific commit here is particularly helpful.
The situation will change anyway at some point.

> +	vsc_sdp.DB16 = 0x3 << 4; /* 0x3 << 4 , YCbCr 420*/
> +	vsc_sdp.DB16 |= 0x1; /* 0x1, ITU-R BT.709 */
> +
> +	/* For pixel encoding formats YCbCr444, YCbCr422, YCbCr420, and Y Only,
> +	 * the following Component Bit Depth values are defined:
> +	 * 001b = 8bpc.
> +	 * 010b = 10bpc.
> +	 * 011b = 12bpc.
> +	 * 100b = 16bpc.
> +	 */
> +	vsc_sdp.DB17 = 0x1;

Don't we need to base this on pipe_bpp? 

And I'm thinking we want the CEA bit set here as well.

> +
> +	/*
> +	 * Content Type (Bits 2:0)
> +	 * 000b = Not defined.
> +	 * 001b = Graphics.
> +	 * 010b = Photo.
> +	 * 011b = Video.
> +	 * 100b = Game
> +	 * All other values are RESERVED.
> +	 * Note: See CTA-861-G for the definition and expected
> +	 * processing by a stream sink for the above contect types.
> +	 */
> +	vsc_sdp.DB18 = 0;

Hmm. I guess we could add the content type prop for DP too.
But that's something for the future.

All the magic numbers should be defined somewhere in the core dp header.
But that could be done as a followup. The PSR code probably needs
changing too in that case.

> +
> +	intel_dig_port->write_infoframe(&intel_dig_port->base,
> +			crtc_state, DP_SDP_VSC, &vsc_sdp, sizeof(vsc_sdp));
> +}
> +
> +void intel_dp_ycbcr_420_enable(struct intel_dp *intel_dp,
> +			       const struct intel_crtc_state *crtc_state)
> +{
> +	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420)
> +		return;
> +
> +	intel_pixel_encoding_setup_vsc(intel_dp, crtc_state);
> +}
> +
>  static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
>  {
>  	int status = 0;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 247893ed1543..5d1845526cf8 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1576,6 +1576,8 @@ void intel_dp_get_m_n(struct intel_crtc *crtc,
>  		      struct intel_crtc_state *pipe_config);
>  void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
>  		      enum link_m_n_set m_n);
> +void intel_dp_ycbcr_420_enable(struct intel_dp *intel_dp,
> +			       const struct intel_crtc_state *crtc_state);
>  int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
>  bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
>  			struct dpll *best_clock);
> -- 
> 2.21.0

-- 
Ville Syrjälä
Intel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [PATCH v6 5/6] drm/i915/dp: Change a link bandwidth computation for DP

[Ville Syrjälä]

On Wed, May 08, 2019 at 11:17:56AM +0300, Gwan-gyeong Mun wrote:
> Data M/N calculations were assumed a bpp as RGB format. But when we are
> using YCbCr 4:2:0 output format on DP, we should change bpp calculations
> as YCbCr 4:2:0 format. The pipe_bpp value was assumed RGB format,
> therefore, it was multiplied with 3. But YCbCr 4:2:0 requires a multiplier
> value to 1.5.
> Therefore we need to divide pipe_bpp to 2 while DP output uses YCbCr4:2:0
> format.
>  - RGB format bpp = bpc x 3
>  - YCbCr 4:2:0 format bpp = bpc x 1.5
> 
> But Link M/N values are calculated and applied based on the Full Clock for
> YCbCr 4:2:0. And DP YCbCr 4:2:0 does not need to pixel clock double for
> a dotclock caluation. Only for HDMI YCbCr 4:2:0 needs to pixel clock double
> for a dot clock calculation.
> 
> And it adds missed bpc values for a programming of VSC Header.
> It only affects dp and edp port which use YCbCr 4:2:0 output format.
> And for now, it does not consider a use case of DSC + YCbCr 4:2:0.
> 
> v2:
>   Addressed review comments from Ville.
>   Remove a changing of pipe_bpp on intel_ddi_set_pipe_settings().
>   Because the pipe is running at the full bpp, keep pipe_bpp as RGB
>   even though YCbCr 4:2:0 output format is used.
>   Add a link bandwidth computation for YCbCr4:2:0 output format.
> 
> v3:
>   Addressed reivew comments from Ville.
>   In order to make codes simple, it adds and uses intel_dp_output_bpp()
>   function.
> 
> v6:
>   Link M/N values are calculated and applied based on the Full Clock for
>   YCbCr420. The Bit per Pixel needs to be adjusted for YUV420 mode as it
>   requires only half of the RGB case.
>     - Link M/N values are calculated and applied based on the Full Clock
>     - Data M/N values needs to be calculated considering the data is half
>       due to subsampling
>   Remove a doubling of pixel clock on a dot clock calculator for
>   DP YCbCr 4:2:0.
>   Rebase and remove a duplicate setting of vsc_sdp.DB17.
>   Add a setting of dynamic range bit to  vsc_sdp.DB17.
>   Change Content Type bit to "Graphics" from "Not defined".
>   Change a dividing of pipe_bpp to muliplying to constant values on a
>   switch-case statement.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c |  3 ++-
>  drivers/gpu/drm/i915/intel_dp.c  | 42 +++++++++++++++++++++++++++++---
>  2 files changed, 41 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 4441c5ba71fb..e22a0898b957 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1457,7 +1457,8 @@ static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
>  	else
>  		dotclock = pipe_config->port_clock;
>  
> -	if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
> +	if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
> +	    !intel_crtc_has_dp_encoder(pipe_config))
>  		dotclock *= 2;
>  
>  	if (pipe_config->pixel_multiplier)
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 74aad8830a80..c75e2bbe612a 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1842,6 +1842,19 @@ intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
>  	}
>  }
>  
> +static int intel_dp_output_bpp(const struct intel_crtc_state *crtc_state, int bpp)
> +{
> +	/*
> +	 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
> +	 * format of the number of bytes per pixel will be half the number
> +	 * of bytes of RGB pixel.
> +	 */
> +	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
> +		bpp /= 2;
> +
> +	return bpp;
> +}
> +
>  /* Optimize link config in order: max bpp, min clock, min lanes */
>  static int
>  intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
> @@ -2212,7 +2225,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>  	if (pipe_config->dsc_params.compression_enable)
>  		output_bpp = pipe_config->dsc_params.compressed_bpp;
>  	else
> -		output_bpp = pipe_config->pipe_bpp;
> +		output_bpp = intel_dp_output_bpp(pipe_config, pipe_config->pipe_bpp);
>  
>  	intel_link_compute_m_n(output_bpp,
>  			       pipe_config->lane_count,
> @@ -4439,7 +4452,30 @@ intel_pixel_encoding_setup_vsc(struct intel_dp *intel_dp,
>  	 * 011b = 12bpc.
>  	 * 100b = 16bpc.
>  	 */
> -	vsc_sdp.DB17 = 0x1;
> +	switch (crtc_state->pipe_bpp) {
> +	case 24: /* 8bpc */
> +		vsc_sdp.DB17 = 0x1;
> +		break;
> +	case 30: /* 10bpc */
> +		vsc_sdp.DB17 = 0x2;
> +		break;
> +	case 36: /* 12bpc */
> +		vsc_sdp.DB17 = 0x3;
> +		break;
> +	case 48: /* 16bpc */
> +		vsc_sdp.DB17 = 0x4;
> +		break;
> +	default:
> +		DRM_DEBUG_KMS("Invalid bpp value '%d'\n", crtc_state->pipe_bpp);
> +		break;
> +	}
> +
> +	/*
> +	 * Dynamic Range (Bit 7)
> +	 * 0 = VESA range, 1 = CTA range.
> +	 * all YCbCr are always limited range
> +	 */
> +	vsc_sdp.DB17 |= 0x80;

Ah, it was all here already. Never mind then.

>  
>  	/*
>  	 * Content Type (Bits 2:0)
> @@ -4452,7 +4488,7 @@ intel_pixel_encoding_setup_vsc(struct intel_dp *intel_dp,
>  	 * Note: See CTA-861-G for the definition and expected
>  	 * processing by a stream sink for the above contect types.
>  	 */
> -	vsc_sdp.DB18 = 0;
> +	vsc_sdp.DB18 = 0x1;

Why is this here?

>  
>  	intel_dig_port->write_infoframe(&intel_dig_port->base,
>  			crtc_state, DP_SDP_VSC, &vsc_sdp, sizeof(vsc_sdp));
> -- 
> 2.21.0

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v6 2/6] drm: Add a VSC structure for handling Pixel Encoding/Colorimetry Formats

[Mun, Gwan-gyeong]

On Wed, 2019-05-08 at 20:32 +0300, Ville Syrjälä wrote:
> On Wed, May 08, 2019 at 11:17:53AM +0300, Gwan-gyeong Mun wrote:
> > SDP VSC Header and Data Block follow DP 1.4a spec, section
> > 2.2.5.7.5,
> > chapter "VSC SDP Payload for Pixel Encoding/Colorimetry Format".
> > 
> > Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > ---
> >  include/drm/drm_dp_helper.h | 17 +++++++++++++++++
> >  1 file changed, 17 insertions(+)
> > 
> > diff --git a/include/drm/drm_dp_helper.h
> > b/include/drm/drm_dp_helper.h
> > index 97ce790a5b5a..3793bea7b7fe 100644
> > --- a/include/drm/drm_dp_helper.h
> > +++ b/include/drm/drm_dp_helper.h
> > @@ -1096,6 +1096,23 @@ struct edp_vsc_psr {
> >  	u8 DB8_31[24]; /* Reserved */
> >  } __packed;
> >  
> > +struct dp_vsc_sdp {
> > +	struct dp_sdp_header sdp_header;
> > +	u8 DB0; /* Stereo Interface */
> > +	u8 DB1; /* 0 - PSR State; 1 - Update RFB; 2 - CRC Valid */
> > +	u8 DB2; /* CRC value bits 7:0 of the R or Cr component */
> > +	u8 DB3; /* CRC value bits 15:8 of the R or Cr component */
> > +	u8 DB4; /* CRC value bits 7:0 of the G or Y component */
> > +	u8 DB5; /* CRC value bits 15:8 of the G or Y component */
> > +	u8 DB6; /* CRC value bits 7:0 of the B or Cb component */
> > +	u8 DB7; /* CRC value bits 15:8 of the B or Cb component */
> > +	u8 DB8_15[8];  /* Reserved */
> > +	u8 DB16; /* Pixel Encoding and Colorimetry Formats */
> > +	u8 DB17; /* Dynamic Range and Component Bit Depth */
> > +	u8 DB18; /* Content Type */
> > +	u8 DB19_31[13]; /* Reserved */
> > +} __packed;
> 
> Isn't this the same thing we have for edp already? Just rename the
> edp
> struct and add the missing stuff?
> 
Okay, I'll rename struct edp_vsc_psr to general name of dp_sdp and will
add missing stuff.
> > +
> >  #define EDP_VSC_PSR_STATE_ACTIVE	(1<<0)
> >  #define EDP_VSC_PSR_UPDATE_RFB		(1<<1)
> >  #define EDP_VSC_PSR_CRC_VALUES_VALID	(1<<2)
> > -- 
> > 2.21.0
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [PATCH v6 3/6] drm/i915/dp: Program VSC Header and DB for Pixel Encoding/Colorimetry Format

[Mun, Gwan-gyeong]

On Wed, 2019-05-08 at 20:56 +0300, Ville Syrjälä wrote:
> On Wed, May 08, 2019 at 11:17:54AM +0300, Gwan-gyeong Mun wrote:
> > Function intel_pixel_encoding_setup_vsc handles vsc header and data
> > block
> > setup for pixel encoding / colorimetry format.
> > 
> > Setup VSC header and data block in function
> > intel_pixel_encoding_setup_vsc
> > for pixel encoding / colorimetry format as per dp 1.4a spec,
> > section 2.2.5.7.1, table 2-119: VSC SDP Header Bytes, section
> > 2.2.5.7.5,
> > table 2-120:VSC SDP Payload for DB16 through DB18.
> > 
> > v2:
> >   Minor style fix. [Maarten]
> >   Refer to commit ids instead of patchwork. [Maarten]
> > 
> > v6: Rebase
> > 
> > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_ddi.c |  1 +
> >  drivers/gpu/drm/i915/intel_dp.c  | 73
> > ++++++++++++++++++++++++++++++++
> >  drivers/gpu/drm/i915/intel_drv.h |  2 +
> >  3 files changed, 76 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > b/drivers/gpu/drm/i915/intel_ddi.c
> > index cd5277d98b03..2f1688ea5a2c 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -3391,6 +3391,7 @@ static void intel_enable_ddi_dp(struct
> > intel_encoder *encoder,
> >  
> >  	intel_edp_backlight_on(crtc_state, conn_state);
> >  	intel_psr_enable(intel_dp, crtc_state);
> > +	intel_dp_ycbcr_420_enable(intel_dp, crtc_state);
> 
> I wonder if this is a bit too late. But we do it for PSR here, so I
> guess we should think about this for both cases. We should actually
> add full readout + state checker for the VSC SDP for both cases as
> well. But that can be done later.
> 
I'll check it again.
> >  	intel_edp_drrs_enable(intel_dp, crtc_state);
> >  
> >  	if (crtc_state->has_audio)
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 06a3417a88d1..74aad8830a80 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -4394,6 +4394,79 @@ u8 intel_dp_dsc_get_slice_count(struct
> > intel_dp *intel_dp,
> >  	return 0;
> >  }
> >  
> > +static void
> > +intel_pixel_encoding_setup_vsc(struct intel_dp *intel_dp,
> > +			       const struct intel_crtc_state
> > *crtc_state)
> > +{
> > +	struct intel_digital_port *intel_dig_port =
> > dp_to_dig_port(intel_dp);
> > +	struct dp_vsc_sdp vsc_sdp;
> > +
> > +	if (!intel_dp->attached_connector->base.ycbcr_420_allowed)
> > +		return;
> > +
> > +	/* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
> > */
> > +	memset(&vsc_sdp, 0, sizeof(vsc_sdp));
> 
> Can be replaced with '= {}' in the declaration.
> 
Yes, I'll use a structure initializer instead of memset().
> > +	vsc_sdp.sdp_header.HB0 = 0;
> > +	vsc_sdp.sdp_header.HB1 = 0x7;
> > +
> > +	/* VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> > +	 * Colorimetry Format indication. A DP Source device is allowed
> > +	 * to indicate the pixel encoding/colorimetry format to the DP
> > Sink
> > +	 * device with VSC SDP only when the DP Sink device supports it
> > +	 * (i.e., VSC_SDP_EXTENSION_FOR_COLORIMETRY_SUPPORTED bit in
> > the register
> > +	 * DPRX_FEATURE_ENUMERATION_LIST (DPCD Address 02210h, bit 3)
> > is set to 1)
> > +	 */
> 
> Are we checking that bit somewhere? I suppose the sink might a bit
> nuts
> if it declares 420_only modes without that set, but maybe it should
> be
> checked anyway.
> 
> Also non-standard comment format all over. Should be
> /*
>  * blah
>  */
> 
I'll add a checking of VSC_SDP_EXTENSION_FOR_COLORIMETRY_SUPPORTED bit
with intel_dp_get_colorimetry_status() on intel_dp_ycbcr420_config().
And I will fix non-standard comment format.
> > +	vsc_sdp.sdp_header.HB2 = 0x5;
> > +
> > +	/* VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/
> > +	 * Colorimetry Format indication (HB2 = 05h).
> > +	 */
> > +	vsc_sdp.sdp_header.HB3 = 0x13;
> > +	/* YCbCr 420 = 3h DB16[7:4] ITU-R BT.601 = 0h, ITU-R BT.709 =
> > 1h
> > +	 * DB16[3:0] DP 1.4a spec, Table 2-120
> > +	 */
> > +
> > +	/* Commit id (25edf91501b8 "drm/i915: prepare csc unit for
> > YCBCR420 output")
> > +	 * uses the BT.709 color space to perform RGB->YCBCR
> > conversion.
> > +	 */
> 
> I don't think referring to specific commit here is particularly
> helpful.
> The situation will change anyway at some point.
> 
Yes, I'll remove a referring to specific commit.
> > +	vsc_sdp.DB16 = 0x3 << 4; /* 0x3 << 4 , YCbCr 420*/
> > +	vsc_sdp.DB16 |= 0x1; /* 0x1, ITU-R BT.709 */
> > +
> > +	/* For pixel encoding formats YCbCr444, YCbCr422, YCbCr420, and
> > Y Only,
> > +	 * the following Component Bit Depth values are defined:
> > +	 * 001b = 8bpc.
> > +	 * 010b = 10bpc.
> > +	 * 011b = 12bpc.
> > +	 * 100b = 16bpc.
> > +	 */
> > +	vsc_sdp.DB17 = 0x1;
> 
> Don't we need to base this on pipe_bpp? 
> 
> And I'm thinking we want the CEA bit set here as well.
> 
I'll move a setting of dynamic range bit and a setting of bpc which is
based on pipe_bpp from a "drm/i915/dp: Change a link bandwidth
computation for DP" commit.
> > +
> > +	/*
> > +	 * Content Type (Bits 2:0)
> > +	 * 000b = Not defined.
> > +	 * 001b = Graphics.
> > +	 * 010b = Photo.
> > +	 * 011b = Video.
> > +	 * 100b = Game
> > +	 * All other values are RESERVED.
> > +	 * Note: See CTA-861-G for the definition and expected
> > +	 * processing by a stream sink for the above contect types.
> > +	 */
> > +	vsc_sdp.DB18 = 0;
> 
> Hmm. I guess we could add the content type prop for DP too.
> But that's something for the future.
> 
Yes. Yes. After this step, I would like to handle it.
> All the magic numbers should be defined somewhere in the core dp
> header.
> But that could be done as a followup. The PSR code probably needs
> changing too in that case.
> 
Sure, After this step, I also would like to refactor these magic
numbers.
> > +
> > +	intel_dig_port->write_infoframe(&intel_dig_port->base,
> > +			crtc_state, DP_SDP_VSC, &vsc_sdp,
> > sizeof(vsc_sdp));
> > +}
> > +
> > +void intel_dp_ycbcr_420_enable(struct intel_dp *intel_dp,
> > +			       const struct intel_crtc_state
> > *crtc_state)
> > +{
> > +	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420)
> > +		return;
> > +
> > +	intel_pixel_encoding_setup_vsc(intel_dp, crtc_state);
> > +}
> > +
> >  static u8 intel_dp_autotest_link_training(struct intel_dp
> > *intel_dp)
> >  {
> >  	int status = 0;
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > b/drivers/gpu/drm/i915/intel_drv.h
> > index 247893ed1543..5d1845526cf8 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -1576,6 +1576,8 @@ void intel_dp_get_m_n(struct intel_crtc
> > *crtc,
> >  		      struct intel_crtc_state *pipe_config);
> >  void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
> >  		      enum link_m_n_set m_n);
> > +void intel_dp_ycbcr_420_enable(struct intel_dp *intel_dp,
> > +			       const struct intel_crtc_state
> > *crtc_state);
> >  int intel_dotclock_calculate(int link_freq, const struct
> > intel_link_m_n *m_n);
> >  bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
> >  			struct dpll *best_clock);
> > -- 
> > 2.21.0
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [PATCH v6 5/6] drm/i915/dp: Change a link bandwidth computation for DP

[Mun, Gwan-gyeong]

On Wed, 2019-05-08 at 20:58 +0300, Ville Syrjälä wrote:
> On Wed, May 08, 2019 at 11:17:56AM +0300, Gwan-gyeong Mun wrote:
> > Data M/N calculations were assumed a bpp as RGB format. But when we
> > are
> > using YCbCr 4:2:0 output format on DP, we should change bpp
> > calculations
> > as YCbCr 4:2:0 format. The pipe_bpp value was assumed RGB format,
> > therefore, it was multiplied with 3. But YCbCr 4:2:0 requires a
> > multiplier
> > value to 1.5.
> > Therefore we need to divide pipe_bpp to 2 while DP output uses
> > YCbCr4:2:0
> > format.
> >  - RGB format bpp = bpc x 3
> >  - YCbCr 4:2:0 format bpp = bpc x 1.5
> > 
> > But Link M/N values are calculated and applied based on the Full
> > Clock for
> > YCbCr 4:2:0. And DP YCbCr 4:2:0 does not need to pixel clock double
> > for
> > a dotclock caluation. Only for HDMI YCbCr 4:2:0 needs to pixel
> > clock double
> > for a dot clock calculation.
> > 
> > And it adds missed bpc values for a programming of VSC Header.
> > It only affects dp and edp port which use YCbCr 4:2:0 output
> > format.
> > And for now, it does not consider a use case of DSC + YCbCr 4:2:0.
> > 
> > v2:
> >   Addressed review comments from Ville.
> >   Remove a changing of pipe_bpp on intel_ddi_set_pipe_settings().
> >   Because the pipe is running at the full bpp, keep pipe_bpp as RGB
> >   even though YCbCr 4:2:0 output format is used.
> >   Add a link bandwidth computation for YCbCr4:2:0 output format.
> > 
> > v3:
> >   Addressed reivew comments from Ville.
> >   In order to make codes simple, it adds and uses
> > intel_dp_output_bpp()
> >   function.
> > 
> > v6:
> >   Link M/N values are calculated and applied based on the Full
> > Clock for
> >   YCbCr420. The Bit per Pixel needs to be adjusted for YUV420 mode
> > as it
> >   requires only half of the RGB case.
> >     - Link M/N values are calculated and applied based on the Full
> > Clock
> >     - Data M/N values needs to be calculated considering the data
> > is half
> >       due to subsampling
> >   Remove a doubling of pixel clock on a dot clock calculator for
> >   DP YCbCr 4:2:0.
> >   Rebase and remove a duplicate setting of vsc_sdp.DB17.
> >   Add a setting of dynamic range bit to  vsc_sdp.DB17.
> >   Change Content Type bit to "Graphics" from "Not defined".
> >   Change a dividing of pipe_bpp to muliplying to constant values on
> > a
> >   switch-case statement.
> > 
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_ddi.c |  3 ++-
> >  drivers/gpu/drm/i915/intel_dp.c  | 42
> > +++++++++++++++++++++++++++++---
> >  2 files changed, 41 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > b/drivers/gpu/drm/i915/intel_ddi.c
> > index 4441c5ba71fb..e22a0898b957 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -1457,7 +1457,8 @@ static void ddi_dotclock_get(struct
> > intel_crtc_state *pipe_config)
> >  	else
> >  		dotclock = pipe_config->port_clock;
> >  
> > -	if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
> > +	if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420
> > &&
> > +	    !intel_crtc_has_dp_encoder(pipe_config))
> >  		dotclock *= 2;
> >  
> >  	if (pipe_config->pixel_multiplier)
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 74aad8830a80..c75e2bbe612a 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -1842,6 +1842,19 @@ intel_dp_adjust_compliance_config(struct
> > intel_dp *intel_dp,
> >  	}
> >  }
> >  
> > +static int intel_dp_output_bpp(const struct intel_crtc_state
> > *crtc_state, int bpp)
> > +{
> > +	/*
> > +	 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
> > +	 * format of the number of bytes per pixel will be half the
> > number
> > +	 * of bytes of RGB pixel.
> > +	 */
> > +	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
> > +		bpp /= 2;
> > +
> > +	return bpp;
> > +}
> > +
> >  /* Optimize link config in order: max bpp, min clock, min lanes */
> >  static int
> >  intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
> > @@ -2212,7 +2225,7 @@ intel_dp_compute_config(struct intel_encoder
> > *encoder,
> >  	if (pipe_config->dsc_params.compression_enable)
> >  		output_bpp = pipe_config->dsc_params.compressed_bpp;
> >  	else
> > -		output_bpp = pipe_config->pipe_bpp;
> > +		output_bpp = intel_dp_output_bpp(pipe_config,
> > pipe_config->pipe_bpp);
> >  
> >  	intel_link_compute_m_n(output_bpp,
> >  			       pipe_config->lane_count,
> > @@ -4439,7 +4452,30 @@ intel_pixel_encoding_setup_vsc(struct
> > intel_dp *intel_dp,
> >  	 * 011b = 12bpc.
> >  	 * 100b = 16bpc.
> >  	 */
> > -	vsc_sdp.DB17 = 0x1;
> > +	switch (crtc_state->pipe_bpp) {
> > +	case 24: /* 8bpc */
> > +		vsc_sdp.DB17 = 0x1;
> > +		break;
> > +	case 30: /* 10bpc */
> > +		vsc_sdp.DB17 = 0x2;
> > +		break;
> > +	case 36: /* 12bpc */
> > +		vsc_sdp.DB17 = 0x3;
> > +		break;
> > +	case 48: /* 16bpc */
> > +		vsc_sdp.DB17 = 0x4;
> > +		break;
> > +	default:
> > +		DRM_DEBUG_KMS("Invalid bpp value '%d'\n", crtc_state-
> > >pipe_bpp);
> > +		break;
> > +	}
> > +
> > +	/*
> > +	 * Dynamic Range (Bit 7)
> > +	 * 0 = VESA range, 1 = CTA range.
> > +	 * all YCbCr are always limited range
> > +	 */
> > +	vsc_sdp.DB17 |= 0x80;
> 
> Ah, it was all here already. Never mind then.
> 
In order to program VSC Header and DB for Pixel Encoding/Colorimetry
Format in one commit, I'll move them to a "drm/i915/dp: Program VSC
Header and DB for Pixel Encoding/Colorimetry Format" commit.
> >  
> >  	/*
> >  	 * Content Type (Bits 2:0)
> > @@ -4452,7 +4488,7 @@ intel_pixel_encoding_setup_vsc(struct
> > intel_dp *intel_dp,
> >  	 * Note: See CTA-861-G for the definition and expected
> >  	 * processing by a stream sink for the above contect types.
> >  	 */
> > -	vsc_sdp.DB18 = 0;
> > +	vsc_sdp.DB18 = 0x1;
> 
> Why is this here?
> 
When I tested HDMI YCbCr4:2:0, logs from i915 showed "Content types" to
"Graphics". We don't have a way to set content type by property on
DP.  For now I'll remove it. And after having properties for DP output,
I'll improve it

> >  
> >  	intel_dig_port->write_infoframe(&intel_dig_port->base,
> >  			crtc_state, DP_SDP_VSC, &vsc_sdp,
> > sizeof(vsc_sdp));
> > -- 
> > 2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx