* [U-Boot] [PATCH v3 00/10] spi: Add Atmel QuadSPI driver
@ 2019-05-14 10:25 Tudor.Ambarus at microchip.com
2019-05-14 10:26 ` [U-Boot] [PATCH v3 01/10] dt-bindings: spi: add bindings for Atmel QSPI driver Tudor.Ambarus at microchip.com
` (9 more replies)
0 siblings, 10 replies; 15+ messages in thread
From: Tudor.Ambarus at microchip.com @ 2019-05-14 10:25 UTC (permalink / raw)
To: u-boot
From: Tudor Ambarus <tudor.ambarus@microchip.com>
Backport the driver from linux v5.1-rc5 and adapt it for u-boot.
Tested on sama5d2_xplained Rev B with mx25l25635e spi-nor flash,
and on sama5d27_som1_ek with sst26vf064b spi-nor flash.
v3: fix following config warnings reported by travis:
./tools/genboardscfg.py
WARNING: no status info for 'sama5d2_xplained_qspiflash'
WARNING: no maintainers for 'sama5d2_xplained_qspiflash'
WARNING: no status info for 'sama5d27_som1_ek_qspiflash'
WARNING: no maintainers for 'sama5d27_som1_ek_qspiflash'
v2: update/add configs and update sama5d2_xplained dts
Cyrille Pitchen (2):
ARM: dts: at91: sama5d2_xplained: fix QSPI0 node
ARM: at91: sama5: add common environment for QSPI
Eugen Hristev (1):
configs: sama5d2_xplained: add support QSPI flash boot
Tudor Ambarus (7):
dt-bindings: spi: add bindings for Atmel QSPI driver
spi: Add Atmel QuadSPI driver
configs: sama5d2_xplained: enable qspi controller and flashes
configs: sama5d27_som1_ek: enable qspi controller and flashes
configs: sama5d2_xplained: add qspiflash_defconfig
configs: sama5d27_som1_ek: add qspiflash_defconfig
configs: sama5d27_som1_ek: qspi: use common memory layout
arch/arm/dts/at91-sama5d2_xplained.dts | 36 +-
board/atmel/sama5d27_som1_ek/MAINTAINERS | 1 +
board/atmel/sama5d2_xplained/MAINTAINERS | 1 +
configs/sama5d27_som1_ek_mmc1_defconfig | 2 +
configs/sama5d27_som1_ek_mmc_defconfig | 2 +
configs/sama5d27_som1_ek_qspiflash_defconfig | 101 +++++
configs/sama5d2_xplained_emmc_defconfig | 5 +
configs/sama5d2_xplained_mmc_defconfig | 5 +
configs/sama5d2_xplained_qspiflash_defconfig | 101 +++++
configs/sama5d2_xplained_spiflash_defconfig | 5 +
doc/device-tree-bindings/spi/atmel-quadspi.txt | 37 ++
drivers/spi/Kconfig | 7 +
drivers/spi/Makefile | 1 +
drivers/spi/atmel-quadspi.c | 535 +++++++++++++++++++++++++
include/configs/at91-sama5_common.h | 8 +
include/configs/sama5d27_som1_ek.h | 7 -
include/configs/sama5d2_xplained.h | 11 +
17 files changed, 839 insertions(+), 26 deletions(-)
create mode 100644 configs/sama5d27_som1_ek_qspiflash_defconfig
create mode 100644 configs/sama5d2_xplained_qspiflash_defconfig
create mode 100644 doc/device-tree-bindings/spi/atmel-quadspi.txt
create mode 100644 drivers/spi/atmel-quadspi.c
--
2.9.5
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH v3 01/10] dt-bindings: spi: add bindings for Atmel QSPI driver
2019-05-14 10:25 [U-Boot] [PATCH v3 00/10] spi: Add Atmel QuadSPI driver Tudor.Ambarus at microchip.com
@ 2019-05-14 10:26 ` Tudor.Ambarus at microchip.com
2019-05-14 10:26 ` [U-Boot] [PATCH v3 02/10] spi: Add Atmel QuadSPI driver Tudor.Ambarus at microchip.com
` (8 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Tudor.Ambarus at microchip.com @ 2019-05-14 10:26 UTC (permalink / raw)
To: u-boot
From: Tudor Ambarus <tudor.ambarus@microchip.com>
Describe the DT bindings for the driver of the Atmel QSPI
controller. Taken form linux v5.1-rc5.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
v3: no change
v2: no change
doc/device-tree-bindings/spi/atmel-quadspi.txt | 37 ++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
create mode 100644 doc/device-tree-bindings/spi/atmel-quadspi.txt
diff --git a/doc/device-tree-bindings/spi/atmel-quadspi.txt b/doc/device-tree-bindings/spi/atmel-quadspi.txt
new file mode 100644
index 000000000000..7c40ea694352
--- /dev/null
+++ b/doc/device-tree-bindings/spi/atmel-quadspi.txt
@@ -0,0 +1,37 @@
+* Atmel Quad Serial Peripheral Interface (QSPI)
+
+Required properties:
+- compatible: Should be one of the following:
+ - "atmel,sama5d2-qspi"
+ - "microchip,sam9x60-qspi"
+- reg: Should contain the locations and lengths of the base registers
+ and the mapped memory.
+- reg-names: Should contain the resource reg names:
+ - qspi_base: configuration register address space
+ - qspi_mmap: memory mapped address space
+- interrupts: Should contain the interrupt for the device.
+- clocks: Should reference the peripheral clock and the QSPI system
+ clock if available.
+- clock-names: Should contain "pclk" for the peripheral clock and "qspick"
+ for the system clock when available.
+- #address-cells: Should be <1>.
+- #size-cells: Should be <0>.
+
+Example:
+
+spi at f0020000 {
+ compatible = "atmel,sama5d2-qspi";
+ reg = <0xf0020000 0x100>, <0xd0000000 0x8000000>;
+ reg-names = "qspi_base", "qspi_mmap";
+ interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 52>;
+ clock-names = "pclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi0_default>;
+
+ m25p80 at 0 {
+ ...
+ };
+};
--
2.9.5
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH v3 02/10] spi: Add Atmel QuadSPI driver
2019-05-14 10:25 [U-Boot] [PATCH v3 00/10] spi: Add Atmel QuadSPI driver Tudor.Ambarus at microchip.com
2019-05-14 10:26 ` [U-Boot] [PATCH v3 01/10] dt-bindings: spi: add bindings for Atmel QSPI driver Tudor.Ambarus at microchip.com
@ 2019-05-14 10:26 ` Tudor.Ambarus at microchip.com
2019-05-14 16:35 ` Tudor.Ambarus at microchip.com
2019-05-14 10:26 ` [U-Boot] [PATCH v3 03/10] configs: sama5d2_xplained: enable qspi controller and flashes Tudor.Ambarus at microchip.com
` (7 subsequent siblings)
9 siblings, 1 reply; 15+ messages in thread
From: Tudor.Ambarus at microchip.com @ 2019-05-14 10:26 UTC (permalink / raw)
To: u-boot
From: Tudor Ambarus <tudor.ambarus@microchip.com>
Backport the driver from linux v5.1-rc5 and adapt it for u-boot.
Tested on sama5d2_xplained Rev B with mx25l25635e spi-nor flash.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
v3: no change
v2: no change
drivers/spi/Kconfig | 7 +
drivers/spi/Makefile | 1 +
drivers/spi/atmel-quadspi.c | 535 ++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 543 insertions(+)
create mode 100644 drivers/spi/atmel-quadspi.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index dc3e23f353aa..69c2f92c7826 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -49,6 +49,13 @@ config ATH79_SPI
uses driver model and requires a device tree binding to operate.
please refer to doc/device-tree-bindings/spi/spi-ath79.txt.
+config ATMEL_QSPI
+ bool "Atmel QSPI driver"
+ depends on ARCH_AT91
+ help
+ Enable the Ateml Quad-SPI (QSPI) driver. This driver can only be
+ used to access SPI NOR flashes.
+
config ATMEL_SPI
bool "Atmel SPI driver"
default y if ARCH_AT91
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 8be9a4baa244..32b42d18b1af 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -18,6 +18,7 @@ endif
obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
+obj-$(CONFIG_ATMEL_QSPI) += atmel-quadspi.o
obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
obj-$(CONFIG_BCM63XX_HSSPI) += bcm63xx_hsspi.o
obj-$(CONFIG_BCM63XX_SPI) += bcm63xx_spi.o
diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c
new file mode 100644
index 000000000000..c54fbe6bc6cf
--- /dev/null
+++ b/drivers/spi/atmel-quadspi.c
@@ -0,0 +1,535 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Driver for Atmel QSPI Controller
+ *
+ * Copyright (C) 2015 Atmel Corporation
+ * Copyright (C) 2018 Cryptera A/S
+ *
+ * Author: Cyrille Pitchen <cyrille.pitchen@atmel.com>
+ * Author: Piotr Bugalski <bugalski.piotr@gmail.com>
+ */
+
+#include <asm/io.h>
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/ioport.h>
+#include <mach/clk.h>
+#include <spi.h>
+#include <spi-mem.h>
+
+/* QSPI register offsets */
+#define QSPI_CR 0x0000 /* Control Register */
+#define QSPI_MR 0x0004 /* Mode Register */
+#define QSPI_RD 0x0008 /* Receive Data Register */
+#define QSPI_TD 0x000c /* Transmit Data Register */
+#define QSPI_SR 0x0010 /* Status Register */
+#define QSPI_IER 0x0014 /* Interrupt Enable Register */
+#define QSPI_IDR 0x0018 /* Interrupt Disable Register */
+#define QSPI_IMR 0x001c /* Interrupt Mask Register */
+#define QSPI_SCR 0x0020 /* Serial Clock Register */
+
+#define QSPI_IAR 0x0030 /* Instruction Address Register */
+#define QSPI_ICR 0x0034 /* Instruction Code Register */
+#define QSPI_WICR 0x0034 /* Write Instruction Code Register */
+#define QSPI_IFR 0x0038 /* Instruction Frame Register */
+#define QSPI_RICR 0x003C /* Read Instruction Code Register */
+
+#define QSPI_SMR 0x0040 /* Scrambling Mode Register */
+#define QSPI_SKR 0x0044 /* Scrambling Key Register */
+
+#define QSPI_WPMR 0x00E4 /* Write Protection Mode Register */
+#define QSPI_WPSR 0x00E8 /* Write Protection Status Register */
+
+#define QSPI_VERSION 0x00FC /* Version Register */
+
+/* Bitfields in QSPI_CR (Control Register) */
+#define QSPI_CR_QSPIEN BIT(0)
+#define QSPI_CR_QSPIDIS BIT(1)
+#define QSPI_CR_SWRST BIT(7)
+#define QSPI_CR_LASTXFER BIT(24)
+
+/* Bitfields in QSPI_MR (Mode Register) */
+#define QSPI_MR_SMM BIT(0)
+#define QSPI_MR_LLB BIT(1)
+#define QSPI_MR_WDRBT BIT(2)
+#define QSPI_MR_SMRM BIT(3)
+#define QSPI_MR_CSMODE_MASK GENMASK(5, 4)
+#define QSPI_MR_CSMODE_NOT_RELOADED (0 << 4)
+#define QSPI_MR_CSMODE_LASTXFER (1 << 4)
+#define QSPI_MR_CSMODE_SYSTEMATICALLY (2 << 4)
+#define QSPI_MR_NBBITS_MASK GENMASK(11, 8)
+#define QSPI_MR_NBBITS(n) ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK)
+#define QSPI_MR_DLYBCT_MASK GENMASK(23, 16)
+#define QSPI_MR_DLYBCT(n) (((n) << 16) & QSPI_MR_DLYBCT_MASK)
+#define QSPI_MR_DLYCS_MASK GENMASK(31, 24)
+#define QSPI_MR_DLYCS(n) (((n) << 24) & QSPI_MR_DLYCS_MASK)
+
+/* Bitfields in QSPI_SR/QSPI_IER/QSPI_IDR/QSPI_IMR */
+#define QSPI_SR_RDRF BIT(0)
+#define QSPI_SR_TDRE BIT(1)
+#define QSPI_SR_TXEMPTY BIT(2)
+#define QSPI_SR_OVRES BIT(3)
+#define QSPI_SR_CSR BIT(8)
+#define QSPI_SR_CSS BIT(9)
+#define QSPI_SR_INSTRE BIT(10)
+#define QSPI_SR_QSPIENS BIT(24)
+
+#define QSPI_SR_CMD_COMPLETED (QSPI_SR_INSTRE | QSPI_SR_CSR)
+
+/* Bitfields in QSPI_SCR (Serial Clock Register) */
+#define QSPI_SCR_CPOL BIT(0)
+#define QSPI_SCR_CPHA BIT(1)
+#define QSPI_SCR_SCBR_MASK GENMASK(15, 8)
+#define QSPI_SCR_SCBR(n) (((n) << 8) & QSPI_SCR_SCBR_MASK)
+#define QSPI_SCR_DLYBS_MASK GENMASK(23, 16)
+#define QSPI_SCR_DLYBS(n) (((n) << 16) & QSPI_SCR_DLYBS_MASK)
+
+/* Bitfields in QSPI_ICR (Read/Write Instruction Code Register) */
+#define QSPI_ICR_INST_MASK GENMASK(7, 0)
+#define QSPI_ICR_INST(inst) (((inst) << 0) & QSPI_ICR_INST_MASK)
+#define QSPI_ICR_OPT_MASK GENMASK(23, 16)
+#define QSPI_ICR_OPT(opt) (((opt) << 16) & QSPI_ICR_OPT_MASK)
+
+/* Bitfields in QSPI_IFR (Instruction Frame Register) */
+#define QSPI_IFR_WIDTH_MASK GENMASK(2, 0)
+#define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0 << 0)
+#define QSPI_IFR_WIDTH_DUAL_OUTPUT (1 << 0)
+#define QSPI_IFR_WIDTH_QUAD_OUTPUT (2 << 0)
+#define QSPI_IFR_WIDTH_DUAL_IO (3 << 0)
+#define QSPI_IFR_WIDTH_QUAD_IO (4 << 0)
+#define QSPI_IFR_WIDTH_DUAL_CMD (5 << 0)
+#define QSPI_IFR_WIDTH_QUAD_CMD (6 << 0)
+#define QSPI_IFR_INSTEN BIT(4)
+#define QSPI_IFR_ADDREN BIT(5)
+#define QSPI_IFR_OPTEN BIT(6)
+#define QSPI_IFR_DATAEN BIT(7)
+#define QSPI_IFR_OPTL_MASK GENMASK(9, 8)
+#define QSPI_IFR_OPTL_1BIT (0 << 8)
+#define QSPI_IFR_OPTL_2BIT (1 << 8)
+#define QSPI_IFR_OPTL_4BIT (2 << 8)
+#define QSPI_IFR_OPTL_8BIT (3 << 8)
+#define QSPI_IFR_ADDRL BIT(10)
+#define QSPI_IFR_TFRTYP_MEM BIT(12)
+#define QSPI_IFR_SAMA5D2_WRITE_TRSFR BIT(13)
+#define QSPI_IFR_CRM BIT(14)
+#define QSPI_IFR_NBDUM_MASK GENMASK(20, 16)
+#define QSPI_IFR_NBDUM(n) (((n) << 16) & QSPI_IFR_NBDUM_MASK)
+#define QSPI_IFR_APBTFRTYP_READ BIT(24) /* Defined in SAM9X60 */
+
+/* Bitfields in QSPI_SMR (Scrambling Mode Register) */
+#define QSPI_SMR_SCREN BIT(0)
+#define QSPI_SMR_RVDIS BIT(1)
+
+/* Bitfields in QSPI_WPMR (Write Protection Mode Register) */
+#define QSPI_WPMR_WPEN BIT(0)
+#define QSPI_WPMR_WPKEY_MASK GENMASK(31, 8)
+#define QSPI_WPMR_WPKEY(wpkey) (((wpkey) << 8) & QSPI_WPMR_WPKEY_MASK)
+
+/* Bitfields in QSPI_WPSR (Write Protection Status Register) */
+#define QSPI_WPSR_WPVS BIT(0)
+#define QSPI_WPSR_WPVSRC_MASK GENMASK(15, 8)
+#define QSPI_WPSR_WPVSRC(src) (((src) << 8) & QSPI_WPSR_WPVSRC)
+
+struct atmel_qspi_caps {
+ bool has_qspick;
+ bool has_ricr;
+};
+
+struct atmel_qspi {
+ void __iomem *regs;
+ void __iomem *mem;
+ struct platform_device *pdev;
+ const struct atmel_qspi_caps *caps;
+ ulong bus_clk_rate;
+ u32 mr;
+};
+
+struct atmel_qspi_mode {
+ u8 cmd_buswidth;
+ u8 addr_buswidth;
+ u8 data_buswidth;
+ u32 config;
+};
+
+static const struct atmel_qspi_mode atmel_qspi_modes[] = {
+ { 1, 1, 1, QSPI_IFR_WIDTH_SINGLE_BIT_SPI },
+ { 1, 1, 2, QSPI_IFR_WIDTH_DUAL_OUTPUT },
+ { 1, 1, 4, QSPI_IFR_WIDTH_QUAD_OUTPUT },
+ { 1, 2, 2, QSPI_IFR_WIDTH_DUAL_IO },
+ { 1, 4, 4, QSPI_IFR_WIDTH_QUAD_IO },
+ { 2, 2, 2, QSPI_IFR_WIDTH_DUAL_CMD },
+ { 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD },
+};
+
+static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op,
+ const struct atmel_qspi_mode *mode)
+{
+ if (op->cmd.buswidth != mode->cmd_buswidth)
+ return false;
+
+ if (op->addr.nbytes && op->addr.buswidth != mode->addr_buswidth)
+ return false;
+
+ if (op->data.nbytes && op->data.buswidth != mode->data_buswidth)
+ return false;
+
+ return true;
+}
+
+static int atmel_qspi_find_mode(const struct spi_mem_op *op)
+{
+ u32 i;
+
+ for (i = 0; i < ARRAY_SIZE(atmel_qspi_modes); i++)
+ if (atmel_qspi_is_compatible(op, &atmel_qspi_modes[i]))
+ return i;
+
+ return -ENOTSUPP;
+}
+
+static bool atmel_qspi_supports_op(struct spi_slave *slave,
+ const struct spi_mem_op *op)
+{
+ if (atmel_qspi_find_mode(op) < 0)
+ return false;
+
+ /* special case not supported by hardware */
+ if (op->addr.nbytes == 2 && op->cmd.buswidth != op->addr.buswidth &&
+ op->dummy.nbytes == 0)
+ return false;
+
+ return true;
+}
+
+static int atmel_qspi_set_cfg(struct atmel_qspi *aq,
+ const struct spi_mem_op *op, u32 *offset)
+{
+ u32 iar, icr, ifr;
+ u32 dummy_cycles = 0;
+ int mode;
+
+ iar = 0;
+ icr = QSPI_ICR_INST(op->cmd.opcode);
+ ifr = QSPI_IFR_INSTEN;
+
+ mode = atmel_qspi_find_mode(op);
+ if (mode < 0)
+ return mode;
+ ifr |= atmel_qspi_modes[mode].config;
+
+ if (op->dummy.buswidth && op->dummy.nbytes)
+ dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;
+
+ /*
+ * The controller allows 24 and 32-bit addressing while NAND-flash
+ * requires 16-bit long. Handling 8-bit long addresses is done using
+ * the option field. For the 16-bit addresses, the workaround depends
+ * of the number of requested dummy bits. If there are 8 or more dummy
+ * cycles, the address is shifted and sent with the first dummy byte.
+ * Otherwise opcode is disabled and the first byte of the address
+ * contains the command opcode (works only if the opcode and address
+ * use the same buswidth). The limitation is when the 16-bit address is
+ * used without enough dummy cycles and the opcode is using a different
+ * buswidth than the address.
+ */
+ if (op->addr.buswidth) {
+ switch (op->addr.nbytes) {
+ case 0:
+ break;
+ case 1:
+ ifr |= QSPI_IFR_OPTEN | QSPI_IFR_OPTL_8BIT;
+ icr |= QSPI_ICR_OPT(op->addr.val & 0xff);
+ break;
+ case 2:
+ if (dummy_cycles < 8 / op->addr.buswidth) {
+ ifr &= ~QSPI_IFR_INSTEN;
+ ifr |= QSPI_IFR_ADDREN;
+ iar = (op->cmd.opcode << 16) |
+ (op->addr.val & 0xffff);
+ } else {
+ ifr |= QSPI_IFR_ADDREN;
+ iar = (op->addr.val << 8) & 0xffffff;
+ dummy_cycles -= 8 / op->addr.buswidth;
+ }
+ break;
+ case 3:
+ ifr |= QSPI_IFR_ADDREN;
+ iar = op->addr.val & 0xffffff;
+ break;
+ case 4:
+ ifr |= QSPI_IFR_ADDREN | QSPI_IFR_ADDRL;
+ iar = op->addr.val & 0x7ffffff;
+ break;
+ default:
+ return -ENOTSUPP;
+ }
+ }
+
+ /* offset of the data access in the QSPI memory space */
+ *offset = iar;
+
+ /* Set number of dummy cycles */
+ if (dummy_cycles)
+ ifr |= QSPI_IFR_NBDUM(dummy_cycles);
+
+ /* Set data enable */
+ if (op->data.nbytes)
+ ifr |= QSPI_IFR_DATAEN;
+
+ /*
+ * If the QSPI controller is set in regular SPI mode, set it in
+ * Serial Memory Mode (SMM).
+ */
+ if (aq->mr != QSPI_MR_SMM) {
+ writel(QSPI_MR_SMM, aq->regs + QSPI_MR);
+ aq->mr = QSPI_MR_SMM;
+ }
+
+ /* Clear pending interrupts */
+ (void)readl(aq->regs + QSPI_SR);
+
+ if (aq->caps->has_ricr) {
+ if (!op->addr.nbytes && op->data.dir == SPI_MEM_DATA_IN)
+ ifr |= QSPI_IFR_APBTFRTYP_READ;
+
+ /* Set QSPI Instruction Frame registers */
+ writel(iar, aq->regs + QSPI_IAR);
+ if (op->data.dir == SPI_MEM_DATA_IN)
+ writel(icr, aq->regs + QSPI_RICR);
+ else
+ writel(icr, aq->regs + QSPI_WICR);
+ writel(ifr, aq->regs + QSPI_IFR);
+ } else {
+ if (op->data.dir == SPI_MEM_DATA_OUT)
+ ifr |= QSPI_IFR_SAMA5D2_WRITE_TRSFR;
+
+ /* Set QSPI Instruction Frame registers */
+ writel(iar, aq->regs + QSPI_IAR);
+ writel(icr, aq->regs + QSPI_ICR);
+ writel(ifr, aq->regs + QSPI_IFR);
+ }
+
+ return 0;
+}
+
+static int atmel_qspi_exec_op(struct spi_slave *slave,
+ const struct spi_mem_op *op)
+{
+ struct atmel_qspi *aq = dev_get_priv(slave->dev->parent);
+ u32 sr, imr, offset;
+ int err;
+
+ err = atmel_qspi_set_cfg(aq, op, &offset);
+ if (err)
+ return err;
+
+ /* Skip to the final steps if there is no data */
+ if (op->data.nbytes) {
+ /* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */
+ (void)readl(aq->regs + QSPI_IFR);
+
+ /* Send/Receive data */
+ if (op->data.dir == SPI_MEM_DATA_IN)
+ memcpy_fromio(op->data.buf.in, aq->mem + offset,
+ op->data.nbytes);
+ else
+ memcpy_toio(aq->mem + offset, op->data.buf.out,
+ op->data.nbytes);
+
+ /* Release the chip-select */
+ writel(QSPI_CR_LASTXFER, aq->regs + QSPI_CR);
+ }
+
+ /* Poll INSTruction End and Chip Select Rise flags. */
+ imr = QSPI_SR_INSTRE | QSPI_SR_CSR;
+ return readl_poll_timeout(aq->regs + QSPI_SR, sr, (sr & imr) == imr,
+ 1000000);
+}
+
+static int atmel_qspi_set_speed(struct udevice *bus, uint hz)
+{
+ struct atmel_qspi *aq = dev_get_priv(bus);
+ u32 scr, scbr, mask, new_value;
+
+ /* Compute the QSPI baudrate */
+ scbr = DIV_ROUND_UP(aq->bus_clk_rate, hz);
+ if (scbr > 0)
+ scbr--;
+
+ new_value = QSPI_SCR_SCBR(scbr);
+ mask = QSPI_SCR_SCBR_MASK;
+
+ scr = readl(aq->regs + QSPI_SCR);
+ if ((scr & mask) == new_value)
+ return 0;
+
+ scr = (scr & ~mask) | new_value;
+ writel(scr, aq->regs + QSPI_SCR);
+
+ return 0;
+}
+
+static int atmel_qspi_set_mode(struct udevice *bus, uint mode)
+{
+ struct atmel_qspi *aq = dev_get_priv(bus);
+ u32 scr, mask, new_value = 0;
+
+ if (mode & SPI_CPOL)
+ new_value = QSPI_SCR_CPOL;
+ if (mode & SPI_CPHA)
+ new_value = QSPI_SCR_CPHA;
+
+ mask = QSPI_SCR_CPOL | QSPI_SCR_CPHA;
+
+ scr = readl(aq->regs + QSPI_SCR);
+ if ((scr & mask) == new_value)
+ return 0;
+
+ scr = (scr & ~mask) | new_value;
+ writel(scr, aq->regs + QSPI_SCR);
+
+ return 0;
+}
+
+static int atmel_qspi_enable_clk(struct udevice *dev)
+{
+ struct atmel_qspi *aq = dev_get_priv(dev);
+ struct clk pclk, qspick;
+ int ret;
+
+ ret = clk_get_by_name(dev, "pclk", &pclk);
+ if (ret)
+ ret = clk_get_by_index(dev, 0, &pclk);
+
+ if (ret) {
+ dev_err(dev, "Missing QSPI peripheral clock\n");
+ return ret;
+ }
+
+ ret = clk_enable(&pclk);
+ if (ret) {
+ dev_err(dev, "Failed to enable QSPI peripheral clock\n");
+ goto free_pclk;
+ }
+
+ if (aq->caps->has_qspick) {
+ /* Get the QSPI system clock */
+ ret = clk_get_by_name(dev, "qspick", &qspick);
+ if (ret) {
+ dev_err(dev, "Missing QSPI peripheral clock\n");
+ goto free_pclk;
+ }
+
+ ret = clk_enable(&qspick);
+ if (ret)
+ dev_err(dev, "Failed to enable QSPI system clock\n");
+ clk_free(&qspick);
+ }
+
+ aq->bus_clk_rate = clk_get_rate(&pclk);
+ if (!aq->bus_clk_rate)
+ ret = -EINVAL;
+
+free_pclk:
+ clk_free(&pclk);
+
+ return ret;
+}
+
+static void atmel_qspi_init(struct atmel_qspi *aq)
+{
+ /* Reset the QSPI controller */
+ writel(QSPI_CR_SWRST, aq->regs + QSPI_CR);
+
+ /* Set the QSPI controller by default in Serial Memory Mode */
+ writel(QSPI_MR_SMM, aq->regs + QSPI_MR);
+ aq->mr = QSPI_MR_SMM;
+
+ /* Enable the QSPI controller */
+ writel(QSPI_CR_QSPIEN, aq->regs + QSPI_CR);
+}
+
+static int atmel_qspi_probe(struct udevice *dev)
+{
+ struct atmel_qspi *aq = dev_get_priv(dev);
+ struct resource res;
+ int ret;
+
+ aq->caps = (struct atmel_qspi_caps *)dev_get_driver_data(dev);
+ if (!aq->caps) {
+ dev_err(dev, "Could not retrieve QSPI caps\n");
+ return -EINVAL;
+ };
+
+ /* Map the registers */
+ ret = dev_read_resource_byname(dev, "qspi_base", &res);
+ if (ret) {
+ dev_err(dev, "missing registers\n");
+ return ret;
+ }
+ aq->regs = devm_ioremap(dev, res.start, resource_size(&res));
+ if (IS_ERR(aq->regs))
+ return PTR_ERR(aq->regs);
+
+ /* Map the AHB memory */
+ ret = dev_read_resource_byname(dev, "qspi_mmap", &res);
+ if (ret) {
+ dev_err(dev, "missing AHB memory\n");
+ return ret;
+ }
+ aq->mem = devm_ioremap(dev, res.start, resource_size(&res));
+ if (IS_ERR(aq->mem))
+ return PTR_ERR(aq->mem);
+
+ ret = atmel_qspi_enable_clk(dev);
+ if (ret)
+ return ret;
+
+ atmel_qspi_init(aq);
+
+ return 0;
+}
+
+static const struct spi_controller_mem_ops atmel_qspi_mem_ops = {
+ .supports_op = atmel_qspi_supports_op,
+ .exec_op = atmel_qspi_exec_op,
+};
+
+static const struct dm_spi_ops atmel_qspi_ops = {
+ .set_speed = atmel_qspi_set_speed,
+ .set_mode = atmel_qspi_set_mode,
+ .mem_ops = &atmel_qspi_mem_ops,
+};
+
+static const struct atmel_qspi_caps atmel_sama5d2_qspi_caps = {};
+
+static const struct atmel_qspi_caps atmel_sam9x60_qspi_caps = {
+ .has_qspick = true,
+ .has_ricr = true,
+};
+
+static const struct udevice_id atmel_qspi_ids[] = {
+ {
+ .compatible = "atmel,sama5d2-qspi",
+ .data = (ulong)&atmel_sama5d2_qspi_caps,
+ },
+ {
+ .compatible = "microchip,sam9x60-qspi",
+ .data = (ulong)&atmel_sam9x60_qspi_caps,
+ },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(atmel_qspi) = {
+ .name = "atmel_qspi",
+ .id = UCLASS_SPI,
+ .of_match = atmel_qspi_ids,
+ .ops = &atmel_qspi_ops,
+ .priv_auto_alloc_size = sizeof(struct atmel_qspi),
+ .probe = atmel_qspi_probe,
+};
--
2.9.5
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH v3 03/10] configs: sama5d2_xplained: enable qspi controller and flashes
2019-05-14 10:25 [U-Boot] [PATCH v3 00/10] spi: Add Atmel QuadSPI driver Tudor.Ambarus at microchip.com
2019-05-14 10:26 ` [U-Boot] [PATCH v3 01/10] dt-bindings: spi: add bindings for Atmel QSPI driver Tudor.Ambarus at microchip.com
2019-05-14 10:26 ` [U-Boot] [PATCH v3 02/10] spi: Add Atmel QuadSPI driver Tudor.Ambarus at microchip.com
@ 2019-05-14 10:26 ` Tudor.Ambarus at microchip.com
2019-05-14 10:26 ` [U-Boot] [PATCH v3 04/10] configs: sama5d27_som1_ek: " Tudor.Ambarus at microchip.com
` (6 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Tudor.Ambarus at microchip.com @ 2019-05-14 10:26 UTC (permalink / raw)
To: u-boot
From: Tudor Ambarus <tudor.ambarus@microchip.com>
We have a macronix spi-nor flash on sama5d2_xplained RevB and
a sst spi-nor flash on RevC. Select the rest for testing purposes.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
v3: no change
v2: new patch
configs/sama5d2_xplained_emmc_defconfig | 5 +++++
configs/sama5d2_xplained_mmc_defconfig | 5 +++++
configs/sama5d2_xplained_spiflash_defconfig | 5 +++++
3 files changed, 15 insertions(+)
diff --git a/configs/sama5d2_xplained_emmc_defconfig b/configs/sama5d2_xplained_emmc_defconfig
index f643b5a62f39..f244777121b1 100644
--- a/configs/sama5d2_xplained_emmc_defconfig
+++ b/configs/sama5d2_xplained_emmc_defconfig
@@ -65,6 +65,10 @@ CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_DM_ETH=y
CONFIG_MACB=y
CONFIG_PINCTRL=y
@@ -76,6 +80,7 @@ CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
+CONFIG_ATMEL_QSPI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig
index c25d67bfebb1..633f6c5ad00c 100644
--- a/configs/sama5d2_xplained_mmc_defconfig
+++ b/configs/sama5d2_xplained_mmc_defconfig
@@ -67,6 +67,10 @@ CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_DM_ETH=y
CONFIG_MACB=y
CONFIG_PINCTRL=y
@@ -78,6 +82,7 @@ CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
+CONFIG_ATMEL_QSPI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig
index ac5ae5133c3d..39da86530429 100644
--- a/configs/sama5d2_xplained_spiflash_defconfig
+++ b/configs/sama5d2_xplained_spiflash_defconfig
@@ -64,6 +64,10 @@ CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_DM_ETH=y
CONFIG_MACB=y
CONFIG_PINCTRL=y
@@ -75,6 +79,7 @@ CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
+CONFIG_ATMEL_QSPI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
--
2.9.5
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH v3 04/10] configs: sama5d27_som1_ek: enable qspi controller and flashes
2019-05-14 10:25 [U-Boot] [PATCH v3 00/10] spi: Add Atmel QuadSPI driver Tudor.Ambarus at microchip.com
` (2 preceding siblings ...)
2019-05-14 10:26 ` [U-Boot] [PATCH v3 03/10] configs: sama5d2_xplained: enable qspi controller and flashes Tudor.Ambarus at microchip.com
@ 2019-05-14 10:26 ` Tudor.Ambarus at microchip.com
2019-05-14 10:26 ` [U-Boot] [PATCH v3 05/10] ARM: dts: at91: sama5d2_xplained: fix QSPI0 node Tudor.Ambarus at microchip.com
` (5 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Tudor.Ambarus at microchip.com @ 2019-05-14 10:26 UTC (permalink / raw)
To: u-boot
From: Tudor Ambarus <tudor.ambarus@microchip.com>
We use a sst spi-nor flash memory on sama5d27_som1_ek. Select
the others for testing purposes.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
v3: no change
v2: new patch
configs/sama5d27_som1_ek_mmc1_defconfig | 2 ++
configs/sama5d27_som1_ek_mmc_defconfig | 2 ++
2 files changed, 4 insertions(+)
diff --git a/configs/sama5d27_som1_ek_mmc1_defconfig b/configs/sama5d27_som1_ek_mmc1_defconfig
index 205a4399410f..9b2b78110357 100644
--- a/configs/sama5d27_som1_ek_mmc1_defconfig
+++ b/configs/sama5d27_som1_ek_mmc1_defconfig
@@ -67,6 +67,7 @@ CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=66000000
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_DM_ETH=y
@@ -80,6 +81,7 @@ CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
+CONFIG_ATMEL_QSPI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
diff --git a/configs/sama5d27_som1_ek_mmc_defconfig b/configs/sama5d27_som1_ek_mmc_defconfig
index 0a0780066cd8..e5c551e205d0 100644
--- a/configs/sama5d27_som1_ek_mmc_defconfig
+++ b/configs/sama5d27_som1_ek_mmc_defconfig
@@ -67,6 +67,7 @@ CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=66000000
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_DM_ETH=y
@@ -80,6 +81,7 @@ CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
+CONFIG_ATMEL_QSPI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
--
2.9.5
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH v3 05/10] ARM: dts: at91: sama5d2_xplained: fix QSPI0 node
2019-05-14 10:25 [U-Boot] [PATCH v3 00/10] spi: Add Atmel QuadSPI driver Tudor.Ambarus at microchip.com
` (3 preceding siblings ...)
2019-05-14 10:26 ` [U-Boot] [PATCH v3 04/10] configs: sama5d27_som1_ek: " Tudor.Ambarus at microchip.com
@ 2019-05-14 10:26 ` Tudor.Ambarus at microchip.com
2019-05-14 10:26 ` [U-Boot] [PATCH v3 06/10] ARM: at91: sama5: add common environment for QSPI Tudor.Ambarus at microchip.com
` (4 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Tudor.Ambarus at microchip.com @ 2019-05-14 10:26 UTC (permalink / raw)
To: u-boot
From: Cyrille Pitchen <cyrille.pitchen@microchip.com>
Fix the following:
- use "jedec,spi-nor" binding, we use jedec compatible flashes
- set bus width to 4, we use quad capable flashes
- differentiate bewteen data and clk and cs pins
- drop partions as we don't use them in u-boot.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@microchip.com>
[tudor.ambarus at microchip.com: use "jedec,spi-nor", edit commit message]
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
v3: no change
v2: new patch
arch/arm/dts/at91-sama5d2_xplained.dts | 36 ++++++++++++++++------------------
1 file changed, 17 insertions(+), 19 deletions(-)
diff --git a/arch/arm/dts/at91-sama5d2_xplained.dts b/arch/arm/dts/at91-sama5d2_xplained.dts
index c0708feeb7b2..7f0d1696ba3e 100644
--- a/arch/arm/dts/at91-sama5d2_xplained.dts
+++ b/arch/arm/dts/at91-sama5d2_xplained.dts
@@ -79,26 +79,18 @@
};
qspi0: spi at f0020000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi0_sck_cs_default &pinctrl_qspi0_dat_default>;
status = "okay";
+ u-boot,dm-pre-reloc;
flash at 0 {
- compatible = "atmel,sama5d2-qspi-flash";
+ compatible = "jedec,spi-nor";
reg = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_qspi0_default>;
spi-max-frequency = <83000000>;
-
- partition at 00000000 {
- label = "boot";
- reg = <0x00000000 0x00c00000>;
- };
-
- partition at 00c00000 {
- label = "rootfs";
- reg = <0x00c00000 0x00000000>;
- };
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ u-boot,dm-pre-reloc;
};
};
@@ -208,14 +200,20 @@
bias-disable;
};
- pinctrl_qspi0_default: qspi0_default {
+ pinctrl_qspi0_sck_cs_default: qspi0_sck_cs_default {
pinmux = <PIN_PA22__QSPI0_SCK>,
- <PIN_PA23__QSPI0_CS>,
- <PIN_PA24__QSPI0_IO0>,
+ <PIN_PA23__QSPI0_CS>;
+ bias-disable;
+ u-boot,dm-pre-reloc;
+ };
+
+ pinctrl_qspi0_dat_default: qspi0_dat_default {
+ pinmux = <PIN_PA24__QSPI0_IO0>,
<PIN_PA25__QSPI0_IO1>,
<PIN_PA26__QSPI0_IO2>,
<PIN_PA27__QSPI0_IO3>;
- bias-disable;
+ bias-pull-up;
+ u-boot,dm-pre-reloc;
};
pinctrl_sdmmc0_cmd_dat_default: sdmmc0_cmd_dat_default {
--
2.9.5
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH v3 06/10] ARM: at91: sama5: add common environment for QSPI
2019-05-14 10:25 [U-Boot] [PATCH v3 00/10] spi: Add Atmel QuadSPI driver Tudor.Ambarus at microchip.com
` (4 preceding siblings ...)
2019-05-14 10:26 ` [U-Boot] [PATCH v3 05/10] ARM: dts: at91: sama5d2_xplained: fix QSPI0 node Tudor.Ambarus at microchip.com
@ 2019-05-14 10:26 ` Tudor.Ambarus at microchip.com
2019-05-14 10:26 ` [U-Boot] [PATCH v3 07/10] configs: sama5d2_xplained: add qspiflash_defconfig Tudor.Ambarus at microchip.com
` (3 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Tudor.Ambarus at microchip.com @ 2019-05-14 10:26 UTC (permalink / raw)
To: u-boot
From: Cyrille Pitchen <cyrille.pitchen@microchip.com>
Use the same memory layout as we use for the NAND boot on the other boards.
QSPI flashes are present on the following boards:
sama5d2_xplained RevB: 32 Mbyte flash (mx25l3273fm2i-08g)
sama5d2_xplained RevC: 8 Mbyte flash (sst26vf064b-104i/sn)
sama5d27_som1_ek: 8 Mbyte flash (sst26vf064b-104i/sn)
sama5d2_ptc_ek: 8 Mbyte flash (sst26vf064b-104i/sn)
The 8 Mbyte limit is enough to cope with the memory layout used in the NAND
boot. rootfs exceeds the 8 Mbyte limit and will stay in eMMC in the
sama5d2_xplained case. The final scope is to use a single memory layout for
all boot medias.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@microchip.com>
[tudor.ambarus at microchip.com: change memory layout, add commit message]
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
v3: no change
v2: new patch
include/configs/at91-sama5_common.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h
index 30c6cd47cac2..fc46540a10ab 100644
--- a/include/configs/at91-sama5_common.h
+++ b/include/configs/at91-sama5_common.h
@@ -72,6 +72,14 @@
"sf read 0x21000000 0x60000 0xc000; " \
"sf read 0x22000000 0x6c000 0x394000; " \
"bootz 0x22000000 - 0x21000000"
+#elif CONFIG_QSPI_BOOT
+#define CONFIG_ENV_OFFSET 0x140000
+#define CONFIG_ENV_SIZE 0x20000
+#define CONFIG_ENV_SECT_SIZE 0x1000
+#define CONFIG_BOOTCOMMAND "sf probe 0; " \
+ "sf read 0x21000000 0x180000 0x80000; " \
+ "sf read 0x22000000 0x200000 0x600000; " \
+ "bootz 0x22000000 - 0x21000000"
#endif
#endif
--
2.9.5
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH v3 07/10] configs: sama5d2_xplained: add qspiflash_defconfig
2019-05-14 10:25 [U-Boot] [PATCH v3 00/10] spi: Add Atmel QuadSPI driver Tudor.Ambarus at microchip.com
` (5 preceding siblings ...)
2019-05-14 10:26 ` [U-Boot] [PATCH v3 06/10] ARM: at91: sama5: add common environment for QSPI Tudor.Ambarus at microchip.com
@ 2019-05-14 10:26 ` Tudor.Ambarus at microchip.com
2019-05-14 10:26 ` [U-Boot] [PATCH v3 08/10] configs: sama5d27_som1_ek: " Tudor.Ambarus at microchip.com
` (2 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Tudor.Ambarus at microchip.com @ 2019-05-14 10:26 UTC (permalink / raw)
To: u-boot
From: Tudor Ambarus <tudor.ambarus@microchip.com>
Add the default config file of QSPI media. The config is based on
sama5d2_xplained_mmc_defconfig.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
v3: fix the following:
./tools/genboardscfg.py
WARNING: no status info for 'sama5d2_xplained_qspiflash'
WARNING: no maintainers for 'sama5d2_xplained_qspiflash'
v2: new patch
board/atmel/sama5d2_xplained/MAINTAINERS | 1 +
configs/sama5d2_xplained_qspiflash_defconfig | 101 +++++++++++++++++++++++++++
2 files changed, 102 insertions(+)
create mode 100644 configs/sama5d2_xplained_qspiflash_defconfig
diff --git a/board/atmel/sama5d2_xplained/MAINTAINERS b/board/atmel/sama5d2_xplained/MAINTAINERS
index 08de5bb6a076..88e327f81cd8 100644
--- a/board/atmel/sama5d2_xplained/MAINTAINERS
+++ b/board/atmel/sama5d2_xplained/MAINTAINERS
@@ -6,3 +6,4 @@ F: include/configs/sama5d2_xplained.h
F: configs/sama5d2_xplained_mmc_defconfig
F: configs/sama5d2_xplained_spiflash_defconfig
F: configs/sama5d2_xplained_emmc_defconfig
+F: configs/sama5d2_xplained_qspiflash_defconfig
diff --git a/configs/sama5d2_xplained_qspiflash_defconfig b/configs/sama5d2_xplained_qspiflash_defconfig
new file mode 100644
index 000000000000..1bf04936f748
--- /dev/null
+++ b/configs/sama5d2_xplained_qspiflash_defconfig
@@ -0,0 +1,101 @@
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_SYS_TEXT_BASE=0x26f00000
+CONFIG_TARGET_SAMA5D2_XPLAINED=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_BASE=0xf8020000
+CONFIG_DEBUG_UART_CLOCK=83000000
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_DEBUG_UART=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_MMC"
+CONFIG_QSPI_BOOT=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p1 rw rootwait"
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL_TEXT_BASE=0x200000
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_xplained"
+CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_AT91_GENERIC_CLK=y
+CONFIG_DM_GPIO=y
+CONFIG_ATMEL_PIO4=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_AT91=y
+CONFIG_I2C_EEPROM=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ATMEL=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=30000000
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_DM_ETH=y
+CONFIG_MACB=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_ATMEL_QSPI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_ATMEL_USBA=y
+CONFIG_DM_VIDEO=y
+CONFIG_ATMEL_HLCD=y
+CONFIG_W1=y
+CONFIG_W1_GPIO=y
+CONFIG_W1_EEPROM=y
+CONFIG_W1_EEPROM_DS24XXX=y
+CONFIG_FAT_WRITE=y
+CONFIG_OF_LIBFDT_OVERLAY=y
--
2.9.5
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH v3 08/10] configs: sama5d27_som1_ek: add qspiflash_defconfig
2019-05-14 10:25 [U-Boot] [PATCH v3 00/10] spi: Add Atmel QuadSPI driver Tudor.Ambarus at microchip.com
` (6 preceding siblings ...)
2019-05-14 10:26 ` [U-Boot] [PATCH v3 07/10] configs: sama5d2_xplained: add qspiflash_defconfig Tudor.Ambarus at microchip.com
@ 2019-05-14 10:26 ` Tudor.Ambarus at microchip.com
2019-05-14 10:26 ` [U-Boot] [PATCH v3 09/10] configs: sama5d27_som1_ek: qspi: use common memory layout Tudor.Ambarus at microchip.com
2019-05-14 10:26 ` [U-Boot] [PATCH v3 10/10] configs: sama5d2_xplained: add support QSPI flash boot Tudor.Ambarus at microchip.com
9 siblings, 0 replies; 15+ messages in thread
From: Tudor.Ambarus at microchip.com @ 2019-05-14 10:26 UTC (permalink / raw)
To: u-boot
From: Tudor Ambarus <tudor.ambarus@microchip.com>
Add the default config file of QSPI media. The config is based on
sama5d27_som1_ek_mmc_defconfig.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
v3: fix the following:
./tools/genboardscfg.py
WARNING: no status info for 'sama5d27_som1_ek_qspiflash'
WARNING: no maintainers for 'sama5d27_som1_ek_qspiflash'
v2: new patch
board/atmel/sama5d27_som1_ek/MAINTAINERS | 1 +
configs/sama5d27_som1_ek_qspiflash_defconfig | 101 +++++++++++++++++++++++++++
2 files changed, 102 insertions(+)
create mode 100644 configs/sama5d27_som1_ek_qspiflash_defconfig
diff --git a/board/atmel/sama5d27_som1_ek/MAINTAINERS b/board/atmel/sama5d27_som1_ek/MAINTAINERS
index 74434e93e952..f2d2f49db304 100644
--- a/board/atmel/sama5d27_som1_ek/MAINTAINERS
+++ b/board/atmel/sama5d27_som1_ek/MAINTAINERS
@@ -5,3 +5,4 @@ F: board/atmel/sama5d27_som1_ek/
F: include/configs/sama5d27_som1_ek.h
F: configs/sama5d27_som1_ek_mmc_defconfig
F: configs/sama5d27_som1_ek_mmc1_defconfig
+F: configs/sama5d27_som1_ek_qspiflash_defconfig
diff --git a/configs/sama5d27_som1_ek_qspiflash_defconfig b/configs/sama5d27_som1_ek_qspiflash_defconfig
new file mode 100644
index 000000000000..128b6645f6d9
--- /dev/null
+++ b/configs/sama5d27_som1_ek_qspiflash_defconfig
@@ -0,0 +1,101 @@
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_SYS_TEXT_BASE=0x23f00000
+CONFIG_TARGET_SAMA5D27_SOM1_EK=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_BASE=0xf8020000
+CONFIG_DEBUG_UART_CLOCK=82000000
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_DEBUG_UART=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2"
+CONFIG_QSPI_BOOT=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL_TEXT_BASE=0x200000
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_som1_ek"
+CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_AT91_GENERIC_CLK=y
+CONFIG_DM_GPIO=y
+CONFIG_ATMEL_PIO4=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_AT91=y
+CONFIG_I2C_EEPROM=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ATMEL=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=66000000
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_DM_ETH=y
+CONFIG_MACB=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_ATMEL_QSPI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_ATMEL_USBA=y
+CONFIG_DM_VIDEO=y
+CONFIG_ATMEL_HLCD=y
+CONFIG_W1=y
+CONFIG_W1_GPIO=y
+CONFIG_W1_EEPROM=y
+CONFIG_W1_EEPROM_DS24XXX=y
+CONFIG_FAT_WRITE=y
+CONFIG_OF_LIBFDT_OVERLAY=y
--
2.9.5
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH v3 09/10] configs: sama5d27_som1_ek: qspi: use common memory layout
2019-05-14 10:25 [U-Boot] [PATCH v3 00/10] spi: Add Atmel QuadSPI driver Tudor.Ambarus at microchip.com
` (7 preceding siblings ...)
2019-05-14 10:26 ` [U-Boot] [PATCH v3 08/10] configs: sama5d27_som1_ek: " Tudor.Ambarus at microchip.com
@ 2019-05-14 10:26 ` Tudor.Ambarus at microchip.com
2019-05-14 10:26 ` [U-Boot] [PATCH v3 10/10] configs: sama5d2_xplained: add support QSPI flash boot Tudor.Ambarus at microchip.com
9 siblings, 0 replies; 15+ messages in thread
From: Tudor.Ambarus at microchip.com @ 2019-05-14 10:26 UTC (permalink / raw)
To: u-boot
From: Tudor Ambarus <tudor.ambarus@microchip.com>
Use the qspi memory layout defined in at91-sama5_common - it aligns
with the 8 Mbyte flash (sst26vf064b-104i/sn) available in sama5d27_som1_ek.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
v3: no change
v2: new patch
include/configs/sama5d27_som1_ek.h | 7 -------
1 file changed, 7 deletions(-)
diff --git a/include/configs/sama5d27_som1_ek.h b/include/configs/sama5d27_som1_ek.h
index 5f6979cd77a5..90846c4bfd44 100644
--- a/include/configs/sama5d27_som1_ek.h
+++ b/include/configs/sama5d27_som1_ek.h
@@ -43,13 +43,6 @@
#endif
#ifdef CONFIG_QSPI_BOOT
-#define CONFIG_ENV_OFFSET 0xb0000
-#define CONFIG_ENV_SIZE 0x10000
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#define CONFIG_BOOTCOMMAND "sf probe 0; " \
- "sf read 0x21000000 0xc0000 0x20000; " \
- "sf read 0x22000000 0xe0000 0x400000; " \
- "bootz 0x22000000 - 0x21000000"
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTARGS \
"console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
--
2.9.5
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH v3 10/10] configs: sama5d2_xplained: add support QSPI flash boot
2019-05-14 10:25 [U-Boot] [PATCH v3 00/10] spi: Add Atmel QuadSPI driver Tudor.Ambarus at microchip.com
` (8 preceding siblings ...)
2019-05-14 10:26 ` [U-Boot] [PATCH v3 09/10] configs: sama5d27_som1_ek: qspi: use common memory layout Tudor.Ambarus at microchip.com
@ 2019-05-14 10:26 ` Tudor.Ambarus at microchip.com
9 siblings, 0 replies; 15+ messages in thread
From: Tudor.Ambarus at microchip.com @ 2019-05-14 10:26 UTC (permalink / raw)
To: u-boot
From: Eugen Hristev <eugen.hristev@microchip.com>
The spi-nor flash resides on spi bus 1. Update the CONFIG_ENV_SPI_CS
and CONFIG_BOOTCOMMAND accordingly.
Based on original work by Wenyou Yang.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
[tudor.ambarus at microchip.com: amend the commit message.]
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
v3: no change
v2: new patch
include/configs/sama5d2_xplained.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/include/configs/sama5d2_xplained.h b/include/configs/sama5d2_xplained.h
index e522740e0c5b..3dea3591275f 100644
--- a/include/configs/sama5d2_xplained.h
+++ b/include/configs/sama5d2_xplained.h
@@ -46,6 +46,17 @@
#endif
+#ifdef CONFIG_QSPI_BOOT
+#undef CONFIG_ENV_SPI_BUS
+#undef CONFIG_BOOTCOMMAND
+#define CONFIG_ENV_SPI_BUS 1
+#define CONFIG_BOOTCOMMAND "sf probe 1:0; " \
+ "sf read 0x21000000 0x180000 0x80000; " \
+ "sf read 0x22000000 0x200000 0x600000; "\
+ "bootz 0x22000000 - 0x21000000"
+
+#endif
+
/* SPL */
#define CONFIG_SPL_MAX_SIZE 0x10000
#define CONFIG_SPL_BSS_START_ADDR 0x20000000
--
2.9.5
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH v3 02/10] spi: Add Atmel QuadSPI driver
2019-05-14 10:26 ` [U-Boot] [PATCH v3 02/10] spi: Add Atmel QuadSPI driver Tudor.Ambarus at microchip.com
@ 2019-05-14 16:35 ` Tudor.Ambarus at microchip.com
2019-05-15 7:01 ` [U-Boot] [PATCH v4 " Tudor.Ambarus at microchip.com
0 siblings, 1 reply; 15+ messages in thread
From: Tudor.Ambarus at microchip.com @ 2019-05-14 16:35 UTC (permalink / raw)
To: u-boot
On 05/14/2019 01:26 PM, Tudor Ambarus - M18064 wrote:
> From: Tudor Ambarus <tudor.ambarus@microchip.com>
>
> Backport the driver from linux v5.1-rc5 and adapt it for u-boot.
> Tested on sama5d2_xplained Rev B with mx25l25635e spi-nor flash.
>
> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
> ---
> v3: no change
> v2: no change
>
> drivers/spi/Kconfig | 7 +
> drivers/spi/Makefile | 1 +
> drivers/spi/atmel-quadspi.c | 535 ++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 543 insertions(+)
> create mode 100644 drivers/spi/atmel-quadspi.c
>
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index dc3e23f353aa..69c2f92c7826 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -49,6 +49,13 @@ config ATH79_SPI
> uses driver model and requires a device tree binding to operate.
> please refer to doc/device-tree-bindings/spi/spi-ath79.txt.
>
> +config ATMEL_QSPI
> + bool "Atmel QSPI driver"
"Atmel Quad SPI Controller"
> + depends on ARCH_AT91
> + help
> + Enable the Ateml Quad-SPI (QSPI) driver. This driver can only be
> + used to access SPI NOR flashes.
The description is wrong, I'll submit a new version if everything else looks ok.
This should have been:
This enables support for the Quad SPI controller in master mode.
This driver does not support generic SPI. The implementation only
supports spi-mem interface.
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH v4 02/10] spi: Add Atmel QuadSPI driver
2019-05-14 16:35 ` Tudor.Ambarus at microchip.com
@ 2019-05-15 7:01 ` Tudor.Ambarus at microchip.com
2019-06-12 8:02 ` Jagan Teki
0 siblings, 1 reply; 15+ messages in thread
From: Tudor.Ambarus at microchip.com @ 2019-05-15 7:01 UTC (permalink / raw)
To: u-boot
From: Tudor Ambarus <tudor.ambarus@microchip.com>
Backport the driver from linux v5.1-rc5 and adapt it for u-boot.
Tested on sama5d2_xplained Rev B with mx25l25635e spi-nor flash.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
v4: update Kconfig description
v3: no change
v2: no change
drivers/spi/Kconfig | 8 +
drivers/spi/Makefile | 1 +
drivers/spi/atmel-quadspi.c | 535 ++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 544 insertions(+)
create mode 100644 drivers/spi/atmel-quadspi.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index dc3e23f353aa..0b87c155b87a 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -49,6 +49,14 @@ config ATH79_SPI
uses driver model and requires a device tree binding to operate.
please refer to doc/device-tree-bindings/spi/spi-ath79.txt.
+config ATMEL_QSPI
+ bool "Atmel Quad SPI Controller"
+ depends on ARCH_AT91
+ help
+ Enable the Atmel Quad SPI controller in master mode. This driver
+ does not support generic SPI. The implementation supports only the
+ spi-mem interface.
+
config ATMEL_SPI
bool "Atmel SPI driver"
default y if ARCH_AT91
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 8be9a4baa244..32b42d18b1af 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -18,6 +18,7 @@ endif
obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
+obj-$(CONFIG_ATMEL_QSPI) += atmel-quadspi.o
obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
obj-$(CONFIG_BCM63XX_HSSPI) += bcm63xx_hsspi.o
obj-$(CONFIG_BCM63XX_SPI) += bcm63xx_spi.o
diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c
new file mode 100644
index 000000000000..c54fbe6bc6cf
--- /dev/null
+++ b/drivers/spi/atmel-quadspi.c
@@ -0,0 +1,535 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Driver for Atmel QSPI Controller
+ *
+ * Copyright (C) 2015 Atmel Corporation
+ * Copyright (C) 2018 Cryptera A/S
+ *
+ * Author: Cyrille Pitchen <cyrille.pitchen@atmel.com>
+ * Author: Piotr Bugalski <bugalski.piotr@gmail.com>
+ */
+
+#include <asm/io.h>
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/ioport.h>
+#include <mach/clk.h>
+#include <spi.h>
+#include <spi-mem.h>
+
+/* QSPI register offsets */
+#define QSPI_CR 0x0000 /* Control Register */
+#define QSPI_MR 0x0004 /* Mode Register */
+#define QSPI_RD 0x0008 /* Receive Data Register */
+#define QSPI_TD 0x000c /* Transmit Data Register */
+#define QSPI_SR 0x0010 /* Status Register */
+#define QSPI_IER 0x0014 /* Interrupt Enable Register */
+#define QSPI_IDR 0x0018 /* Interrupt Disable Register */
+#define QSPI_IMR 0x001c /* Interrupt Mask Register */
+#define QSPI_SCR 0x0020 /* Serial Clock Register */
+
+#define QSPI_IAR 0x0030 /* Instruction Address Register */
+#define QSPI_ICR 0x0034 /* Instruction Code Register */
+#define QSPI_WICR 0x0034 /* Write Instruction Code Register */
+#define QSPI_IFR 0x0038 /* Instruction Frame Register */
+#define QSPI_RICR 0x003C /* Read Instruction Code Register */
+
+#define QSPI_SMR 0x0040 /* Scrambling Mode Register */
+#define QSPI_SKR 0x0044 /* Scrambling Key Register */
+
+#define QSPI_WPMR 0x00E4 /* Write Protection Mode Register */
+#define QSPI_WPSR 0x00E8 /* Write Protection Status Register */
+
+#define QSPI_VERSION 0x00FC /* Version Register */
+
+/* Bitfields in QSPI_CR (Control Register) */
+#define QSPI_CR_QSPIEN BIT(0)
+#define QSPI_CR_QSPIDIS BIT(1)
+#define QSPI_CR_SWRST BIT(7)
+#define QSPI_CR_LASTXFER BIT(24)
+
+/* Bitfields in QSPI_MR (Mode Register) */
+#define QSPI_MR_SMM BIT(0)
+#define QSPI_MR_LLB BIT(1)
+#define QSPI_MR_WDRBT BIT(2)
+#define QSPI_MR_SMRM BIT(3)
+#define QSPI_MR_CSMODE_MASK GENMASK(5, 4)
+#define QSPI_MR_CSMODE_NOT_RELOADED (0 << 4)
+#define QSPI_MR_CSMODE_LASTXFER (1 << 4)
+#define QSPI_MR_CSMODE_SYSTEMATICALLY (2 << 4)
+#define QSPI_MR_NBBITS_MASK GENMASK(11, 8)
+#define QSPI_MR_NBBITS(n) ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK)
+#define QSPI_MR_DLYBCT_MASK GENMASK(23, 16)
+#define QSPI_MR_DLYBCT(n) (((n) << 16) & QSPI_MR_DLYBCT_MASK)
+#define QSPI_MR_DLYCS_MASK GENMASK(31, 24)
+#define QSPI_MR_DLYCS(n) (((n) << 24) & QSPI_MR_DLYCS_MASK)
+
+/* Bitfields in QSPI_SR/QSPI_IER/QSPI_IDR/QSPI_IMR */
+#define QSPI_SR_RDRF BIT(0)
+#define QSPI_SR_TDRE BIT(1)
+#define QSPI_SR_TXEMPTY BIT(2)
+#define QSPI_SR_OVRES BIT(3)
+#define QSPI_SR_CSR BIT(8)
+#define QSPI_SR_CSS BIT(9)
+#define QSPI_SR_INSTRE BIT(10)
+#define QSPI_SR_QSPIENS BIT(24)
+
+#define QSPI_SR_CMD_COMPLETED (QSPI_SR_INSTRE | QSPI_SR_CSR)
+
+/* Bitfields in QSPI_SCR (Serial Clock Register) */
+#define QSPI_SCR_CPOL BIT(0)
+#define QSPI_SCR_CPHA BIT(1)
+#define QSPI_SCR_SCBR_MASK GENMASK(15, 8)
+#define QSPI_SCR_SCBR(n) (((n) << 8) & QSPI_SCR_SCBR_MASK)
+#define QSPI_SCR_DLYBS_MASK GENMASK(23, 16)
+#define QSPI_SCR_DLYBS(n) (((n) << 16) & QSPI_SCR_DLYBS_MASK)
+
+/* Bitfields in QSPI_ICR (Read/Write Instruction Code Register) */
+#define QSPI_ICR_INST_MASK GENMASK(7, 0)
+#define QSPI_ICR_INST(inst) (((inst) << 0) & QSPI_ICR_INST_MASK)
+#define QSPI_ICR_OPT_MASK GENMASK(23, 16)
+#define QSPI_ICR_OPT(opt) (((opt) << 16) & QSPI_ICR_OPT_MASK)
+
+/* Bitfields in QSPI_IFR (Instruction Frame Register) */
+#define QSPI_IFR_WIDTH_MASK GENMASK(2, 0)
+#define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0 << 0)
+#define QSPI_IFR_WIDTH_DUAL_OUTPUT (1 << 0)
+#define QSPI_IFR_WIDTH_QUAD_OUTPUT (2 << 0)
+#define QSPI_IFR_WIDTH_DUAL_IO (3 << 0)
+#define QSPI_IFR_WIDTH_QUAD_IO (4 << 0)
+#define QSPI_IFR_WIDTH_DUAL_CMD (5 << 0)
+#define QSPI_IFR_WIDTH_QUAD_CMD (6 << 0)
+#define QSPI_IFR_INSTEN BIT(4)
+#define QSPI_IFR_ADDREN BIT(5)
+#define QSPI_IFR_OPTEN BIT(6)
+#define QSPI_IFR_DATAEN BIT(7)
+#define QSPI_IFR_OPTL_MASK GENMASK(9, 8)
+#define QSPI_IFR_OPTL_1BIT (0 << 8)
+#define QSPI_IFR_OPTL_2BIT (1 << 8)
+#define QSPI_IFR_OPTL_4BIT (2 << 8)
+#define QSPI_IFR_OPTL_8BIT (3 << 8)
+#define QSPI_IFR_ADDRL BIT(10)
+#define QSPI_IFR_TFRTYP_MEM BIT(12)
+#define QSPI_IFR_SAMA5D2_WRITE_TRSFR BIT(13)
+#define QSPI_IFR_CRM BIT(14)
+#define QSPI_IFR_NBDUM_MASK GENMASK(20, 16)
+#define QSPI_IFR_NBDUM(n) (((n) << 16) & QSPI_IFR_NBDUM_MASK)
+#define QSPI_IFR_APBTFRTYP_READ BIT(24) /* Defined in SAM9X60 */
+
+/* Bitfields in QSPI_SMR (Scrambling Mode Register) */
+#define QSPI_SMR_SCREN BIT(0)
+#define QSPI_SMR_RVDIS BIT(1)
+
+/* Bitfields in QSPI_WPMR (Write Protection Mode Register) */
+#define QSPI_WPMR_WPEN BIT(0)
+#define QSPI_WPMR_WPKEY_MASK GENMASK(31, 8)
+#define QSPI_WPMR_WPKEY(wpkey) (((wpkey) << 8) & QSPI_WPMR_WPKEY_MASK)
+
+/* Bitfields in QSPI_WPSR (Write Protection Status Register) */
+#define QSPI_WPSR_WPVS BIT(0)
+#define QSPI_WPSR_WPVSRC_MASK GENMASK(15, 8)
+#define QSPI_WPSR_WPVSRC(src) (((src) << 8) & QSPI_WPSR_WPVSRC)
+
+struct atmel_qspi_caps {
+ bool has_qspick;
+ bool has_ricr;
+};
+
+struct atmel_qspi {
+ void __iomem *regs;
+ void __iomem *mem;
+ struct platform_device *pdev;
+ const struct atmel_qspi_caps *caps;
+ ulong bus_clk_rate;
+ u32 mr;
+};
+
+struct atmel_qspi_mode {
+ u8 cmd_buswidth;
+ u8 addr_buswidth;
+ u8 data_buswidth;
+ u32 config;
+};
+
+static const struct atmel_qspi_mode atmel_qspi_modes[] = {
+ { 1, 1, 1, QSPI_IFR_WIDTH_SINGLE_BIT_SPI },
+ { 1, 1, 2, QSPI_IFR_WIDTH_DUAL_OUTPUT },
+ { 1, 1, 4, QSPI_IFR_WIDTH_QUAD_OUTPUT },
+ { 1, 2, 2, QSPI_IFR_WIDTH_DUAL_IO },
+ { 1, 4, 4, QSPI_IFR_WIDTH_QUAD_IO },
+ { 2, 2, 2, QSPI_IFR_WIDTH_DUAL_CMD },
+ { 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD },
+};
+
+static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op,
+ const struct atmel_qspi_mode *mode)
+{
+ if (op->cmd.buswidth != mode->cmd_buswidth)
+ return false;
+
+ if (op->addr.nbytes && op->addr.buswidth != mode->addr_buswidth)
+ return false;
+
+ if (op->data.nbytes && op->data.buswidth != mode->data_buswidth)
+ return false;
+
+ return true;
+}
+
+static int atmel_qspi_find_mode(const struct spi_mem_op *op)
+{
+ u32 i;
+
+ for (i = 0; i < ARRAY_SIZE(atmel_qspi_modes); i++)
+ if (atmel_qspi_is_compatible(op, &atmel_qspi_modes[i]))
+ return i;
+
+ return -ENOTSUPP;
+}
+
+static bool atmel_qspi_supports_op(struct spi_slave *slave,
+ const struct spi_mem_op *op)
+{
+ if (atmel_qspi_find_mode(op) < 0)
+ return false;
+
+ /* special case not supported by hardware */
+ if (op->addr.nbytes == 2 && op->cmd.buswidth != op->addr.buswidth &&
+ op->dummy.nbytes == 0)
+ return false;
+
+ return true;
+}
+
+static int atmel_qspi_set_cfg(struct atmel_qspi *aq,
+ const struct spi_mem_op *op, u32 *offset)
+{
+ u32 iar, icr, ifr;
+ u32 dummy_cycles = 0;
+ int mode;
+
+ iar = 0;
+ icr = QSPI_ICR_INST(op->cmd.opcode);
+ ifr = QSPI_IFR_INSTEN;
+
+ mode = atmel_qspi_find_mode(op);
+ if (mode < 0)
+ return mode;
+ ifr |= atmel_qspi_modes[mode].config;
+
+ if (op->dummy.buswidth && op->dummy.nbytes)
+ dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;
+
+ /*
+ * The controller allows 24 and 32-bit addressing while NAND-flash
+ * requires 16-bit long. Handling 8-bit long addresses is done using
+ * the option field. For the 16-bit addresses, the workaround depends
+ * of the number of requested dummy bits. If there are 8 or more dummy
+ * cycles, the address is shifted and sent with the first dummy byte.
+ * Otherwise opcode is disabled and the first byte of the address
+ * contains the command opcode (works only if the opcode and address
+ * use the same buswidth). The limitation is when the 16-bit address is
+ * used without enough dummy cycles and the opcode is using a different
+ * buswidth than the address.
+ */
+ if (op->addr.buswidth) {
+ switch (op->addr.nbytes) {
+ case 0:
+ break;
+ case 1:
+ ifr |= QSPI_IFR_OPTEN | QSPI_IFR_OPTL_8BIT;
+ icr |= QSPI_ICR_OPT(op->addr.val & 0xff);
+ break;
+ case 2:
+ if (dummy_cycles < 8 / op->addr.buswidth) {
+ ifr &= ~QSPI_IFR_INSTEN;
+ ifr |= QSPI_IFR_ADDREN;
+ iar = (op->cmd.opcode << 16) |
+ (op->addr.val & 0xffff);
+ } else {
+ ifr |= QSPI_IFR_ADDREN;
+ iar = (op->addr.val << 8) & 0xffffff;
+ dummy_cycles -= 8 / op->addr.buswidth;
+ }
+ break;
+ case 3:
+ ifr |= QSPI_IFR_ADDREN;
+ iar = op->addr.val & 0xffffff;
+ break;
+ case 4:
+ ifr |= QSPI_IFR_ADDREN | QSPI_IFR_ADDRL;
+ iar = op->addr.val & 0x7ffffff;
+ break;
+ default:
+ return -ENOTSUPP;
+ }
+ }
+
+ /* offset of the data access in the QSPI memory space */
+ *offset = iar;
+
+ /* Set number of dummy cycles */
+ if (dummy_cycles)
+ ifr |= QSPI_IFR_NBDUM(dummy_cycles);
+
+ /* Set data enable */
+ if (op->data.nbytes)
+ ifr |= QSPI_IFR_DATAEN;
+
+ /*
+ * If the QSPI controller is set in regular SPI mode, set it in
+ * Serial Memory Mode (SMM).
+ */
+ if (aq->mr != QSPI_MR_SMM) {
+ writel(QSPI_MR_SMM, aq->regs + QSPI_MR);
+ aq->mr = QSPI_MR_SMM;
+ }
+
+ /* Clear pending interrupts */
+ (void)readl(aq->regs + QSPI_SR);
+
+ if (aq->caps->has_ricr) {
+ if (!op->addr.nbytes && op->data.dir == SPI_MEM_DATA_IN)
+ ifr |= QSPI_IFR_APBTFRTYP_READ;
+
+ /* Set QSPI Instruction Frame registers */
+ writel(iar, aq->regs + QSPI_IAR);
+ if (op->data.dir == SPI_MEM_DATA_IN)
+ writel(icr, aq->regs + QSPI_RICR);
+ else
+ writel(icr, aq->regs + QSPI_WICR);
+ writel(ifr, aq->regs + QSPI_IFR);
+ } else {
+ if (op->data.dir == SPI_MEM_DATA_OUT)
+ ifr |= QSPI_IFR_SAMA5D2_WRITE_TRSFR;
+
+ /* Set QSPI Instruction Frame registers */
+ writel(iar, aq->regs + QSPI_IAR);
+ writel(icr, aq->regs + QSPI_ICR);
+ writel(ifr, aq->regs + QSPI_IFR);
+ }
+
+ return 0;
+}
+
+static int atmel_qspi_exec_op(struct spi_slave *slave,
+ const struct spi_mem_op *op)
+{
+ struct atmel_qspi *aq = dev_get_priv(slave->dev->parent);
+ u32 sr, imr, offset;
+ int err;
+
+ err = atmel_qspi_set_cfg(aq, op, &offset);
+ if (err)
+ return err;
+
+ /* Skip to the final steps if there is no data */
+ if (op->data.nbytes) {
+ /* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */
+ (void)readl(aq->regs + QSPI_IFR);
+
+ /* Send/Receive data */
+ if (op->data.dir == SPI_MEM_DATA_IN)
+ memcpy_fromio(op->data.buf.in, aq->mem + offset,
+ op->data.nbytes);
+ else
+ memcpy_toio(aq->mem + offset, op->data.buf.out,
+ op->data.nbytes);
+
+ /* Release the chip-select */
+ writel(QSPI_CR_LASTXFER, aq->regs + QSPI_CR);
+ }
+
+ /* Poll INSTruction End and Chip Select Rise flags. */
+ imr = QSPI_SR_INSTRE | QSPI_SR_CSR;
+ return readl_poll_timeout(aq->regs + QSPI_SR, sr, (sr & imr) == imr,
+ 1000000);
+}
+
+static int atmel_qspi_set_speed(struct udevice *bus, uint hz)
+{
+ struct atmel_qspi *aq = dev_get_priv(bus);
+ u32 scr, scbr, mask, new_value;
+
+ /* Compute the QSPI baudrate */
+ scbr = DIV_ROUND_UP(aq->bus_clk_rate, hz);
+ if (scbr > 0)
+ scbr--;
+
+ new_value = QSPI_SCR_SCBR(scbr);
+ mask = QSPI_SCR_SCBR_MASK;
+
+ scr = readl(aq->regs + QSPI_SCR);
+ if ((scr & mask) == new_value)
+ return 0;
+
+ scr = (scr & ~mask) | new_value;
+ writel(scr, aq->regs + QSPI_SCR);
+
+ return 0;
+}
+
+static int atmel_qspi_set_mode(struct udevice *bus, uint mode)
+{
+ struct atmel_qspi *aq = dev_get_priv(bus);
+ u32 scr, mask, new_value = 0;
+
+ if (mode & SPI_CPOL)
+ new_value = QSPI_SCR_CPOL;
+ if (mode & SPI_CPHA)
+ new_value = QSPI_SCR_CPHA;
+
+ mask = QSPI_SCR_CPOL | QSPI_SCR_CPHA;
+
+ scr = readl(aq->regs + QSPI_SCR);
+ if ((scr & mask) == new_value)
+ return 0;
+
+ scr = (scr & ~mask) | new_value;
+ writel(scr, aq->regs + QSPI_SCR);
+
+ return 0;
+}
+
+static int atmel_qspi_enable_clk(struct udevice *dev)
+{
+ struct atmel_qspi *aq = dev_get_priv(dev);
+ struct clk pclk, qspick;
+ int ret;
+
+ ret = clk_get_by_name(dev, "pclk", &pclk);
+ if (ret)
+ ret = clk_get_by_index(dev, 0, &pclk);
+
+ if (ret) {
+ dev_err(dev, "Missing QSPI peripheral clock\n");
+ return ret;
+ }
+
+ ret = clk_enable(&pclk);
+ if (ret) {
+ dev_err(dev, "Failed to enable QSPI peripheral clock\n");
+ goto free_pclk;
+ }
+
+ if (aq->caps->has_qspick) {
+ /* Get the QSPI system clock */
+ ret = clk_get_by_name(dev, "qspick", &qspick);
+ if (ret) {
+ dev_err(dev, "Missing QSPI peripheral clock\n");
+ goto free_pclk;
+ }
+
+ ret = clk_enable(&qspick);
+ if (ret)
+ dev_err(dev, "Failed to enable QSPI system clock\n");
+ clk_free(&qspick);
+ }
+
+ aq->bus_clk_rate = clk_get_rate(&pclk);
+ if (!aq->bus_clk_rate)
+ ret = -EINVAL;
+
+free_pclk:
+ clk_free(&pclk);
+
+ return ret;
+}
+
+static void atmel_qspi_init(struct atmel_qspi *aq)
+{
+ /* Reset the QSPI controller */
+ writel(QSPI_CR_SWRST, aq->regs + QSPI_CR);
+
+ /* Set the QSPI controller by default in Serial Memory Mode */
+ writel(QSPI_MR_SMM, aq->regs + QSPI_MR);
+ aq->mr = QSPI_MR_SMM;
+
+ /* Enable the QSPI controller */
+ writel(QSPI_CR_QSPIEN, aq->regs + QSPI_CR);
+}
+
+static int atmel_qspi_probe(struct udevice *dev)
+{
+ struct atmel_qspi *aq = dev_get_priv(dev);
+ struct resource res;
+ int ret;
+
+ aq->caps = (struct atmel_qspi_caps *)dev_get_driver_data(dev);
+ if (!aq->caps) {
+ dev_err(dev, "Could not retrieve QSPI caps\n");
+ return -EINVAL;
+ };
+
+ /* Map the registers */
+ ret = dev_read_resource_byname(dev, "qspi_base", &res);
+ if (ret) {
+ dev_err(dev, "missing registers\n");
+ return ret;
+ }
+ aq->regs = devm_ioremap(dev, res.start, resource_size(&res));
+ if (IS_ERR(aq->regs))
+ return PTR_ERR(aq->regs);
+
+ /* Map the AHB memory */
+ ret = dev_read_resource_byname(dev, "qspi_mmap", &res);
+ if (ret) {
+ dev_err(dev, "missing AHB memory\n");
+ return ret;
+ }
+ aq->mem = devm_ioremap(dev, res.start, resource_size(&res));
+ if (IS_ERR(aq->mem))
+ return PTR_ERR(aq->mem);
+
+ ret = atmel_qspi_enable_clk(dev);
+ if (ret)
+ return ret;
+
+ atmel_qspi_init(aq);
+
+ return 0;
+}
+
+static const struct spi_controller_mem_ops atmel_qspi_mem_ops = {
+ .supports_op = atmel_qspi_supports_op,
+ .exec_op = atmel_qspi_exec_op,
+};
+
+static const struct dm_spi_ops atmel_qspi_ops = {
+ .set_speed = atmel_qspi_set_speed,
+ .set_mode = atmel_qspi_set_mode,
+ .mem_ops = &atmel_qspi_mem_ops,
+};
+
+static const struct atmel_qspi_caps atmel_sama5d2_qspi_caps = {};
+
+static const struct atmel_qspi_caps atmel_sam9x60_qspi_caps = {
+ .has_qspick = true,
+ .has_ricr = true,
+};
+
+static const struct udevice_id atmel_qspi_ids[] = {
+ {
+ .compatible = "atmel,sama5d2-qspi",
+ .data = (ulong)&atmel_sama5d2_qspi_caps,
+ },
+ {
+ .compatible = "microchip,sam9x60-qspi",
+ .data = (ulong)&atmel_sam9x60_qspi_caps,
+ },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(atmel_qspi) = {
+ .name = "atmel_qspi",
+ .id = UCLASS_SPI,
+ .of_match = atmel_qspi_ids,
+ .ops = &atmel_qspi_ops,
+ .priv_auto_alloc_size = sizeof(struct atmel_qspi),
+ .probe = atmel_qspi_probe,
+};
--
2.9.5
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH v4 02/10] spi: Add Atmel QuadSPI driver
2019-05-15 7:01 ` [U-Boot] [PATCH v4 " Tudor.Ambarus at microchip.com
@ 2019-06-12 8:02 ` Jagan Teki
2019-06-14 8:12 ` Tudor.Ambarus at microchip.com
0 siblings, 1 reply; 15+ messages in thread
From: Jagan Teki @ 2019-06-12 8:02 UTC (permalink / raw)
To: u-boot
On Wed, May 15, 2019 at 12:33 PM <Tudor.Ambarus@microchip.com> wrote:
>
> From: Tudor Ambarus <tudor.ambarus@microchip.com>
>
> Backport the driver from linux v5.1-rc5 and adapt it for u-boot.
> Tested on sama5d2_xplained Rev B with mx25l25635e spi-nor flash.
>
> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
> ---
> v4: update Kconfig description
> v3: no change
> v2: no change
>
> drivers/spi/Kconfig | 8 +
> drivers/spi/Makefile | 1 +
> drivers/spi/atmel-quadspi.c | 535 ++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 544 insertions(+)
> create mode 100644 drivers/spi/atmel-quadspi.c
>
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index dc3e23f353aa..0b87c155b87a 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -49,6 +49,14 @@ config ATH79_SPI
> uses driver model and requires a device tree binding to operate.
> please refer to doc/device-tree-bindings/spi/spi-ath79.txt.
>
> +config ATMEL_QSPI
> + bool "Atmel Quad SPI Controller"
> + depends on ARCH_AT91
> + help
> + Enable the Atmel Quad SPI controller in master mode. This driver
> + does not support generic SPI. The implementation supports only the
> + spi-mem interface.
> +
> config ATMEL_SPI
> bool "Atmel SPI driver"
> default y if ARCH_AT91
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index 8be9a4baa244..32b42d18b1af 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -18,6 +18,7 @@ endif
>
> obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
> obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
> +obj-$(CONFIG_ATMEL_QSPI) += atmel-quadspi.o
> obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
> obj-$(CONFIG_BCM63XX_HSSPI) += bcm63xx_hsspi.o
> obj-$(CONFIG_BCM63XX_SPI) += bcm63xx_spi.o
> diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c
> new file mode 100644
> index 000000000000..c54fbe6bc6cf
> --- /dev/null
> +++ b/drivers/spi/atmel-quadspi.c
> @@ -0,0 +1,535 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Driver for Atmel QSPI Controller
> + *
> + * Copyright (C) 2015 Atmel Corporation
> + * Copyright (C) 2018 Cryptera A/S
> + *
> + * Author: Cyrille Pitchen <cyrille.pitchen@atmel.com>
> + * Author: Piotr Bugalski <bugalski.piotr@gmail.com>
> + */
> +
> +#include <asm/io.h>
> +#include <clk.h>
> +#include <common.h>
> +#include <dm.h>
> +#include <errno.h>
> +#include <fdtdec.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/ioport.h>
> +#include <mach/clk.h>
> +#include <spi.h>
> +#include <spi-mem.h>
> +
> +/* QSPI register offsets */
> +#define QSPI_CR 0x0000 /* Control Register */
> +#define QSPI_MR 0x0004 /* Mode Register */
> +#define QSPI_RD 0x0008 /* Receive Data Register */
> +#define QSPI_TD 0x000c /* Transmit Data Register */
> +#define QSPI_SR 0x0010 /* Status Register */
> +#define QSPI_IER 0x0014 /* Interrupt Enable Register */
> +#define QSPI_IDR 0x0018 /* Interrupt Disable Register */
> +#define QSPI_IMR 0x001c /* Interrupt Mask Register */
> +#define QSPI_SCR 0x0020 /* Serial Clock Register */
> +
> +#define QSPI_IAR 0x0030 /* Instruction Address Register */
> +#define QSPI_ICR 0x0034 /* Instruction Code Register */
> +#define QSPI_WICR 0x0034 /* Write Instruction Code Register */
> +#define QSPI_IFR 0x0038 /* Instruction Frame Register */
> +#define QSPI_RICR 0x003C /* Read Instruction Code Register */
> +
> +#define QSPI_SMR 0x0040 /* Scrambling Mode Register */
> +#define QSPI_SKR 0x0044 /* Scrambling Key Register */
> +
> +#define QSPI_WPMR 0x00E4 /* Write Protection Mode Register */
> +#define QSPI_WPSR 0x00E8 /* Write Protection Status Register */
> +
> +#define QSPI_VERSION 0x00FC /* Version Register */
> +
> +/* Bitfields in QSPI_CR (Control Register) */
> +#define QSPI_CR_QSPIEN BIT(0)
> +#define QSPI_CR_QSPIDIS BIT(1)
> +#define QSPI_CR_SWRST BIT(7)
> +#define QSPI_CR_LASTXFER BIT(24)
> +
> +/* Bitfields in QSPI_MR (Mode Register) */
> +#define QSPI_MR_SMM BIT(0)
> +#define QSPI_MR_LLB BIT(1)
> +#define QSPI_MR_WDRBT BIT(2)
> +#define QSPI_MR_SMRM BIT(3)
> +#define QSPI_MR_CSMODE_MASK GENMASK(5, 4)
> +#define QSPI_MR_CSMODE_NOT_RELOADED (0 << 4)
> +#define QSPI_MR_CSMODE_LASTXFER (1 << 4)
> +#define QSPI_MR_CSMODE_SYSTEMATICALLY (2 << 4)
> +#define QSPI_MR_NBBITS_MASK GENMASK(11, 8)
> +#define QSPI_MR_NBBITS(n) ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK)
> +#define QSPI_MR_DLYBCT_MASK GENMASK(23, 16)
> +#define QSPI_MR_DLYBCT(n) (((n) << 16) & QSPI_MR_DLYBCT_MASK)
> +#define QSPI_MR_DLYCS_MASK GENMASK(31, 24)
> +#define QSPI_MR_DLYCS(n) (((n) << 24) & QSPI_MR_DLYCS_MASK)
> +
> +/* Bitfields in QSPI_SR/QSPI_IER/QSPI_IDR/QSPI_IMR */
> +#define QSPI_SR_RDRF BIT(0)
> +#define QSPI_SR_TDRE BIT(1)
> +#define QSPI_SR_TXEMPTY BIT(2)
> +#define QSPI_SR_OVRES BIT(3)
> +#define QSPI_SR_CSR BIT(8)
> +#define QSPI_SR_CSS BIT(9)
> +#define QSPI_SR_INSTRE BIT(10)
> +#define QSPI_SR_QSPIENS BIT(24)
> +
> +#define QSPI_SR_CMD_COMPLETED (QSPI_SR_INSTRE | QSPI_SR_CSR)
> +
> +/* Bitfields in QSPI_SCR (Serial Clock Register) */
> +#define QSPI_SCR_CPOL BIT(0)
> +#define QSPI_SCR_CPHA BIT(1)
> +#define QSPI_SCR_SCBR_MASK GENMASK(15, 8)
> +#define QSPI_SCR_SCBR(n) (((n) << 8) & QSPI_SCR_SCBR_MASK)
> +#define QSPI_SCR_DLYBS_MASK GENMASK(23, 16)
> +#define QSPI_SCR_DLYBS(n) (((n) << 16) & QSPI_SCR_DLYBS_MASK)
> +
> +/* Bitfields in QSPI_ICR (Read/Write Instruction Code Register) */
> +#define QSPI_ICR_INST_MASK GENMASK(7, 0)
> +#define QSPI_ICR_INST(inst) (((inst) << 0) & QSPI_ICR_INST_MASK)
> +#define QSPI_ICR_OPT_MASK GENMASK(23, 16)
> +#define QSPI_ICR_OPT(opt) (((opt) << 16) & QSPI_ICR_OPT_MASK)
> +
> +/* Bitfields in QSPI_IFR (Instruction Frame Register) */
> +#define QSPI_IFR_WIDTH_MASK GENMASK(2, 0)
> +#define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0 << 0)
> +#define QSPI_IFR_WIDTH_DUAL_OUTPUT (1 << 0)
> +#define QSPI_IFR_WIDTH_QUAD_OUTPUT (2 << 0)
> +#define QSPI_IFR_WIDTH_DUAL_IO (3 << 0)
> +#define QSPI_IFR_WIDTH_QUAD_IO (4 << 0)
> +#define QSPI_IFR_WIDTH_DUAL_CMD (5 << 0)
> +#define QSPI_IFR_WIDTH_QUAD_CMD (6 << 0)
> +#define QSPI_IFR_INSTEN BIT(4)
> +#define QSPI_IFR_ADDREN BIT(5)
> +#define QSPI_IFR_OPTEN BIT(6)
> +#define QSPI_IFR_DATAEN BIT(7)
> +#define QSPI_IFR_OPTL_MASK GENMASK(9, 8)
> +#define QSPI_IFR_OPTL_1BIT (0 << 8)
> +#define QSPI_IFR_OPTL_2BIT (1 << 8)
> +#define QSPI_IFR_OPTL_4BIT (2 << 8)
> +#define QSPI_IFR_OPTL_8BIT (3 << 8)
> +#define QSPI_IFR_ADDRL BIT(10)
> +#define QSPI_IFR_TFRTYP_MEM BIT(12)
> +#define QSPI_IFR_SAMA5D2_WRITE_TRSFR BIT(13)
> +#define QSPI_IFR_CRM BIT(14)
> +#define QSPI_IFR_NBDUM_MASK GENMASK(20, 16)
> +#define QSPI_IFR_NBDUM(n) (((n) << 16) & QSPI_IFR_NBDUM_MASK)
> +#define QSPI_IFR_APBTFRTYP_READ BIT(24) /* Defined in SAM9X60 */
> +
> +/* Bitfields in QSPI_SMR (Scrambling Mode Register) */
> +#define QSPI_SMR_SCREN BIT(0)
> +#define QSPI_SMR_RVDIS BIT(1)
> +
> +/* Bitfields in QSPI_WPMR (Write Protection Mode Register) */
> +#define QSPI_WPMR_WPEN BIT(0)
> +#define QSPI_WPMR_WPKEY_MASK GENMASK(31, 8)
> +#define QSPI_WPMR_WPKEY(wpkey) (((wpkey) << 8) & QSPI_WPMR_WPKEY_MASK)
> +
> +/* Bitfields in QSPI_WPSR (Write Protection Status Register) */
> +#define QSPI_WPSR_WPVS BIT(0)
> +#define QSPI_WPSR_WPVSRC_MASK GENMASK(15, 8)
> +#define QSPI_WPSR_WPVSRC(src) (((src) << 8) & QSPI_WPSR_WPVSRC)
> +
> +struct atmel_qspi_caps {
> + bool has_qspick;
> + bool has_ricr;
> +};
> +
> +struct atmel_qspi {
> + void __iomem *regs;
> + void __iomem *mem;
> + struct platform_device *pdev;
Linux copy, please drop this.
> + const struct atmel_qspi_caps *caps;
> + ulong bus_clk_rate;
> + u32 mr;
> +};
> +
> +struct atmel_qspi_mode {
> + u8 cmd_buswidth;
> + u8 addr_buswidth;
> + u8 data_buswidth;
> + u32 config;
> +};
> +
> +static const struct atmel_qspi_mode atmel_qspi_modes[] = {
> + { 1, 1, 1, QSPI_IFR_WIDTH_SINGLE_BIT_SPI },
> + { 1, 1, 2, QSPI_IFR_WIDTH_DUAL_OUTPUT },
> + { 1, 1, 4, QSPI_IFR_WIDTH_QUAD_OUTPUT },
> + { 1, 2, 2, QSPI_IFR_WIDTH_DUAL_IO },
> + { 1, 4, 4, QSPI_IFR_WIDTH_QUAD_IO },
> + { 2, 2, 2, QSPI_IFR_WIDTH_DUAL_CMD },
> + { 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD },
> +};
> +
> +static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op,
> + const struct atmel_qspi_mode *mode)
> +{
> + if (op->cmd.buswidth != mode->cmd_buswidth)
> + return false;
> +
> + if (op->addr.nbytes && op->addr.buswidth != mode->addr_buswidth)
> + return false;
> +
> + if (op->data.nbytes && op->data.buswidth != mode->data_buswidth)
> + return false;
> +
> + return true;
> +}
> +
> +static int atmel_qspi_find_mode(const struct spi_mem_op *op)
> +{
> + u32 i;
> +
> + for (i = 0; i < ARRAY_SIZE(atmel_qspi_modes); i++)
> + if (atmel_qspi_is_compatible(op, &atmel_qspi_modes[i]))
> + return i;
> +
> + return -ENOTSUPP;
> +}
> +
> +static bool atmel_qspi_supports_op(struct spi_slave *slave,
> + const struct spi_mem_op *op)
> +{
> + if (atmel_qspi_find_mode(op) < 0)
> + return false;
> +
> + /* special case not supported by hardware */
> + if (op->addr.nbytes == 2 && op->cmd.buswidth != op->addr.buswidth &&
> + op->dummy.nbytes == 0)
> + return false;
> +
> + return true;
> +}
> +
> +static int atmel_qspi_set_cfg(struct atmel_qspi *aq,
> + const struct spi_mem_op *op, u32 *offset)
> +{
> + u32 iar, icr, ifr;
> + u32 dummy_cycles = 0;
> + int mode;
> +
> + iar = 0;
> + icr = QSPI_ICR_INST(op->cmd.opcode);
> + ifr = QSPI_IFR_INSTEN;
> +
> + mode = atmel_qspi_find_mode(op);
> + if (mode < 0)
> + return mode;
> + ifr |= atmel_qspi_modes[mode].config;
> +
> + if (op->dummy.buswidth && op->dummy.nbytes)
> + dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;
> +
> + /*
> + * The controller allows 24 and 32-bit addressing while NAND-flash
> + * requires 16-bit long. Handling 8-bit long addresses is done using
> + * the option field. For the 16-bit addresses, the workaround depends
> + * of the number of requested dummy bits. If there are 8 or more dummy
> + * cycles, the address is shifted and sent with the first dummy byte.
> + * Otherwise opcode is disabled and the first byte of the address
> + * contains the command opcode (works only if the opcode and address
> + * use the same buswidth). The limitation is when the 16-bit address is
> + * used without enough dummy cycles and the opcode is using a different
> + * buswidth than the address.
> + */
> + if (op->addr.buswidth) {
> + switch (op->addr.nbytes) {
> + case 0:
> + break;
> + case 1:
> + ifr |= QSPI_IFR_OPTEN | QSPI_IFR_OPTL_8BIT;
> + icr |= QSPI_ICR_OPT(op->addr.val & 0xff);
> + break;
> + case 2:
> + if (dummy_cycles < 8 / op->addr.buswidth) {
> + ifr &= ~QSPI_IFR_INSTEN;
> + ifr |= QSPI_IFR_ADDREN;
> + iar = (op->cmd.opcode << 16) |
> + (op->addr.val & 0xffff);
> + } else {
> + ifr |= QSPI_IFR_ADDREN;
> + iar = (op->addr.val << 8) & 0xffffff;
> + dummy_cycles -= 8 / op->addr.buswidth;
> + }
> + break;
> + case 3:
> + ifr |= QSPI_IFR_ADDREN;
> + iar = op->addr.val & 0xffffff;
> + break;
> + case 4:
> + ifr |= QSPI_IFR_ADDREN | QSPI_IFR_ADDRL;
> + iar = op->addr.val & 0x7ffffff;
> + break;
> + default:
> + return -ENOTSUPP;
> + }
> + }
> +
> + /* offset of the data access in the QSPI memory space */
> + *offset = iar;
> +
> + /* Set number of dummy cycles */
> + if (dummy_cycles)
> + ifr |= QSPI_IFR_NBDUM(dummy_cycles);
> +
> + /* Set data enable */
> + if (op->data.nbytes)
> + ifr |= QSPI_IFR_DATAEN;
> +
> + /*
> + * If the QSPI controller is set in regular SPI mode, set it in
> + * Serial Memory Mode (SMM).
> + */
> + if (aq->mr != QSPI_MR_SMM) {
> + writel(QSPI_MR_SMM, aq->regs + QSPI_MR);
> + aq->mr = QSPI_MR_SMM;
> + }
> +
> + /* Clear pending interrupts */
> + (void)readl(aq->regs + QSPI_SR);
> +
> + if (aq->caps->has_ricr) {
> + if (!op->addr.nbytes && op->data.dir == SPI_MEM_DATA_IN)
> + ifr |= QSPI_IFR_APBTFRTYP_READ;
> +
> + /* Set QSPI Instruction Frame registers */
> + writel(iar, aq->regs + QSPI_IAR);
> + if (op->data.dir == SPI_MEM_DATA_IN)
> + writel(icr, aq->regs + QSPI_RICR);
> + else
> + writel(icr, aq->regs + QSPI_WICR);
> + writel(ifr, aq->regs + QSPI_IFR);
> + } else {
> + if (op->data.dir == SPI_MEM_DATA_OUT)
> + ifr |= QSPI_IFR_SAMA5D2_WRITE_TRSFR;
> +
> + /* Set QSPI Instruction Frame registers */
> + writel(iar, aq->regs + QSPI_IAR);
> + writel(icr, aq->regs + QSPI_ICR);
> + writel(ifr, aq->regs + QSPI_IFR);
> + }
> +
> + return 0;
> +}
> +
> +static int atmel_qspi_exec_op(struct spi_slave *slave,
> + const struct spi_mem_op *op)
> +{
> + struct atmel_qspi *aq = dev_get_priv(slave->dev->parent);
> + u32 sr, imr, offset;
> + int err;
> +
> + err = atmel_qspi_set_cfg(aq, op, &offset);
> + if (err)
> + return err;
> +
> + /* Skip to the final steps if there is no data */
> + if (op->data.nbytes) {
> + /* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */
> + (void)readl(aq->regs + QSPI_IFR);
> +
> + /* Send/Receive data */
> + if (op->data.dir == SPI_MEM_DATA_IN)
> + memcpy_fromio(op->data.buf.in, aq->mem + offset,
> + op->data.nbytes);
> + else
> + memcpy_toio(aq->mem + offset, op->data.buf.out,
> + op->data.nbytes);
> +
> + /* Release the chip-select */
> + writel(QSPI_CR_LASTXFER, aq->regs + QSPI_CR);
> + }
> +
> + /* Poll INSTruction End and Chip Select Rise flags. */
> + imr = QSPI_SR_INSTRE | QSPI_SR_CSR;
> + return readl_poll_timeout(aq->regs + QSPI_SR, sr, (sr & imr) == imr,
> + 1000000);
> +}
> +
> +static int atmel_qspi_set_speed(struct udevice *bus, uint hz)
> +{
> + struct atmel_qspi *aq = dev_get_priv(bus);
> + u32 scr, scbr, mask, new_value;
> +
> + /* Compute the QSPI baudrate */
> + scbr = DIV_ROUND_UP(aq->bus_clk_rate, hz);
> + if (scbr > 0)
> + scbr--;
> +
> + new_value = QSPI_SCR_SCBR(scbr);
> + mask = QSPI_SCR_SCBR_MASK;
> +
> + scr = readl(aq->regs + QSPI_SCR);
> + if ((scr & mask) == new_value)
> + return 0;
> +
> + scr = (scr & ~mask) | new_value;
> + writel(scr, aq->regs + QSPI_SCR);
> +
> + return 0;
> +}
> +
> +static int atmel_qspi_set_mode(struct udevice *bus, uint mode)
> +{
> + struct atmel_qspi *aq = dev_get_priv(bus);
> + u32 scr, mask, new_value = 0;
> +
> + if (mode & SPI_CPOL)
> + new_value = QSPI_SCR_CPOL;
> + if (mode & SPI_CPHA)
> + new_value = QSPI_SCR_CPHA;
> +
> + mask = QSPI_SCR_CPOL | QSPI_SCR_CPHA;
> +
> + scr = readl(aq->regs + QSPI_SCR);
> + if ((scr & mask) == new_value)
> + return 0;
> +
> + scr = (scr & ~mask) | new_value;
> + writel(scr, aq->regs + QSPI_SCR);
> +
> + return 0;
> +}
> +
> +static int atmel_qspi_enable_clk(struct udevice *dev)
> +{
> + struct atmel_qspi *aq = dev_get_priv(dev);
> + struct clk pclk, qspick;
> + int ret;
> +
> + ret = clk_get_by_name(dev, "pclk", &pclk);
> + if (ret)
> + ret = clk_get_by_index(dev, 0, &pclk);
> +
> + if (ret) {
> + dev_err(dev, "Missing QSPI peripheral clock\n");
> + return ret;
> + }
> +
> + ret = clk_enable(&pclk);
> + if (ret) {
> + dev_err(dev, "Failed to enable QSPI peripheral clock\n");
> + goto free_pclk;
> + }
> +
> + if (aq->caps->has_qspick) {
> + /* Get the QSPI system clock */
> + ret = clk_get_by_name(dev, "qspick", &qspick);
> + if (ret) {
> + dev_err(dev, "Missing QSPI peripheral clock\n");
> + goto free_pclk;
> + }
> +
> + ret = clk_enable(&qspick);
> + if (ret)
> + dev_err(dev, "Failed to enable QSPI system clock\n");
> + clk_free(&qspick);
> + }
> +
> + aq->bus_clk_rate = clk_get_rate(&pclk);
> + if (!aq->bus_clk_rate)
> + ret = -EINVAL;
> +
> +free_pclk:
> + clk_free(&pclk);
> +
> + return ret;
> +}
> +
> +static void atmel_qspi_init(struct atmel_qspi *aq)
> +{
> + /* Reset the QSPI controller */
> + writel(QSPI_CR_SWRST, aq->regs + QSPI_CR);
> +
> + /* Set the QSPI controller by default in Serial Memory Mode */
> + writel(QSPI_MR_SMM, aq->regs + QSPI_MR);
> + aq->mr = QSPI_MR_SMM;
> +
> + /* Enable the QSPI controller */
> + writel(QSPI_CR_QSPIEN, aq->regs + QSPI_CR);
> +}
> +
> +static int atmel_qspi_probe(struct udevice *dev)
> +{
> + struct atmel_qspi *aq = dev_get_priv(dev);
> + struct resource res;
> + int ret;
> +
> + aq->caps = (struct atmel_qspi_caps *)dev_get_driver_data(dev);
> + if (!aq->caps) {
> + dev_err(dev, "Could not retrieve QSPI caps\n");
> + return -EINVAL;
> + };
> +
> + /* Map the registers */
> + ret = dev_read_resource_byname(dev, "qspi_base", &res);
> + if (ret) {
> + dev_err(dev, "missing registers\n");
> + return ret;
> + }
space
> + aq->regs = devm_ioremap(dev, res.start, resource_size(&res));
> + if (IS_ERR(aq->regs))
> + return PTR_ERR(aq->regs);
> +
> + /* Map the AHB memory */
> + ret = dev_read_resource_byname(dev, "qspi_mmap", &res);
> + if (ret) {
> + dev_err(dev, "missing AHB memory\n");
> + return ret;
> + }
space
> + aq->mem = devm_ioremap(dev, res.start, resource_size(&res));
> + if (IS_ERR(aq->mem))
> + return PTR_ERR(aq->mem);
> +
> + ret = atmel_qspi_enable_clk(dev);
> + if (ret)
> + return ret;
> +
> + atmel_qspi_init(aq);
> +
> + return 0;
> +}
> +
> +static const struct spi_controller_mem_ops atmel_qspi_mem_ops = {
> + .supports_op = atmel_qspi_supports_op,
> + .exec_op = atmel_qspi_exec_op,
> +};
> +
> +static const struct dm_spi_ops atmel_qspi_ops = {
> + .set_speed = atmel_qspi_set_speed,
> + .set_mode = atmel_qspi_set_mode,
> + .mem_ops = &atmel_qspi_mem_ops,
> +};
> +
> +static const struct atmel_qspi_caps atmel_sama5d2_qspi_caps = {};
> +
> +static const struct atmel_qspi_caps atmel_sam9x60_qspi_caps = {
> + .has_qspick = true,
> + .has_ricr = true,
> +};
> +
> +static const struct udevice_id atmel_qspi_ids[] = {
> + {
> + .compatible = "atmel,sama5d2-qspi",
> + .data = (ulong)&atmel_sama5d2_qspi_caps,
Better assign NULL
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH v4 02/10] spi: Add Atmel QuadSPI driver
2019-06-12 8:02 ` Jagan Teki
@ 2019-06-14 8:12 ` Tudor.Ambarus at microchip.com
0 siblings, 0 replies; 15+ messages in thread
From: Tudor.Ambarus at microchip.com @ 2019-06-14 8:12 UTC (permalink / raw)
To: u-boot
Hi, Jagan,
On 06/12/2019 11:02 AM, Jagan Teki wrote:
> External E-Mail
>
>
> On Wed, May 15, 2019 at 12:33 PM <Tudor.Ambarus@microchip.com> wrote:
>>
>> From: Tudor Ambarus <tudor.ambarus@microchip.com>
>>
>> Backport the driver from linux v5.1-rc5 and adapt it for u-boot.
>> Tested on sama5d2_xplained Rev B with mx25l25635e spi-nor flash.
>>
>> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
>> ---
>> v4: update Kconfig description
>> v3: no change
>> v2: no change
>>
>> drivers/spi/Kconfig | 8 +
>> drivers/spi/Makefile | 1 +
>> drivers/spi/atmel-quadspi.c | 535 ++++++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 544 insertions(+)
>> create mode 100644 drivers/spi/atmel-quadspi.c
>>
cut
>> diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c
>> new file mode 100644
>> index 000000000000..c54fbe6bc6cf
>> --- /dev/null
>> +++ b/drivers/spi/atmel-quadspi.c
>> @@ -0,0 +1,535 @@
cut
>> +struct atmel_qspi {
>> + void __iomem *regs;
>> + void __iomem *mem;
>> + struct platform_device *pdev;
>
> Linux copy, please drop this.
>
will do
>> +static int atmel_qspi_probe(struct udevice *dev)
>> +{
>> + struct atmel_qspi *aq = dev_get_priv(dev);
>> + struct resource res;
>> + int ret;
>> +
>> + aq->caps = (struct atmel_qspi_caps *)dev_get_driver_data(dev);
>> + if (!aq->caps) {
>> + dev_err(dev, "Could not retrieve QSPI caps\n");
>> + return -EINVAL;
>> + };
>> +
>> + /* Map the registers */
>> + ret = dev_read_resource_byname(dev, "qspi_base", &res);
>> + if (ret) {
>> + dev_err(dev, "missing registers\n");
>> + return ret;
>> + }
>
> space
ok
>
>> + aq->regs = devm_ioremap(dev, res.start, resource_size(&res));
>> + if (IS_ERR(aq->regs))
>> + return PTR_ERR(aq->regs);
>> +
>> + /* Map the AHB memory */
>> + ret = dev_read_resource_byname(dev, "qspi_mmap", &res);
>> + if (ret) {
>> + dev_err(dev, "missing AHB memory\n");
>> + return ret;
>> + }
>
> space
ok
>
>> + aq->mem = devm_ioremap(dev, res.start, resource_size(&res));
>> + if (IS_ERR(aq->mem))
>> + return PTR_ERR(aq->mem);
>> +
>> + ret = atmel_qspi_enable_clk(dev);
>> + if (ret)
>> + return ret;
>> +
>> + atmel_qspi_init(aq);
>> +
>> + return 0;
>> +}
>> +
>> +static const struct spi_controller_mem_ops atmel_qspi_mem_ops = {
>> + .supports_op = atmel_qspi_supports_op,
>> + .exec_op = atmel_qspi_exec_op,
>> +};
>> +
>> +static const struct dm_spi_ops atmel_qspi_ops = {
>> + .set_speed = atmel_qspi_set_speed,
>> + .set_mode = atmel_qspi_set_mode,
>> + .mem_ops = &atmel_qspi_mem_ops,
>> +};
>> +
>> +static const struct atmel_qspi_caps atmel_sama5d2_qspi_caps = {};
>> +
>> +static const struct atmel_qspi_caps atmel_sam9x60_qspi_caps = {
>> + .has_qspick = true,
>> + .has_ricr = true,
>> +};
>> +
>> +static const struct udevice_id atmel_qspi_ids[] = {
>> + {
>> + .compatible = "atmel,sama5d2-qspi",
>> + .data = (ulong)&atmel_sama5d2_qspi_caps,
>
> Better assign NULL
I deliberately added a zeroed caps instance to the sama5d2 entry to not allow
aq->caps to be NULL. This way I avoid redundant checks like:
+ if (aq->caps && aq->caps->has_qspick) {
and
+ if (aq->caps && aq->caps->has_ricr) {
Since this patch is just a backport from the linux driver and does not modify
the code logic, can we keep it as it is, and modify it later on if you have a
strong opinion on this?
Cheers,
ta
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2019-06-14 8:12 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-05-14 10:25 [U-Boot] [PATCH v3 00/10] spi: Add Atmel QuadSPI driver Tudor.Ambarus at microchip.com
2019-05-14 10:26 ` [U-Boot] [PATCH v3 01/10] dt-bindings: spi: add bindings for Atmel QSPI driver Tudor.Ambarus at microchip.com
2019-05-14 10:26 ` [U-Boot] [PATCH v3 02/10] spi: Add Atmel QuadSPI driver Tudor.Ambarus at microchip.com
2019-05-14 16:35 ` Tudor.Ambarus at microchip.com
2019-05-15 7:01 ` [U-Boot] [PATCH v4 " Tudor.Ambarus at microchip.com
2019-06-12 8:02 ` Jagan Teki
2019-06-14 8:12 ` Tudor.Ambarus at microchip.com
2019-05-14 10:26 ` [U-Boot] [PATCH v3 03/10] configs: sama5d2_xplained: enable qspi controller and flashes Tudor.Ambarus at microchip.com
2019-05-14 10:26 ` [U-Boot] [PATCH v3 04/10] configs: sama5d27_som1_ek: " Tudor.Ambarus at microchip.com
2019-05-14 10:26 ` [U-Boot] [PATCH v3 05/10] ARM: dts: at91: sama5d2_xplained: fix QSPI0 node Tudor.Ambarus at microchip.com
2019-05-14 10:26 ` [U-Boot] [PATCH v3 06/10] ARM: at91: sama5: add common environment for QSPI Tudor.Ambarus at microchip.com
2019-05-14 10:26 ` [U-Boot] [PATCH v3 07/10] configs: sama5d2_xplained: add qspiflash_defconfig Tudor.Ambarus at microchip.com
2019-05-14 10:26 ` [U-Boot] [PATCH v3 08/10] configs: sama5d27_som1_ek: " Tudor.Ambarus at microchip.com
2019-05-14 10:26 ` [U-Boot] [PATCH v3 09/10] configs: sama5d27_som1_ek: qspi: use common memory layout Tudor.Ambarus at microchip.com
2019-05-14 10:26 ` [U-Boot] [PATCH v3 10/10] configs: sama5d2_xplained: add support QSPI flash boot Tudor.Ambarus at microchip.com
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