From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> To: igt-dev@lists.freedesktop.org Cc: Intel-gfx@lists.freedesktop.org Subject: [PATCH i-g-t 21/25] gem_wsim: Allow RCS virtual engine with SSEU control Date: Fri, 17 May 2019 12:25:22 +0100 [thread overview] Message-ID: <20190517112526.6738-22-tvrtko.ursulin@linux.intel.com> (raw) In-Reply-To: <20190517112526.6738-1-tvrtko.ursulin@linux.intel.com> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> To allow exercising the SSEU configuration in combination with Virtual Engine, allow RCS to be specified in the engine map and use appropriate index based addressing when applying SSEU configuration to it. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> --- benchmarks/gem_wsim.c | 51 ++++++++++++++++++++++++++++++------------- 1 file changed, 36 insertions(+), 15 deletions(-) diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c index feb9650588a1..af042d71c1d3 100644 --- a/benchmarks/gem_wsim.c +++ b/benchmarks/gem_wsim.c @@ -382,7 +382,8 @@ static int parse_engine_map(struct w_step *step, const char *_str) if ((int)engine < 0) return -1; - if (engine != VCS && engine != VCS1 && engine != VCS2) + if (engine != VCS && engine != VCS1 && engine != VCS2 && + engine != RCS) return -1; /* TODO */ add = engine == VCS ? 2 : 1; @@ -1183,7 +1184,7 @@ static struct drm_i915_gem_context_param_sseu get_device_sseu(void) } static uint64_t -set_ctx_sseu(uint32_t ctx, uint64_t slice_mask) +set_ctx_sseu(struct ctx *ctx, uint64_t slice_mask) { struct drm_i915_gem_context_param_sseu sseu = get_device_sseu(); struct drm_i915_gem_context_param param = { }; @@ -1191,10 +1192,17 @@ set_ctx_sseu(uint32_t ctx, uint64_t slice_mask) if (slice_mask == -1) slice_mask = device_sseu.slice_mask; + if (ctx->engine_map && ctx->wants_balance) { + sseu.flags = I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX; + sseu.engine.engine_class = I915_ENGINE_CLASS_INVALID; + sseu.engine.engine_instance = 0; + } + sseu.slice_mask = slice_mask; - param.ctx_id = ctx; + param.ctx_id = ctx->id; param.param = I915_CONTEXT_PARAM_SSEU; + param.size = sizeof(sseu); param.value = (uintptr_t)&sseu; gem_context_set_param(fd, ¶m); @@ -1465,10 +1473,17 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags) ctx->engine_map_count; for (j = 0; j < ctx->engine_map_count; j++) { - load_balance.engines[j].engine_class = - I915_ENGINE_CLASS_VIDEO; /* FIXME */ - load_balance.engines[j].engine_instance = - ctx->engine_map[j] - VCS1; /* FIXME */ + if (ctx->engine_map[j] == RCS) { + load_balance.engines[j].engine_class = + I915_ENGINE_CLASS_RENDER; + load_balance.engines[j].engine_instance = + 0; /* FIXME */ + } else { + load_balance.engines[j].engine_class = + I915_ENGINE_CLASS_VIDEO; /* FIXME */ + load_balance.engines[j].engine_instance = + ctx->engine_map[j] - VCS1; /* FIXME */ + } } } else { set_engines.extensions = 0; @@ -1481,10 +1496,16 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags) I915_ENGINE_CLASS_INVALID_NONE; for (j = 1; j <= ctx->engine_map_count; j++) { - set_engines.engines[j].engine_class = - I915_ENGINE_CLASS_VIDEO; /* FIXME */ - set_engines.engines[j].engine_instance = - ctx->engine_map[j - 1] - VCS1; /* FIXME */ + if (ctx->engine_map[j - 1] == RCS) { + set_engines.engines[j].engine_class = + I915_ENGINE_CLASS_RENDER; + set_engines.engines[j].engine_instance = 0; /* FIXME */ + } else { + set_engines.engines[j].engine_class = + I915_ENGINE_CLASS_VIDEO; /* FIXME */ + set_engines.engines[j].engine_instance = + ctx->engine_map[j - 1] - VCS1; /* FIXME */ + } } for (j = 0; j < ctx->bond_count; j++) { @@ -1563,7 +1584,7 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags) if (wrk->sseu) { /* Set to slice 0 only, one slice. */ - ctx->sseu = set_ctx_sseu(ctx_id, 1); + ctx->sseu = set_ctx_sseu(ctx, 1); } if (share_vm) @@ -2547,9 +2568,9 @@ static void *run_workload(void *data) w->type == BOND) { continue; } else if (w->type == SSEU) { - if (w->sseu != wrk->ctx_list[w->context].sseu) { - wrk->ctx_list[w->context].sseu = - set_ctx_sseu(wrk->ctx_list[w->context].id, + if (w->sseu != wrk->ctx_list[w->context * 2].sseu) { + wrk->ctx_list[w->context * 2].sseu = + set_ctx_sseu(&wrk->ctx_list[w->context * 2], w->sseu); } continue; -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> To: igt-dev@lists.freedesktop.org Cc: Intel-gfx@lists.freedesktop.org, Tvrtko Ursulin <tvrtko.ursulin@intel.com> Subject: [igt-dev] [PATCH i-g-t 21/25] gem_wsim: Allow RCS virtual engine with SSEU control Date: Fri, 17 May 2019 12:25:22 +0100 [thread overview] Message-ID: <20190517112526.6738-22-tvrtko.ursulin@linux.intel.com> (raw) In-Reply-To: <20190517112526.6738-1-tvrtko.ursulin@linux.intel.com> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> To allow exercising the SSEU configuration in combination with Virtual Engine, allow RCS to be specified in the engine map and use appropriate index based addressing when applying SSEU configuration to it. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> --- benchmarks/gem_wsim.c | 51 ++++++++++++++++++++++++++++++------------- 1 file changed, 36 insertions(+), 15 deletions(-) diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c index feb9650588a1..af042d71c1d3 100644 --- a/benchmarks/gem_wsim.c +++ b/benchmarks/gem_wsim.c @@ -382,7 +382,8 @@ static int parse_engine_map(struct w_step *step, const char *_str) if ((int)engine < 0) return -1; - if (engine != VCS && engine != VCS1 && engine != VCS2) + if (engine != VCS && engine != VCS1 && engine != VCS2 && + engine != RCS) return -1; /* TODO */ add = engine == VCS ? 2 : 1; @@ -1183,7 +1184,7 @@ static struct drm_i915_gem_context_param_sseu get_device_sseu(void) } static uint64_t -set_ctx_sseu(uint32_t ctx, uint64_t slice_mask) +set_ctx_sseu(struct ctx *ctx, uint64_t slice_mask) { struct drm_i915_gem_context_param_sseu sseu = get_device_sseu(); struct drm_i915_gem_context_param param = { }; @@ -1191,10 +1192,17 @@ set_ctx_sseu(uint32_t ctx, uint64_t slice_mask) if (slice_mask == -1) slice_mask = device_sseu.slice_mask; + if (ctx->engine_map && ctx->wants_balance) { + sseu.flags = I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX; + sseu.engine.engine_class = I915_ENGINE_CLASS_INVALID; + sseu.engine.engine_instance = 0; + } + sseu.slice_mask = slice_mask; - param.ctx_id = ctx; + param.ctx_id = ctx->id; param.param = I915_CONTEXT_PARAM_SSEU; + param.size = sizeof(sseu); param.value = (uintptr_t)&sseu; gem_context_set_param(fd, ¶m); @@ -1465,10 +1473,17 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags) ctx->engine_map_count; for (j = 0; j < ctx->engine_map_count; j++) { - load_balance.engines[j].engine_class = - I915_ENGINE_CLASS_VIDEO; /* FIXME */ - load_balance.engines[j].engine_instance = - ctx->engine_map[j] - VCS1; /* FIXME */ + if (ctx->engine_map[j] == RCS) { + load_balance.engines[j].engine_class = + I915_ENGINE_CLASS_RENDER; + load_balance.engines[j].engine_instance = + 0; /* FIXME */ + } else { + load_balance.engines[j].engine_class = + I915_ENGINE_CLASS_VIDEO; /* FIXME */ + load_balance.engines[j].engine_instance = + ctx->engine_map[j] - VCS1; /* FIXME */ + } } } else { set_engines.extensions = 0; @@ -1481,10 +1496,16 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags) I915_ENGINE_CLASS_INVALID_NONE; for (j = 1; j <= ctx->engine_map_count; j++) { - set_engines.engines[j].engine_class = - I915_ENGINE_CLASS_VIDEO; /* FIXME */ - set_engines.engines[j].engine_instance = - ctx->engine_map[j - 1] - VCS1; /* FIXME */ + if (ctx->engine_map[j - 1] == RCS) { + set_engines.engines[j].engine_class = + I915_ENGINE_CLASS_RENDER; + set_engines.engines[j].engine_instance = 0; /* FIXME */ + } else { + set_engines.engines[j].engine_class = + I915_ENGINE_CLASS_VIDEO; /* FIXME */ + set_engines.engines[j].engine_instance = + ctx->engine_map[j - 1] - VCS1; /* FIXME */ + } } for (j = 0; j < ctx->bond_count; j++) { @@ -1563,7 +1584,7 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags) if (wrk->sseu) { /* Set to slice 0 only, one slice. */ - ctx->sseu = set_ctx_sseu(ctx_id, 1); + ctx->sseu = set_ctx_sseu(ctx, 1); } if (share_vm) @@ -2547,9 +2568,9 @@ static void *run_workload(void *data) w->type == BOND) { continue; } else if (w->type == SSEU) { - if (w->sseu != wrk->ctx_list[w->context].sseu) { - wrk->ctx_list[w->context].sseu = - set_ctx_sseu(wrk->ctx_list[w->context].id, + if (w->sseu != wrk->ctx_list[w->context * 2].sseu) { + wrk->ctx_list[w->context * 2].sseu = + set_ctx_sseu(&wrk->ctx_list[w->context * 2], w->sseu); } continue; -- 2.20.1 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev
next prev parent reply other threads:[~2019-05-17 11:25 UTC|newest] Thread overview: 109+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-05-17 11:25 [PATCH i-g-t 00/25] Media scalability tooling Tvrtko Ursulin 2019-05-17 11:25 ` [igt-dev] " Tvrtko Ursulin 2019-05-17 11:25 ` [PATCH i-g-t 01/25] scripts/trace.pl: Fix after intel_engine_notify removal Tvrtko Ursulin 2019-05-17 11:25 ` [Intel-gfx] " Tvrtko Ursulin 2019-05-17 11:25 ` [PATCH i-g-t 02/25] trace.pl: Ignore signaling on non i915 fences Tvrtko Ursulin 2019-05-17 11:25 ` [Intel-gfx] " Tvrtko Ursulin 2019-05-17 19:20 ` Chris Wilson 2019-05-17 19:20 ` [igt-dev] [Intel-gfx] " Chris Wilson 2019-05-20 10:30 ` Tvrtko Ursulin 2019-05-20 10:30 ` [igt-dev] [Intel-gfx] " Tvrtko Ursulin 2019-05-20 12:04 ` [PATCH v2 " Tvrtko Ursulin 2019-05-20 12:04 ` [igt-dev] " Tvrtko Ursulin 2019-05-17 11:25 ` [PATCH i-g-t 03/25] headers: bump Tvrtko Ursulin 2019-05-17 11:25 ` [igt-dev] " Tvrtko Ursulin 2019-05-17 11:25 ` [PATCH i-g-t 04/25] trace.pl: Virtual engine support Tvrtko Ursulin 2019-05-17 11:25 ` [igt-dev] " Tvrtko Ursulin 2019-05-17 19:23 ` Chris Wilson 2019-05-17 19:23 ` [igt-dev] " Chris Wilson 2019-05-17 11:25 ` [PATCH i-g-t 05/25] trace.pl: Virtual engine preemption support Tvrtko Ursulin 2019-05-17 11:25 ` [igt-dev] " Tvrtko Ursulin 2019-05-17 19:24 ` Chris Wilson 2019-05-17 19:24 ` Chris Wilson 2019-05-17 11:25 ` [PATCH i-g-t 06/25] wsim/media-bench: i915 balancing Tvrtko Ursulin 2019-05-17 11:25 ` [igt-dev] " Tvrtko Ursulin 2019-05-17 11:25 ` [PATCH i-g-t 07/25] gem_wsim: Use IGT uapi headers Tvrtko Ursulin 2019-05-17 11:25 ` [igt-dev] " Tvrtko Ursulin 2019-05-17 11:25 ` [PATCH i-g-t 08/25] gem_wsim: Factor out common error handling Tvrtko Ursulin 2019-05-17 11:25 ` [igt-dev] " Tvrtko Ursulin 2019-05-17 11:25 ` [PATCH i-g-t 09/25] gem_wsim: More wsim_err Tvrtko Ursulin 2019-05-17 11:25 ` [igt-dev] " Tvrtko Ursulin 2019-05-17 11:25 ` [PATCH i-g-t 10/25] gem_wsim: Submit fence support Tvrtko Ursulin 2019-05-17 11:25 ` [Intel-gfx] " Tvrtko Ursulin 2019-05-17 11:25 ` [PATCH i-g-t 11/25] gem_wsim: Extract str to engine lookup Tvrtko Ursulin 2019-05-17 11:25 ` [Intel-gfx] " Tvrtko Ursulin 2019-05-17 11:25 ` [PATCH i-g-t 12/25] gem_wsim: Engine map support Tvrtko Ursulin 2019-05-17 11:25 ` [igt-dev] " Tvrtko Ursulin 2019-05-17 19:35 ` Chris Wilson 2019-05-17 19:35 ` Chris Wilson 2019-05-20 10:49 ` Tvrtko Ursulin 2019-05-20 10:49 ` Tvrtko Ursulin 2019-05-20 10:59 ` Chris Wilson 2019-05-20 10:59 ` Chris Wilson 2019-05-20 11:10 ` Tvrtko Ursulin 2019-05-20 11:10 ` Tvrtko Ursulin 2019-05-17 11:25 ` [PATCH i-g-t 13/25] gem_wsim: Save some lines by changing to implicit NULL checking Tvrtko Ursulin 2019-05-17 11:25 ` [igt-dev] " Tvrtko Ursulin 2019-05-17 11:25 ` [PATCH i-g-t 14/25] gem_wsim: Compact int command parsing with a macro Tvrtko Ursulin 2019-05-17 11:25 ` [igt-dev] " Tvrtko Ursulin 2019-05-17 11:25 ` [PATCH i-g-t 15/25] gem_wsim: Engine map load balance command Tvrtko Ursulin 2019-05-17 11:25 ` [igt-dev] " Tvrtko Ursulin 2019-05-17 11:38 ` Chris Wilson 2019-05-17 11:38 ` Chris Wilson 2019-05-17 11:52 ` Tvrtko Ursulin 2019-05-17 11:52 ` Tvrtko Ursulin 2019-05-17 13:19 ` Chris Wilson 2019-05-17 13:19 ` Chris Wilson 2019-05-17 19:36 ` Chris Wilson 2019-05-17 19:36 ` Chris Wilson 2019-05-20 10:27 ` Tvrtko Ursulin 2019-05-20 10:27 ` Tvrtko Ursulin 2019-05-17 11:25 ` [PATCH i-g-t 16/25] gem_wsim: Engine bond command Tvrtko Ursulin 2019-05-17 11:25 ` [Intel-gfx] " Tvrtko Ursulin 2019-05-17 19:41 ` [igt-dev] " Chris Wilson 2019-05-17 19:41 ` Chris Wilson 2019-05-17 11:25 ` [PATCH i-g-t 17/25] gem_wsim: Some more example workloads Tvrtko Ursulin 2019-05-17 11:25 ` [igt-dev] " Tvrtko Ursulin 2019-05-17 11:25 ` [PATCH i-g-t 18/25] gem_wsim: Infinite batch support Tvrtko Ursulin 2019-05-17 11:25 ` [igt-dev] " Tvrtko Ursulin 2019-05-17 11:25 ` [PATCH i-g-t 19/25] gem_wsim: Command line switch for specifying low slice count workloads Tvrtko Ursulin 2019-05-17 11:25 ` [igt-dev] " Tvrtko Ursulin 2019-05-17 19:43 ` Chris Wilson 2019-05-17 19:43 ` Chris Wilson 2019-05-17 11:25 ` [PATCH i-g-t 20/25] gem_wsim: Per context SSEU control Tvrtko Ursulin 2019-05-17 11:25 ` [igt-dev] " Tvrtko Ursulin 2019-05-17 19:44 ` Chris Wilson 2019-05-17 19:44 ` Chris Wilson 2019-05-17 11:25 ` Tvrtko Ursulin [this message] 2019-05-17 11:25 ` [igt-dev] [PATCH i-g-t 21/25] gem_wsim: Allow RCS virtual engine with " Tvrtko Ursulin 2019-05-17 19:45 ` Chris Wilson 2019-05-17 19:45 ` Chris Wilson 2019-05-17 11:25 ` [PATCH i-g-t 22/25] tests/i915_query: Engine discovery tests Tvrtko Ursulin 2019-05-17 11:25 ` [igt-dev] " Tvrtko Ursulin 2019-05-17 11:25 ` [PATCH i-g-t 23/25] gem_wsim: Consolidate engine assignments into helpers Tvrtko Ursulin 2019-05-17 11:25 ` [Intel-gfx] " Tvrtko Ursulin 2019-05-17 11:25 ` [PATCH i-g-t 24/25] gem_wsim: Discover engines Tvrtko Ursulin 2019-05-17 11:25 ` [igt-dev] " Tvrtko Ursulin 2019-05-17 11:39 ` Andi Shyti 2019-05-17 11:39 ` Andi Shyti 2019-05-17 11:51 ` Tvrtko Ursulin 2019-05-17 11:51 ` Tvrtko Ursulin 2019-05-17 11:55 ` Andi Shyti 2019-05-17 11:55 ` Andi Shyti 2019-05-17 19:50 ` Chris Wilson 2019-05-17 19:50 ` Chris Wilson 2019-05-17 12:10 ` Andi Shyti 2019-05-17 12:10 ` Andi Shyti 2019-05-17 12:19 ` Tvrtko Ursulin 2019-05-17 12:19 ` Tvrtko Ursulin 2019-05-17 13:02 ` Andi Shyti 2019-05-17 13:02 ` Andi Shyti 2019-05-17 13:05 ` Tvrtko Ursulin 2019-05-17 13:05 ` Tvrtko Ursulin 2019-05-17 11:25 ` [PATCH i-g-t 25/25] gem_wsim: Support Icelake parts Tvrtko Ursulin 2019-05-17 11:25 ` [Intel-gfx] " Tvrtko Ursulin 2019-05-17 19:51 ` Chris Wilson 2019-05-17 19:51 ` [igt-dev] [Intel-gfx] " Chris Wilson 2019-05-17 12:18 ` [igt-dev] ✓ Fi.CI.BAT: success for Media scalability tooling (rev3) Patchwork 2019-05-17 17:33 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork 2019-05-20 13:30 ` [igt-dev] ✓ Fi.CI.BAT: success for Media scalability tooling (rev4) Patchwork
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