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* [CI i-g-t 00/14] Andi's engine discovery for CI
@ 2019-05-22 13:50 ` Tvrtko Ursulin
  0 siblings, 0 replies; 32+ messages in thread
From: Tvrtko Ursulin @ 2019-05-22 13:50 UTC (permalink / raw)
  To: igt-dev; +Cc: Intel-gfx

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Just for CI since the first patch from the original series won't apply any more.

Andi Shyti (13):
  lib/i915: add gem_engine_topology library and for_each loop definition
  lib: igt_gt: add execution buffer flags to class helper
  lib: igt_gt: make gem_engine_can_store_dword() check engine class
  lib: igt_dummyload: use for_each_context_engine()
  test: perf_pmu: use the gem_engine_topology library
  test/i915: gem_busy: use the gem_engine_topology library
  test/i915: gem_cs_tlb: use the gem_engine_topology library
  test/i915: gem_ctx_exec: use the gem_engine_topology library
  test/i915: gem_exec_basic: use the gem_engine_topology library
  test/i915: gem_exec_parallel: use the gem_engine_topology library
  test/i915: gem_exec_store: use the gem_engine_topology library
  test/i915: gem_wait: use the gem_engine_topology library
  test/i915: i915_hangman: use the gem_engine_topology library

Tvrtko Ursulin (1):
  drm-uapi: Import i915_drm.h upto
    c5d3e39caa456b1e061644b739131f2b54c84c08

 include/drm-uapi/i915_drm.h    |  42 +++++
 lib/Makefile.sources           |   2 +
 lib/i915/gem_engine_topology.c | 298 +++++++++++++++++++++++++++++++++
 lib/i915/gem_engine_topology.h |  70 ++++++++
 lib/igt.h                      |   1 +
 lib/igt_dummyload.c            |  29 +++-
 lib/igt_gt.c                   |  30 +++-
 lib/igt_gt.h                   |  12 +-
 lib/meson.build                |   1 +
 tests/i915/gem_busy.c          | 128 ++++++--------
 tests/i915/gem_cs_tlb.c        |   8 +-
 tests/i915/gem_ctx_exec.c      |  16 +-
 tests/i915/gem_exec_basic.c    |  28 ++--
 tests/i915/gem_exec_parallel.c |  26 +--
 tests/i915/gem_exec_store.c    |  36 ++--
 tests/i915/gem_wait.c          |  24 +--
 tests/i915/i915_hangman.c      |  15 +-
 tests/perf_pmu.c               | 110 ++++++------
 18 files changed, 647 insertions(+), 229 deletions(-)
 create mode 100644 lib/i915/gem_engine_topology.c
 create mode 100644 lib/i915/gem_engine_topology.h

-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 32+ messages in thread
* [igt-dev] [CI i-g-t 00/14] Andi's engine discovery for CI
@ 2019-05-22 13:50 ` Tvrtko Ursulin
  0 siblings, 0 replies; 32+ messages in thread
From: Tvrtko Ursulin @ 2019-05-22 13:50 UTC (permalink / raw)
  To: igt-dev; +Cc: Intel-gfx

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Just for CI since the first patch from the original series won't apply any more.

Andi Shyti (13):
  lib/i915: add gem_engine_topology library and for_each loop definition
  lib: igt_gt: add execution buffer flags to class helper
  lib: igt_gt: make gem_engine_can_store_dword() check engine class
  lib: igt_dummyload: use for_each_context_engine()
  test: perf_pmu: use the gem_engine_topology library
  test/i915: gem_busy: use the gem_engine_topology library
  test/i915: gem_cs_tlb: use the gem_engine_topology library
  test/i915: gem_ctx_exec: use the gem_engine_topology library
  test/i915: gem_exec_basic: use the gem_engine_topology library
  test/i915: gem_exec_parallel: use the gem_engine_topology library
  test/i915: gem_exec_store: use the gem_engine_topology library
  test/i915: gem_wait: use the gem_engine_topology library
  test/i915: i915_hangman: use the gem_engine_topology library

Tvrtko Ursulin (1):
  drm-uapi: Import i915_drm.h upto
    c5d3e39caa456b1e061644b739131f2b54c84c08

 include/drm-uapi/i915_drm.h    |  42 +++++
 lib/Makefile.sources           |   2 +
 lib/i915/gem_engine_topology.c | 298 +++++++++++++++++++++++++++++++++
 lib/i915/gem_engine_topology.h |  70 ++++++++
 lib/igt.h                      |   1 +
 lib/igt_dummyload.c            |  29 +++-
 lib/igt_gt.c                   |  30 +++-
 lib/igt_gt.h                   |  12 +-
 lib/meson.build                |   1 +
 tests/i915/gem_busy.c          | 128 ++++++--------
 tests/i915/gem_cs_tlb.c        |   8 +-
 tests/i915/gem_ctx_exec.c      |  16 +-
 tests/i915/gem_exec_basic.c    |  28 ++--
 tests/i915/gem_exec_parallel.c |  26 +--
 tests/i915/gem_exec_store.c    |  36 ++--
 tests/i915/gem_wait.c          |  24 +--
 tests/i915/i915_hangman.c      |  15 +-
 tests/perf_pmu.c               | 110 ++++++------
 18 files changed, 647 insertions(+), 229 deletions(-)
 create mode 100644 lib/i915/gem_engine_topology.c
 create mode 100644 lib/i915/gem_engine_topology.h

-- 
2.20.1

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply	[flat|nested] 32+ messages in thread
* [CI i-g-t 01/14] drm-uapi: Import i915_drm.h upto c5d3e39caa456b1e061644b739131f2b54c84c08
  2019-05-22 13:50 ` [igt-dev] " Tvrtko Ursulin
@ 2019-05-22 13:50   ` Tvrtko Ursulin
  -1 siblings, 0 replies; 32+ messages in thread
From: Tvrtko Ursulin @ 2019-05-22 13:50 UTC (permalink / raw)
  To: igt-dev; +Cc: Intel-gfx

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

  commit c5d3e39caa456b1e061644b739131f2b54c84c08
  Author: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
  Date:   Wed May 22 10:00:54 2019 +0100

      drm/i915: Engine discovery query

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 include/drm-uapi/i915_drm.h | 42 +++++++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index de7be1bc6b04..761517f15368 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -1982,6 +1982,7 @@ struct drm_i915_perf_oa_config {
 struct drm_i915_query_item {
 	__u64 query_id;
 #define DRM_I915_QUERY_TOPOLOGY_INFO    1
+#define DRM_I915_QUERY_ENGINE_INFO	2
 /* Must be kept compact -- no holes and well documented */
 
 	/*
@@ -2080,6 +2081,47 @@ struct drm_i915_query_topology_info {
 	__u8 data[];
 };
 
+/**
+ * struct drm_i915_engine_info
+ *
+ * Describes one engine and it's capabilities as known to the driver.
+ */
+struct drm_i915_engine_info {
+	/** Engine class and instance. */
+	struct i915_engine_class_instance engine;
+
+	/** Reserved field. */
+	__u32 rsvd0;
+
+	/** Engine flags. */
+	__u64 flags;
+
+	/** Capabilities of this engine. */
+	__u64 capabilities;
+#define I915_VIDEO_CLASS_CAPABILITY_HEVC		(1 << 0)
+#define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC	(1 << 1)
+
+	/** Reserved fields. */
+	__u64 rsvd1[4];
+};
+
+/**
+ * struct drm_i915_query_engine_info
+ *
+ * Engine info query enumerates all engines known to the driver by filling in
+ * an array of struct drm_i915_engine_info structures.
+ */
+struct drm_i915_query_engine_info {
+	/** Number of struct drm_i915_engine_info structs following. */
+	__u32 num_engines;
+
+	/** MBZ */
+	__u32 rsvd[3];
+
+	/** Marker for drm_i915_engine_info structures. */
+	struct drm_i915_engine_info engines[];
+};
+
 #if defined(__cplusplus)
 }
 #endif
-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 32+ messages in thread
* [Intel-gfx] [CI i-g-t 01/14] drm-uapi: Import i915_drm.h upto c5d3e39caa456b1e061644b739131f2b54c84c08
@ 2019-05-22 13:50   ` Tvrtko Ursulin
  0 siblings, 0 replies; 32+ messages in thread
From: Tvrtko Ursulin @ 2019-05-22 13:50 UTC (permalink / raw)
  To: igt-dev; +Cc: Intel-gfx

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

  commit c5d3e39caa456b1e061644b739131f2b54c84c08
  Author: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
  Date:   Wed May 22 10:00:54 2019 +0100

      drm/i915: Engine discovery query

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 include/drm-uapi/i915_drm.h | 42 +++++++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index de7be1bc6b04..761517f15368 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -1982,6 +1982,7 @@ struct drm_i915_perf_oa_config {
 struct drm_i915_query_item {
 	__u64 query_id;
 #define DRM_I915_QUERY_TOPOLOGY_INFO    1
+#define DRM_I915_QUERY_ENGINE_INFO	2
 /* Must be kept compact -- no holes and well documented */
 
 	/*
@@ -2080,6 +2081,47 @@ struct drm_i915_query_topology_info {
 	__u8 data[];
 };
 
+/**
+ * struct drm_i915_engine_info
+ *
+ * Describes one engine and it's capabilities as known to the driver.
+ */
+struct drm_i915_engine_info {
+	/** Engine class and instance. */
+	struct i915_engine_class_instance engine;
+
+	/** Reserved field. */
+	__u32 rsvd0;
+
+	/** Engine flags. */
+	__u64 flags;
+
+	/** Capabilities of this engine. */
+	__u64 capabilities;
+#define I915_VIDEO_CLASS_CAPABILITY_HEVC		(1 << 0)
+#define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC	(1 << 1)
+
+	/** Reserved fields. */
+	__u64 rsvd1[4];
+};
+
+/**
+ * struct drm_i915_query_engine_info
+ *
+ * Engine info query enumerates all engines known to the driver by filling in
+ * an array of struct drm_i915_engine_info structures.
+ */
+struct drm_i915_query_engine_info {
+	/** Number of struct drm_i915_engine_info structs following. */
+	__u32 num_engines;
+
+	/** MBZ */
+	__u32 rsvd[3];
+
+	/** Marker for drm_i915_engine_info structures. */
+	struct drm_i915_engine_info engines[];
+};
+
 #if defined(__cplusplus)
 }
 #endif
-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 32+ messages in thread
* [CI i-g-t 02/14] lib/i915: add gem_engine_topology library and for_each loop definition
  2019-05-22 13:50 ` [igt-dev] " Tvrtko Ursulin
@ 2019-05-22 13:50   ` Tvrtko Ursulin
  -1 siblings, 0 replies; 32+ messages in thread
From: Tvrtko Ursulin @ 2019-05-22 13:50 UTC (permalink / raw)
  To: igt-dev; +Cc: Intel-gfx

From: Andi Shyti <andi.shyti@intel.com>

The gem_engine_topology library is a set of functions that
interface with the query and getparam/setparam ioctls.

The library's access point is the 'intel_init_engine_list()'
function that, everytime is called, generates the list of active
engines and returns them in a 'struct intel_engine_data'. The
structure contains only the engines that are actively present in
the GPU.

The function can work in both the cases that the query and
getparam ioctls are implemented or not by the running kernel. In
case they are implemented, a query is made to the driver to fetch
the list of active engines. In case they are not implemented, the
list is taken from the 'intel_execution_engines2' array and
stored only after checking their presence.

The gem_engine_topology library provides some iteration helpers:

 - intel_get_current_engine(): provides the current engine in the
   iteration.

 - intel_get_current_physical_engine(): provides the current
   physical engine, if the current engine is a virtual engine,
   it moves forward until it finds a physical engine.

 - intel_next_engine() it just increments the counter so that it
   points to the next engine.

Extend the 'for_each_engine_class_instance' so that it can loop
using the new 'intel_init_engine_list()' and rename it to
'for_each_context_engine'.

Move '__for_each_engine_class_instance' to gem_engine_topology.h
and rename it to '__for_each_static_engine'.

Update accordingly tests/perf_pmu.c to use correctly the new
for_each loops.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 lib/Makefile.sources           |   2 +
 lib/i915/gem_engine_topology.c | 298 +++++++++++++++++++++++++++++++++
 lib/i915/gem_engine_topology.h |  70 ++++++++
 lib/igt.h                      |   1 +
 lib/igt_gt.h                   |   2 +
 lib/meson.build                |   1 +
 6 files changed, 374 insertions(+)
 create mode 100644 lib/i915/gem_engine_topology.c
 create mode 100644 lib/i915/gem_engine_topology.h

diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index 97685823894b..ef96bd09d049 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -13,6 +13,8 @@ lib_source_list =	 	\
 	i915/gem_ring.c	\
 	i915/gem_mman.c	\
 	i915/gem_mman.h	\
+	i915/gem_engine_topology.c	\
+	i915/gem_engine_topology.h	\
 	i915_3d.h		\
 	i915_reg.h		\
 	i915_pciids.h		\
diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
new file mode 100644
index 000000000000..dd26fae00853
--- /dev/null
+++ b/lib/i915/gem_engine_topology.c
@@ -0,0 +1,298 @@
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "drmtest.h"
+#include "ioctl_wrappers.h"
+
+#include "i915/gem_engine_topology.h"
+
+/*
+ * Limit what we support for simplicity due limitation in how much we
+ * can address via execbuf2.
+ */
+#define SIZEOF_CTX_PARAM	offsetof(struct i915_context_param_engines, \
+					 engines[GEM_MAX_ENGINES])
+#define SIZEOF_QUERY		offsetof(struct drm_i915_query_engine_info, \
+					 engines[GEM_MAX_ENGINES])
+
+#define DEFINE_CONTEXT_ENGINES_PARAM(e__, p__, c__, N__) \
+		I915_DEFINE_CONTEXT_PARAM_ENGINES(e__, N__); \
+		struct drm_i915_gem_context_param p__ = { \
+			.param = I915_CONTEXT_PARAM_ENGINES, \
+			.ctx_id = c__, \
+			.size = SIZEOF_CTX_PARAM, \
+			.value = to_user_pointer(&e__), \
+		}
+
+static int __gem_query(int fd, struct drm_i915_query *q)
+{
+	int err = 0;
+
+	if (igt_ioctl(fd, DRM_IOCTL_I915_QUERY, q))
+		err = -errno;
+
+	errno = 0;
+	return err;
+}
+
+static void gem_query(int fd, struct drm_i915_query *q)
+{
+	igt_assert_eq(__gem_query(fd, q), 0);
+}
+
+static void query_engines(int fd,
+			  struct drm_i915_query_engine_info *query_engines,
+			  int length)
+{
+	struct drm_i915_query_item item = { };
+	struct drm_i915_query query = { };
+
+	item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+	query.items_ptr = to_user_pointer(&item);
+	query.num_items = 1;
+	item.length = length;
+
+	item.data_ptr = to_user_pointer(query_engines);
+
+	gem_query(fd, &query);
+}
+
+static void ctx_map_engines(int fd, struct intel_engine_data *ed,
+			    struct drm_i915_gem_context_param *param)
+{
+	struct i915_context_param_engines *engines =
+			(struct i915_context_param_engines *) param->value;
+	int i = 0;
+
+	for (typeof(engines->engines[0]) *p =
+	     &engines->engines[0];
+	     i < ed->nengines; i++, p++) {
+		p->engine_class = ed->engines[i].class;
+		p->engine_instance = ed->engines[i].instance;
+	}
+
+	param->size = offsetof(typeof(*engines), engines[i]);
+	engines->extensions = 0;
+
+	gem_context_set_param(fd, param);
+}
+
+static void init_engine(struct intel_execution_engine2 *e2,
+			int class, int instance, uint64_t flags)
+{
+	const struct intel_execution_engine2 *__e2;
+	static const char *unknown_name = "unknown",
+			  *virtual_name = "virtual";
+
+	e2->class    = class;
+	e2->instance = instance;
+	e2->flags    = flags;
+
+	/* engine is a virtual engine */
+	if (class == I915_ENGINE_CLASS_INVALID &&
+	    instance == I915_ENGINE_CLASS_INVALID_VIRTUAL) {
+		e2->name = virtual_name;
+		e2->is_virtual = true;
+		return;
+	}
+
+	__for_each_static_engine(__e2)
+		if (__e2->class == class && __e2->instance == instance)
+			break;
+
+	if (__e2->name) {
+		e2->name = __e2->name;
+	} else {
+		igt_warn("found unknown engine (%d, %d)", class, instance);
+		e2->name = unknown_name;
+		e2->flags = -1;
+	}
+
+	/* just to remark it */
+	e2->is_virtual = false;
+}
+
+static void query_engine_list(int fd, struct intel_engine_data *ed)
+{
+	uint8_t buff[SIZEOF_QUERY] = { };
+	struct drm_i915_query_engine_info *query_engine =
+			(struct drm_i915_query_engine_info *) buff;
+	int i;
+
+	query_engines(fd, query_engine, SIZEOF_QUERY);
+
+	for (i = 0; i < query_engine->num_engines; i++)
+		init_engine(&ed->engines[i],
+			    query_engine->engines[i].engine.engine_class,
+			    query_engine->engines[i].engine.engine_instance, i);
+
+	ed->nengines = query_engine->num_engines;
+}
+
+struct intel_execution_engine2 *
+intel_get_current_engine(struct intel_engine_data *ed)
+{
+	if (!ed->n)
+		ed->current_engine = &ed->engines[0];
+	else if (ed->n >= ed->nengines)
+		ed->current_engine = NULL;
+
+	return ed->current_engine;
+}
+
+void intel_next_engine(struct intel_engine_data *ed)
+{
+	if (ed->n + 1 < ed->nengines) {
+		ed->n++;
+		ed->current_engine = &ed->engines[ed->n];
+	} else {
+		ed->n = ed->nengines;
+		ed->current_engine = NULL;
+	}
+}
+
+struct intel_execution_engine2 *
+intel_get_current_physical_engine(struct intel_engine_data *ed)
+{
+	struct intel_execution_engine2 *e;
+
+	for (e = intel_get_current_engine(ed);
+	     e && e->is_virtual;
+	     intel_next_engine(ed))
+		;
+
+	return e;
+}
+
+static int gem_topology_get_param(int fd,
+				  struct drm_i915_gem_context_param *p)
+{
+	if (igt_only_list_subtests())
+		return -ENODEV;
+
+	if (__gem_context_get_param(fd, p))
+		return -1; /* using default engine map */
+
+	if (!p->size)
+		return 0;
+
+	/* size will store the engine count */
+	p->size = (p->size - sizeof(struct i915_context_param_engines)) /
+		  (offsetof(struct i915_context_param_engines,
+			    engines[1]) -
+		  sizeof(struct i915_context_param_engines));
+
+	igt_assert_f(p->size <= GEM_MAX_ENGINES, "unsupported engine count\n");
+
+	return 0;
+}
+
+struct intel_engine_data intel_init_engine_list(int fd, uint32_t ctx_id)
+{
+	DEFINE_CONTEXT_ENGINES_PARAM(engines, param, ctx_id, GEM_MAX_ENGINES);
+	struct intel_engine_data engine_data = { };
+	int i;
+
+	if (gem_topology_get_param(fd, &param)) {
+		/* if kernel does not support engine/context mapping */
+		const struct intel_execution_engine2 *e2;
+
+		igt_debug("using pre-allocated engine list\n");
+
+		__for_each_static_engine(e2) {
+			struct intel_execution_engine2 *__e2 =
+				&engine_data.engines[engine_data.nengines];
+
+			if (!igt_only_list_subtests()) {
+				__e2->flags = gem_class_instance_to_eb_flags(fd,
+						e2->class, e2->instance);
+
+				if (!gem_has_ring(fd, __e2->flags))
+					continue;
+			} else {
+				__e2->flags = -1; /* 0xfff... */
+			}
+
+			__e2->name       = e2->name;
+			__e2->instance   = e2->instance;
+			__e2->class      = e2->class;
+			__e2->is_virtual = false;
+
+			engine_data.nengines++;
+		}
+		return engine_data;
+	}
+
+	if (!param.size) {
+		query_engine_list(fd, &engine_data);
+		ctx_map_engines(fd, &engine_data, &param);
+	} else {
+		/* param.size contains the engine count */
+		for (i = 0; i < param.size; i++)
+			init_engine(&engine_data.engines[i],
+				    engines.engines[i].engine_class,
+				    engines.engines[i].engine_instance,
+				    i);
+
+		engine_data.nengines = i;
+	}
+
+	return engine_data;
+}
+
+int gem_context_lookup_engine(int fd, uint64_t engine, uint32_t ctx_id,
+			      struct intel_execution_engine2 *e)
+{
+	DEFINE_CONTEXT_ENGINES_PARAM(engines, param, ctx_id, GEM_MAX_ENGINES);
+
+	/* a bit paranoic */
+	igt_assert(e);
+
+	if (gem_topology_get_param(fd, &param) || !param.size)
+		return -EINVAL;
+
+	e->class = engines.engines[engine].engine_class;
+	e->instance = engines.engines[engine].engine_instance;
+
+	return 0;
+}
+
+void gem_context_set_all_engines(int fd, uint32_t ctx)
+{
+	DEFINE_CONTEXT_ENGINES_PARAM(engines, param, ctx, GEM_MAX_ENGINES);
+	struct intel_engine_data engine_data = { };
+
+	if (!gem_topology_get_param(fd, &param) && !param.size) {
+		query_engine_list(fd, &engine_data);
+		ctx_map_engines(fd, &engine_data, &param);
+	}
+}
+
+bool gem_has_engine_topology(int fd)
+{
+	struct drm_i915_gem_context_param param = {
+		.param = I915_CONTEXT_PARAM_ENGINES,
+	};
+
+	return !__gem_context_get_param(fd, &param);
+}
diff --git a/lib/i915/gem_engine_topology.h b/lib/i915/gem_engine_topology.h
new file mode 100644
index 000000000000..2415fd1e379b
--- /dev/null
+++ b/lib/i915/gem_engine_topology.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef GEM_ENGINE_TOPOLOGY_H
+#define GEM_ENGINE_TOPOLOGY_H
+
+#include "igt_gt.h"
+#include "i915_drm.h"
+
+#define GEM_MAX_ENGINES		I915_EXEC_RING_MASK + 1
+
+struct intel_engine_data {
+	uint32_t nengines;
+	uint32_t n;
+	struct intel_execution_engine2 *current_engine;
+	struct intel_execution_engine2 engines[GEM_MAX_ENGINES];
+};
+
+bool gem_has_engine_topology(int fd);
+struct intel_engine_data intel_init_engine_list(int fd, uint32_t ctx_id);
+
+/* iteration functions */
+struct intel_execution_engine2 *
+intel_get_current_engine(struct intel_engine_data *ed);
+
+struct intel_execution_engine2 *
+intel_get_current_physical_engine(struct intel_engine_data *ed);
+
+void intel_next_engine(struct intel_engine_data *ed);
+
+int gem_context_lookup_engine(int fd, uint64_t engine, uint32_t ctx_id,
+			      struct intel_execution_engine2 *e);
+
+void gem_context_set_all_engines(int fd, uint32_t ctx);
+
+#define __for_each_static_engine(e__) \
+	for ((e__) = intel_execution_engines2; (e__)->name; (e__)++)
+
+#define for_each_context_engine(fd__, ctx__, e__) \
+	for (struct intel_engine_data i__ = intel_init_engine_list(fd__, ctx__); \
+	     ((e__) = intel_get_current_engine(&i__)); \
+	     intel_next_engine(&i__))
+
+/* needs to replace "for_each_physical_engine" when conflicts are fixed */
+#define __for_each_physical_engine(fd__, e__) \
+	for (struct intel_engine_data i__ = intel_init_engine_list(fd__, 0); \
+	     ((e__) = intel_get_current_physical_engine(&i__)); \
+	     intel_next_engine(&i__))
+
+#endif /* GEM_ENGINE_TOPOLOGY_H */
diff --git a/lib/igt.h b/lib/igt.h
index 2ae43c30ff61..82cdd57a4deb 100644
--- a/lib/igt.h
+++ b/lib/igt.h
@@ -54,5 +54,6 @@
 #include "media_spin.h"
 #include "rendercopy.h"
 #include "i915/gem_mman.h"
+#include "i915/gem_engine_topology.h"
 
 #endif /* IGT_H */
diff --git a/lib/igt_gt.h b/lib/igt_gt.h
index 475c0b3c3cc6..52b2f1ea95a5 100644
--- a/lib/igt_gt.h
+++ b/lib/igt_gt.h
@@ -95,6 +95,8 @@ extern const struct intel_execution_engine2 {
 	const char *name;
 	int class;
 	int instance;
+	uint64_t flags;
+	bool is_virtual;
 } intel_execution_engines2[];
 
 unsigned int
diff --git a/lib/meson.build b/lib/meson.build
index 8073686867d4..b6d8e6ca5a7e 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -5,6 +5,7 @@ lib_sources = [
 	'i915/gem_submission.c',
 	'i915/gem_ring.c',
 	'i915/gem_mman.c',
+	'i915/gem_engine_topology.c',
 	'igt_color_encoding.c',
 	'igt_debugfs.c',
 	'igt_device.c',
-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 32+ messages in thread
* [Intel-gfx] [CI i-g-t 02/14] lib/i915: add gem_engine_topology library and for_each loop definition
@ 2019-05-22 13:50   ` Tvrtko Ursulin
  0 siblings, 0 replies; 32+ messages in thread
From: Tvrtko Ursulin @ 2019-05-22 13:50 UTC (permalink / raw)
  To: igt-dev; +Cc: Intel-gfx

From: Andi Shyti <andi.shyti@intel.com>

The gem_engine_topology library is a set of functions that
interface with the query and getparam/setparam ioctls.

The library's access point is the 'intel_init_engine_list()'
function that, everytime is called, generates the list of active
engines and returns them in a 'struct intel_engine_data'. The
structure contains only the engines that are actively present in
the GPU.

The function can work in both the cases that the query and
getparam ioctls are implemented or not by the running kernel. In
case they are implemented, a query is made to the driver to fetch
the list of active engines. In case they are not implemented, the
list is taken from the 'intel_execution_engines2' array and
stored only after checking their presence.

The gem_engine_topology library provides some iteration helpers:

 - intel_get_current_engine(): provides the current engine in the
   iteration.

 - intel_get_current_physical_engine(): provides the current
   physical engine, if the current engine is a virtual engine,
   it moves forward until it finds a physical engine.

 - intel_next_engine() it just increments the counter so that it
   points to the next engine.

Extend the 'for_each_engine_class_instance' so that it can loop
using the new 'intel_init_engine_list()' and rename it to
'for_each_context_engine'.

Move '__for_each_engine_class_instance' to gem_engine_topology.h
and rename it to '__for_each_static_engine'.

Update accordingly tests/perf_pmu.c to use correctly the new
for_each loops.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 lib/Makefile.sources           |   2 +
 lib/i915/gem_engine_topology.c | 298 +++++++++++++++++++++++++++++++++
 lib/i915/gem_engine_topology.h |  70 ++++++++
 lib/igt.h                      |   1 +
 lib/igt_gt.h                   |   2 +
 lib/meson.build                |   1 +
 6 files changed, 374 insertions(+)
 create mode 100644 lib/i915/gem_engine_topology.c
 create mode 100644 lib/i915/gem_engine_topology.h

diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index 97685823894b..ef96bd09d049 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -13,6 +13,8 @@ lib_source_list =	 	\
 	i915/gem_ring.c	\
 	i915/gem_mman.c	\
 	i915/gem_mman.h	\
+	i915/gem_engine_topology.c	\
+	i915/gem_engine_topology.h	\
 	i915_3d.h		\
 	i915_reg.h		\
 	i915_pciids.h		\
diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
new file mode 100644
index 000000000000..dd26fae00853
--- /dev/null
+++ b/lib/i915/gem_engine_topology.c
@@ -0,0 +1,298 @@
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "drmtest.h"
+#include "ioctl_wrappers.h"
+
+#include "i915/gem_engine_topology.h"
+
+/*
+ * Limit what we support for simplicity due limitation in how much we
+ * can address via execbuf2.
+ */
+#define SIZEOF_CTX_PARAM	offsetof(struct i915_context_param_engines, \
+					 engines[GEM_MAX_ENGINES])
+#define SIZEOF_QUERY		offsetof(struct drm_i915_query_engine_info, \
+					 engines[GEM_MAX_ENGINES])
+
+#define DEFINE_CONTEXT_ENGINES_PARAM(e__, p__, c__, N__) \
+		I915_DEFINE_CONTEXT_PARAM_ENGINES(e__, N__); \
+		struct drm_i915_gem_context_param p__ = { \
+			.param = I915_CONTEXT_PARAM_ENGINES, \
+			.ctx_id = c__, \
+			.size = SIZEOF_CTX_PARAM, \
+			.value = to_user_pointer(&e__), \
+		}
+
+static int __gem_query(int fd, struct drm_i915_query *q)
+{
+	int err = 0;
+
+	if (igt_ioctl(fd, DRM_IOCTL_I915_QUERY, q))
+		err = -errno;
+
+	errno = 0;
+	return err;
+}
+
+static void gem_query(int fd, struct drm_i915_query *q)
+{
+	igt_assert_eq(__gem_query(fd, q), 0);
+}
+
+static void query_engines(int fd,
+			  struct drm_i915_query_engine_info *query_engines,
+			  int length)
+{
+	struct drm_i915_query_item item = { };
+	struct drm_i915_query query = { };
+
+	item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+	query.items_ptr = to_user_pointer(&item);
+	query.num_items = 1;
+	item.length = length;
+
+	item.data_ptr = to_user_pointer(query_engines);
+
+	gem_query(fd, &query);
+}
+
+static void ctx_map_engines(int fd, struct intel_engine_data *ed,
+			    struct drm_i915_gem_context_param *param)
+{
+	struct i915_context_param_engines *engines =
+			(struct i915_context_param_engines *) param->value;
+	int i = 0;
+
+	for (typeof(engines->engines[0]) *p =
+	     &engines->engines[0];
+	     i < ed->nengines; i++, p++) {
+		p->engine_class = ed->engines[i].class;
+		p->engine_instance = ed->engines[i].instance;
+	}
+
+	param->size = offsetof(typeof(*engines), engines[i]);
+	engines->extensions = 0;
+
+	gem_context_set_param(fd, param);
+}
+
+static void init_engine(struct intel_execution_engine2 *e2,
+			int class, int instance, uint64_t flags)
+{
+	const struct intel_execution_engine2 *__e2;
+	static const char *unknown_name = "unknown",
+			  *virtual_name = "virtual";
+
+	e2->class    = class;
+	e2->instance = instance;
+	e2->flags    = flags;
+
+	/* engine is a virtual engine */
+	if (class == I915_ENGINE_CLASS_INVALID &&
+	    instance == I915_ENGINE_CLASS_INVALID_VIRTUAL) {
+		e2->name = virtual_name;
+		e2->is_virtual = true;
+		return;
+	}
+
+	__for_each_static_engine(__e2)
+		if (__e2->class == class && __e2->instance == instance)
+			break;
+
+	if (__e2->name) {
+		e2->name = __e2->name;
+	} else {
+		igt_warn("found unknown engine (%d, %d)", class, instance);
+		e2->name = unknown_name;
+		e2->flags = -1;
+	}
+
+	/* just to remark it */
+	e2->is_virtual = false;
+}
+
+static void query_engine_list(int fd, struct intel_engine_data *ed)
+{
+	uint8_t buff[SIZEOF_QUERY] = { };
+	struct drm_i915_query_engine_info *query_engine =
+			(struct drm_i915_query_engine_info *) buff;
+	int i;
+
+	query_engines(fd, query_engine, SIZEOF_QUERY);
+
+	for (i = 0; i < query_engine->num_engines; i++)
+		init_engine(&ed->engines[i],
+			    query_engine->engines[i].engine.engine_class,
+			    query_engine->engines[i].engine.engine_instance, i);
+
+	ed->nengines = query_engine->num_engines;
+}
+
+struct intel_execution_engine2 *
+intel_get_current_engine(struct intel_engine_data *ed)
+{
+	if (!ed->n)
+		ed->current_engine = &ed->engines[0];
+	else if (ed->n >= ed->nengines)
+		ed->current_engine = NULL;
+
+	return ed->current_engine;
+}
+
+void intel_next_engine(struct intel_engine_data *ed)
+{
+	if (ed->n + 1 < ed->nengines) {
+		ed->n++;
+		ed->current_engine = &ed->engines[ed->n];
+	} else {
+		ed->n = ed->nengines;
+		ed->current_engine = NULL;
+	}
+}
+
+struct intel_execution_engine2 *
+intel_get_current_physical_engine(struct intel_engine_data *ed)
+{
+	struct intel_execution_engine2 *e;
+
+	for (e = intel_get_current_engine(ed);
+	     e && e->is_virtual;
+	     intel_next_engine(ed))
+		;
+
+	return e;
+}
+
+static int gem_topology_get_param(int fd,
+				  struct drm_i915_gem_context_param *p)
+{
+	if (igt_only_list_subtests())
+		return -ENODEV;
+
+	if (__gem_context_get_param(fd, p))
+		return -1; /* using default engine map */
+
+	if (!p->size)
+		return 0;
+
+	/* size will store the engine count */
+	p->size = (p->size - sizeof(struct i915_context_param_engines)) /
+		  (offsetof(struct i915_context_param_engines,
+			    engines[1]) -
+		  sizeof(struct i915_context_param_engines));
+
+	igt_assert_f(p->size <= GEM_MAX_ENGINES, "unsupported engine count\n");
+
+	return 0;
+}
+
+struct intel_engine_data intel_init_engine_list(int fd, uint32_t ctx_id)
+{
+	DEFINE_CONTEXT_ENGINES_PARAM(engines, param, ctx_id, GEM_MAX_ENGINES);
+	struct intel_engine_data engine_data = { };
+	int i;
+
+	if (gem_topology_get_param(fd, &param)) {
+		/* if kernel does not support engine/context mapping */
+		const struct intel_execution_engine2 *e2;
+
+		igt_debug("using pre-allocated engine list\n");
+
+		__for_each_static_engine(e2) {
+			struct intel_execution_engine2 *__e2 =
+				&engine_data.engines[engine_data.nengines];
+
+			if (!igt_only_list_subtests()) {
+				__e2->flags = gem_class_instance_to_eb_flags(fd,
+						e2->class, e2->instance);
+
+				if (!gem_has_ring(fd, __e2->flags))
+					continue;
+			} else {
+				__e2->flags = -1; /* 0xfff... */
+			}
+
+			__e2->name       = e2->name;
+			__e2->instance   = e2->instance;
+			__e2->class      = e2->class;
+			__e2->is_virtual = false;
+
+			engine_data.nengines++;
+		}
+		return engine_data;
+	}
+
+	if (!param.size) {
+		query_engine_list(fd, &engine_data);
+		ctx_map_engines(fd, &engine_data, &param);
+	} else {
+		/* param.size contains the engine count */
+		for (i = 0; i < param.size; i++)
+			init_engine(&engine_data.engines[i],
+				    engines.engines[i].engine_class,
+				    engines.engines[i].engine_instance,
+				    i);
+
+		engine_data.nengines = i;
+	}
+
+	return engine_data;
+}
+
+int gem_context_lookup_engine(int fd, uint64_t engine, uint32_t ctx_id,
+			      struct intel_execution_engine2 *e)
+{
+	DEFINE_CONTEXT_ENGINES_PARAM(engines, param, ctx_id, GEM_MAX_ENGINES);
+
+	/* a bit paranoic */
+	igt_assert(e);
+
+	if (gem_topology_get_param(fd, &param) || !param.size)
+		return -EINVAL;
+
+	e->class = engines.engines[engine].engine_class;
+	e->instance = engines.engines[engine].engine_instance;
+
+	return 0;
+}
+
+void gem_context_set_all_engines(int fd, uint32_t ctx)
+{
+	DEFINE_CONTEXT_ENGINES_PARAM(engines, param, ctx, GEM_MAX_ENGINES);
+	struct intel_engine_data engine_data = { };
+
+	if (!gem_topology_get_param(fd, &param) && !param.size) {
+		query_engine_list(fd, &engine_data);
+		ctx_map_engines(fd, &engine_data, &param);
+	}
+}
+
+bool gem_has_engine_topology(int fd)
+{
+	struct drm_i915_gem_context_param param = {
+		.param = I915_CONTEXT_PARAM_ENGINES,
+	};
+
+	return !__gem_context_get_param(fd, &param);
+}
diff --git a/lib/i915/gem_engine_topology.h b/lib/i915/gem_engine_topology.h
new file mode 100644
index 000000000000..2415fd1e379b
--- /dev/null
+++ b/lib/i915/gem_engine_topology.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef GEM_ENGINE_TOPOLOGY_H
+#define GEM_ENGINE_TOPOLOGY_H
+
+#include "igt_gt.h"
+#include "i915_drm.h"
+
+#define GEM_MAX_ENGINES		I915_EXEC_RING_MASK + 1
+
+struct intel_engine_data {
+	uint32_t nengines;
+	uint32_t n;
+	struct intel_execution_engine2 *current_engine;
+	struct intel_execution_engine2 engines[GEM_MAX_ENGINES];
+};
+
+bool gem_has_engine_topology(int fd);
+struct intel_engine_data intel_init_engine_list(int fd, uint32_t ctx_id);
+
+/* iteration functions */
+struct intel_execution_engine2 *
+intel_get_current_engine(struct intel_engine_data *ed);
+
+struct intel_execution_engine2 *
+intel_get_current_physical_engine(struct intel_engine_data *ed);
+
+void intel_next_engine(struct intel_engine_data *ed);
+
+int gem_context_lookup_engine(int fd, uint64_t engine, uint32_t ctx_id,
+			      struct intel_execution_engine2 *e);
+
+void gem_context_set_all_engines(int fd, uint32_t ctx);
+
+#define __for_each_static_engine(e__) \
+	for ((e__) = intel_execution_engines2; (e__)->name; (e__)++)
+
+#define for_each_context_engine(fd__, ctx__, e__) \
+	for (struct intel_engine_data i__ = intel_init_engine_list(fd__, ctx__); \
+	     ((e__) = intel_get_current_engine(&i__)); \
+	     intel_next_engine(&i__))
+
+/* needs to replace "for_each_physical_engine" when conflicts are fixed */
+#define __for_each_physical_engine(fd__, e__) \
+	for (struct intel_engine_data i__ = intel_init_engine_list(fd__, 0); \
+	     ((e__) = intel_get_current_physical_engine(&i__)); \
+	     intel_next_engine(&i__))
+
+#endif /* GEM_ENGINE_TOPOLOGY_H */
diff --git a/lib/igt.h b/lib/igt.h
index 2ae43c30ff61..82cdd57a4deb 100644
--- a/lib/igt.h
+++ b/lib/igt.h
@@ -54,5 +54,6 @@
 #include "media_spin.h"
 #include "rendercopy.h"
 #include "i915/gem_mman.h"
+#include "i915/gem_engine_topology.h"
 
 #endif /* IGT_H */
diff --git a/lib/igt_gt.h b/lib/igt_gt.h
index 475c0b3c3cc6..52b2f1ea95a5 100644
--- a/lib/igt_gt.h
+++ b/lib/igt_gt.h
@@ -95,6 +95,8 @@ extern const struct intel_execution_engine2 {
 	const char *name;
 	int class;
 	int instance;
+	uint64_t flags;
+	bool is_virtual;
 } intel_execution_engines2[];
 
 unsigned int
diff --git a/lib/meson.build b/lib/meson.build
index 8073686867d4..b6d8e6ca5a7e 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -5,6 +5,7 @@ lib_sources = [
 	'i915/gem_submission.c',
 	'i915/gem_ring.c',
 	'i915/gem_mman.c',
+	'i915/gem_engine_topology.c',
 	'igt_color_encoding.c',
 	'igt_debugfs.c',
 	'igt_device.c',
-- 
2.20.1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 32+ messages in thread
* [CI i-g-t 03/14] lib: igt_gt: add execution buffer flags to class helper
  2019-05-22 13:50 ` [igt-dev] " Tvrtko Ursulin
@ 2019-05-22 13:50   ` Tvrtko Ursulin
  -1 siblings, 0 replies; 32+ messages in thread
From: Tvrtko Ursulin @ 2019-05-22 13:50 UTC (permalink / raw)
  To: igt-dev; +Cc: Intel-gfx

From: Andi Shyti <andi.shyti@intel.com>

we have a "class/instance to eb flags" helper but not the
opposite, add it.

Suggested-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 lib/igt_gt.c | 18 ++++++++++++++++++
 lib/igt_gt.h |  2 ++
 2 files changed, 20 insertions(+)

diff --git a/lib/igt_gt.c b/lib/igt_gt.c
index a2eaadf5cc8e..59b62242749e 100644
--- a/lib/igt_gt.c
+++ b/lib/igt_gt.c
@@ -41,6 +41,7 @@
 #include "intel_reg.h"
 #include "intel_chipset.h"
 #include "igt_dummyload.h"
+#include "i915/gem_engine_topology.h"
 
 /**
  * SECTION:igt_gt
@@ -586,6 +587,23 @@ const struct intel_execution_engine2 intel_execution_engines2[] = {
 	{ }
 };
 
+int gem_execbuf_flags_to_engine_class(unsigned int flags)
+{
+	switch (flags & 0x3f) {
+	case I915_EXEC_DEFAULT:
+	case I915_EXEC_RENDER:
+		return I915_ENGINE_CLASS_RENDER;
+	case I915_EXEC_BLT:
+		return I915_ENGINE_CLASS_COPY;
+	case I915_EXEC_BSD:
+		return I915_ENGINE_CLASS_VIDEO;
+	case I915_EXEC_VEBOX:
+		return I915_ENGINE_CLASS_VIDEO_ENHANCE;
+	default:
+		igt_assert(0);
+	}
+}
+
 unsigned int
 gem_class_instance_to_eb_flags(int gem_fd,
 			       enum drm_i915_gem_engine_class class,
diff --git a/lib/igt_gt.h b/lib/igt_gt.h
index 52b2f1ea95a5..8ceed14288c7 100644
--- a/lib/igt_gt.h
+++ b/lib/igt_gt.h
@@ -99,6 +99,8 @@ extern const struct intel_execution_engine2 {
 	bool is_virtual;
 } intel_execution_engines2[];
 
+int gem_execbuf_flags_to_engine_class(unsigned int flags);
+
 unsigned int
 gem_class_instance_to_eb_flags(int gem_fd,
 			       enum drm_i915_gem_engine_class class,
-- 
2.20.1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 32+ messages in thread
* [igt-dev] [CI i-g-t 03/14] lib: igt_gt: add execution buffer flags to class helper
@ 2019-05-22 13:50   ` Tvrtko Ursulin
  0 siblings, 0 replies; 32+ messages in thread
From: Tvrtko Ursulin @ 2019-05-22 13:50 UTC (permalink / raw)
  To: igt-dev; +Cc: Intel-gfx

From: Andi Shyti <andi.shyti@intel.com>

we have a "class/instance to eb flags" helper but not the
opposite, add it.

Suggested-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 lib/igt_gt.c | 18 ++++++++++++++++++
 lib/igt_gt.h |  2 ++
 2 files changed, 20 insertions(+)

diff --git a/lib/igt_gt.c b/lib/igt_gt.c
index a2eaadf5cc8e..59b62242749e 100644
--- a/lib/igt_gt.c
+++ b/lib/igt_gt.c
@@ -41,6 +41,7 @@
 #include "intel_reg.h"
 #include "intel_chipset.h"
 #include "igt_dummyload.h"
+#include "i915/gem_engine_topology.h"
 
 /**
  * SECTION:igt_gt
@@ -586,6 +587,23 @@ const struct intel_execution_engine2 intel_execution_engines2[] = {
 	{ }
 };
 
+int gem_execbuf_flags_to_engine_class(unsigned int flags)
+{
+	switch (flags & 0x3f) {
+	case I915_EXEC_DEFAULT:
+	case I915_EXEC_RENDER:
+		return I915_ENGINE_CLASS_RENDER;
+	case I915_EXEC_BLT:
+		return I915_ENGINE_CLASS_COPY;
+	case I915_EXEC_BSD:
+		return I915_ENGINE_CLASS_VIDEO;
+	case I915_EXEC_VEBOX:
+		return I915_ENGINE_CLASS_VIDEO_ENHANCE;
+	default:
+		igt_assert(0);
+	}
+}
+
 unsigned int
 gem_class_instance_to_eb_flags(int gem_fd,
 			       enum drm_i915_gem_engine_class class,
diff --git a/lib/igt_gt.h b/lib/igt_gt.h
index 52b2f1ea95a5..8ceed14288c7 100644
--- a/lib/igt_gt.h
+++ b/lib/igt_gt.h
@@ -99,6 +99,8 @@ extern const struct intel_execution_engine2 {
 	bool is_virtual;
 } intel_execution_engines2[];
 
+int gem_execbuf_flags_to_engine_class(unsigned int flags);
+
 unsigned int
 gem_class_instance_to_eb_flags(int gem_fd,
 			       enum drm_i915_gem_engine_class class,
-- 
2.20.1

_______________________________________________
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igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply related	[flat|nested] 32+ messages in thread
* [CI i-g-t 04/14] lib: igt_gt: make gem_engine_can_store_dword() check engine class
  2019-05-22 13:50 ` [igt-dev] " Tvrtko Ursulin
@ 2019-05-22 13:50   ` Tvrtko Ursulin
  -1 siblings, 0 replies; 32+ messages in thread
From: Tvrtko Ursulin @ 2019-05-22 13:50 UTC (permalink / raw)
  To: igt-dev; +Cc: Intel-gfx

From: Andi Shyti <andi.shyti@intel.com>

Engines referred by class and instance are getting more popular,
gem_engine_can_store_dword() should handle the situation.

Suggested-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 lib/igt_gt.c | 12 +++++++++---
 lib/igt_gt.h |  1 +
 2 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/lib/igt_gt.c b/lib/igt_gt.c
index 59b62242749e..5e5b9bef03dc 100644
--- a/lib/igt_gt.c
+++ b/lib/igt_gt.c
@@ -557,7 +557,7 @@ const struct intel_execution_engine intel_execution_engines[] = {
 	{ NULL, 0, 0 }
 };
 
-bool gem_can_store_dword(int fd, unsigned int engine)
+bool gem_class_can_store_dword(int fd, int class)
 {
 	uint16_t devid = intel_get_drm_devid(fd);
 	const struct intel_device_info *info = intel_get_device_info(devid);
@@ -569,8 +569,8 @@ bool gem_can_store_dword(int fd, unsigned int engine)
 	if (gen == 3 && (info->is_grantsdale || info->is_alviso))
 		return false; /* only supports physical addresses */
 
-	if (gen == 6 && ((engine & 0x3f) == I915_EXEC_BSD))
-		return false; /* kills the machine! */
+	if (gen == 6 && class == I915_ENGINE_CLASS_VIDEO)
+		return false;
 
 	if (info->is_broadwater)
 		return false; /* Not sure yet... */
@@ -578,6 +578,12 @@ bool gem_can_store_dword(int fd, unsigned int engine)
 	return true;
 }
 
+bool gem_can_store_dword(int fd, unsigned int engine)
+{
+	return gem_class_can_store_dword(fd,
+				gem_execbuf_flags_to_engine_class(engine));
+}
+
 const struct intel_execution_engine2 intel_execution_engines2[] = {
 	{ "rcs0", I915_ENGINE_CLASS_RENDER, 0 },
 	{ "bcs0", I915_ENGINE_CLASS_COPY, 0 },
diff --git a/lib/igt_gt.h b/lib/igt_gt.h
index 8ceed14288c7..0b5c7fcb4c3c 100644
--- a/lib/igt_gt.h
+++ b/lib/igt_gt.h
@@ -90,6 +90,7 @@ bool gem_ring_is_physical_engine(int fd, unsigned int ring);
 bool gem_ring_has_physical_engine(int fd, unsigned int ring);
 
 bool gem_can_store_dword(int fd, unsigned int engine);
+bool gem_class_can_store_dword(int fd, int class);
 
 extern const struct intel_execution_engine2 {
 	const char *name;
-- 
2.20.1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 32+ messages in thread
* [igt-dev] [CI i-g-t 04/14] lib: igt_gt: make gem_engine_can_store_dword() check engine class
@ 2019-05-22 13:50   ` Tvrtko Ursulin
  0 siblings, 0 replies; 32+ messages in thread
From: Tvrtko Ursulin @ 2019-05-22 13:50 UTC (permalink / raw)
  To: igt-dev; +Cc: Intel-gfx

From: Andi Shyti <andi.shyti@intel.com>

Engines referred by class and instance are getting more popular,
gem_engine_can_store_dword() should handle the situation.

Suggested-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 lib/igt_gt.c | 12 +++++++++---
 lib/igt_gt.h |  1 +
 2 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/lib/igt_gt.c b/lib/igt_gt.c
index 59b62242749e..5e5b9bef03dc 100644
--- a/lib/igt_gt.c
+++ b/lib/igt_gt.c
@@ -557,7 +557,7 @@ const struct intel_execution_engine intel_execution_engines[] = {
 	{ NULL, 0, 0 }
 };
 
-bool gem_can_store_dword(int fd, unsigned int engine)
+bool gem_class_can_store_dword(int fd, int class)
 {
 	uint16_t devid = intel_get_drm_devid(fd);
 	const struct intel_device_info *info = intel_get_device_info(devid);
@@ -569,8 +569,8 @@ bool gem_can_store_dword(int fd, unsigned int engine)
 	if (gen == 3 && (info->is_grantsdale || info->is_alviso))
 		return false; /* only supports physical addresses */
 
-	if (gen == 6 && ((engine & 0x3f) == I915_EXEC_BSD))
-		return false; /* kills the machine! */
+	if (gen == 6 && class == I915_ENGINE_CLASS_VIDEO)
+		return false;
 
 	if (info->is_broadwater)
 		return false; /* Not sure yet... */
@@ -578,6 +578,12 @@ bool gem_can_store_dword(int fd, unsigned int engine)
 	return true;
 }
 
+bool gem_can_store_dword(int fd, unsigned int engine)
+{
+	return gem_class_can_store_dword(fd,
+				gem_execbuf_flags_to_engine_class(engine));
+}
+
 const struct intel_execution_engine2 intel_execution_engines2[] = {
 	{ "rcs0", I915_ENGINE_CLASS_RENDER, 0 },
 	{ "bcs0", I915_ENGINE_CLASS_COPY, 0 },
diff --git a/lib/igt_gt.h b/lib/igt_gt.h
index 8ceed14288c7..0b5c7fcb4c3c 100644
--- a/lib/igt_gt.h
+++ b/lib/igt_gt.h
@@ -90,6 +90,7 @@ bool gem_ring_is_physical_engine(int fd, unsigned int ring);
 bool gem_ring_has_physical_engine(int fd, unsigned int ring);
 
 bool gem_can_store_dword(int fd, unsigned int engine);
+bool gem_class_can_store_dword(int fd, int class);
 
 extern const struct intel_execution_engine2 {
 	const char *name;
-- 
2.20.1

_______________________________________________
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igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply related	[flat|nested] 32+ messages in thread
* [CI i-g-t 05/14] lib: igt_dummyload: use for_each_context_engine()
  2019-05-22 13:50 ` [igt-dev] " Tvrtko Ursulin
@ 2019-05-22 13:50   ` Tvrtko Ursulin
  -1 siblings, 0 replies; 32+ messages in thread
From: Tvrtko Ursulin @ 2019-05-22 13:50 UTC (permalink / raw)
  To: igt-dev; +Cc: Intel-gfx

From: Andi Shyti <andi.shyti@intel.com>

With the new getparam/setparam api, engines are mapped to
context. Use for_each_context_engine() to loop through existing
engines.

Suggested-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 lib/igt_dummyload.c | 29 ++++++++++++++++++++---------
 1 file changed, 20 insertions(+), 9 deletions(-)

diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
index 15d64fadc115..1e11ccd3de33 100644
--- a/lib/igt_dummyload.c
+++ b/lib/igt_dummyload.c
@@ -39,6 +39,7 @@
 #include "ioctl_wrappers.h"
 #include "sw_sync.h"
 #include "igt_vgem.h"
+#include "i915/gem_engine_topology.h"
 #include "i915/gem_mman.h"
 
 /**
@@ -77,7 +78,7 @@ emit_recursive_batch(igt_spin_t *spin,
 	struct drm_i915_gem_relocation_entry relocs[2], *r;
 	struct drm_i915_gem_execbuffer2 *execbuf;
 	struct drm_i915_gem_exec_object2 *obj;
-	unsigned int engines[16];
+	unsigned int flags[GEM_MAX_ENGINES];
 	unsigned int nengine;
 	int fence_fd = -1;
 	uint32_t *cs, *batch;
@@ -85,17 +86,17 @@ emit_recursive_batch(igt_spin_t *spin,
 
 	nengine = 0;
 	if (opts->engine == ALL_ENGINES) {
-		unsigned int engine;
+		struct intel_execution_engine2 *engine;
 
-		for_each_physical_engine(fd, engine) {
+		for_each_context_engine(fd, opts->ctx, engine) {
 			if (opts->flags & IGT_SPIN_POLL_RUN &&
-			    !gem_can_store_dword(fd, engine))
+			    !gem_class_can_store_dword(fd, engine->class))
 				continue;
 
-			engines[nengine++] = engine;
+			flags[nengine++] = engine->flags;
 		}
 	} else {
-		engines[nengine++] = opts->engine;
+		flags[nengine++] = opts->engine;
 	}
 	igt_require(nengine);
 
@@ -237,7 +238,7 @@ emit_recursive_batch(igt_spin_t *spin,
 
 	for (i = 0; i < nengine; i++) {
 		execbuf->flags &= ~ENGINE_MASK;
-		execbuf->flags |= engines[i];
+		execbuf->flags |= flags[i];
 
 		gem_execbuf_wr(fd, execbuf);
 
@@ -316,9 +317,19 @@ igt_spin_factory(int fd, const struct igt_spin_factory *opts)
 	igt_require_gem(fd);
 
 	if (opts->engine != ALL_ENGINES) {
-		gem_require_ring(fd, opts->engine);
+		struct intel_execution_engine2 e;
+		int class;
+
+		if (!gem_context_lookup_engine(fd, opts->engine,
+					       opts->ctx, &e)) {
+			class = e.class;
+		} else {
+			gem_require_ring(fd, opts->engine);
+			class = gem_execbuf_flags_to_engine_class(opts->engine);
+		}
+
 		if (opts->flags & IGT_SPIN_POLL_RUN)
-			igt_require(gem_can_store_dword(fd, opts->engine));
+			igt_require(gem_class_can_store_dword(fd, class));
 	}
 
 	spin = spin_create(fd, opts);
-- 
2.20.1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 32+ messages in thread
* [igt-dev] [CI i-g-t 05/14] lib: igt_dummyload: use for_each_context_engine()
@ 2019-05-22 13:50   ` Tvrtko Ursulin
  0 siblings, 0 replies; 32+ messages in thread
From: Tvrtko Ursulin @ 2019-05-22 13:50 UTC (permalink / raw)
  To: igt-dev; +Cc: Intel-gfx

From: Andi Shyti <andi.shyti@intel.com>

With the new getparam/setparam api, engines are mapped to
context. Use for_each_context_engine() to loop through existing
engines.

Suggested-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 lib/igt_dummyload.c | 29 ++++++++++++++++++++---------
 1 file changed, 20 insertions(+), 9 deletions(-)

diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
index 15d64fadc115..1e11ccd3de33 100644
--- a/lib/igt_dummyload.c
+++ b/lib/igt_dummyload.c
@@ -39,6 +39,7 @@
 #include "ioctl_wrappers.h"
 #include "sw_sync.h"
 #include "igt_vgem.h"
+#include "i915/gem_engine_topology.h"
 #include "i915/gem_mman.h"
 
 /**
@@ -77,7 +78,7 @@ emit_recursive_batch(igt_spin_t *spin,
 	struct drm_i915_gem_relocation_entry relocs[2], *r;
 	struct drm_i915_gem_execbuffer2 *execbuf;
 	struct drm_i915_gem_exec_object2 *obj;
-	unsigned int engines[16];
+	unsigned int flags[GEM_MAX_ENGINES];
 	unsigned int nengine;
 	int fence_fd = -1;
 	uint32_t *cs, *batch;
@@ -85,17 +86,17 @@ emit_recursive_batch(igt_spin_t *spin,
 
 	nengine = 0;
 	if (opts->engine == ALL_ENGINES) {
-		unsigned int engine;
+		struct intel_execution_engine2 *engine;
 
-		for_each_physical_engine(fd, engine) {
+		for_each_context_engine(fd, opts->ctx, engine) {
 			if (opts->flags & IGT_SPIN_POLL_RUN &&
-			    !gem_can_store_dword(fd, engine))
+			    !gem_class_can_store_dword(fd, engine->class))
 				continue;
 
-			engines[nengine++] = engine;
+			flags[nengine++] = engine->flags;
 		}
 	} else {
-		engines[nengine++] = opts->engine;
+		flags[nengine++] = opts->engine;
 	}
 	igt_require(nengine);
 
@@ -237,7 +238,7 @@ emit_recursive_batch(igt_spin_t *spin,
 
 	for (i = 0; i < nengine; i++) {
 		execbuf->flags &= ~ENGINE_MASK;
-		execbuf->flags |= engines[i];
+		execbuf->flags |= flags[i];
 
 		gem_execbuf_wr(fd, execbuf);
 
@@ -316,9 +317,19 @@ igt_spin_factory(int fd, const struct igt_spin_factory *opts)
 	igt_require_gem(fd);
 
 	if (opts->engine != ALL_ENGINES) {
-		gem_require_ring(fd, opts->engine);
+		struct intel_execution_engine2 e;
+		int class;
+
+		if (!gem_context_lookup_engine(fd, opts->engine,
+					       opts->ctx, &e)) {
+			class = e.class;
+		} else {
+			gem_require_ring(fd, opts->engine);
+			class = gem_execbuf_flags_to_engine_class(opts->engine);
+		}
+
 		if (opts->flags & IGT_SPIN_POLL_RUN)
-			igt_require(gem_can_store_dword(fd, opts->engine));
+			igt_require(gem_class_can_store_dword(fd, class));
 	}
 
 	spin = spin_create(fd, opts);
-- 
2.20.1

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply related	[flat|nested] 32+ messages in thread
* [CI i-g-t 06/14] test: perf_pmu: use the gem_engine_topology library
  2019-05-22 13:50 ` [igt-dev] " Tvrtko Ursulin
@ 2019-05-22 13:50   ` Tvrtko Ursulin
  -1 siblings, 0 replies; 32+ messages in thread
From: Tvrtko Ursulin @ 2019-05-22 13:50 UTC (permalink / raw)
  To: igt-dev; +Cc: Intel-gfx

From: Andi Shyti <andi.shyti@intel.com>

Replace the legacy for_each_engine* defines with the ones
implemented in the gem_engine_topology library.

Use whenever possible gem_engine_can_store_dword() that checks
class instead of flags.

Now the __for_each_engine_class_instance and
for_each_engine_class_instance are unused, remove them.

Suggested-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 lib/igt_gt.h     |   7 ---
 tests/perf_pmu.c | 110 ++++++++++++++++++++++++++---------------------
 2 files changed, 60 insertions(+), 57 deletions(-)

diff --git a/lib/igt_gt.h b/lib/igt_gt.h
index 0b5c7fcb4c3c..77318e2a82b8 100644
--- a/lib/igt_gt.h
+++ b/lib/igt_gt.h
@@ -119,11 +119,4 @@ void gem_require_engine(int gem_fd,
 	igt_require(gem_has_engine(gem_fd, class, instance));
 }
 
-#define __for_each_engine_class_instance(e__) \
-	for ((e__) = intel_execution_engines2; (e__)->name; (e__)++)
-
-#define for_each_engine_class_instance(fd__, e__) \
-	for ((e__) = intel_execution_engines2; (e__)->name; (e__)++) \
-		for_if (gem_has_engine((fd__), (e__)->class, (e__)->instance))
-
 #endif /* IGT_GT_H */
diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index e719a292a3d1..72b9166afb4c 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -82,7 +82,7 @@ init(int gem_fd, const struct intel_execution_engine2 *e, uint8_t sample)
 	if (fd < 0)
 		err = errno;
 
-	exists = gem_has_engine(gem_fd, e->class, e->instance);
+	exists = gem_context_has_engine(gem_fd, 0, e->flags);
 	if (intel_gen(intel_get_drm_devid(gem_fd)) < 6 &&
 	    sample == I915_SAMPLE_SEMA)
 		exists = false;
@@ -158,11 +158,6 @@ static unsigned int measured_usleep(unsigned int usec)
 	return igt_nsec_elapsed(&ts);
 }
 
-static unsigned int e2ring(int gem_fd, const struct intel_execution_engine2 *e)
-{
-	return gem_class_instance_to_eb_flags(gem_fd, e->class, e->instance);
-}
-
 #define TEST_BUSY (1)
 #define FLAG_SYNC (2)
 #define TEST_TRAILING_IDLE (4)
@@ -170,14 +165,15 @@ static unsigned int e2ring(int gem_fd, const struct intel_execution_engine2 *e)
 #define FLAG_LONG (16)
 #define FLAG_HANG (32)
 
-static igt_spin_t * __spin_poll(int fd, uint32_t ctx, unsigned long flags)
+static igt_spin_t * __spin_poll(int fd, uint32_t ctx,
+				const struct intel_execution_engine2 *e)
 {
 	struct igt_spin_factory opts = {
 		.ctx = ctx,
-		.engine = flags,
+		.engine = e->flags,
 	};
 
-	if (gem_can_store_dword(fd, flags))
+	if (gem_class_can_store_dword(fd, e->class))
 		opts.flags |= IGT_SPIN_POLL_RUN;
 
 	return __igt_spin_factory(fd, &opts);
@@ -209,20 +205,34 @@ static unsigned long __spin_wait(int fd, igt_spin_t *spin)
 	return igt_nsec_elapsed(&start);
 }
 
-static igt_spin_t * __spin_sync(int fd, uint32_t ctx, unsigned long flags)
+static igt_spin_t * __spin_sync(int fd, uint32_t ctx,
+				const struct intel_execution_engine2 *e)
 {
-	igt_spin_t *spin = __spin_poll(fd, ctx, flags);
+	igt_spin_t *spin = __spin_poll(fd, ctx, e);
 
 	__spin_wait(fd, spin);
 
 	return spin;
 }
 
-static igt_spin_t * spin_sync(int fd, uint32_t ctx, unsigned long flags)
+static igt_spin_t * spin_sync(int fd, uint32_t ctx,
+			      const struct intel_execution_engine2 *e)
 {
 	igt_require_gem(fd);
 
-	return __spin_sync(fd, ctx, flags);
+	return __spin_sync(fd, ctx, e);
+}
+
+static igt_spin_t * spin_sync_flags(int fd, uint32_t ctx, unsigned int flags)
+{
+	struct intel_execution_engine2 e = { };
+
+	e.class = gem_execbuf_flags_to_engine_class(flags);
+	e.instance = (flags & (I915_EXEC_BSD_MASK | I915_EXEC_RING_MASK)) ==
+		     (I915_EXEC_BSD | I915_EXEC_BSD_RING2) ? 1 : 0;
+	e.flags = flags;
+
+	return spin_sync(fd, ctx, &e);
 }
 
 static void end_spin(int fd, igt_spin_t *spin, unsigned int flags)
@@ -267,7 +277,7 @@ single(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
 	fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
 
 	if (flags & TEST_BUSY)
-		spin = spin_sync(gem_fd, 0, e2ring(gem_fd, e));
+		spin = spin_sync(gem_fd, 0, e);
 	else
 		spin = NULL;
 
@@ -316,7 +326,7 @@ busy_start(int gem_fd, const struct intel_execution_engine2 *e)
 	 */
 	sleep(2);
 
-	spin = __spin_sync(gem_fd, 0, e2ring(gem_fd, e));
+	spin = __spin_sync(gem_fd, 0, e);
 
 	fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
 
@@ -347,6 +357,7 @@ busy_double_start(int gem_fd, const struct intel_execution_engine2 *e)
 	int fd;
 
 	ctx = gem_context_create(gem_fd);
+	gem_context_set_all_engines(gem_fd, ctx);
 
 	/*
 	 * Defeat the busy stats delayed disable, we need to guarantee we are
@@ -359,11 +370,11 @@ busy_double_start(int gem_fd, const struct intel_execution_engine2 *e)
 	 * re-submission in execlists mode. Make sure busyness is correctly
 	 * reported with the engine busy, and after the engine went idle.
 	 */
-	spin[0] = __spin_sync(gem_fd, 0, e2ring(gem_fd, e));
+	spin[0] = __spin_sync(gem_fd, 0, e);
 	usleep(500e3);
 	spin[1] = __igt_spin_new(gem_fd,
 				 .ctx = ctx,
-				 .engine = e2ring(gem_fd, e));
+				 .engine = e->flags);
 
 	/*
 	 * Open PMU as fast as possible after the second spin batch in attempt
@@ -424,7 +435,7 @@ static void
 busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 	       const unsigned int num_engines, unsigned int flags)
 {
-	const struct intel_execution_engine2 *e_;
+	struct intel_execution_engine2 *e_;
 	uint64_t tval[2][num_engines];
 	unsigned int busy_idx = 0, i;
 	uint64_t val[num_engines];
@@ -434,8 +445,8 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 
 	i = 0;
 	fd[0] = -1;
-	for_each_engine_class_instance(gem_fd, e_) {
-		if (e == e_)
+	__for_each_physical_engine(gem_fd, e_) {
+		if (e->class == e_->class && e->instance == e_->instance)
 			busy_idx = i;
 
 		fd[i++] = open_group(I915_PMU_ENGINE_BUSY(e_->class,
@@ -445,7 +456,7 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 
 	igt_assert_eq(i, num_engines);
 
-	spin = spin_sync(gem_fd, 0, e2ring(gem_fd, e));
+	spin = spin_sync(gem_fd, 0, e);
 	pmu_read_multi(fd[0], num_engines, tval[0]);
 	slept = measured_usleep(batch_duration_ns / 1000);
 	if (flags & TEST_TRAILING_IDLE)
@@ -478,7 +489,7 @@ __submit_spin(int gem_fd, igt_spin_t *spin,
 	struct drm_i915_gem_execbuffer2 eb = spin->execbuf;
 
 	eb.flags &= ~(0x3f | I915_EXEC_BSD_MASK);
-	eb.flags |= e2ring(gem_fd, e) | I915_EXEC_NO_RELOC;
+	eb.flags |= e->flags | I915_EXEC_NO_RELOC;
 	eb.batch_start_offset += offset;
 
 	gem_execbuf(gem_fd, &eb);
@@ -488,7 +499,7 @@ static void
 most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 		    const unsigned int num_engines, unsigned int flags)
 {
-	const struct intel_execution_engine2 *e_;
+	struct intel_execution_engine2 *e_;
 	uint64_t tval[2][num_engines];
 	uint64_t val[num_engines];
 	int fd[num_engines];
@@ -497,13 +508,13 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 	unsigned int idle_idx, i;
 
 	i = 0;
-	for_each_engine_class_instance(gem_fd, e_) {
-		if (e == e_)
+	__for_each_physical_engine(gem_fd, e_) {
+		if (e->class == e_->class && e->instance == e_->instance)
 			idle_idx = i;
 		else if (spin)
 			__submit_spin(gem_fd, spin, e_, 64);
 		else
-			spin = __spin_poll(gem_fd, 0, e2ring(gem_fd, e_));
+			spin = __spin_poll(gem_fd, 0, e_);
 
 		val[i++] = I915_PMU_ENGINE_BUSY(e_->class, e_->instance);
 	}
@@ -545,7 +556,7 @@ static void
 all_busy_check_all(int gem_fd, const unsigned int num_engines,
 		   unsigned int flags)
 {
-	const struct intel_execution_engine2 *e;
+	struct intel_execution_engine2 *e;
 	uint64_t tval[2][num_engines];
 	uint64_t val[num_engines];
 	int fd[num_engines];
@@ -554,11 +565,11 @@ all_busy_check_all(int gem_fd, const unsigned int num_engines,
 	unsigned int i;
 
 	i = 0;
-	for_each_engine_class_instance(gem_fd, e) {
+	__for_each_physical_engine(gem_fd, e) {
 		if (spin)
 			__submit_spin(gem_fd, spin, e, 64);
 		else
-			spin = __spin_poll(gem_fd, 0, e2ring(gem_fd, e));
+			spin = __spin_poll(gem_fd, 0, e);
 
 		val[i++] = I915_PMU_ENGINE_BUSY(e->class, e->instance);
 	}
@@ -602,7 +613,7 @@ no_sema(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
 	open_group(I915_PMU_ENGINE_WAIT(e->class, e->instance), fd);
 
 	if (flags & TEST_BUSY)
-		spin = spin_sync(gem_fd, 0, e2ring(gem_fd, e));
+		spin = spin_sync(gem_fd, 0, e);
 	else
 		spin = NULL;
 
@@ -689,7 +700,7 @@ sema_wait(int gem_fd, const struct intel_execution_engine2 *e,
 
 	eb.buffer_count = 2;
 	eb.buffers_ptr = to_user_pointer(obj);
-	eb.flags = e2ring(gem_fd, e);
+	eb.flags = e->flags;
 
 	/**
 	 * Start the semaphore wait PMU and after some known time let the above
@@ -845,7 +856,7 @@ event_wait(int gem_fd, const struct intel_execution_engine2 *e)
 
 	eb.buffer_count = 1;
 	eb.buffers_ptr = to_user_pointer(&obj);
-	eb.flags = e2ring(gem_fd, e) | I915_EXEC_SECURE;
+	eb.flags = e->flags | I915_EXEC_SECURE;
 
 	for_each_pipe_with_valid_output(&data.display, p, output) {
 		struct igt_helper_process waiter = { };
@@ -936,7 +947,7 @@ multi_client(int gem_fd, const struct intel_execution_engine2 *e)
 	 */
 	fd[1] = open_pmu(config);
 
-	spin = spin_sync(gem_fd, 0, e2ring(gem_fd, e));
+	spin = spin_sync(gem_fd, 0, e);
 
 	val[0] = val[1] = __pmu_read_single(fd[0], &ts[0]);
 	slept[1] = measured_usleep(batch_duration_ns / 1000);
@@ -1052,8 +1063,8 @@ static void cpu_hotplug(int gem_fd)
 	 * Create two spinners so test can ensure shorter gaps in engine
 	 * busyness as it is terminating one and re-starting the other.
 	 */
-	spin[0] = igt_spin_new(gem_fd, .engine = I915_EXEC_RENDER);
-	spin[1] = __igt_spin_new(gem_fd, .engine = I915_EXEC_RENDER);
+	spin[0] = igt_spin_new(gem_fd, .engine = I915_EXEC_DEFAULT);
+	spin[1] = __igt_spin_new(gem_fd, .engine = I915_EXEC_DEFAULT);
 
 	val = __pmu_read_single(fd, &ts[0]);
 
@@ -1137,7 +1148,7 @@ static void cpu_hotplug(int gem_fd)
 
 		igt_spin_free(gem_fd, spin[cur]);
 		spin[cur] = __igt_spin_new(gem_fd,
-					   .engine = I915_EXEC_RENDER);
+					   .engine = I915_EXEC_DEFAULT);
 		cur ^= 1;
 	}
 
@@ -1175,7 +1186,7 @@ test_interrupts(int gem_fd)
 	/* Queue spinning batches. */
 	for (int i = 0; i < target; i++) {
 		spin[i] = __igt_spin_new(gem_fd,
-					 .engine = I915_EXEC_RENDER,
+					 .engine = I915_EXEC_DEFAULT,
 					 .flags = IGT_SPIN_FENCE_OUT);
 		if (i == 0) {
 			fence_fd = spin[i]->out_fence;
@@ -1301,7 +1312,7 @@ test_frequency(int gem_fd)
 	igt_require(igt_sysfs_get_u32(sysfs, "gt_boost_freq_mhz") == min_freq);
 
 	gem_quiescent_gpu(gem_fd); /* Idle to be sure the change takes effect */
-	spin = spin_sync(gem_fd, 0, I915_EXEC_RENDER);
+	spin = spin_sync_flags(gem_fd, 0, I915_EXEC_DEFAULT);
 
 	slept = pmu_read_multi(fd, 2, start);
 	measured_usleep(batch_duration_ns / 1000);
@@ -1327,7 +1338,7 @@ test_frequency(int gem_fd)
 	igt_require(igt_sysfs_get_u32(sysfs, "gt_min_freq_mhz") == max_freq);
 
 	gem_quiescent_gpu(gem_fd);
-	spin = spin_sync(gem_fd, 0, I915_EXEC_RENDER);
+	spin = spin_sync_flags(gem_fd, 0, I915_EXEC_DEFAULT);
 
 	slept = pmu_read_multi(fd, 2, start);
 	measured_usleep(batch_duration_ns / 1000);
@@ -1458,14 +1469,14 @@ test_enable_race(int gem_fd, const struct intel_execution_engine2 *e)
 	int fd;
 
 	igt_require(gem_has_execlists(gem_fd));
-	igt_require(gem_has_engine(gem_fd, e->class, e->instance));
+	igt_require(gem_context_has_engine(gem_fd, 0, e->flags));
 
 	obj.handle = gem_create(gem_fd, 4096);
 	gem_write(gem_fd, obj.handle, 0, &bbend, sizeof(bbend));
 
 	eb.buffer_count = 1;
 	eb.buffers_ptr = to_user_pointer(&obj);
-	eb.flags = e2ring(gem_fd, e);
+	eb.flags = e->flags;
 
 	/*
 	 * This test is probabilistic so run in a few times to increase the
@@ -1562,7 +1573,7 @@ accuracy(int gem_fd, const struct intel_execution_engine2 *e,
 		igt_spin_t *spin;
 
 		/* Allocate our spin batch and idle it. */
-		spin = igt_spin_new(gem_fd, .engine = e2ring(gem_fd, e));
+		spin = igt_spin_new(gem_fd, .engine = e->flags);
 		igt_spin_end(spin);
 		gem_sync(gem_fd, spin->handle);
 
@@ -1666,7 +1677,7 @@ igt_main
 				I915_PMU_LAST - __I915_PMU_OTHER(0) + 1;
 	unsigned int num_engines = 0;
 	int fd = -1;
-	const struct intel_execution_engine2 *e;
+	struct intel_execution_engine2 *e;
 	unsigned int i;
 
 	igt_fixture {
@@ -1675,7 +1686,7 @@ igt_main
 		igt_require_gem(fd);
 		igt_require(i915_type_id() > 0);
 
-		for_each_engine_class_instance(fd, e)
+		__for_each_physical_engine(fd, e)
 			num_engines++;
 	}
 
@@ -1685,7 +1696,7 @@ igt_main
 	igt_subtest("invalid-init")
 		invalid_init();
 
-	__for_each_engine_class_instance(e) {
+	__for_each_physical_engine(fd, e) {
 		const unsigned int pct[] = { 2, 50, 98 };
 
 		/**
@@ -1703,7 +1714,7 @@ igt_main
 
 		igt_subtest_group {
 			igt_fixture {
-				gem_require_engine(fd, e->class, e->instance);
+				gem_context_has_engine(fd, 0, e->flags);
 			}
 
 			/**
@@ -1889,12 +1900,11 @@ igt_main
 			gem_quiescent_gpu(fd);
 		}
 
-		__for_each_engine_class_instance(e) {
+		__for_each_physical_engine(render_fd, e) {
 			igt_subtest_group {
 				igt_fixture {
-					gem_require_engine(render_fd,
-							   e->class,
-							   e->instance);
+					gem_context_has_engine(render_fd,
+							   0, e->flags);
 				}
 
 				igt_subtest_f("render-node-busy-%s", e->name)
-- 
2.20.1

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^ permalink raw reply related	[flat|nested] 32+ messages in thread
* [Intel-gfx] [CI i-g-t 06/14] test: perf_pmu: use the gem_engine_topology library
@ 2019-05-22 13:50   ` Tvrtko Ursulin
  0 siblings, 0 replies; 32+ messages in thread
From: Tvrtko Ursulin @ 2019-05-22 13:50 UTC (permalink / raw)
  To: igt-dev; +Cc: Intel-gfx

From: Andi Shyti <andi.shyti@intel.com>

Replace the legacy for_each_engine* defines with the ones
implemented in the gem_engine_topology library.

Use whenever possible gem_engine_can_store_dword() that checks
class instead of flags.

Now the __for_each_engine_class_instance and
for_each_engine_class_instance are unused, remove them.

Suggested-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 lib/igt_gt.h     |   7 ---
 tests/perf_pmu.c | 110 ++++++++++++++++++++++++++---------------------
 2 files changed, 60 insertions(+), 57 deletions(-)

diff --git a/lib/igt_gt.h b/lib/igt_gt.h
index 0b5c7fcb4c3c..77318e2a82b8 100644
--- a/lib/igt_gt.h
+++ b/lib/igt_gt.h
@@ -119,11 +119,4 @@ void gem_require_engine(int gem_fd,
 	igt_require(gem_has_engine(gem_fd, class, instance));
 }
 
-#define __for_each_engine_class_instance(e__) \
-	for ((e__) = intel_execution_engines2; (e__)->name; (e__)++)
-
-#define for_each_engine_class_instance(fd__, e__) \
-	for ((e__) = intel_execution_engines2; (e__)->name; (e__)++) \
-		for_if (gem_has_engine((fd__), (e__)->class, (e__)->instance))
-
 #endif /* IGT_GT_H */
diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index e719a292a3d1..72b9166afb4c 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -82,7 +82,7 @@ init(int gem_fd, const struct intel_execution_engine2 *e, uint8_t sample)
 	if (fd < 0)
 		err = errno;
 
-	exists = gem_has_engine(gem_fd, e->class, e->instance);
+	exists = gem_context_has_engine(gem_fd, 0, e->flags);
 	if (intel_gen(intel_get_drm_devid(gem_fd)) < 6 &&
 	    sample == I915_SAMPLE_SEMA)
 		exists = false;
@@ -158,11 +158,6 @@ static unsigned int measured_usleep(unsigned int usec)
 	return igt_nsec_elapsed(&ts);
 }
 
-static unsigned int e2ring(int gem_fd, const struct intel_execution_engine2 *e)
-{
-	return gem_class_instance_to_eb_flags(gem_fd, e->class, e->instance);
-}
-
 #define TEST_BUSY (1)
 #define FLAG_SYNC (2)
 #define TEST_TRAILING_IDLE (4)
@@ -170,14 +165,15 @@ static unsigned int e2ring(int gem_fd, const struct intel_execution_engine2 *e)
 #define FLAG_LONG (16)
 #define FLAG_HANG (32)
 
-static igt_spin_t * __spin_poll(int fd, uint32_t ctx, unsigned long flags)
+static igt_spin_t * __spin_poll(int fd, uint32_t ctx,
+				const struct intel_execution_engine2 *e)
 {
 	struct igt_spin_factory opts = {
 		.ctx = ctx,
-		.engine = flags,
+		.engine = e->flags,
 	};
 
-	if (gem_can_store_dword(fd, flags))
+	if (gem_class_can_store_dword(fd, e->class))
 		opts.flags |= IGT_SPIN_POLL_RUN;
 
 	return __igt_spin_factory(fd, &opts);
@@ -209,20 +205,34 @@ static unsigned long __spin_wait(int fd, igt_spin_t *spin)
 	return igt_nsec_elapsed(&start);
 }
 
-static igt_spin_t * __spin_sync(int fd, uint32_t ctx, unsigned long flags)
+static igt_spin_t * __spin_sync(int fd, uint32_t ctx,
+				const struct intel_execution_engine2 *e)
 {
-	igt_spin_t *spin = __spin_poll(fd, ctx, flags);
+	igt_spin_t *spin = __spin_poll(fd, ctx, e);
 
 	__spin_wait(fd, spin);
 
 	return spin;
 }
 
-static igt_spin_t * spin_sync(int fd, uint32_t ctx, unsigned long flags)
+static igt_spin_t * spin_sync(int fd, uint32_t ctx,
+			      const struct intel_execution_engine2 *e)
 {
 	igt_require_gem(fd);
 
-	return __spin_sync(fd, ctx, flags);
+	return __spin_sync(fd, ctx, e);
+}
+
+static igt_spin_t * spin_sync_flags(int fd, uint32_t ctx, unsigned int flags)
+{
+	struct intel_execution_engine2 e = { };
+
+	e.class = gem_execbuf_flags_to_engine_class(flags);
+	e.instance = (flags & (I915_EXEC_BSD_MASK | I915_EXEC_RING_MASK)) ==
+		     (I915_EXEC_BSD | I915_EXEC_BSD_RING2) ? 1 : 0;
+	e.flags = flags;
+
+	return spin_sync(fd, ctx, &e);
 }
 
 static void end_spin(int fd, igt_spin_t *spin, unsigned int flags)
@@ -267,7 +277,7 @@ single(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
 	fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
 
 	if (flags & TEST_BUSY)
-		spin = spin_sync(gem_fd, 0, e2ring(gem_fd, e));
+		spin = spin_sync(gem_fd, 0, e);
 	else
 		spin = NULL;
 
@@ -316,7 +326,7 @@ busy_start(int gem_fd, const struct intel_execution_engine2 *e)
 	 */
 	sleep(2);
 
-	spin = __spin_sync(gem_fd, 0, e2ring(gem_fd, e));
+	spin = __spin_sync(gem_fd, 0, e);
 
 	fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
 
@@ -347,6 +357,7 @@ busy_double_start(int gem_fd, const struct intel_execution_engine2 *e)
 	int fd;
 
 	ctx = gem_context_create(gem_fd);
+	gem_context_set_all_engines(gem_fd, ctx);
 
 	/*
 	 * Defeat the busy stats delayed disable, we need to guarantee we are
@@ -359,11 +370,11 @@ busy_double_start(int gem_fd, const struct intel_execution_engine2 *e)
 	 * re-submission in execlists mode. Make sure busyness is correctly
 	 * reported with the engine busy, and after the engine went idle.
 	 */
-	spin[0] = __spin_sync(gem_fd, 0, e2ring(gem_fd, e));
+	spin[0] = __spin_sync(gem_fd, 0, e);
 	usleep(500e3);
 	spin[1] = __igt_spin_new(gem_fd,
 				 .ctx = ctx,
-				 .engine = e2ring(gem_fd, e));
+				 .engine = e->flags);
 
 	/*
 	 * Open PMU as fast as possible after the second spin batch in attempt
@@ -424,7 +435,7 @@ static void
 busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 	       const unsigned int num_engines, unsigned int flags)
 {
-	const struct intel_execution_engine2 *e_;
+	struct intel_execution_engine2 *e_;
 	uint64_t tval[2][num_engines];
 	unsigned int busy_idx = 0, i;
 	uint64_t val[num_engines];
@@ -434,8 +445,8 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 
 	i = 0;
 	fd[0] = -1;
-	for_each_engine_class_instance(gem_fd, e_) {
-		if (e == e_)
+	__for_each_physical_engine(gem_fd, e_) {
+		if (e->class == e_->class && e->instance == e_->instance)
 			busy_idx = i;
 
 		fd[i++] = open_group(I915_PMU_ENGINE_BUSY(e_->class,
@@ -445,7 +456,7 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 
 	igt_assert_eq(i, num_engines);
 
-	spin = spin_sync(gem_fd, 0, e2ring(gem_fd, e));
+	spin = spin_sync(gem_fd, 0, e);
 	pmu_read_multi(fd[0], num_engines, tval[0]);
 	slept = measured_usleep(batch_duration_ns / 1000);
 	if (flags & TEST_TRAILING_IDLE)
@@ -478,7 +489,7 @@ __submit_spin(int gem_fd, igt_spin_t *spin,
 	struct drm_i915_gem_execbuffer2 eb = spin->execbuf;
 
 	eb.flags &= ~(0x3f | I915_EXEC_BSD_MASK);
-	eb.flags |= e2ring(gem_fd, e) | I915_EXEC_NO_RELOC;
+	eb.flags |= e->flags | I915_EXEC_NO_RELOC;
 	eb.batch_start_offset += offset;
 
 	gem_execbuf(gem_fd, &eb);
@@ -488,7 +499,7 @@ static void
 most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 		    const unsigned int num_engines, unsigned int flags)
 {
-	const struct intel_execution_engine2 *e_;
+	struct intel_execution_engine2 *e_;
 	uint64_t tval[2][num_engines];
 	uint64_t val[num_engines];
 	int fd[num_engines];
@@ -497,13 +508,13 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 	unsigned int idle_idx, i;
 
 	i = 0;
-	for_each_engine_class_instance(gem_fd, e_) {
-		if (e == e_)
+	__for_each_physical_engine(gem_fd, e_) {
+		if (e->class == e_->class && e->instance == e_->instance)
 			idle_idx = i;
 		else if (spin)
 			__submit_spin(gem_fd, spin, e_, 64);
 		else
-			spin = __spin_poll(gem_fd, 0, e2ring(gem_fd, e_));
+			spin = __spin_poll(gem_fd, 0, e_);
 
 		val[i++] = I915_PMU_ENGINE_BUSY(e_->class, e_->instance);
 	}
@@ -545,7 +556,7 @@ static void
 all_busy_check_all(int gem_fd, const unsigned int num_engines,
 		   unsigned int flags)
 {
-	const struct intel_execution_engine2 *e;
+	struct intel_execution_engine2 *e;
 	uint64_t tval[2][num_engines];
 	uint64_t val[num_engines];
 	int fd[num_engines];
@@ -554,11 +565,11 @@ all_busy_check_all(int gem_fd, const unsigned int num_engines,
 	unsigned int i;
 
 	i = 0;
-	for_each_engine_class_instance(gem_fd, e) {
+	__for_each_physical_engine(gem_fd, e) {
 		if (spin)
 			__submit_spin(gem_fd, spin, e, 64);
 		else
-			spin = __spin_poll(gem_fd, 0, e2ring(gem_fd, e));
+			spin = __spin_poll(gem_fd, 0, e);
 
 		val[i++] = I915_PMU_ENGINE_BUSY(e->class, e->instance);
 	}
@@ -602,7 +613,7 @@ no_sema(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
 	open_group(I915_PMU_ENGINE_WAIT(e->class, e->instance), fd);
 
 	if (flags & TEST_BUSY)
-		spin = spin_sync(gem_fd, 0, e2ring(gem_fd, e));
+		spin = spin_sync(gem_fd, 0, e);
 	else
 		spin = NULL;
 
@@ -689,7 +700,7 @@ sema_wait(int gem_fd, const struct intel_execution_engine2 *e,
 
 	eb.buffer_count = 2;
 	eb.buffers_ptr = to_user_pointer(obj);
-	eb.flags = e2ring(gem_fd, e);
+	eb.flags = e->flags;
 
 	/**
 	 * Start the semaphore wait PMU and after some known time let the above
@@ -845,7 +856,7 @@ event_wait(int gem_fd, const struct intel_execution_engine2 *e)
 
 	eb.buffer_count = 1;
 	eb.buffers_ptr = to_user_pointer(&obj);
-	eb.flags = e2ring(gem_fd, e) | I915_EXEC_SECURE;
+	eb.flags = e->flags | I915_EXEC_SECURE;
 
 	for_each_pipe_with_valid_output(&data.display, p, output) {
 		struct igt_helper_process waiter = { };
@@ -936,7 +947,7 @@ multi_client(int gem_fd, const struct intel_execution_engine2 *e)
 	 */
 	fd[1] = open_pmu(config);
 
-	spin = spin_sync(gem_fd, 0, e2ring(gem_fd, e));
+	spin = spin_sync(gem_fd, 0, e);
 
 	val[0] = val[1] = __pmu_read_single(fd[0], &ts[0]);
 	slept[1] = measured_usleep(batch_duration_ns / 1000);
@@ -1052,8 +1063,8 @@ static void cpu_hotplug(int gem_fd)
 	 * Create two spinners so test can ensure shorter gaps in engine
 	 * busyness as it is terminating one and re-starting the other.
 	 */
-	spin[0] = igt_spin_new(gem_fd, .engine = I915_EXEC_RENDER);
-	spin[1] = __igt_spin_new(gem_fd, .engine = I915_EXEC_RENDER);
+	spin[0] = igt_spin_new(gem_fd, .engine = I915_EXEC_DEFAULT);
+	spin[1] = __igt_spin_new(gem_fd, .engine = I915_EXEC_DEFAULT);
 
 	val = __pmu_read_single(fd, &ts[0]);
 
@@ -1137,7 +1148,7 @@ static void cpu_hotplug(int gem_fd)
 
 		igt_spin_free(gem_fd, spin[cur]);
 		spin[cur] = __igt_spin_new(gem_fd,
-					   .engine = I915_EXEC_RENDER);
+					   .engine = I915_EXEC_DEFAULT);
 		cur ^= 1;
 	}
 
@@ -1175,7 +1186,7 @@ test_interrupts(int gem_fd)
 	/* Queue spinning batches. */
 	for (int i = 0; i < target; i++) {
 		spin[i] = __igt_spin_new(gem_fd,
-					 .engine = I915_EXEC_RENDER,
+					 .engine = I915_EXEC_DEFAULT,
 					 .flags = IGT_SPIN_FENCE_OUT);
 		if (i == 0) {
 			fence_fd = spin[i]->out_fence;
@@ -1301,7 +1312,7 @@ test_frequency(int gem_fd)
 	igt_require(igt_sysfs_get_u32(sysfs, "gt_boost_freq_mhz") == min_freq);
 
 	gem_quiescent_gpu(gem_fd); /* Idle to be sure the change takes effect */
-	spin = spin_sync(gem_fd, 0, I915_EXEC_RENDER);
+	spin = spin_sync_flags(gem_fd, 0, I915_EXEC_DEFAULT);
 
 	slept = pmu_read_multi(fd, 2, start);
 	measured_usleep(batch_duration_ns / 1000);
@@ -1327,7 +1338,7 @@ test_frequency(int gem_fd)
 	igt_require(igt_sysfs_get_u32(sysfs, "gt_min_freq_mhz") == max_freq);
 
 	gem_quiescent_gpu(gem_fd);
-	spin = spin_sync(gem_fd, 0, I915_EXEC_RENDER);
+	spin = spin_sync_flags(gem_fd, 0, I915_EXEC_DEFAULT);
 
 	slept = pmu_read_multi(fd, 2, start);
 	measured_usleep(batch_duration_ns / 1000);
@@ -1458,14 +1469,14 @@ test_enable_race(int gem_fd, const struct intel_execution_engine2 *e)
 	int fd;
 
 	igt_require(gem_has_execlists(gem_fd));
-	igt_require(gem_has_engine(gem_fd, e->class, e->instance));
+	igt_require(gem_context_has_engine(gem_fd, 0, e->flags));
 
 	obj.handle = gem_create(gem_fd, 4096);
 	gem_write(gem_fd, obj.handle, 0, &bbend, sizeof(bbend));
 
 	eb.buffer_count = 1;
 	eb.buffers_ptr = to_user_pointer(&obj);
-	eb.flags = e2ring(gem_fd, e);
+	eb.flags = e->flags;
 
 	/*
 	 * This test is probabilistic so run in a few times to increase the
@@ -1562,7 +1573,7 @@ accuracy(int gem_fd, const struct intel_execution_engine2 *e,
 		igt_spin_t *spin;
 
 		/* Allocate our spin batch and idle it. */
-		spin = igt_spin_new(gem_fd, .engine = e2ring(gem_fd, e));
+		spin = igt_spin_new(gem_fd, .engine = e->flags);
 		igt_spin_end(spin);
 		gem_sync(gem_fd, spin->handle);
 
@@ -1666,7 +1677,7 @@ igt_main
 				I915_PMU_LAST - __I915_PMU_OTHER(0) + 1;
 	unsigned int num_engines = 0;
 	int fd = -1;
-	const struct intel_execution_engine2 *e;
+	struct intel_execution_engine2 *e;
 	unsigned int i;
 
 	igt_fixture {
@@ -1675,7 +1686,7 @@ igt_main
 		igt_require_gem(fd);
 		igt_require(i915_type_id() > 0);
 
-		for_each_engine_class_instance(fd, e)
+		__for_each_physical_engine(fd, e)
 			num_engines++;
 	}
 
@@ -1685,7 +1696,7 @@ igt_main
 	igt_subtest("invalid-init")
 		invalid_init();
 
-	__for_each_engine_class_instance(e) {
+	__for_each_physical_engine(fd, e) {
 		const unsigned int pct[] = { 2, 50, 98 };
 
 		/**
@@ -1703,7 +1714,7 @@ igt_main
 
 		igt_subtest_group {
 			igt_fixture {
-				gem_require_engine(fd, e->class, e->instance);
+				gem_context_has_engine(fd, 0, e->flags);
 			}
 
 			/**
@@ -1889,12 +1900,11 @@ igt_main
 			gem_quiescent_gpu(fd);
 		}
 
-		__for_each_engine_class_instance(e) {
+		__for_each_physical_engine(render_fd, e) {
 			igt_subtest_group {
 				igt_fixture {
-					gem_require_engine(render_fd,
-							   e->class,
-							   e->instance);
+					gem_context_has_engine(render_fd,
+							   0, e->flags);
 				}
 
 				igt_subtest_f("render-node-busy-%s", e->name)
-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 32+ messages in thread
* [CI i-g-t 07/14] test/i915: gem_busy: use the gem_engine_topology library
  2019-05-22 13:50 ` [igt-dev] " Tvrtko Ursulin
@ 2019-05-22 13:50   ` Tvrtko Ursulin
  -1 siblings, 0 replies; 32+ messages in thread
From: Tvrtko Ursulin @ 2019-05-22 13:50 UTC (permalink / raw)
  To: igt-dev; +Cc: Intel-gfx

From: Andi Shyti <andi.shyti@intel.com>

Replace the legacy for_each_engine* defines with the ones
implemented in the gem_engine_topology library.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 tests/i915/gem_busy.c | 128 ++++++++++++++++--------------------------
 1 file changed, 48 insertions(+), 80 deletions(-)

diff --git a/tests/i915/gem_busy.c b/tests/i915/gem_busy.c
index c120faf10983..2872e7b7be62 100644
--- a/tests/i915/gem_busy.c
+++ b/tests/i915/gem_busy.c
@@ -66,22 +66,9 @@ static void __gem_busy(int fd,
 	*read = busy.busy >> 16;
 }
 
-static uint32_t ring_to_class(unsigned int ring)
-{
-	uint32_t class[] = {
-		[I915_EXEC_DEFAULT] = I915_ENGINE_CLASS_RENDER,
-		[I915_EXEC_RENDER]  = I915_ENGINE_CLASS_RENDER,
-		[I915_EXEC_BLT]     = I915_ENGINE_CLASS_COPY,
-		[I915_EXEC_BSD]     = I915_ENGINE_CLASS_VIDEO,
-		[I915_EXEC_VEBOX]   = I915_ENGINE_CLASS_VIDEO_ENHANCE,
-	};
-	igt_assert(ring < ARRAY_SIZE(class));
-	return class[ring];
-}
-
 static bool exec_noop(int fd,
 		      uint32_t *handles,
-		      unsigned ring,
+		      unsigned flags,
 		      bool write)
 {
 	struct drm_i915_gem_execbuffer2 execbuf;
@@ -97,9 +84,9 @@ static bool exec_noop(int fd,
 	memset(&execbuf, 0, sizeof(execbuf));
 	execbuf.buffers_ptr = to_user_pointer(exec);
 	execbuf.buffer_count = 3;
-	execbuf.flags = ring;
-	igt_debug("Queuing handle for %s on ring %d\n",
-		  write ? "writing" : "reading", ring & 0x7);
+	execbuf.flags = flags;
+	igt_debug("Queuing handle for %s on engine %d\n",
+		  write ? "writing" : "reading", flags);
 	return __gem_execbuf(fd, &execbuf) == 0;
 }
 
@@ -110,18 +97,17 @@ static bool still_busy(int fd, uint32_t handle)
 	return write;
 }
 
-static void semaphore(int fd, unsigned ring, uint32_t flags)
+static void semaphore(int fd, const struct intel_execution_engine2 *e)
 {
+	struct intel_execution_engine2 *__e;
 	uint32_t bbe = MI_BATCH_BUFFER_END;
-	const unsigned uabi = ring_to_class(ring & 63);
+	const unsigned uabi = e->class;
 	igt_spin_t *spin;
 	uint32_t handle[3];
 	uint32_t read, write;
 	uint32_t active;
 	unsigned i;
 
-	gem_require_ring(fd, ring | flags);
-
 	handle[TEST] = gem_create(fd, 4096);
 	handle[BATCH] = gem_create(fd, 4096);
 	gem_write(fd, handle[BATCH], 0, &bbe, sizeof(bbe));
@@ -129,18 +115,18 @@ static void semaphore(int fd, unsigned ring, uint32_t flags)
 	/* Create a long running batch which we can use to hog the GPU */
 	handle[BUSY] = gem_create(fd, 4096);
 	spin = igt_spin_new(fd,
-			    .engine = ring,
+			    .engine = e->flags,
 			    .dependency = handle[BUSY]);
 
 	/* Queue a batch after the busy, it should block and remain "busy" */
-	igt_assert(exec_noop(fd, handle, ring | flags, false));
+	igt_assert(exec_noop(fd, handle, e->flags, false));
 	igt_assert(still_busy(fd, handle[BUSY]));
 	__gem_busy(fd, handle[TEST], &read, &write);
 	igt_assert_eq(read, 1 << uabi);
 	igt_assert_eq(write, 0);
 
 	/* Requeue with a write */
-	igt_assert(exec_noop(fd, handle, ring | flags, true));
+	igt_assert(exec_noop(fd, handle, e->flags, true));
 	igt_assert(still_busy(fd, handle[BUSY]));
 	__gem_busy(fd, handle[TEST], &read, &write);
 	igt_assert_eq(read, 1 << uabi);
@@ -148,9 +134,9 @@ static void semaphore(int fd, unsigned ring, uint32_t flags)
 
 	/* Now queue it for a read across all available rings */
 	active = 0;
-	for (i = I915_EXEC_RENDER; i <= I915_EXEC_VEBOX; i++) {
-		if (exec_noop(fd, handle, i | flags, false))
-			active |= 1 << ring_to_class(i);
+	__for_each_physical_engine(fd, __e) {
+		if (exec_noop(fd, handle, __e->flags, false))
+			active |= 1 << __e->class;
 	}
 	igt_assert(still_busy(fd, handle[BUSY]));
 	__gem_busy(fd, handle[TEST], &read, &write);
@@ -173,7 +159,7 @@ static void semaphore(int fd, unsigned ring, uint32_t flags)
 
 #define PARALLEL 1
 #define HANG 2
-static void one(int fd, unsigned ring, unsigned test_flags)
+static void one(int fd, const struct intel_execution_engine2 *e, unsigned test_flags)
 {
 	const int gen = intel_gen(intel_get_drm_devid(fd));
 	struct drm_i915_gem_exec_object2 obj[2];
@@ -182,7 +168,7 @@ static void one(int fd, unsigned ring, unsigned test_flags)
 	struct drm_i915_gem_relocation_entry store[1024+1];
 	struct drm_i915_gem_execbuffer2 execbuf;
 	unsigned size = ALIGN(ARRAY_SIZE(store)*16 + 4, 4096);
-	const unsigned uabi = ring_to_class(ring & 63);
+	const unsigned uabi = e->class;
 	uint32_t read[2], write[2];
 	struct timespec tv;
 	uint32_t *batch, *bbe;
@@ -191,7 +177,7 @@ static void one(int fd, unsigned ring, unsigned test_flags)
 	memset(&execbuf, 0, sizeof(execbuf));
 	execbuf.buffers_ptr = to_user_pointer(obj);
 	execbuf.buffer_count = 2;
-	execbuf.flags = ring;
+	execbuf.flags = e->flags;
 	if (gen < 6)
 		execbuf.flags |= I915_EXEC_SECURE;
 
@@ -263,17 +249,18 @@ static void one(int fd, unsigned ring, unsigned test_flags)
 	__gem_busy(fd, obj[BATCH].handle, &read[BATCH], &write[BATCH]);
 
 	if (test_flags & PARALLEL) {
-		unsigned other;
+		struct intel_execution_engine2 *e2;
 
-		for_each_physical_engine(fd, other) {
-			if (other == ring)
+		__for_each_physical_engine(fd, e2) {
+			if (e2->class == e->class &&
+			    e2->instance == e->instance)
 				continue;
 
-			if (!gem_can_store_dword(fd, other))
+			if (!gem_class_can_store_dword(fd, e->class))
 				continue;
 
-			igt_debug("Testing %s in parallel\n", e__->name);
-			one(fd, other, 0);
+			igt_debug("Testing %s in parallel\n", e2->name);
+			one(fd, e2, 0);
 		}
 	}
 
@@ -439,11 +426,11 @@ static bool has_extended_busy_ioctl(int fd)
 	return read != 0;
 }
 
-static void basic(int fd, unsigned ring, unsigned flags)
+static void basic(int fd, const struct intel_execution_engine2 *e, unsigned flags)
 {
 	igt_spin_t *spin =
 		igt_spin_new(fd,
-			     .engine = ring,
+			     .engine = e->flags,
 			     .flags = IGT_SPIN_NO_PREEMPTION);
 	struct timespec tv;
 	int timeout;
@@ -475,13 +462,14 @@ static void basic(int fd, unsigned ring, unsigned flags)
 
 igt_main
 {
-	const struct intel_execution_engine *e;
+	const struct intel_execution_engine2 *e;
 	int fd = -1;
 
 	igt_fixture {
 		fd = drm_open_driver_master(DRIVER_INTEL);
 		igt_require_gem(fd);
-		igt_require(gem_can_store_dword(fd, 0));
+		igt_require(gem_class_can_store_dword(fd,
+						     I915_ENGINE_CLASS_RENDER));
 	}
 
 	igt_subtest_group {
@@ -489,14 +477,13 @@ igt_main
 			igt_fork_hang_detector(fd);
 		}
 
-		for (e = intel_execution_engines; e->name; e++) {
+		__for_each_physical_engine(fd, e) {
 			igt_subtest_group {
 				igt_subtest_f("%sbusy-%s",
-					      e->exec_id == 0 ? "basic-" : "",
-					      e->name) {
-					igt_require(gem_has_ring(fd, e->exec_id | e->flags));
+					      e->class == I915_ENGINE_CLASS_RENDER
+					      ? "basic-" : "", e->name) {
 					gem_quiescent_gpu(fd);
-					basic(fd, e->exec_id | e->flags, 0);
+					basic(fd, e, false);
 				}
 			}
 		}
@@ -507,31 +494,22 @@ igt_main
 				gem_require_mmap_wc(fd);
 			}
 
-			for (e = intel_execution_engines; e->name; e++) {
-				/* default exec-id is purely symbolic */
-				if (e->exec_id == 0)
-					continue;
-
+			__for_each_physical_engine(fd, e) {
 				igt_subtest_f("extended-%s", e->name) {
-					igt_require(gem_ring_has_physical_engine(fd, e->exec_id | e->flags));
-					igt_require(gem_can_store_dword(fd, e->exec_id | e->flags));
+					igt_require(gem_class_can_store_dword(fd,
+						     e->class));
 					gem_quiescent_gpu(fd);
-					one(fd, e->exec_id | e->flags, 0);
+					one(fd, e, 0);
 					gem_quiescent_gpu(fd);
 				}
 			}
 
-			for (e = intel_execution_engines; e->name; e++) {
-				/* default exec-id is purely symbolic */
-				if (e->exec_id == 0)
-					continue;
-
+			__for_each_physical_engine(fd, e) {
 				igt_subtest_f("extended-parallel-%s", e->name) {
-					igt_require(gem_ring_has_physical_engine(fd, e->exec_id | e->flags));
-					igt_require(gem_can_store_dword(fd, e->exec_id | e->flags));
+					igt_require(gem_class_can_store_dword(fd, e->class));
 
 					gem_quiescent_gpu(fd);
-					one(fd, e->exec_id | e->flags, PARALLEL);
+					one(fd, e, PARALLEL);
 					gem_quiescent_gpu(fd);
 				}
 			}
@@ -543,13 +521,9 @@ igt_main
 				igt_require(has_semaphores(fd));
 			}
 
-			for (e = intel_execution_engines; e->name; e++) {
-				/* default exec-id is purely symbolic */
-				if (e->exec_id == 0)
-					continue;
-
+			__for_each_physical_engine(fd, e) {
 				igt_subtest_f("extended-semaphore-%s", e->name)
-					semaphore(fd, e->exec_id, e->flags);
+					semaphore(fd, e);
 			}
 		}
 
@@ -568,14 +542,13 @@ igt_main
 			hang = igt_allow_hang(fd, 0, 0);
 		}
 
-		for (e = intel_execution_engines; e->name; e++) {
+		__for_each_physical_engine(fd, e) {
 			igt_subtest_f("%shang-%s",
-				      e->exec_id == 0 ? "basic-" : "",
-				      e->name) {
+				      e->class == I915_ENGINE_CLASS_RENDER
+				      ? "basic-" : "", e->name) {
 				igt_skip_on_simulation();
-				igt_require(gem_has_ring(fd, e->exec_id | e->flags));
 				gem_quiescent_gpu(fd);
-				basic(fd, e->exec_id | e->flags, HANG);
+				basic(fd, e, true);
 			}
 		}
 
@@ -585,18 +558,13 @@ igt_main
 				gem_require_mmap_wc(fd);
 			}
 
-			for (e = intel_execution_engines; e->name; e++) {
-				/* default exec-id is purely symbolic */
-				if (e->exec_id == 0)
-					continue;
-
+			__for_each_physical_engine(fd, e) {
 				igt_subtest_f("extended-hang-%s", e->name) {
 					igt_skip_on_simulation();
-					igt_require(gem_ring_has_physical_engine(fd, e->exec_id | e->flags));
-					igt_require(gem_can_store_dword(fd, e->exec_id | e->flags));
+					igt_require(gem_class_can_store_dword(fd, e->class));
 
 					gem_quiescent_gpu(fd);
-					one(fd, e->exec_id | e->flags, HANG);
+					one(fd, e, HANG);
 					gem_quiescent_gpu(fd);
 				}
 			}
-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 32+ messages in thread
* [igt-dev] [CI i-g-t 07/14] test/i915: gem_busy: use the gem_engine_topology library
@ 2019-05-22 13:50   ` Tvrtko Ursulin
  0 siblings, 0 replies; 32+ messages in thread
From: Tvrtko Ursulin @ 2019-05-22 13:50 UTC (permalink / raw)
  To: igt-dev; +Cc: Intel-gfx

From: Andi Shyti <andi.shyti@intel.com>

Replace the legacy for_each_engine* defines with the ones
implemented in the gem_engine_topology library.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 tests/i915/gem_busy.c | 128 ++++++++++++++++--------------------------
 1 file changed, 48 insertions(+), 80 deletions(-)

diff --git a/tests/i915/gem_busy.c b/tests/i915/gem_busy.c
index c120faf10983..2872e7b7be62 100644
--- a/tests/i915/gem_busy.c
+++ b/tests/i915/gem_busy.c
@@ -66,22 +66,9 @@ static void __gem_busy(int fd,
 	*read = busy.busy >> 16;
 }
 
-static uint32_t ring_to_class(unsigned int ring)
-{
-	uint32_t class[] = {
-		[I915_EXEC_DEFAULT] = I915_ENGINE_CLASS_RENDER,
-		[I915_EXEC_RENDER]  = I915_ENGINE_CLASS_RENDER,
-		[I915_EXEC_BLT]     = I915_ENGINE_CLASS_COPY,
-		[I915_EXEC_BSD]     = I915_ENGINE_CLASS_VIDEO,
-		[I915_EXEC_VEBOX]   = I915_ENGINE_CLASS_VIDEO_ENHANCE,
-	};
-	igt_assert(ring < ARRAY_SIZE(class));
-	return class[ring];
-}
-
 static bool exec_noop(int fd,
 		      uint32_t *handles,
-		      unsigned ring,
+		      unsigned flags,
 		      bool write)
 {
 	struct drm_i915_gem_execbuffer2 execbuf;
@@ -97,9 +84,9 @@ static bool exec_noop(int fd,
 	memset(&execbuf, 0, sizeof(execbuf));
 	execbuf.buffers_ptr = to_user_pointer(exec);
 	execbuf.buffer_count = 3;
-	execbuf.flags = ring;
-	igt_debug("Queuing handle for %s on ring %d\n",
-		  write ? "writing" : "reading", ring & 0x7);
+	execbuf.flags = flags;
+	igt_debug("Queuing handle for %s on engine %d\n",
+		  write ? "writing" : "reading", flags);
 	return __gem_execbuf(fd, &execbuf) == 0;
 }
 
@@ -110,18 +97,17 @@ static bool still_busy(int fd, uint32_t handle)
 	return write;
 }
 
-static void semaphore(int fd, unsigned ring, uint32_t flags)
+static void semaphore(int fd, const struct intel_execution_engine2 *e)
 {
+	struct intel_execution_engine2 *__e;
 	uint32_t bbe = MI_BATCH_BUFFER_END;
-	const unsigned uabi = ring_to_class(ring & 63);
+	const unsigned uabi = e->class;
 	igt_spin_t *spin;
 	uint32_t handle[3];
 	uint32_t read, write;
 	uint32_t active;
 	unsigned i;
 
-	gem_require_ring(fd, ring | flags);
-
 	handle[TEST] = gem_create(fd, 4096);
 	handle[BATCH] = gem_create(fd, 4096);
 	gem_write(fd, handle[BATCH], 0, &bbe, sizeof(bbe));
@@ -129,18 +115,18 @@ static void semaphore(int fd, unsigned ring, uint32_t flags)
 	/* Create a long running batch which we can use to hog the GPU */
 	handle[BUSY] = gem_create(fd, 4096);
 	spin = igt_spin_new(fd,
-			    .engine = ring,
+			    .engine = e->flags,
 			    .dependency = handle[BUSY]);
 
 	/* Queue a batch after the busy, it should block and remain "busy" */
-	igt_assert(exec_noop(fd, handle, ring | flags, false));
+	igt_assert(exec_noop(fd, handle, e->flags, false));
 	igt_assert(still_busy(fd, handle[BUSY]));
 	__gem_busy(fd, handle[TEST], &read, &write);
 	igt_assert_eq(read, 1 << uabi);
 	igt_assert_eq(write, 0);
 
 	/* Requeue with a write */
-	igt_assert(exec_noop(fd, handle, ring | flags, true));
+	igt_assert(exec_noop(fd, handle, e->flags, true));
 	igt_assert(still_busy(fd, handle[BUSY]));
 	__gem_busy(fd, handle[TEST], &read, &write);
 	igt_assert_eq(read, 1 << uabi);
@@ -148,9 +134,9 @@ static void semaphore(int fd, unsigned ring, uint32_t flags)
 
 	/* Now queue it for a read across all available rings */
 	active = 0;
-	for (i = I915_EXEC_RENDER; i <= I915_EXEC_VEBOX; i++) {
-		if (exec_noop(fd, handle, i | flags, false))
-			active |= 1 << ring_to_class(i);
+	__for_each_physical_engine(fd, __e) {
+		if (exec_noop(fd, handle, __e->flags, false))
+			active |= 1 << __e->class;
 	}
 	igt_assert(still_busy(fd, handle[BUSY]));
 	__gem_busy(fd, handle[TEST], &read, &write);
@@ -173,7 +159,7 @@ static void semaphore(int fd, unsigned ring, uint32_t flags)
 
 #define PARALLEL 1
 #define HANG 2
-static void one(int fd, unsigned ring, unsigned test_flags)
+static void one(int fd, const struct intel_execution_engine2 *e, unsigned test_flags)
 {
 	const int gen = intel_gen(intel_get_drm_devid(fd));
 	struct drm_i915_gem_exec_object2 obj[2];
@@ -182,7 +168,7 @@ static void one(int fd, unsigned ring, unsigned test_flags)
 	struct drm_i915_gem_relocation_entry store[1024+1];
 	struct drm_i915_gem_execbuffer2 execbuf;
 	unsigned size = ALIGN(ARRAY_SIZE(store)*16 + 4, 4096);
-	const unsigned uabi = ring_to_class(ring & 63);
+	const unsigned uabi = e->class;
 	uint32_t read[2], write[2];
 	struct timespec tv;
 	uint32_t *batch, *bbe;
@@ -191,7 +177,7 @@ static void one(int fd, unsigned ring, unsigned test_flags)
 	memset(&execbuf, 0, sizeof(execbuf));
 	execbuf.buffers_ptr = to_user_pointer(obj);
 	execbuf.buffer_count = 2;
-	execbuf.flags = ring;
+	execbuf.flags = e->flags;
 	if (gen < 6)
 		execbuf.flags |= I915_EXEC_SECURE;
 
@@ -263,17 +249,18 @@ static void one(int fd, unsigned ring, unsigned test_flags)
 	__gem_busy(fd, obj[BATCH].handle, &read[BATCH], &write[BATCH]);
 
 	if (test_flags & PARALLEL) {
-		unsigned other;
+		struct intel_execution_engine2 *e2;
 
-		for_each_physical_engine(fd, other) {
-			if (other == ring)
+		__for_each_physical_engine(fd, e2) {
+			if (e2->class == e->class &&
+			    e2->instance == e->instance)
 				continue;
 
-			if (!gem_can_store_dword(fd, other))
+			if (!gem_class_can_store_dword(fd, e->class))
 				continue;
 
-			igt_debug("Testing %s in parallel\n", e__->name);
-			one(fd, other, 0);
+			igt_debug("Testing %s in parallel\n", e2->name);
+			one(fd, e2, 0);
 		}
 	}
 
@@ -439,11 +426,11 @@ static bool has_extended_busy_ioctl(int fd)
 	return read != 0;
 }
 
-static void basic(int fd, unsigned ring, unsigned flags)
+static void basic(int fd, const struct intel_execution_engine2 *e, unsigned flags)
 {
 	igt_spin_t *spin =
 		igt_spin_new(fd,
-			     .engine = ring,
+			     .engine = e->flags,
 			     .flags = IGT_SPIN_NO_PREEMPTION);
 	struct timespec tv;
 	int timeout;
@@ -475,13 +462,14 @@ static void basic(int fd, unsigned ring, unsigned flags)
 
 igt_main
 {
-	const struct intel_execution_engine *e;
+	const struct intel_execution_engine2 *e;
 	int fd = -1;
 
 	igt_fixture {
 		fd = drm_open_driver_master(DRIVER_INTEL);
 		igt_require_gem(fd);
-		igt_require(gem_can_store_dword(fd, 0));
+		igt_require(gem_class_can_store_dword(fd,
+						     I915_ENGINE_CLASS_RENDER));
 	}
 
 	igt_subtest_group {
@@ -489,14 +477,13 @@ igt_main
 			igt_fork_hang_detector(fd);
 		}
 
-		for (e = intel_execution_engines; e->name; e++) {
+		__for_each_physical_engine(fd, e) {
 			igt_subtest_group {
 				igt_subtest_f("%sbusy-%s",
-					      e->exec_id == 0 ? "basic-" : "",
-					      e->name) {
-					igt_require(gem_has_ring(fd, e->exec_id | e->flags));
+					      e->class == I915_ENGINE_CLASS_RENDER
+					      ? "basic-" : "", e->name) {
 					gem_quiescent_gpu(fd);
-					basic(fd, e->exec_id | e->flags, 0);
+					basic(fd, e, false);
 				}
 			}
 		}
@@ -507,31 +494,22 @@ igt_main
 				gem_require_mmap_wc(fd);
 			}
 
-			for (e = intel_execution_engines; e->name; e++) {
-				/* default exec-id is purely symbolic */
-				if (e->exec_id == 0)
-					continue;
-
+			__for_each_physical_engine(fd, e) {
 				igt_subtest_f("extended-%s", e->name) {
-					igt_require(gem_ring_has_physical_engine(fd, e->exec_id | e->flags));
-					igt_require(gem_can_store_dword(fd, e->exec_id | e->flags));
+					igt_require(gem_class_can_store_dword(fd,
+						     e->class));
 					gem_quiescent_gpu(fd);
-					one(fd, e->exec_id | e->flags, 0);
+					one(fd, e, 0);
 					gem_quiescent_gpu(fd);
 				}
 			}
 
-			for (e = intel_execution_engines; e->name; e++) {
-				/* default exec-id is purely symbolic */
-				if (e->exec_id == 0)
-					continue;
-
+			__for_each_physical_engine(fd, e) {
 				igt_subtest_f("extended-parallel-%s", e->name) {
-					igt_require(gem_ring_has_physical_engine(fd, e->exec_id | e->flags));
-					igt_require(gem_can_store_dword(fd, e->exec_id | e->flags));
+					igt_require(gem_class_can_store_dword(fd, e->class));
 
 					gem_quiescent_gpu(fd);
-					one(fd, e->exec_id | e->flags, PARALLEL);
+					one(fd, e, PARALLEL);
 					gem_quiescent_gpu(fd);
 				}
 			}
@@ -543,13 +521,9 @@ igt_main
 				igt_require(has_semaphores(fd));
 			}
 
-			for (e = intel_execution_engines; e->name; e++) {
-				/* default exec-id is purely symbolic */
-				if (e->exec_id == 0)
-					continue;
-
+			__for_each_physical_engine(fd, e) {
 				igt_subtest_f("extended-semaphore-%s", e->name)
-					semaphore(fd, e->exec_id, e->flags);
+					semaphore(fd, e);
 			}
 		}
 
@@ -568,14 +542,13 @@ igt_main
 			hang = igt_allow_hang(fd, 0, 0);
 		}
 
-		for (e = intel_execution_engines; e->name; e++) {
+		__for_each_physical_engine(fd, e) {
 			igt_subtest_f("%shang-%s",
-				      e->exec_id == 0 ? "basic-" : "",
-				      e->name) {
+				      e->class == I915_ENGINE_CLASS_RENDER
+				      ? "basic-" : "", e->name) {
 				igt_skip_on_simulation();
-				igt_require(gem_has_ring(fd, e->exec_id | e->flags));
 				gem_quiescent_gpu(fd);
-				basic(fd, e->exec_id | e->flags, HANG);
+				basic(fd, e, true);
 			}
 		}
 
@@ -585,18 +558,13 @@ igt_main
 				gem_require_mmap_wc(fd);
 			}
 
-			for (e = intel_execution_engines; e->name; e++) {
-				/* default exec-id is purely symbolic */
-				if (e->exec_id == 0)
-					continue;
-
+			__for_each_physical_engine(fd, e) {
 				igt_subtest_f("extended-hang-%s", e->name) {
 					igt_skip_on_simulation();
-					igt_require(gem_ring_has_physical_engine(fd, e->exec_id | e->flags));
-					igt_require(gem_can_store_dword(fd, e->exec_id | e->flags));
+					igt_require(gem_class_can_store_dword(fd, e->class));
 
 					gem_quiescent_gpu(fd);
-					one(fd, e->exec_id | e->flags, HANG);
+					one(fd, e, HANG);
 					gem_quiescent_gpu(fd);
 				}
 			}
-- 
2.20.1

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply related	[flat|nested] 32+ messages in thread
* [CI i-g-t 08/14] test/i915: gem_cs_tlb: use the gem_engine_topology library
  2019-05-22 13:50 ` [igt-dev] " Tvrtko Ursulin
@ 2019-05-22 13:50   ` Tvrtko Ursulin
  -1 siblings, 0 replies; 32+ messages in thread
From: Tvrtko Ursulin @ 2019-05-22 13:50 UTC (permalink / raw)
  To: igt-dev; +Cc: Intel-gfx

From: Andi Shyti <andi.shyti@intel.com>

Replace the legacy for_each_engine* defines with the ones
implemented in the gem_engine_topology library.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 tests/i915/gem_cs_tlb.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/tests/i915/gem_cs_tlb.c b/tests/i915/gem_cs_tlb.c
index 51e1c4e19930..13de5499f1c7 100644
--- a/tests/i915/gem_cs_tlb.c
+++ b/tests/i915/gem_cs_tlb.c
@@ -140,7 +140,7 @@ static void run_on_ring(int fd, unsigned ring_id, const char *ring_name)
 
 igt_main
 {
-	const struct intel_execution_engine *e;
+	const struct intel_execution_engine2 *e;
 	int fd = -1;
 
 	igt_skip_on_simulation();
@@ -150,9 +150,9 @@ igt_main
 		igt_require_gem(fd);
 	}
 
-	for (e = intel_execution_engines; e->name; e++)
-		igt_subtest_f("%s%s", e->exec_id ? "" : "basic-", e->name)
-			run_on_ring(fd, e->exec_id | e->flags, e->name);
+	__for_each_physical_engine(fd, e)
+		igt_subtest_f("%s", e->name)
+			run_on_ring(fd, e->flags, e->name);
 
 	igt_fixture
 		close(fd);
-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 32+ messages in thread
* [Intel-gfx] [CI i-g-t 08/14] test/i915: gem_cs_tlb: use the gem_engine_topology library
@ 2019-05-22 13:50   ` Tvrtko Ursulin
  0 siblings, 0 replies; 32+ messages in thread
From: Tvrtko Ursulin @ 2019-05-22 13:50 UTC (permalink / raw)
  To: igt-dev; +Cc: Intel-gfx

From: Andi Shyti <andi.shyti@intel.com>

Replace the legacy for_each_engine* defines with the ones
implemented in the gem_engine_topology library.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 tests/i915/gem_cs_tlb.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/tests/i915/gem_cs_tlb.c b/tests/i915/gem_cs_tlb.c
index 51e1c4e19930..13de5499f1c7 100644
--- a/tests/i915/gem_cs_tlb.c
+++ b/tests/i915/gem_cs_tlb.c
@@ -140,7 +140,7 @@ static void run_on_ring(int fd, unsigned ring_id, const char *ring_name)
 
 igt_main
 {
-	const struct intel_execution_engine *e;
+	const struct intel_execution_engine2 *e;
 	int fd = -1;
 
 	igt_skip_on_simulation();
@@ -150,9 +150,9 @@ igt_main
 		igt_require_gem(fd);
 	}
 
-	for (e = intel_execution_engines; e->name; e++)
-		igt_subtest_f("%s%s", e->exec_id ? "" : "basic-", e->name)
-			run_on_ring(fd, e->exec_id | e->flags, e->name);
+	__for_each_physical_engine(fd, e)
+		igt_subtest_f("%s", e->name)
+			run_on_ring(fd, e->flags, e->name);
 
 	igt_fixture
 		close(fd);
-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 32+ messages in thread
* [CI i-g-t 09/14] test/i915: gem_ctx_exec: use the gem_engine_topology library
  2019-05-22 13:50 ` [igt-dev] " Tvrtko Ursulin
@ 2019-05-22 13:50   ` Tvrtko Ursulin
  -1 siblings, 0 replies; 32+ messages in thread
From: Tvrtko Ursulin @ 2019-05-22 13:50 UTC (permalink / raw)
  To: igt-dev; +Cc: Intel-gfx

From: Andi Shyti <andi.shyti@intel.com>

Replace the legacy for_each_engine* defines with the ones
implemented in the gem_engine_topology library.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 tests/i915/gem_ctx_exec.c | 16 +++++++---------
 1 file changed, 7 insertions(+), 9 deletions(-)

diff --git a/tests/i915/gem_ctx_exec.c b/tests/i915/gem_ctx_exec.c
index b8e0e0743892..614a9f401931 100644
--- a/tests/i915/gem_ctx_exec.c
+++ b/tests/i915/gem_ctx_exec.c
@@ -111,7 +111,8 @@ static void big_exec(int fd, uint32_t handle, int ring)
 	gem_sync(fd, handle);
 }
 
-static void invalid_context(int fd, unsigned ring, uint32_t handle)
+static void invalid_context(int fd, const struct intel_execution_engine2 *e,
+			    uint32_t handle)
 {
 	struct drm_i915_gem_exec_object2 obj = {
 		.handle = handle,
@@ -119,7 +120,7 @@ static void invalid_context(int fd, unsigned ring, uint32_t handle)
 	struct drm_i915_gem_execbuffer2 execbuf = {
 		.buffers_ptr = to_user_pointer(&obj),
 		.buffer_count = 1,
-		.flags = ring,
+		.flags = e->flags,
 	};
 	unsigned int i;
 	uint32_t ctx;
@@ -198,7 +199,7 @@ static void norecovery(int i915)
 igt_main
 {
 	const uint32_t batch[2] = { 0, MI_BATCH_BUFFER_END };
-	const struct intel_execution_engine *e;
+	const struct intel_execution_engine2 *e;
 	uint32_t handle;
 	uint32_t ctx_id;
 	int fd;
@@ -228,12 +229,9 @@ igt_main
 		gem_sync(fd, handle);
 	}
 
-	for (e = intel_execution_engines; e->name; e++) {
-		igt_subtest_f("basic-invalid-context-%s", e->name) {
-			gem_require_ring(fd, e->exec_id | e->flags);
-			invalid_context(fd, e->exec_id | e->flags, handle);
-		}
-	}
+	__for_each_physical_engine(fd, e)
+		igt_subtest_f("basic-invalid-context-%s", e->name)
+			invalid_context(fd, e, handle);
 
 	igt_subtest("eviction")
 		big_exec(fd, handle, 0);
-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 32+ messages in thread
* [igt-dev] [CI i-g-t 09/14] test/i915: gem_ctx_exec: use the gem_engine_topology library
@ 2019-05-22 13:50   ` Tvrtko Ursulin
  0 siblings, 0 replies; 32+ messages in thread
From: Tvrtko Ursulin @ 2019-05-22 13:50 UTC (permalink / raw)
  To: igt-dev; +Cc: Intel-gfx

From: Andi Shyti <andi.shyti@intel.com>

Replace the legacy for_each_engine* defines with the ones
implemented in the gem_engine_topology library.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 tests/i915/gem_ctx_exec.c | 16 +++++++---------
 1 file changed, 7 insertions(+), 9 deletions(-)

diff --git a/tests/i915/gem_ctx_exec.c b/tests/i915/gem_ctx_exec.c
index b8e0e0743892..614a9f401931 100644
--- a/tests/i915/gem_ctx_exec.c
+++ b/tests/i915/gem_ctx_exec.c
@@ -111,7 +111,8 @@ static void big_exec(int fd, uint32_t handle, int ring)
 	gem_sync(fd, handle);
 }
 
-static void invalid_context(int fd, unsigned ring, uint32_t handle)
+static void invalid_context(int fd, const struct intel_execution_engine2 *e,
+			    uint32_t handle)
 {
 	struct drm_i915_gem_exec_object2 obj = {
 		.handle = handle,
@@ -119,7 +120,7 @@ static void invalid_context(int fd, unsigned ring, uint32_t handle)
 	struct drm_i915_gem_execbuffer2 execbuf = {
 		.buffers_ptr = to_user_pointer(&obj),
 		.buffer_count = 1,
-		.flags = ring,
+		.flags = e->flags,
 	};
 	unsigned int i;
 	uint32_t ctx;
@@ -198,7 +199,7 @@ static void norecovery(int i915)
 igt_main
 {
 	const uint32_t batch[2] = { 0, MI_BATCH_BUFFER_END };
-	const struct intel_execution_engine *e;
+	const struct intel_execution_engine2 *e;
 	uint32_t handle;
 	uint32_t ctx_id;
 	int fd;
@@ -228,12 +229,9 @@ igt_main
 		gem_sync(fd, handle);
 	}
 
-	for (e = intel_execution_engines; e->name; e++) {
-		igt_subtest_f("basic-invalid-context-%s", e->name) {
-			gem_require_ring(fd, e->exec_id | e->flags);
-			invalid_context(fd, e->exec_id | e->flags, handle);
-		}
-	}
+	__for_each_physical_engine(fd, e)
+		igt_subtest_f("basic-invalid-context-%s", e->name)
+			invalid_context(fd, e, handle);
 
 	igt_subtest("eviction")
 		big_exec(fd, handle, 0);
-- 
2.20.1

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply related	[flat|nested] 32+ messages in thread
* [CI i-g-t 10/14] test/i915: gem_exec_basic: use the gem_engine_topology library
  2019-05-22 13:50 ` [igt-dev] " Tvrtko Ursulin
@ 2019-05-22 13:51   ` Tvrtko Ursulin
  -1 siblings, 0 replies; 32+ messages in thread
From: Tvrtko Ursulin @ 2019-05-22 13:51 UTC (permalink / raw)
  To: igt-dev; +Cc: Intel-gfx

From: Andi Shyti <andi.shyti@intel.com>

Replace the legacy for_each_engine* defines with the ones
implemented in the gem_engine_topology library.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 tests/i915/gem_exec_basic.c | 28 ++++++++++++++--------------
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/tests/i915/gem_exec_basic.c b/tests/i915/gem_exec_basic.c
index dcb83864b1c1..140cbdbc66a5 100644
--- a/tests/i915/gem_exec_basic.c
+++ b/tests/i915/gem_exec_basic.c
@@ -42,12 +42,12 @@ static void batch_fini(int fd, uint32_t handle)
 	gem_close(fd, handle);
 }
 
-static void noop(int fd, unsigned ring)
+static void noop(int fd, uint64_t flags)
 {
 	struct drm_i915_gem_execbuffer2 execbuf;
 	struct drm_i915_gem_exec_object2 exec;
 
-	gem_require_ring(fd, ring);
+	gem_require_ring(fd, flags);
 
 	memset(&exec, 0, sizeof(exec));
 
@@ -56,18 +56,18 @@ static void noop(int fd, unsigned ring)
 	memset(&execbuf, 0, sizeof(execbuf));
 	execbuf.buffers_ptr = to_user_pointer(&exec);
 	execbuf.buffer_count = 1;
-	execbuf.flags = ring;
+	execbuf.flags = flags;
 	gem_execbuf(fd, &execbuf);
 
 	batch_fini(fd, exec.handle);
 }
 
-static void readonly(int fd, unsigned ring)
+static void readonly(int fd, uint64_t flags)
 {
 	struct drm_i915_gem_execbuffer2 *execbuf;
 	struct drm_i915_gem_exec_object2 exec;
 
-	gem_require_ring(fd, ring);
+	gem_require_ring(fd, flags);
 
 	memset(&exec, 0, sizeof(exec));
 	exec.handle = batch_create(fd);
@@ -77,7 +77,7 @@ static void readonly(int fd, unsigned ring)
 
 	execbuf->buffers_ptr = to_user_pointer(&exec);
 	execbuf->buffer_count = 1;
-	execbuf->flags = ring;
+	execbuf->flags = flags;
 	igt_assert(mprotect(execbuf, 4096, PROT_READ) == 0);
 
 	gem_execbuf(fd, execbuf);
@@ -87,13 +87,13 @@ static void readonly(int fd, unsigned ring)
 	batch_fini(fd, exec.handle);
 }
 
-static void gtt(int fd, unsigned ring)
+static void gtt(int fd, uint64_t flags)
 {
 	struct drm_i915_gem_execbuffer2 *execbuf;
 	struct drm_i915_gem_exec_object2 *exec;
 	uint32_t handle;
 
-	gem_require_ring(fd, ring);
+	gem_require_ring(fd, flags);
 
 	handle = gem_create(fd, 4096);
 
@@ -106,7 +106,7 @@ static void gtt(int fd, unsigned ring)
 
 	execbuf->buffers_ptr = to_user_pointer(exec);
 	execbuf->buffer_count = 1;
-	execbuf->flags = ring;
+	execbuf->flags = flags;
 
 	gem_execbuf(fd, execbuf);
 
@@ -116,7 +116,7 @@ static void gtt(int fd, unsigned ring)
 
 igt_main
 {
-	const struct intel_execution_engine *e;
+	const struct intel_execution_engine2 *e;
 	int fd = -1;
 
 	igt_fixture {
@@ -126,13 +126,13 @@ igt_main
 		igt_fork_hang_detector(fd);
 	}
 
-	for (e = intel_execution_engines; e->name; e++) {
+	__for_each_physical_engine(fd, e) {
 		igt_subtest_f("basic-%s", e->name)
-			noop(fd, e->exec_id | e->flags);
+			noop(fd, e->flags);
 		igt_subtest_f("readonly-%s", e->name)
-			readonly(fd, e->exec_id | e->flags);
+			readonly(fd, e->flags);
 		igt_subtest_f("gtt-%s", e->name)
-			gtt(fd, e->exec_id | e->flags);
+			gtt(fd, e->flags);
 	}
 
 	igt_fixture {
-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 32+ messages in thread
* [igt-dev] [CI i-g-t 10/14] test/i915: gem_exec_basic: use the gem_engine_topology library
@ 2019-05-22 13:51   ` Tvrtko Ursulin
  0 siblings, 0 replies; 32+ messages in thread
From: Tvrtko Ursulin @ 2019-05-22 13:51 UTC (permalink / raw)
  To: igt-dev; +Cc: Intel-gfx

From: Andi Shyti <andi.shyti@intel.com>

Replace the legacy for_each_engine* defines with the ones
implemented in the gem_engine_topology library.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 tests/i915/gem_exec_basic.c | 28 ++++++++++++++--------------
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/tests/i915/gem_exec_basic.c b/tests/i915/gem_exec_basic.c
index dcb83864b1c1..140cbdbc66a5 100644
--- a/tests/i915/gem_exec_basic.c
+++ b/tests/i915/gem_exec_basic.c
@@ -42,12 +42,12 @@ static void batch_fini(int fd, uint32_t handle)
 	gem_close(fd, handle);
 }
 
-static void noop(int fd, unsigned ring)
+static void noop(int fd, uint64_t flags)
 {
 	struct drm_i915_gem_execbuffer2 execbuf;
 	struct drm_i915_gem_exec_object2 exec;
 
-	gem_require_ring(fd, ring);
+	gem_require_ring(fd, flags);
 
 	memset(&exec, 0, sizeof(exec));
 
@@ -56,18 +56,18 @@ static void noop(int fd, unsigned ring)
 	memset(&execbuf, 0, sizeof(execbuf));
 	execbuf.buffers_ptr = to_user_pointer(&exec);
 	execbuf.buffer_count = 1;
-	execbuf.flags = ring;
+	execbuf.flags = flags;
 	gem_execbuf(fd, &execbuf);
 
 	batch_fini(fd, exec.handle);
 }
 
-static void readonly(int fd, unsigned ring)
+static void readonly(int fd, uint64_t flags)
 {
 	struct drm_i915_gem_execbuffer2 *execbuf;
 	struct drm_i915_gem_exec_object2 exec;
 
-	gem_require_ring(fd, ring);
+	gem_require_ring(fd, flags);
 
 	memset(&exec, 0, sizeof(exec));
 	exec.handle = batch_create(fd);
@@ -77,7 +77,7 @@ static void readonly(int fd, unsigned ring)
 
 	execbuf->buffers_ptr = to_user_pointer(&exec);
 	execbuf->buffer_count = 1;
-	execbuf->flags = ring;
+	execbuf->flags = flags;
 	igt_assert(mprotect(execbuf, 4096, PROT_READ) == 0);
 
 	gem_execbuf(fd, execbuf);
@@ -87,13 +87,13 @@ static void readonly(int fd, unsigned ring)
 	batch_fini(fd, exec.handle);
 }
 
-static void gtt(int fd, unsigned ring)
+static void gtt(int fd, uint64_t flags)
 {
 	struct drm_i915_gem_execbuffer2 *execbuf;
 	struct drm_i915_gem_exec_object2 *exec;
 	uint32_t handle;
 
-	gem_require_ring(fd, ring);
+	gem_require_ring(fd, flags);
 
 	handle = gem_create(fd, 4096);
 
@@ -106,7 +106,7 @@ static void gtt(int fd, unsigned ring)
 
 	execbuf->buffers_ptr = to_user_pointer(exec);
 	execbuf->buffer_count = 1;
-	execbuf->flags = ring;
+	execbuf->flags = flags;
 
 	gem_execbuf(fd, execbuf);
 
@@ -116,7 +116,7 @@ static void gtt(int fd, unsigned ring)
 
 igt_main
 {
-	const struct intel_execution_engine *e;
+	const struct intel_execution_engine2 *e;
 	int fd = -1;
 
 	igt_fixture {
@@ -126,13 +126,13 @@ igt_main
 		igt_fork_hang_detector(fd);
 	}
 
-	for (e = intel_execution_engines; e->name; e++) {
+	__for_each_physical_engine(fd, e) {
 		igt_subtest_f("basic-%s", e->name)
-			noop(fd, e->exec_id | e->flags);
+			noop(fd, e->flags);
 		igt_subtest_f("readonly-%s", e->name)
-			readonly(fd, e->exec_id | e->flags);
+			readonly(fd, e->flags);
 		igt_subtest_f("gtt-%s", e->name)
-			gtt(fd, e->exec_id | e->flags);
+			gtt(fd, e->flags);
 	}
 
 	igt_fixture {
-- 
2.20.1

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply related	[flat|nested] 32+ messages in thread
* [CI i-g-t 11/14] test/i915: gem_exec_parallel: use the gem_engine_topology library
  2019-05-22 13:50 ` [igt-dev] " Tvrtko Ursulin
@ 2019-05-22 13:51   ` Tvrtko Ursulin
  -1 siblings, 0 replies; 32+ messages in thread
From: Tvrtko Ursulin @ 2019-05-22 13:51 UTC (permalink / raw)
  To: igt-dev; +Cc: Intel-gfx

From: Andi Shyti <andi.shyti@intel.com>

Replace the legacy for_each_engine* defines with the ones
implemented in the gem_engine_topology library.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/i915/gem_exec_parallel.c | 26 ++++++++++++++------------
 1 file changed, 14 insertions(+), 12 deletions(-)

diff --git a/tests/i915/gem_exec_parallel.c b/tests/i915/gem_exec_parallel.c
index 7597befb0b39..8a4482e52a6e 100644
--- a/tests/i915/gem_exec_parallel.c
+++ b/tests/i915/gem_exec_parallel.c
@@ -149,7 +149,7 @@ static void *thread(void *data)
 	return NULL;
 }
 
-static void all(int fd, unsigned engine, unsigned flags)
+static void all(int fd, struct intel_execution_engine2 *engine, unsigned flags)
 {
 	const int gen = intel_gen(intel_get_drm_devid(fd));
 	pthread_mutex_t mutex;
@@ -170,15 +170,15 @@ static void all(int fd, unsigned engine, unsigned flags)
 	}
 
 	nengine = 0;
-	if (engine == ALL_ENGINES) {
-		for_each_physical_engine(fd, engine) {
-			if (gem_can_store_dword(fd, engine))
-				engines[nengine++] = engine;
+	if (!engine) {
+		struct intel_execution_engine2 *e;
+		__for_each_physical_engine(fd, e) {
+			if (gem_class_can_store_dword(fd, e->class))
+				engines[nengine++] = e->flags;
 		}
 	} else {
-		igt_require(gem_has_ring(fd, engine));
-		igt_require(gem_can_store_dword(fd, engine));
-		engines[nengine++] = engine;
+		igt_require(gem_class_can_store_dword(fd, engine->class));
+		engines[nengine++] = engine->flags;
 	}
 	igt_require(nengine);
 
@@ -229,6 +229,8 @@ static void all(int fd, unsigned engine, unsigned flags)
 
 igt_main
 {
+	struct intel_execution_engine2 *e;
+
 	const struct mode {
 		const char *name;
 		unsigned flags;
@@ -249,16 +251,16 @@ igt_main
 
 	for (const struct mode *m = modes; m->name; m++)
 		igt_subtest_f("%s", *m->name ? m->name : "basic")
-			all(fd, ALL_ENGINES, m->flags);
+			/* NULL value means all engines */
+			all(fd, NULL, m->flags);
 
-	for (const struct intel_execution_engine *e = intel_execution_engines;
-	     e->name; e++) {
+	__for_each_physical_engine(fd, e) {
 		for (const struct mode *m = modes; m->name; m++)
 			igt_subtest_f("%s%s%s",
 				      e->name,
 				      *m->name ? "-" : "",
 				      m->name)
-				all(fd, e->exec_id | e->flags, m->flags);
+				all(fd, e, m->flags);
 	}
 
 	igt_fixture {
-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 32+ messages in thread
* [igt-dev] [CI i-g-t 11/14] test/i915: gem_exec_parallel: use the gem_engine_topology library
@ 2019-05-22 13:51   ` Tvrtko Ursulin
  0 siblings, 0 replies; 32+ messages in thread
From: Tvrtko Ursulin @ 2019-05-22 13:51 UTC (permalink / raw)
  To: igt-dev; +Cc: Intel-gfx

From: Andi Shyti <andi.shyti@intel.com>

Replace the legacy for_each_engine* defines with the ones
implemented in the gem_engine_topology library.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/i915/gem_exec_parallel.c | 26 ++++++++++++++------------
 1 file changed, 14 insertions(+), 12 deletions(-)

diff --git a/tests/i915/gem_exec_parallel.c b/tests/i915/gem_exec_parallel.c
index 7597befb0b39..8a4482e52a6e 100644
--- a/tests/i915/gem_exec_parallel.c
+++ b/tests/i915/gem_exec_parallel.c
@@ -149,7 +149,7 @@ static void *thread(void *data)
 	return NULL;
 }
 
-static void all(int fd, unsigned engine, unsigned flags)
+static void all(int fd, struct intel_execution_engine2 *engine, unsigned flags)
 {
 	const int gen = intel_gen(intel_get_drm_devid(fd));
 	pthread_mutex_t mutex;
@@ -170,15 +170,15 @@ static void all(int fd, unsigned engine, unsigned flags)
 	}
 
 	nengine = 0;
-	if (engine == ALL_ENGINES) {
-		for_each_physical_engine(fd, engine) {
-			if (gem_can_store_dword(fd, engine))
-				engines[nengine++] = engine;
+	if (!engine) {
+		struct intel_execution_engine2 *e;
+		__for_each_physical_engine(fd, e) {
+			if (gem_class_can_store_dword(fd, e->class))
+				engines[nengine++] = e->flags;
 		}
 	} else {
-		igt_require(gem_has_ring(fd, engine));
-		igt_require(gem_can_store_dword(fd, engine));
-		engines[nengine++] = engine;
+		igt_require(gem_class_can_store_dword(fd, engine->class));
+		engines[nengine++] = engine->flags;
 	}
 	igt_require(nengine);
 
@@ -229,6 +229,8 @@ static void all(int fd, unsigned engine, unsigned flags)
 
 igt_main
 {
+	struct intel_execution_engine2 *e;
+
 	const struct mode {
 		const char *name;
 		unsigned flags;
@@ -249,16 +251,16 @@ igt_main
 
 	for (const struct mode *m = modes; m->name; m++)
 		igt_subtest_f("%s", *m->name ? m->name : "basic")
-			all(fd, ALL_ENGINES, m->flags);
+			/* NULL value means all engines */
+			all(fd, NULL, m->flags);
 
-	for (const struct intel_execution_engine *e = intel_execution_engines;
-	     e->name; e++) {
+	__for_each_physical_engine(fd, e) {
 		for (const struct mode *m = modes; m->name; m++)
 			igt_subtest_f("%s%s%s",
 				      e->name,
 				      *m->name ? "-" : "",
 				      m->name)
-				all(fd, e->exec_id | e->flags, m->flags);
+				all(fd, e, m->flags);
 	}
 
 	igt_fixture {
-- 
2.20.1

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply related	[flat|nested] 32+ messages in thread
* [CI i-g-t 12/14] test/i915: gem_exec_store: use the gem_engine_topology library
  2019-05-22 13:50 ` [igt-dev] " Tvrtko Ursulin
@ 2019-05-22 13:51   ` Tvrtko Ursulin
  -1 siblings, 0 replies; 32+ messages in thread
From: Tvrtko Ursulin @ 2019-05-22 13:51 UTC (permalink / raw)
  To: igt-dev; +Cc: Intel-gfx

From: Andi Shyti <andi.shyti@intel.com>

Replace the legacy for_each_engine* defines with the ones
implemented in the gem_engine_topology library.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 tests/i915/gem_exec_store.c | 36 ++++++++++++++++++------------------
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/tests/i915/gem_exec_store.c b/tests/i915/gem_exec_store.c
index a767348933ac..b74c3d84bcc2 100644
--- a/tests/i915/gem_exec_store.c
+++ b/tests/i915/gem_exec_store.c
@@ -37,7 +37,7 @@
 
 #define ENGINE_MASK  (I915_EXEC_RING_MASK | LOCAL_I915_EXEC_BSD_MASK)
 
-static void store_dword(int fd, unsigned ring)
+static void store_dword(int fd, const struct intel_execution_engine2 *e)
 {
 	const int gen = intel_gen(intel_get_drm_devid(fd));
 	struct drm_i915_gem_exec_object2 obj[2];
@@ -46,14 +46,13 @@ static void store_dword(int fd, unsigned ring)
 	uint32_t batch[16];
 	int i;
 
-	gem_require_ring(fd, ring);
-	igt_require(gem_can_store_dword(fd, ring));
+	igt_require(gem_class_can_store_dword(fd, e->class));
 
 	intel_detect_and_clear_missed_interrupts(fd);
 	memset(&execbuf, 0, sizeof(execbuf));
 	execbuf.buffers_ptr = to_user_pointer(obj);
 	execbuf.buffer_count = 2;
-	execbuf.flags = ring;
+	execbuf.flags = e->flags;
 	if (gen > 3 && gen < 6)
 		execbuf.flags |= I915_EXEC_SECURE;
 
@@ -97,7 +96,8 @@ static void store_dword(int fd, unsigned ring)
 }
 
 #define PAGES 1
-static void store_cachelines(int fd, unsigned ring, unsigned int flags)
+static void store_cachelines(int fd, const struct intel_execution_engine2 *e,
+			     unsigned int flags)
 {
 	const int gen = intel_gen(intel_get_drm_devid(fd));
 	struct drm_i915_gem_exec_object2 *obj;
@@ -110,13 +110,12 @@ static void store_cachelines(int fd, unsigned ring, unsigned int flags)
 	reloc = calloc(NCACHELINES, sizeof(*reloc));
 	igt_assert(reloc);
 
-	gem_require_ring(fd, ring);
-	igt_require(gem_can_store_dword(fd, ring));
+	igt_require(gem_class_can_store_dword(fd, e->class));
 
 	intel_detect_and_clear_missed_interrupts(fd);
 	memset(&execbuf, 0, sizeof(execbuf));
 	execbuf.buffer_count = flags & PAGES ? NCACHELINES + 1 : 2;
-	execbuf.flags = ring;
+	execbuf.flags = e->flags;
 	if (gen > 3 && gen < 6)
 		execbuf.flags |= I915_EXEC_SECURE;
 
@@ -180,12 +179,13 @@ static void store_all(int fd)
 {
 	const int gen = intel_gen(intel_get_drm_devid(fd));
 	struct drm_i915_gem_exec_object2 obj[2];
+	struct intel_execution_engine2 *engine;
 	struct drm_i915_gem_relocation_entry reloc[32];
 	struct drm_i915_gem_execbuffer2 execbuf;
 	unsigned engines[16], permuted[16];
 	uint32_t batch[16];
 	uint64_t offset;
-	unsigned engine, nengine;
+	unsigned nengine;
 	int value;
 	int i, j;
 
@@ -220,14 +220,14 @@ static void store_all(int fd)
 
 	nengine = 0;
 	intel_detect_and_clear_missed_interrupts(fd);
-	for_each_physical_engine(fd, engine) {
-		if (!gem_can_store_dword(fd, engine))
+	__for_each_physical_engine(fd, engine) {
+		if (!gem_class_can_store_dword(fd, engine->class))
 			continue;
 
 		igt_assert(2*(nengine+1)*sizeof(batch) <= 4096);
 
 		execbuf.flags &= ~ENGINE_MASK;
-		execbuf.flags |= engine;
+		execbuf.flags |= engine->flags;
 
 		j = 2*nengine;
 		reloc[j].target_handle = obj[0].handle;
@@ -259,7 +259,7 @@ static void store_all(int fd)
 		execbuf.batch_start_offset = j*sizeof(batch);
 		gem_execbuf(fd, &execbuf);
 
-		engines[nengine++] = engine;
+		engines[nengine++] = engine->flags;
 	}
 	gem_sync(fd, obj[1].handle);
 
@@ -311,7 +311,7 @@ static int print_welcome(int fd)
 
 igt_main
 {
-	const struct intel_execution_engine *e;
+	const struct intel_execution_engine2 *e;
 	int fd;
 
 	igt_fixture {
@@ -329,15 +329,15 @@ igt_main
 		igt_fork_hang_detector(fd);
 	}
 
-	for (e = intel_execution_engines; e->name; e++) {
+	__for_each_physical_engine(fd, e) {
 		igt_subtest_f("basic-%s", e->name)
-			store_dword(fd, e->exec_id | e->flags);
+			store_dword(fd, e);
 
 		igt_subtest_f("cachelines-%s", e->name)
-			store_cachelines(fd, e->exec_id | e->flags, 0);
+			store_cachelines(fd, e, 0);
 
 		igt_subtest_f("pages-%s", e->name)
-			store_cachelines(fd, e->exec_id | e->flags, PAGES);
+			store_cachelines(fd, e, PAGES);
 	}
 
 	igt_subtest("basic-all")
-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 32+ messages in thread
* [igt-dev] [CI i-g-t 12/14] test/i915: gem_exec_store: use the gem_engine_topology library
@ 2019-05-22 13:51   ` Tvrtko Ursulin
  0 siblings, 0 replies; 32+ messages in thread
From: Tvrtko Ursulin @ 2019-05-22 13:51 UTC (permalink / raw)
  To: igt-dev; +Cc: Intel-gfx

From: Andi Shyti <andi.shyti@intel.com>

Replace the legacy for_each_engine* defines with the ones
implemented in the gem_engine_topology library.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 tests/i915/gem_exec_store.c | 36 ++++++++++++++++++------------------
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/tests/i915/gem_exec_store.c b/tests/i915/gem_exec_store.c
index a767348933ac..b74c3d84bcc2 100644
--- a/tests/i915/gem_exec_store.c
+++ b/tests/i915/gem_exec_store.c
@@ -37,7 +37,7 @@
 
 #define ENGINE_MASK  (I915_EXEC_RING_MASK | LOCAL_I915_EXEC_BSD_MASK)
 
-static void store_dword(int fd, unsigned ring)
+static void store_dword(int fd, const struct intel_execution_engine2 *e)
 {
 	const int gen = intel_gen(intel_get_drm_devid(fd));
 	struct drm_i915_gem_exec_object2 obj[2];
@@ -46,14 +46,13 @@ static void store_dword(int fd, unsigned ring)
 	uint32_t batch[16];
 	int i;
 
-	gem_require_ring(fd, ring);
-	igt_require(gem_can_store_dword(fd, ring));
+	igt_require(gem_class_can_store_dword(fd, e->class));
 
 	intel_detect_and_clear_missed_interrupts(fd);
 	memset(&execbuf, 0, sizeof(execbuf));
 	execbuf.buffers_ptr = to_user_pointer(obj);
 	execbuf.buffer_count = 2;
-	execbuf.flags = ring;
+	execbuf.flags = e->flags;
 	if (gen > 3 && gen < 6)
 		execbuf.flags |= I915_EXEC_SECURE;
 
@@ -97,7 +96,8 @@ static void store_dword(int fd, unsigned ring)
 }
 
 #define PAGES 1
-static void store_cachelines(int fd, unsigned ring, unsigned int flags)
+static void store_cachelines(int fd, const struct intel_execution_engine2 *e,
+			     unsigned int flags)
 {
 	const int gen = intel_gen(intel_get_drm_devid(fd));
 	struct drm_i915_gem_exec_object2 *obj;
@@ -110,13 +110,12 @@ static void store_cachelines(int fd, unsigned ring, unsigned int flags)
 	reloc = calloc(NCACHELINES, sizeof(*reloc));
 	igt_assert(reloc);
 
-	gem_require_ring(fd, ring);
-	igt_require(gem_can_store_dword(fd, ring));
+	igt_require(gem_class_can_store_dword(fd, e->class));
 
 	intel_detect_and_clear_missed_interrupts(fd);
 	memset(&execbuf, 0, sizeof(execbuf));
 	execbuf.buffer_count = flags & PAGES ? NCACHELINES + 1 : 2;
-	execbuf.flags = ring;
+	execbuf.flags = e->flags;
 	if (gen > 3 && gen < 6)
 		execbuf.flags |= I915_EXEC_SECURE;
 
@@ -180,12 +179,13 @@ static void store_all(int fd)
 {
 	const int gen = intel_gen(intel_get_drm_devid(fd));
 	struct drm_i915_gem_exec_object2 obj[2];
+	struct intel_execution_engine2 *engine;
 	struct drm_i915_gem_relocation_entry reloc[32];
 	struct drm_i915_gem_execbuffer2 execbuf;
 	unsigned engines[16], permuted[16];
 	uint32_t batch[16];
 	uint64_t offset;
-	unsigned engine, nengine;
+	unsigned nengine;
 	int value;
 	int i, j;
 
@@ -220,14 +220,14 @@ static void store_all(int fd)
 
 	nengine = 0;
 	intel_detect_and_clear_missed_interrupts(fd);
-	for_each_physical_engine(fd, engine) {
-		if (!gem_can_store_dword(fd, engine))
+	__for_each_physical_engine(fd, engine) {
+		if (!gem_class_can_store_dword(fd, engine->class))
 			continue;
 
 		igt_assert(2*(nengine+1)*sizeof(batch) <= 4096);
 
 		execbuf.flags &= ~ENGINE_MASK;
-		execbuf.flags |= engine;
+		execbuf.flags |= engine->flags;
 
 		j = 2*nengine;
 		reloc[j].target_handle = obj[0].handle;
@@ -259,7 +259,7 @@ static void store_all(int fd)
 		execbuf.batch_start_offset = j*sizeof(batch);
 		gem_execbuf(fd, &execbuf);
 
-		engines[nengine++] = engine;
+		engines[nengine++] = engine->flags;
 	}
 	gem_sync(fd, obj[1].handle);
 
@@ -311,7 +311,7 @@ static int print_welcome(int fd)
 
 igt_main
 {
-	const struct intel_execution_engine *e;
+	const struct intel_execution_engine2 *e;
 	int fd;
 
 	igt_fixture {
@@ -329,15 +329,15 @@ igt_main
 		igt_fork_hang_detector(fd);
 	}
 
-	for (e = intel_execution_engines; e->name; e++) {
+	__for_each_physical_engine(fd, e) {
 		igt_subtest_f("basic-%s", e->name)
-			store_dword(fd, e->exec_id | e->flags);
+			store_dword(fd, e);
 
 		igt_subtest_f("cachelines-%s", e->name)
-			store_cachelines(fd, e->exec_id | e->flags, 0);
+			store_cachelines(fd, e, 0);
 
 		igt_subtest_f("pages-%s", e->name)
-			store_cachelines(fd, e->exec_id | e->flags, PAGES);
+			store_cachelines(fd, e, PAGES);
 	}
 
 	igt_subtest("basic-all")
-- 
2.20.1

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply related	[flat|nested] 32+ messages in thread
* [CI i-g-t 13/14] test/i915: gem_wait: use the gem_engine_topology library
  2019-05-22 13:50 ` [igt-dev] " Tvrtko Ursulin
@ 2019-05-22 13:51   ` Tvrtko Ursulin
  -1 siblings, 0 replies; 32+ messages in thread
From: Tvrtko Ursulin @ 2019-05-22 13:51 UTC (permalink / raw)
  To: igt-dev; +Cc: Intel-gfx

From: Andi Shyti <andi.shyti@intel.com>

Replace the legacy for_each_engine* defines with the ones
implemented in the gem_engine_topology library.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 tests/i915/gem_wait.c | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/tests/i915/gem_wait.c b/tests/i915/gem_wait.c
index ee2ecfa0d056..b5e32219d77b 100644
--- a/tests/i915/gem_wait.c
+++ b/tests/i915/gem_wait.c
@@ -134,7 +134,7 @@ static void basic(int fd, unsigned engine, unsigned flags)
 
 igt_main
 {
-	const struct intel_execution_engine *e;
+	const struct intel_execution_engine2 *e;
 	int fd = -1;
 
 	igt_skip_on_simulation();
@@ -177,27 +177,27 @@ igt_main
 			basic(fd, ALL_ENGINES, WRITE);
 		}
 
-		for (e = intel_execution_engines; e->name; e++) {
+		__for_each_physical_engine(fd, e) {
 			igt_subtest_group {
 				igt_subtest_f("busy-%s", e->name) {
 					gem_quiescent_gpu(fd);
-					basic(fd, e->exec_id | e->flags, BUSY);
+					basic(fd, e->flags, BUSY);
 				}
 				igt_subtest_f("wait-%s", e->name) {
 					gem_quiescent_gpu(fd);
-					basic(fd, e->exec_id | e->flags, 0);
+					basic(fd, e->flags, 0);
 				}
 				igt_subtest_f("await-%s", e->name) {
 					gem_quiescent_gpu(fd);
-					basic(fd, e->exec_id | e->flags, AWAIT);
+					basic(fd, e->flags, AWAIT);
 				}
 				igt_subtest_f("write-busy-%s", e->name) {
 					gem_quiescent_gpu(fd);
-					basic(fd, e->exec_id | e->flags, BUSY | WRITE);
+					basic(fd, e->flags, BUSY | WRITE);
 				}
 				igt_subtest_f("write-wait-%s", e->name) {
 					gem_quiescent_gpu(fd);
-					basic(fd, e->exec_id | e->flags, WRITE);
+					basic(fd, e->flags, WRITE);
 				}
 			}
 		}
@@ -234,22 +234,22 @@ igt_main
 			basic(fd, ALL_ENGINES, WRITE | HANG);
 		}
 
-		for (e = intel_execution_engines; e->name; e++) {
+		__for_each_physical_engine(fd, e) {
 			igt_subtest_f("hang-busy-%s", e->name) {
 				gem_quiescent_gpu(fd);
-				basic(fd, e->exec_id | e->flags, HANG | BUSY);
+				basic(fd, e->flags, HANG | BUSY);
 			}
 			igt_subtest_f("hang-wait-%s", e->name) {
 				gem_quiescent_gpu(fd);
-				basic(fd, e->exec_id | e->flags, HANG);
+				basic(fd, e->flags, HANG);
 			}
 			igt_subtest_f("hang-busy-write-%s", e->name) {
 				gem_quiescent_gpu(fd);
-				basic(fd, e->exec_id | e->flags, HANG | WRITE | BUSY);
+				basic(fd, e->flags, HANG | WRITE | BUSY);
 			}
 			igt_subtest_f("hang-wait-write-%s", e->name) {
 				gem_quiescent_gpu(fd);
-				basic(fd, e->exec_id | e->flags, HANG | WRITE);
+				basic(fd, e->flags, HANG | WRITE);
 			}
 		}
 
-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 32+ messages in thread
* [Intel-gfx] [CI i-g-t 13/14] test/i915: gem_wait: use the gem_engine_topology library
@ 2019-05-22 13:51   ` Tvrtko Ursulin
  0 siblings, 0 replies; 32+ messages in thread
From: Tvrtko Ursulin @ 2019-05-22 13:51 UTC (permalink / raw)
  To: igt-dev; +Cc: Intel-gfx

From: Andi Shyti <andi.shyti@intel.com>

Replace the legacy for_each_engine* defines with the ones
implemented in the gem_engine_topology library.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 tests/i915/gem_wait.c | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/tests/i915/gem_wait.c b/tests/i915/gem_wait.c
index ee2ecfa0d056..b5e32219d77b 100644
--- a/tests/i915/gem_wait.c
+++ b/tests/i915/gem_wait.c
@@ -134,7 +134,7 @@ static void basic(int fd, unsigned engine, unsigned flags)
 
 igt_main
 {
-	const struct intel_execution_engine *e;
+	const struct intel_execution_engine2 *e;
 	int fd = -1;
 
 	igt_skip_on_simulation();
@@ -177,27 +177,27 @@ igt_main
 			basic(fd, ALL_ENGINES, WRITE);
 		}
 
-		for (e = intel_execution_engines; e->name; e++) {
+		__for_each_physical_engine(fd, e) {
 			igt_subtest_group {
 				igt_subtest_f("busy-%s", e->name) {
 					gem_quiescent_gpu(fd);
-					basic(fd, e->exec_id | e->flags, BUSY);
+					basic(fd, e->flags, BUSY);
 				}
 				igt_subtest_f("wait-%s", e->name) {
 					gem_quiescent_gpu(fd);
-					basic(fd, e->exec_id | e->flags, 0);
+					basic(fd, e->flags, 0);
 				}
 				igt_subtest_f("await-%s", e->name) {
 					gem_quiescent_gpu(fd);
-					basic(fd, e->exec_id | e->flags, AWAIT);
+					basic(fd, e->flags, AWAIT);
 				}
 				igt_subtest_f("write-busy-%s", e->name) {
 					gem_quiescent_gpu(fd);
-					basic(fd, e->exec_id | e->flags, BUSY | WRITE);
+					basic(fd, e->flags, BUSY | WRITE);
 				}
 				igt_subtest_f("write-wait-%s", e->name) {
 					gem_quiescent_gpu(fd);
-					basic(fd, e->exec_id | e->flags, WRITE);
+					basic(fd, e->flags, WRITE);
 				}
 			}
 		}
@@ -234,22 +234,22 @@ igt_main
 			basic(fd, ALL_ENGINES, WRITE | HANG);
 		}
 
-		for (e = intel_execution_engines; e->name; e++) {
+		__for_each_physical_engine(fd, e) {
 			igt_subtest_f("hang-busy-%s", e->name) {
 				gem_quiescent_gpu(fd);
-				basic(fd, e->exec_id | e->flags, HANG | BUSY);
+				basic(fd, e->flags, HANG | BUSY);
 			}
 			igt_subtest_f("hang-wait-%s", e->name) {
 				gem_quiescent_gpu(fd);
-				basic(fd, e->exec_id | e->flags, HANG);
+				basic(fd, e->flags, HANG);
 			}
 			igt_subtest_f("hang-busy-write-%s", e->name) {
 				gem_quiescent_gpu(fd);
-				basic(fd, e->exec_id | e->flags, HANG | WRITE | BUSY);
+				basic(fd, e->flags, HANG | WRITE | BUSY);
 			}
 			igt_subtest_f("hang-wait-write-%s", e->name) {
 				gem_quiescent_gpu(fd);
-				basic(fd, e->exec_id | e->flags, HANG | WRITE);
+				basic(fd, e->flags, HANG | WRITE);
 			}
 		}
 
-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 32+ messages in thread
* [CI i-g-t 14/14] test/i915: i915_hangman: use the gem_engine_topology library
  2019-05-22 13:50 ` [igt-dev] " Tvrtko Ursulin
@ 2019-05-22 13:51   ` Tvrtko Ursulin
  -1 siblings, 0 replies; 32+ messages in thread
From: Tvrtko Ursulin @ 2019-05-22 13:51 UTC (permalink / raw)
  To: igt-dev; +Cc: Intel-gfx

From: Andi Shyti <andi.shyti@intel.com>

Replace the legacy for_each_engine* defines with the ones
implemented in the gem_engine_topology library.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 tests/i915/i915_hangman.c | 15 ++++-----------
 1 file changed, 4 insertions(+), 11 deletions(-)

diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
index 9a1d58897ca1..bb5521e03dd3 100644
--- a/tests/i915/i915_hangman.c
+++ b/tests/i915/i915_hangman.c
@@ -256,7 +256,7 @@ static void hangcheck_unterminated(void)
 
 igt_main
 {
-	const struct intel_execution_engine *e;
+	const struct intel_execution_engine2 *e;
 	igt_hang_t hang = {};
 
 	igt_skip_on_simulation();
@@ -276,16 +276,9 @@ igt_main
 	igt_subtest("error-state-basic")
 		test_error_state_basic();
 
-	for (e = intel_execution_engines; e->name; e++) {
-		if (e->exec_id == 0)
-			continue;
-
-		igt_subtest_f("error-state-capture-%s", e->name) {
-			igt_require(gem_ring_has_physical_engine(device, e->exec_id | e->flags));
-			test_error_state_capture(e->exec_id | e->flags,
-						 e->full_name);
-		}
-	}
+	__for_each_physical_engine(device, e)
+		igt_subtest_f("error-state-capture-%s", e->name)
+			test_error_state_capture(e->flags, e->name);
 
 	igt_subtest("hangcheck-unterminated")
 		hangcheck_unterminated();
-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 32+ messages in thread
* [igt-dev] [CI i-g-t 14/14] test/i915: i915_hangman: use the gem_engine_topology library
@ 2019-05-22 13:51   ` Tvrtko Ursulin
  0 siblings, 0 replies; 32+ messages in thread
From: Tvrtko Ursulin @ 2019-05-22 13:51 UTC (permalink / raw)
  To: igt-dev; +Cc: Intel-gfx

From: Andi Shyti <andi.shyti@intel.com>

Replace the legacy for_each_engine* defines with the ones
implemented in the gem_engine_topology library.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 tests/i915/i915_hangman.c | 15 ++++-----------
 1 file changed, 4 insertions(+), 11 deletions(-)

diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
index 9a1d58897ca1..bb5521e03dd3 100644
--- a/tests/i915/i915_hangman.c
+++ b/tests/i915/i915_hangman.c
@@ -256,7 +256,7 @@ static void hangcheck_unterminated(void)
 
 igt_main
 {
-	const struct intel_execution_engine *e;
+	const struct intel_execution_engine2 *e;
 	igt_hang_t hang = {};
 
 	igt_skip_on_simulation();
@@ -276,16 +276,9 @@ igt_main
 	igt_subtest("error-state-basic")
 		test_error_state_basic();
 
-	for (e = intel_execution_engines; e->name; e++) {
-		if (e->exec_id == 0)
-			continue;
-
-		igt_subtest_f("error-state-capture-%s", e->name) {
-			igt_require(gem_ring_has_physical_engine(device, e->exec_id | e->flags));
-			test_error_state_capture(e->exec_id | e->flags,
-						 e->full_name);
-		}
-	}
+	__for_each_physical_engine(device, e)
+		igt_subtest_f("error-state-capture-%s", e->name)
+			test_error_state_capture(e->flags, e->name);
 
 	igt_subtest("hangcheck-unterminated")
 		hangcheck_unterminated();
-- 
2.20.1

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply related	[flat|nested] 32+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for Andi's engine discovery for CI
  2019-05-22 13:50 ` [igt-dev] " Tvrtko Ursulin
                   ` (14 preceding siblings ...)
  (?)
@ 2019-05-22 14:56 ` Patchwork
  -1 siblings, 0 replies; 32+ messages in thread
From: Patchwork @ 2019-05-22 14:56 UTC (permalink / raw)
  To: Tvrtko Ursulin; +Cc: igt-dev

== Series Details ==

Series: Andi's engine discovery for CI
URL   : https://patchwork.freedesktop.org/series/60965/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6121 -> IGTPW_3028
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/60965/revisions/1/mbox/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_3028:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_exec_parallel@basic:
    - {fi-icl-dsi}:       [PASS][1] -> [FAIL][2] +3 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6121/fi-icl-dsi/igt@gem_exec_parallel@basic.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3028/fi-icl-dsi/igt@gem_exec_parallel@basic.html

  * igt@gem_exec_store@basic-all:
    - {fi-icl-u2}:        [PASS][3] -> [FAIL][4] +3 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6121/fi-icl-u2/igt@gem_exec_store@basic-all.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3028/fi-icl-u2/igt@gem_exec_store@basic-all.html

  * igt@gem_wait@basic-await-all:
    - {fi-icl-u3}:        [PASS][5] -> [DMESG-FAIL][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6121/fi-icl-u3/igt@gem_wait@basic-await-all.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3028/fi-icl-u3/igt@gem_wait@basic-await-all.html
    - {fi-icl-u2}:        [PASS][7] -> [DMESG-FAIL][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6121/fi-icl-u2/igt@gem_wait@basic-await-all.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3028/fi-icl-u2/igt@gem_wait@basic-await-all.html
    - {fi-icl-dsi}:       [PASS][9] -> [DMESG-FAIL][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6121/fi-icl-dsi/igt@gem_wait@basic-await-all.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3028/fi-icl-dsi/igt@gem_wait@basic-await-all.html

  * igt@gem_wait@basic-busy-all:
    - {fi-icl-u3}:        [PASS][11] -> [FAIL][12] +3 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6121/fi-icl-u3/igt@gem_wait@basic-busy-all.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3028/fi-icl-u3/igt@gem_wait@basic-busy-all.html

  
Known issues
------------

  Here are the changes found in IGTPW_3028 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_module_load@reload:
    - fi-blb-e6850:       [PASS][13] -> [INCOMPLETE][14] ([fdo#107718])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6121/fi-blb-e6850/igt@i915_module_load@reload.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3028/fi-blb-e6850/igt@i915_module_load@reload.html

  * igt@i915_pm_rpm@module-reload:
    - fi-skl-6770hq:      [PASS][15] -> [FAIL][16] ([fdo#108511])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6121/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3028/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live_hangcheck:
    - fi-skl-iommu:       [PASS][17] -> [INCOMPLETE][18] ([fdo#108602] / [fdo#108744])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6121/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3028/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html
    - fi-apl-guc:         [PASS][19] -> [FAIL][20] ([fdo#110623])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6121/fi-apl-guc/igt@i915_selftest@live_hangcheck.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3028/fi-apl-guc/igt@i915_selftest@live_hangcheck.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-hsw-peppy:       [PASS][21] -> [DMESG-WARN][22] ([fdo#102614])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6121/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3028/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html

  
#### Possible fixes ####

  * igt@gem_mmap_gtt@basic-read-write-distinct:
    - {fi-icl-u3}:        [DMESG-WARN][23] ([fdo#107724]) -> [PASS][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6121/fi-icl-u3/igt@gem_mmap_gtt@basic-read-write-distinct.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3028/fi-icl-u3/igt@gem_mmap_gtt@basic-read-write-distinct.html

  * igt@i915_selftest@live_execlists:
    - fi-apl-guc:         [INCOMPLETE][25] ([fdo#103927] / [fdo#109720]) -> [PASS][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6121/fi-apl-guc/igt@i915_selftest@live_execlists.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3028/fi-apl-guc/igt@i915_selftest@live_execlists.html

  * igt@prime_vgem@basic-fence-flip:
    - fi-ilk-650:         [DMESG-WARN][27] ([fdo#106387]) -> [PASS][28] +1 similar issue
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6121/fi-ilk-650/igt@prime_vgem@basic-fence-flip.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3028/fi-ilk-650/igt@prime_vgem@basic-fence-flip.html

  
#### Warnings ####

  * igt@runner@aborted:
    - fi-apl-guc:         [FAIL][29] ([fdo#108622] / [fdo#109720]) -> [FAIL][30] ([fdo#110622])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6121/fi-apl-guc/igt@runner@aborted.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3028/fi-apl-guc/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#106387]: https://bugs.freedesktop.org/show_bug.cgi?id=106387
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
  [fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602
  [fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
  [fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744
  [fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
  [fdo#110622]: https://bugs.freedesktop.org/show_bug.cgi?id=110622
  [fdo#110623]: https://bugs.freedesktop.org/show_bug.cgi?id=110623


Participating hosts (53 -> 45)
------------------------------

  Missing    (8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * IGT: IGT_5003 -> IGTPW_3028

  CI_DRM_6121: 0a029524f22ca287ec7e515edc1258e7f806750c @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_3028: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3028/
  IGT_5003: 54e6d651d1122dfb6578b8179f782d335fe15864 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools



== Testlist changes ==

+++ 135 lines
--- 184 lines

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3028/
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply	[flat|nested] 32+ messages in thread
* [igt-dev] ✓ Fi.CI.IGT: success for Andi's engine discovery for CI
  2019-05-22 13:50 ` [igt-dev] " Tvrtko Ursulin
                   ` (15 preceding siblings ...)
  (?)
@ 2019-05-23 10:43 ` Patchwork
  -1 siblings, 0 replies; 32+ messages in thread
From: Patchwork @ 2019-05-23 10:43 UTC (permalink / raw)
  To: Tvrtko Ursulin; +Cc: igt-dev

== Series Details ==

Series: Andi's engine discovery for CI
URL   : https://patchwork.freedesktop.org/series/60965/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6121_full -> IGTPW_3028_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/60965/revisions/1/mbox/

New tests
---------

  New tests have been introduced between CI_DRM_6121_full and IGTPW_3028_full:

### New IGT tests (106) ###

  * igt@gem_busy@basic-busy-rcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.00] s

  * igt@gem_busy@basic-hang-rcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.01, 0.03] s

  * igt@gem_busy@busy-bcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.00] s

  * igt@gem_busy@busy-vcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.00] s

  * igt@gem_busy@busy-vcs1:
    - Statuses : 1 pass(s)
    - Exec time: [0.00] s

  * igt@gem_busy@busy-vecs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0, 0.00] s

  * igt@gem_busy@extended-bcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.01, 0.04] s

  * igt@gem_busy@extended-parallel-bcs0:
    - Statuses : 1 incomplete(s) 4 pass(s)
    - Exec time: [0.0, 0.03] s

  * igt@gem_busy@extended-parallel-rcs0:
    - Statuses : 1 incomplete(s) 4 pass(s)
    - Exec time: [0.0, 0.04] s

  * igt@gem_busy@extended-parallel-vcs0:
    - Statuses : 4 pass(s) 1 skip(s)
    - Exec time: [0.0, 0.04] s

  * igt@gem_busy@extended-parallel-vcs1:
    - Statuses : 1 pass(s)
    - Exec time: [0.04] s

  * igt@gem_busy@extended-parallel-vecs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.01, 0.04] s

  * igt@gem_busy@extended-rcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.01, 0.04] s

  * igt@gem_busy@extended-semaphore-bcs0:
    - Statuses : 3 pass(s) 2 skip(s)
    - Exec time: [0.0, 0.00] s

  * igt@gem_busy@extended-semaphore-rcs0:
    - Statuses : 3 pass(s) 2 skip(s)
    - Exec time: [0.0, 0.00] s

  * igt@gem_busy@extended-semaphore-vcs0:
    - Statuses : 3 pass(s) 2 skip(s)
    - Exec time: [0.0, 0.01] s

  * igt@gem_busy@extended-semaphore-vcs1:
    - Statuses : 1 pass(s)
    - Exec time: [0.00] s

  * igt@gem_busy@extended-semaphore-vecs0:
    - Statuses : 3 pass(s) 1 skip(s)
    - Exec time: [0.0, 0.01] s

  * igt@gem_busy@extended-vcs0:
    - Statuses : 4 pass(s) 1 skip(s)
    - Exec time: [0.0, 0.03] s

  * igt@gem_busy@extended-vcs1:
    - Statuses : 1 pass(s)
    - Exec time: [0.03] s

  * igt@gem_busy@extended-vecs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.01, 0.03] s

  * igt@gem_cs_tlb@bcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.75, 4.65] s

  * igt@gem_cs_tlb@rcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.77, 5.46] s

  * igt@gem_cs_tlb@vcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.97, 5.25] s

  * igt@gem_cs_tlb@vcs1:
    - Statuses : 1 pass(s)
    - Exec time: [1.93] s

  * igt@gem_cs_tlb@vecs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.75, 4.59] s

  * igt@gem_ctx_exec@basic-invalid-context-bcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.00] s

  * igt@gem_ctx_exec@basic-invalid-context-rcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.00] s

  * igt@gem_ctx_exec@basic-invalid-context-vcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.00] s

  * igt@gem_ctx_exec@basic-invalid-context-vcs1:
    - Statuses : 1 pass(s)
    - Exec time: [0.00] s

  * igt@gem_ctx_exec@basic-invalid-context-vecs0:
    - Statuses : 3 pass(s)
    - Exec time: [0.00] s

  * igt@gem_exec_basic@basic-bcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.0, 0.00] s

  * igt@gem_exec_basic@basic-rcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.0, 0.00] s

  * igt@gem_exec_basic@basic-vcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.0, 0.00] s

  * igt@gem_exec_basic@basic-vcs1:
    - Statuses : 1 pass(s)
    - Exec time: [0.00] s

  * igt@gem_exec_basic@basic-vecs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0, 0.00] s

  * igt@gem_exec_basic@gtt-bcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.0, 0.00] s

  * igt@gem_exec_basic@gtt-rcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.0, 0.00] s

  * igt@gem_exec_basic@gtt-vcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.00] s

  * igt@gem_exec_basic@gtt-vcs1:
    - Statuses : 1 pass(s)
    - Exec time: [0.00] s

  * igt@gem_exec_basic@gtt-vecs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.00] s

  * igt@gem_exec_basic@readonly-bcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.0, 0.00] s

  * igt@gem_exec_basic@readonly-rcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.0, 0.00] s

  * igt@gem_exec_basic@readonly-vcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.0, 0.00] s

  * igt@gem_exec_basic@readonly-vcs1:
    - Statuses : 1 pass(s)
    - Exec time: [0.00] s

  * igt@gem_exec_basic@readonly-vecs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0, 0.00] s

  * igt@gem_exec_parallel@bcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.82, 2.28] s

  * igt@gem_exec_parallel@bcs0-contexts:
    - Statuses : 5 pass(s)
    - Exec time: [1.42, 5.16] s

  * igt@gem_exec_parallel@bcs0-fds:
    - Statuses : 5 pass(s)
    - Exec time: [1.41, 5.32] s

  * igt@gem_exec_parallel@rcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.79, 2.44] s

  * igt@gem_exec_parallel@rcs0-contexts:
    - Statuses : 5 pass(s)
    - Exec time: [1.42, 5.12] s

  * igt@gem_exec_parallel@rcs0-fds:
    - Statuses : 4 pass(s)
    - Exec time: [1.42, 5.31] s

  * igt@gem_exec_parallel@vcs0:
    - Statuses : 4 pass(s) 1 skip(s)
    - Exec time: [0.0, 2.29] s

  * igt@gem_exec_parallel@vcs0-contexts:
    - Statuses : 4 pass(s) 1 skip(s)
    - Exec time: [0.0, 4.43] s

  * igt@gem_exec_parallel@vcs0-fds:
    - Statuses : 4 pass(s) 1 skip(s)
    - Exec time: [0.0, 4.58] s

  * igt@gem_exec_parallel@vcs1:
    - Statuses : 1 pass(s)
    - Exec time: [0.83] s

  * igt@gem_exec_parallel@vcs1-contexts:
    - Statuses : 1 pass(s)
    - Exec time: [1.58] s

  * igt@gem_exec_parallel@vcs1-fds:
    - Statuses : 1 pass(s)
    - Exec time: [1.66] s

  * igt@gem_exec_parallel@vecs0:
    - Statuses : 3 pass(s)
    - Exec time: [0.82, 2.30] s

  * igt@gem_exec_parallel@vecs0-contexts:
    - Statuses : 4 pass(s)
    - Exec time: [1.26, 4.35] s

  * igt@gem_exec_parallel@vecs0-fds:
    - Statuses : 4 pass(s)
    - Exec time: [1.29, 4.59] s

  * igt@gem_exec_store@basic-bcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.01, 0.02] s

  * igt@gem_exec_store@basic-rcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.01] s

  * igt@gem_exec_store@basic-vcs0:
    - Statuses : 4 pass(s) 1 skip(s)
    - Exec time: [0.0, 0.01] s

  * igt@gem_exec_store@basic-vcs1:
    - Statuses : 1 pass(s)
    - Exec time: [0.01] s

  * igt@gem_exec_store@basic-vecs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.01] s

  * igt@gem_exec_store@cachelines-bcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.01, 0.02] s

  * igt@gem_exec_store@cachelines-rcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.01, 0.04] s

  * igt@gem_exec_store@cachelines-vcs0:
    - Statuses : 4 pass(s) 1 skip(s)
    - Exec time: [0.0, 0.01] s

  * igt@gem_exec_store@cachelines-vcs1:
    - Statuses : 1 pass(s)
    - Exec time: [0.01] s

  * igt@gem_exec_store@cachelines-vecs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.01] s

  * igt@gem_exec_store@pages-bcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.01, 0.03] s

  * igt@gem_exec_store@pages-rcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.01, 0.02] s

  * igt@gem_exec_store@pages-vcs0:
    - Statuses : 4 pass(s) 1 skip(s)
    - Exec time: [0.0, 0.03] s

  * igt@gem_exec_store@pages-vcs1:
    - Statuses : 1 pass(s)
    - Exec time: [0.01] s

  * igt@gem_exec_store@pages-vecs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.01, 0.02] s

  * igt@gem_wait@await-bcs0:
    - Statuses : 3 pass(s)
    - Exec time: [1.01, 1.02] s

  * igt@gem_wait@await-rcs0:
    - Statuses : 5 pass(s)
    - Exec time: [1.01, 1.02] s

  * igt@gem_wait@await-vcs0:
    - Statuses : 5 pass(s)
    - Exec time: [1.01, 1.02] s

  * igt@gem_wait@await-vcs1:
    - Statuses : 1 pass(s)
    - Exec time: [1.02] s

  * igt@gem_wait@await-vecs0:
    - Statuses : 4 pass(s)
    - Exec time: [1.00, 1.02] s

  * igt@gem_wait@busy-bcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.50] s

  * igt@gem_wait@busy-rcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.50, 0.51] s

  * igt@gem_wait@busy-vcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.50] s

  * igt@gem_wait@busy-vcs1:
    - Statuses : 1 pass(s)
    - Exec time: [0.50] s

  * igt@gem_wait@busy-vecs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.50] s

  * igt@gem_wait@wait-bcs0:
    - Statuses : 5 pass(s)
    - Exec time: [1.00, 1.01] s

  * igt@gem_wait@wait-rcs0:
    - Statuses : 5 pass(s)
    - Exec time: [1.01, 1.02] s

  * igt@gem_wait@wait-vcs0:
    - Statuses : 5 pass(s)
    - Exec time: [1.00, 1.01] s

  * igt@gem_wait@wait-vcs1:
    - Statuses : 1 pass(s)
    - Exec time: [1.01] s

  * igt@gem_wait@wait-vecs0:
    - Statuses : 4 pass(s)
    - Exec time: [1.01, 1.02] s

  * igt@gem_wait@write-busy-bcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.50, 0.51] s

  * igt@gem_wait@write-busy-rcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.50, 0.51] s

  * igt@gem_wait@write-busy-vcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.50, 0.51] s

  * igt@gem_wait@write-busy-vcs1:
    - Statuses : 1 pass(s)
    - Exec time: [0.50] s

  * igt@gem_wait@write-busy-vecs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.50, 0.51] s

  * igt@gem_wait@write-wait-bcs0:
    - Statuses : 5 pass(s)
    - Exec time: [1.01, 1.02] s

  * igt@gem_wait@write-wait-rcs0:
    - Statuses : 5 pass(s)
    - Exec time: [1.01, 1.02] s

  * igt@gem_wait@write-wait-vcs0:
    - Statuses : 5 pass(s)
    - Exec time: [1.00, 1.02] s

  * igt@gem_wait@write-wait-vcs1:
    - Statuses : 1 pass(s)
    - Exec time: [1.02] s

  * igt@gem_wait@write-wait-vecs0:
    - Statuses : 4 pass(s)
    - Exec time: [1.01, 1.03] s

  * igt@i915_hangman@error-state-capture-bcs0:
    - Statuses : 5 pass(s)
    - Exec time: [13.33, 16.48] s

  * igt@i915_hangman@error-state-capture-rcs0:
    - Statuses : 5 pass(s)
    - Exec time: [13.27, 14.80] s

  * igt@i915_hangman@error-state-capture-vcs0:
    - Statuses : 4 pass(s)
    - Exec time: [12.29, 15.62] s

  * igt@i915_hangman@error-state-capture-vcs1:
    - Statuses : 1 pass(s)
    - Exec time: [15.57] s

  * igt@i915_hangman@error-state-capture-vecs0:
    - Statuses : 4 pass(s)
    - Exec time: [9.23, 15.00] s

  

Known issues
------------

  Here are the changes found in IGTPW_3028_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_workarounds@suspend-resume-context:
    - shard-apl:          [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +4 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6121/shard-apl3/igt@gem_workarounds@suspend-resume-context.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3028/shard-apl7/igt@gem_workarounds@suspend-resume-context.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-glk:          [PASS][3] -> [FAIL][4] ([fdo#102887] / [fdo#105363])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6121/shard-glk2/igt@kms_flip@flip-vs-expired-vblank.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3028/shard-glk3/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_frontbuffer_tracking@fbc-2p-pri-indfb-multidraw:
    - shard-hsw:          [PASS][5] -> [SKIP][6] ([fdo#109271])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6121/shard-hsw6/igt@kms_frontbuffer_tracking@fbc-2p-pri-indfb-multidraw.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3028/shard-hsw2/igt@kms_frontbuffer_tracking@fbc-2p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@fbc-stridechange:
    - shard-glk:          [PASS][7] -> [FAIL][8] ([fdo#103167])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6121/shard-glk6/igt@kms_frontbuffer_tracking@fbc-stridechange.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3028/shard-glk7/igt@kms_frontbuffer_tracking@fbc-stridechange.html
    - shard-apl:          [PASS][9] -> [FAIL][10] ([fdo#103167])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6121/shard-apl7/igt@kms_frontbuffer_tracking@fbc-stridechange.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3028/shard-apl1/igt@kms_frontbuffer_tracking@fbc-stridechange.html
    - shard-kbl:          [PASS][11] -> [FAIL][12] ([fdo#103167])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6121/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-stridechange.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3028/shard-kbl2/igt@kms_frontbuffer_tracking@fbc-stridechange.html

  * igt@kms_setmode@basic:
    - shard-apl:          [PASS][13] -> [FAIL][14] ([fdo#99912])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6121/shard-apl4/igt@kms_setmode@basic.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3028/shard-apl3/igt@kms_setmode@basic.html
    - shard-kbl:          [PASS][15] -> [FAIL][16] ([fdo#99912])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6121/shard-kbl4/igt@kms_setmode@basic.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3028/shard-kbl2/igt@kms_setmode@basic.html

  
#### Possible fixes ####

  * {igt@kms_cursor_crc@pipe-a-cursor-128x128-random}:
    - shard-kbl:          [FAIL][17] ([fdo#103232]) -> [PASS][18] +1 similar issue
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6121/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-128x128-random.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3028/shard-kbl2/igt@kms_cursor_crc@pipe-a-cursor-128x128-random.html

  * {igt@kms_cursor_crc@pipe-b-cursor-dpms}:
    - shard-apl:          [FAIL][19] ([fdo#103232]) -> [PASS][20] +1 similar issue
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6121/shard-apl6/igt@kms_cursor_crc@pipe-b-cursor-dpms.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3028/shard-apl6/igt@kms_cursor_crc@pipe-b-cursor-dpms.html

  * igt@kms_lease@lease-uevent:
    - shard-apl:          [DMESG-WARN][21] ([fdo#103558] / [fdo#105602]) -> [PASS][22] +10 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6121/shard-apl6/igt@kms_lease@lease-uevent.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3028/shard-apl6/igt@kms_lease@lease-uevent.html

  * igt@kms_vblank@pipe-c-ts-continuation-suspend:
    - shard-apl:          [DMESG-WARN][23] ([fdo#108566]) -> [PASS][24] +4 similar issues
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6121/shard-apl4/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3028/shard-apl1/igt@kms_vblank@pipe-c-ts-continuation-suspend.html

  * igt@perf_pmu@rc6:
    - shard-kbl:          [SKIP][25] ([fdo#109271]) -> [PASS][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6121/shard-kbl7/igt@perf_pmu@rc6.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3028/shard-kbl4/igt@perf_pmu@rc6.html

  
#### Warnings ####

  * igt@kms_busy@extended-modeset-hang-oldfb-render-d:
    - shard-apl:          [SKIP][27] ([fdo#105602] / [fdo#109271] / [fdo#109278]) -> [SKIP][28] ([fdo#109271] / [fdo#109278])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6121/shard-apl6/igt@kms_busy@extended-modeset-hang-oldfb-render-d.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3028/shard-apl7/igt@kms_busy@extended-modeset-hang-oldfb-render-d.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-plflip-blt:
    - shard-apl:          [SKIP][29] ([fdo#105602] / [fdo#109271]) -> [SKIP][30] ([fdo#109271]) +3 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6121/shard-apl6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-plflip-blt.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3028/shard-apl1/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-plflip-blt.html

  * igt@prime_nv_api@i915_nv_import_twice:
    - shard-hsw:          [INCOMPLETE][31] ([fdo#103540]) -> [SKIP][32] ([fdo#109271])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6121/shard-hsw7/igt@prime_nv_api@i915_nv_import_twice.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3028/shard-hsw4/igt@prime_nv_api@i915_nv_import_twice.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#102887]: https://bugs.freedesktop.org/show_bug.cgi?id=102887
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
  [fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912


Participating hosts (10 -> 5)
------------------------------

  Missing    (5): shard-skl pig-hsw-4770r pig-glk-j5005 shard-iclb pig-skl-6260u 


Build changes
-------------

  * IGT: IGT_5003 -> IGTPW_3028
  * Piglit: piglit_4509 -> None

  CI_DRM_6121: 0a029524f22ca287ec7e515edc1258e7f806750c @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_3028: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3028/
  IGT_5003: 54e6d651d1122dfb6578b8179f782d335fe15864 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3028/
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply	[flat|nested] 32+ messages in thread
end of thread, other threads:[~2019-05-23 10:43 UTC | newest]

Thread overview: 32+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-05-22 13:50 [CI i-g-t 00/14] Andi's engine discovery for CI Tvrtko Ursulin
2019-05-22 13:50 ` [igt-dev] " Tvrtko Ursulin
2019-05-22 13:50 ` [CI i-g-t 01/14] drm-uapi: Import i915_drm.h upto c5d3e39caa456b1e061644b739131f2b54c84c08 Tvrtko Ursulin
2019-05-22 13:50   ` [Intel-gfx] " Tvrtko Ursulin
2019-05-22 13:50 ` [CI i-g-t 02/14] lib/i915: add gem_engine_topology library and for_each loop definition Tvrtko Ursulin
2019-05-22 13:50   ` [Intel-gfx] " Tvrtko Ursulin
2019-05-22 13:50 ` [CI i-g-t 03/14] lib: igt_gt: add execution buffer flags to class helper Tvrtko Ursulin
2019-05-22 13:50   ` [igt-dev] " Tvrtko Ursulin
2019-05-22 13:50 ` [CI i-g-t 04/14] lib: igt_gt: make gem_engine_can_store_dword() check engine class Tvrtko Ursulin
2019-05-22 13:50   ` [igt-dev] " Tvrtko Ursulin
2019-05-22 13:50 ` [CI i-g-t 05/14] lib: igt_dummyload: use for_each_context_engine() Tvrtko Ursulin
2019-05-22 13:50   ` [igt-dev] " Tvrtko Ursulin
2019-05-22 13:50 ` [CI i-g-t 06/14] test: perf_pmu: use the gem_engine_topology library Tvrtko Ursulin
2019-05-22 13:50   ` [Intel-gfx] " Tvrtko Ursulin
2019-05-22 13:50 ` [CI i-g-t 07/14] test/i915: gem_busy: " Tvrtko Ursulin
2019-05-22 13:50   ` [igt-dev] " Tvrtko Ursulin
2019-05-22 13:50 ` [CI i-g-t 08/14] test/i915: gem_cs_tlb: " Tvrtko Ursulin
2019-05-22 13:50   ` [Intel-gfx] " Tvrtko Ursulin
2019-05-22 13:50 ` [CI i-g-t 09/14] test/i915: gem_ctx_exec: " Tvrtko Ursulin
2019-05-22 13:50   ` [igt-dev] " Tvrtko Ursulin
2019-05-22 13:51 ` [CI i-g-t 10/14] test/i915: gem_exec_basic: " Tvrtko Ursulin
2019-05-22 13:51   ` [igt-dev] " Tvrtko Ursulin
2019-05-22 13:51 ` [CI i-g-t 11/14] test/i915: gem_exec_parallel: " Tvrtko Ursulin
2019-05-22 13:51   ` [igt-dev] " Tvrtko Ursulin
2019-05-22 13:51 ` [CI i-g-t 12/14] test/i915: gem_exec_store: " Tvrtko Ursulin
2019-05-22 13:51   ` [igt-dev] " Tvrtko Ursulin
2019-05-22 13:51 ` [CI i-g-t 13/14] test/i915: gem_wait: " Tvrtko Ursulin
2019-05-22 13:51   ` [Intel-gfx] " Tvrtko Ursulin
2019-05-22 13:51 ` [CI i-g-t 14/14] test/i915: i915_hangman: " Tvrtko Ursulin
2019-05-22 13:51   ` [igt-dev] " Tvrtko Ursulin
2019-05-22 14:56 ` [igt-dev] ✓ Fi.CI.BAT: success for Andi's engine discovery for CI Patchwork
2019-05-23 10:43 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork

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