* [PATCH v4 01/22] drm/i915/guc: Change platform default GuC mode
2019-05-23 23:30 [PATCH v4 00/22] GuC 32.0.3 Michal Wajdeczko
@ 2019-05-23 23:30 ` Michal Wajdeczko
2019-05-27 11:36 ` Joonas Lahtinen
2019-05-23 23:30 ` [PATCH v4 02/22] drm/i915/guc: Don't allow GuC submission Michal Wajdeczko
` (23 subsequent siblings)
24 siblings, 1 reply; 34+ messages in thread
From: Michal Wajdeczko @ 2019-05-23 23:30 UTC (permalink / raw)
To: intel-gfx
Today our most desired GuC configuration is to only enable HuC
if it is available and we really don't care about GuC submission.
Change platform default GuC mode to match our desire.
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: John Spotswood <john.a.spotswood@intel.com>
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Cc: Tony Ye <tony.ye@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Jeff Mcgee <jeff.mcgee@intel.com>
Cc: Antonio Argenziano <antonio.argenziano@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Acked-by: Tony Ye <tony.ye@intel.com>
Reviewed-by: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
---
drivers/gpu/drm/i915/intel_uc.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 63fc12cbc25d..1a265fbd95c7 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -57,10 +57,8 @@ static int __get_platform_enable_guc(struct drm_i915_private *i915)
struct intel_uc_fw *huc_fw = &i915->huc.fw;
int enable_guc = 0;
- /* Default is to enable GuC/HuC if we know their firmwares */
- if (intel_uc_fw_is_selected(guc_fw))
- enable_guc |= ENABLE_GUC_SUBMISSION;
- if (intel_uc_fw_is_selected(huc_fw))
+ /* Default is to use HuC if we know GuC and HuC firmwares */
+ if (intel_uc_fw_is_selected(guc_fw) && intel_uc_fw_is_selected(huc_fw))
enable_guc |= ENABLE_GUC_LOAD_HUC;
/* Any platform specific fine-tuning can be done here */
--
2.19.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread* Re: [PATCH v4 01/22] drm/i915/guc: Change platform default GuC mode
2019-05-23 23:30 ` [PATCH v4 01/22] drm/i915/guc: Change platform default GuC mode Michal Wajdeczko
@ 2019-05-27 11:36 ` Joonas Lahtinen
0 siblings, 0 replies; 34+ messages in thread
From: Joonas Lahtinen @ 2019-05-27 11:36 UTC (permalink / raw)
To: Michal Wajdeczko, intel-gfx
Quoting Michal Wajdeczko (2019-05-24 02:30:28)
> Today our most desired GuC configuration is to only enable HuC
> if it is available and we really don't care about GuC submission.
> Change platform default GuC mode to match our desire.
You should amend here that the HuC authentication is needed to enable
all media codecs on the hardware.
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: John Spotswood <john.a.spotswood@intel.com>
> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> Cc: Tony Ye <tony.ye@intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Jeff Mcgee <jeff.mcgee@intel.com>
> Cc: Antonio Argenziano <antonio.argenziano@intel.com>
> Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
> Acked-by: Tony Ye <tony.ye@intel.com>
> Reviewed-by: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
With the patch message amended, this is:
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Regards, Joonas
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH v4 02/22] drm/i915/guc: Don't allow GuC submission
2019-05-23 23:30 [PATCH v4 00/22] GuC 32.0.3 Michal Wajdeczko
2019-05-23 23:30 ` [PATCH v4 01/22] drm/i915/guc: Change platform default GuC mode Michal Wajdeczko
@ 2019-05-23 23:30 ` Michal Wajdeczko
2019-05-27 11:40 ` Joonas Lahtinen
2019-05-23 23:30 ` [PATCH v4 03/22] drm/i915/guc: Update GuC firmware versions and names Michal Wajdeczko
` (22 subsequent siblings)
24 siblings, 1 reply; 34+ messages in thread
From: Michal Wajdeczko @ 2019-05-23 23:30 UTC (permalink / raw)
To: intel-gfx
Due to the upcoming changes to the GuC ABI interface, we must
disable GuC submission mode until final ABI will be available
on all GuC firmwares.
To avoid regressions on systems configured to run with no longer
supported configuration "enable_guc=3" or "enable_guc=1" clear
GuC submission bit.
v2: force switch to non-GuC submission mode
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: John Spotswood <john.a.spotswood@intel.com>
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Cc: Tony Ye <tony.ye@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Jeff Mcgee <jeff.mcgee@intel.com>
Cc: Antonio Argenziano <antonio.argenziano@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Cc: Martin Peres <martin.peres@linux.intel.com>
Acked-by: Martin Peres <martin.peres@linux.intel.com>
---
drivers/gpu/drm/i915/intel_uc.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 1a265fbd95c7..f66105d756df 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -130,6 +130,15 @@ static void sanitize_options_early(struct drm_i915_private *i915)
"no HuC firmware");
}
+ /* XXX: GuC submission is unavailable for now */
+ if (intel_uc_is_using_guc_submission(i915)) {
+ DRM_INFO("Incompatible option detected: %s=%d, %s!\n",
+ "enable_guc", i915_modparams.enable_guc,
+ "GuC submission not supported");
+ DRM_INFO("Switching to non-GuC submission mode!\n");
+ i915_modparams.enable_guc &= ~ENABLE_GUC_SUBMISSION;
+ }
+
/* A negative value means "use platform/config default" */
if (i915_modparams.guc_log_level < 0)
i915_modparams.guc_log_level =
@@ -298,6 +307,10 @@ int intel_uc_init(struct drm_i915_private *i915)
if (!HAS_GUC(i915))
return -ENODEV;
+ /* XXX: GuC submission is unavailable for now */
+ if (USES_GUC_SUBMISSION(i915))
+ return -EIO;
+
ret = intel_guc_init(guc);
if (ret)
return ret;
--
2.19.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread* Re: [PATCH v4 02/22] drm/i915/guc: Don't allow GuC submission
2019-05-23 23:30 ` [PATCH v4 02/22] drm/i915/guc: Don't allow GuC submission Michal Wajdeczko
@ 2019-05-27 11:40 ` Joonas Lahtinen
2019-05-27 11:59 ` Michal Wajdeczko
0 siblings, 1 reply; 34+ messages in thread
From: Joonas Lahtinen @ 2019-05-27 11:40 UTC (permalink / raw)
To: Michal Wajdeczko, intel-gfx
Quoting Michal Wajdeczko (2019-05-24 02:30:29)
> Due to the upcoming changes to the GuC ABI interface, we must
> disable GuC submission mode until final ABI will be available
> on all GuC firmwares.
>
> To avoid regressions on systems configured to run with no longer
> supported configuration "enable_guc=3" or "enable_guc=1" clear
> GuC submission bit.
>
> v2: force switch to non-GuC submission mode
>
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: John Spotswood <john.a.spotswood@intel.com>
> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> Cc: Tony Ye <tony.ye@intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Jeff Mcgee <jeff.mcgee@intel.com>
> Cc: Antonio Argenziano <antonio.argenziano@intel.com>
> Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
> Cc: Martin Peres <martin.peres@linux.intel.com>
> Acked-by: Martin Peres <martin.peres@linux.intel.com>
> diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
> index 1a265fbd95c7..f66105d756df 100644
> --- a/drivers/gpu/drm/i915/intel_uc.c
> +++ b/drivers/gpu/drm/i915/intel_uc.c
> @@ -298,6 +307,10 @@ int intel_uc_init(struct drm_i915_private *i915)
> if (!HAS_GUC(i915))
> return -ENODEV;
>
> + /* XXX: GuC submission is unavailable for now */
> + if (USES_GUC_SUBMISSION(i915))
> + return -EIO;
> +
This would be a driver programmer error, wouldn't it?
Maybe add GEM_BUG_ON() to the later branch that does the check?
Regards, Joonas
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v4 02/22] drm/i915/guc: Don't allow GuC submission
2019-05-27 11:40 ` Joonas Lahtinen
@ 2019-05-27 11:59 ` Michal Wajdeczko
0 siblings, 0 replies; 34+ messages in thread
From: Michal Wajdeczko @ 2019-05-27 11:59 UTC (permalink / raw)
To: intel-gfx, Joonas Lahtinen
On Mon, 27 May 2019 13:40:25 +0200, Joonas Lahtinen
<joonas.lahtinen@linux.intel.com> wrote:
> Quoting Michal Wajdeczko (2019-05-24 02:30:29)
>> Due to the upcoming changes to the GuC ABI interface, we must
>> disable GuC submission mode until final ABI will be available
>> on all GuC firmwares.
>>
>> To avoid regressions on systems configured to run with no longer
>> supported configuration "enable_guc=3" or "enable_guc=1" clear
>> GuC submission bit.
>>
>> v2: force switch to non-GuC submission mode
>>
>> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Cc: John Spotswood <john.a.spotswood@intel.com>
>> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
>> Cc: Tony Ye <tony.ye@intel.com>
>> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> Cc: Jeff Mcgee <jeff.mcgee@intel.com>
>> Cc: Antonio Argenziano <antonio.argenziano@intel.com>
>> Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
>> Cc: Martin Peres <martin.peres@linux.intel.com>
>> Acked-by: Martin Peres <martin.peres@linux.intel.com>
>
>> diff --git a/drivers/gpu/drm/i915/intel_uc.c
>> b/drivers/gpu/drm/i915/intel_uc.c
>> index 1a265fbd95c7..f66105d756df 100644
>> --- a/drivers/gpu/drm/i915/intel_uc.c
>> +++ b/drivers/gpu/drm/i915/intel_uc.c
>> @@ -298,6 +307,10 @@ int intel_uc_init(struct drm_i915_private *i915)
>> if (!HAS_GUC(i915))
>> return -ENODEV;
>>
>> + /* XXX: GuC submission is unavailable for now */
>> + if (USES_GUC_SUBMISSION(i915))
>> + return -EIO;
>> +
>
> This would be a driver programmer error, wouldn't it?
>
> Maybe add GEM_BUG_ON() to the later branch that does the check?
Yes as this should never happen now as in v2 we forced non-GuC submission
mode (it was needed only in v1 where we were just printing message)
Thanks for catching that!
>
> Regards, Joonas
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH v4 03/22] drm/i915/guc: Update GuC firmware versions and names
2019-05-23 23:30 [PATCH v4 00/22] GuC 32.0.3 Michal Wajdeczko
2019-05-23 23:30 ` [PATCH v4 01/22] drm/i915/guc: Change platform default GuC mode Michal Wajdeczko
2019-05-23 23:30 ` [PATCH v4 02/22] drm/i915/guc: Don't allow GuC submission Michal Wajdeczko
@ 2019-05-23 23:30 ` Michal Wajdeczko
2019-05-23 23:30 ` [PATCH v4 04/22] drm/i915/guc: Update GuC firmware CSS header Michal Wajdeczko
` (21 subsequent siblings)
24 siblings, 0 replies; 34+ messages in thread
From: Michal Wajdeczko @ 2019-05-23 23:30 UTC (permalink / raw)
To: intel-gfx
GuC firmware changed its release version numbering schema and now it
also includes patch version. Update our GuC firmware path definitions
to match new pattern:
<platform>_guc_<major>.<minor>.<patch>.bin
While here, reorder platform checks and start from the latest.
v2: keep single platform defs in one block (Daniele)
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Jeff Mcgee <jeff.mcgee@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/intel_guc_fw.c | 75 ++++++++++++++++-------------
1 file changed, 41 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c b/drivers/gpu/drm/i915/intel_guc_fw.c
index 8b2dcc70b956..c740bf3731de 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -30,53 +30,60 @@
#include "intel_guc_fw.h"
#include "i915_drv.h"
-#define SKL_FW_MAJOR 9
-#define SKL_FW_MINOR 33
-
-#define BXT_FW_MAJOR 9
-#define BXT_FW_MINOR 29
-
-#define KBL_FW_MAJOR 9
-#define KBL_FW_MINOR 39
-
-#define GUC_FW_PATH(platform, major, minor) \
- "i915/" __stringify(platform) "_guc_ver" __stringify(major) "_" __stringify(minor) ".bin"
-
-#define I915_SKL_GUC_UCODE GUC_FW_PATH(skl, SKL_FW_MAJOR, SKL_FW_MINOR)
-MODULE_FIRMWARE(I915_SKL_GUC_UCODE);
-
-#define I915_BXT_GUC_UCODE GUC_FW_PATH(bxt, BXT_FW_MAJOR, BXT_FW_MINOR)
-MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
-
-#define I915_KBL_GUC_UCODE GUC_FW_PATH(kbl, KBL_FW_MAJOR, KBL_FW_MINOR)
-MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
+#define __MAKE_GUC_FW_PATH(KEY) \
+ "i915/" \
+ __stringify(KEY##_GUC_FW_PREFIX) "_guc_" \
+ __stringify(KEY##_GUC_FW_MAJOR) "." \
+ __stringify(KEY##_GUC_FW_MINOR) "." \
+ __stringify(KEY##_GUC_FW_PATCH) ".bin"
+
+#define SKL_GUC_FW_PREFIX skl
+#define SKL_GUC_FW_MAJOR 32
+#define SKL_GUC_FW_MINOR 0
+#define SKL_GUC_FW_PATCH 3
+#define SKL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(SKL)
+MODULE_FIRMWARE(SKL_GUC_FIRMWARE_PATH);
+
+#define BXT_GUC_FW_PREFIX bxt
+#define BXT_GUC_FW_MAJOR 32
+#define BXT_GUC_FW_MINOR 0
+#define BXT_GUC_FW_PATCH 3
+#define BXT_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(BXT)
+MODULE_FIRMWARE(BXT_GUC_FIRMWARE_PATH);
+
+#define KBL_GUC_FW_PREFIX kbl
+#define KBL_GUC_FW_MAJOR 32
+#define KBL_GUC_FW_MINOR 0
+#define KBL_GUC_FW_PATCH 3
+#define KBL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(KBL)
+MODULE_FIRMWARE(KBL_GUC_FIRMWARE_PATH);
static void guc_fw_select(struct intel_uc_fw *guc_fw)
{
struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct drm_i915_private *i915 = guc_to_i915(guc);
GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC);
- if (!HAS_GUC(dev_priv))
+ if (!HAS_GUC(i915))
return;
if (i915_modparams.guc_firmware_path) {
guc_fw->path = i915_modparams.guc_firmware_path;
guc_fw->major_ver_wanted = 0;
guc_fw->minor_ver_wanted = 0;
- } else if (IS_SKYLAKE(dev_priv)) {
- guc_fw->path = I915_SKL_GUC_UCODE;
- guc_fw->major_ver_wanted = SKL_FW_MAJOR;
- guc_fw->minor_ver_wanted = SKL_FW_MINOR;
- } else if (IS_BROXTON(dev_priv)) {
- guc_fw->path = I915_BXT_GUC_UCODE;
- guc_fw->major_ver_wanted = BXT_FW_MAJOR;
- guc_fw->minor_ver_wanted = BXT_FW_MINOR;
- } else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
- guc_fw->path = I915_KBL_GUC_UCODE;
- guc_fw->major_ver_wanted = KBL_FW_MAJOR;
- guc_fw->minor_ver_wanted = KBL_FW_MINOR;
+ } else if (IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) {
+ guc_fw->path = KBL_GUC_FIRMWARE_PATH;
+ guc_fw->major_ver_wanted = KBL_GUC_FW_MAJOR;
+ guc_fw->minor_ver_wanted = KBL_GUC_FW_MINOR;
+ } else if (IS_BROXTON(i915)) {
+ guc_fw->path = BXT_GUC_FIRMWARE_PATH;
+ guc_fw->major_ver_wanted = BXT_GUC_FW_MAJOR;
+ guc_fw->minor_ver_wanted = BXT_GUC_FW_MINOR;
+ } else if (IS_SKYLAKE(i915)) {
+ guc_fw->path = SKL_GUC_FIRMWARE_PATH;
+ guc_fw->major_ver_wanted = SKL_GUC_FW_MAJOR;
+ guc_fw->minor_ver_wanted = SKL_GUC_FW_MINOR;
}
}
--
2.19.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH v4 04/22] drm/i915/guc: Update GuC firmware CSS header
2019-05-23 23:30 [PATCH v4 00/22] GuC 32.0.3 Michal Wajdeczko
` (2 preceding siblings ...)
2019-05-23 23:30 ` [PATCH v4 03/22] drm/i915/guc: Update GuC firmware versions and names Michal Wajdeczko
@ 2019-05-23 23:30 ` Michal Wajdeczko
2019-05-23 23:30 ` [PATCH v4 05/22] drm/i915/guc: Update GuC boot parameters Michal Wajdeczko
` (20 subsequent siblings)
24 siblings, 0 replies; 34+ messages in thread
From: Michal Wajdeczko @ 2019-05-23 23:30 UTC (permalink / raw)
To: intel-gfx
There are few minor changes in the CSS header related to the version
numbering in new GuC firmwares. Update our definition and start using
common tools for extracting bitfields.
v2: drop deprecated prod_preprod_fw field, replace unions with bit defs
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: John Spotswood <john.a.spotswood@intel.com>
Cc: Jeff Mcgee <jeff.mcgee@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/intel_guc_fwif.h | 50 +++++++++------------------
drivers/gpu/drm/i915/intel_uc_fw.c | 20 +++++------
2 files changed, 26 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index b2f5148f4f17..4528e098d3a5 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -168,11 +168,7 @@
* in fw. So driver will load a truncated firmware in this case.
*
* HuC firmware layout is same as GuC firmware.
- *
- * HuC firmware css header is different. However, the only difference is where
- * the version information is saved. The uc_css_header is unified to support
- * both. Driver should get HuC version from uc_css_header.huc_sw_version, while
- * uc_css_header.guc_sw_version for GuC.
+ * Only HuC version information is saved in a different way.
*/
struct uc_css_header {
@@ -183,41 +179,27 @@ struct uc_css_header {
u32 header_version;
u32 module_id;
u32 module_vendor;
- union {
- struct {
- u8 day;
- u8 month;
- u16 year;
- };
- u32 date;
- };
+ u32 date;
+#define CSS_DATE_DAY (0xFF << 0)
+#define CSS_DATE_MONTH (0xFF << 8)
+#define CSS_DATE_YEAR (0xFFFF << 16)
u32 size_dw; /* uCode plus header_size_dw */
u32 key_size_dw;
u32 modulus_size_dw;
u32 exponent_size_dw;
- union {
- struct {
- u8 hour;
- u8 min;
- u16 sec;
- };
- u32 time;
- };
-
+ u32 time;
+#define CSS_TIME_HOUR (0xFF << 0)
+#define CSS_DATE_MIN (0xFF << 8)
+#define CSS_DATE_SEC (0xFFFF << 16)
char username[8];
char buildnumber[12];
- union {
- struct {
- u32 branch_client_version;
- u32 sw_version;
- } guc;
- struct {
- u32 sw_version;
- u32 reserved;
- } huc;
- };
- u32 prod_preprod_fw;
- u32 reserved[12];
+ u32 sw_version;
+#define CSS_SW_VERSION_GUC_MAJOR (0xFF << 16)
+#define CSS_SW_VERSION_GUC_MINOR (0xFF << 8)
+#define CSS_SW_VERSION_GUC_PATCH (0xFF << 0)
+#define CSS_SW_VERSION_HUC_MAJOR (0xFFFF << 16)
+#define CSS_SW_VERSION_HUC_MINOR (0xFFFF << 0)
+ u32 reserved[14];
u32 header_info;
} __packed;
diff --git a/drivers/gpu/drm/i915/intel_uc_fw.c b/drivers/gpu/drm/i915/intel_uc_fw.c
index b9cb6fea9332..eca741a857a5 100644
--- a/drivers/gpu/drm/i915/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/intel_uc_fw.c
@@ -22,6 +22,7 @@
*
*/
+#include <linux/bitfield.h>
#include <linux/firmware.h>
#include <drm/drm_print.h>
@@ -119,21 +120,20 @@ void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
goto fail;
}
- /*
- * The GuC firmware image has the version number embedded at a
- * well-known offset within the firmware blob; note that major / minor
- * version are TWO bytes each (i.e. u16), although all pointers and
- * offsets are defined in terms of bytes (u8).
- */
+ /* Get version numbers from the CSS header */
switch (uc_fw->type) {
case INTEL_UC_FW_TYPE_GUC:
- uc_fw->major_ver_found = css->guc.sw_version >> 16;
- uc_fw->minor_ver_found = css->guc.sw_version & 0xFFFF;
+ uc_fw->major_ver_found = FIELD_GET(CSS_SW_VERSION_GUC_MAJOR,
+ css->sw_version);
+ uc_fw->minor_ver_found = FIELD_GET(CSS_SW_VERSION_GUC_MINOR,
+ css->sw_version);
break;
case INTEL_UC_FW_TYPE_HUC:
- uc_fw->major_ver_found = css->huc.sw_version >> 16;
- uc_fw->minor_ver_found = css->huc.sw_version & 0xFFFF;
+ uc_fw->major_ver_found = FIELD_GET(CSS_SW_VERSION_HUC_MAJOR,
+ css->sw_version);
+ uc_fw->minor_ver_found = FIELD_GET(CSS_SW_VERSION_HUC_MINOR,
+ css->sw_version);
break;
default:
--
2.19.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH v4 05/22] drm/i915/guc: Update GuC boot parameters
2019-05-23 23:30 [PATCH v4 00/22] GuC 32.0.3 Michal Wajdeczko
` (3 preceding siblings ...)
2019-05-23 23:30 ` [PATCH v4 04/22] drm/i915/guc: Update GuC firmware CSS header Michal Wajdeczko
@ 2019-05-23 23:30 ` Michal Wajdeczko
2019-05-23 23:30 ` [PATCH v4 06/22] drm/i915/guc: Update suspend/resume protocol Michal Wajdeczko
` (19 subsequent siblings)
24 siblings, 0 replies; 34+ messages in thread
From: Michal Wajdeczko @ 2019-05-23 23:30 UTC (permalink / raw)
To: intel-gfx
New GuC firmwares require updated boot parameters.
v2: rebased
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: John Spotswood <john.a.spotswood@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/intel_guc.c | 38 +++++++++-----------------
drivers/gpu/drm/i915/intel_guc_fwif.h | 39 +++++++--------------------
2 files changed, 23 insertions(+), 54 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index c4ac29309fcc..29513e3ce118 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -250,14 +250,7 @@ void intel_guc_fini(struct intel_guc *guc)
static u32 guc_ctl_debug_flags(struct intel_guc *guc)
{
u32 level = intel_guc_log_get_level(&guc->log);
- u32 flags;
- u32 ads;
-
- ads = intel_guc_ggtt_offset(guc, guc->ads_vma) >> PAGE_SHIFT;
- flags = ads << GUC_ADS_ADDR_SHIFT | GUC_ADS_ENABLED;
-
- if (!GUC_LOG_LEVEL_IS_ENABLED(level))
- flags |= GUC_LOG_DEFAULT_DISABLED;
+ u32 flags = 0;
if (!GUC_LOG_LEVEL_IS_VERBOSE(level))
flags |= GUC_LOG_DISABLED;
@@ -272,11 +265,7 @@ static u32 guc_ctl_feature_flags(struct intel_guc *guc)
{
u32 flags = 0;
- flags |= GUC_CTL_VCS2_ENABLED;
-
- if (USES_GUC_SUBMISSION(guc_to_i915(guc)))
- flags |= GUC_CTL_KERNEL_SUBMISSIONS;
- else
+ if (!USES_GUC_SUBMISSION(guc_to_i915(guc)))
flags |= GUC_CTL_DISABLE_SCHEDULER;
return flags;
@@ -340,6 +329,14 @@ static u32 guc_ctl_log_params_flags(struct intel_guc *guc)
return flags;
}
+static u32 guc_ctl_ads_flags(struct intel_guc *guc)
+{
+ u32 ads = intel_guc_ggtt_offset(guc, guc->ads_vma) >> PAGE_SHIFT;
+ u32 flags = ads << GUC_ADS_ADDR_SHIFT;
+
+ return flags;
+}
+
/*
* Initialise the GuC parameter block before starting the firmware
* transfer. These parameters are read by the firmware on startup
@@ -353,20 +350,11 @@ void intel_guc_init_params(struct intel_guc *guc)
memset(params, 0, sizeof(params));
- /*
- * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
- * second. This ARAR is calculated by:
- * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10
- */
- params[GUC_CTL_ARAT_HIGH] = 0;
- params[GUC_CTL_ARAT_LOW] = 100000000;
-
- params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER;
-
+ params[GUC_CTL_CTXINFO] = guc_ctl_ctxinfo_flags(guc);
+ params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc);
params[GUC_CTL_FEATURE] = guc_ctl_feature_flags(guc);
- params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc);
params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc);
- params[GUC_CTL_CTXINFO] = guc_ctl_ctxinfo_flags(guc);
+ params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc);
for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
DRM_DEBUG_DRIVER("param[%2d] = %#x\n", i, params[i]);
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 4528e098d3a5..e18a8c0312ef 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -73,44 +73,28 @@
#define GUC_STAGE_DESC_ATTR_PCH BIT(6)
#define GUC_STAGE_DESC_ATTR_TERMINATED BIT(7)
-/* The guc control data is 10 DWORDs */
+/* New GuC control data */
#define GUC_CTL_CTXINFO 0
#define GUC_CTL_CTXNUM_IN16_SHIFT 0
#define GUC_CTL_BASE_ADDR_SHIFT 12
-#define GUC_CTL_ARAT_HIGH 1
-#define GUC_CTL_ARAT_LOW 2
-
-#define GUC_CTL_DEVICE_INFO 3
-
-#define GUC_CTL_LOG_PARAMS 4
+#define GUC_CTL_LOG_PARAMS 1
#define GUC_LOG_VALID (1 << 0)
#define GUC_LOG_NOTIFY_ON_HALF_FULL (1 << 1)
#define GUC_LOG_ALLOC_IN_MEGABYTE (1 << 3)
#define GUC_LOG_CRASH_SHIFT 4
-#define GUC_LOG_CRASH_MASK (0x1 << GUC_LOG_CRASH_SHIFT)
+#define GUC_LOG_CRASH_MASK (0x3 << GUC_LOG_CRASH_SHIFT)
#define GUC_LOG_DPC_SHIFT 6
#define GUC_LOG_DPC_MASK (0x7 << GUC_LOG_DPC_SHIFT)
#define GUC_LOG_ISR_SHIFT 9
#define GUC_LOG_ISR_MASK (0x7 << GUC_LOG_ISR_SHIFT)
#define GUC_LOG_BUF_ADDR_SHIFT 12
-#define GUC_CTL_PAGE_FAULT_CONTROL 5
-
-#define GUC_CTL_WA 6
-#define GUC_CTL_WA_UK_BY_DRIVER (1 << 3)
-
-#define GUC_CTL_FEATURE 7
-#define GUC_CTL_VCS2_ENABLED (1 << 0)
-#define GUC_CTL_KERNEL_SUBMISSIONS (1 << 1)
-#define GUC_CTL_FEATURE2 (1 << 2)
-#define GUC_CTL_POWER_GATING (1 << 3)
-#define GUC_CTL_DISABLE_SCHEDULER (1 << 4)
-#define GUC_CTL_PREEMPTION_LOG (1 << 5)
-#define GUC_CTL_ENABLE_SLPC (1 << 7)
-#define GUC_CTL_RESET_ON_PREMPT_FAILURE (1 << 8)
+#define GUC_CTL_WA 2
+#define GUC_CTL_FEATURE 3
+#define GUC_CTL_DISABLE_SCHEDULER (1 << 14)
-#define GUC_CTL_DEBUG 8
+#define GUC_CTL_DEBUG 4
#define GUC_LOG_VERBOSITY_SHIFT 0
#define GUC_LOG_VERBOSITY_LOW (0 << GUC_LOG_VERBOSITY_SHIFT)
#define GUC_LOG_VERBOSITY_MED (1 << GUC_LOG_VERBOSITY_SHIFT)
@@ -123,13 +107,10 @@
#define GUC_LOG_DESTINATION_MASK (3 << 4)
#define GUC_LOG_DISABLED (1 << 6)
#define GUC_PROFILE_ENABLED (1 << 7)
-#define GUC_WQ_TRACK_ENABLED (1 << 8)
-#define GUC_ADS_ENABLED (1 << 9)
-#define GUC_LOG_DEFAULT_DISABLED (1 << 10)
-#define GUC_ADS_ADDR_SHIFT 11
-#define GUC_ADS_ADDR_MASK 0xfffff800
-#define GUC_CTL_RSRVD 9
+#define GUC_CTL_ADS 5
+#define GUC_ADS_ADDR_SHIFT 1
+#define GUC_ADS_ADDR_MASK (0xFFFFF << GUC_ADS_ADDR_SHIFT)
#define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2) /* [1..14] */
--
2.19.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH v4 06/22] drm/i915/guc: Update suspend/resume protocol
2019-05-23 23:30 [PATCH v4 00/22] GuC 32.0.3 Michal Wajdeczko
` (4 preceding siblings ...)
2019-05-23 23:30 ` [PATCH v4 05/22] drm/i915/guc: Update GuC boot parameters Michal Wajdeczko
@ 2019-05-23 23:30 ` Michal Wajdeczko
2019-05-23 23:30 ` [PATCH v4 07/22] drm/i915/guc: Update GuC sample-forcewake command Michal Wajdeczko
` (18 subsequent siblings)
24 siblings, 0 replies; 34+ messages in thread
From: Michal Wajdeczko @ 2019-05-23 23:30 UTC (permalink / raw)
To: intel-gfx
New GuC firmwares use updated sleep status definitions.
The polling on scratch register 14 is also now required only on suspend
and there is no need to provide the shared page.
v2: include changes for polling and shared page
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: John Spotswood <john.a.spotswood@intel.com>
Reviewed-by: John Spotswood <john.a.spotswood@intel.com>
---
drivers/gpu/drm/i915/intel_guc.c | 50 +++++++++++----------------
drivers/gpu/drm/i915/intel_guc_fwif.h | 6 ++--
2 files changed, 24 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 29513e3ce118..60e6463a3aac 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -538,25 +538,33 @@ int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset)
return intel_guc_send(guc, action, ARRAY_SIZE(action));
}
-/*
- * The ENTER/EXIT_S_STATE actions queue the save/restore operation in GuC FW and
- * then return, so waiting on the H2G is not enough to guarantee GuC is done.
- * When all the processing is done, GuC writes INTEL_GUC_SLEEP_STATE_SUCCESS to
- * scratch register 14, so we can poll on that. Note that GuC does not ensure
- * that the value in the register is different from
- * INTEL_GUC_SLEEP_STATE_SUCCESS while the action is in progress so we need to
- * take care of that ourselves as well.
+/**
+ * intel_guc_suspend() - notify GuC entering suspend state
+ * @guc: the guc
*/
-static int guc_sleep_state_action(struct intel_guc *guc,
- const u32 *action, u32 len)
+int intel_guc_suspend(struct intel_guc *guc)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
int ret;
u32 status;
+ u32 action[] = {
+ INTEL_GUC_ACTION_ENTER_S_STATE,
+ GUC_POWER_D1, /* any value greater than GUC_POWER_D0 */
+ };
+
+ /*
+ * The ENTER_S_STATE action queues the save/restore operation in GuC FW
+ * and then returns, so waiting on the H2G is not enough to guarantee
+ * GuC is done. When all the processing is done, GuC writes
+ * INTEL_GUC_SLEEP_STATE_SUCCESS to scratch register 14, so we can poll
+ * on that. Note that GuC does not ensure that the value in the register
+ * is different from INTEL_GUC_SLEEP_STATE_SUCCESS while the action is
+ * in progress so we need to take care of that ourselves as well.
+ */
I915_WRITE(SOFT_SCRATCH(14), INTEL_GUC_SLEEP_STATE_INVALID_MASK);
- ret = intel_guc_send(guc, action, len);
+ ret = intel_guc_send(guc, action, ARRAY_SIZE(action));
if (ret)
return ret;
@@ -576,21 +584,6 @@ static int guc_sleep_state_action(struct intel_guc *guc,
return 0;
}
-/**
- * intel_guc_suspend() - notify GuC entering suspend state
- * @guc: the guc
- */
-int intel_guc_suspend(struct intel_guc *guc)
-{
- u32 data[] = {
- INTEL_GUC_ACTION_ENTER_S_STATE,
- GUC_POWER_D1, /* any value greater than GUC_POWER_D0 */
- intel_guc_ggtt_offset(guc, guc->shared_data)
- };
-
- return guc_sleep_state_action(guc, data, ARRAY_SIZE(data));
-}
-
/**
* intel_guc_reset_engine() - ask GuC to reset an engine
* @guc: intel_guc structure
@@ -620,13 +613,12 @@ int intel_guc_reset_engine(struct intel_guc *guc,
*/
int intel_guc_resume(struct intel_guc *guc)
{
- u32 data[] = {
+ u32 action[] = {
INTEL_GUC_ACTION_EXIT_S_STATE,
GUC_POWER_D0,
- intel_guc_ggtt_offset(guc, guc->shared_data)
};
- return guc_sleep_state_action(guc, data, ARRAY_SIZE(data));
+ return intel_guc_send(guc, action, ARRAY_SIZE(action));
}
/**
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index e18a8c0312ef..592c78c1ecc8 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -637,9 +637,9 @@ enum intel_guc_report_status {
};
enum intel_guc_sleep_state_status {
- INTEL_GUC_SLEEP_STATE_SUCCESS = 0x0,
- INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x1,
- INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x2
+ INTEL_GUC_SLEEP_STATE_SUCCESS = 0x1,
+ INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x2,
+ INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x3
#define INTEL_GUC_SLEEP_STATE_INVALID_MASK 0x80000000
};
--
2.19.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH v4 07/22] drm/i915/guc: Update GuC sample-forcewake command
2019-05-23 23:30 [PATCH v4 00/22] GuC 32.0.3 Michal Wajdeczko
` (5 preceding siblings ...)
2019-05-23 23:30 ` [PATCH v4 06/22] drm/i915/guc: Update suspend/resume protocol Michal Wajdeczko
@ 2019-05-23 23:30 ` Michal Wajdeczko
2019-05-23 23:30 ` [PATCH v4 08/22] drm/i915/guc: Update GuC ADS object definition Michal Wajdeczko
` (17 subsequent siblings)
24 siblings, 0 replies; 34+ messages in thread
From: Michal Wajdeczko @ 2019-05-23 23:30 UTC (permalink / raw)
To: intel-gfx
New GuC firmwares use different action code value for this command.
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: John Spotswood <john.a.spotswood@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: John Spotswood <john.a.spotswood@intel.com>
---
drivers/gpu/drm/i915/intel_guc_fwif.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 592c78c1ecc8..9b4436acba17 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -609,7 +609,6 @@ enum intel_guc_action {
INTEL_GUC_ACTION_DEFAULT = 0x0,
INTEL_GUC_ACTION_REQUEST_PREEMPTION = 0x2,
INTEL_GUC_ACTION_REQUEST_ENGINE_RESET = 0x3,
- INTEL_GUC_ACTION_SAMPLE_FORCEWAKE = 0x6,
INTEL_GUC_ACTION_ALLOCATE_DOORBELL = 0x10,
INTEL_GUC_ACTION_DEALLOCATE_DOORBELL = 0x20,
INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE = 0x30,
@@ -617,6 +616,7 @@ enum intel_guc_action {
INTEL_GUC_ACTION_ENTER_S_STATE = 0x501,
INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
+ INTEL_GUC_ACTION_SAMPLE_FORCEWAKE = 0x3005,
INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505,
INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER = 0x4506,
--
2.19.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH v4 08/22] drm/i915/guc: Update GuC ADS object definition
2019-05-23 23:30 [PATCH v4 00/22] GuC 32.0.3 Michal Wajdeczko
` (6 preceding siblings ...)
2019-05-23 23:30 ` [PATCH v4 07/22] drm/i915/guc: Update GuC sample-forcewake command Michal Wajdeczko
@ 2019-05-23 23:30 ` Michal Wajdeczko
2019-05-23 23:30 ` [PATCH v4 09/22] drm/i915/guc: Reset GuC ADS during sanitize Michal Wajdeczko
` (16 subsequent siblings)
24 siblings, 0 replies; 34+ messages in thread
From: Michal Wajdeczko @ 2019-05-23 23:30 UTC (permalink / raw)
To: intel-gfx
New GuC firmwares use updated definitions for the Additional Data
Structures (ADS).
v2: add note about Gen9 definition mismatch (Daniele)
rename __intel_engine_context_size (Daniele)
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Fernando Pacheco <fernando.pacheco@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: John Spotswood <john.a.spotswood@intel.com>
Cc: Tomasz Lis <tomasz.lis@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine.h | 2 +
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 9 +--
drivers/gpu/drm/i915/intel_guc_ads.c | 95 ++++++++++++++---------
drivers/gpu/drm/i915/intel_guc_fwif.h | 94 +++++++++++++---------
4 files changed, 122 insertions(+), 78 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
index 9359b3a7ad9c..1c0db151f0b1 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -526,6 +526,8 @@ ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine);
struct i915_request *
intel_engine_find_active_request(struct intel_engine_cs *engine);
+u32 intel_engine_context_size(struct drm_i915_private *i915, u8 class);
+
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
static inline bool inject_preempt_hang(struct intel_engine_execlists *execlists)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 2590f5904b67..1c83ea9adac0 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -156,7 +156,7 @@ static const struct engine_info intel_engines[] = {
};
/**
- * ___intel_engine_context_size() - return the size of the context for an engine
+ * intel_engine_context_size() - return the size of the context for an engine
* @dev_priv: i915 device private
* @class: engine class
*
@@ -169,8 +169,7 @@ static const struct engine_info intel_engines[] = {
* in LRC mode, but does not include the "shared data page" used with
* GuC submission. The caller should account for this if using the GuC.
*/
-static u32
-__intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class)
+u32 intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class)
{
u32 cxt_size;
@@ -327,8 +326,8 @@ intel_engine_setup(struct drm_i915_private *dev_priv,
engine->uabi_class = intel_engine_classes[info->class].uabi_class;
- engine->context_size = __intel_engine_context_size(dev_priv,
- engine->class);
+ engine->context_size = intel_engine_context_size(dev_priv,
+ engine->class);
if (WARN_ON(engine->context_size > BIT(20)))
engine->context_size = 0;
if (engine->context_size)
diff --git a/drivers/gpu/drm/i915/intel_guc_ads.c b/drivers/gpu/drm/i915/intel_guc_ads.c
index bec62f34b15a..1aa1ec0ff4a1 100644
--- a/drivers/gpu/drm/i915/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/intel_guc_ads.c
@@ -51,7 +51,7 @@ static void guc_policies_init(struct guc_policies *policies)
policies->max_num_work_items = POLICY_MAX_NUM_WI;
for (p = 0; p < GUC_CLIENT_PRIORITY_NUM; p++) {
- for (i = GUC_RENDER_ENGINE; i < GUC_MAX_ENGINES_NUM; i++) {
+ for (i = 0; i < GUC_MAX_ENGINE_CLASSES; i++) {
policy = &policies->policy[p][i];
guc_policy_init(policy);
@@ -61,6 +61,11 @@ static void guc_policies_init(struct guc_policies *policies)
policies->is_valid = 1;
}
+static void guc_ct_pool_entries_init(struct guc_ct_pool_entry *pool, u32 num)
+{
+ memset(pool, 0, num * sizeof(*pool));
+}
+
/*
* The first 80 dwords of the register state context, containing the
* execlists and ppgtt registers.
@@ -75,20 +80,21 @@ static void guc_policies_init(struct guc_policies *policies)
int intel_guc_ads_create(struct intel_guc *guc)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
- struct i915_vma *vma, *kernel_ctx_vma;
- struct page *page;
+ struct i915_vma *vma;
/* The ads obj includes the struct itself and buffers passed to GuC */
struct {
struct guc_ads ads;
struct guc_policies policies;
struct guc_mmio_reg_state reg_state;
+ struct guc_gt_system_info system_info;
+ struct guc_clients_info clients_info;
+ struct guc_ct_pool_entry ct_pool[GUC_CT_POOL_SIZE];
u8 reg_state_buffer[GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE];
} __packed *blob;
- struct intel_engine_cs *engine;
- enum intel_engine_id id;
- const u32 skipped_offset = LRC_HEADER_PAGES * PAGE_SIZE;
const u32 skipped_size = LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE;
u32 base;
+ u8 engine_class;
+ int ret;
GEM_BUG_ON(guc->ads_vma);
@@ -98,51 +104,68 @@ int intel_guc_ads_create(struct intel_guc *guc)
guc->ads_vma = vma;
- page = i915_vma_first_page(vma);
- blob = kmap(page);
+ blob = i915_gem_object_pin_map(guc->ads_vma->obj, I915_MAP_WB);
+ if (IS_ERR(blob)) {
+ ret = PTR_ERR(blob);
+ goto err_vma;
+ }
/* GuC scheduling policies */
guc_policies_init(&blob->policies);
- /* MMIO reg state */
- for_each_engine(engine, dev_priv, id) {
- blob->reg_state.white_list[engine->guc_id].mmio_start =
- engine->mmio_base + GUC_MMIO_WHITE_LIST_START;
-
- /* Nothing to be saved or restored for now. */
- blob->reg_state.white_list[engine->guc_id].count = 0;
- }
-
/*
- * The GuC requires a "Golden Context" when it reinitialises
- * engines after a reset. Here we use the Render ring default
- * context, which must already exist and be pinned in the GGTT,
- * so its address won't change after we've told the GuC where
- * to find it. Note that we have to skip our header (1 page),
- * because our GuC shared data is there.
+ * GuC expects a per-engine-class context image and size
+ * (minus hwsp and ring context). The context image will be
+ * used to reinitialize engines after a reset. It must exist
+ * and be pinned in the GGTT, so that the address won't change after
+ * we have told GuC where to find it. The context size will be used
+ * to validate that the LRC base + size fall within allowed GGTT.
*/
- kernel_ctx_vma = dev_priv->engine[RCS0]->kernel_context->state;
- blob->ads.golden_context_lrca =
- intel_guc_ggtt_offset(guc, kernel_ctx_vma) + skipped_offset;
+ for (engine_class = 0; engine_class <= MAX_ENGINE_CLASS; ++engine_class) {
+ if (engine_class == OTHER_CLASS)
+ continue;
+ /*
+ * TODO: Set context pointer to default state to allow
+ * GuC to re-init guilty contexts after internal reset.
+ */
+ blob->ads.golden_context_lrca[engine_class] = 0;
+ blob->ads.eng_state_size[engine_class] =
+ intel_engine_context_size(dev_priv, engine_class) -
+ skipped_size;
+ }
- /*
- * The GuC expects us to exclude the portion of the context image that
- * it skips from the size it is to read. It starts reading from after
- * the execlist context (so skipping the first page [PPHWSP] and 80
- * dwords). Weird guc is weird.
- */
- for_each_engine(engine, dev_priv, id)
- blob->ads.eng_state_size[engine->guc_id] =
- engine->context_size - skipped_size;
+ /* System info */
+ blob->system_info.slice_enabled = hweight8(RUNTIME_INFO(dev_priv)->sseu.slice_mask);
+ blob->system_info.rcs_enabled = 1;
+ blob->system_info.bcs_enabled = 1;
+
+ blob->system_info.vdbox_enable_mask = VDBOX_MASK(dev_priv);
+ blob->system_info.vebox_enable_mask = VEBOX_MASK(dev_priv);
+ blob->system_info.vdbox_sfc_support_mask = RUNTIME_INFO(dev_priv)->vdbox_sfc_access;
base = intel_guc_ggtt_offset(guc, vma);
+
+ /* Clients info */
+ guc_ct_pool_entries_init(blob->ct_pool, ARRAY_SIZE(blob->ct_pool));
+
+ blob->clients_info.clients_num = 1;
+ blob->clients_info.ct_pool_addr = base + ptr_offset(blob, ct_pool);
+ blob->clients_info.ct_pool_count = ARRAY_SIZE(blob->ct_pool);
+
+ /* ADS */
blob->ads.scheduler_policies = base + ptr_offset(blob, policies);
blob->ads.reg_state_buffer = base + ptr_offset(blob, reg_state_buffer);
blob->ads.reg_state_addr = base + ptr_offset(blob, reg_state);
+ blob->ads.gt_system_info = base + ptr_offset(blob, system_info);
+ blob->ads.clients_info = base + ptr_offset(blob, clients_info);
- kunmap(page);
+ i915_gem_object_unpin_map(guc->ads_vma->obj);
return 0;
+
+err_vma:
+ i915_vma_unpin_and_release(&guc->ads_vma, 0);
+ return ret;
}
void intel_guc_ads_destroy(struct intel_guc *guc)
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 9b4436acba17..fa745a58d38d 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -39,6 +39,14 @@
#define GUC_VIDEO_ENGINE2 4
#define GUC_MAX_ENGINES_NUM (GUC_VIDEO_ENGINE2 + 1)
+/*
+ * XXX: Beware that Gen9 firmware 32.x uses wrong definition for
+ * GUC_MAX_INSTANCES_PER_CLASS (1) but this is harmless for us now
+ * as we are not enabling GuC submission mode where this will be used
+ */
+#define GUC_MAX_ENGINE_CLASSES 5
+#define GUC_MAX_INSTANCES_PER_CLASS 4
+
#define GUC_DOORBELL_INVALID 256
#define GUC_DB_SIZE (PAGE_SIZE)
@@ -386,23 +394,19 @@ struct guc_ct_buffer_desc {
struct guc_policy {
/* Time for one workload to execute. (in micro seconds) */
u32 execution_quantum;
- u32 reserved1;
-
/* Time to wait for a preemption request to completed before issuing a
* reset. (in micro seconds). */
u32 preemption_time;
-
/* How much time to allow to run after the first fault is observed.
* Then preempt afterwards. (in micro seconds) */
u32 fault_time;
-
u32 policy_flags;
- u32 reserved[2];
+ u32 reserved[8];
} __packed;
struct guc_policies {
- struct guc_policy policy[GUC_CLIENT_PRIORITY_NUM][GUC_MAX_ENGINES_NUM];
-
+ struct guc_policy policy[GUC_CLIENT_PRIORITY_NUM][GUC_MAX_ENGINE_CLASSES];
+ u32 submission_queue_depth[GUC_MAX_ENGINE_CLASSES];
/* In micro seconds. How much time to allow before DPC processing is
* called back via interrupt (to prevent DPC queue drain starving).
* Typically 1000s of micro seconds (example only, not granularity). */
@@ -415,57 +419,73 @@ struct guc_policies {
* idle. */
u32 max_num_work_items;
- u32 reserved[19];
+ u32 reserved[4];
} __packed;
/* GuC MMIO reg state struct */
-#define GUC_REGSET_FLAGS_NONE 0x0
-#define GUC_REGSET_POWERCYCLE 0x1
-#define GUC_REGSET_MASKED 0x2
-#define GUC_REGSET_ENGINERESET 0x4
-#define GUC_REGSET_SAVE_DEFAULT_VALUE 0x8
-#define GUC_REGSET_SAVE_CURRENT_VALUE 0x10
-#define GUC_REGSET_MAX_REGISTERS 25
-#define GUC_MMIO_WHITE_LIST_START 0x24d0
-#define GUC_MMIO_WHITE_LIST_MAX 12
+#define GUC_REGSET_MAX_REGISTERS 64
#define GUC_S3_SAVE_SPACE_PAGES 10
-struct guc_mmio_regset {
- struct __packed {
- u32 offset;
- u32 value;
- u32 flags;
- } registers[GUC_REGSET_MAX_REGISTERS];
+struct guc_mmio_reg {
+ u32 offset;
+ u32 value;
+ u32 flags;
+#define GUC_REGSET_MASKED (1 << 0)
+} __packed;
+struct guc_mmio_regset {
+ struct guc_mmio_reg registers[GUC_REGSET_MAX_REGISTERS];
u32 values_valid;
u32 number_of_registers;
} __packed;
-/* MMIO registers that are set as non privileged */
-struct mmio_white_list {
- u32 mmio_start;
- u32 offsets[GUC_MMIO_WHITE_LIST_MAX];
- u32 count;
+/* GuC register sets */
+struct guc_mmio_reg_state {
+ struct guc_mmio_regset engine_reg[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
+ u32 reserved[98];
} __packed;
-struct guc_mmio_reg_state {
- struct guc_mmio_regset global_reg;
- struct guc_mmio_regset engine_reg[GUC_MAX_ENGINES_NUM];
- struct mmio_white_list white_list[GUC_MAX_ENGINES_NUM];
+/* HW info */
+struct guc_gt_system_info {
+ u32 slice_enabled;
+ u32 rcs_enabled;
+ u32 reserved0;
+ u32 bcs_enabled;
+ u32 vdbox_enable_mask;
+ u32 vdbox_sfc_support_mask;
+ u32 vebox_enable_mask;
+ u32 reserved[9];
} __packed;
-/* GuC Additional Data Struct */
+/* Clients info */
+struct guc_ct_pool_entry {
+ struct guc_ct_buffer_desc desc;
+ u32 reserved[7];
+} __packed;
+#define GUC_CT_POOL_SIZE 2
+
+struct guc_clients_info {
+ u32 clients_num;
+ u32 reserved0[13];
+ u32 ct_pool_addr;
+ u32 ct_pool_count;
+ u32 reserved[4];
+} __packed;
+
+/* GuC Additional Data Struct */
struct guc_ads {
u32 reg_state_addr;
u32 reg_state_buffer;
- u32 golden_context_lrca;
u32 scheduler_policies;
- u32 reserved0[3];
- u32 eng_state_size[GUC_MAX_ENGINES_NUM];
- u32 reserved2[4];
+ u32 gt_system_info;
+ u32 clients_info;
+ u32 control_data;
+ u32 golden_context_lrca[GUC_MAX_ENGINE_CLASSES];
+ u32 eng_state_size[GUC_MAX_ENGINE_CLASSES];
+ u32 reserved[16];
} __packed;
/* GuC logging structures */
--
2.19.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH v4 09/22] drm/i915/guc: Reset GuC ADS during sanitize
2019-05-23 23:30 [PATCH v4 00/22] GuC 32.0.3 Michal Wajdeczko
` (7 preceding siblings ...)
2019-05-23 23:30 ` [PATCH v4 08/22] drm/i915/guc: Update GuC ADS object definition Michal Wajdeczko
@ 2019-05-23 23:30 ` Michal Wajdeczko
2019-05-23 23:30 ` [PATCH v4 10/22] drm/i915/guc: Always ask GuC to update power domain states Michal Wajdeczko
` (15 subsequent siblings)
24 siblings, 0 replies; 34+ messages in thread
From: Michal Wajdeczko @ 2019-05-23 23:30 UTC (permalink / raw)
To: intel-gfx
GuC stores some data in there, which might be stale after a reset.
Reinitialize whole ADS in case any part of it was corrupted during
previous GuC run.
v2: s/reinit/init, update functions descriptions (Tomek/Michal)
v3: reset ADS right before fw upload
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: MichaĹ Winiarski <michal.winiarski@intel.com>
Cc: Tomasz Lis <tomasz.lis@intel.com>
Reviewed-by: Tomasz Lis <tomasz.lis@intel.com> #v2
Reviewed-by: MichaĹ Winiarski <michal.winiarski@intel.com> #v2
---
drivers/gpu/drm/i915/intel_guc_ads.c | 90 ++++++++++++++++++----------
drivers/gpu/drm/i915/intel_guc_ads.h | 1 +
drivers/gpu/drm/i915/intel_uc.c | 4 +-
3 files changed, 63 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_ads.c b/drivers/gpu/drm/i915/intel_guc_ads.c
index 1aa1ec0ff4a1..ecb69fc94218 100644
--- a/drivers/gpu/drm/i915/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/intel_guc_ads.c
@@ -72,43 +72,28 @@ static void guc_ct_pool_entries_init(struct guc_ct_pool_entry *pool, u32 num)
*/
#define LR_HW_CONTEXT_SIZE (80 * sizeof(u32))
-/**
- * intel_guc_ads_create() - creates GuC ADS
- * @guc: intel_guc struct
- *
- */
-int intel_guc_ads_create(struct intel_guc *guc)
+/* The ads obj includes the struct itself and buffers passed to GuC */
+struct __guc_ads_blob {
+ struct guc_ads ads;
+ struct guc_policies policies;
+ struct guc_mmio_reg_state reg_state;
+ struct guc_gt_system_info system_info;
+ struct guc_clients_info clients_info;
+ struct guc_ct_pool_entry ct_pool[GUC_CT_POOL_SIZE];
+ u8 reg_state_buffer[GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE];
+} __packed;
+
+static int __guc_ads_init(struct intel_guc *guc)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
- struct i915_vma *vma;
- /* The ads obj includes the struct itself and buffers passed to GuC */
- struct {
- struct guc_ads ads;
- struct guc_policies policies;
- struct guc_mmio_reg_state reg_state;
- struct guc_gt_system_info system_info;
- struct guc_clients_info clients_info;
- struct guc_ct_pool_entry ct_pool[GUC_CT_POOL_SIZE];
- u8 reg_state_buffer[GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE];
- } __packed *blob;
+ struct __guc_ads_blob *blob;
const u32 skipped_size = LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE;
u32 base;
u8 engine_class;
- int ret;
-
- GEM_BUG_ON(guc->ads_vma);
-
- vma = intel_guc_allocate_vma(guc, PAGE_ALIGN(sizeof(*blob)));
- if (IS_ERR(vma))
- return PTR_ERR(vma);
-
- guc->ads_vma = vma;
blob = i915_gem_object_pin_map(guc->ads_vma->obj, I915_MAP_WB);
- if (IS_ERR(blob)) {
- ret = PTR_ERR(blob);
- goto err_vma;
- }
+ if (IS_ERR(blob))
+ return PTR_ERR(blob);
/* GuC scheduling policies */
guc_policies_init(&blob->policies);
@@ -143,7 +128,7 @@ int intel_guc_ads_create(struct intel_guc *guc)
blob->system_info.vebox_enable_mask = VEBOX_MASK(dev_priv);
blob->system_info.vdbox_sfc_support_mask = RUNTIME_INFO(dev_priv)->vdbox_sfc_access;
- base = intel_guc_ggtt_offset(guc, vma);
+ base = intel_guc_ggtt_offset(guc, guc->ads_vma);
/* Clients info */
guc_ct_pool_entries_init(blob->ct_pool, ARRAY_SIZE(blob->ct_pool));
@@ -162,6 +147,34 @@ int intel_guc_ads_create(struct intel_guc *guc)
i915_gem_object_unpin_map(guc->ads_vma->obj);
return 0;
+}
+
+/**
+ * intel_guc_ads_create() - allocates and initializes GuC ADS.
+ * @guc: intel_guc struct
+ *
+ * GuC needs memory block (Additional Data Struct), where it will store
+ * some data. Allocate and initialize such memory block for GuC use.
+ */
+int intel_guc_ads_create(struct intel_guc *guc)
+{
+ const u32 size = PAGE_ALIGN(sizeof(struct __guc_ads_blob));
+ struct i915_vma *vma;
+ int ret;
+
+ GEM_BUG_ON(guc->ads_vma);
+
+ vma = intel_guc_allocate_vma(guc, size);
+ if (IS_ERR(vma))
+ return PTR_ERR(vma);
+
+ guc->ads_vma = vma;
+
+ ret = __guc_ads_init(guc);
+ if (ret)
+ goto err_vma;
+
+ return 0;
err_vma:
i915_vma_unpin_and_release(&guc->ads_vma, 0);
@@ -172,3 +185,18 @@ void intel_guc_ads_destroy(struct intel_guc *guc)
{
i915_vma_unpin_and_release(&guc->ads_vma, 0);
}
+
+/**
+ * intel_guc_ads_reset() - prepares GuC Additional Data Struct for reuse
+ * @guc: intel_guc struct
+ *
+ * GuC stores some data in ADS, which might be stale after a reset.
+ * Reinitialize whole ADS in case any part of it was corrupted during
+ * previous GuC run.
+ */
+void intel_guc_ads_reset(struct intel_guc *guc)
+{
+ if (!guc->ads_vma)
+ return;
+ __guc_ads_init(guc);
+}
diff --git a/drivers/gpu/drm/i915/intel_guc_ads.h b/drivers/gpu/drm/i915/intel_guc_ads.h
index c4735742c564..7f40f9cd5fb9 100644
--- a/drivers/gpu/drm/i915/intel_guc_ads.h
+++ b/drivers/gpu/drm/i915/intel_guc_ads.h
@@ -29,5 +29,6 @@ struct intel_guc;
int intel_guc_ads_create(struct intel_guc *guc);
void intel_guc_ads_destroy(struct intel_guc *guc);
+void intel_guc_ads_reset(struct intel_guc *guc);
#endif
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index f66105d756df..2de9d5360f02 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -24,8 +24,9 @@
#include "gt/intel_reset.h"
#include "intel_uc.h"
-#include "intel_guc_submission.h"
#include "intel_guc.h"
+#include "intel_guc_ads.h"
+#include "intel_guc_submission.h"
#include "i915_drv.h"
static void guc_free_load_err_log(struct intel_guc *guc);
@@ -415,6 +416,7 @@ int intel_uc_init_hw(struct drm_i915_private *i915)
goto err_out;
}
+ intel_guc_ads_reset(guc);
intel_guc_init_params(guc);
ret = intel_guc_fw_upload(guc);
if (ret == 0)
--
2.19.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH v4 10/22] drm/i915/guc: Always ask GuC to update power domain states
2019-05-23 23:30 [PATCH v4 00/22] GuC 32.0.3 Michal Wajdeczko
` (8 preceding siblings ...)
2019-05-23 23:30 ` [PATCH v4 09/22] drm/i915/guc: Reset GuC ADS during sanitize Michal Wajdeczko
@ 2019-05-23 23:30 ` Michal Wajdeczko
2019-05-23 23:30 ` [PATCH v4 11/22] drm/i915/guc: Define GuC firmware version for Geminilake Michal Wajdeczko
` (14 subsequent siblings)
24 siblings, 0 replies; 34+ messages in thread
From: Michal Wajdeczko @ 2019-05-23 23:30 UTC (permalink / raw)
To: intel-gfx
With newer GuC firmware it is always ok to ask GuC to update power
domain states. Make it an unconditional initialization step.
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: John Spotswood <john.a.spotswood@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: John Spotswood <john.a.spotswood@intel.com>
---
drivers/gpu/drm/i915/intel_guc_submission.c | 4 ----
drivers/gpu/drm/i915/intel_uc.c | 8 ++++----
2 files changed, 4 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c
index 987ff586d7f9..ffdab22db2b0 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -1426,10 +1426,6 @@ int intel_guc_submission_enable(struct intel_guc *guc)
GEM_BUG_ON(!guc->execbuf_client);
- err = intel_guc_sample_forcewake(guc);
- if (err)
- return err;
-
err = guc_clients_enable(guc);
if (err)
return err;
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 2de9d5360f02..2df530de07af 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -440,14 +440,14 @@ int intel_uc_init_hw(struct drm_i915_private *i915)
goto err_communication;
}
+ ret = intel_guc_sample_forcewake(guc);
+ if (ret)
+ goto err_communication;
+
if (USES_GUC_SUBMISSION(i915)) {
ret = intel_guc_submission_enable(guc);
if (ret)
goto err_communication;
- } else if (INTEL_GEN(i915) < 11) {
- ret = intel_guc_sample_forcewake(guc);
- if (ret)
- goto err_communication;
}
dev_info(i915->drm.dev, "GuC firmware version %u.%u\n",
--
2.19.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH v4 11/22] drm/i915/guc: Define GuC firmware version for Geminilake
2019-05-23 23:30 [PATCH v4 00/22] GuC 32.0.3 Michal Wajdeczko
` (9 preceding siblings ...)
2019-05-23 23:30 ` [PATCH v4 10/22] drm/i915/guc: Always ask GuC to update power domain states Michal Wajdeczko
@ 2019-05-23 23:30 ` Michal Wajdeczko
2019-05-24 17:36 ` Srivatsa, Anusha
2019-05-23 23:30 ` [PATCH v4 12/22] drm/i915/huc: Define HuC " Michal Wajdeczko
` (13 subsequent siblings)
24 siblings, 1 reply; 34+ messages in thread
From: Michal Wajdeczko @ 2019-05-23 23:30 UTC (permalink / raw)
To: intel-gfx
Define GuC firmware version for Geminilake.
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/intel_guc_fw.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c b/drivers/gpu/drm/i915/intel_guc_fw.c
index c740bf3731de..c1e9bb4e04fd 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -58,6 +58,13 @@ MODULE_FIRMWARE(BXT_GUC_FIRMWARE_PATH);
#define KBL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(KBL)
MODULE_FIRMWARE(KBL_GUC_FIRMWARE_PATH);
+#define GLK_GUC_FW_PREFIX glk
+#define GLK_GUC_FW_MAJOR 32
+#define GLK_GUC_FW_MINOR 0
+#define GLK_GUC_FW_PATCH 3
+#define GLK_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(GLK)
+MODULE_FIRMWARE(GLK_GUC_FIRMWARE_PATH);
+
static void guc_fw_select(struct intel_uc_fw *guc_fw)
{
struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
@@ -72,6 +79,10 @@ static void guc_fw_select(struct intel_uc_fw *guc_fw)
guc_fw->path = i915_modparams.guc_firmware_path;
guc_fw->major_ver_wanted = 0;
guc_fw->minor_ver_wanted = 0;
+ } else if (IS_GEMINILAKE(i915)) {
+ guc_fw->path = GLK_GUC_FIRMWARE_PATH;
+ guc_fw->major_ver_wanted = GLK_GUC_FW_MAJOR;
+ guc_fw->minor_ver_wanted = GLK_GUC_FW_MINOR;
} else if (IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) {
guc_fw->path = KBL_GUC_FIRMWARE_PATH;
guc_fw->major_ver_wanted = KBL_GUC_FW_MAJOR;
--
2.19.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread* Re: [PATCH v4 11/22] drm/i915/guc: Define GuC firmware version for Geminilake
2019-05-23 23:30 ` [PATCH v4 11/22] drm/i915/guc: Define GuC firmware version for Geminilake Michal Wajdeczko
@ 2019-05-24 17:36 ` Srivatsa, Anusha
0 siblings, 0 replies; 34+ messages in thread
From: Srivatsa, Anusha @ 2019-05-24 17:36 UTC (permalink / raw)
To: Wajdeczko, Michal, intel-gfx
>-----Original Message-----
>From: Wajdeczko, Michal
>Sent: Thursday, May 23, 2019 4:31 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Wajdeczko, Michal <Michal.Wajdeczko@intel.com>; Ceraolo Spurio, Daniele
><daniele.ceraolospurio@intel.com>; Srivatsa, Anusha
><anusha.srivatsa@intel.com>
>Subject: [PATCH v4 11/22] drm/i915/guc: Define GuC firmware version for
>Geminilake
>
>Define GuC firmware version for Geminilake.
Thanks for this patch Michal.
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
>Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
>---
> drivers/gpu/drm/i915/intel_guc_fw.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c
>b/drivers/gpu/drm/i915/intel_guc_fw.c
>index c740bf3731de..c1e9bb4e04fd 100644
>--- a/drivers/gpu/drm/i915/intel_guc_fw.c
>+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
>@@ -58,6 +58,13 @@ MODULE_FIRMWARE(BXT_GUC_FIRMWARE_PATH);
> #define KBL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(KBL)
>MODULE_FIRMWARE(KBL_GUC_FIRMWARE_PATH);
>
>+#define GLK_GUC_FW_PREFIX glk
>+#define GLK_GUC_FW_MAJOR 32
>+#define GLK_GUC_FW_MINOR 0
>+#define GLK_GUC_FW_PATCH 3
>+#define GLK_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(GLK)
>+MODULE_FIRMWARE(GLK_GUC_FIRMWARE_PATH);
>+
> static void guc_fw_select(struct intel_uc_fw *guc_fw) {
> struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw); @@ -
>72,6 +79,10 @@ static void guc_fw_select(struct intel_uc_fw *guc_fw)
> guc_fw->path = i915_modparams.guc_firmware_path;
> guc_fw->major_ver_wanted = 0;
> guc_fw->minor_ver_wanted = 0;
>+ } else if (IS_GEMINILAKE(i915)) {
>+ guc_fw->path = GLK_GUC_FIRMWARE_PATH;
>+ guc_fw->major_ver_wanted = GLK_GUC_FW_MAJOR;
>+ guc_fw->minor_ver_wanted = GLK_GUC_FW_MINOR;
> } else if (IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) {
> guc_fw->path = KBL_GUC_FIRMWARE_PATH;
> guc_fw->major_ver_wanted = KBL_GUC_FW_MAJOR;
>--
>2.19.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH v4 12/22] drm/i915/huc: Define HuC firmware version for Geminilake
2019-05-23 23:30 [PATCH v4 00/22] GuC 32.0.3 Michal Wajdeczko
` (10 preceding siblings ...)
2019-05-23 23:30 ` [PATCH v4 11/22] drm/i915/guc: Define GuC firmware version for Geminilake Michal Wajdeczko
@ 2019-05-23 23:30 ` Michal Wajdeczko
2019-05-24 17:39 ` Srivatsa, Anusha
2019-05-23 23:30 ` [PATCH v4 13/22] drm/i915/guc: New GuC interrupt register for Gen11 Michal Wajdeczko
` (12 subsequent siblings)
24 siblings, 1 reply; 34+ messages in thread
From: Michal Wajdeczko @ 2019-05-23 23:30 UTC (permalink / raw)
To: intel-gfx
Define HuC firmware version for Geminilake.
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Tony Ye <tony.ye@intel.com>
---
drivers/gpu/drm/i915/intel_huc_fw.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_huc_fw.c b/drivers/gpu/drm/i915/intel_huc_fw.c
index 44c559526072..8bac6a051c18 100644
--- a/drivers/gpu/drm/i915/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/intel_huc_fw.c
@@ -34,6 +34,10 @@
#define KBL_HUC_FW_MINOR 00
#define KBL_BLD_NUM 1810
+#define GLK_HUC_FW_MAJOR 03
+#define GLK_HUC_FW_MINOR 01
+#define GLK_BLD_NUM 2893
+
#define HUC_FW_PATH(platform, major, minor, bld_num) \
"i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
__stringify(minor) "_" __stringify(bld_num) ".bin"
@@ -50,6 +54,10 @@ MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
KBL_HUC_FW_MINOR, KBL_BLD_NUM)
MODULE_FIRMWARE(I915_KBL_HUC_UCODE);
+#define I915_GLK_HUC_UCODE HUC_FW_PATH(glk, GLK_HUC_FW_MAJOR, \
+ GLK_HUC_FW_MINOR, GLK_BLD_NUM)
+MODULE_FIRMWARE(I915_GLK_HUC_UCODE);
+
static void huc_fw_select(struct intel_uc_fw *huc_fw)
{
struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
@@ -76,6 +84,10 @@ static void huc_fw_select(struct intel_uc_fw *huc_fw)
huc_fw->path = I915_KBL_HUC_UCODE;
huc_fw->major_ver_wanted = KBL_HUC_FW_MAJOR;
huc_fw->minor_ver_wanted = KBL_HUC_FW_MINOR;
+ } else if (IS_GEMINILAKE(dev_priv)) {
+ huc_fw->path = I915_GLK_HUC_UCODE;
+ huc_fw->major_ver_wanted = GLK_HUC_FW_MAJOR;
+ huc_fw->minor_ver_wanted = GLK_HUC_FW_MINOR;
}
}
--
2.19.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread* Re: [PATCH v4 12/22] drm/i915/huc: Define HuC firmware version for Geminilake
2019-05-23 23:30 ` [PATCH v4 12/22] drm/i915/huc: Define HuC " Michal Wajdeczko
@ 2019-05-24 17:39 ` Srivatsa, Anusha
0 siblings, 0 replies; 34+ messages in thread
From: Srivatsa, Anusha @ 2019-05-24 17:39 UTC (permalink / raw)
To: Wajdeczko, Michal, intel-gfx
>-----Original Message-----
>From: Wajdeczko, Michal
>Sent: Thursday, May 23, 2019 4:31 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Wajdeczko, Michal <Michal.Wajdeczko@intel.com>; Ceraolo Spurio, Daniele
><daniele.ceraolospurio@intel.com>; Joonas Lahtinen
><joonas.lahtinen@linux.intel.com>; Srivatsa, Anusha
><anusha.srivatsa@intel.com>; Ye, Tony <tony.ye@intel.com>
>Subject: [PATCH v4 12/22] drm/i915/huc: Define HuC firmware version for
>Geminilake
>
>Define HuC firmware version for Geminilake.
>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
>Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
>Cc: Tony Ye <tony.ye@intel.com>
>---
> drivers/gpu/drm/i915/intel_huc_fw.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/intel_huc_fw.c
>b/drivers/gpu/drm/i915/intel_huc_fw.c
>index 44c559526072..8bac6a051c18 100644
>--- a/drivers/gpu/drm/i915/intel_huc_fw.c
>+++ b/drivers/gpu/drm/i915/intel_huc_fw.c
>@@ -34,6 +34,10 @@
> #define KBL_HUC_FW_MINOR 00
> #define KBL_BLD_NUM 1810
>
>+#define GLK_HUC_FW_MAJOR 03
>+#define GLK_HUC_FW_MINOR 01
>+#define GLK_BLD_NUM 2893
>+
> #define HUC_FW_PATH(platform, major, minor, bld_num) \
> "i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
> __stringify(minor) "_" __stringify(bld_num) ".bin"
>@@ -50,6 +54,10 @@ MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
> KBL_HUC_FW_MINOR, KBL_BLD_NUM)
> MODULE_FIRMWARE(I915_KBL_HUC_UCODE);
>
>+#define I915_GLK_HUC_UCODE HUC_FW_PATH(glk, GLK_HUC_FW_MAJOR, \
>+ GLK_HUC_FW_MINOR, GLK_BLD_NUM)
>+MODULE_FIRMWARE(I915_GLK_HUC_UCODE);
>+
> static void huc_fw_select(struct intel_uc_fw *huc_fw) {
> struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw); @@ -
>76,6 +84,10 @@ static void huc_fw_select(struct intel_uc_fw *huc_fw)
> huc_fw->path = I915_KBL_HUC_UCODE;
> huc_fw->major_ver_wanted = KBL_HUC_FW_MAJOR;
> huc_fw->minor_ver_wanted = KBL_HUC_FW_MINOR;
>+ } else if (IS_GEMINILAKE(dev_priv)) {
>+ huc_fw->path = I915_GLK_HUC_UCODE;
>+ huc_fw->major_ver_wanted = GLK_HUC_FW_MAJOR;
>+ huc_fw->minor_ver_wanted = GLK_HUC_FW_MINOR;
> }
> }
>
>--
>2.19.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH v4 13/22] drm/i915/guc: New GuC interrupt register for Gen11
2019-05-23 23:30 [PATCH v4 00/22] GuC 32.0.3 Michal Wajdeczko
` (11 preceding siblings ...)
2019-05-23 23:30 ` [PATCH v4 12/22] drm/i915/huc: Define HuC " Michal Wajdeczko
@ 2019-05-23 23:30 ` Michal Wajdeczko
2019-05-23 23:30 ` [PATCH v4 14/22] drm/i915/guc: New GuC scratch registers " Michal Wajdeczko
` (11 subsequent siblings)
24 siblings, 0 replies; 34+ messages in thread
From: Michal Wajdeczko @ 2019-05-23 23:30 UTC (permalink / raw)
To: intel-gfx
Gen11 defines new more flexible Host-to-GuC interrupt register.
Now the host can write any 32-bit payload to trigger an interrupt
and GuC can additionally read this payload from the register.
Current GuC firmware ignores the payload so we just write 0.
Bspec: 21043
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/intel_guc.c | 14 +++++++++++++-
drivers/gpu/drm/i915/intel_guc_reg.h | 1 +
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 60e6463a3aac..888a1e999c8b 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -34,6 +34,13 @@ static void gen8_guc_raise_irq(struct intel_guc *guc)
I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
}
+static void gen11_guc_raise_irq(struct intel_guc *guc)
+{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
+ I915_WRITE(GEN11_GUC_HOST_INTERRUPT, 0);
+}
+
static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)
{
GEM_BUG_ON(!guc->send_regs.base);
@@ -63,6 +70,8 @@ void intel_guc_init_send_regs(struct intel_guc *guc)
void intel_guc_init_early(struct intel_guc *guc)
{
+ struct drm_i915_private *i915 = guc_to_i915(guc);
+
intel_guc_fw_init_early(guc);
intel_guc_ct_init_early(&guc->ct);
intel_guc_log_init_early(&guc->log);
@@ -71,7 +80,10 @@ void intel_guc_init_early(struct intel_guc *guc)
spin_lock_init(&guc->irq_lock);
guc->send = intel_guc_send_nop;
guc->handler = intel_guc_to_host_event_handler_nop;
- guc->notify = gen8_guc_raise_irq;
+ if (INTEL_GEN(i915) >= 11)
+ guc->notify = gen11_guc_raise_irq;
+ else
+ guc->notify = gen8_guc_raise_irq;
}
static int guc_init_wq(struct intel_guc *guc)
diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h b/drivers/gpu/drm/i915/intel_guc_reg.h
index 57e7ad522c2f..aec02eddbaed 100644
--- a/drivers/gpu/drm/i915/intel_guc_reg.h
+++ b/drivers/gpu/drm/i915/intel_guc_reg.h
@@ -103,6 +103,7 @@
#define GUC_SEND_INTERRUPT _MMIO(0xc4c8)
#define GUC_SEND_TRIGGER (1<<0)
+#define GEN11_GUC_HOST_INTERRUPT _MMIO(0x1901f0)
#define GUC_NUM_DOORBELLS 256
--
2.19.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH v4 14/22] drm/i915/guc: New GuC scratch registers for Gen11
2019-05-23 23:30 [PATCH v4 00/22] GuC 32.0.3 Michal Wajdeczko
` (12 preceding siblings ...)
2019-05-23 23:30 ` [PATCH v4 13/22] drm/i915/guc: New GuC interrupt register for Gen11 Michal Wajdeczko
@ 2019-05-23 23:30 ` Michal Wajdeczko
2019-05-23 23:30 ` [PATCH v4 15/22] drm/i915/huc: New HuC status register " Michal Wajdeczko
` (10 subsequent siblings)
24 siblings, 0 replies; 34+ messages in thread
From: Michal Wajdeczko @ 2019-05-23 23:30 UTC (permalink / raw)
To: intel-gfx
Gen11 adds new set of scratch registers that can be used for MMIO
based Host-to-Guc communication. Due to limited number of these
registers it is expected that host will use them only for command
transport buffers (CTB) communication setup if one is available.
Bspec: 21044
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/intel_guc.c | 12 +++++++++---
drivers/gpu/drm/i915/intel_guc_reg.h | 3 +++
2 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 888a1e999c8b..538868a10168 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -56,9 +56,15 @@ void intel_guc_init_send_regs(struct intel_guc *guc)
enum forcewake_domains fw_domains = 0;
unsigned int i;
- guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
- guc->send_regs.count = GUC_MAX_MMIO_MSG_LEN;
- BUILD_BUG_ON(GUC_MAX_MMIO_MSG_LEN > SOFT_SCRATCH_COUNT);
+ if (HAS_GUC_CT(dev_priv) && INTEL_GEN(dev_priv) >= 11) {
+ guc->send_regs.base =
+ i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0));
+ guc->send_regs.count = GEN11_SOFT_SCRATCH_COUNT;
+ } else {
+ guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
+ guc->send_regs.count = GUC_MAX_MMIO_MSG_LEN;
+ BUILD_BUG_ON(GUC_MAX_MMIO_MSG_LEN > SOFT_SCRATCH_COUNT);
+ }
for (i = 0; i < guc->send_regs.count; i++) {
fw_domains |= intel_uncore_forcewake_for_reg(&dev_priv->uncore,
diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h b/drivers/gpu/drm/i915/intel_guc_reg.h
index aec02eddbaed..d26de5193568 100644
--- a/drivers/gpu/drm/i915/intel_guc_reg.h
+++ b/drivers/gpu/drm/i915/intel_guc_reg.h
@@ -51,6 +51,9 @@
#define SOFT_SCRATCH(n) _MMIO(0xc180 + (n) * 4)
#define SOFT_SCRATCH_COUNT 16
+#define GEN11_SOFT_SCRATCH(n) _MMIO(0x190240 + (n) * 4)
+#define GEN11_SOFT_SCRATCH_COUNT 4
+
#define UOS_RSA_SCRATCH(i) _MMIO(0xc200 + (i) * 4)
#define UOS_RSA_SCRATCH_COUNT 64
--
2.19.2
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH v4 15/22] drm/i915/huc: New HuC status register for Gen11
2019-05-23 23:30 [PATCH v4 00/22] GuC 32.0.3 Michal Wajdeczko
` (13 preceding siblings ...)
2019-05-23 23:30 ` [PATCH v4 14/22] drm/i915/guc: New GuC scratch registers " Michal Wajdeczko
@ 2019-05-23 23:30 ` Michal Wajdeczko
2019-05-23 23:30 ` [PATCH v4 16/22] drm/i915/guc: Create vfuncs for the GuC interrupts control functions Michal Wajdeczko
` (9 subsequent siblings)
24 siblings, 0 replies; 34+ messages in thread
From: Michal Wajdeczko @ 2019-05-23 23:30 UTC (permalink / raw)
To: intel-gfx
Gen11 defines new register for checking HuC authentication status.
Look into the right register and bit.
v2: use reg/mask/value instead of dedicated functions (Daniele)
BSpec: 19686
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Tony Ye <tony.ye@intel.com>
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Cc: John Spotswood <john.a.spotswood@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/intel_guc_reg.h | 3 +++
drivers/gpu/drm/i915/intel_huc.c | 26 +++++++++++++++++++-------
drivers/gpu/drm/i915/intel_huc.h | 7 +++++++
3 files changed, 29 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h b/drivers/gpu/drm/i915/intel_guc_reg.h
index d26de5193568..7eba65795b58 100644
--- a/drivers/gpu/drm/i915/intel_guc_reg.h
+++ b/drivers/gpu/drm/i915/intel_guc_reg.h
@@ -79,6 +79,9 @@
#define HUC_STATUS2 _MMIO(0xD3B0)
#define HUC_FW_VERIFIED (1<<7)
+#define GEN11_HUC_KERNEL_LOAD_INFO _MMIO(0xC1DC)
+#define HUC_LOAD_SUCCESSFUL (1 << 0)
+
#define GUC_WOPCM_SIZE _MMIO(0xc050)
#define GUC_WOPCM_SIZE_LOCKED (1<<0)
#define GUC_WOPCM_SIZE_SHIFT 12
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index 1ff1fb015e58..8572a0588efc 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -29,7 +29,19 @@
void intel_huc_init_early(struct intel_huc *huc)
{
+ struct drm_i915_private *i915 = huc_to_i915(huc);
+
intel_huc_fw_init_early(huc);
+
+ if (INTEL_GEN(i915) >= 11) {
+ huc->status.reg = GEN11_HUC_KERNEL_LOAD_INFO;
+ huc->status.mask = HUC_LOAD_SUCCESSFUL;
+ huc->status.value = HUC_LOAD_SUCCESSFUL;
+ } else {
+ huc->status.reg = HUC_STATUS2;
+ huc->status.mask = HUC_FW_VERIFIED;
+ huc->status.value = HUC_FW_VERIFIED;
+ }
}
int intel_huc_init_misc(struct intel_huc *huc)
@@ -110,7 +122,6 @@ int intel_huc_auth(struct intel_huc *huc)
{
struct drm_i915_private *i915 = huc_to_i915(huc);
struct intel_guc *guc = &i915->guc;
- u32 status;
int ret;
if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
@@ -125,12 +136,12 @@ int intel_huc_auth(struct intel_huc *huc)
/* Check authentication status, it should be done by now */
ret = __intel_wait_for_register(&i915->uncore,
- HUC_STATUS2,
- HUC_FW_VERIFIED,
- HUC_FW_VERIFIED,
- 2, 50, &status);
+ huc->status.reg,
+ huc->status.mask,
+ huc->status.value,
+ 2, 50, NULL);
if (ret) {
- DRM_ERROR("HuC: Firmware not verified %#x\n", status);
+ DRM_ERROR("HuC: Firmware not verified %d\n", ret);
goto fail;
}
@@ -164,7 +175,8 @@ int intel_huc_check_status(struct intel_huc *huc)
return -ENODEV;
with_intel_runtime_pm(dev_priv, wakeref)
- status = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
+ status = (I915_READ(huc->status.reg) & huc->status.mask) ==
+ huc->status.value;
return status;
}
diff --git a/drivers/gpu/drm/i915/intel_huc.h b/drivers/gpu/drm/i915/intel_huc.h
index a0c21ae02a99..2a6c94e79f17 100644
--- a/drivers/gpu/drm/i915/intel_huc.h
+++ b/drivers/gpu/drm/i915/intel_huc.h
@@ -25,6 +25,7 @@
#ifndef _INTEL_HUC_H_
#define _INTEL_HUC_H_
+#include "i915_reg.h"
#include "intel_uc_fw.h"
#include "intel_huc_fw.h"
@@ -35,6 +36,12 @@ struct intel_huc {
/* HuC-specific additions */
struct i915_vma *rsa_data;
void *rsa_data_vaddr;
+
+ struct {
+ i915_reg_t reg;
+ u32 mask;
+ u32 value;
+ } status;
};
void intel_huc_init_early(struct intel_huc *huc);
--
2.19.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH v4 16/22] drm/i915/guc: Create vfuncs for the GuC interrupts control functions
2019-05-23 23:30 [PATCH v4 00/22] GuC 32.0.3 Michal Wajdeczko
` (14 preceding siblings ...)
2019-05-23 23:30 ` [PATCH v4 15/22] drm/i915/huc: New HuC status register " Michal Wajdeczko
@ 2019-05-23 23:30 ` Michal Wajdeczko
2019-05-23 23:30 ` [PATCH v4 17/22] drm/i915/guc: Correctly handle GuC interrupts on Gen11 Michal Wajdeczko
` (8 subsequent siblings)
24 siblings, 0 replies; 34+ messages in thread
From: Michal Wajdeczko @ 2019-05-23 23:30 UTC (permalink / raw)
To: intel-gfx; +Cc: Oscar Mateo
From: Oscar Mateo <oscar.mateo@intel.com>
Controlling and handling of the GuC interrupts is Gen specific.
Create virtual functions to avoid redundant runtime Gen checks.
Gen-specific versions of these functions will follow.
v2: move vfuncs to struct guc (Daniele)
v3: rebased
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 6 +++---
drivers/gpu/drm/i915/intel_guc.c | 8 ++++++--
drivers/gpu/drm/i915/intel_guc.h | 8 +++++++-
drivers/gpu/drm/i915/intel_uc.c | 21 ++++++++++++++++++---
4 files changed, 34 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 233211fde0ea..607709a8c229 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -600,10 +600,10 @@ void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
assert_rpm_wakelock_held(dev_priv);
spin_lock_irq(&dev_priv->irq_lock);
- if (!dev_priv->guc.interrupts_enabled) {
+ if (!dev_priv->guc.interrupts.enabled) {
WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
dev_priv->pm_guc_events);
- dev_priv->guc.interrupts_enabled = true;
+ dev_priv->guc.interrupts.enabled = true;
gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events);
}
spin_unlock_irq(&dev_priv->irq_lock);
@@ -614,7 +614,7 @@ void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
assert_rpm_wakelock_held(dev_priv);
spin_lock_irq(&dev_priv->irq_lock);
- dev_priv->guc.interrupts_enabled = false;
+ dev_priv->guc.interrupts.enabled = false;
gen6_disable_pm_irq(dev_priv, dev_priv->pm_guc_events);
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 538868a10168..28642bf977bd 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -86,10 +86,14 @@ void intel_guc_init_early(struct intel_guc *guc)
spin_lock_init(&guc->irq_lock);
guc->send = intel_guc_send_nop;
guc->handler = intel_guc_to_host_event_handler_nop;
- if (INTEL_GEN(i915) >= 11)
+ if (INTEL_GEN(i915) >= 11) {
guc->notify = gen11_guc_raise_irq;
- else
+ } else {
guc->notify = gen8_guc_raise_irq;
+ guc->interrupts.reset = gen9_reset_guc_interrupts;
+ guc->interrupts.enable = gen9_enable_guc_interrupts;
+ guc->interrupts.disable = gen9_disable_guc_interrupts;
+ }
}
static int guc_init_wq(struct intel_guc *guc)
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index d4b015ab8a36..cbfed7a77c8b 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -55,9 +55,15 @@ struct intel_guc {
/* intel_guc_recv interrupt related state */
spinlock_t irq_lock;
- bool interrupts_enabled;
unsigned int msg_enabled_mask;
+ struct {
+ bool enabled;
+ void (*reset)(struct drm_i915_private *i915);
+ void (*enable)(struct drm_i915_private *i915);
+ void (*disable)(struct drm_i915_private *i915);
+ } interrupts;
+
struct i915_vma *ads_vma;
struct i915_vma *stage_desc_pool;
void *stage_desc_pool_vaddr;
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 2df530de07af..59f28e88c6de 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -218,11 +218,26 @@ static void guc_free_load_err_log(struct intel_guc *guc)
i915_gem_object_put(guc->load_err_log);
}
+static void guc_reset_interrupts(struct intel_guc *guc)
+{
+ guc->interrupts.reset(guc_to_i915(guc));
+}
+
+static void guc_enable_interrupts(struct intel_guc *guc)
+{
+ guc->interrupts.enable(guc_to_i915(guc));
+}
+
+static void guc_disable_interrupts(struct intel_guc *guc)
+{
+ guc->interrupts.disable(guc_to_i915(guc));
+}
+
static int guc_enable_communication(struct intel_guc *guc)
{
struct drm_i915_private *i915 = guc_to_i915(guc);
- gen9_enable_guc_interrupts(i915);
+ guc_enable_interrupts(guc);
if (HAS_GUC_CT(i915))
return intel_guc_ct_enable(&guc->ct);
@@ -250,7 +265,7 @@ static void guc_disable_communication(struct intel_guc *guc)
if (HAS_GUC_CT(i915))
intel_guc_ct_disable(&guc->ct);
- gen9_disable_guc_interrupts(i915);
+ guc_disable_interrupts(guc);
guc->send = intel_guc_send_nop;
guc->handler = intel_guc_to_host_event_handler_nop;
@@ -392,7 +407,7 @@ int intel_uc_init_hw(struct drm_i915_private *i915)
GEM_BUG_ON(!HAS_GUC(i915));
- gen9_reset_guc_interrupts(i915);
+ guc_reset_interrupts(guc);
/* WaEnableuKernelHeaderValidFix:skl */
/* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */
--
2.19.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH v4 17/22] drm/i915/guc: Correctly handle GuC interrupts on Gen11
2019-05-23 23:30 [PATCH v4 00/22] GuC 32.0.3 Michal Wajdeczko
` (15 preceding siblings ...)
2019-05-23 23:30 ` [PATCH v4 16/22] drm/i915/guc: Create vfuncs for the GuC interrupts control functions Michal Wajdeczko
@ 2019-05-23 23:30 ` Michal Wajdeczko
2019-05-27 14:30 ` Michał Winiarski
2019-05-23 23:30 ` [PATCH v4 18/22] drm/i915/guc: Update GuC CTB response definition Michal Wajdeczko
` (7 subsequent siblings)
24 siblings, 1 reply; 34+ messages in thread
From: Michal Wajdeczko @ 2019-05-23 23:30 UTC (permalink / raw)
To: intel-gfx; +Cc: Oscar Mateo
From: Oscar Mateo <oscar.mateo@intel.com>
The GuC interrupts now get their own interrupt vector (instead of
sharing a register with the PM interrupts) so handle appropriately.
v2: (Chris)
v3: rebased (Michal)
Bspec: 19820
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 6 ++-
drivers/gpu/drm/i915/i915_irq.c | 58 +++++++++++++++++++++++++++-
drivers/gpu/drm/i915/i915_irq.h | 3 ++
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_guc.c | 3 ++
drivers/gpu/drm/i915/intel_guc_reg.h | 18 +++++++++
6 files changed, 86 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 311e19154672..6bd7a9347071 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1570,7 +1570,11 @@ struct drm_i915_private {
u32 pm_imr;
u32 pm_ier;
u32 pm_rps_events;
- u32 pm_guc_events;
+ union {
+ /* RPS and GuC share a register pre-Gen11 */
+ u32 pm_guc_events;
+ u32 guc_events;
+ };
u32 pipestat_irq_mask[I915_MAX_PIPES];
struct i915_hotplug hotplug;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 607709a8c229..52345772f84c 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -624,6 +624,41 @@ void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
gen9_reset_guc_interrupts(dev_priv);
}
+void gen11_reset_guc_interrupts(struct drm_i915_private *i915)
+{
+ spin_lock_irq(&i915->irq_lock);
+ gen11_reset_one_iir(i915, 0, GEN11_GUC);
+ spin_unlock_irq(&i915->irq_lock);
+}
+
+void gen11_enable_guc_interrupts(struct drm_i915_private *dev_priv)
+{
+ spin_lock_irq(&dev_priv->irq_lock);
+ if (!dev_priv->guc.interrupts.enabled) {
+ u32 guc_events = dev_priv->guc_events << 16;
+
+ WARN_ON_ONCE(gen11_reset_one_iir(dev_priv, 0, GEN11_GUC));
+ I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, guc_events);
+ I915_WRITE(GEN11_GUC_SG_INTR_MASK, ~guc_events);
+ dev_priv->guc.interrupts.enabled = true;
+ }
+ spin_unlock_irq(&dev_priv->irq_lock);
+}
+
+void gen11_disable_guc_interrupts(struct drm_i915_private *dev_priv)
+{
+ spin_lock_irq(&dev_priv->irq_lock);
+ dev_priv->guc.interrupts.enabled = false;
+
+ I915_WRITE(GEN11_GUC_SG_INTR_MASK, ~0);
+ I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, 0);
+
+ spin_unlock_irq(&dev_priv->irq_lock);
+ synchronize_irq(dev_priv->drm.irq);
+
+ gen11_reset_guc_interrupts(dev_priv);
+}
+
/**
* bdw_update_port_irq - update DE port interrupt
* @dev_priv: driver private
@@ -1893,6 +1928,12 @@ static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir)
intel_guc_to_host_event_handler(&dev_priv->guc);
}
+static void gen11_guc_irq_handler(struct drm_i915_private *i915, u16 iir)
+{
+ if (iir & GEN11_GUC_INTR_GUC2HOST)
+ intel_guc_to_host_event_handler(&i915->guc);
+}
+
static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
{
enum pipe pipe;
@@ -3015,6 +3056,9 @@ static void
gen11_other_irq_handler(struct drm_i915_private * const i915,
const u8 instance, const u16 iir)
{
+ if (instance == OTHER_GUC_INSTANCE)
+ return gen11_guc_irq_handler(i915, iir);
+
if (instance == OTHER_GTPM_INSTANCE)
return gen11_rps_irq_handler(i915, iir);
@@ -3545,6 +3589,8 @@ static void gen11_gt_irq_reset(struct drm_i915_private *dev_priv)
I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
+ I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, 0);
+ I915_WRITE(GEN11_GUC_SG_INTR_MASK, ~0);
}
static void gen11_irq_reset(struct drm_device *dev)
@@ -4200,6 +4246,10 @@ static void gen11_gt_irq_postinstall(struct drm_i915_private *dev_priv)
dev_priv->pm_imr = ~dev_priv->pm_ier;
I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
+
+ /* Same thing for GuC interrupts */
+ I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, 0);
+ I915_WRITE(GEN11_GUC_SG_INTR_MASK, ~0);
}
static void icp_irq_postinstall(struct drm_device *dev)
@@ -4707,8 +4757,12 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
for (i = 0; i < MAX_L3_SLICES; ++i)
dev_priv->l3_parity.remap_info[i] = NULL;
- if (HAS_GUC_SCHED(dev_priv))
- dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT;
+ if (HAS_GUC_SCHED(dev_priv)) {
+ if (INTEL_GEN(dev_priv) < 11)
+ dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT;
+ else
+ dev_priv->guc_events = GEN11_GUC_INTR_GUC2HOST;
+ }
/* Let's track the enabled rps events */
if (IS_VALLEYVIEW(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h
index 0ccd0d90919d..cb25dd213308 100644
--- a/drivers/gpu/drm/i915/i915_irq.h
+++ b/drivers/gpu/drm/i915/i915_irq.h
@@ -110,5 +110,8 @@ void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
+void gen11_reset_guc_interrupts(struct drm_i915_private *i915);
+void gen11_enable_guc_interrupts(struct drm_i915_private *i915);
+void gen11_disable_guc_interrupts(struct drm_i915_private *i915);
#endif /* __I915_IRQ_H__ */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bba420aaa4ab..0dfa1fe3e0c0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -290,6 +290,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define OTHER_CLASS 4
#define MAX_ENGINE_CLASS 4
+#define OTHER_GUC_INSTANCE 0
#define OTHER_GTPM_INSTANCE 1
#define MAX_ENGINE_INSTANCE 3
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 28642bf977bd..cbe4b8df15fd 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -88,6 +88,9 @@ void intel_guc_init_early(struct intel_guc *guc)
guc->handler = intel_guc_to_host_event_handler_nop;
if (INTEL_GEN(i915) >= 11) {
guc->notify = gen11_guc_raise_irq;
+ guc->interrupts.reset = gen11_reset_guc_interrupts;
+ guc->interrupts.enable = gen11_enable_guc_interrupts;
+ guc->interrupts.disable = gen11_disable_guc_interrupts;
} else {
guc->notify = gen8_guc_raise_irq;
guc->interrupts.reset = gen9_reset_guc_interrupts;
diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h b/drivers/gpu/drm/i915/intel_guc_reg.h
index 7eba65795b58..a214f8b71929 100644
--- a/drivers/gpu/drm/i915/intel_guc_reg.h
+++ b/drivers/gpu/drm/i915/intel_guc_reg.h
@@ -134,4 +134,22 @@ struct guc_doorbell_info {
#define GUC_WD_VECS_IER _MMIO(0xC558)
#define GUC_PM_P24C_IER _MMIO(0xC55C)
+/* GuC Interrupt Vector */
+#define GEN11_GUC_INTR_GUC2HOST (1 << 15)
+#define GEN11_GUC_INTR_EXEC_ERROR (1 << 14)
+#define GEN11_GUC_INTR_DISPLAY_EVENT (1 << 13)
+#define GEN11_GUC_INTR_SEM_SIG (1 << 12)
+#define GEN11_GUC_INTR_IOMMU2GUC (1 << 11)
+#define GEN11_GUC_INTR_DOORBELL_RANG (1 << 10)
+#define GEN11_GUC_INTR_DMA_DONE (1 << 9)
+#define GEN11_GUC_INTR_FATAL_ERROR (1 << 8)
+#define GEN11_GUC_INTR_NOTIF_ERROR (1 << 7)
+#define GEN11_GUC_INTR_SW_INT_6 (1 << 6)
+#define GEN11_GUC_INTR_SW_INT_5 (1 << 5)
+#define GEN11_GUC_INTR_SW_INT_4 (1 << 4)
+#define GEN11_GUC_INTR_SW_INT_3 (1 << 3)
+#define GEN11_GUC_INTR_SW_INT_2 (1 << 2)
+#define GEN11_GUC_INTR_SW_INT_1 (1 << 1)
+#define GEN11_GUC_INTR_SW_INT_0 (1 << 0)
+
#endif
--
2.19.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread* Re: [PATCH v4 17/22] drm/i915/guc: Correctly handle GuC interrupts on Gen11
2019-05-23 23:30 ` [PATCH v4 17/22] drm/i915/guc: Correctly handle GuC interrupts on Gen11 Michal Wajdeczko
@ 2019-05-27 14:30 ` Michał Winiarski
0 siblings, 0 replies; 34+ messages in thread
From: Michał Winiarski @ 2019-05-27 14:30 UTC (permalink / raw)
To: Michal Wajdeczko; +Cc: Oscar Mateo, intel-gfx
On Thu, May 23, 2019 at 11:30:44PM +0000, Michal Wajdeczko wrote:
> From: Oscar Mateo <oscar.mateo@intel.com>
>
> The GuC interrupts now get their own interrupt vector (instead of
> sharing a register with the PM interrupts) so handle appropriately.
>
> v2: (Chris)
> v3: rebased (Michal)
> Bspec: 19820
Bspec: 19820, 19840, 19841, 20176
>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 6 ++-
> drivers/gpu/drm/i915/i915_irq.c | 58 +++++++++++++++++++++++++++-
> drivers/gpu/drm/i915/i915_irq.h | 3 ++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_guc.c | 3 ++
> drivers/gpu/drm/i915/intel_guc_reg.h | 18 +++++++++
> 6 files changed, 86 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 311e19154672..6bd7a9347071 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1570,7 +1570,11 @@ struct drm_i915_private {
> u32 pm_imr;
> u32 pm_ier;
> u32 pm_rps_events;
> - u32 pm_guc_events;
> + union {
> + /* RPS and GuC share a register pre-Gen11 */
> + u32 pm_guc_events;
> + u32 guc_events;
> + };
> u32 pipestat_irq_mask[I915_MAX_PIPES];
>
> struct i915_hotplug hotplug;
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 607709a8c229..52345772f84c 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -624,6 +624,41 @@ void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
> gen9_reset_guc_interrupts(dev_priv);
> }
>
> +void gen11_reset_guc_interrupts(struct drm_i915_private *i915)
> +{
> + spin_lock_irq(&i915->irq_lock);
> + gen11_reset_one_iir(i915, 0, GEN11_GUC);
> + spin_unlock_irq(&i915->irq_lock);
> +}
> +
> +void gen11_enable_guc_interrupts(struct drm_i915_private *dev_priv)
> +{
> + spin_lock_irq(&dev_priv->irq_lock);
> + if (!dev_priv->guc.interrupts.enabled) {
> + u32 guc_events = dev_priv->guc_events << 16;
#define the GuC enable/mask shift somewhere (also, adding a comment stating that
GuC is sharing this register with SG, and we currently don't care about
SG interrupts wouldn't hurt)
With that
Reviewed-by: Michał Winiarski <michal.winiarski@intel.com>
-Michał
> +
> + WARN_ON_ONCE(gen11_reset_one_iir(dev_priv, 0, GEN11_GUC));
> + I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, guc_events);
> + I915_WRITE(GEN11_GUC_SG_INTR_MASK, ~guc_events);
> + dev_priv->guc.interrupts.enabled = true;
> + }
> + spin_unlock_irq(&dev_priv->irq_lock);
> +}
> +
> +void gen11_disable_guc_interrupts(struct drm_i915_private *dev_priv)
> +{
> + spin_lock_irq(&dev_priv->irq_lock);
> + dev_priv->guc.interrupts.enabled = false;
> +
> + I915_WRITE(GEN11_GUC_SG_INTR_MASK, ~0);
> + I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, 0);
> +
> + spin_unlock_irq(&dev_priv->irq_lock);
> + synchronize_irq(dev_priv->drm.irq);
> +
> + gen11_reset_guc_interrupts(dev_priv);
> +}
> +
> /**
> * bdw_update_port_irq - update DE port interrupt
> * @dev_priv: driver private
> @@ -1893,6 +1928,12 @@ static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir)
> intel_guc_to_host_event_handler(&dev_priv->guc);
> }
>
> +static void gen11_guc_irq_handler(struct drm_i915_private *i915, u16 iir)
> +{
> + if (iir & GEN11_GUC_INTR_GUC2HOST)
> + intel_guc_to_host_event_handler(&i915->guc);
> +}
> +
> static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
> {
> enum pipe pipe;
> @@ -3015,6 +3056,9 @@ static void
> gen11_other_irq_handler(struct drm_i915_private * const i915,
> const u8 instance, const u16 iir)
> {
> + if (instance == OTHER_GUC_INSTANCE)
> + return gen11_guc_irq_handler(i915, iir);
> +
> if (instance == OTHER_GTPM_INSTANCE)
> return gen11_rps_irq_handler(i915, iir);
>
> @@ -3545,6 +3589,8 @@ static void gen11_gt_irq_reset(struct drm_i915_private *dev_priv)
>
> I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
> I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
> + I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, 0);
> + I915_WRITE(GEN11_GUC_SG_INTR_MASK, ~0);
> }
>
> static void gen11_irq_reset(struct drm_device *dev)
> @@ -4200,6 +4246,10 @@ static void gen11_gt_irq_postinstall(struct drm_i915_private *dev_priv)
> dev_priv->pm_imr = ~dev_priv->pm_ier;
> I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
> I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
> +
> + /* Same thing for GuC interrupts */
> + I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, 0);
> + I915_WRITE(GEN11_GUC_SG_INTR_MASK, ~0);
> }
>
> static void icp_irq_postinstall(struct drm_device *dev)
> @@ -4707,8 +4757,12 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
> for (i = 0; i < MAX_L3_SLICES; ++i)
> dev_priv->l3_parity.remap_info[i] = NULL;
>
> - if (HAS_GUC_SCHED(dev_priv))
> - dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT;
> + if (HAS_GUC_SCHED(dev_priv)) {
> + if (INTEL_GEN(dev_priv) < 11)
> + dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT;
> + else
> + dev_priv->guc_events = GEN11_GUC_INTR_GUC2HOST;
> + }
>
> /* Let's track the enabled rps events */
> if (IS_VALLEYVIEW(dev_priv))
> diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h
> index 0ccd0d90919d..cb25dd213308 100644
> --- a/drivers/gpu/drm/i915/i915_irq.h
> +++ b/drivers/gpu/drm/i915/i915_irq.h
> @@ -110,5 +110,8 @@ void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
> void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
> void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
> void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
> +void gen11_reset_guc_interrupts(struct drm_i915_private *i915);
> +void gen11_enable_guc_interrupts(struct drm_i915_private *i915);
> +void gen11_disable_guc_interrupts(struct drm_i915_private *i915);
>
> #endif /* __I915_IRQ_H__ */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index bba420aaa4ab..0dfa1fe3e0c0 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -290,6 +290,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define OTHER_CLASS 4
> #define MAX_ENGINE_CLASS 4
>
> +#define OTHER_GUC_INSTANCE 0
> #define OTHER_GTPM_INSTANCE 1
> #define MAX_ENGINE_INSTANCE 3
>
> diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
> index 28642bf977bd..cbe4b8df15fd 100644
> --- a/drivers/gpu/drm/i915/intel_guc.c
> +++ b/drivers/gpu/drm/i915/intel_guc.c
> @@ -88,6 +88,9 @@ void intel_guc_init_early(struct intel_guc *guc)
> guc->handler = intel_guc_to_host_event_handler_nop;
> if (INTEL_GEN(i915) >= 11) {
> guc->notify = gen11_guc_raise_irq;
> + guc->interrupts.reset = gen11_reset_guc_interrupts;
> + guc->interrupts.enable = gen11_enable_guc_interrupts;
> + guc->interrupts.disable = gen11_disable_guc_interrupts;
> } else {
> guc->notify = gen8_guc_raise_irq;
> guc->interrupts.reset = gen9_reset_guc_interrupts;
> diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h b/drivers/gpu/drm/i915/intel_guc_reg.h
> index 7eba65795b58..a214f8b71929 100644
> --- a/drivers/gpu/drm/i915/intel_guc_reg.h
> +++ b/drivers/gpu/drm/i915/intel_guc_reg.h
> @@ -134,4 +134,22 @@ struct guc_doorbell_info {
> #define GUC_WD_VECS_IER _MMIO(0xC558)
> #define GUC_PM_P24C_IER _MMIO(0xC55C)
>
> +/* GuC Interrupt Vector */
> +#define GEN11_GUC_INTR_GUC2HOST (1 << 15)
> +#define GEN11_GUC_INTR_EXEC_ERROR (1 << 14)
> +#define GEN11_GUC_INTR_DISPLAY_EVENT (1 << 13)
> +#define GEN11_GUC_INTR_SEM_SIG (1 << 12)
> +#define GEN11_GUC_INTR_IOMMU2GUC (1 << 11)
> +#define GEN11_GUC_INTR_DOORBELL_RANG (1 << 10)
> +#define GEN11_GUC_INTR_DMA_DONE (1 << 9)
> +#define GEN11_GUC_INTR_FATAL_ERROR (1 << 8)
> +#define GEN11_GUC_INTR_NOTIF_ERROR (1 << 7)
> +#define GEN11_GUC_INTR_SW_INT_6 (1 << 6)
> +#define GEN11_GUC_INTR_SW_INT_5 (1 << 5)
> +#define GEN11_GUC_INTR_SW_INT_4 (1 << 4)
> +#define GEN11_GUC_INTR_SW_INT_3 (1 << 3)
> +#define GEN11_GUC_INTR_SW_INT_2 (1 << 2)
> +#define GEN11_GUC_INTR_SW_INT_1 (1 << 1)
> +#define GEN11_GUC_INTR_SW_INT_0 (1 << 0)
> +
> #endif
> --
> 2.19.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH v4 18/22] drm/i915/guc: Update GuC CTB response definition
2019-05-23 23:30 [PATCH v4 00/22] GuC 32.0.3 Michal Wajdeczko
` (16 preceding siblings ...)
2019-05-23 23:30 ` [PATCH v4 17/22] drm/i915/guc: Correctly handle GuC interrupts on Gen11 Michal Wajdeczko
@ 2019-05-23 23:30 ` Michal Wajdeczko
2019-05-23 23:30 ` [PATCH v4 19/22] drm/i915/guc: Enable GuC CTB communication on Gen11 Michal Wajdeczko
` (6 subsequent siblings)
24 siblings, 0 replies; 34+ messages in thread
From: Michal Wajdeczko @ 2019-05-23 23:30 UTC (permalink / raw)
To: intel-gfx
Current GuC firmwares identify response message in a different way.
v2: update comments for other H2G bits (Daniele)
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Kelvin Gardiner <kelvin.gardiner@intel.com>
Cc: John Spotswood <john.a.spotswood@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/intel_guc_ct.c | 2 +-
drivers/gpu/drm/i915/intel_guc_fwif.h | 8 +++++---
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_ct.c b/drivers/gpu/drm/i915/intel_guc_ct.c
index dde1dc0d6e69..2d5dc2aa22a7 100644
--- a/drivers/gpu/drm/i915/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/intel_guc_ct.c
@@ -565,7 +565,7 @@ static inline unsigned int ct_header_get_action(u32 header)
static inline bool ct_header_is_response(u32 header)
{
- return ct_header_get_action(header) == INTEL_GUC_ACTION_DEFAULT;
+ return !!(header & GUC_CT_MSG_IS_RESPONSE);
}
static int ctb_read(struct intel_guc_ct_buffer *ctb, u32 *data)
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index fa745a58d38d..3d1de288d96c 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -355,14 +355,16 @@ struct guc_ct_buffer_desc {
*
* bit[4..0] message len (in dwords)
* bit[7..5] reserved
- * bit[8] write fence to desc
- * bit[9] write status to H2G buff
- * bit[10] send status (via G2H)
+ * bit[8] response (G2H only)
+ * bit[8] write fence to desc (H2G only)
+ * bit[9] write status to H2G buff (H2G only)
+ * bit[10] send status back via G2H (H2G only)
* bit[15..11] reserved
* bit[31..16] action code
*/
#define GUC_CT_MSG_LEN_SHIFT 0
#define GUC_CT_MSG_LEN_MASK 0x1F
+#define GUC_CT_MSG_IS_RESPONSE (1 << 8)
#define GUC_CT_MSG_WRITE_FENCE_TO_DESC (1 << 8)
#define GUC_CT_MSG_WRITE_STATUS_TO_BUFF (1 << 9)
#define GUC_CT_MSG_SEND_STATUS (1 << 10)
--
2.19.2
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH v4 19/22] drm/i915/guc: Enable GuC CTB communication on Gen11
2019-05-23 23:30 [PATCH v4 00/22] GuC 32.0.3 Michal Wajdeczko
` (17 preceding siblings ...)
2019-05-23 23:30 ` [PATCH v4 18/22] drm/i915/guc: Update GuC CTB response definition Michal Wajdeczko
@ 2019-05-23 23:30 ` Michal Wajdeczko
2019-05-23 23:30 ` [PATCH v4 20/22] drm/i915/guc: Define GuC firmware version for Icelake Michal Wajdeczko
` (5 subsequent siblings)
24 siblings, 0 replies; 34+ messages in thread
From: Michal Wajdeczko @ 2019-05-23 23:30 UTC (permalink / raw)
To: intel-gfx
Gen11 GuC firmware expects H2G command messages to be sent over CTB
(command transport buffers).
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: John Spotswood <john.a.spotswood@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d7c07a947497..fc66d7f348fc 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -746,6 +746,7 @@ static const struct intel_device_info intel_cannonlake_info = {
}, \
GEN(11), \
.ddb_size = 2048, \
+ .has_guc_ct = 1, \
.has_logical_ring_elsq = 1, \
.color = { .degamma_lut_size = 33, .gamma_lut_size = 1024 }
--
2.19.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH v4 20/22] drm/i915/guc: Define GuC firmware version for Icelake
2019-05-23 23:30 [PATCH v4 00/22] GuC 32.0.3 Michal Wajdeczko
` (18 preceding siblings ...)
2019-05-23 23:30 ` [PATCH v4 19/22] drm/i915/guc: Enable GuC CTB communication on Gen11 Michal Wajdeczko
@ 2019-05-23 23:30 ` Michal Wajdeczko
2019-05-23 23:30 ` [PATCH v4 21/22] drm/i915/huc: Define HuC " Michal Wajdeczko
` (4 subsequent siblings)
24 siblings, 0 replies; 34+ messages in thread
From: Michal Wajdeczko @ 2019-05-23 23:30 UTC (permalink / raw)
To: intel-gfx
Define GuC firmware version for Icelake.
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/intel_guc_fw.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c b/drivers/gpu/drm/i915/intel_guc_fw.c
index c1e9bb4e04fd..72cdafd9636a 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -65,6 +65,13 @@ MODULE_FIRMWARE(KBL_GUC_FIRMWARE_PATH);
#define GLK_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(GLK)
MODULE_FIRMWARE(GLK_GUC_FIRMWARE_PATH);
+#define ICL_GUC_FW_PREFIX icl
+#define ICL_GUC_FW_MAJOR 32
+#define ICL_GUC_FW_MINOR 0
+#define ICL_GUC_FW_PATCH 3
+#define ICL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(ICL)
+MODULE_FIRMWARE(ICL_GUC_FIRMWARE_PATH);
+
static void guc_fw_select(struct intel_uc_fw *guc_fw)
{
struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
@@ -79,6 +86,10 @@ static void guc_fw_select(struct intel_uc_fw *guc_fw)
guc_fw->path = i915_modparams.guc_firmware_path;
guc_fw->major_ver_wanted = 0;
guc_fw->minor_ver_wanted = 0;
+ } else if (IS_ICELAKE(i915)) {
+ guc_fw->path = ICL_GUC_FIRMWARE_PATH;
+ guc_fw->major_ver_wanted = ICL_GUC_FW_MAJOR;
+ guc_fw->minor_ver_wanted = ICL_GUC_FW_MINOR;
} else if (IS_GEMINILAKE(i915)) {
guc_fw->path = GLK_GUC_FIRMWARE_PATH;
guc_fw->major_ver_wanted = GLK_GUC_FW_MAJOR;
--
2.19.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH v4 21/22] drm/i915/huc: Define HuC firmware version for Icelake
2019-05-23 23:30 [PATCH v4 00/22] GuC 32.0.3 Michal Wajdeczko
` (19 preceding siblings ...)
2019-05-23 23:30 ` [PATCH v4 20/22] drm/i915/guc: Define GuC firmware version for Icelake Michal Wajdeczko
@ 2019-05-23 23:30 ` Michal Wajdeczko
2019-05-25 0:58 ` Ye, Tony
2019-05-23 23:30 ` [PATCH v4 22/22] HAX: turn on GuC/HuC auto mode Michal Wajdeczko
` (3 subsequent siblings)
24 siblings, 1 reply; 34+ messages in thread
From: Michal Wajdeczko @ 2019-05-23 23:30 UTC (permalink / raw)
To: intel-gfx
Define HuC firmware version for Icelake.
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Tony Ye <tony.ye@intel.com>
v2: 8.4.3238 is now available
---
drivers/gpu/drm/i915/intel_huc_fw.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_huc_fw.c b/drivers/gpu/drm/i915/intel_huc_fw.c
index 8bac6a051c18..05cbf8338f53 100644
--- a/drivers/gpu/drm/i915/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/intel_huc_fw.c
@@ -38,6 +38,10 @@
#define GLK_HUC_FW_MINOR 01
#define GLK_BLD_NUM 2893
+#define ICL_HUC_FW_MAJOR 8
+#define ICL_HUC_FW_MINOR 4
+#define ICL_BLD_NUM 3238
+
#define HUC_FW_PATH(platform, major, minor, bld_num) \
"i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
__stringify(minor) "_" __stringify(bld_num) ".bin"
@@ -58,6 +62,10 @@ MODULE_FIRMWARE(I915_KBL_HUC_UCODE);
GLK_HUC_FW_MINOR, GLK_BLD_NUM)
MODULE_FIRMWARE(I915_GLK_HUC_UCODE);
+#define I915_ICL_HUC_UCODE HUC_FW_PATH(icl, ICL_HUC_FW_MAJOR, \
+ ICL_HUC_FW_MINOR, ICL_BLD_NUM)
+MODULE_FIRMWARE(I915_ICL_HUC_UCODE);
+
static void huc_fw_select(struct intel_uc_fw *huc_fw)
{
struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
@@ -88,6 +96,10 @@ static void huc_fw_select(struct intel_uc_fw *huc_fw)
huc_fw->path = I915_GLK_HUC_UCODE;
huc_fw->major_ver_wanted = GLK_HUC_FW_MAJOR;
huc_fw->minor_ver_wanted = GLK_HUC_FW_MINOR;
+ } else if (IS_ICELAKE(dev_priv)) {
+ huc_fw->path = I915_ICL_HUC_UCODE;
+ huc_fw->major_ver_wanted = ICL_HUC_FW_MAJOR;
+ huc_fw->minor_ver_wanted = ICL_HUC_FW_MINOR;
}
}
--
2.19.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread* Re: [PATCH v4 21/22] drm/i915/huc: Define HuC firmware version for Icelake
2019-05-23 23:30 ` [PATCH v4 21/22] drm/i915/huc: Define HuC " Michal Wajdeczko
@ 2019-05-25 0:58 ` Ye, Tony
0 siblings, 0 replies; 34+ messages in thread
From: Ye, Tony @ 2019-05-25 0:58 UTC (permalink / raw)
To: Wajdeczko, Michal; +Cc: intel-gfx
Reviewed-by: Tony Ye <tony.ye@intel.com>
> 在 2019年5月24日，上午7:32，Wajdeczko, Michal <Michal.Wajdeczko@intel.com> 写道：
>
> Define HuC firmware version for Icelake.
>
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Tony Ye <tony.ye@intel.com>
>
> v2: 8.4.3238 is now available
> ---
> drivers/gpu/drm/i915/intel_huc_fw.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_huc_fw.c b/drivers/gpu/drm/i915/intel_huc_fw.c
> index 8bac6a051c18..05cbf8338f53 100644
> --- a/drivers/gpu/drm/i915/intel_huc_fw.c
> +++ b/drivers/gpu/drm/i915/intel_huc_fw.c
> @@ -38,6 +38,10 @@
> #define GLK_HUC_FW_MINOR 01
> #define GLK_BLD_NUM 2893
>
> +#define ICL_HUC_FW_MAJOR 8
> +#define ICL_HUC_FW_MINOR 4
> +#define ICL_BLD_NUM 3238
> +
> #define HUC_FW_PATH(platform, major, minor, bld_num) \
> "i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
> __stringify(minor) "_" __stringify(bld_num) ".bin"
> @@ -58,6 +62,10 @@ MODULE_FIRMWARE(I915_KBL_HUC_UCODE);
> GLK_HUC_FW_MINOR, GLK_BLD_NUM)
> MODULE_FIRMWARE(I915_GLK_HUC_UCODE);
>
> +#define I915_ICL_HUC_UCODE HUC_FW_PATH(icl, ICL_HUC_FW_MAJOR, \
> + ICL_HUC_FW_MINOR, ICL_BLD_NUM)
> +MODULE_FIRMWARE(I915_ICL_HUC_UCODE);
> +
> static void huc_fw_select(struct intel_uc_fw *huc_fw)
> {
> struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
> @@ -88,6 +96,10 @@ static void huc_fw_select(struct intel_uc_fw *huc_fw)
> huc_fw->path = I915_GLK_HUC_UCODE;
> huc_fw->major_ver_wanted = GLK_HUC_FW_MAJOR;
> huc_fw->minor_ver_wanted = GLK_HUC_FW_MINOR;
> + } else if (IS_ICELAKE(dev_priv)) {
> + huc_fw->path = I915_ICL_HUC_UCODE;
> + huc_fw->major_ver_wanted = ICL_HUC_FW_MAJOR;
> + huc_fw->minor_ver_wanted = ICL_HUC_FW_MINOR;
> }
> }
>
> --
> 2.19.2
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH v4 22/22] HAX: turn on GuC/HuC auto mode
2019-05-23 23:30 [PATCH v4 00/22] GuC 32.0.3 Michal Wajdeczko
` (20 preceding siblings ...)
2019-05-23 23:30 ` [PATCH v4 21/22] drm/i915/huc: Define HuC " Michal Wajdeczko
@ 2019-05-23 23:30 ` Michal Wajdeczko
2019-05-23 23:51 ` ✗ Fi.CI.CHECKPATCH: warning for GuC 32.0.3 (rev5) Patchwork
` (2 subsequent siblings)
24 siblings, 0 replies; 34+ messages in thread
From: Michal Wajdeczko @ 2019-05-23 23:30 UTC (permalink / raw)
To: intel-gfx
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
drivers/gpu/drm/i915/intel_huc.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 3f14e9881a0d..e28ae23de516 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -54,7 +54,7 @@ struct drm_printer;
param(int, disable_power_well, -1) \
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
- param(int, enable_guc, 0) \
+ param(int, enable_guc, -1) \
param(int, guc_log_level, -1) \
param(char *, guc_firmware_path, NULL) \
param(char *, huc_firmware_path, NULL) \
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index 8572a0588efc..33d17ca5152d 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -139,7 +139,7 @@ int intel_huc_auth(struct intel_huc *huc)
huc->status.reg,
huc->status.mask,
huc->status.value,
- 2, 50, NULL);
+ 2, 150, NULL);
if (ret) {
DRM_ERROR("HuC: Firmware not verified %d\n", ret);
goto fail;
--
2.19.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread* ✗ Fi.CI.CHECKPATCH: warning for GuC 32.0.3 (rev5)
2019-05-23 23:30 [PATCH v4 00/22] GuC 32.0.3 Michal Wajdeczko
` (21 preceding siblings ...)
2019-05-23 23:30 ` [PATCH v4 22/22] HAX: turn on GuC/HuC auto mode Michal Wajdeczko
@ 2019-05-23 23:51 ` Patchwork
2019-05-24 0:09 ` ✓ Fi.CI.BAT: success " Patchwork
2019-05-25 10:39 ` ✗ Fi.CI.IGT: failure " Patchwork
24 siblings, 0 replies; 34+ messages in thread
From: Patchwork @ 2019-05-23 23:51 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx
== Series Details ==
Series: GuC 32.0.3 (rev5)
URL : https://patchwork.freedesktop.org/series/58760/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
492a32a18ce1 drm/i915/guc: Change platform default GuC mode
e563e9032b70 drm/i915/guc: Don't allow GuC submission
dab8c578708e drm/i915/guc: Update GuC firmware versions and names
7ab12cc002a1 drm/i915/guc: Update GuC firmware CSS header
66c70a6a79a0 drm/i915/guc: Update GuC boot parameters
8dadadfd8d3c drm/i915/guc: Update suspend/resume protocol
babdc74f71ec drm/i915/guc: Update GuC sample-forcewake command
7afa9119548d drm/i915/guc: Update GuC ADS object definition
ee1b1cb04071 drm/i915/guc: Reset GuC ADS during sanitize
45831353894e drm/i915/guc: Always ask GuC to update power domain states
f04e6d373ba9 drm/i915/guc: Define GuC firmware version for Geminilake
e8e0dc5b9c8f drm/i915/huc: Define HuC firmware version for Geminilake
10f29ecf26e1 drm/i915/guc: New GuC interrupt register for Gen11
c1211394017e drm/i915/guc: New GuC scratch registers for Gen11
4325181c8c9e drm/i915/huc: New HuC status register for Gen11
ab2c6a333f49 drm/i915/guc: Create vfuncs for the GuC interrupts control functions
3f682f2b01ac drm/i915/guc: Correctly handle GuC interrupts on Gen11
ec7b885f8851 drm/i915/guc: Update GuC CTB response definition
7e97a31ba0f9 drm/i915/guc: Enable GuC CTB communication on Gen11
5474348ad0d5 drm/i915/guc: Define GuC firmware version for Icelake
3a472e369ec2 drm/i915/huc: Define HuC firmware version for Icelake
ab934c8dd4b5 HAX: turn on GuC/HuC auto mode
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
total: 0 errors, 1 warnings, 0 checks, 16 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 34+ messages in thread* ✓ Fi.CI.BAT: success for GuC 32.0.3 (rev5)
2019-05-23 23:30 [PATCH v4 00/22] GuC 32.0.3 Michal Wajdeczko
` (22 preceding siblings ...)
2019-05-23 23:51 ` ✗ Fi.CI.CHECKPATCH: warning for GuC 32.0.3 (rev5) Patchwork
@ 2019-05-24 0:09 ` Patchwork
2019-05-25 10:39 ` ✗ Fi.CI.IGT: failure " Patchwork
24 siblings, 0 replies; 34+ messages in thread
From: Patchwork @ 2019-05-24 0:09 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx
== Series Details ==
Series: GuC 32.0.3 (rev5)
URL : https://patchwork.freedesktop.org/series/58760/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6137 -> Patchwork_13086
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_13086:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live_hangcheck:
- {fi-icl-u3}: [PASS][1] -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6137/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
- {fi-icl-y}: [INCOMPLETE][3] ([fdo#107713] / [fdo#108569]) -> [DMESG-FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6137/fi-icl-y/igt@i915_selftest@live_hangcheck.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/fi-icl-y/igt@i915_selftest@live_hangcheck.html
- {fi-icl-dsi}: [INCOMPLETE][5] ([fdo#107713] / [fdo#108569]) -> [DMESG-FAIL][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6137/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
Known issues
------------
Here are the changes found in Patchwork_13086 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-kbl-7567u: [PASS][7] -> [DMESG-WARN][8] ([fdo#108566])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6137/fi-kbl-7567u/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/fi-kbl-7567u/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3:
- fi-apl-guc: [DMESG-WARN][9] ([fdo#110512]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6137/fi-apl-guc/igt@gem_exec_suspend@basic-s3.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/fi-apl-guc/igt@gem_exec_suspend@basic-s3.html
* igt@i915_module_load@reload:
- fi-apl-guc: [DMESG-WARN][11] -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6137/fi-apl-guc/igt@i915_module_load@reload.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/fi-apl-guc/igt@i915_module_load@reload.html
* igt@kms_flip@basic-flip-vs-wf_vblank:
- fi-pnv-d510: [FAIL][13] ([fdo#100368]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6137/fi-pnv-d510/igt@kms_flip@basic-flip-vs-wf_vblank.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/fi-pnv-d510/igt@kms_flip@basic-flip-vs-wf_vblank.html
* igt@kms_frontbuffer_tracking@basic:
- {fi-icl-u3}: [FAIL][15] ([fdo#103167]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6137/fi-icl-u3/igt@kms_frontbuffer_tracking@basic.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/fi-icl-u3/igt@kms_frontbuffer_tracking@basic.html
- {fi-icl-u2}: [FAIL][17] ([fdo#103167]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6137/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#110512]: https://bugs.freedesktop.org/show_bug.cgi?id=110512
Participating hosts (44 -> 41)
------------------------------
Additional (2): fi-hsw-4770r fi-icl-guc
Missing (5): fi-kbl-soraka fi-ilk-m540 fi-skl-gvtdvm fi-bsw-cyan fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_6137 -> Patchwork_13086
CI_DRM_6137: e0fe0a5239c1f280c1268e519dbed94e3c429d80 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5011: 7f120c5f1bff2727d50f3c392d81c0f6878b61d6 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13086: ab934c8dd4b5805236d70ef1e66156991ade6ade @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
ab934c8dd4b5 HAX: turn on GuC/HuC auto mode
3a472e369ec2 drm/i915/huc: Define HuC firmware version for Icelake
5474348ad0d5 drm/i915/guc: Define GuC firmware version for Icelake
7e97a31ba0f9 drm/i915/guc: Enable GuC CTB communication on Gen11
ec7b885f8851 drm/i915/guc: Update GuC CTB response definition
3f682f2b01ac drm/i915/guc: Correctly handle GuC interrupts on Gen11
ab2c6a333f49 drm/i915/guc: Create vfuncs for the GuC interrupts control functions
4325181c8c9e drm/i915/huc: New HuC status register for Gen11
c1211394017e drm/i915/guc: New GuC scratch registers for Gen11
10f29ecf26e1 drm/i915/guc: New GuC interrupt register for Gen11
e8e0dc5b9c8f drm/i915/huc: Define HuC firmware version for Geminilake
f04e6d373ba9 drm/i915/guc: Define GuC firmware version for Geminilake
45831353894e drm/i915/guc: Always ask GuC to update power domain states
ee1b1cb04071 drm/i915/guc: Reset GuC ADS during sanitize
7afa9119548d drm/i915/guc: Update GuC ADS object definition
babdc74f71ec drm/i915/guc: Update GuC sample-forcewake command
8dadadfd8d3c drm/i915/guc: Update suspend/resume protocol
66c70a6a79a0 drm/i915/guc: Update GuC boot parameters
7ab12cc002a1 drm/i915/guc: Update GuC firmware CSS header
dab8c578708e drm/i915/guc: Update GuC firmware versions and names
e563e9032b70 drm/i915/guc: Don't allow GuC submission
492a32a18ce1 drm/i915/guc: Change platform default GuC mode
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 34+ messages in thread* ✗ Fi.CI.IGT: failure for GuC 32.0.3 (rev5)
2019-05-23 23:30 [PATCH v4 00/22] GuC 32.0.3 Michal Wajdeczko
` (23 preceding siblings ...)
2019-05-24 0:09 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-05-25 10:39 ` Patchwork
2019-05-25 11:47 ` Michal Wajdeczko
24 siblings, 1 reply; 34+ messages in thread
From: Patchwork @ 2019-05-25 10:39 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx
== Series Details ==
Series: GuC 32.0.3 (rev5)
URL : https://patchwork.freedesktop.org/series/58760/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6137_full -> Patchwork_13086_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_13086_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_13086_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_13086_full:
### IGT changes ###
#### Possible regressions ####
* igt@debugfs_test@read_all_entries:
- shard-glk: [PASS][1] -> [DMESG-WARN][2] +3 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6137/shard-glk4/igt@debugfs_test@read_all_entries.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/shard-glk1/igt@debugfs_test@read_all_entries.html
- shard-apl: [PASS][3] -> [DMESG-WARN][4] +2 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6137/shard-apl3/igt@debugfs_test@read_all_entries.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/shard-apl2/igt@debugfs_test@read_all_entries.html
* igt@debugfs_test@read_all_entries_display_off:
- shard-skl: [PASS][5] -> [DMESG-WARN][6] +4 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6137/shard-skl3/igt@debugfs_test@read_all_entries_display_off.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/shard-skl9/igt@debugfs_test@read_all_entries_display_off.html
* igt@debugfs_test@read_all_entries_display_on:
- shard-kbl: [PASS][7] -> [DMESG-WARN][8] +3 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6137/shard-kbl7/igt@debugfs_test@read_all_entries_display_on.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/shard-kbl3/igt@debugfs_test@read_all_entries_display_on.html
* igt@i915_selftest@live_hangcheck:
- shard-iclb: [PASS][9] -> [DMESG-FAIL][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6137/shard-iclb7/igt@i915_selftest@live_hangcheck.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/shard-iclb8/igt@i915_selftest@live_hangcheck.html
* igt@i915_suspend@debugfs-reader:
- shard-iclb: [PASS][11] -> [DMESG-WARN][12] +2 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6137/shard-iclb2/igt@i915_suspend@debugfs-reader.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/shard-iclb1/igt@i915_suspend@debugfs-reader.html
Known issues
------------
Here are the changes found in Patchwork_13086_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@bcs0-s3:
- shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([fdo#108566]) +8 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6137/shard-kbl4/igt@gem_ctx_isolation@bcs0-s3.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/shard-kbl3/igt@gem_ctx_isolation@bcs0-s3.html
* igt@gem_tiled_swapping@non-threaded:
- shard-apl: [PASS][15] -> [FAIL][16] ([fdo#108686])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6137/shard-apl1/igt@gem_tiled_swapping@non-threaded.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/shard-apl2/igt@gem_tiled_swapping@non-threaded.html
* igt@i915_suspend@debugfs-reader:
- shard-apl: [PASS][17] -> [DMESG-WARN][18] ([fdo#108566]) +5 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6137/shard-apl5/igt@i915_suspend@debugfs-reader.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/shard-apl1/igt@i915_suspend@debugfs-reader.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109349])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6137/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/shard-iclb1/igt@kms_dp_dsc@basic-dsc-enable-edp.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: [PASS][21] -> [FAIL][22] ([fdo#105363])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6137/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-skl: [PASS][23] -> [INCOMPLETE][24] ([fdo#109507])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6137/shard-skl9/igt@kms_flip@flip-vs-suspend-interruptible.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/shard-skl1/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt:
- shard-skl: [PASS][25] -> [FAIL][26] ([fdo#103167]) +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6137/shard-skl10/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/shard-skl9/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-stridechange:
- shard-iclb: [PASS][27] -> [FAIL][28] ([fdo#103167]) +7 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6137/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-stridechange.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-stridechange.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [PASS][29] -> [FAIL][30] ([fdo#108145]) +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6137/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_psr@psr2_suspend:
- shard-iclb: [PASS][31] -> [SKIP][32] ([fdo#109441]) +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6137/shard-iclb2/igt@kms_psr@psr2_suspend.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/shard-iclb4/igt@kms_psr@psr2_suspend.html
* igt@kms_setmode@basic:
- shard-kbl: [PASS][33] -> [FAIL][34] ([fdo#99912])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6137/shard-kbl6/igt@kms_setmode@basic.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/shard-kbl4/igt@kms_setmode@basic.html
* igt@perf_pmu@rc6:
- shard-apl: [PASS][35] -> [SKIP][36] ([fdo#109271])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6137/shard-apl2/igt@perf_pmu@rc6.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/shard-apl5/igt@perf_pmu@rc6.html
- shard-glk: [PASS][37] -> [SKIP][38] ([fdo#109271])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6137/shard-glk8/igt@perf_pmu@rc6.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/shard-glk6/igt@perf_pmu@rc6.html
- shard-skl: [PASS][39] -> [SKIP][40] ([fdo#109271])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6137/shard-skl7/igt@perf_pmu@rc6.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/shard-skl3/igt@perf_pmu@rc6.html
- shard-kbl: [PASS][41] -> [SKIP][42] ([fdo#109271])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6137/shard-kbl1/igt@perf_pmu@rc6.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/shard-kbl3/igt@perf_pmu@rc6.html
#### Possible fixes ####
* igt@gem_mmap_gtt@forked-big-copy:
- shard-iclb: [TIMEOUT][43] ([fdo#109673]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6137/shard-iclb6/igt@gem_mmap_gtt@forked-big-copy.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/shard-iclb2/igt@gem_mmap_gtt@forked-big-copy.html
* igt@i915_suspend@fence-restore-untiled:
- shard-apl: [DMESG-WARN][45] ([fdo#108566]) -> [PASS][46] +5 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6137/shard-apl5/igt@i915_suspend@fence-restore-untiled.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/shard-apl1/igt@i915_suspend@fence-restore-untiled.html
* igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
- shard-glk: [FAIL][47] ([fdo#106509] / [fdo#107409]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6137/shard-glk8/igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/shard-glk3/igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic.html
* igt@kms_draw_crc@draw-method-xrgb8888-blt-untiled:
- shard-skl: [FAIL][49] ([fdo#103184] / [fdo#103232] / [fdo#108472]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6137/shard-skl4/igt@kms_draw_crc@draw-method-xrgb8888-blt-untiled.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/shard-skl8/igt@kms_draw_crc@draw-method-xrgb8888-blt-untiled.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [FAIL][51] ([fdo#105363]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6137/shard-skl3/igt@kms_flip@flip-vs-expired-vblank.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/shard-skl8/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw:
- shard-iclb: [FAIL][53] ([fdo#103167]) -> [PASS][54] +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6137/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc:
- shard-iclb: [INCOMPLETE][55] ([fdo#106978] / [fdo#107713]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6137/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- shard-skl: [FAIL][57] ([fdo#103191]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6137/shard-skl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/shard-skl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [FAIL][59] ([fdo#108145] / [fdo#110403]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6137/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [FAIL][61] ([fdo#108145]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6137/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [SKIP][63] ([fdo#109441]) -> [PASS][64] +1 similar issue
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6137/shard-iclb6/igt@kms_psr@psr2_no_drrs.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
* igt@perf@polling:
- shard-iclb: [FAIL][65] ([fdo#110728]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6137/shard-iclb7/igt@perf@polling.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/shard-iclb3/igt@perf@polling.html
#### Warnings ####
* igt@gem_mmap_gtt@forked-big-copy-xy:
- shard-iclb: [TIMEOUT][67] ([fdo#109673]) -> [INCOMPLETE][68] ([fdo#107713] / [fdo#109100])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6137/shard-iclb3/igt@gem_mmap_gtt@forked-big-copy-xy.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/shard-iclb8/igt@gem_mmap_gtt@forked-big-copy-xy.html
* igt@prime_vgem@busy-bsd1:
- shard-snb: [FAIL][69] -> [INCOMPLETE][70] ([fdo#105411])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6137/shard-snb7/igt@prime_vgem@busy-bsd1.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/shard-snb5/igt@prime_vgem@busy-bsd1.html
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#106509]: https://bugs.freedesktop.org/show_bug.cgi?id=106509
[fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978
[fdo#107409]: https://bugs.freedesktop.org/show_bug.cgi?id=107409
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108472]: https://bugs.freedesktop.org/show_bug.cgi?id=108472
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
[fdo#109673]: https://bugs.freedesktop.org/show_bug.cgi?id=109673
[fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
[fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (8 -> 9)
------------------------------
Additional (1): shard-hsw
Build changes
-------------
* Linux: CI_DRM_6137 -> Patchwork_13086
CI_DRM_6137: e0fe0a5239c1f280c1268e519dbed94e3c429d80 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5011: 7f120c5f1bff2727d50f3c392d81c0f6878b61d6 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13086: ab934c8dd4b5805236d70ef1e66156991ade6ade @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13086/
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