* [v7][PATCH 01/12] drm/i915: Introduce vfunc read_luts() to create hw lut
2019-05-27 13:41 [v7][PATCH 00/12] drm/i915: adding state checker for gamma lut values Swati Sharma
@ 2019-05-27 13:41 ` Swati Sharma
2019-05-27 13:41 ` [v7][PATCH 02/12] drm/i915: Enable intel_color_get_config() Swati Sharma
` (14 subsequent siblings)
15 siblings, 0 replies; 20+ messages in thread
From: Swati Sharma @ 2019-05-27 13:41 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ankit.k.nautiyal
In this patch, a vfunc read_luts() is introduced to create a hw lut
i.e. lut having values read from gamma/degamma registers which will
later be used to compare with sw lut to validate gamma/degamma lut values.
v3: -Rebase
v4: -Renamed intel_get_color_config to intel_color_get_config [Jani]
-Wrapped get_color_config() [Jani]
v5: -Renamed intel_color_get_config() to intel_color_read_luts()
-Renamed get_color_config to read_luts
v6: -Renamed intel_color_read_luts() back to intel_color_get_config()
[Jani and Ville]
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_color.c | 8 ++++++++
drivers/gpu/drm/i915/intel_color.h | 1 +
3 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d025780..6343e70 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -343,6 +343,7 @@ struct drm_i915_display_funcs {
* involved with the same commit.
*/
void (*load_luts)(const struct intel_crtc_state *crtc_state);
+ void (*read_luts)(struct intel_crtc_state *crtc_state);
};
struct intel_csr {
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 962db12..50b98ee 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -879,6 +879,14 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
return dev_priv->display.color_check(crtc_state);
}
+void intel_color_get_config(struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+
+ if (dev_priv->display.read_luts)
+ dev_priv->display.read_luts(crtc_state);
+}
+
static bool need_plane_update(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state)
{
diff --git a/drivers/gpu/drm/i915/intel_color.h b/drivers/gpu/drm/i915/intel_color.h
index b8a3ce6..057e8ac 100644
--- a/drivers/gpu/drm/i915/intel_color.h
+++ b/drivers/gpu/drm/i915/intel_color.h
@@ -13,5 +13,6 @@
int intel_color_check(struct intel_crtc_state *crtc_state);
void intel_color_commit(const struct intel_crtc_state *crtc_state);
void intel_color_load_luts(const struct intel_crtc_state *crtc_state);
+void intel_color_get_config(struct intel_crtc_state *crtc_state);
#endif /* __INTEL_COLOR_H__ */
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [v7][PATCH 02/12] drm/i915: Enable intel_color_get_config()
2019-05-27 13:41 [v7][PATCH 00/12] drm/i915: adding state checker for gamma lut values Swati Sharma
2019-05-27 13:41 ` [v7][PATCH 01/12] drm/i915: Introduce vfunc read_luts() to create hw lut Swati Sharma
@ 2019-05-27 13:41 ` Swati Sharma
2019-05-27 13:41 ` [v7][PATCH 03/12] drm/i915: Add intel_color_lut_equal() to compare hw and sw gamma/degamma lut values Swati Sharma
` (13 subsequent siblings)
15 siblings, 0 replies; 20+ messages in thread
From: Swati Sharma @ 2019-05-27 13:41 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ankit.k.nautiyal
In this patch, intel_color_get_config() is enabled and support
for read_luts() will be added platform by platform incrementally
in the follow-up patches.
v4: -Renamed intel_get_color_config to intel_color_get_config [Jani]
-Added the user early on such that support for get_color_config()
can be added platform by platform incrementally [Jani]
v5: -Incorrect place for calling intel_color_get_config() in
haswell_get_pipe_config() [Ville]
v6: -Renamed intel_color_read_luts() to intel_color_get_config()
[Jani and Ville]
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 05177f3..3e01028 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8351,6 +8351,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
pipe_config->cgm_mode = I915_READ(CGM_PIPE_MODE(crtc->pipe));
i9xx_get_pipe_color_config(pipe_config);
+ intel_color_get_config(pipe_config);
if (INTEL_GEN(dev_priv) < 4)
pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
@@ -9426,6 +9427,7 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe));
i9xx_get_pipe_color_config(pipe_config);
+ intel_color_get_config(pipe_config);
if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
struct intel_shared_dpll *pll;
@@ -9874,6 +9876,8 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
i9xx_get_pipe_color_config(pipe_config);
}
+ intel_color_get_config(pipe_config);
+
power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
WARN_ON(power_domain_mask & BIT_ULL(power_domain));
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [v7][PATCH 03/12] drm/i915: Add intel_color_lut_equal() to compare hw and sw gamma/degamma lut values
2019-05-27 13:41 [v7][PATCH 00/12] drm/i915: adding state checker for gamma lut values Swati Sharma
2019-05-27 13:41 ` [v7][PATCH 01/12] drm/i915: Introduce vfunc read_luts() to create hw lut Swati Sharma
2019-05-27 13:41 ` [v7][PATCH 02/12] drm/i915: Enable intel_color_get_config() Swati Sharma
@ 2019-05-27 13:41 ` Swati Sharma
2019-05-27 13:41 ` [v7][PATCH 04/12] drm/i915: Extract i9xx_read_luts() Swati Sharma
` (12 subsequent siblings)
15 siblings, 0 replies; 20+ messages in thread
From: Swati Sharma @ 2019-05-27 13:41 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ankit.k.nautiyal
v3: -Rebase
v4: -Renamed intel_compare_color_lut() to intel_color_lut_equal() [Jani]
-Added the default label above the correct label [Jani]
-Corrected smatch warn "variable dereferenced before check" [Dan Carpenter]
v5: -Added condition (!blob1 && !blob2) return true [Jani]
-Called PIPE_CONF_CHECK_COLOR_LUT inside if (!adjust) [Jani]
-Added #undef PIPE_CONF_CHECK_COLOR_LUT [Jani]
v6: -Added func intel_color_get_bit_precision() to get bit precision for
gamma and degamma lut readout depending upon platform and
corresponding to load_luts() [Ankit]
-Added debug log for color para in intel_dump_pipe_config [Jani]
-Made patch11 as patch3 [Jani]
v7: -Renamed func intel_color_get_bit_precision() to intel_color_get_gamma_bit_precision()
-Added separate function/platform for gamma bit precision [Ville]
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
drivers/gpu/drm/i915/intel_color.c | 166 +++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_color.h | 7 ++
drivers/gpu/drm/i915/intel_display.c | 25 ++++++
3 files changed, 198 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 50b98ee..e566af5 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -1251,6 +1251,172 @@ static int icl_color_check(struct intel_crtc_state *crtc_state)
return 0;
}
+static int i9xx_gamma_precision(struct intel_crtc_state *crtc_state)
+{
+ if (!crtc_state->gamma_enable)
+ return 0;
+
+ switch (crtc_state->gamma_mode) {
+ case GAMMA_MODE_MODE_8BIT:
+ return 8;
+ case GAMMA_MODE_MODE_10BIT:
+ return 16;
+ default:
+ MISSING_CASE(crtc_state->gamma_mode);
+ return 0;
+ }
+}
+
+static int chv_gamma_precision(struct intel_crtc_state *crtc_state)
+{
+ if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
+ return 10;
+ else
+ return i9xx_gamma_precision(crtc_state);
+}
+
+static int ilk_gamma_precision(struct intel_crtc_state *crtc_state)
+{
+ if (!crtc_state->gamma_enable)
+ return 0;
+
+ if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
+ return 0;
+
+ switch (crtc_state->gamma_mode) {
+ case GAMMA_MODE_MODE_8BIT:
+ return 8;
+ case GAMMA_MODE_MODE_10BIT:
+ return 10;
+ default:
+ MISSING_CASE(crtc_state->gamma_mode);
+ return 0;
+ }
+}
+
+static int ivb_gamma_precision(struct intel_crtc_state *crtc_state)
+{
+ if (!crtc_state->gamma_enable)
+ return 0;
+
+ if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
+ return 0;
+
+ switch (crtc_state->gamma_mode) {
+ case GAMMA_MODE_MODE_8BIT:
+ return 8;
+ case GAMMA_MODE_MODE_SPLIT:
+ case GAMMA_MODE_MODE_10BIT:
+ return 10;
+ default:
+ MISSING_CASE(crtc_state->gamma_mode);
+ return 0;
+ }
+}
+
+static int glk_gamma_precision(struct intel_crtc_state *crtc_state)
+{
+ if (!crtc_state->gamma_enable)
+ return 0;
+
+ if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
+ return 0;
+
+ switch (crtc_state->gamma_mode) {
+ case GAMMA_MODE_MODE_8BIT:
+ return 8;
+ case GAMMA_MODE_MODE_10BIT:
+ return 10;
+ default:
+ MISSING_CASE(crtc_state->gamma_mode);
+ return 0;
+ }
+}
+
+static int icl_gamma_precision(struct intel_crtc_state *crtc_state)
+{
+ if ((crtc_state->gamma_mode & PRE_CSC_GAMMA_ENABLE) == 0)
+ return 0;
+
+ switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
+ case GAMMA_MODE_MODE_8BIT:
+ return 8;
+ case GAMMA_MODE_MODE_10BIT:
+ return 10;
+ default:
+ MISSING_CASE(crtc_state->gamma_mode);
+ return 0;
+ }
+}
+
+int intel_color_get_gamma_bit_precision(struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+
+ if (HAS_GMCH(dev_priv)) {
+ if (IS_CHERRYVIEW(dev_priv))
+ return chv_gamma_precision(crtc_state);
+ else
+ return i9xx_gamma_precision(crtc_state);
+ } else {
+ if (INTEL_GEN(dev_priv) >= 11)
+ return icl_gamma_precision(crtc_state);
+ else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
+ return glk_gamma_precision(crtc_state);
+ else if (INTEL_GEN(dev_priv) >= 7)
+ return ivb_gamma_precision(crtc_state);
+ else
+ return ilk_gamma_precision(crtc_state);
+ }
+
+ return 0;
+}
+
+static inline bool err_check(struct drm_color_lut *sw_lut,
+ struct drm_color_lut *hw_lut, u32 err)
+{
+ return ((abs((long)hw_lut->red - sw_lut->red)) <= err) &&
+ ((abs((long)hw_lut->blue - sw_lut->blue)) <= err) &&
+ ((abs((long)hw_lut->green - sw_lut->green)) <= err);
+}
+
+bool intel_color_lut_equal(struct drm_property_blob *blob1,
+ struct drm_property_blob *blob2,
+ u32 bit_precision)
+{
+ struct drm_color_lut *sw_lut, *hw_lut;
+ int sw_lut_size, hw_lut_size, i;
+ u32 err;
+
+ if (!blob1 && !blob2)
+ return true;
+
+ if (!blob1)
+ return true;
+
+ if (!blob2)
+ return false;
+
+ sw_lut_size = drm_color_lut_size(blob1);
+ hw_lut_size = drm_color_lut_size(blob2);
+
+ if (sw_lut_size != hw_lut_size)
+ return false;
+
+ sw_lut = blob1->data;
+ hw_lut = blob2->data;
+
+ err = 0xffff >> bit_precision;
+
+ for (i = 0; i < sw_lut_size; i++) {
+ if (!err_check(&hw_lut[i], &sw_lut[i], err))
+ return false;
+ }
+
+ return true;
+}
+
void intel_color_init(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
diff --git a/drivers/gpu/drm/i915/intel_color.h b/drivers/gpu/drm/i915/intel_color.h
index 057e8ac..02ea1bc 100644
--- a/drivers/gpu/drm/i915/intel_color.h
+++ b/drivers/gpu/drm/i915/intel_color.h
@@ -6,13 +6,20 @@
#ifndef __INTEL_COLOR_H__
#define __INTEL_COLOR_H__
+#include <linux/types.h>
+
struct intel_crtc_state;
struct intel_crtc;
+struct drm_property_blob;
void intel_color_init(struct intel_crtc *crtc);
int intel_color_check(struct intel_crtc_state *crtc_state);
void intel_color_commit(const struct intel_crtc_state *crtc_state);
void intel_color_load_luts(const struct intel_crtc_state *crtc_state);
void intel_color_get_config(struct intel_crtc_state *crtc_state);
+bool intel_color_lut_equal(struct drm_property_blob *blob1,
+ struct drm_property_blob *blob2,
+ u32 bit_precision);
+int intel_color_get_gamma_bit_precision(struct intel_crtc_state *crtc_state);
#endif /* __INTEL_COLOR_H__ */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3e01028..b3bded6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11570,6 +11570,16 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
drm_rect_width(&state->base.dst),
drm_rect_height(&state->base.dst));
}
+
+ if (IS_CHERRYVIEW(dev_priv))
+ DRM_DEBUG_KMS("cgm_mode:%d gamma_mode:%d gamma_enable:%d csc_enable:%d\n",
+ pipe_config->cgm_mode, pipe_config->gamma_mode, pipe_config->gamma_enable,
+ pipe_config->csc_enable);
+ else
+ DRM_DEBUG_KMS("csc_mode:%d gamma_mode:%d gamma_enable:%d csc_enable:%d\n",
+ pipe_config->csc_mode, pipe_config->gamma_mode, pipe_config->gamma_enable,
+ pipe_config->csc_enable);
+
}
static bool check_digital_port_conflicts(struct drm_atomic_state *state)
@@ -11947,6 +11957,7 @@ static bool fastboot_enabled(struct drm_i915_private *dev_priv)
bool adjust)
{
bool ret = true;
+ u32 bp_gamma = 0;
bool fixup_inherited = adjust &&
(current_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED) &&
!(pipe_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED);
@@ -12098,6 +12109,15 @@ static bool fastboot_enabled(struct drm_i915_private *dev_priv)
} \
} while (0)
+#define PIPE_CONF_CHECK_COLOR_LUT(name, bit_precision) do { \
+ if (!intel_color_lut_equal(current_config->name, \
+ pipe_config->name, bit_precision)) { \
+ pipe_config_err(adjust, __stringify(name), \
+ "hw_state doesn't match sw_state\n"); \
+ ret = false; \
+ } \
+} while (0)
+
#define PIPE_CONF_QUIRK(quirk) \
((current_config->quirks | pipe_config->quirks) & (quirk))
@@ -12193,6 +12213,10 @@ static bool fastboot_enabled(struct drm_i915_private *dev_priv)
PIPE_CONF_CHECK_X(csc_mode);
PIPE_CONF_CHECK_BOOL(gamma_enable);
PIPE_CONF_CHECK_BOOL(csc_enable);
+
+ bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
+ if (!bp_gamma)
+ PIPE_CONF_CHECK_COLOR_LUT(base.gamma_lut, bp_gamma);
}
PIPE_CONF_CHECK_BOOL(double_wide);
@@ -12255,6 +12279,7 @@ static bool fastboot_enabled(struct drm_i915_private *dev_priv)
#undef PIPE_CONF_CHECK_FLAGS
#undef PIPE_CONF_CHECK_CLOCK_FUZZY
#undef PIPE_CONF_QUIRK
+#undef PIPE_CONF_CHECK_COLOR_LUT
return ret;
}
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [v7][PATCH 04/12] drm/i915: Extract i9xx_read_luts()
2019-05-27 13:41 [v7][PATCH 00/12] drm/i915: adding state checker for gamma lut values Swati Sharma
` (2 preceding siblings ...)
2019-05-27 13:41 ` [v7][PATCH 03/12] drm/i915: Add intel_color_lut_equal() to compare hw and sw gamma/degamma lut values Swati Sharma
@ 2019-05-27 13:41 ` Swati Sharma
2019-05-27 17:42 ` kbuild test robot
2019-05-27 17:42 ` [RFC PATCH] drm/i915: i9xx_read_luts() can be static kbuild test robot
2019-05-27 13:41 ` [v7][PATCH 05/12] drm/i915: Extract chv_read_luts() Swati Sharma
` (11 subsequent siblings)
15 siblings, 2 replies; 20+ messages in thread
From: Swati Sharma @ 2019-05-27 13:41 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ankit.k.nautiyal
In this patch, hw gamma blob is created for the legacy
gamma. Also, function intel_color_lut_pack is added to
convert hw value with given bit_precision to lut property val.
v4: -No need to initialize *blob [Jani]
-Removed right shifts [Jani]
-Dropped dev local var [Jani]
v5: -Returned blob instead of assigning it internally withing the
function [Ville]
-Renamed function i9xx_get_color_config() to i9xx_read_luts()
-Renamed i9xx_get_config_internal() to i9xx_read_lut_8() [Ville]
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_color.c | 51 ++++++++++++++++++++++++++++++++++++++
2 files changed, 54 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e97c47f..d8475f2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7178,6 +7178,9 @@ enum {
/* legacy palette */
#define _LGC_PALETTE_A 0x4a000
#define _LGC_PALETTE_B 0x4a800
+#define LGC_PALETTE_RED_MASK REG_GENMASK(23, 16)
+#define LGC_PALETTE_GREEN_MASK REG_GENMASK(15, 8)
+#define LGC_PALETTE_BLUE_MASK REG_GENMASK(7, 0)
#define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)
/* ilk/snb precision palette */
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index e566af5..e8d8167 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -1417,6 +1417,56 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1,
return true;
}
+/* convert hw value with given bit_precision to lut property val */
+static u32 intel_color_lut_pack(u32 val, u32 bit_precision)
+{
+ u32 max = 0xffff >> (16 - bit_precision);
+
+ val = clamp_val(val, 0, max);
+
+ if (bit_precision < 16)
+ val <<= 16 - bit_precision;
+
+ return val;
+}
+
+static struct drm_property_blob *
+i9xx_read_lut_8(struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+ struct drm_property_blob *blob;
+ struct drm_color_lut *blob_data;
+ u32 i, val;
+
+ blob = drm_property_create_blob(&dev_priv->drm,
+ sizeof(struct drm_color_lut) * 256,
+ NULL);
+ if (IS_ERR(blob))
+ return NULL;
+
+ blob_data = blob->data;
+
+ for (i = 0; i < 256; i++) {
+ if (HAS_GMCH(dev_priv))
+ val = I915_READ(PALETTE(pipe, i));
+ else
+ val = I915_READ(LGC_PALETTE(pipe, i));
+
+ blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_RED_MASK, val), 8);
+ blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_GREEN_MASK, val), 8);
+ blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_BLUE_MASK, val), 8);
+ }
+
+ return blob;
+}
+
+void i9xx_read_luts(struct intel_crtc_state *crtc_state)
+{
+ crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
+}
+
void intel_color_init(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -1437,6 +1487,7 @@ void intel_color_init(struct intel_crtc *crtc)
dev_priv->display.color_check = i9xx_color_check;
dev_priv->display.color_commit = i9xx_color_commit;
dev_priv->display.load_luts = i9xx_load_luts;
+ dev_priv->display.read_luts = i9xx_read_luts;
}
} else {
if (INTEL_GEN(dev_priv) >= 11)
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [v7][PATCH 04/12] drm/i915: Extract i9xx_read_luts()
2019-05-27 13:41 ` [v7][PATCH 04/12] drm/i915: Extract i9xx_read_luts() Swati Sharma
@ 2019-05-27 17:42 ` kbuild test robot
2019-05-27 17:42 ` [RFC PATCH] drm/i915: i9xx_read_luts() can be static kbuild test robot
1 sibling, 0 replies; 20+ messages in thread
From: kbuild test robot @ 2019-05-27 17:42 UTC (permalink / raw)
To: Swati Sharma; +Cc: jani.nikula, intel-gfx, ankit.k.nautiyal, kbuild-all
Hi Swati,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on v5.2-rc2 next-20190524]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Swati-Sharma/drm-i915-adding-state-checker-for-gamma-lut-values/20190527-214948
base: git://anongit.freedesktop.org/drm-intel for-linux-next
reproduce:
# apt-get install sparse
# sparse version: v0.6.1-rc1-7-g2b96cd8-dirty
make ARCH=x86_64 allmodconfig
make C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__'
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>
sparse warnings: (new ones prefixed by >>)
Please review and possibly fold the followup patch.
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* [RFC PATCH] drm/i915: i9xx_read_luts() can be static
2019-05-27 13:41 ` [v7][PATCH 04/12] drm/i915: Extract i9xx_read_luts() Swati Sharma
2019-05-27 17:42 ` kbuild test robot
@ 2019-05-27 17:42 ` kbuild test robot
1 sibling, 0 replies; 20+ messages in thread
From: kbuild test robot @ 2019-05-27 17:42 UTC (permalink / raw)
To: Swati Sharma; +Cc: jani.nikula, intel-gfx, ankit.k.nautiyal, kbuild-all
Fixes: 14dcd98a43c8 ("drm/i915: Extract i9xx_read_luts()")
Signed-off-by: kbuild test robot <lkp@intel.com>
---
intel_color.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index e8d8167..bf92365 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -1462,7 +1462,7 @@ i9xx_read_lut_8(struct intel_crtc_state *crtc_state)
return blob;
}
-void i9xx_read_luts(struct intel_crtc_state *crtc_state)
+static void i9xx_read_luts(struct intel_crtc_state *crtc_state)
{
crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
}
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^ permalink raw reply related [flat|nested] 20+ messages in thread
* [v7][PATCH 05/12] drm/i915: Extract chv_read_luts()
2019-05-27 13:41 [v7][PATCH 00/12] drm/i915: adding state checker for gamma lut values Swati Sharma
` (3 preceding siblings ...)
2019-05-27 13:41 ` [v7][PATCH 04/12] drm/i915: Extract i9xx_read_luts() Swati Sharma
@ 2019-05-27 13:41 ` Swati Sharma
2019-05-27 13:41 ` [v7][PATCH 06/12] drm/i915: Extract i965_read_luts() Swati Sharma
` (10 subsequent siblings)
15 siblings, 0 replies; 20+ messages in thread
From: Swati Sharma @ 2019-05-27 13:41 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ankit.k.nautiyal
In this patch, hw gamma and degamma blob is created for
cherryview.
v4: -No need to initialize *blob [Jani]
-Removed right shifts [Jani]
-Dropped dev local var [Jani]
v5: -Returned blob instead of assigning it internally within the
function [Ville]
-Renamed function cherryview_get_color_config() to chv_read_luts()
-Renamed cherryview_get_gamma_config() to chv_read_cgm_gamma_lut() [Ville]
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_color.c | 40 ++++++++++++++++++++++++++++++++++++++
2 files changed, 43 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d8475f2..b58c66d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10160,6 +10160,9 @@ enum skl_power_gate {
#define CGM_PIPE_MODE_GAMMA (1 << 2)
#define CGM_PIPE_MODE_CSC (1 << 1)
#define CGM_PIPE_MODE_DEGAMMA (1 << 0)
+#define CGM_PIPE_GAMMA_RED_MASK REG_GENMASK(9, 0)
+#define CGM_PIPE_GAMMA_GREEN_MASK REG_GENMASK(25, 16)
+#define CGM_PIPE_GAMMA_BLUE_MASK REG_GENMASK(9, 0)
#define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900)
#define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904)
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index e8d8167..9d759e1 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -1467,6 +1467,45 @@ void i9xx_read_luts(struct intel_crtc_state *crtc_state)
crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
}
+static struct drm_property_blob *
+chv_read_cgm_gamma_lut(struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ u32 i, val, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+ enum pipe pipe = crtc->pipe;
+ struct drm_property_blob *blob;
+ struct drm_color_lut *blob_data;
+
+ blob = drm_property_create_blob(&dev_priv->drm,
+ sizeof(struct drm_color_lut) * lut_size,
+ NULL);
+ if (IS_ERR(blob))
+ return NULL;
+
+ blob_data = blob->data;
+
+ for (i = 0; i < lut_size; i++) {
+ val = I915_READ(CGM_PIPE_GAMMA(pipe, i, 0));
+ blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_GREEN_MASK, val), 10);
+ blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_BLUE_MASK, val), 10);
+
+ val = I915_READ(CGM_PIPE_GAMMA(pipe, i, 1));
+ blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_RED_MASK, val), 10);
+ }
+
+ return blob;
+}
+
+static void chv_read_luts(struct intel_crtc_state *crtc_state)
+{
+ if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
+ crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
+ else
+ crtc_state->base.gamma_lut = chv_read_cgm_gamma_lut(crtc_state);
+
+}
+
void intel_color_init(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -1479,6 +1518,7 @@ void intel_color_init(struct intel_crtc *crtc)
dev_priv->display.color_check = chv_color_check;
dev_priv->display.color_commit = i9xx_color_commit;
dev_priv->display.load_luts = chv_load_luts;
+ dev_priv->display.read_luts = chv_read_luts;
} else if (INTEL_GEN(dev_priv) >= 4) {
dev_priv->display.color_check = i9xx_color_check;
dev_priv->display.color_commit = i9xx_color_commit;
--
1.9.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [v7][PATCH 06/12] drm/i915: Extract i965_read_luts()
2019-05-27 13:41 [v7][PATCH 00/12] drm/i915: adding state checker for gamma lut values Swati Sharma
` (4 preceding siblings ...)
2019-05-27 13:41 ` [v7][PATCH 05/12] drm/i915: Extract chv_read_luts() Swati Sharma
@ 2019-05-27 13:41 ` Swati Sharma
2019-05-27 13:41 ` [v7][PATCH 07/12] drm/i915: Extract icl_read_luts() Swati Sharma
` (9 subsequent siblings)
15 siblings, 0 replies; 20+ messages in thread
From: Swati Sharma @ 2019-05-27 13:41 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ankit.k.nautiyal
In this patch, hw gamma blob is created for i965.
v4: -No need to initialize *blob [Jani]
-Removed right shifts [Jani]
-Dropped dev local var [Jani]
v5: -Returned blob instead of assigning it internally
within the function [Ville]
-Renamed i965_get_color_config() to i965_read_lut() [Ville]
-Renamed i965_get_gamma_config_10p6() to i965_read_gamma_lut_10p6() [Ville]
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_color.c | 39 ++++++++++++++++++++++++++++++++++++++
2 files changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b58c66d..7988fa5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3584,6 +3584,9 @@ enum i915_power_well_id {
#define _PALETTE_A 0xa000
#define _PALETTE_B 0xa800
#define _CHV_PALETTE_C 0xc000
+#define PALETTE_RED_MASK REG_GENMASK(23, 16)
+#define PALETTE_GREEN_MASK REG_GENMASK(15, 8)
+#define PALETTE_BLUE_MASK REG_GENMASK(7, 0)
#define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
_PICK((pipe), _PALETTE_A, \
_PALETTE_B, _CHV_PALETTE_C) + \
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 9d759e1..0b91e22 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -1506,6 +1506,44 @@ static void chv_read_luts(struct intel_crtc_state *crtc_state)
}
+static struct drm_property_blob *
+i965_read_gamma_lut_10p6(struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ u32 i, val1, val2, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+ enum pipe pipe = crtc->pipe;
+ struct drm_property_blob *blob;
+ struct drm_color_lut *blob_data;
+
+ blob = drm_property_create_blob(&dev_priv->drm,
+ sizeof(struct drm_color_lut) * lut_size,
+ NULL);
+ if (IS_ERR(blob))
+ return NULL;
+
+ blob_data = blob->data;
+
+ for (i = 0; i < lut_size - 1; i++) {
+ val1 = I915_READ(PALETTE(pipe, 2 * i + 0));
+ val2 = I915_READ(PALETTE(pipe, 2 * i + 1));
+
+ blob_data[i].red = REG_FIELD_GET(PALETTE_RED_MASK, val1) << 8 | REG_FIELD_GET(PALETTE_RED_MASK, val2);
+ blob_data[i].green = REG_FIELD_GET(PALETTE_GREEN_MASK, val1) << 8 | REG_FIELD_GET(PALETTE_GREEN_MASK, val2);
+ blob_data[i].blue = REG_FIELD_GET(PALETTE_BLUE_MASK, val1) << 8 | REG_FIELD_GET(PALETTE_BLUE_MASK, val2) ;
+ }
+
+ return blob;
+}
+
+static void i965_read_luts(struct intel_crtc_state *crtc_state)
+{
+ if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
+ crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
+ else
+ crtc_state->base.gamma_lut = i965_read_gamma_lut_10p6(crtc_state);
+}
+
void intel_color_init(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -1523,6 +1561,7 @@ void intel_color_init(struct intel_crtc *crtc)
dev_priv->display.color_check = i9xx_color_check;
dev_priv->display.color_commit = i9xx_color_commit;
dev_priv->display.load_luts = i965_load_luts;
+ dev_priv->display.read_luts = i965_read_luts;
} else {
dev_priv->display.color_check = i9xx_color_check;
dev_priv->display.color_commit = i9xx_color_commit;
--
1.9.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [v7][PATCH 07/12] drm/i915: Extract icl_read_luts()
2019-05-27 13:41 [v7][PATCH 00/12] drm/i915: adding state checker for gamma lut values Swati Sharma
` (5 preceding siblings ...)
2019-05-27 13:41 ` [v7][PATCH 06/12] drm/i915: Extract i965_read_luts() Swati Sharma
@ 2019-05-27 13:41 ` Swati Sharma
2019-05-27 13:41 ` [v7][PATCH 08/12] drm/i915: Extract glk_read_luts() Swati Sharma
` (8 subsequent siblings)
15 siblings, 0 replies; 20+ messages in thread
From: Swati Sharma @ 2019-05-27 13:41 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ankit.k.nautiyal
In this patch, gamma hw blobs are created for ICL.
v4: -No need to initialize *blob [Jani]
-Removed right shifts [Jani]
-Dropped dev local var [Jani]
v5: -Returned blob instead of assigning it internally within the
function [Ville]
-Renamed icl_get_color_config() to icl_read_luts() [Ville]
-Renamed bdw_get_gamma_config() to bdw_read_lut_10() [Ville]
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_color.c | 49 +++++++++++++++++++++++++++++++++++++-
2 files changed, 51 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7988fa5..249296b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10124,6 +10124,9 @@ enum skl_power_gate {
#define _PAL_PREC_DATA_A 0x4A404
#define _PAL_PREC_DATA_B 0x4AC04
#define _PAL_PREC_DATA_C 0x4B404
+#define PREC_PAL_DATA_RED_MASK REG_GENMASK(29, 20)
+#define PREC_PAL_DATA_GREEN_MASK REG_GENMASK(19, 10)
+#define PREC_PAL_DATA_BLUE_MASK REG_GENMASK(9, 0)
#define _PAL_PREC_GC_MAX_A 0x4A410
#define _PAL_PREC_GC_MAX_B 0x4AC10
#define _PAL_PREC_GC_MAX_C 0x4B410
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 0b91e22..fa8e895 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -1544,6 +1544,51 @@ static void i965_read_luts(struct intel_crtc_state *crtc_state)
crtc_state->base.gamma_lut = i965_read_gamma_lut_10p6(crtc_state);
}
+static struct drm_property_blob *
+bdw_read_lut_10(struct intel_crtc_state *crtc_state,
+ u32 prec_index)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ int hw_lut_size = ivb_lut_10_size(prec_index);
+ enum pipe pipe = crtc->pipe;
+ struct drm_property_blob *blob;
+ struct drm_color_lut *blob_data;
+ u32 i, val;
+
+ I915_WRITE(PREC_PAL_INDEX(pipe), prec_index |
+ PAL_PREC_AUTO_INCREMENT);
+
+ blob = drm_property_create_blob(&dev_priv->drm,
+ sizeof(struct drm_color_lut) * hw_lut_size,
+ NULL);
+ if (IS_ERR(blob))
+ return NULL;
+
+ blob_data = blob->data;
+
+ for (i = 0; i < hw_lut_size; i++) {
+ val = I915_READ(PREC_PAL_DATA(pipe));
+
+ blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(PREC_PAL_DATA_RED_MASK, val), 10);
+ blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(PREC_PAL_DATA_GREEN_MASK, val), 10);
+ blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(PREC_PAL_DATA_BLUE_MASK, val), 10);
+ }
+
+ I915_WRITE(PREC_PAL_INDEX(pipe), 0);
+
+ return blob;
+}
+
+static void icl_read_luts(struct intel_crtc_state *crtc_state)
+{
+ if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) ==
+ GAMMA_MODE_MODE_8BIT)
+ crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
+ else
+ crtc_state->base.gamma_lut = bdw_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
+}
+
void intel_color_init(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -1585,8 +1630,10 @@ void intel_color_init(struct intel_crtc *crtc)
else
dev_priv->display.color_commit = ilk_color_commit;
- if (INTEL_GEN(dev_priv) >= 11)
+ if (INTEL_GEN(dev_priv) >= 11) {
dev_priv->display.load_luts = icl_load_luts;
+ dev_priv->display.read_luts = icl_read_luts;
+ }
else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
dev_priv->display.load_luts = glk_load_luts;
else if (INTEL_GEN(dev_priv) >= 8)
--
1.9.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [v7][PATCH 08/12] drm/i915: Extract glk_read_luts()
2019-05-27 13:41 [v7][PATCH 00/12] drm/i915: adding state checker for gamma lut values Swati Sharma
` (6 preceding siblings ...)
2019-05-27 13:41 ` [v7][PATCH 07/12] drm/i915: Extract icl_read_luts() Swati Sharma
@ 2019-05-27 13:41 ` Swati Sharma
2019-05-27 13:41 ` [v7][PATCH 09/12] drm/i915: Extract bdw_read_luts() Swati Sharma
` (7 subsequent siblings)
15 siblings, 0 replies; 20+ messages in thread
From: Swati Sharma @ 2019-05-27 13:41 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ankit.k.nautiyal
In this patch, gamma and degamma hw blobs are created for GLK.
v4: -No need to initialize *blob [Jani]
-Removed right shifts [Jani]
-Dropped dev local var [Jani]
v5: -Returned blob instead of assigning it internally within the
function [Ville]
-Renamed glk_get_color_config() to glk_read_luts() [Ville]
-Added degamma validation [Ville]
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
drivers/gpu/drm/i915/intel_color.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index fa8e895..4e58cd1 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -1589,6 +1589,14 @@ static void icl_read_luts(struct intel_crtc_state *crtc_state)
crtc_state->base.gamma_lut = bdw_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
}
+static void glk_read_luts(struct intel_crtc_state *crtc_state)
+{
+ if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
+ crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
+ else
+ crtc_state->base.gamma_lut = bdw_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
+}
+
void intel_color_init(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -1633,9 +1641,10 @@ void intel_color_init(struct intel_crtc *crtc)
if (INTEL_GEN(dev_priv) >= 11) {
dev_priv->display.load_luts = icl_load_luts;
dev_priv->display.read_luts = icl_read_luts;
- }
- else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
+ } else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
dev_priv->display.load_luts = glk_load_luts;
+ dev_priv->display.read_luts = glk_read_luts;
+ }
else if (INTEL_GEN(dev_priv) >= 8)
dev_priv->display.load_luts = bdw_load_luts;
else if (INTEL_GEN(dev_priv) >= 7)
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [v7][PATCH 09/12] drm/i915: Extract bdw_read_luts()
2019-05-27 13:41 [v7][PATCH 00/12] drm/i915: adding state checker for gamma lut values Swati Sharma
` (7 preceding siblings ...)
2019-05-27 13:41 ` [v7][PATCH 08/12] drm/i915: Extract glk_read_luts() Swati Sharma
@ 2019-05-27 13:41 ` Swati Sharma
2019-05-27 13:42 ` [v7][PATCH 10/12] drm/i915: Extract ivb_read_luts() Swati Sharma
` (6 subsequent siblings)
15 siblings, 0 replies; 20+ messages in thread
From: Swati Sharma @ 2019-05-27 13:41 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ankit.k.nautiyal
In this patch, gamma and degamma hw blobs are created for BDW.
v4: -No need to initialize *blob [Jani]
-Removed right shifts [Jani]
-Dropped dev local var [Jani]
v5: -Returned blob instead of assigning it internally within the
function [Ville]
-Renamed bdw_get_color_config() to bdw_read_luts() [Ville]
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
drivers/gpu/drm/i915/intel_color.c | 15 +++++++++++++--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 4e58cd1..ce6dc5e 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -1597,6 +1597,16 @@ static void glk_read_luts(struct intel_crtc_state *crtc_state)
crtc_state->base.gamma_lut = bdw_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
}
+static void bdw_read_luts(struct intel_crtc_state *crtc_state)
+{
+ if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
+ crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
+ else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
+ crtc_state->base.gamma_lut = bdw_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(512));
+ else
+ crtc_state->base.gamma_lut = bdw_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
+}
+
void intel_color_init(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -1644,9 +1654,10 @@ void intel_color_init(struct intel_crtc *crtc)
} else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
dev_priv->display.load_luts = glk_load_luts;
dev_priv->display.read_luts = glk_read_luts;
- }
- else if (INTEL_GEN(dev_priv) >= 8)
+ } else if (INTEL_GEN(dev_priv) >= 8) {
dev_priv->display.load_luts = bdw_load_luts;
+ dev_priv->display.read_luts = bdw_read_luts;
+ }
else if (INTEL_GEN(dev_priv) >= 7)
dev_priv->display.load_luts = ivb_load_luts;
else
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [v7][PATCH 10/12] drm/i915: Extract ivb_read_luts()
2019-05-27 13:41 [v7][PATCH 00/12] drm/i915: adding state checker for gamma lut values Swati Sharma
` (8 preceding siblings ...)
2019-05-27 13:41 ` [v7][PATCH 09/12] drm/i915: Extract bdw_read_luts() Swati Sharma
@ 2019-05-27 13:42 ` Swati Sharma
2019-05-27 13:42 ` [v7][PATCH 11/12] drm/i915: Extract ilk_read_luts() Swati Sharma
` (5 subsequent siblings)
15 siblings, 0 replies; 20+ messages in thread
From: Swati Sharma @ 2019-05-27 13:42 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ankit.k.nautiyal
In this patch, gamma and degamma hw blobs are created for IVB.
v4: -No need to initialize *blob [Jani]
-Removed right shifts [Jani]
-Dropped dev local var [Jani]
v5: -Returned blob instead of assigning it internally within the
function [Ville]
-Renamed ivb_get_color_config() to ivb_read_luts() [Ville]
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
drivers/gpu/drm/i915/intel_color.c | 50 ++++++++++++++++++++++++++++++++++++--
1 file changed, 48 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index ce6dc5e..4c00215 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -1607,6 +1607,51 @@ static void bdw_read_luts(struct intel_crtc_state *crtc_state)
crtc_state->base.gamma_lut = bdw_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
}
+static struct drm_property_blob *
+ivb_read_lut_10(struct intel_crtc_state *crtc_state,
+ u32 prec_index)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ int hw_lut_size = ivb_lut_10_size(prec_index);
+ enum pipe pipe = crtc->pipe;
+ struct drm_property_blob *blob;
+ struct drm_color_lut *blob_data;
+ u32 i, val;
+
+ blob = drm_property_create_blob(&dev_priv->drm,
+ sizeof(struct drm_color_lut) * hw_lut_size,
+ NULL);
+ if (IS_ERR(blob))
+ return NULL;
+
+ blob_data = blob->data;
+
+ for (i = 0; i < hw_lut_size; i++) {
+ I915_WRITE(PREC_PAL_INDEX(pipe), prec_index++);
+ val = I915_READ(PREC_PAL_DATA(pipe));
+
+ blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(PREC_PAL_DATA_RED_MASK, val), 10);
+ blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(PREC_PAL_DATA_GREEN_MASK, val), 10);
+ blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(PREC_PAL_DATA_BLUE_MASK, val), 10);
+ }
+
+ I915_WRITE(PREC_PAL_INDEX(pipe), 0);
+
+ return blob;
+}
+
+static void ivb_read_luts(struct intel_crtc_state *crtc_state)
+{
+ if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
+ crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
+ else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
+ crtc_state->base.gamma_lut = ivb_read_lut_10(crtc_state, PAL_PREC_SPLIT_MODE | PAL_PREC_INDEX_VALUE(512));
+ else
+ crtc_state->base.gamma_lut = ivb_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
+
+}
+
void intel_color_init(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -1657,9 +1702,10 @@ void intel_color_init(struct intel_crtc *crtc)
} else if (INTEL_GEN(dev_priv) >= 8) {
dev_priv->display.load_luts = bdw_load_luts;
dev_priv->display.read_luts = bdw_read_luts;
- }
- else if (INTEL_GEN(dev_priv) >= 7)
+ } else if (INTEL_GEN(dev_priv) >= 7) {
dev_priv->display.load_luts = ivb_load_luts;
+ dev_priv->display.read_luts = ivb_read_luts;
+ }
else
dev_priv->display.load_luts = ilk_load_luts;
}
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [v7][PATCH 11/12] drm/i915: Extract ilk_read_luts()
2019-05-27 13:41 [v7][PATCH 00/12] drm/i915: adding state checker for gamma lut values Swati Sharma
` (9 preceding siblings ...)
2019-05-27 13:42 ` [v7][PATCH 10/12] drm/i915: Extract ivb_read_luts() Swati Sharma
@ 2019-05-27 13:42 ` Swati Sharma
2019-05-27 13:42 ` [v7][PATCH 12/12] FOR_TESTING_ONLY: Print rgb values of hw and sw blobs Swati Sharma
` (4 subsequent siblings)
15 siblings, 0 replies; 20+ messages in thread
From: Swati Sharma @ 2019-05-27 13:42 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ankit.k.nautiyal
In this patch, hw gamma blob is created for ILK.
v4: -No need to initialize *blob [Jani]
-Removed right shifts [Jani]
-Dropped dev local var [Jani]
v5: -Returned blob instead of assigning it internally within the
function [Ville]
-Renamed ilk_get_color_config() to ilk_read_luts() [Ville]
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_color.c | 42 ++++++++++++++++++++++++++++++++++++--
2 files changed, 43 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 249296b..d5ff323 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7189,6 +7189,9 @@ enum {
/* ilk/snb precision palette */
#define _PREC_PALETTE_A 0x4b000
#define _PREC_PALETTE_B 0x4c000
+#define PREC_PALETTE_RED_MASK REG_GENMASK(29, 20)
+#define PREC_PALETTE_GREEN_MASK REG_GENMASK(19, 10)
+#define PREC_PALETTE_BLUE_MASK REG_GENMASK(9, 0)
#define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4)
#define _PREC_PIPEAGCMAX 0x4d000
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 4c00215..061bdbf 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -1652,6 +1652,43 @@ static void ivb_read_luts(struct intel_crtc_state *crtc_state)
}
+static struct drm_property_blob *
+ilk_read_gamma_lut(struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ u32 i, val, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+ enum pipe pipe = crtc->pipe;
+ struct drm_property_blob *blob;
+ struct drm_color_lut *blob_data;
+
+ blob = drm_property_create_blob(&dev_priv->drm,
+ sizeof(struct drm_color_lut) * lut_size,
+ NULL);
+ if (IS_ERR(blob))
+ return NULL;
+
+ blob_data = blob->data;
+
+ for (i = 0; i < lut_size - 1; i++) {
+ val = I915_READ(PREC_PALETTE(pipe, i));
+
+ blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_RED_MASK, val), 10);
+ blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_GREEN_MASK, val), 10);
+ blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_BLUE_MASK, val), 10);
+ }
+
+ return blob;
+}
+
+static void ilk_read_luts(struct intel_crtc_state *crtc_state)
+{
+ if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
+ crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
+ else
+ crtc_state->base.gamma_lut = ilk_read_gamma_lut(crtc_state);
+}
+
void intel_color_init(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -1705,9 +1742,10 @@ void intel_color_init(struct intel_crtc *crtc)
} else if (INTEL_GEN(dev_priv) >= 7) {
dev_priv->display.load_luts = ivb_load_luts;
dev_priv->display.read_luts = ivb_read_luts;
- }
- else
+ } else {
dev_priv->display.load_luts = ilk_load_luts;
+ dev_priv->display.read_luts = ilk_read_luts;
+ }
}
drm_crtc_enable_color_mgmt(&crtc->base,
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [v7][PATCH 12/12] FOR_TESTING_ONLY: Print rgb values of hw and sw blobs
2019-05-27 13:41 [v7][PATCH 00/12] drm/i915: adding state checker for gamma lut values Swati Sharma
` (10 preceding siblings ...)
2019-05-27 13:42 ` [v7][PATCH 11/12] drm/i915: Extract ilk_read_luts() Swati Sharma
@ 2019-05-27 13:42 ` Swati Sharma
2019-05-27 14:00 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: adding state checker for gamma lut values (rev10) Patchwork
` (3 subsequent siblings)
15 siblings, 0 replies; 20+ messages in thread
From: Swati Sharma @ 2019-05-27 13:42 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ankit.k.nautiyal
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
drivers/gpu/drm/i915/intel_color.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 061bdbf..31e5a44 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -1376,6 +1376,8 @@ int intel_color_get_gamma_bit_precision(struct intel_crtc_state *crtc_state)
static inline bool err_check(struct drm_color_lut *sw_lut,
struct drm_color_lut *hw_lut, u32 err)
{
+ DRM_DEBUG_KMS("hw_lut->red=0x%x sw_lut->red=0x%x hw_lut->blue=0x%x sw_lut->blue=0x%x hw_lut->green=0x%x sw_lut->green=0x%x", hw_lut->red, sw_lut->red, hw_lut->blue, sw_lut->blue, hw_lut->green, sw_lut->green);
+
return ((abs((long)hw_lut->red - sw_lut->red)) <= err) &&
((abs((long)hw_lut->blue - sw_lut->blue)) <= err) &&
((abs((long)hw_lut->green - sw_lut->green)) <= err);
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915: adding state checker for gamma lut values (rev10)
2019-05-27 13:41 [v7][PATCH 00/12] drm/i915: adding state checker for gamma lut values Swati Sharma
` (11 preceding siblings ...)
2019-05-27 13:42 ` [v7][PATCH 12/12] FOR_TESTING_ONLY: Print rgb values of hw and sw blobs Swati Sharma
@ 2019-05-27 14:00 ` Patchwork
2019-05-27 14:05 ` ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
15 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2019-05-27 14:00 UTC (permalink / raw)
To: Swati Sharma; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: adding state checker for gamma lut values (rev10)
URL : https://patchwork.freedesktop.org/series/58039/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d7ec7acfa25a drm/i915: Introduce vfunc read_luts() to create hw lut
729d4500e37f drm/i915: Enable intel_color_get_config()
118f9a116296 drm/i915: Add intel_color_lut_equal() to compare hw and sw gamma/degamma lut values
-:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#10:
-Corrected smatch warn "variable dereferenced before check" [Dan Carpenter]
-:37: ERROR:SWITCH_CASE_INDENT_LEVEL: switch and case should be at the same indent
#37: FILE: drivers/gpu/drm/i915/intel_color.c:1259:
+ switch (crtc_state->gamma_mode) {
+ case GAMMA_MODE_MODE_8BIT:
[...]
+ case GAMMA_MODE_MODE_10BIT:
[...]
+ default:
-:64: ERROR:SWITCH_CASE_INDENT_LEVEL: switch and case should be at the same indent
#64: FILE: drivers/gpu/drm/i915/intel_color.c:1286:
+ switch (crtc_state->gamma_mode) {
+ case GAMMA_MODE_MODE_8BIT:
[...]
+ case GAMMA_MODE_MODE_10BIT:
[...]
+ default:
-:83: ERROR:SWITCH_CASE_INDENT_LEVEL: switch and case should be at the same indent
#83: FILE: drivers/gpu/drm/i915/intel_color.c:1305:
+ switch (crtc_state->gamma_mode) {
+ case GAMMA_MODE_MODE_8BIT:
[...]
+ case GAMMA_MODE_MODE_SPLIT:
+ case GAMMA_MODE_MODE_10BIT:
[...]
+ default:
-:103: ERROR:SWITCH_CASE_INDENT_LEVEL: switch and case should be at the same indent
#103: FILE: drivers/gpu/drm/i915/intel_color.c:1325:
+ switch (crtc_state->gamma_mode) {
+ case GAMMA_MODE_MODE_8BIT:
[...]
+ case GAMMA_MODE_MODE_10BIT:
[...]
+ default:
-:119: ERROR:SWITCH_CASE_INDENT_LEVEL: switch and case should be at the same indent
#119: FILE: drivers/gpu/drm/i915/intel_color.c:1341:
+ switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
+ case GAMMA_MODE_MODE_8BIT:
[...]
+ case GAMMA_MODE_MODE_10BIT:
[...]
+ default:
-:155: ERROR:CODE_INDENT: code indent should use tabs where possible
#155: FILE: drivers/gpu/drm/i915/intel_color.c:1377:
+^I struct drm_color_lut *hw_lut, u32 err)$
-:155: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#155: FILE: drivers/gpu/drm/i915/intel_color.c:1377:
+static inline bool err_check(struct drm_color_lut *sw_lut,
+ struct drm_color_lut *hw_lut, u32 err)
-:157: WARNING:TABSTOP: Statements should start on a tabstop
#157: FILE: drivers/gpu/drm/i915/intel_color.c:1379:
+ return ((abs((long)hw_lut->red - sw_lut->red)) <= err) &&
-:158: ERROR:CODE_INDENT: code indent should use tabs where possible
#158: FILE: drivers/gpu/drm/i915/intel_color.c:1380:
+^I ((abs((long)hw_lut->blue - sw_lut->blue)) <= err) &&$
-:159: ERROR:CODE_INDENT: code indent should use tabs where possible
#159: FILE: drivers/gpu/drm/i915/intel_color.c:1381:
+^I ((abs((long)hw_lut->green - sw_lut->green)) <= err);$
-:190: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional statements (8, 17)
#190: FILE: drivers/gpu/drm/i915/intel_color.c:1412:
+ for (i = 0; i < sw_lut_size; i++) {
+ if (!err_check(&hw_lut[i], &sw_lut[i], err))
-:191: WARNING:TABSTOP: Statements should start on a tabstop
#191: FILE: drivers/gpu/drm/i915/intel_color.c:1413:
+ if (!err_check(&hw_lut[i], &sw_lut[i], err))
-:237: WARNING:LONG_LINE: line over 100 characters
#237: FILE: drivers/gpu/drm/i915/intel_display.c:11895:
+ pipe_config->cgm_mode, pipe_config->gamma_mode, pipe_config->gamma_enable,
-:237: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#237: FILE: drivers/gpu/drm/i915/intel_display.c:11895:
+ DRM_DEBUG_KMS("cgm_mode:%d gamma_mode:%d gamma_enable:%d csc_enable:%d\n",
+ pipe_config->cgm_mode, pipe_config->gamma_mode, pipe_config->gamma_enable,
-:241: WARNING:LONG_LINE: line over 100 characters
#241: FILE: drivers/gpu/drm/i915/intel_display.c:11899:
+ pipe_config->csc_mode, pipe_config->gamma_mode, pipe_config->gamma_enable,
-:241: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#241: FILE: drivers/gpu/drm/i915/intel_display.c:11899:
+ DRM_DEBUG_KMS("csc_mode:%d gamma_mode:%d gamma_enable:%d csc_enable:%d\n",
+ pipe_config->csc_mode, pipe_config->gamma_mode, pipe_config->gamma_enable,
-:259: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible side-effects?
#259: FILE: drivers/gpu/drm/i915/intel_display.c:12431:
+#define PIPE_CONF_CHECK_COLOR_LUT(name, bit_precision) do { \
+ if (!intel_color_lut_equal(current_config->name, \
+ pipe_config->name, bit_precision)) { \
+ pipe_config_err(adjust, __stringify(name), \
+ "hw_state doesn't match sw_state\n"); \
+ ret = false; \
+ } \
+} while (0)
-:259: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'name' may be better as '(name)' to avoid precedence issues
#259: FILE: drivers/gpu/drm/i915/intel_display.c:12431:
+#define PIPE_CONF_CHECK_COLOR_LUT(name, bit_precision) do { \
+ if (!intel_color_lut_equal(current_config->name, \
+ pipe_config->name, bit_precision)) { \
+ pipe_config_err(adjust, __stringify(name), \
+ "hw_state doesn't match sw_state\n"); \
+ ret = false; \
+ } \
+} while (0)
total: 8 errors, 6 warnings, 5 checks, 247 lines checked
383d2598835a drm/i915: Extract i9xx_read_luts()
-:13: WARNING:TYPO_SPELLING: 'withing' may be misspelled - perhaps 'within'?
#13:
v5: -Returned blob instead of assigning it internally withing the
-:79: WARNING:LONG_LINE: line over 100 characters
#79: FILE: drivers/gpu/drm/i915/intel_color.c:1457:
+ blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_RED_MASK, val), 8);
-:80: WARNING:LONG_LINE: line over 100 characters
#80: FILE: drivers/gpu/drm/i915/intel_color.c:1458:
+ blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_GREEN_MASK, val), 8);
-:81: WARNING:LONG_LINE: line over 100 characters
#81: FILE: drivers/gpu/drm/i915/intel_color.c:1459:
+ blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_BLUE_MASK, val), 8);
-:89: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#89: FILE: drivers/gpu/drm/i915/intel_color.c:1467:
+ crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);$
total: 0 errors, 5 warnings, 0 checks, 72 lines checked
bf2b1d9e58da drm/i915: Extract chv_read_luts()
-:15: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#15:
-Renamed cherryview_get_gamma_config() to chv_read_cgm_gamma_lut() [Ville]
-:61: WARNING:LONG_LINE: line over 100 characters
#61: FILE: drivers/gpu/drm/i915/intel_color.c:1490:
+ blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_GREEN_MASK, val), 10);
-:62: WARNING:LONG_LINE: line over 100 characters
#62: FILE: drivers/gpu/drm/i915/intel_color.c:1491:
+ blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_BLUE_MASK, val), 10);
-:65: WARNING:LONG_LINE: line over 100 characters
#65: FILE: drivers/gpu/drm/i915/intel_color.c:1494:
+ blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_RED_MASK, val), 10);
-:78: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#78: FILE: drivers/gpu/drm/i915/intel_color.c:1507:
+
+}
total: 0 errors, 4 warnings, 1 checks, 61 lines checked
5fc9737ac9e0 drm/i915: Extract i965_read_luts()
-:14: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#14:
-Renamed i965_get_gamma_config_10p6() to i965_read_gamma_lut_10p6() [Ville]
-:62: WARNING:LONG_LINE: line over 100 characters
#62: FILE: drivers/gpu/drm/i915/intel_color.c:1531:
+ blob_data[i].red = REG_FIELD_GET(PALETTE_RED_MASK, val1) << 8 | REG_FIELD_GET(PALETTE_RED_MASK, val2);
-:63: WARNING:LONG_LINE: line over 100 characters
#63: FILE: drivers/gpu/drm/i915/intel_color.c:1532:
+ blob_data[i].green = REG_FIELD_GET(PALETTE_GREEN_MASK, val1) << 8 | REG_FIELD_GET(PALETTE_GREEN_MASK, val2);
-:64: WARNING:LONG_LINE: line over 100 characters
#64: FILE: drivers/gpu/drm/i915/intel_color.c:1533:
+ blob_data[i].blue = REG_FIELD_GET(PALETTE_BLUE_MASK, val1) << 8 | REG_FIELD_GET(PALETTE_BLUE_MASK, val2) ;
-:64: WARNING:SPACING: space prohibited before semicolon
#64: FILE: drivers/gpu/drm/i915/intel_color.c:1533:
+ blob_data[i].blue = REG_FIELD_GET(PALETTE_BLUE_MASK, val1) << 8 | REG_FIELD_GET(PALETTE_BLUE_MASK, val2) ;
total: 0 errors, 5 warnings, 0 checks, 60 lines checked
8d64f5ac9f48 drm/i915: Extract icl_read_luts()
-:42: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#42: FILE: drivers/gpu/drm/i915/intel_color.c:1549:
+bdw_read_lut_10(struct intel_crtc_state *crtc_state,
+ u32 prec_index)
-:66: WARNING:LONG_LINE: line over 100 characters
#66: FILE: drivers/gpu/drm/i915/intel_color.c:1573:
+ blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(PREC_PAL_DATA_RED_MASK, val), 10);
-:67: WARNING:LONG_LINE: line over 100 characters
#67: FILE: drivers/gpu/drm/i915/intel_color.c:1574:
+ blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(PREC_PAL_DATA_GREEN_MASK, val), 10);
-:68: WARNING:LONG_LINE: line over 100 characters
#68: FILE: drivers/gpu/drm/i915/intel_color.c:1575:
+ blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(PREC_PAL_DATA_BLUE_MASK, val), 10);
-:93: CHECK:BRACES: braces {} should be used on all arms of this statement
#93: FILE: drivers/gpu/drm/i915/intel_color.c:1633:
+ if (INTEL_GEN(dev_priv) >= 11) {
[...]
else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
[...]
total: 0 errors, 3 warnings, 2 checks, 71 lines checked
02d08e6b269c drm/i915: Extract glk_read_luts()
cff18dde61e5 drm/i915: Extract bdw_read_luts()
94bf4f217515 drm/i915: Extract ivb_read_luts()
-:27: ERROR:CODE_INDENT: code indent should use tabs where possible
#27: FILE: drivers/gpu/drm/i915/intel_color.c:1612:
+^I u32 prec_index)$
-:27: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#27: FILE: drivers/gpu/drm/i915/intel_color.c:1612:
+ivb_read_lut_10(struct intel_crtc_state *crtc_state,
+ u32 prec_index)
-:49: WARNING:LONG_LINE: line over 100 characters
#49: FILE: drivers/gpu/drm/i915/intel_color.c:1634:
+ blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(PREC_PAL_DATA_RED_MASK, val), 10);
-:50: WARNING:LONG_LINE: line over 100 characters
#50: FILE: drivers/gpu/drm/i915/intel_color.c:1635:
+ blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(PREC_PAL_DATA_GREEN_MASK, val), 10);
-:51: WARNING:LONG_LINE: line over 100 characters
#51: FILE: drivers/gpu/drm/i915/intel_color.c:1636:
+ blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(PREC_PAL_DATA_BLUE_MASK, val), 10);
-:64: WARNING:LONG_LINE: line over 100 characters
#64: FILE: drivers/gpu/drm/i915/intel_color.c:1649:
+ crtc_state->base.gamma_lut = ivb_read_lut_10(crtc_state, PAL_PREC_SPLIT_MODE | PAL_PREC_INDEX_VALUE(512));
-:68: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#68: FILE: drivers/gpu/drm/i915/intel_color.c:1653:
+
+}
total: 1 errors, 4 warnings, 2 checks, 63 lines checked
affb0e1188e9 drm/i915: Extract ilk_read_luts()
-:60: WARNING:LONG_LINE: line over 100 characters
#60: FILE: drivers/gpu/drm/i915/intel_color.c:1676:
+ blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_RED_MASK, val), 10);
-:61: WARNING:LONG_LINE: line over 100 characters
#61: FILE: drivers/gpu/drm/i915/intel_color.c:1677:
+ blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_GREEN_MASK, val), 10);
-:62: WARNING:LONG_LINE: line over 100 characters
#62: FILE: drivers/gpu/drm/i915/intel_color.c:1678:
+ blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_BLUE_MASK, val), 10);
total: 0 errors, 3 warnings, 0 checks, 64 lines checked
d106ea46c080 FOR_TESTING_ONLY: Print rgb values of hw and sw blobs
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
-:16: WARNING:LONG_LINE: line over 100 characters
#16: FILE: drivers/gpu/drm/i915/intel_color.c:1379:
+ DRM_DEBUG_KMS("hw_lut->red=0x%x sw_lut->red=0x%x hw_lut->blue=0x%x sw_lut->blue=0x%x hw_lut->green=0x%x sw_lut->green=0x%x", hw_lut->red, sw_lut->red, hw_lut->blue, sw_lut->blue, hw_lut->green, sw_lut->green);
total: 0 errors, 2 warnings, 0 checks, 8 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* ✗ Fi.CI.SPARSE: warning for drm/i915: adding state checker for gamma lut values (rev10)
2019-05-27 13:41 [v7][PATCH 00/12] drm/i915: adding state checker for gamma lut values Swati Sharma
` (12 preceding siblings ...)
2019-05-27 14:00 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: adding state checker for gamma lut values (rev10) Patchwork
@ 2019-05-27 14:05 ` Patchwork
2019-05-27 14:53 ` ✓ Fi.CI.BAT: success " Patchwork
2019-05-28 2:43 ` ✗ Fi.CI.IGT: failure " Patchwork
15 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2019-05-27 14:05 UTC (permalink / raw)
To: Swati Sharma; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: adding state checker for gamma lut values (rev10)
URL : https://patchwork.freedesktop.org/series/58039/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Introduce vfunc read_luts() to create hw lut
Okay!
Commit: drm/i915: Enable intel_color_get_config()
Okay!
Commit: drm/i915: Add intel_color_lut_equal() to compare hw and sw gamma/degamma lut values
Okay!
Commit: drm/i915: Extract i9xx_read_luts()
+drivers/gpu/drm/i915/intel_color.c:1425:15: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:1425:15: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:1425:15: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:1425:15: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:1425:15: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:1425:15: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:1425:15: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:1425:15: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:1465:6: warning: symbol 'i9xx_read_luts' was not declared. Should it be static?
Commit: drm/i915: Extract chv_read_luts()
Okay!
Commit: drm/i915: Extract i965_read_luts()
Okay!
Commit: drm/i915: Extract icl_read_luts()
Okay!
Commit: drm/i915: Extract glk_read_luts()
Okay!
Commit: drm/i915: Extract bdw_read_luts()
Okay!
Commit: drm/i915: Extract ivb_read_luts()
Okay!
Commit: drm/i915: Extract ilk_read_luts()
Okay!
Commit: FOR_TESTING_ONLY: Print rgb values of hw and sw blobs
Okay!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: adding state checker for gamma lut values (rev10)
2019-05-27 13:41 [v7][PATCH 00/12] drm/i915: adding state checker for gamma lut values Swati Sharma
` (13 preceding siblings ...)
2019-05-27 14:05 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2019-05-27 14:53 ` Patchwork
2019-05-28 2:43 ` ✗ Fi.CI.IGT: failure " Patchwork
15 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2019-05-27 14:53 UTC (permalink / raw)
To: Swati Sharma; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: adding state checker for gamma lut values (rev10)
URL : https://patchwork.freedesktop.org/series/58039/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6148 -> Patchwork_13107
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13107/
Known issues
------------
Here are the changes found in Patchwork_13107 that come from known issues:
### IGT changes ###
#### Possible fixes ####
* igt@gem_tiled_pread_basic:
- fi-icl-u3: [DMESG-WARN][1] ([fdo#107724]) -> [PASS][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6148/fi-icl-u3/igt@gem_tiled_pread_basic.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13107/fi-icl-u3/igt@gem_tiled_pread_basic.html
* igt@i915_selftest@live_hangcheck:
- fi-skl-iommu: [INCOMPLETE][3] ([fdo#108602] / [fdo#108744]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6148/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13107/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html
- {fi-icl-dsi}: [INCOMPLETE][5] ([fdo#107713] / [fdo#108569]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6148/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13107/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
#### Warnings ####
* igt@kms_flip@basic-flip-vs-modeset:
- fi-icl-u3: [DMESG-FAIL][7] ([fdo#110718]) -> [DMESG-WARN][8] ([fdo#110718])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6148/fi-icl-u3/igt@kms_flip@basic-flip-vs-modeset.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13107/fi-icl-u3/igt@kms_flip@basic-flip-vs-modeset.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602
[fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744
[fdo#110718]: https://bugs.freedesktop.org/show_bug.cgi?id=110718
Participating hosts (52 -> 45)
------------------------------
Additional (1): fi-gdg-551
Missing (8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-pnv-d510 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_6148 -> Patchwork_13107
CI_DRM_6148: 91e4739d3a58b7a95a43788bad6cd68887934595 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5017: 2892adce93fb8eea3d764dc0f766a202d9dcef37 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13107: d106ea46c08077cd12e35f1bc511b92323da6b86 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
d106ea46c080 FOR_TESTING_ONLY: Print rgb values of hw and sw blobs
affb0e1188e9 drm/i915: Extract ilk_read_luts()
94bf4f217515 drm/i915: Extract ivb_read_luts()
cff18dde61e5 drm/i915: Extract bdw_read_luts()
02d08e6b269c drm/i915: Extract glk_read_luts()
8d64f5ac9f48 drm/i915: Extract icl_read_luts()
5fc9737ac9e0 drm/i915: Extract i965_read_luts()
bf2b1d9e58da drm/i915: Extract chv_read_luts()
383d2598835a drm/i915: Extract i9xx_read_luts()
118f9a116296 drm/i915: Add intel_color_lut_equal() to compare hw and sw gamma/degamma lut values
729d4500e37f drm/i915: Enable intel_color_get_config()
d7ec7acfa25a drm/i915: Introduce vfunc read_luts() to create hw lut
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13107/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* ✗ Fi.CI.IGT: failure for drm/i915: adding state checker for gamma lut values (rev10)
2019-05-27 13:41 [v7][PATCH 00/12] drm/i915: adding state checker for gamma lut values Swati Sharma
` (14 preceding siblings ...)
2019-05-27 14:53 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-05-28 2:43 ` Patchwork
15 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2019-05-28 2:43 UTC (permalink / raw)
To: Swati Sharma; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: adding state checker for gamma lut values (rev10)
URL : https://patchwork.freedesktop.org/series/58039/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6148_full -> Patchwork_13107_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_13107_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_13107_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_13107_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_pwrite@huge-cpu-forwards:
- shard-snb: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6148/shard-snb6/igt@gem_pwrite@huge-cpu-forwards.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13107/shard-snb2/igt@gem_pwrite@huge-cpu-forwards.html
* igt@kms_color@pipe-b-ctm-red-to-blue:
- shard-hsw: [PASS][3] -> [DMESG-WARN][4] +10 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6148/shard-hsw8/igt@kms_color@pipe-b-ctm-red-to-blue.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13107/shard-hsw1/igt@kms_color@pipe-b-ctm-red-to-blue.html
* igt@runner@aborted:
- shard-hsw: NOTRUN -> ([FAIL][5], [FAIL][6], [FAIL][7], [FAIL][8], [FAIL][9], [FAIL][10], [FAIL][11], [FAIL][12], [FAIL][13], [FAIL][14], [FAIL][15])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13107/shard-hsw2/igt@runner@aborted.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13107/shard-hsw1/igt@runner@aborted.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13107/shard-hsw1/igt@runner@aborted.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13107/shard-hsw6/igt@runner@aborted.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13107/shard-hsw1/igt@runner@aborted.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13107/shard-hsw4/igt@runner@aborted.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13107/shard-hsw7/igt@runner@aborted.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13107/shard-hsw4/igt@runner@aborted.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13107/shard-hsw1/igt@runner@aborted.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13107/shard-hsw6/igt@runner@aborted.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13107/shard-hsw8/igt@runner@aborted.html
- shard-snb: NOTRUN -> [FAIL][16]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13107/shard-snb2/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_13107_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_eio@in-flight-suspend:
- shard-glk: [PASS][17] -> [FAIL][18] ([fdo#110667])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6148/shard-glk1/igt@gem_eio@in-flight-suspend.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13107/shard-glk6/igt@gem_eio@in-flight-suspend.html
* igt@gem_exec_schedule@wide-render:
- shard-iclb: [PASS][19] -> [INCOMPLETE][20] ([fdo#107713] / [fdo#110338 ])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6148/shard-iclb4/igt@gem_exec_schedule@wide-render.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13107/shard-iclb1/igt@gem_exec_schedule@wide-render.html
* igt@gem_mmap_gtt@forked-big-copy:
- shard-iclb: [PASS][21] -> [TIMEOUT][22] ([fdo#109673])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6148/shard-iclb6/igt@gem_mmap_gtt@forked-big-copy.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13107/shard-iclb4/igt@gem_mmap_gtt@forked-big-copy.html
* igt@gem_workarounds@suspend-resume-context:
- shard-skl: [PASS][23] -> [INCOMPLETE][24] ([fdo#104108])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6148/shard-skl1/igt@gem_workarounds@suspend-resume-context.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13107/shard-skl10/igt@gem_workarounds@suspend-resume-context.html
* igt@i915_pm_rpm@legacy-planes:
- shard-iclb: [PASS][25] -> [INCOMPLETE][26] ([fdo#107713] / [fdo#108840] / [fdo#109960])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6148/shard-iclb7/igt@i915_pm_rpm@legacy-planes.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13107/shard-iclb2/igt@i915_pm_rpm@legacy-planes.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-apl: [PASS][27] -> [DMESG-WARN][28] ([fdo#108566]) +1 similar issue
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6148/shard-apl3/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13107/shard-apl5/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-hsw: [PASS][29] -> [SKIP][30] ([fdo#109271]) +19 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6148/shard-hsw4/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13107/shard-hsw1/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-glk: [PASS][31] -> [FAIL][32] ([fdo#102887] / [fdo#105363])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6148/shard-glk4/igt@kms_flip@flip-vs-expired-vblank.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13107/shard-glk3/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move:
- shard-iclb: [PASS][33] -> [FAIL][34] ([fdo#103167]) +4 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6148/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13107/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [PASS][35] -> [FAIL][36] ([fdo#108145])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6148/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13107/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][37] -> [FAIL][38] ([fdo#108145] / [fdo#110403])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6148/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13107/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_psr@psr2_primary_mmap_gtt:
- shard-iclb: [PASS][39] -> [SKIP][40] ([fdo#109441])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6148/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13107/shard-iclb6/igt@kms_psr@psr2_primary_mmap_gtt.html
* igt@kms_sysfs_edid_timing:
- shard-iclb: [PASS][41] -> [FAIL][42] ([fdo#100047])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6148/shard-iclb7/igt@kms_sysfs_edid_timing.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13107/shard-iclb2/igt@kms_sysfs_edid_timing.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: [PASS][43] -> [DMESG-WARN][44] ([fdo#108566]) +4 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6148/shard-kbl4/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13107/shard-kbl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-iclb: [PASS][45] -> [INCOMPLETE][46] ([fdo#107713])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6148/shard-iclb1/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13107/shard-iclb1/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
#### Possible fixes ####
* igt@gem_tiled_swapping@non-threaded:
- shard-kbl: [FAIL][47] ([fdo#108686]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6148/shard-kbl1/igt@gem_tiled_swapping@non-threaded.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13107/shard-kbl7/igt@gem_tiled_swapping@non-threaded.html
* igt@gem_workarounds@suspend-resume:
- shard-apl: [DMESG-WARN][49] ([fdo#108566]) -> [PASS][50] +4 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6148/shard-apl6/igt@gem_workarounds@suspend-resume.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13107/shard-apl4/igt@gem_workarounds@suspend-resume.html
* igt@i915_suspend@fence-restore-untiled:
- shard-kbl: [DMESG-WARN][51] ([fdo#108566]) -> [PASS][52] +2 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6148/shard-kbl1/igt@i915_suspend@fence-restore-untiled.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13107/shard-kbl7/igt@i915_suspend@fence-restore-untiled.html
* igt@kms_cursor_crc@pipe-b-cursor-64x64-sliding:
- shard-iclb: [INCOMPLETE][53] ([fdo#107713]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6148/shard-iclb7/igt@kms_cursor_crc@pipe-b-cursor-64x64-sliding.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13107/shard-iclb4/igt@kms_cursor_crc@pipe-b-cursor-64x64-sliding.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-hsw: [SKIP][55] ([fdo#109271]) -> [PASS][56] +16 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6148/shard-hsw1/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13107/shard-hsw7/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite:
- shard-iclb: [FAIL][57] ([fdo#103167]) -> [PASS][58] +1 similar issue
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6148/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13107/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html
* igt@kms_psr@psr2_cursor_plane_onoff:
- shard-iclb: [SKIP][59] ([fdo#109441]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6148/shard-iclb7/igt@kms_psr@psr2_cursor_plane_onoff.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13107/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html
#### Warnings ####
* igt@gem_tiled_swapping@non-threaded:
- shard-hsw: [INCOMPLETE][61] ([fdo#103540]) -> [FAIL][62] ([fdo#108686])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6148/shard-hsw1/igt@gem_tiled_swapping@non-threaded.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13107/shard-hsw2/igt@gem_tiled_swapping@non-threaded.html
* igt@kms_chamelium@hdmi-cmp-yu12:
- shard-glk: [SKIP][63] ([fdo#109271]) -> [INCOMPLETE][64] ([fdo#103359] / [k.org#198133])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6148/shard-glk7/igt@kms_chamelium@hdmi-cmp-yu12.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13107/shard-glk2/igt@kms_chamelium@hdmi-cmp-yu12.html
[fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
[fdo#102887]: https://bugs.freedesktop.org/show_bug.cgi?id=102887
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
[fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109673]: https://bugs.freedesktop.org/show_bug.cgi?id=109673
[fdo#109960]: https://bugs.freedesktop.org/show_bug.cgi?id=109960
[fdo#110338 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110338
[fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
[fdo#110667]: https://bugs.freedesktop.org/show_bug.cgi?id=110667
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_6148 -> Patchwork_13107
CI_DRM_6148: 91e4739d3a58b7a95a43788bad6cd68887934595 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5017: 2892adce93fb8eea3d764dc0f766a202d9dcef37 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13107: d106ea46c08077cd12e35f1bc511b92323da6b86 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13107/
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Intel-gfx@lists.freedesktop.org
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