* [PATCH 1/1] arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs
@ 2019-05-28 4:48 ` Jianqun Xu
0 siblings, 0 replies; 20+ messages in thread
From: Jianqun Xu @ 2019-05-28 4:48 UTC (permalink / raw)
To: jay.xu, heiko, mark.rutland, robh+dt
Cc: zhangzj, manivannan.sadhasivam, linux-rockchip, linux-arm-kernel,
linux-kernel, devicetree
This patch adds core dtsi file for Rockchip RK3399Pro SoCs,
include rk3399.dtsi. Also enable these nodes:
- dfi/dmc for ddr devfreq
- pcie/pcie_phy
- sdhci/sdio/emmc/sdmmc
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
arch/arm64/boot/dts/rockchip/rk3399pro.dtsi | 111 ++++++++++++++++++++
1 file changed, 111 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
new file mode 100644
index 000000000000..62f67f857c45
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
+
+#include "rk3399.dtsi"
+
+/ {
+ compatible = "rockchip,rk3399pro";
+
+ xin32k: xin32k {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "xin32k";
+ #clock-cells = <0>;
+ };
+};
+
+&dfi {
+ status = "okay";
+};
+
+&dmc {
+ status = "okay";
+ center-supply = <&vdd_log>;
+ upthreshold = <40>;
+ downdifferential = <20>;
+ system-status-freq = <
+ /*system status freq(KHz)*/
+ SYS_STATUS_NORMAL 800000
+ SYS_STATUS_REBOOT 528000
+ SYS_STATUS_SUSPEND 200000
+ SYS_STATUS_VIDEO_1080P 200000
+ SYS_STATUS_VIDEO_4K 600000
+ SYS_STATUS_VIDEO_4K_10B 800000
+ SYS_STATUS_PERFORMANCE 800000
+ SYS_STATUS_BOOST 400000
+ SYS_STATUS_DUALVIEW 600000
+ SYS_STATUS_ISP 600000
+ >;
+ vop-pn-msch-readlatency = <
+ /* plane_number readlatency */
+ 0 0
+ 4 0x20
+ >;
+ vop-bw-dmc-freq = <
+ /* min_bw(MB/s) max_bw(MB/s) freq(KHz) */
+ 0 762 200000
+ 763 1893 400000
+ 1894 3012 528000
+ 3013 99999 800000
+ >;
+ auto-min-freq = <200000>;
+};
+
+&emmc_phy {
+ status = "okay";
+};
+
+&pcie_phy {
+ status = "okay";
+};
+
+&pcie0 {
+ ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
+ num-lanes = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_clkreqn_cpm>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ mmc-hs400-1_8v;
+ supports-emmc;
+ non-removable;
+ keep-power-in-suspend;
+ mmc-hs400-enhanced-strobe;
+ status = "okay";
+};
+
+&sdio0 {
+ clock-frequency = <150000000>;
+ clock-freq-min-max = <200000 150000000>;
+ supports-sdio;
+ bus-width = <4>;
+ disable-wp;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ num-slots = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
+&sdmmc {
+ clock-frequency = <150000000>;
+ clock-freq-min-max = <400000 150000000>;
+ supports-sd;
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ num-slots = <1>;
+ vqmmc-supply = <&vccio_sd>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+ status = "okay";
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 1/1] arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs
@ 2019-05-28 4:48 ` Jianqun Xu
0 siblings, 0 replies; 20+ messages in thread
From: Jianqun Xu @ 2019-05-28 4:48 UTC (permalink / raw)
To: jay.xu-TNX95d0MmH7DzftRWevZcw, heiko-4mtYJXux2i+zQB+pC5nmwQ,
mark.rutland-5wv7dgnIgG8, robh+dt-DgEjT+Ai2ygdnm+yROfE0A
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
zhangzj-TNX95d0MmH7DzftRWevZcw,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
manivannan.sadhasivam-QSEj5FYQhm4dnm+yROfE0A,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
This patch adds core dtsi file for Rockchip RK3399Pro SoCs,
include rk3399.dtsi. Also enable these nodes:
- dfi/dmc for ddr devfreq
- pcie/pcie_phy
- sdhci/sdio/emmc/sdmmc
Signed-off-by: Jianqun Xu <jay.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
arch/arm64/boot/dts/rockchip/rk3399pro.dtsi | 111 ++++++++++++++++++++
1 file changed, 111 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
new file mode 100644
index 000000000000..62f67f857c45
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
+
+#include "rk3399.dtsi"
+
+/ {
+ compatible = "rockchip,rk3399pro";
+
+ xin32k: xin32k {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "xin32k";
+ #clock-cells = <0>;
+ };
+};
+
+&dfi {
+ status = "okay";
+};
+
+&dmc {
+ status = "okay";
+ center-supply = <&vdd_log>;
+ upthreshold = <40>;
+ downdifferential = <20>;
+ system-status-freq = <
+ /*system status freq(KHz)*/
+ SYS_STATUS_NORMAL 800000
+ SYS_STATUS_REBOOT 528000
+ SYS_STATUS_SUSPEND 200000
+ SYS_STATUS_VIDEO_1080P 200000
+ SYS_STATUS_VIDEO_4K 600000
+ SYS_STATUS_VIDEO_4K_10B 800000
+ SYS_STATUS_PERFORMANCE 800000
+ SYS_STATUS_BOOST 400000
+ SYS_STATUS_DUALVIEW 600000
+ SYS_STATUS_ISP 600000
+ >;
+ vop-pn-msch-readlatency = <
+ /* plane_number readlatency */
+ 0 0
+ 4 0x20
+ >;
+ vop-bw-dmc-freq = <
+ /* min_bw(MB/s) max_bw(MB/s) freq(KHz) */
+ 0 762 200000
+ 763 1893 400000
+ 1894 3012 528000
+ 3013 99999 800000
+ >;
+ auto-min-freq = <200000>;
+};
+
+&emmc_phy {
+ status = "okay";
+};
+
+&pcie_phy {
+ status = "okay";
+};
+
+&pcie0 {
+ ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
+ num-lanes = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_clkreqn_cpm>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ mmc-hs400-1_8v;
+ supports-emmc;
+ non-removable;
+ keep-power-in-suspend;
+ mmc-hs400-enhanced-strobe;
+ status = "okay";
+};
+
+&sdio0 {
+ clock-frequency = <150000000>;
+ clock-freq-min-max = <200000 150000000>;
+ supports-sdio;
+ bus-width = <4>;
+ disable-wp;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ num-slots = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
+&sdmmc {
+ clock-frequency = <150000000>;
+ clock-freq-min-max = <400000 150000000>;
+ supports-sd;
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ num-slots = <1>;
+ vqmmc-supply = <&vccio_sd>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+ status = "okay";
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 1/1] arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs
@ 2019-05-28 4:48 ` Jianqun Xu
0 siblings, 0 replies; 20+ messages in thread
From: Jianqun Xu @ 2019-05-28 4:48 UTC (permalink / raw)
To: jay.xu, heiko, mark.rutland, robh+dt
Cc: devicetree, linux-kernel, zhangzj, linux-rockchip,
manivannan.sadhasivam, linux-arm-kernel
This patch adds core dtsi file for Rockchip RK3399Pro SoCs,
include rk3399.dtsi. Also enable these nodes:
- dfi/dmc for ddr devfreq
- pcie/pcie_phy
- sdhci/sdio/emmc/sdmmc
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
arch/arm64/boot/dts/rockchip/rk3399pro.dtsi | 111 ++++++++++++++++++++
1 file changed, 111 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
new file mode 100644
index 000000000000..62f67f857c45
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
+
+#include "rk3399.dtsi"
+
+/ {
+ compatible = "rockchip,rk3399pro";
+
+ xin32k: xin32k {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "xin32k";
+ #clock-cells = <0>;
+ };
+};
+
+&dfi {
+ status = "okay";
+};
+
+&dmc {
+ status = "okay";
+ center-supply = <&vdd_log>;
+ upthreshold = <40>;
+ downdifferential = <20>;
+ system-status-freq = <
+ /*system status freq(KHz)*/
+ SYS_STATUS_NORMAL 800000
+ SYS_STATUS_REBOOT 528000
+ SYS_STATUS_SUSPEND 200000
+ SYS_STATUS_VIDEO_1080P 200000
+ SYS_STATUS_VIDEO_4K 600000
+ SYS_STATUS_VIDEO_4K_10B 800000
+ SYS_STATUS_PERFORMANCE 800000
+ SYS_STATUS_BOOST 400000
+ SYS_STATUS_DUALVIEW 600000
+ SYS_STATUS_ISP 600000
+ >;
+ vop-pn-msch-readlatency = <
+ /* plane_number readlatency */
+ 0 0
+ 4 0x20
+ >;
+ vop-bw-dmc-freq = <
+ /* min_bw(MB/s) max_bw(MB/s) freq(KHz) */
+ 0 762 200000
+ 763 1893 400000
+ 1894 3012 528000
+ 3013 99999 800000
+ >;
+ auto-min-freq = <200000>;
+};
+
+&emmc_phy {
+ status = "okay";
+};
+
+&pcie_phy {
+ status = "okay";
+};
+
+&pcie0 {
+ ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
+ num-lanes = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_clkreqn_cpm>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ mmc-hs400-1_8v;
+ supports-emmc;
+ non-removable;
+ keep-power-in-suspend;
+ mmc-hs400-enhanced-strobe;
+ status = "okay";
+};
+
+&sdio0 {
+ clock-frequency = <150000000>;
+ clock-freq-min-max = <200000 150000000>;
+ supports-sdio;
+ bus-width = <4>;
+ disable-wp;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ num-slots = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
+&sdmmc {
+ clock-frequency = <150000000>;
+ clock-freq-min-max = <400000 150000000>;
+ supports-sd;
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ num-slots = <1>;
+ vqmmc-supply = <&vccio_sd>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+ status = "okay";
+};
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 1/1] arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs
2019-05-28 4:48 ` Jianqun Xu
@ 2019-05-29 7:47 ` Jianqun Xu
-1 siblings, 0 replies; 20+ messages in thread
From: Jianqun Xu @ 2019-05-29 7:47 UTC (permalink / raw)
To: jay.xu, heiko, mark.rutland, robh+dt
Cc: zhangzj, manivannan.sadhasivam, linux-rockchip, linux-arm-kernel,
linux-kernel, devicetree
This patch adds core dtsi file for Rockchip RK3399Pro SoCs,
include rk3399.dtsi. Also enable these nodes:
- pcie/pcie_phy
- sdhci/sdio/emmc/sdmmc
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
changes since v1:
- remove dfi and dmc
arch/arm64/boot/dts/rockchip/rk3399pro.dtsi | 74 +++++++++++++++++++++
1 file changed, 74 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
new file mode 100644
index 000000000000..b6d433ffa67d
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
+
+#include "rk3399.dtsi"
+
+/ {
+ compatible = "rockchip,rk3399pro";
+
+ xin32k: xin32k {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "xin32k";
+ #clock-cells = <0>;
+ };
+};
+
+&emmc_phy {
+ status = "okay";
+};
+
+&pcie_phy {
+ status = "okay";
+};
+
+&pcie0 {
+ ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
+ num-lanes = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_clkreqn_cpm>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ mmc-hs400-1_8v;
+ supports-emmc;
+ non-removable;
+ keep-power-in-suspend;
+ mmc-hs400-enhanced-strobe;
+ status = "okay";
+};
+
+&sdio0 {
+ clock-frequency = <150000000>;
+ clock-freq-min-max = <200000 150000000>;
+ supports-sdio;
+ bus-width = <4>;
+ disable-wp;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ num-slots = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
+&sdmmc {
+ clock-frequency = <150000000>;
+ clock-freq-min-max = <400000 150000000>;
+ supports-sd;
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ num-slots = <1>;
+ vqmmc-supply = <&vccio_sd>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+ status = "okay";
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 1/1] arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs
@ 2019-05-29 7:47 ` Jianqun Xu
0 siblings, 0 replies; 20+ messages in thread
From: Jianqun Xu @ 2019-05-29 7:47 UTC (permalink / raw)
To: jay.xu, heiko, mark.rutland, robh+dt
Cc: devicetree, linux-kernel, zhangzj, linux-rockchip,
manivannan.sadhasivam, linux-arm-kernel
This patch adds core dtsi file for Rockchip RK3399Pro SoCs,
include rk3399.dtsi. Also enable these nodes:
- pcie/pcie_phy
- sdhci/sdio/emmc/sdmmc
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
changes since v1:
- remove dfi and dmc
arch/arm64/boot/dts/rockchip/rk3399pro.dtsi | 74 +++++++++++++++++++++
1 file changed, 74 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
new file mode 100644
index 000000000000..b6d433ffa67d
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
+
+#include "rk3399.dtsi"
+
+/ {
+ compatible = "rockchip,rk3399pro";
+
+ xin32k: xin32k {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "xin32k";
+ #clock-cells = <0>;
+ };
+};
+
+&emmc_phy {
+ status = "okay";
+};
+
+&pcie_phy {
+ status = "okay";
+};
+
+&pcie0 {
+ ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
+ num-lanes = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_clkreqn_cpm>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ mmc-hs400-1_8v;
+ supports-emmc;
+ non-removable;
+ keep-power-in-suspend;
+ mmc-hs400-enhanced-strobe;
+ status = "okay";
+};
+
+&sdio0 {
+ clock-frequency = <150000000>;
+ clock-freq-min-max = <200000 150000000>;
+ supports-sdio;
+ bus-width = <4>;
+ disable-wp;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ num-slots = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
+&sdmmc {
+ clock-frequency = <150000000>;
+ clock-freq-min-max = <400000 150000000>;
+ supports-sd;
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ num-slots = <1>;
+ vqmmc-supply = <&vccio_sd>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+ status = "okay";
+};
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH v2 1/1] arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs
2019-05-29 7:47 ` Jianqun Xu
@ 2019-05-29 8:06 ` Heiko Stübner
-1 siblings, 0 replies; 20+ messages in thread
From: Heiko Stübner @ 2019-05-29 8:06 UTC (permalink / raw)
To: Jianqun Xu
Cc: mark.rutland, robh+dt, zhangzj, manivannan.sadhasivam,
linux-rockchip, linux-arm-kernel, linux-kernel, devicetree
Hi Jay,
Am Mittwoch, 29. Mai 2019, 09:47:52 CEST schrieb Jianqun Xu:
> This patch adds core dtsi file for Rockchip RK3399Pro SoCs,
> include rk3399.dtsi. Also enable these nodes:
> - pcie/pcie_phy
> - sdhci/sdio/emmc/sdmmc
>
> Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
> ---
> changes since v1:
> - remove dfi and dmc
>
> arch/arm64/boot/dts/rockchip/rk3399pro.dtsi | 74 +++++++++++++++++++++
> 1 file changed, 74 insertions(+)
> create mode 100644 arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
> new file mode 100644
> index 000000000000..b6d433ffa67d
> --- /dev/null
> +++ b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
> @@ -0,0 +1,74 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +// Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
> +
> +#include "rk3399.dtsi"
> +
> +/ {
> + compatible = "rockchip,rk3399pro";
> +
> + xin32k: xin32k {
> + compatible = "fixed-clock";
> + clock-frequency = <32768>;
> + clock-output-names = "xin32k";
> + #clock-cells = <0>;
> + };
Just to clarify, is the x32k clock really part of the soc itself?
Like on older SoCs it was always supplied from the pmic
or a separate rtc chip.
> +};
> +
> +&emmc_phy {
> + status = "okay";
> +};
Is the emmc used inside the soc? As otherwise emmc / mmc controller
settings would be more a part of the actual board using the soc.
> +&pcie_phy {
> + status = "okay";
> +};
> +
> +&pcie0 {
> + ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
> + num-lanes = <4>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie_clkreqn_cpm>;
> + status = "okay";
> +};
This is probably needed as it needs to talk the rk1808
part over pcie, so it's really internal to the soc.
> +
> +&sdhci {
> + bus-width = <8>;
> + mmc-hs400-1_8v;
> + supports-emmc;
> + non-removable;
> + keep-power-in-suspend;
> + mmc-hs400-enhanced-strobe;
> + status = "okay";
> +};
Same comment as for emmc_phy above
> +&sdio0 {
> + clock-frequency = <150000000>;
> + clock-freq-min-max = <200000 150000000>;
> + supports-sdio;
> + bus-width = <4>;
> + disable-wp;
> + cap-sd-highspeed;
> + cap-sdio-irq;
> + keep-power-in-suspend;
> + mmc-pwrseq = <&sdio_pwrseq>;
> + non-removable;
> + num-slots = <1>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
> + sd-uhs-sdr104;
> + status = "okay";
> +};
Same comment as for emmc_phy above
> +&sdmmc {
> + clock-frequency = <150000000>;
> + clock-freq-min-max = <400000 150000000>;
> + supports-sd;
> + bus-width = <4>;
> + cap-mmc-highspeed;
> + cap-sd-highspeed;
> + disable-wp;
> + num-slots = <1>;
> + vqmmc-supply = <&vccio_sd>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
> + status = "okay";
> +};
Same comment as for emmc_phy above
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 1/1] arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs
@ 2019-05-29 8:06 ` Heiko Stübner
0 siblings, 0 replies; 20+ messages in thread
From: Heiko Stübner @ 2019-05-29 8:06 UTC (permalink / raw)
To: Jianqun Xu
Cc: mark.rutland, devicetree, linux-kernel, zhangzj, linux-rockchip,
robh+dt, manivannan.sadhasivam, linux-arm-kernel
Hi Jay,
Am Mittwoch, 29. Mai 2019, 09:47:52 CEST schrieb Jianqun Xu:
> This patch adds core dtsi file for Rockchip RK3399Pro SoCs,
> include rk3399.dtsi. Also enable these nodes:
> - pcie/pcie_phy
> - sdhci/sdio/emmc/sdmmc
>
> Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
> ---
> changes since v1:
> - remove dfi and dmc
>
> arch/arm64/boot/dts/rockchip/rk3399pro.dtsi | 74 +++++++++++++++++++++
> 1 file changed, 74 insertions(+)
> create mode 100644 arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
> new file mode 100644
> index 000000000000..b6d433ffa67d
> --- /dev/null
> +++ b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
> @@ -0,0 +1,74 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +// Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
> +
> +#include "rk3399.dtsi"
> +
> +/ {
> + compatible = "rockchip,rk3399pro";
> +
> + xin32k: xin32k {
> + compatible = "fixed-clock";
> + clock-frequency = <32768>;
> + clock-output-names = "xin32k";
> + #clock-cells = <0>;
> + };
Just to clarify, is the x32k clock really part of the soc itself?
Like on older SoCs it was always supplied from the pmic
or a separate rtc chip.
> +};
> +
> +&emmc_phy {
> + status = "okay";
> +};
Is the emmc used inside the soc? As otherwise emmc / mmc controller
settings would be more a part of the actual board using the soc.
> +&pcie_phy {
> + status = "okay";
> +};
> +
> +&pcie0 {
> + ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
> + num-lanes = <4>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie_clkreqn_cpm>;
> + status = "okay";
> +};
This is probably needed as it needs to talk the rk1808
part over pcie, so it's really internal to the soc.
> +
> +&sdhci {
> + bus-width = <8>;
> + mmc-hs400-1_8v;
> + supports-emmc;
> + non-removable;
> + keep-power-in-suspend;
> + mmc-hs400-enhanced-strobe;
> + status = "okay";
> +};
Same comment as for emmc_phy above
> +&sdio0 {
> + clock-frequency = <150000000>;
> + clock-freq-min-max = <200000 150000000>;
> + supports-sdio;
> + bus-width = <4>;
> + disable-wp;
> + cap-sd-highspeed;
> + cap-sdio-irq;
> + keep-power-in-suspend;
> + mmc-pwrseq = <&sdio_pwrseq>;
> + non-removable;
> + num-slots = <1>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
> + sd-uhs-sdr104;
> + status = "okay";
> +};
Same comment as for emmc_phy above
> +&sdmmc {
> + clock-frequency = <150000000>;
> + clock-freq-min-max = <400000 150000000>;
> + supports-sd;
> + bus-width = <4>;
> + cap-mmc-highspeed;
> + cap-sd-highspeed;
> + disable-wp;
> + num-slots = <1>;
> + vqmmc-supply = <&vccio_sd>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
> + status = "okay";
> +};
Same comment as for emmc_phy above
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 1/1] arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs
2019-05-29 7:47 ` Jianqun Xu
(?)
(?)
@ 2019-05-29 12:27 ` Manivannan Sadhasivam
2019-05-29 23:59 ` jay.xu
-1 siblings, 1 reply; 20+ messages in thread
From: Manivannan Sadhasivam @ 2019-05-29 12:27 UTC (permalink / raw)
To: Jianqun Xu
Cc: Heiko Stuebner, Mark Rutland, robh+dt, zhangzj, linux-rockchip,
linux-arm-kernel, linux-kernel, devicetree
[-- Attachment #1: Type: text/plain, Size: 2934 bytes --]
Hi,
Thanks for the patch.
On top of Heiko's review:
On Wed, 29 May, 2019, 1:18 PM Jianqun Xu, <jay.xu@rock-chips.com> wrote:
> This patch adds core dtsi file for Rockchip RK3399Pro SoCs,
> include rk3399.dtsi. Also enable these nodes:
> - pcie/pcie_phy
> - sdhci/sdio/emmc/sdmmc
>
> Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
> ---
> changes since v1:
> - remove dfi and dmc
>
> arch/arm64/boot/dts/rockchip/rk3399pro.dtsi | 74 +++++++++++++++++++++
> 1 file changed, 74 insertions(+)
> create mode 100644 arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
> b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
> new file mode 100644
> index 000000000000..b6d433ffa67d
> --- /dev/null
> +++ b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
> @@ -0,0 +1,74 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +// Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
> +
> +#include "rk3399.dtsi"
> +
> +/ {
> + compatible = "rockchip,rk3399pro";
> +
> + xin32k: xin32k {
> + compatible = "fixed-clock";
> + clock-frequency = <32768>;
> + clock-output-names = "xin32k";
> + #clock-cells = <0>;
> + };
> +};
> +
> +&emmc_phy {
> + status = "okay";
> +};
> +
> +&pcie_phy {
> + status = "okay";
> +};
> +
> +&pcie0 {
> + ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
> + num-lanes = <4>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie_clkreqn_cpm>;
> + status = "okay";
> +};
>
So, this is for the NPU inside the soc? If yes, then probably only pcie
nodes should be present in rk3399pro.dtsi and others should be in
respective board dts.
Thanks,
Mani
> +
> +&sdhci {
> + bus-width = <8>;
> + mmc-hs400-1_8v;
> + supports-emmc;
> + non-removable;
> + keep-power-in-suspend;
> + mmc-hs400-enhanced-strobe;
> + status = "okay";
> +};
> +
> +&sdio0 {
> + clock-frequency = <150000000>;
> + clock-freq-min-max = <200000 150000000>;
> + supports-sdio;
> + bus-width = <4>;
> + disable-wp;
> + cap-sd-highspeed;
> + cap-sdio-irq;
> + keep-power-in-suspend;
> + mmc-pwrseq = <&sdio_pwrseq>;
> + non-removable;
> + num-slots = <1>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
> + sd-uhs-sdr104;
> + status = "okay";
> +};
> +
> +&sdmmc {
> + clock-frequency = <150000000>;
> + clock-freq-min-max = <400000 150000000>;
> + supports-sd;
> + bus-width = <4>;
> + cap-mmc-highspeed;
> + cap-sd-highspeed;
> + disable-wp;
> + num-slots = <1>;
> + vqmmc-supply = <&vccio_sd>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
> + status = "okay";
> +};
> --
> 2.17.1
>
>
>
>
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: Re: [PATCH v2 1/1] arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs
2019-05-29 8:06 ` Heiko Stübner
(?)
@ 2019-05-29 23:55 ` jay.xu
-1 siblings, 0 replies; 20+ messages in thread
From: jay.xu @ 2019-05-29 23:55 UTC (permalink / raw)
To: HeikoStübner
Cc: mark.rutland, robh+dt, zhangzj, manivannan.sadhasivam,
linux-rockchip, linux-arm-kernel, linux-kernel, devicetree
[-- Attachment #1: Type: text/plain, Size: 3480 bytes --]
Hi, Heiko
From: HeikoStübner
Date: 2019-05-29 16:06
To: Jianqun Xu
CC: mark.rutland; robh+dt; zhangzj; manivannan.sadhasivam; linux-rockchip; linux-arm-kernel; linux-kernel; devicetree
Subject: Re: [PATCH v2 1/1] arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs
Hi Jay,
Am Mittwoch, 29. Mai 2019, 09:47:52 CEST schrieb Jianqun Xu:
> This patch adds core dtsi file for Rockchip RK3399Pro SoCs,
> include rk3399.dtsi. Also enable these nodes:
> - pcie/pcie_phy
> - sdhci/sdio/emmc/sdmmc
>
> Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
> ---
> changes since v1:
> - remove dfi and dmc
>
> arch/arm64/boot/dts/rockchip/rk3399pro.dtsi | 74 +++++++++++++++++++++
> 1 file changed, 74 insertions(+)
> create mode 100644 arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
> new file mode 100644
> index 000000000000..b6d433ffa67d
> --- /dev/null
> +++ b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
> @@ -0,0 +1,74 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +// Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
> +
> +#include "rk3399.dtsi"
> +
> +/ {
> + compatible = "rockchip,rk3399pro";
> +
> + xin32k: xin32k {
> + compatible = "fixed-clock";
> + clock-frequency = <32768>;
> + clock-output-names = "xin32k";
> + #clock-cells = <0>;
> + };
Just to clarify, is the x32k clock really part of the soc itself?
Like on older SoCs it was always supplied from the pmic
or a separate rtc chip.
The 32K is not part of rk3399pro, it's from pmic.
> +};
> +
> +&emmc_phy {
> + status = "okay";
> +};
Is the emmc used inside the soc? As otherwise emmc / mmc controller
settings would be more a part of the actual board using the soc.
okay, it should be a part of the actual board using the soc, thank you
> +&pcie_phy {
> + status = "okay";
> +};
> +
> +&pcie0 {
> + ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
> + num-lanes = <4>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie_clkreqn_cpm>;
> + status = "okay";
> +};
This is probably needed as it needs to talk the rk1808
part over pcie, so it's really internal to the soc.
Yes, you are right
> +
> +&sdhci {
> + bus-width = <8>;
> + mmc-hs400-1_8v;
> + supports-emmc;
> + non-removable;
> + keep-power-in-suspend;
> + mmc-hs400-enhanced-strobe;
> + status = "okay";
> +};
Same comment as for emmc_phy above
okay, I will add comment here in next version
> +&sdio0 {
> + clock-frequency = <150000000>;
> + clock-freq-min-max = <200000 150000000>;
> + supports-sdio;
> + bus-width = <4>;
> + disable-wp;
> + cap-sd-highspeed;
> + cap-sdio-irq;
> + keep-power-in-suspend;
> + mmc-pwrseq = <&sdio_pwrseq>;
> + non-removable;
> + num-slots = <1>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
> + sd-uhs-sdr104;
> + status = "okay";
> +};
Same comment as for emmc_phy above
okay
> +&sdmmc {
> + clock-frequency = <150000000>;
> + clock-freq-min-max = <400000 150000000>;
> + supports-sd;
> + bus-width = <4>;
> + cap-mmc-highspeed;
> + cap-sd-highspeed;
> + disable-wp;
> + num-slots = <1>;
> + vqmmc-supply = <&vccio_sd>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
> + status = "okay";
> +};
Same comment as for emmc_phy above
okay
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: Re: [PATCH v2 1/1] arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs
2019-05-29 12:27 ` Manivannan Sadhasivam
@ 2019-05-29 23:59 ` jay.xu
0 siblings, 0 replies; 20+ messages in thread
From: jay.xu @ 2019-05-29 23:59 UTC (permalink / raw)
To: manivannan.sadhasivam
Cc: HeikoStübner, mark.rutland, robh+dt,
张志杰(创新),
linux-rockchip, linux-arm-kernel, linux-kernel, devicetree
[-- Attachment #1: Type: text/plain, Size: 3208 bytes --]
Hi manivannan.sadhasivam,
jay.xu@rock-chips.com
From: Manivannan Sadhasivam
Date: 2019-05-29 20:57
To: Jianqun Xu
CC: Heiko Stuebner; Mark Rutland; robh+dt; zhangzj; linux-rockchip; linux-arm-kernel; linux-kernel; devicetree
Subject: Re: [PATCH v2 1/1] arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs
Hi,
Thanks for the patch.
On top of Heiko's review:
On Wed, 29 May, 2019, 1:18 PM Jianqun Xu, <jay.xu@rock-chips.com> wrote:
This patch adds core dtsi file for Rockchip RK3399Pro SoCs,
include rk3399.dtsi. Also enable these nodes:
- pcie/pcie_phy
- sdhci/sdio/emmc/sdmmc
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
changes since v1:
- remove dfi and dmc
arch/arm64/boot/dts/rockchip/rk3399pro.dtsi | 74 +++++++++++++++++++++
1 file changed, 74 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
new file mode 100644
index 000000000000..b6d433ffa67d
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
+
+#include "rk3399.dtsi"
+
+/ {
+ compatible = "rockchip,rk3399pro";
+
+ xin32k: xin32k {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "xin32k";
+ #clock-cells = <0>;
+ };
+};
+
+&emmc_phy {
+ status = "okay";
+};
+
+&pcie_phy {
+ status = "okay";
+};
+
+&pcie0 {
+ ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
+ num-lanes = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_clkreqn_cpm>;
+ status = "okay";
+};
So, this is for the NPU inside the soc? If yes, then probably only pcie nodes should be present in rk3399pro.dtsi and others should be in respective board dts.
ok, thanks for your tips.
Thanks,
Mani
+
+&sdhci {
+ bus-width = <8>;
+ mmc-hs400-1_8v;
+ supports-emmc;
+ non-removable;
+ keep-power-in-suspend;
+ mmc-hs400-enhanced-strobe;
+ status = "okay";
+};
+
+&sdio0 {
+ clock-frequency = <150000000>;
+ clock-freq-min-max = <200000 150000000>;
+ supports-sdio;
+ bus-width = <4>;
+ disable-wp;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ num-slots = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
+&sdmmc {
+ clock-frequency = <150000000>;
+ clock-freq-min-max = <400000 150000000>;
+ supports-sd;
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ num-slots = <1>;
+ vqmmc-supply = <&vccio_sd>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+ status = "okay";
+};
--
2.17.1
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^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v3 1/1] arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs
2019-05-29 7:47 ` Jianqun Xu
@ 2019-05-30 0:08 ` Jianqun Xu
-1 siblings, 0 replies; 20+ messages in thread
From: Jianqun Xu @ 2019-05-30 0:08 UTC (permalink / raw)
To: jay.xu, heiko, mark.rutland, robh+dt
Cc: zhangzj, manivannan.sadhasivam, linux-rockchip, linux-arm-kernel,
linux-kernel, devicetree
This patch adds core dtsi file for Rockchip RK3399Pro SoCs,
include rk3399.dtsi. Also enable pciei0/pcie_phy for AP to
talk to NPU part inside SoC.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
changes since v2:
- only enable pcie0 and pcie_phy nodes, thanks for Heiko and manivannan
changes since v1:
- remove dfi and dmc
arch/arm64/boot/dts/rockchip/rk3399pro.dtsi | 22 +++++++++++++++++++++
1 file changed, 22 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
new file mode 100644
index 000000000000..bb5ebf6608b9
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
+
+#include "rk3399.dtsi"
+
+/ {
+ compatible = "rockchip,rk3399pro";
+};
+
+/* Default to enabled since AP talk to NPU part over pcie */
+&pcie_phy {
+ status = "okay";
+};
+
+/* Default to enabled since AP talk to NPU part over pcie */
+&pcie0 {
+ ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
+ num-lanes = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_clkreqn_cpm>;
+ status = "okay";
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v3 1/1] arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs
@ 2019-05-30 0:08 ` Jianqun Xu
0 siblings, 0 replies; 20+ messages in thread
From: Jianqun Xu @ 2019-05-30 0:08 UTC (permalink / raw)
To: jay.xu, heiko, mark.rutland, robh+dt
Cc: devicetree, linux-kernel, zhangzj, linux-rockchip,
manivannan.sadhasivam, linux-arm-kernel
This patch adds core dtsi file for Rockchip RK3399Pro SoCs,
include rk3399.dtsi. Also enable pciei0/pcie_phy for AP to
talk to NPU part inside SoC.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
changes since v2:
- only enable pcie0 and pcie_phy nodes, thanks for Heiko and manivannan
changes since v1:
- remove dfi and dmc
arch/arm64/boot/dts/rockchip/rk3399pro.dtsi | 22 +++++++++++++++++++++
1 file changed, 22 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
new file mode 100644
index 000000000000..bb5ebf6608b9
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
+
+#include "rk3399.dtsi"
+
+/ {
+ compatible = "rockchip,rk3399pro";
+};
+
+/* Default to enabled since AP talk to NPU part over pcie */
+&pcie_phy {
+ status = "okay";
+};
+
+/* Default to enabled since AP talk to NPU part over pcie */
+&pcie0 {
+ ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
+ num-lanes = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_clkreqn_cpm>;
+ status = "okay";
+};
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH v3 1/1] arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs
2019-05-30 0:08 ` Jianqun Xu
(?)
@ 2019-05-31 3:24 ` Manivannan Sadhasivam
-1 siblings, 0 replies; 20+ messages in thread
From: Manivannan Sadhasivam @ 2019-05-31 3:24 UTC (permalink / raw)
To: Jianqun Xu
Cc: heiko, mark.rutland, robh+dt, zhangzj, linux-rockchip,
linux-arm-kernel, linux-kernel, devicetree
On Thu, May 30, 2019 at 08:08:48AM +0800, Jianqun Xu wrote:
> This patch adds core dtsi file for Rockchip RK3399Pro SoCs,
> include rk3399.dtsi. Also enable pciei0/pcie_phy for AP to
> talk to NPU part inside SoC.
>
> Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
> ---
> changes since v2:
> - only enable pcie0 and pcie_phy nodes, thanks for Heiko and manivannan
>
> changes since v1:
> - remove dfi and dmc
>
> arch/arm64/boot/dts/rockchip/rk3399pro.dtsi | 22 +++++++++++++++++++++
> 1 file changed, 22 insertions(+)
> create mode 100644 arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
> new file mode 100644
> index 000000000000..bb5ebf6608b9
> --- /dev/null
> +++ b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
> @@ -0,0 +1,22 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +// Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
> +
> +#include "rk3399.dtsi"
> +
> +/ {
> + compatible = "rockchip,rk3399pro";
> +};
> +
> +/* Default to enabled since AP talk to NPU part over pcie */
> +&pcie_phy {
> + status = "okay";
> +};
> +
> +/* Default to enabled since AP talk to NPU part over pcie */
> +&pcie0 {
> + ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
> + num-lanes = <4>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie_clkreqn_cpm>;
No pinctrl config for ep-gpio? Other than that, it looks good to me.
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Thanks,
Mani
> + status = "okay";
> +};
> --
> 2.17.1
>
>
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v3 1/1] arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs
@ 2019-05-31 3:24 ` Manivannan Sadhasivam
0 siblings, 0 replies; 20+ messages in thread
From: Manivannan Sadhasivam @ 2019-05-31 3:24 UTC (permalink / raw)
To: Jianqun Xu
Cc: mark.rutland, devicetree, heiko, linux-kernel, zhangzj,
linux-rockchip, robh+dt, linux-arm-kernel
On Thu, May 30, 2019 at 08:08:48AM +0800, Jianqun Xu wrote:
> This patch adds core dtsi file for Rockchip RK3399Pro SoCs,
> include rk3399.dtsi. Also enable pciei0/pcie_phy for AP to
> talk to NPU part inside SoC.
>
> Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
> ---
> changes since v2:
> - only enable pcie0 and pcie_phy nodes, thanks for Heiko and manivannan
>
> changes since v1:
> - remove dfi and dmc
>
> arch/arm64/boot/dts/rockchip/rk3399pro.dtsi | 22 +++++++++++++++++++++
> 1 file changed, 22 insertions(+)
> create mode 100644 arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
> new file mode 100644
> index 000000000000..bb5ebf6608b9
> --- /dev/null
> +++ b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
> @@ -0,0 +1,22 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +// Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
> +
> +#include "rk3399.dtsi"
> +
> +/ {
> + compatible = "rockchip,rk3399pro";
> +};
> +
> +/* Default to enabled since AP talk to NPU part over pcie */
> +&pcie_phy {
> + status = "okay";
> +};
> +
> +/* Default to enabled since AP talk to NPU part over pcie */
> +&pcie0 {
> + ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
> + num-lanes = <4>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie_clkreqn_cpm>;
No pinctrl config for ep-gpio? Other than that, it looks good to me.
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Thanks,
Mani
> + status = "okay";
> +};
> --
> 2.17.1
>
>
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v3 1/1] arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs
@ 2019-05-31 3:24 ` Manivannan Sadhasivam
0 siblings, 0 replies; 20+ messages in thread
From: Manivannan Sadhasivam @ 2019-05-31 3:24 UTC (permalink / raw)
To: Jianqun Xu
Cc: mark.rutland, devicetree, heiko, linux-kernel, zhangzj,
linux-rockchip, robh+dt, linux-arm-kernel
On Thu, May 30, 2019 at 08:08:48AM +0800, Jianqun Xu wrote:
> This patch adds core dtsi file for Rockchip RK3399Pro SoCs,
> include rk3399.dtsi. Also enable pciei0/pcie_phy for AP to
> talk to NPU part inside SoC.
>
> Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
> ---
> changes since v2:
> - only enable pcie0 and pcie_phy nodes, thanks for Heiko and manivannan
>
> changes since v1:
> - remove dfi and dmc
>
> arch/arm64/boot/dts/rockchip/rk3399pro.dtsi | 22 +++++++++++++++++++++
> 1 file changed, 22 insertions(+)
> create mode 100644 arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
> new file mode 100644
> index 000000000000..bb5ebf6608b9
> --- /dev/null
> +++ b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
> @@ -0,0 +1,22 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +// Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
> +
> +#include "rk3399.dtsi"
> +
> +/ {
> + compatible = "rockchip,rk3399pro";
> +};
> +
> +/* Default to enabled since AP talk to NPU part over pcie */
> +&pcie_phy {
> + status = "okay";
> +};
> +
> +/* Default to enabled since AP talk to NPU part over pcie */
> +&pcie0 {
> + ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
> + num-lanes = <4>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie_clkreqn_cpm>;
No pinctrl config for ep-gpio? Other than that, it looks good to me.
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Thanks,
Mani
> + status = "okay";
> +};
> --
> 2.17.1
>
>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v3 1/1] arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs
2019-05-30 0:08 ` Jianqun Xu
@ 2019-06-14 9:52 ` Heiko Stuebner
-1 siblings, 0 replies; 20+ messages in thread
From: Heiko Stuebner @ 2019-06-14 9:52 UTC (permalink / raw)
To: Jianqun Xu
Cc: mark.rutland, robh+dt, zhangzj, manivannan.sadhasivam,
linux-rockchip, linux-arm-kernel, linux-kernel, devicetree
Hi Jianqun,
Am Donnerstag, 30. Mai 2019, 02:08:48 CEST schrieb Jianqun Xu:
> This patch adds core dtsi file for Rockchip RK3399Pro SoCs,
> include rk3399.dtsi. Also enable pciei0/pcie_phy for AP to
> talk to NPU part inside SoC.
>
> Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
could you add the necessary pinctrl entry, as suggested by Manivannan?
Thanks
Heiko
> ---
> changes since v2:
> - only enable pcie0 and pcie_phy nodes, thanks for Heiko and manivannan
>
> changes since v1:
> - remove dfi and dmc
>
> arch/arm64/boot/dts/rockchip/rk3399pro.dtsi | 22 +++++++++++++++++++++
> 1 file changed, 22 insertions(+)
> create mode 100644 arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
> new file mode 100644
> index 000000000000..bb5ebf6608b9
> --- /dev/null
> +++ b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
> @@ -0,0 +1,22 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +// Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
> +
> +#include "rk3399.dtsi"
> +
> +/ {
> + compatible = "rockchip,rk3399pro";
> +};
> +
> +/* Default to enabled since AP talk to NPU part over pcie */
> +&pcie_phy {
> + status = "okay";
> +};
> +
> +/* Default to enabled since AP talk to NPU part over pcie */
> +&pcie0 {
> + ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
> + num-lanes = <4>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie_clkreqn_cpm>;
> + status = "okay";
> +};
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v3 1/1] arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs
@ 2019-06-14 9:52 ` Heiko Stuebner
0 siblings, 0 replies; 20+ messages in thread
From: Heiko Stuebner @ 2019-06-14 9:52 UTC (permalink / raw)
To: Jianqun Xu
Cc: mark.rutland, devicetree, linux-kernel, zhangzj, linux-rockchip,
robh+dt, manivannan.sadhasivam, linux-arm-kernel
Hi Jianqun,
Am Donnerstag, 30. Mai 2019, 02:08:48 CEST schrieb Jianqun Xu:
> This patch adds core dtsi file for Rockchip RK3399Pro SoCs,
> include rk3399.dtsi. Also enable pciei0/pcie_phy for AP to
> talk to NPU part inside SoC.
>
> Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
could you add the necessary pinctrl entry, as suggested by Manivannan?
Thanks
Heiko
> ---
> changes since v2:
> - only enable pcie0 and pcie_phy nodes, thanks for Heiko and manivannan
>
> changes since v1:
> - remove dfi and dmc
>
> arch/arm64/boot/dts/rockchip/rk3399pro.dtsi | 22 +++++++++++++++++++++
> 1 file changed, 22 insertions(+)
> create mode 100644 arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
> new file mode 100644
> index 000000000000..bb5ebf6608b9
> --- /dev/null
> +++ b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
> @@ -0,0 +1,22 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +// Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
> +
> +#include "rk3399.dtsi"
> +
> +/ {
> + compatible = "rockchip,rk3399pro";
> +};
> +
> +/* Default to enabled since AP talk to NPU part over pcie */
> +&pcie_phy {
> + status = "okay";
> +};
> +
> +/* Default to enabled since AP talk to NPU part over pcie */
> +&pcie0 {
> + ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
> + num-lanes = <4>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie_clkreqn_cpm>;
> + status = "okay";
> +};
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: Re: [PATCH v3 1/1] arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs
2019-06-14 9:52 ` Heiko Stuebner
(?)
@ 2019-06-24 1:57 ` jay.xu
-1 siblings, 0 replies; 20+ messages in thread
From: jay.xu @ 2019-06-24 1:57 UTC (permalink / raw)
To: Heiko Stuebner
Cc: mark.rutland, robh+dt,
张志杰(创新),
manivannan.sadhasivam, linux-rockchip, linux-arm-kernel,
linux-kernel, devicetree
[-- Attachment #1: Type: text/plain, Size: 2093 bytes --]
Hi, Keiko and Manivannan:
Sorry late to reply since I missed this mail after a long leave time.
jay.xu@rock-chips.com
From: Heiko Stuebner
Date: 2019-06-14 17:52
To: Jianqun Xu
CC: mark.rutland; robh+dt; zhangzj; manivannan.sadhasivam; linux-rockchip; linux-arm-kernel; linux-kernel; devicetree
Subject: Re: [PATCH v3 1/1] arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs
Hi Jianqun,
Am Donnerstag, 30. Mai 2019, 02:08:48 CEST schrieb Jianqun Xu:
> This patch adds core dtsi file for Rockchip RK3399Pro SoCs,
> include rk3399.dtsi. Also enable pciei0/pcie_phy for AP to
> talk to NPU part inside SoC.
>
> Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
could you add the necessary pinctrl entry, as suggested by Manivannan?
Hi, there is no pinctrl for ep-gpios, which used as GPIO, they will set by gpio driver
mux to GPIO defaultly.
Thanks
Heiko
> ---
> changes since v2:
> - only enable pcie0 and pcie_phy nodes, thanks for Heiko and manivannan
>
> changes since v1:
> - remove dfi and dmc
>
> arch/arm64/boot/dts/rockchip/rk3399pro.dtsi | 22 +++++++++++++++++++++
> 1 file changed, 22 insertions(+)
> create mode 100644 arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
> new file mode 100644
> index 000000000000..bb5ebf6608b9
> --- /dev/null
> +++ b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
> @@ -0,0 +1,22 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +// Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
> +
> +#include "rk3399.dtsi"
> +
> +/ {
> + compatible = "rockchip,rk3399pro";
> +};
> +
> +/* Default to enabled since AP talk to NPU part over pcie */
> +&pcie_phy {
> + status = "okay";
> +};
> +
> +/* Default to enabled since AP talk to NPU part over pcie */
> +&pcie0 {
> + ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
> + num-lanes = <4>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie_clkreqn_cpm>;
> + status = "okay";
> +};
>
[-- Attachment #2: Type: text/html, Size: 4501 bytes --]
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v3 1/1] arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs
2019-05-30 0:08 ` Jianqun Xu
@ 2019-06-26 22:23 ` Heiko Stuebner
-1 siblings, 0 replies; 20+ messages in thread
From: Heiko Stuebner @ 2019-06-26 22:23 UTC (permalink / raw)
To: Jianqun Xu
Cc: mark.rutland, robh+dt, zhangzj, manivannan.sadhasivam,
linux-rockchip, linux-arm-kernel, linux-kernel, devicetree
Am Donnerstag, 30. Mai 2019, 02:08:48 CEST schrieb Jianqun Xu:
> This patch adds core dtsi file for Rockchip RK3399Pro SoCs,
> include rk3399.dtsi. Also enable pciei0/pcie_phy for AP to
> talk to NPU part inside SoC.
>
> Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
applied for 5.3
Thanks
Heiko
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v3 1/1] arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs
@ 2019-06-26 22:23 ` Heiko Stuebner
0 siblings, 0 replies; 20+ messages in thread
From: Heiko Stuebner @ 2019-06-26 22:23 UTC (permalink / raw)
To: Jianqun Xu
Cc: mark.rutland, devicetree, linux-kernel, zhangzj, linux-rockchip,
robh+dt, manivannan.sadhasivam, linux-arm-kernel
Am Donnerstag, 30. Mai 2019, 02:08:48 CEST schrieb Jianqun Xu:
> This patch adds core dtsi file for Rockchip RK3399Pro SoCs,
> include rk3399.dtsi. Also enable pciei0/pcie_phy for AP to
> talk to NPU part inside SoC.
>
> Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
applied for 5.3
Thanks
Heiko
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2019-06-27 5:34 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-05-28 4:48 [PATCH 1/1] arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs Jianqun Xu
2019-05-28 4:48 ` Jianqun Xu
2019-05-28 4:48 ` Jianqun Xu
2019-05-29 7:47 ` [PATCH v2 " Jianqun Xu
2019-05-29 7:47 ` Jianqun Xu
2019-05-29 8:06 ` Heiko Stübner
2019-05-29 8:06 ` Heiko Stübner
2019-05-29 23:55 ` jay.xu
2019-05-29 12:27 ` Manivannan Sadhasivam
2019-05-29 23:59 ` jay.xu
2019-05-30 0:08 ` [PATCH v3 " Jianqun Xu
2019-05-30 0:08 ` Jianqun Xu
2019-05-31 3:24 ` Manivannan Sadhasivam
2019-05-31 3:24 ` Manivannan Sadhasivam
2019-05-31 3:24 ` Manivannan Sadhasivam
2019-06-14 9:52 ` Heiko Stuebner
2019-06-14 9:52 ` Heiko Stuebner
2019-06-24 1:57 ` jay.xu
2019-06-26 22:23 ` Heiko Stuebner
2019-06-26 22:23 ` Heiko Stuebner
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