* [PATCH 0/5] arch: riscv: add board and SoC DT file support
@ 2019-06-02 8:02 ` Paul Walmsley
0 siblings, 0 replies; 6+ messages in thread
From: Paul Walmsley @ 2019-06-02 8:02 UTC (permalink / raw)
To: linux-kernel, linux-riscv
Add support for building flattened DT files from DT source files under
arch/riscv/boot/dts. Follow existing kernel precedent from other SoC
architectures. Start our board support by adding initial support for
the SiFive FU540 SoC and the first development board that uses it, the
SiFive HiFive Unleashed A00.
This third version of the patch set adds I2C data for the chip,
incorporates all remaining changes that riscv-pk was making
automatically, and addresses a comment from Rob Herring
<robh@kernel.org>.
Boot-tested on v5.2-rc1 on a HiFive Unleashed A00 board, using the
BBL and open-source FSBL, with modifications to pass in the DTB
file generated by these patches.
This patch series can be found, along with the PRCI patch set
and the DT macro prerequisite patch, at:
https://github.com/sifive/riscv-linux/tree/dev/paulw/dts-v5.2-rc1
- Paul
Paul Walmsley (5):
arch: riscv: add support for building DTB files from DT source data
dt-bindings: riscv: sifive: add YAML documentation for the SiFive
FU540
dt-bindings: riscv: convert cpu binding to json-schema
riscv: dts: add initial support for the SiFive FU540-C000 SoC
riscv: dts: add initial board data for the SiFive HiFive Unleashed
.../devicetree/bindings/riscv/cpus.yaml | 168 ++++++++++++++
.../devicetree/bindings/riscv/sifive.yaml | 25 ++
MAINTAINERS | 9 +
arch/riscv/boot/dts/Makefile | 2 +
arch/riscv/boot/dts/sifive/Makefile | 2 +
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 215 ++++++++++++++++++
.../boot/dts/sifive/hifive-unleashed-a00.dts | 67 ++++++
7 files changed, 488 insertions(+)
create mode 100644 Documentation/devicetree/bindings/riscv/cpus.yaml
create mode 100644 Documentation/devicetree/bindings/riscv/sifive.yaml
create mode 100644 arch/riscv/boot/dts/Makefile
create mode 100644 arch/riscv/boot/dts/sifive/Makefile
create mode 100644 arch/riscv/boot/dts/sifive/fu540-c000.dtsi
create mode 100644 arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
--
2.20.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 0/5] arch: riscv: add board and SoC DT file support
@ 2019-06-02 8:02 ` Paul Walmsley
0 siblings, 0 replies; 6+ messages in thread
From: Paul Walmsley @ 2019-06-02 8:02 UTC (permalink / raw)
To: linux-kernel, linux-riscv
Add support for building flattened DT files from DT source files under
arch/riscv/boot/dts. Follow existing kernel precedent from other SoC
architectures. Start our board support by adding initial support for
the SiFive FU540 SoC and the first development board that uses it, the
SiFive HiFive Unleashed A00.
This third version of the patch set adds I2C data for the chip,
incorporates all remaining changes that riscv-pk was making
automatically, and addresses a comment from Rob Herring
<robh@kernel.org>.
Boot-tested on v5.2-rc1 on a HiFive Unleashed A00 board, using the
BBL and open-source FSBL, with modifications to pass in the DTB
file generated by these patches.
This patch series can be found, along with the PRCI patch set
and the DT macro prerequisite patch, at:
https://github.com/sifive/riscv-linux/tree/dev/paulw/dts-v5.2-rc1
- Paul
Paul Walmsley (5):
arch: riscv: add support for building DTB files from DT source data
dt-bindings: riscv: sifive: add YAML documentation for the SiFive
FU540
dt-bindings: riscv: convert cpu binding to json-schema
riscv: dts: add initial support for the SiFive FU540-C000 SoC
riscv: dts: add initial board data for the SiFive HiFive Unleashed
.../devicetree/bindings/riscv/cpus.yaml | 168 ++++++++++++++
.../devicetree/bindings/riscv/sifive.yaml | 25 ++
MAINTAINERS | 9 +
arch/riscv/boot/dts/Makefile | 2 +
arch/riscv/boot/dts/sifive/Makefile | 2 +
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 215 ++++++++++++++++++
.../boot/dts/sifive/hifive-unleashed-a00.dts | 67 ++++++
7 files changed, 488 insertions(+)
create mode 100644 Documentation/devicetree/bindings/riscv/cpus.yaml
create mode 100644 Documentation/devicetree/bindings/riscv/sifive.yaml
create mode 100644 arch/riscv/boot/dts/Makefile
create mode 100644 arch/riscv/boot/dts/sifive/Makefile
create mode 100644 arch/riscv/boot/dts/sifive/fu540-c000.dtsi
create mode 100644 arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
--
2.20.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/5] arch: riscv: add support for building DTB files from DT source data
2019-06-02 8:02 ` Paul Walmsley
@ 2019-06-02 8:02 ` Paul Walmsley
-1 siblings, 0 replies; 6+ messages in thread
From: Paul Walmsley @ 2019-06-02 8:02 UTC (permalink / raw)
To: linux-kernel, linux-riscv; +Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou
Similar to ARM64, add support for building DTB files from DT source
data for RISC-V boards.
This patch starts with the infrastructure needed for SiFive boards.
Boards from other vendors would add support here in a similar form.
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>
---
arch/riscv/boot/dts/Makefile | 2 ++
1 file changed, 2 insertions(+)
create mode 100644 arch/riscv/boot/dts/Makefile
diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
new file mode 100644
index 000000000000..dcc3ada78455
--- /dev/null
+++ b/arch/riscv/boot/dts/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+subdir-y += sifive
--
2.20.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 1/5] arch: riscv: add support for building DTB files from DT source data
@ 2019-06-02 8:02 ` Paul Walmsley
0 siblings, 0 replies; 6+ messages in thread
From: Paul Walmsley @ 2019-06-02 8:02 UTC (permalink / raw)
To: linux-kernel, linux-riscv; +Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou
Similar to ARM64, add support for building DTB files from DT source
data for RISC-V boards.
This patch starts with the infrastructure needed for SiFive boards.
Boards from other vendors would add support here in a similar form.
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>
---
arch/riscv/boot/dts/Makefile | 2 ++
1 file changed, 2 insertions(+)
create mode 100644 arch/riscv/boot/dts/Makefile
diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
new file mode 100644
index 000000000000..dcc3ada78455
--- /dev/null
+++ b/arch/riscv/boot/dts/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+subdir-y += sifive
--
2.20.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 0/5] arch: riscv: add board and SoC DT file support
@ 2019-06-02 8:01 ` Paul Walmsley
0 siblings, 0 replies; 6+ messages in thread
From: Paul Walmsley @ 2019-06-02 8:01 UTC (permalink / raw)
To: linux-kernel, linux-riscv
Add support for building flattened DT files from DT source files under
arch/riscv/boot/dts. Follow existing kernel precedent from other SoC
architectures. Start our board support by adding initial support for
the SiFive FU540 SoC and the first development board that uses it, the
SiFive HiFive Unleashed A00.
This third version of the patch set adds I2C data for the chip,
incorporates all remaining changes that riscv-pk was making
automatically, and addresses a comment from Rob Herring
<robh@kernel.org>.
Boot-tested on v5.2-rc1 on a HiFive Unleashed A00 board, using the
BBL and open-source FSBL, with modifications to pass in the DTB
file generated by these patches.
This patch series can be found, along with the PRCI patch set
and the DT macro prerequisite patch, at:
https://github.com/sifive/riscv-linux/tree/dev/paulw/dts-v5.2-rc1
- Paul
Paul Walmsley (5):
arch: riscv: add support for building DTB files from DT source data
dt-bindings: riscv: sifive: add YAML documentation for the SiFive
FU540
dt-bindings: riscv: convert cpu binding to json-schema
riscv: dts: add initial support for the SiFive FU540-C000 SoC
riscv: dts: add initial board data for the SiFive HiFive Unleashed
.../devicetree/bindings/riscv/cpus.yaml | 168 ++++++++++++++
.../devicetree/bindings/riscv/sifive.yaml | 25 ++
MAINTAINERS | 9 +
arch/riscv/boot/dts/Makefile | 2 +
arch/riscv/boot/dts/sifive/Makefile | 2 +
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 215 ++++++++++++++++++
.../boot/dts/sifive/hifive-unleashed-a00.dts | 67 ++++++
7 files changed, 488 insertions(+)
create mode 100644 Documentation/devicetree/bindings/riscv/cpus.yaml
create mode 100644 Documentation/devicetree/bindings/riscv/sifive.yaml
create mode 100644 arch/riscv/boot/dts/Makefile
create mode 100644 arch/riscv/boot/dts/sifive/Makefile
create mode 100644 arch/riscv/boot/dts/sifive/fu540-c000.dtsi
create mode 100644 arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
--
2.20.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 0/5] arch: riscv: add board and SoC DT file support
@ 2019-06-02 8:01 ` Paul Walmsley
0 siblings, 0 replies; 6+ messages in thread
From: Paul Walmsley @ 2019-06-02 8:01 UTC (permalink / raw)
To: linux-kernel, linux-riscv
Add support for building flattened DT files from DT source files under
arch/riscv/boot/dts. Follow existing kernel precedent from other SoC
architectures. Start our board support by adding initial support for
the SiFive FU540 SoC and the first development board that uses it, the
SiFive HiFive Unleashed A00.
This third version of the patch set adds I2C data for the chip,
incorporates all remaining changes that riscv-pk was making
automatically, and addresses a comment from Rob Herring
<robh@kernel.org>.
Boot-tested on v5.2-rc1 on a HiFive Unleashed A00 board, using the
BBL and open-source FSBL, with modifications to pass in the DTB
file generated by these patches.
This patch series can be found, along with the PRCI patch set
and the DT macro prerequisite patch, at:
https://github.com/sifive/riscv-linux/tree/dev/paulw/dts-v5.2-rc1
- Paul
Paul Walmsley (5):
arch: riscv: add support for building DTB files from DT source data
dt-bindings: riscv: sifive: add YAML documentation for the SiFive
FU540
dt-bindings: riscv: convert cpu binding to json-schema
riscv: dts: add initial support for the SiFive FU540-C000 SoC
riscv: dts: add initial board data for the SiFive HiFive Unleashed
.../devicetree/bindings/riscv/cpus.yaml | 168 ++++++++++++++
.../devicetree/bindings/riscv/sifive.yaml | 25 ++
MAINTAINERS | 9 +
arch/riscv/boot/dts/Makefile | 2 +
arch/riscv/boot/dts/sifive/Makefile | 2 +
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 215 ++++++++++++++++++
.../boot/dts/sifive/hifive-unleashed-a00.dts | 67 ++++++
7 files changed, 488 insertions(+)
create mode 100644 Documentation/devicetree/bindings/riscv/cpus.yaml
create mode 100644 Documentation/devicetree/bindings/riscv/sifive.yaml
create mode 100644 arch/riscv/boot/dts/Makefile
create mode 100644 arch/riscv/boot/dts/sifive/Makefile
create mode 100644 arch/riscv/boot/dts/sifive/fu540-c000.dtsi
create mode 100644 arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
--
2.20.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2019-06-02 8:03 UTC | newest]
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2019-06-02 8:02 [PATCH 0/5] arch: riscv: add board and SoC DT file support Paul Walmsley
2019-06-02 8:02 ` Paul Walmsley
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2019-06-02 8:02 ` Paul Walmsley
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2019-06-02 8:01 ` Paul Walmsley
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