* [Qemu-devel] [PATCH v2 00/22] s390x/tcg: Vector Instruction Support Part 4
@ 2019-06-03 9:06 David Hildenbrand
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 01/22] s390x/tcg: Store only the necessary amount of doublewords for STFLE David Hildenbrand
` (23 more replies)
0 siblings, 24 replies; 34+ messages in thread
From: David Hildenbrand @ 2019-06-03 9:06 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Denys Vlasenko, David Hildenbrand, Cornelia Huck,
Pino Toscano, Christian Borntraeger, qemu-s390x,
Richard Henderson
This is the final part of vector instruction support for s390x.
Part 1: Vector Support Instructions
Part 2: Vector Integer Instructions
Part 3: Vector String Instructions
Part 4: Vector Floating-Point Instructions
The current state can be found at (kept updated):
https://github.com/davidhildenbrand/qemu/tree/vx
It is based on:
- [PATCH v2 0/5] s390x/tcg: Vector Instruction Support Part 3
- [PATCH v1 0/2] s390x: Fix vector register alignment
With the current state I can boot Linux kernel + user space compiled with
SIMD support. This allows to boot distributions compiled exclusively for
z13, requiring SIMD support. Also, it is now possible to build a complete
kernel using rpmbuild as quite some issues have been sorted out.
While the current state works fine for me with RHEL 8, I am experiencing
some issues with newer userspace versions. I already found and fixed
some stack overflow protection issues (stfle instruction). I still see
random rpm database corruptions and rpmbuild doesn't work correctly
(looks like another stack protection issue).
In this part, all Vector Floating-Point Instructions introduced with the
"Vector Facility" are added. Also, the "qemu" model is changed to a
z13 machine.
v1 -> v2:
- get rid of make_float64() and float64_val().
- fixed two cc calculation issues (thanks Richard)
- Rework "VECTOR FP COMPARE (EQUAL|HIGH|HIGH OR EQUAL)"
- Rework "VECTOR FP MULTIPLY AND (ADD|SUBTRACT)"
- Use gvec expansion in "s390x/tcg: Implement VECTOR FP PERFORM SIGN
OPERATION"
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: Christian Borntraeger <borntraeger@de.ibm.com>
Cc: Pino Toscano <ptoscano@redhat.com>
David Hildenbrand (22):
s390x/tcg: Store only the necessary amount of doublewords for STFLE
s390x/tcg: Introduce tcg_s390_vector_exception()
s390x/tcg: Export float_comp_to_cc() and float(32|64|128)_dcmask()
s390x/tcg: Implement VECTOR FP ADD
s390x/tcg: Implement VECTOR FP COMPARE (AND SIGNAL) SCALAR
s390x/tcg: Implement VECTOR FP COMPARE (EQUAL|HIGH|HIGH OR EQUAL)
s390x/tcg: Implement VECTOR FP CONVERT FROM FIXED 64-BIT
s390x/tcg: Implement VECTOR FP CONVERT FROM LOGICAL 64-BIT
s390x/tcg: Implement VECTOR FP CONVERT TO FIXED 64-BIT
s390x/tcg: Implement VECTOR FP CONVERT TO LOGICAL 64-BIT
s390x/tcg: Implement VECTOR FP DIVIDE
s390x/tcg: Implement VECTOR LOAD FP INTEGER
s390x/tcg: Implement VECTOR LOAD LENGTHENED
s390x/tcg: Implement VECTOR LOAD ROUNDED
s390x/tcg: Implement VECTOR FP MULTIPLY
s390x/tcg: Implement VECTOR FP MULTIPLY AND (ADD|SUBTRACT)
s390x/tcg: Implement VECTOR FP PERFORM SIGN OPERATION
s390x/tcg: Implement VECTOR FP SQUARE ROOT
s390x/tcg: Implement VECTOR FP SUBTRACT
s390x/tcg: Implement VECTOR FP TEST DATA CLASS IMMEDIATE
s390x/tcg: Allow linux-user to use vector instructions
s390x/tcg: We support the Vector Facility
target/s390x/Makefile.objs | 1 +
target/s390x/cpu.c | 3 +
target/s390x/cpu.h | 1 +
target/s390x/excp_helper.c | 15 +
target/s390x/fpu_helper.c | 4 +-
target/s390x/gen-features.c | 1 +
target/s390x/helper.h | 46 +++
target/s390x/insn-data.def | 45 +++
target/s390x/internal.h | 4 +
target/s390x/misc_helper.c | 8 +-
target/s390x/tcg_s390x.h | 2 +
target/s390x/translate_vx.inc.c | 284 +++++++++++++++
target/s390x/vec_fpu_helper.c | 625 ++++++++++++++++++++++++++++++++
13 files changed, 1036 insertions(+), 3 deletions(-)
create mode 100644 target/s390x/vec_fpu_helper.c
--
2.21.0
^ permalink raw reply [flat|nested] 34+ messages in thread
* [Qemu-devel] [PATCH v2 01/22] s390x/tcg: Store only the necessary amount of doublewords for STFLE
2019-06-03 9:06 [Qemu-devel] [PATCH v2 00/22] s390x/tcg: Vector Instruction Support Part 4 David Hildenbrand
@ 2019-06-03 9:06 ` David Hildenbrand
2019-06-03 9:07 ` David Hildenbrand
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 02/22] s390x/tcg: Introduce tcg_s390_vector_exception() David Hildenbrand
` (22 subsequent siblings)
23 siblings, 1 reply; 34+ messages in thread
From: David Hildenbrand @ 2019-06-03 9:06 UTC (permalink / raw)
To: qemu-devel
Cc: Stefan Liebler, Thomas Huth, Denys Vlasenko, David Hildenbrand,
Andreas Krebbel, Cornelia Huck, Richard Henderson, Pino Toscano,
Christian Borntraeger, qemu-s390x, Richard Henderson
The PoP (z14, 7-382) says:
Doublewords to the right of the doubleword in which the
highest-numbered facility bit is assigned for a model
may or may not be stored.
However, stack protection in certain binaries can't deal with that.
"gzip" example code:
f1b4: a7 08 00 03 lhi %r0,3
f1b8: b2 b0 f0 a0 stfle 160(%r15)
f1bc: e3 20 f0 b2 00 90 llgc %r2,178(%r15)
f1c2: c0 2b 00 00 00 01 nilf %r2,1
f1c8: b2 4f 00 10 ear %r1,%a0
f1cc: b9 14 00 22 lgfr %r2,%r2
f1d0: eb 11 00 20 00 0d sllg %r1,%r1,32
f1d6: b2 4f 00 11 ear %r1,%a1
f1da: d5 07 f0 b8 10 28 clc 184(8,%r15),40(%r1)
f1e0: a7 74 00 06 jne f1ec <file_read@@Base+0x1bc>
f1e4: eb ef f1 30 00 04 lmg %r14,%r15,304(%r15)
f1ea: 07 fe br %r14
f1ec: c0 e5 ff ff 9d 6e brasl %r14,2cc8 <__stack_chk_fail@plt>
In QEMU, we currently have:
max_bytes = 24
the code asks for (3 + 1) doublewords == 32 bytes.
If we write 32 bytes instead of only 24, and return "2 + 1" doublewords
("one less than the number of doulewords needed to contain all of the
facility bits"), the example code detects a stack corruption.
In my opinion, the code is wrong. However, it seems to work fine on
real machines. So let's limit storing to the minimum of the requested
and the maximum doublewords.
Cc: Stefan Liebler <stli@linux.ibm.com>
Cc: Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/misc_helper.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/target/s390x/misc_helper.c b/target/s390x/misc_helper.c
index 34476134a4..10aa617cf9 100644
--- a/target/s390x/misc_helper.c
+++ b/target/s390x/misc_helper.c
@@ -678,7 +678,13 @@ uint32_t HELPER(stfle)(CPUS390XState *env, uint64_t addr)
prepare_stfl();
max_bytes = ROUND_UP(used_stfl_bytes, 8);
- for (i = 0; i < count_bytes; ++i) {
+
+ /*
+ * The PoP says that doublewords beyond the highest-numbered facility
+ * bit may or may not be stored. However, existing hardware appears to
+ * not store the words, and existing software depend on that.
+ */
+ for (i = 0; i < MIN(count_bytes, max_bytes); ++i) {
cpu_stb_data_ra(env, addr + i, stfl_bytes[i], ra);
}
--
2.21.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Qemu-devel] [PATCH v2 02/22] s390x/tcg: Introduce tcg_s390_vector_exception()
2019-06-03 9:06 [Qemu-devel] [PATCH v2 00/22] s390x/tcg: Vector Instruction Support Part 4 David Hildenbrand
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 01/22] s390x/tcg: Store only the necessary amount of doublewords for STFLE David Hildenbrand
@ 2019-06-03 9:06 ` David Hildenbrand
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 03/22] s390x/tcg: Export float_comp_to_cc() and float(32|64|128)_dcmask() David Hildenbrand
` (21 subsequent siblings)
23 siblings, 0 replies; 34+ messages in thread
From: David Hildenbrand @ 2019-06-03 9:06 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Denys Vlasenko, David Hildenbrand, Cornelia Huck,
Pino Toscano, Christian Borntraeger, qemu-s390x,
Richard Henderson
Handling is similar to data exceptions, however we can always store the
VXC into the lowore and the FPC:
z14 PoP, 6-20, "Vector-Exception Code"
When a vector-processing exception causes a pro-
gram interruption, a vector-exception code (VXC) is
stored at location 147, and zeros are stored at loca-
tions 144-146. The VXC is also placed in the DXC
field of the floating-point-control (FPC) register if bit
45 of control register 0 is one. When bit 45 of control
register 0 is zero and bit 46 of control register 0 is
one, the DXC field of the FPC register and the con-
tents of storage at location 147 are unpredictable.
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/cpu.h | 1 +
target/s390x/excp_helper.c | 15 +++++++++++++++
target/s390x/tcg_s390x.h | 2 ++
3 files changed, 18 insertions(+)
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 317a1377e6..4fc08a2c88 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -215,6 +215,7 @@ extern const struct VMStateDescription vmstate_s390_cpu;
#define PGM_SPECIAL_OP 0x0013
#define PGM_OPERAND 0x0015
#define PGM_TRACE_TABLE 0x0016
+#define PGM_VECTOR_PROCESSING 0x001b
#define PGM_SPACE_SWITCH 0x001c
#define PGM_HFP_SQRT 0x001d
#define PGM_PC_TRANS_SPEC 0x001f
diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c
index 85223d00c0..f21bcf79ae 100644
--- a/target/s390x/excp_helper.c
+++ b/target/s390x/excp_helper.c
@@ -62,6 +62,21 @@ void QEMU_NORETURN tcg_s390_data_exception(CPUS390XState *env, uint32_t dxc,
tcg_s390_program_interrupt(env, PGM_DATA, ILEN_AUTO, ra);
}
+void QEMU_NORETURN tcg_s390_vector_exception(CPUS390XState *env, uint32_t vxc,
+ uintptr_t ra)
+{
+ g_assert(vxc <= 0xff);
+#if !defined(CONFIG_USER_ONLY)
+ /* Always store the VXC into the lowcore, without AFP it is undefined */
+ stl_phys(CPU(s390_env_get_cpu(env))->as,
+ env->psa + offsetof(LowCore, data_exc_code), vxc);
+#endif
+
+ /* Always store the VXC into the FPC, without AFP it is undefined */
+ env->fpc = deposit32(env->fpc, 8, 8, vxc);
+ tcg_s390_program_interrupt(env, PGM_VECTOR_PROCESSING, ILEN_AUTO, ra);
+}
+
void HELPER(data_exception)(CPUS390XState *env, uint32_t dxc)
{
tcg_s390_data_exception(env, dxc, GETPC());
diff --git a/target/s390x/tcg_s390x.h b/target/s390x/tcg_s390x.h
index ab2c4ba703..2813f9d48e 100644
--- a/target/s390x/tcg_s390x.h
+++ b/target/s390x/tcg_s390x.h
@@ -18,5 +18,7 @@ void QEMU_NORETURN tcg_s390_program_interrupt(CPUS390XState *env, uint32_t code,
int ilen, uintptr_t ra);
void QEMU_NORETURN tcg_s390_data_exception(CPUS390XState *env, uint32_t dxc,
uintptr_t ra);
+void QEMU_NORETURN tcg_s390_vector_exception(CPUS390XState *env, uint32_t vxc,
+ uintptr_t ra);
#endif /* TCG_S390X_H */
--
2.21.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Qemu-devel] [PATCH v2 03/22] s390x/tcg: Export float_comp_to_cc() and float(32|64|128)_dcmask()
2019-06-03 9:06 [Qemu-devel] [PATCH v2 00/22] s390x/tcg: Vector Instruction Support Part 4 David Hildenbrand
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 01/22] s390x/tcg: Store only the necessary amount of doublewords for STFLE David Hildenbrand
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 02/22] s390x/tcg: Introduce tcg_s390_vector_exception() David Hildenbrand
@ 2019-06-03 9:06 ` David Hildenbrand
2019-06-03 16:17 ` Richard Henderson
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 04/22] s390x/tcg: Implement VECTOR FP ADD David Hildenbrand
` (20 subsequent siblings)
23 siblings, 1 reply; 34+ messages in thread
From: David Hildenbrand @ 2019-06-03 9:06 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Denys Vlasenko, David Hildenbrand, Cornelia Huck,
Pino Toscano, Christian Borntraeger, qemu-s390x,
Richard Henderson
Vector floating-point instructions will require these functions, so
allow to use them from other files.
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/fpu_helper.c | 4 ++--
target/s390x/internal.h | 4 ++++
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/target/s390x/fpu_helper.c b/target/s390x/fpu_helper.c
index 1be68bafea..d2c17ed942 100644
--- a/target/s390x/fpu_helper.c
+++ b/target/s390x/fpu_helper.c
@@ -112,7 +112,7 @@ static void handle_exceptions(CPUS390XState *env, bool XxC, uintptr_t retaddr)
}
}
-static inline int float_comp_to_cc(CPUS390XState *env, int float_compare)
+int float_comp_to_cc(CPUS390XState *env, int float_compare)
{
S390CPU *cpu = s390_env_get_cpu(env);
@@ -746,7 +746,7 @@ static inline uint16_t dcmask(int bit, bool neg)
}
#define DEF_FLOAT_DCMASK(_TYPE) \
-static uint16_t _TYPE##_dcmask(CPUS390XState *env, _TYPE f1) \
+uint16_t _TYPE##_dcmask(CPUS390XState *env, _TYPE f1) \
{ \
const bool neg = _TYPE##_is_neg(f1); \
\
diff --git a/target/s390x/internal.h b/target/s390x/internal.h
index 9893fc094b..c243fa725b 100644
--- a/target/s390x/internal.h
+++ b/target/s390x/internal.h
@@ -285,6 +285,10 @@ uint32_t set_cc_nz_f128(float128 v);
uint8_t s390_softfloat_exc_to_ieee(unsigned int exc);
int s390_swap_bfp_rounding_mode(CPUS390XState *env, int m3);
void s390_restore_bfp_rounding_mode(CPUS390XState *env, int old_mode);
+int float_comp_to_cc(CPUS390XState *env, int float_compare);
+uint16_t float32_dcmask(CPUS390XState *env, float32 f1);
+uint16_t float64_dcmask(CPUS390XState *env, float64 f1);
+uint16_t float128_dcmask(CPUS390XState *env, float128 f1);
/* gdbstub.c */
--
2.21.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Qemu-devel] [PATCH v2 04/22] s390x/tcg: Implement VECTOR FP ADD
2019-06-03 9:06 [Qemu-devel] [PATCH v2 00/22] s390x/tcg: Vector Instruction Support Part 4 David Hildenbrand
` (2 preceding siblings ...)
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 03/22] s390x/tcg: Export float_comp_to_cc() and float(32|64|128)_dcmask() David Hildenbrand
@ 2019-06-03 9:06 ` David Hildenbrand
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 05/22] s390x/tcg: Implement VECTOR FP COMPARE (AND SIGNAL) SCALAR David Hildenbrand
` (19 subsequent siblings)
23 siblings, 0 replies; 34+ messages in thread
From: David Hildenbrand @ 2019-06-03 9:06 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Denys Vlasenko, David Hildenbrand, Cornelia Huck,
Richard Henderson, Pino Toscano, Christian Borntraeger,
qemu-s390x, Richard Henderson
1. We'll reuse op_vfa() for similar instructions later, prepare for
that.
2. We'll reuse vop64_3() for other instructions later.
3. Take care of modifying the vector register only if no trap happened.
- on traps, flags are not updated and no elements are modified
- traps don't modify the fpc flags
- without traps, all exceptions of all elements are merged
4. We'll reuse check_ieee_exc() later when we need the XxC flag.
We have to check for exceptions after processing each element.
Provide separate handlers for single/all element processing. We'll do
the same for all applicable FP instructions.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/Makefile.objs | 1 +
target/s390x/helper.h | 4 ++
target/s390x/insn-data.def | 5 ++
target/s390x/translate_vx.inc.c | 29 ++++++++
target/s390x/vec_fpu_helper.c | 119 ++++++++++++++++++++++++++++++++
5 files changed, 158 insertions(+)
create mode 100644 target/s390x/vec_fpu_helper.c
diff --git a/target/s390x/Makefile.objs b/target/s390x/Makefile.objs
index ffdd484ef0..3e2745594a 100644
--- a/target/s390x/Makefile.objs
+++ b/target/s390x/Makefile.objs
@@ -2,6 +2,7 @@ obj-y += cpu.o cpu_models.o cpu_features.o gdbstub.o interrupt.o helper.o
obj-$(CONFIG_TCG) += translate.o cc_helper.o excp_helper.o fpu_helper.o
obj-$(CONFIG_TCG) += int_helper.o mem_helper.o misc_helper.o crypto_helper.o
obj-$(CONFIG_TCG) += vec_helper.o vec_int_helper.o vec_string_helper.o
+obj-$(CONFIG_TCG) += vec_fpu_helper.o
obj-$(CONFIG_SOFTMMU) += machine.o ioinst.o arch_dump.o mmu_helper.o diag.o
obj-$(CONFIG_SOFTMMU) += sigp.o
obj-$(CONFIG_KVM) += kvm.o
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 5db67779d3..21658a2771 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -249,6 +249,10 @@ DEF_HELPER_6(gvec_vstrc_cc_rt8, void, ptr, cptr, cptr, cptr, env, i32)
DEF_HELPER_6(gvec_vstrc_cc_rt16, void, ptr, cptr, cptr, cptr, env, i32)
DEF_HELPER_6(gvec_vstrc_cc_rt32, void, ptr, cptr, cptr, cptr, env, i32)
+/* === Vector Floating-Point Instructions */
+DEF_HELPER_FLAGS_5(gvec_vfa64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
+DEF_HELPER_FLAGS_5(gvec_vfa64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
+
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
DEF_HELPER_4(diag, void, env, i32, i32, i32)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index a2969fab58..79892f6042 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1204,6 +1204,11 @@
/* VECTOR STRING RANGE COMPARE */
F(0xe78a, VSTRC, VRR_d, V, 0, 0, 0, 0, vstrc, 0, IF_VEC)
+/* === Vector Floating-Point Instructions */
+
+/* VECTOR FP ADD */
+ F(0xe7e3, VFA, VRR_c, V, 0, 0, 0, 0, vfa, 0, IF_VEC)
+
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
E(0xb250, CSP, RRE, Z, r1_32u, ra2, r1_P, 0, csp, 0, MO_TEUL, IF_PRIV)
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index f26ffa2895..44da9f2645 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -52,6 +52,11 @@
#define ES_64 MO_64
#define ES_128 4
+/* Floating-Point Format */
+#define FPF_SHORT 2
+#define FPF_LONG 3
+#define FPF_EXT 4
+
static inline bool valid_vec_element(uint8_t enr, TCGMemOp es)
{
return !(enr & ~(NUM_VEC_ELEMENTS(es) - 1));
@@ -2538,3 +2543,27 @@ static DisasJumpType op_vstrc(DisasContext *s, DisasOps *o)
}
return DISAS_NEXT;
}
+
+static DisasJumpType op_vfa(DisasContext *s, DisasOps *o)
+{
+ const uint8_t fpf = get_field(s->fields, m4);
+ const uint8_t m5 = get_field(s->fields, m5);
+ const bool se = extract32(m5, 3, 1);
+ gen_helper_gvec_3_ptr *fn;
+
+ if (fpf != FPF_LONG || extract32(m5, 0, 3)) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ switch (s->fields->op2) {
+ case 0xe3:
+ fn = se ? gen_helper_gvec_vfa64s : gen_helper_gvec_vfa64;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ gen_gvec_3_ptr(get_field(s->fields, v1), get_field(s->fields, v2),
+ get_field(s->fields, v3), cpu_env, 0, fn);
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_fpu_helper.c b/target/s390x/vec_fpu_helper.c
new file mode 100644
index 0000000000..c7db0791d7
--- /dev/null
+++ b/target/s390x/vec_fpu_helper.c
@@ -0,0 +1,119 @@
+/*
+ * QEMU TCG support -- s390x vector floating point instruction support
+ *
+ * Copyright (C) 2019 Red Hat Inc
+ *
+ * Authors:
+ * David Hildenbrand <david@redhat.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "cpu.h"
+#include "internal.h"
+#include "vec.h"
+#include "tcg_s390x.h"
+#include "tcg/tcg-gvec-desc.h"
+#include "exec/exec-all.h"
+#include "exec/helper-proto.h"
+#include "fpu/softfloat.h"
+
+#define VIC_INVALID 0x1
+#define VIC_DIVBYZERO 0x2
+#define VIC_OVERFLOW 0x3
+#define VIC_UNDERFLOW 0x4
+#define VIC_INEXACT 0x5
+
+/* returns the VEX. If the VEX is 0, there is no trap */
+static uint8_t check_ieee_exc(CPUS390XState *env, uint8_t enr, bool XxC,
+ uint8_t *vec_exc)
+{
+ uint8_t vece_exc = 0, trap_exc;
+ unsigned qemu_exc;
+
+ /* Retrieve and clear the softfloat exceptions */
+ qemu_exc = env->fpu_status.float_exception_flags;
+ if (qemu_exc == 0) {
+ return 0;
+ }
+ env->fpu_status.float_exception_flags = 0;
+
+ vece_exc = s390_softfloat_exc_to_ieee(qemu_exc);
+
+ /* Add them to the vector-wide s390x exception bits */
+ *vec_exc |= vece_exc;
+
+ /* Check for traps and construct the VXC */
+ trap_exc = vece_exc & env->fpc >> 24;
+ if (trap_exc) {
+ if (trap_exc & S390_IEEE_MASK_INVALID) {
+ return enr << 4 | VIC_INVALID;
+ } else if (trap_exc & S390_IEEE_MASK_DIVBYZERO) {
+ return enr << 4 | VIC_DIVBYZERO;
+ } else if (trap_exc & S390_IEEE_MASK_OVERFLOW) {
+ return enr << 4 | VIC_OVERFLOW;
+ } else if (trap_exc & S390_IEEE_MASK_UNDERFLOW) {
+ return enr << 4 | VIC_UNDERFLOW;
+ } else if (!XxC) {
+ g_assert(trap_exc & S390_IEEE_MASK_INEXACT);
+ /* inexact has lowest priority on traps */
+ return enr << 4 | VIC_INEXACT;
+ }
+ }
+ return 0;
+}
+
+static void handle_ieee_exc(CPUS390XState *env, uint8_t vxc, uint8_t vec_exc,
+ uintptr_t retaddr)
+{
+ if (vxc) {
+ /* on traps, the fpc flags are not updated, instruction is suppressed */
+ tcg_s390_vector_exception(env, vxc, retaddr);
+ }
+ if (vec_exc) {
+ /* indicate exceptions for all elements combined */
+ env->fpc |= vec_exc << 16;
+ }
+}
+
+typedef uint64_t (*vop64_3_fn)(uint64_t a, uint64_t b, float_status *s);
+static void vop64_3(S390Vector *v1, const S390Vector *v2, const S390Vector *v3,
+ CPUS390XState *env, bool s, vop64_3_fn fn,
+ uintptr_t retaddr)
+{
+ uint8_t vxc, vec_exc = 0;
+ S390Vector tmp = {};
+ int i;
+
+ for (i = 0; i < 2; i++) {
+ const uint64_t a = s390_vec_read_element64(v2, i);
+ const uint64_t b = s390_vec_read_element64(v3, i);
+
+ s390_vec_write_element64(&tmp, i, fn(a, b, &env->fpu_status));
+ vxc = check_ieee_exc(env, i, false, &vec_exc);
+ if (s || vxc) {
+ break;
+ }
+ }
+ handle_ieee_exc(env, vxc, vec_exc, retaddr);
+ *v1 = tmp;
+}
+
+static uint64_t vfa64(uint64_t a, uint64_t b, float_status *s)
+{
+ return float64_add(a, b, s);
+}
+
+void HELPER(gvec_vfa64)(void *v1, const void *v2, const void *v3,
+ CPUS390XState *env, uint32_t desc)
+{
+ vop64_3(v1, v2, v3, env, false, vfa64, GETPC());
+}
+
+void HELPER(gvec_vfa64s)(void *v1, const void *v2, const void *v3,
+ CPUS390XState *env, uint32_t desc)
+{
+ vop64_3(v1, v2, v3, env, true, vfa64, GETPC());
+}
--
2.21.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Qemu-devel] [PATCH v2 05/22] s390x/tcg: Implement VECTOR FP COMPARE (AND SIGNAL) SCALAR
2019-06-03 9:06 [Qemu-devel] [PATCH v2 00/22] s390x/tcg: Vector Instruction Support Part 4 David Hildenbrand
` (3 preceding siblings ...)
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 04/22] s390x/tcg: Implement VECTOR FP ADD David Hildenbrand
@ 2019-06-03 9:06 ` David Hildenbrand
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 06/22] s390x/tcg: Implement VECTOR FP COMPARE (EQUAL|HIGH|HIGH OR EQUAL) David Hildenbrand
` (18 subsequent siblings)
23 siblings, 0 replies; 34+ messages in thread
From: David Hildenbrand @ 2019-06-03 9:06 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Denys Vlasenko, David Hildenbrand, Cornelia Huck,
Richard Henderson, Pino Toscano, Christian Borntraeger,
qemu-s390x, Richard Henderson
As far as I can see, there is only a tiny difference.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 4 ++++
target/s390x/translate_vx.inc.c | 21 +++++++++++++++++++++
target/s390x/vec_fpu_helper.c | 32 ++++++++++++++++++++++++++++++++
4 files changed, 59 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 21658a2771..d34d6802a6 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -252,6 +252,8 @@ DEF_HELPER_6(gvec_vstrc_cc_rt32, void, ptr, cptr, cptr, cptr, env, i32)
/* === Vector Floating-Point Instructions */
DEF_HELPER_FLAGS_5(gvec_vfa64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vfa64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
+DEF_HELPER_4(gvec_wfc64, void, cptr, cptr, env, i32)
+DEF_HELPER_4(gvec_wfk64, void, cptr, cptr, env, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 79892f6042..c45e101b10 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1208,6 +1208,10 @@
/* VECTOR FP ADD */
F(0xe7e3, VFA, VRR_c, V, 0, 0, 0, 0, vfa, 0, IF_VEC)
+/* VECTOR FP COMPARE SCALAR */
+ F(0xe7cb, WFC, VRR_a, V, 0, 0, 0, 0, wfc, 0, IF_VEC)
+/* VECTOR FP COMPARE AND SIGNAL SCALAR */
+ F(0xe7ca, WFK, VRR_a, V, 0, 0, 0, 0, wfc, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 44da9f2645..283e8aa07a 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -2567,3 +2567,24 @@ static DisasJumpType op_vfa(DisasContext *s, DisasOps *o)
get_field(s->fields, v3), cpu_env, 0, fn);
return DISAS_NEXT;
}
+
+static DisasJumpType op_wfc(DisasContext *s, DisasOps *o)
+{
+ const uint8_t fpf = get_field(s->fields, m3);
+ const uint8_t m4 = get_field(s->fields, m4);
+
+ if (fpf != FPF_LONG || m4) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ if (s->fields->op2 == 0xcb) {
+ gen_gvec_2_ptr(get_field(s->fields, v1), get_field(s->fields, v2),
+ cpu_env, 0, gen_helper_gvec_wfc64);
+ } else {
+ gen_gvec_2_ptr(get_field(s->fields, v1), get_field(s->fields, v2),
+ cpu_env, 0, gen_helper_gvec_wfk64);
+ }
+ set_cc_static(s);
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_fpu_helper.c b/target/s390x/vec_fpu_helper.c
index c7db0791d7..f9357d9221 100644
--- a/target/s390x/vec_fpu_helper.c
+++ b/target/s390x/vec_fpu_helper.c
@@ -117,3 +117,35 @@ void HELPER(gvec_vfa64s)(void *v1, const void *v2, const void *v3,
{
vop64_3(v1, v2, v3, env, true, vfa64, GETPC());
}
+
+static int wfc64(const S390Vector *v1, const S390Vector *v2,
+ CPUS390XState *env, bool signal, uintptr_t retaddr)
+{
+ /* only the zero-indexed elements are compared */
+ const float64 a = s390_vec_read_element64(v1, 0);
+ const float64 b = s390_vec_read_element64(v2, 0);
+ uint8_t vxc, vec_exc = 0;
+ int cmp;
+
+ if (signal) {
+ cmp = float64_compare(a, b, &env->fpu_status);
+ } else {
+ cmp = float64_compare_quiet(a, b, &env->fpu_status);
+ }
+ vxc = check_ieee_exc(env, 0, false, &vec_exc);
+ handle_ieee_exc(env, vxc, vec_exc, retaddr);
+
+ return float_comp_to_cc(env, cmp);
+}
+
+void HELPER(gvec_wfc64)(const void *v1, const void *v2, CPUS390XState *env,
+ uint32_t desc)
+{
+ env->cc_op = wfc64(v1, v2, env, false, GETPC());
+}
+
+void HELPER(gvec_wfk64)(const void *v1, const void *v2, CPUS390XState *env,
+ uint32_t desc)
+{
+ env->cc_op = wfc64(v1, v2, env, true, GETPC());
+}
--
2.21.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Qemu-devel] [PATCH v2 06/22] s390x/tcg: Implement VECTOR FP COMPARE (EQUAL|HIGH|HIGH OR EQUAL)
2019-06-03 9:06 [Qemu-devel] [PATCH v2 00/22] s390x/tcg: Vector Instruction Support Part 4 David Hildenbrand
` (4 preceding siblings ...)
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 05/22] s390x/tcg: Implement VECTOR FP COMPARE (AND SIGNAL) SCALAR David Hildenbrand
@ 2019-06-03 9:06 ` David Hildenbrand
2019-06-05 9:19 ` David Hildenbrand
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 07/22] s390x/tcg: Implement VECTOR FP CONVERT FROM FIXED 64-BIT David Hildenbrand
` (17 subsequent siblings)
23 siblings, 1 reply; 34+ messages in thread
From: David Hildenbrand @ 2019-06-03 9:06 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Denys Vlasenko, David Hildenbrand, Cornelia Huck,
Pino Toscano, Christian Borntraeger, qemu-s390x,
Richard Henderson
Provide for all three instructions all four combinations of cc bit and
s bit.
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 12 ++++
target/s390x/insn-data.def | 6 ++
target/s390x/translate_vx.inc.c | 51 ++++++++++++++++
target/s390x/vec_fpu_helper.c | 104 ++++++++++++++++++++++++++++++++
4 files changed, 173 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index d34d6802a6..33d3bacf74 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -254,6 +254,18 @@ DEF_HELPER_FLAGS_5(gvec_vfa64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vfa64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_4(gvec_wfc64, void, cptr, cptr, env, i32)
DEF_HELPER_4(gvec_wfk64, void, cptr, cptr, env, i32)
+DEF_HELPER_FLAGS_5(gvec_vfce64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
+DEF_HELPER_FLAGS_5(gvec_vfce64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
+DEF_HELPER_5(gvec_vfce64_cc, void, ptr, cptr, cptr, env, i32)
+DEF_HELPER_5(gvec_vfce64s_cc, void, ptr, cptr, cptr, env, i32)
+DEF_HELPER_FLAGS_5(gvec_vfch64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
+DEF_HELPER_FLAGS_5(gvec_vfch64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
+DEF_HELPER_5(gvec_vfch64_cc, void, ptr, cptr, cptr, env, i32)
+DEF_HELPER_5(gvec_vfch64s_cc, void, ptr, cptr, cptr, env, i32)
+DEF_HELPER_FLAGS_5(gvec_vfche64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
+DEF_HELPER_FLAGS_5(gvec_vfche64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
+DEF_HELPER_5(gvec_vfche64_cc, void, ptr, cptr, cptr, env, i32)
+DEF_HELPER_5(gvec_vfche64s_cc, void, ptr, cptr, cptr, env, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index c45e101b10..446552f251 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1212,6 +1212,12 @@
F(0xe7cb, WFC, VRR_a, V, 0, 0, 0, 0, wfc, 0, IF_VEC)
/* VECTOR FP COMPARE AND SIGNAL SCALAR */
F(0xe7ca, WFK, VRR_a, V, 0, 0, 0, 0, wfc, 0, IF_VEC)
+/* VECTOR FP COMPARE EQUAL */
+ F(0xe7e8, VFCE, VRR_c, V, 0, 0, 0, 0, vfc, 0, IF_VEC)
+/* VECTOR FP COMPARE HIGH */
+ F(0xe7eb, VFCH, VRR_c, V, 0, 0, 0, 0, vfc, 0, IF_VEC)
+/* VECTOR FP COMPARE HIGH OR EQUAL */
+ F(0xe7ea, VFCHE, VRR_c, V, 0, 0, 0, 0, vfc, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 283e8aa07a..5571a71e1a 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -2588,3 +2588,54 @@ static DisasJumpType op_wfc(DisasContext *s, DisasOps *o)
set_cc_static(s);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vfc(DisasContext *s, DisasOps *o)
+{
+ const uint8_t fpf = get_field(s->fields, m4);
+ const uint8_t m5 = get_field(s->fields, m5);
+ const uint8_t m6 = get_field(s->fields, m6);
+ const bool se = extract32(m5, 3, 1);
+ const bool cs = extract32(m6, 0, 1);
+ gen_helper_gvec_3_ptr *fn;
+
+ if (fpf != FPF_LONG || extract32(m5, 0, 3) || extract32(m6, 1, 3)) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ if (cs) {
+ switch (s->fields->op2) {
+ case 0xe8:
+ fn = se ? gen_helper_gvec_vfce64s_cc : gen_helper_gvec_vfce64_cc;
+ break;
+ case 0xeb:
+ fn = se ? gen_helper_gvec_vfch64s_cc : gen_helper_gvec_vfch64_cc;
+ break;
+ case 0xea:
+ fn = se ? gen_helper_gvec_vfche64s_cc : gen_helper_gvec_vfche64_cc;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ } else {
+ switch (s->fields->op2) {
+ case 0xe8:
+ fn = se ? gen_helper_gvec_vfce64s : gen_helper_gvec_vfce64;
+ break;
+ case 0xeb:
+ fn = se ? gen_helper_gvec_vfch64s : gen_helper_gvec_vfch64;
+ break;
+ case 0xea:
+ fn = se ? gen_helper_gvec_vfche64s : gen_helper_gvec_vfche64;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ }
+ gen_gvec_3_ptr(get_field(s->fields, v1), get_field(s->fields, v2),
+ get_field(s->fields, v3), cpu_env, 0, fn);
+ if (cs) {
+ set_cc_static(s);
+ }
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_fpu_helper.c b/target/s390x/vec_fpu_helper.c
index f9357d9221..e72500d4d5 100644
--- a/target/s390x/vec_fpu_helper.c
+++ b/target/s390x/vec_fpu_helper.c
@@ -149,3 +149,107 @@ void HELPER(gvec_wfk64)(const void *v1, const void *v2, CPUS390XState *env,
{
env->cc_op = wfc64(v1, v2, env, true, GETPC());
}
+
+typedef int (*vfc64_fn)(float64 a, float64 b, float_status *status);
+static int vfc64(S390Vector *v1, const S390Vector *v2, const S390Vector *v3,
+ CPUS390XState *env, bool s, vfc64_fn fn, uintptr_t retaddr)
+{
+ uint8_t vxc, vec_exc = 0;
+ S390Vector tmp = {};
+ int match = 0;
+ int i;
+
+ for (i = 0; i < 2; i++) {
+ const float64 a = s390_vec_read_element64(v2, i);
+ const float64 b = s390_vec_read_element64(v3, i);
+
+ /* swap the order of the parameters, so we can use existing functions */
+ if (fn(b, a, &env->fpu_status)) {
+ match++;
+ s390_vec_write_element64(&tmp, i, -1ull);
+ }
+ vxc = check_ieee_exc(env, i, false, &vec_exc);
+ if (s || vxc) {
+ break;
+ }
+ }
+
+ handle_ieee_exc(env, vxc, vec_exc, retaddr);
+ *v1 = tmp;
+ if (match) {
+ return s || match == 2 ? 0 : 1;
+ }
+ return 3;
+}
+
+void HELPER(gvec_vfce64)(void *v1, const void *v2, const void *v3,
+ CPUS390XState *env, uint32_t desc)
+{
+ vfc64(v1, v2, v3, env, false, float64_eq_quiet, GETPC());
+}
+
+void HELPER(gvec_vfce64s)(void *v1, const void *v2, const void *v3,
+ CPUS390XState *env, uint32_t desc)
+{
+ vfc64(v1, v2, v3, env, true, float64_eq_quiet, GETPC());
+}
+
+void HELPER(gvec_vfce64_cc)(void *v1, const void *v2, const void *v3,
+ CPUS390XState *env, uint32_t desc)
+{
+ env->cc_op = vfc64(v1, v2, v3, env, false, float64_eq_quiet, GETPC());
+}
+
+void HELPER(gvec_vfce64s_cc)(void *v1, const void *v2, const void *v3,
+ CPUS390XState *env, uint32_t desc)
+{
+ env->cc_op = vfc64(v1, v2, v3, env, true, float64_eq_quiet, GETPC());
+}
+
+void HELPER(gvec_vfch64)(void *v1, const void *v2, const void *v3,
+ CPUS390XState *env, uint32_t desc)
+{
+ vfc64(v1, v2, v3, env, false, float64_lt_quiet, GETPC());
+}
+
+void HELPER(gvec_vfch64s)(void *v1, const void *v2, const void *v3,
+ CPUS390XState *env, uint32_t desc)
+{
+ vfc64(v1, v2, v3, env, true, float64_lt_quiet, GETPC());
+}
+
+void HELPER(gvec_vfch64_cc)(void *v1, const void *v2, const void *v3,
+ CPUS390XState *env, uint32_t desc)
+{
+ env->cc_op = vfc64(v1, v2, v3, env, false, float64_lt_quiet, GETPC());
+}
+
+void HELPER(gvec_vfch64s_cc)(void *v1, const void *v2, const void *v3,
+ CPUS390XState *env, uint32_t desc)
+{
+ env->cc_op = vfc64(v1, v2, v3, env, true, float64_lt_quiet, GETPC());
+}
+
+void HELPER(gvec_vfche64)(void *v1, const void *v2, const void *v3,
+ CPUS390XState *env, uint32_t desc)
+{
+ vfc64(v1, v2, v3, env, false, float64_le_quiet, GETPC());
+}
+
+void HELPER(gvec_vfche64s)(void *v1, const void *v2, const void *v3,
+ CPUS390XState *env, uint32_t desc)
+{
+ vfc64(v1, v2, v3, env, true, float64_le_quiet, GETPC());
+}
+
+void HELPER(gvec_vfche64_cc)(void *v1, const void *v2, const void *v3,
+ CPUS390XState *env, uint32_t desc)
+{
+ env->cc_op = vfc64(v1, v2, v3, env, false, float64_le_quiet, GETPC());
+}
+
+void HELPER(gvec_vfche64s_cc)(void *v1, const void *v2, const void *v3,
+ CPUS390XState *env, uint32_t desc)
+{
+ env->cc_op = vfc64(v1, v2, v3, env, true, float64_le_quiet, GETPC());
+}
--
2.21.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Qemu-devel] [PATCH v2 07/22] s390x/tcg: Implement VECTOR FP CONVERT FROM FIXED 64-BIT
2019-06-03 9:06 [Qemu-devel] [PATCH v2 00/22] s390x/tcg: Vector Instruction Support Part 4 David Hildenbrand
` (5 preceding siblings ...)
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 06/22] s390x/tcg: Implement VECTOR FP COMPARE (EQUAL|HIGH|HIGH OR EQUAL) David Hildenbrand
@ 2019-06-03 9:06 ` David Hildenbrand
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 08/22] s390x/tcg: Implement VECTOR FP CONVERT FROM LOGICAL 64-BIT David Hildenbrand
` (16 subsequent siblings)
23 siblings, 0 replies; 34+ messages in thread
From: David Hildenbrand @ 2019-06-03 9:06 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Denys Vlasenko, David Hildenbrand, Cornelia Huck,
Richard Henderson, Pino Toscano, Christian Borntraeger,
qemu-s390x, Richard Henderson
1. We'll reuse op_vcdg() for similar instructions later, prepare for
that.
2. We'll reuse vop64_2() later for other instructions.
We have to mangle the erm (effective rounding mode) and the m4 into
the simd_data(), and properly unmangle them again.
Make sure to restore the erm before triggering an exception.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 25 ++++++++++++++++++
target/s390x/vec_fpu_helper.c | 47 +++++++++++++++++++++++++++++++++
4 files changed, 76 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 33d3bacf74..a60f4c49fc 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -266,6 +266,8 @@ DEF_HELPER_FLAGS_5(gvec_vfche64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32
DEF_HELPER_FLAGS_5(gvec_vfche64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_5(gvec_vfche64_cc, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_5(gvec_vfche64s_cc, void, ptr, cptr, cptr, env, i32)
+DEF_HELPER_FLAGS_4(gvec_vcdg64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
+DEF_HELPER_FLAGS_4(gvec_vcdg64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 446552f251..d3386024c8 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1218,6 +1218,8 @@
F(0xe7eb, VFCH, VRR_c, V, 0, 0, 0, 0, vfc, 0, IF_VEC)
/* VECTOR FP COMPARE HIGH OR EQUAL */
F(0xe7ea, VFCHE, VRR_c, V, 0, 0, 0, 0, vfc, 0, IF_VEC)
+/* VECTOR FP CONVERT FROM FIXED 64-BIT */
+ F(0xe7c3, VCDG, VRR_a, V, 0, 0, 0, 0, vcdg, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 5571a71e1a..6741b707cc 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -2639,3 +2639,28 @@ static DisasJumpType op_vfc(DisasContext *s, DisasOps *o)
}
return DISAS_NEXT;
}
+
+static DisasJumpType op_vcdg(DisasContext *s, DisasOps *o)
+{
+ const uint8_t fpf = get_field(s->fields, m3);
+ const uint8_t m4 = get_field(s->fields, m4);
+ const uint8_t erm = get_field(s->fields, m5);
+ const bool se = extract32(m4, 3, 1);
+ gen_helper_gvec_2_ptr *fn;
+
+ if (fpf != FPF_LONG || extract32(m4, 0, 2) || erm > 7 || erm == 2) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ switch (s->fields->op2) {
+ case 0xc3:
+ fn = se ? gen_helper_gvec_vcdg64s : gen_helper_gvec_vcdg64;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ gen_gvec_2_ptr(get_field(s->fields, v1), get_field(s->fields, v2), cpu_env,
+ deposit32(m4, 4, 4, erm), fn);
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_fpu_helper.c b/target/s390x/vec_fpu_helper.c
index e72500d4d5..53430c7843 100644
--- a/target/s390x/vec_fpu_helper.c
+++ b/target/s390x/vec_fpu_helper.c
@@ -78,6 +78,30 @@ static void handle_ieee_exc(CPUS390XState *env, uint8_t vxc, uint8_t vec_exc,
}
}
+typedef uint64_t (*vop64_2_fn)(uint64_t a, float_status *s);
+static void vop64_2(S390Vector *v1, const S390Vector *v2, CPUS390XState *env,
+ bool s, bool XxC, uint8_t erm, vop64_2_fn fn,
+ uintptr_t retaddr)
+{
+ uint8_t vxc, vec_exc = 0;
+ S390Vector tmp = {};
+ int i, old_mode;
+
+ old_mode = s390_swap_bfp_rounding_mode(env, erm);
+ for (i = 0; i < 2; i++) {
+ const uint64_t a = s390_vec_read_element64(v2, i);
+
+ s390_vec_write_element64(&tmp, i, fn(a, &env->fpu_status));
+ vxc = check_ieee_exc(env, i, XxC, &vec_exc);
+ if (s || vxc) {
+ break;
+ }
+ }
+ s390_restore_bfp_rounding_mode(env, old_mode);
+ handle_ieee_exc(env, vxc, vec_exc, retaddr);
+ *v1 = tmp;
+}
+
typedef uint64_t (*vop64_3_fn)(uint64_t a, uint64_t b, float_status *s);
static void vop64_3(S390Vector *v1, const S390Vector *v2, const S390Vector *v3,
CPUS390XState *env, bool s, vop64_3_fn fn,
@@ -253,3 +277,26 @@ void HELPER(gvec_vfche64s_cc)(void *v1, const void *v2, const void *v3,
{
env->cc_op = vfc64(v1, v2, v3, env, true, float64_le_quiet, GETPC());
}
+
+static uint64_t vcdg64(uint64_t a, float_status *s)
+{
+ return int64_to_float64(a, s);
+}
+
+void HELPER(gvec_vcdg64)(void *v1, const void *v2, CPUS390XState *env,
+ uint32_t desc)
+{
+ const uint8_t erm = extract32(simd_data(desc), 4, 4);
+ const bool XxC = extract32(simd_data(desc), 2, 1);
+
+ vop64_2(v1, v2, env, false, XxC, erm, vcdg64, GETPC());
+}
+
+void HELPER(gvec_vcdg64s)(void *v1, const void *v2, CPUS390XState *env,
+ uint32_t desc)
+{
+ const uint8_t erm = extract32(simd_data(desc), 4, 4);
+ const bool XxC = extract32(simd_data(desc), 2, 1);
+
+ vop64_2(v1, v2, env, true, XxC, erm, vcdg64, GETPC());
+}
--
2.21.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Qemu-devel] [PATCH v2 08/22] s390x/tcg: Implement VECTOR FP CONVERT FROM LOGICAL 64-BIT
2019-06-03 9:06 [Qemu-devel] [PATCH v2 00/22] s390x/tcg: Vector Instruction Support Part 4 David Hildenbrand
` (6 preceding siblings ...)
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 07/22] s390x/tcg: Implement VECTOR FP CONVERT FROM FIXED 64-BIT David Hildenbrand
@ 2019-06-03 9:06 ` David Hildenbrand
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 09/22] s390x/tcg: Implement VECTOR FP CONVERT TO FIXED 64-BIT David Hildenbrand
` (15 subsequent siblings)
23 siblings, 0 replies; 34+ messages in thread
From: David Hildenbrand @ 2019-06-03 9:06 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Denys Vlasenko, David Hildenbrand, Cornelia Huck,
Richard Henderson, Pino Toscano, Christian Borntraeger,
qemu-s390x, Richard Henderson
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 3 +++
target/s390x/vec_fpu_helper.c | 23 +++++++++++++++++++++++
4 files changed, 30 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index a60f4c49fc..6fd996e924 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -268,6 +268,8 @@ DEF_HELPER_5(gvec_vfche64_cc, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_5(gvec_vfche64s_cc, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vcdg64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vcdg64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
+DEF_HELPER_FLAGS_4(gvec_vcdlg64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
+DEF_HELPER_FLAGS_4(gvec_vcdlg64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index d3386024c8..465b36dd70 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1220,6 +1220,8 @@
F(0xe7ea, VFCHE, VRR_c, V, 0, 0, 0, 0, vfc, 0, IF_VEC)
/* VECTOR FP CONVERT FROM FIXED 64-BIT */
F(0xe7c3, VCDG, VRR_a, V, 0, 0, 0, 0, vcdg, 0, IF_VEC)
+/* VECTOR FP CONVERT FROM LOGICAL 64-BIT */
+ F(0xe7c1, VCDLG, VRR_a, V, 0, 0, 0, 0, vcdg, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 6741b707cc..fa755cd1d6 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -2657,6 +2657,9 @@ static DisasJumpType op_vcdg(DisasContext *s, DisasOps *o)
case 0xc3:
fn = se ? gen_helper_gvec_vcdg64s : gen_helper_gvec_vcdg64;
break;
+ case 0xc1:
+ fn = se ? gen_helper_gvec_vcdlg64s : gen_helper_gvec_vcdlg64;
+ break;
default:
g_assert_not_reached();
}
diff --git a/target/s390x/vec_fpu_helper.c b/target/s390x/vec_fpu_helper.c
index 53430c7843..181378e167 100644
--- a/target/s390x/vec_fpu_helper.c
+++ b/target/s390x/vec_fpu_helper.c
@@ -300,3 +300,26 @@ void HELPER(gvec_vcdg64s)(void *v1, const void *v2, CPUS390XState *env,
vop64_2(v1, v2, env, true, XxC, erm, vcdg64, GETPC());
}
+
+static uint64_t vcdlg64(uint64_t a, float_status *s)
+{
+ return uint64_to_float64(a, s);
+}
+
+void HELPER(gvec_vcdlg64)(void *v1, const void *v2, CPUS390XState *env,
+ uint32_t desc)
+{
+ const uint8_t erm = extract32(simd_data(desc), 4, 4);
+ const bool XxC = extract32(simd_data(desc), 2, 1);
+
+ vop64_2(v1, v2, env, false, XxC, erm, vcdlg64, GETPC());
+}
+
+void HELPER(gvec_vcdlg64s)(void *v1, const void *v2, CPUS390XState *env,
+ uint32_t desc)
+{
+ const uint8_t erm = extract32(simd_data(desc), 4, 4);
+ const bool XxC = extract32(simd_data(desc), 2, 1);
+
+ vop64_2(v1, v2, env, true, XxC, erm, vcdlg64, GETPC());
+}
--
2.21.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Qemu-devel] [PATCH v2 09/22] s390x/tcg: Implement VECTOR FP CONVERT TO FIXED 64-BIT
2019-06-03 9:06 [Qemu-devel] [PATCH v2 00/22] s390x/tcg: Vector Instruction Support Part 4 David Hildenbrand
` (7 preceding siblings ...)
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 08/22] s390x/tcg: Implement VECTOR FP CONVERT FROM LOGICAL 64-BIT David Hildenbrand
@ 2019-06-03 9:06 ` David Hildenbrand
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 10/22] s390x/tcg: Implement VECTOR FP CONVERT TO LOGICAL 64-BIT David Hildenbrand
` (14 subsequent siblings)
23 siblings, 0 replies; 34+ messages in thread
From: David Hildenbrand @ 2019-06-03 9:06 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Denys Vlasenko, David Hildenbrand, Cornelia Huck,
Richard Henderson, Pino Toscano, Christian Borntraeger,
qemu-s390x, Richard Henderson
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 3 +++
target/s390x/vec_fpu_helper.c | 23 +++++++++++++++++++++++
4 files changed, 30 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 6fd996e924..9893c677da 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -270,6 +270,8 @@ DEF_HELPER_FLAGS_4(gvec_vcdg64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vcdg64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vcdlg64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vcdlg64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
+DEF_HELPER_FLAGS_4(gvec_vcgd64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
+DEF_HELPER_FLAGS_4(gvec_vcgd64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 465b36dd70..97c62a8af5 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1222,6 +1222,8 @@
F(0xe7c3, VCDG, VRR_a, V, 0, 0, 0, 0, vcdg, 0, IF_VEC)
/* VECTOR FP CONVERT FROM LOGICAL 64-BIT */
F(0xe7c1, VCDLG, VRR_a, V, 0, 0, 0, 0, vcdg, 0, IF_VEC)
+/* VECTOR FP CONVERT TO FIXED 64-BIT */
+ F(0xe7c2, VCGD, VRR_a, V, 0, 0, 0, 0, vcdg, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index fa755cd1d6..a42de2ff01 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -2660,6 +2660,9 @@ static DisasJumpType op_vcdg(DisasContext *s, DisasOps *o)
case 0xc1:
fn = se ? gen_helper_gvec_vcdlg64s : gen_helper_gvec_vcdlg64;
break;
+ case 0xc2:
+ fn = se ? gen_helper_gvec_vcgd64s : gen_helper_gvec_vcgd64;
+ break;
default:
g_assert_not_reached();
}
diff --git a/target/s390x/vec_fpu_helper.c b/target/s390x/vec_fpu_helper.c
index 181378e167..e7251aca04 100644
--- a/target/s390x/vec_fpu_helper.c
+++ b/target/s390x/vec_fpu_helper.c
@@ -323,3 +323,26 @@ void HELPER(gvec_vcdlg64s)(void *v1, const void *v2, CPUS390XState *env,
vop64_2(v1, v2, env, true, XxC, erm, vcdlg64, GETPC());
}
+
+static uint64_t vcgd64(uint64_t a, float_status *s)
+{
+ return float64_to_int64(a, s);
+}
+
+void HELPER(gvec_vcgd64)(void *v1, const void *v2, CPUS390XState *env,
+ uint32_t desc)
+{
+ const uint8_t erm = extract32(simd_data(desc), 4, 4);
+ const bool XxC = extract32(simd_data(desc), 2, 1);
+
+ vop64_2(v1, v2, env, false, XxC, erm, vcgd64, GETPC());
+}
+
+void HELPER(gvec_vcgd64s)(void *v1, const void *v2, CPUS390XState *env,
+ uint32_t desc)
+{
+ const uint8_t erm = extract32(simd_data(desc), 4, 4);
+ const bool XxC = extract32(simd_data(desc), 2, 1);
+
+ vop64_2(v1, v2, env, true, XxC, erm, vcgd64, GETPC());
+}
--
2.21.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Qemu-devel] [PATCH v2 10/22] s390x/tcg: Implement VECTOR FP CONVERT TO LOGICAL 64-BIT
2019-06-03 9:06 [Qemu-devel] [PATCH v2 00/22] s390x/tcg: Vector Instruction Support Part 4 David Hildenbrand
` (8 preceding siblings ...)
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 09/22] s390x/tcg: Implement VECTOR FP CONVERT TO FIXED 64-BIT David Hildenbrand
@ 2019-06-03 9:06 ` David Hildenbrand
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 11/22] s390x/tcg: Implement VECTOR FP DIVIDE David Hildenbrand
` (13 subsequent siblings)
23 siblings, 0 replies; 34+ messages in thread
From: David Hildenbrand @ 2019-06-03 9:06 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Denys Vlasenko, David Hildenbrand, Cornelia Huck,
Richard Henderson, Pino Toscano, Christian Borntraeger,
qemu-s390x, Richard Henderson
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 3 +++
target/s390x/vec_fpu_helper.c | 23 +++++++++++++++++++++++
4 files changed, 30 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 9893c677da..9b9062970a 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -272,6 +272,8 @@ DEF_HELPER_FLAGS_4(gvec_vcdlg64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vcdlg64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vcgd64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vcgd64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
+DEF_HELPER_FLAGS_4(gvec_vclgd64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
+DEF_HELPER_FLAGS_4(gvec_vclgd64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 97c62a8af5..ed8b888d59 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1224,6 +1224,8 @@
F(0xe7c1, VCDLG, VRR_a, V, 0, 0, 0, 0, vcdg, 0, IF_VEC)
/* VECTOR FP CONVERT TO FIXED 64-BIT */
F(0xe7c2, VCGD, VRR_a, V, 0, 0, 0, 0, vcdg, 0, IF_VEC)
+/* VECTOR FP CONVERT TO LOGICAL 64-BIT */
+ F(0xe7c0, VCLGD, VRR_a, V, 0, 0, 0, 0, vcdg, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index a42de2ff01..0395d69968 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -2663,6 +2663,9 @@ static DisasJumpType op_vcdg(DisasContext *s, DisasOps *o)
case 0xc2:
fn = se ? gen_helper_gvec_vcgd64s : gen_helper_gvec_vcgd64;
break;
+ case 0xc0:
+ fn = se ? gen_helper_gvec_vclgd64s : gen_helper_gvec_vclgd64;
+ break;
default:
g_assert_not_reached();
}
diff --git a/target/s390x/vec_fpu_helper.c b/target/s390x/vec_fpu_helper.c
index e7251aca04..09ef0abfb0 100644
--- a/target/s390x/vec_fpu_helper.c
+++ b/target/s390x/vec_fpu_helper.c
@@ -346,3 +346,26 @@ void HELPER(gvec_vcgd64s)(void *v1, const void *v2, CPUS390XState *env,
vop64_2(v1, v2, env, true, XxC, erm, vcgd64, GETPC());
}
+
+static uint64_t vclgd64(uint64_t a, float_status *s)
+{
+ return float64_to_uint64(a, s);
+}
+
+void HELPER(gvec_vclgd64)(void *v1, const void *v2, CPUS390XState *env,
+ uint32_t desc)
+{
+ const uint8_t erm = extract32(simd_data(desc), 4, 4);
+ const bool XxC = extract32(simd_data(desc), 2, 1);
+
+ vop64_2(v1, v2, env, false, XxC, erm, vclgd64, GETPC());
+}
+
+void HELPER(gvec_vclgd64s)(void *v1, const void *v2, CPUS390XState *env,
+ uint32_t desc)
+{
+ const uint8_t erm = extract32(simd_data(desc), 4, 4);
+ const bool XxC = extract32(simd_data(desc), 2, 1);
+
+ vop64_2(v1, v2, env, true, XxC, erm, vclgd64, GETPC());
+}
--
2.21.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Qemu-devel] [PATCH v2 11/22] s390x/tcg: Implement VECTOR FP DIVIDE
2019-06-03 9:06 [Qemu-devel] [PATCH v2 00/22] s390x/tcg: Vector Instruction Support Part 4 David Hildenbrand
` (9 preceding siblings ...)
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 10/22] s390x/tcg: Implement VECTOR FP CONVERT TO LOGICAL 64-BIT David Hildenbrand
@ 2019-06-03 9:06 ` David Hildenbrand
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 12/22] s390x/tcg: Implement VECTOR LOAD FP INTEGER David Hildenbrand
` (12 subsequent siblings)
23 siblings, 0 replies; 34+ messages in thread
From: David Hildenbrand @ 2019-06-03 9:06 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Denys Vlasenko, David Hildenbrand, Cornelia Huck,
Richard Henderson, Pino Toscano, Christian Borntraeger,
qemu-s390x, Richard Henderson
We can reuse most of the infrastructure added for VECTOR FP ADD.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 3 +++
target/s390x/vec_fpu_helper.c | 17 +++++++++++++++++
4 files changed, 24 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 9b9062970a..238bfa2509 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -274,6 +274,8 @@ DEF_HELPER_FLAGS_4(gvec_vcgd64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vcgd64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vclgd64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vclgd64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
+DEF_HELPER_FLAGS_5(gvec_vfd64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
+DEF_HELPER_FLAGS_5(gvec_vfd64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index ed8b888d59..f9830deace 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1226,6 +1226,8 @@
F(0xe7c2, VCGD, VRR_a, V, 0, 0, 0, 0, vcdg, 0, IF_VEC)
/* VECTOR FP CONVERT TO LOGICAL 64-BIT */
F(0xe7c0, VCLGD, VRR_a, V, 0, 0, 0, 0, vcdg, 0, IF_VEC)
+/* VECTOR FP DIVIDE */
+ F(0xe7e5, VFD, VRR_c, V, 0, 0, 0, 0, vfa, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 0395d69968..9e55d4488b 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -2560,6 +2560,9 @@ static DisasJumpType op_vfa(DisasContext *s, DisasOps *o)
case 0xe3:
fn = se ? gen_helper_gvec_vfa64s : gen_helper_gvec_vfa64;
break;
+ case 0xe5:
+ fn = se ? gen_helper_gvec_vfd64s : gen_helper_gvec_vfd64;
+ break;
default:
g_assert_not_reached();
}
diff --git a/target/s390x/vec_fpu_helper.c b/target/s390x/vec_fpu_helper.c
index 09ef0abfb0..3c62eb5787 100644
--- a/target/s390x/vec_fpu_helper.c
+++ b/target/s390x/vec_fpu_helper.c
@@ -369,3 +369,20 @@ void HELPER(gvec_vclgd64s)(void *v1, const void *v2, CPUS390XState *env,
vop64_2(v1, v2, env, true, XxC, erm, vclgd64, GETPC());
}
+
+static uint64_t vfd64(uint64_t a, uint64_t b, float_status *s)
+{
+ return float64_div(a, b, s);
+}
+
+void HELPER(gvec_vfd64)(void *v1, const void *v2, const void *v3,
+ CPUS390XState *env, uint32_t desc)
+{
+ vop64_3(v1, v2, v3, env, false, vfd64, GETPC());
+}
+
+void HELPER(gvec_vfd64s)(void *v1, const void *v2, const void *v3,
+ CPUS390XState *env, uint32_t desc)
+{
+ vop64_3(v1, v2, v3, env, true, vfd64, GETPC());
+}
--
2.21.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Qemu-devel] [PATCH v2 12/22] s390x/tcg: Implement VECTOR LOAD FP INTEGER
2019-06-03 9:06 [Qemu-devel] [PATCH v2 00/22] s390x/tcg: Vector Instruction Support Part 4 David Hildenbrand
` (10 preceding siblings ...)
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 11/22] s390x/tcg: Implement VECTOR FP DIVIDE David Hildenbrand
@ 2019-06-03 9:06 ` David Hildenbrand
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 13/22] s390x/tcg: Implement VECTOR LOAD LENGTHENED David Hildenbrand
` (11 subsequent siblings)
23 siblings, 0 replies; 34+ messages in thread
From: David Hildenbrand @ 2019-06-03 9:06 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Denys Vlasenko, David Hildenbrand, Cornelia Huck,
Richard Henderson, Pino Toscano, Christian Borntraeger,
qemu-s390x, Richard Henderson
We can reuse most of the infrastructure introduced for
VECTOR FP CONVERT FROM FIXED 64-BIT and friends.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 3 +++
target/s390x/vec_fpu_helper.c | 23 +++++++++++++++++++++++
4 files changed, 30 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 238bfa2509..10a9cb39b6 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -276,6 +276,8 @@ DEF_HELPER_FLAGS_4(gvec_vclgd64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vclgd64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vfd64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vfd64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
+DEF_HELPER_FLAGS_4(gvec_vfi64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
+DEF_HELPER_FLAGS_4(gvec_vfi64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index f9830deace..f77aa41253 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1228,6 +1228,8 @@
F(0xe7c0, VCLGD, VRR_a, V, 0, 0, 0, 0, vcdg, 0, IF_VEC)
/* VECTOR FP DIVIDE */
F(0xe7e5, VFD, VRR_c, V, 0, 0, 0, 0, vfa, 0, IF_VEC)
+/* VECTOR LOAD FP INTEGER */
+ F(0xe7c7, VFI, VRR_a, V, 0, 0, 0, 0, vcdg, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 9e55d4488b..59d8b971c0 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -2669,6 +2669,9 @@ static DisasJumpType op_vcdg(DisasContext *s, DisasOps *o)
case 0xc0:
fn = se ? gen_helper_gvec_vclgd64s : gen_helper_gvec_vclgd64;
break;
+ case 0xc7:
+ fn = se ? gen_helper_gvec_vfi64s : gen_helper_gvec_vfi64;
+ break;
default:
g_assert_not_reached();
}
diff --git a/target/s390x/vec_fpu_helper.c b/target/s390x/vec_fpu_helper.c
index 3c62eb5787..bdcafc6738 100644
--- a/target/s390x/vec_fpu_helper.c
+++ b/target/s390x/vec_fpu_helper.c
@@ -386,3 +386,26 @@ void HELPER(gvec_vfd64s)(void *v1, const void *v2, const void *v3,
{
vop64_3(v1, v2, v3, env, true, vfd64, GETPC());
}
+
+static uint64_t vfi64(uint64_t a, float_status *s)
+{
+ return float64_round_to_int(a, s);
+}
+
+void HELPER(gvec_vfi64)(void *v1, const void *v2, CPUS390XState *env,
+ uint32_t desc)
+{
+ const uint8_t erm = extract32(simd_data(desc), 4, 4);
+ const bool XxC = extract32(simd_data(desc), 2, 1);
+
+ vop64_2(v1, v2, env, false, XxC, erm, vfi64, GETPC());
+}
+
+void HELPER(gvec_vfi64s)(void *v1, const void *v2, CPUS390XState *env,
+ uint32_t desc)
+{
+ const uint8_t erm = extract32(simd_data(desc), 4, 4);
+ const bool XxC = extract32(simd_data(desc), 2, 1);
+
+ vop64_2(v1, v2, env, true, XxC, erm, vfi64, GETPC());
+}
--
2.21.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Qemu-devel] [PATCH v2 13/22] s390x/tcg: Implement VECTOR LOAD LENGTHENED
2019-06-03 9:06 [Qemu-devel] [PATCH v2 00/22] s390x/tcg: Vector Instruction Support Part 4 David Hildenbrand
` (11 preceding siblings ...)
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 12/22] s390x/tcg: Implement VECTOR LOAD FP INTEGER David Hildenbrand
@ 2019-06-03 9:06 ` David Hildenbrand
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 14/22] s390x/tcg: Implement VECTOR LOAD ROUNDED David Hildenbrand
` (10 subsequent siblings)
23 siblings, 0 replies; 34+ messages in thread
From: David Hildenbrand @ 2019-06-03 9:06 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Denys Vlasenko, David Hildenbrand, Cornelia Huck,
Richard Henderson, Pino Toscano, Christian Borntraeger,
qemu-s390x, Richard Henderson
Take care of reading/indicating the 32-bit elements.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 19 ++++++++++++++++++
target/s390x/vec_fpu_helper.c | 35 +++++++++++++++++++++++++++++++++
4 files changed, 58 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 10a9cb39b6..cb25141ffe 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -278,6 +278,8 @@ DEF_HELPER_FLAGS_5(gvec_vfd64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vfd64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vfi64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vfi64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
+DEF_HELPER_FLAGS_4(gvec_vfll32, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
+DEF_HELPER_FLAGS_4(gvec_vfll32s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index f77aa41253..5afdb36aec 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1230,6 +1230,8 @@
F(0xe7e5, VFD, VRR_c, V, 0, 0, 0, 0, vfa, 0, IF_VEC)
/* VECTOR LOAD FP INTEGER */
F(0xe7c7, VFI, VRR_a, V, 0, 0, 0, 0, vcdg, 0, IF_VEC)
+/* VECTOR LOAD LENGTHENED */
+ F(0xe7c4, VFLL, VRR_a, V, 0, 0, 0, 0, vfll, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 59d8b971c0..a25985e5c9 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -2679,3 +2679,22 @@ static DisasJumpType op_vcdg(DisasContext *s, DisasOps *o)
deposit32(m4, 4, 4, erm), fn);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vfll(DisasContext *s, DisasOps *o)
+{
+ const uint8_t fpf = get_field(s->fields, m3);
+ const uint8_t m4 = get_field(s->fields, m4);
+ gen_helper_gvec_2_ptr *fn = gen_helper_gvec_vfll32;
+
+ if (fpf != FPF_SHORT || extract32(m4, 0, 3)) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ if (extract32(m4, 3, 1)) {
+ fn = gen_helper_gvec_vfll32s;
+ }
+ gen_gvec_2_ptr(get_field(s->fields, v1), get_field(s->fields, v2), cpu_env,
+ 0, fn);
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_fpu_helper.c b/target/s390x/vec_fpu_helper.c
index bdcafc6738..f5b7fdf871 100644
--- a/target/s390x/vec_fpu_helper.c
+++ b/target/s390x/vec_fpu_helper.c
@@ -409,3 +409,38 @@ void HELPER(gvec_vfi64s)(void *v1, const void *v2, CPUS390XState *env,
vop64_2(v1, v2, env, true, XxC, erm, vfi64, GETPC());
}
+
+static void vfll32(S390Vector *v1, const S390Vector *v2, CPUS390XState *env,
+ bool s, uintptr_t retaddr)
+{
+ uint8_t vxc, vec_exc = 0;
+ S390Vector tmp = {};
+ int i;
+
+ for (i = 0; i < 2; i++) {
+ /* load from even element */
+ const float32 a = s390_vec_read_element32(v2, i * 2);
+ const uint64_t ret = float32_to_float64(a, &env->fpu_status);
+
+ s390_vec_write_element64(&tmp, i, ret);
+ /* indicate the source element */
+ vxc = check_ieee_exc(env, i * 2, false, &vec_exc);
+ if (s || vxc) {
+ break;
+ }
+ }
+ handle_ieee_exc(env, vxc, vec_exc, retaddr);
+ *v1 = tmp;
+}
+
+void HELPER(gvec_vfll32)(void *v1, const void *v2, CPUS390XState *env,
+ uint32_t desc)
+{
+ vfll32(v1, v2, env, false, GETPC());
+}
+
+void HELPER(gvec_vfll32s)(void *v1, const void *v2, CPUS390XState *env,
+ uint32_t desc)
+{
+ vfll32(v1, v2, env, true, GETPC());
+}
--
2.21.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Qemu-devel] [PATCH v2 14/22] s390x/tcg: Implement VECTOR LOAD ROUNDED
2019-06-03 9:06 [Qemu-devel] [PATCH v2 00/22] s390x/tcg: Vector Instruction Support Part 4 David Hildenbrand
` (12 preceding siblings ...)
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 13/22] s390x/tcg: Implement VECTOR LOAD LENGTHENED David Hildenbrand
@ 2019-06-03 9:06 ` David Hildenbrand
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 15/22] s390x/tcg: Implement VECTOR FP MULTIPLY David Hildenbrand
` (9 subsequent siblings)
23 siblings, 0 replies; 34+ messages in thread
From: David Hildenbrand @ 2019-06-03 9:06 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Denys Vlasenko, David Hildenbrand, Cornelia Huck,
Richard Henderson, Pino Toscano, Christian Borntraeger,
qemu-s390x, Richard Henderson
We can reuse some of the infrastructure introduced for
VECTOR FP CONVERT FROM FIXED 64-BIT and friends.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 3 +++
target/s390x/vec_fpu_helper.c | 43 +++++++++++++++++++++++++++++++++
4 files changed, 50 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index cb25141ffe..7526f8e8c6 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -280,6 +280,8 @@ DEF_HELPER_FLAGS_4(gvec_vfi64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vfi64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vfll32, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vfll32s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
+DEF_HELPER_FLAGS_4(gvec_vflr64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
+DEF_HELPER_FLAGS_4(gvec_vflr64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 5afdb36aec..f03914d528 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1232,6 +1232,8 @@
F(0xe7c7, VFI, VRR_a, V, 0, 0, 0, 0, vcdg, 0, IF_VEC)
/* VECTOR LOAD LENGTHENED */
F(0xe7c4, VFLL, VRR_a, V, 0, 0, 0, 0, vfll, 0, IF_VEC)
+/* VECTOR LOAD ROUNDED */
+ F(0xe7c5, VFLR, VRR_a, V, 0, 0, 0, 0, vcdg, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index a25985e5c9..73e1b1062a 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -2672,6 +2672,9 @@ static DisasJumpType op_vcdg(DisasContext *s, DisasOps *o)
case 0xc7:
fn = se ? gen_helper_gvec_vfi64s : gen_helper_gvec_vfi64;
break;
+ case 0xc5:
+ fn = se ? gen_helper_gvec_vflr64s : gen_helper_gvec_vflr64;
+ break;
default:
g_assert_not_reached();
}
diff --git a/target/s390x/vec_fpu_helper.c b/target/s390x/vec_fpu_helper.c
index f5b7fdf871..764f7379da 100644
--- a/target/s390x/vec_fpu_helper.c
+++ b/target/s390x/vec_fpu_helper.c
@@ -444,3 +444,46 @@ void HELPER(gvec_vfll32s)(void *v1, const void *v2, CPUS390XState *env,
{
vfll32(v1, v2, env, true, GETPC());
}
+
+static void vflr64(S390Vector *v1, const S390Vector *v2, CPUS390XState *env,
+ bool s, bool XxC, uint8_t erm, uintptr_t retaddr)
+{
+ uint8_t vxc, vec_exc = 0;
+ S390Vector tmp = {};
+ int i, old_mode;
+
+ old_mode = s390_swap_bfp_rounding_mode(env, erm);
+ for (i = 0; i < 2; i++) {
+ float64 a = s390_vec_read_element64(v2, i);
+ uint32_t ret = float64_to_float32(a, &env->fpu_status);
+
+ /* place at even element */
+ s390_vec_write_element32(&tmp, i * 2, ret);
+ /* indicate the source element */
+ vxc = check_ieee_exc(env, i, XxC, &vec_exc);
+ if (s || vxc) {
+ break;
+ }
+ }
+ s390_restore_bfp_rounding_mode(env, old_mode);
+ handle_ieee_exc(env, vxc, vec_exc, retaddr);
+ *v1 = tmp;
+}
+
+void HELPER(gvec_vflr64)(void *v1, const void *v2, CPUS390XState *env,
+ uint32_t desc)
+{
+ const uint8_t erm = extract32(simd_data(desc), 4, 4);
+ const bool XxC = extract32(simd_data(desc), 2, 1);
+
+ vflr64(v1, v2, env, false, XxC, erm, GETPC());
+}
+
+void HELPER(gvec_vflr64s)(void *v1, const void *v2, CPUS390XState *env,
+ uint32_t desc)
+{
+ const uint8_t erm = extract32(simd_data(desc), 4, 4);
+ const bool XxC = extract32(simd_data(desc), 2, 1);
+
+ vflr64(v1, v2, env, true, XxC, erm, GETPC());
+}
--
2.21.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Qemu-devel] [PATCH v2 15/22] s390x/tcg: Implement VECTOR FP MULTIPLY
2019-06-03 9:06 [Qemu-devel] [PATCH v2 00/22] s390x/tcg: Vector Instruction Support Part 4 David Hildenbrand
` (13 preceding siblings ...)
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 14/22] s390x/tcg: Implement VECTOR LOAD ROUNDED David Hildenbrand
@ 2019-06-03 9:06 ` David Hildenbrand
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 16/22] s390x/tcg: Implement VECTOR FP MULTIPLY AND (ADD|SUBTRACT) David Hildenbrand
` (8 subsequent siblings)
23 siblings, 0 replies; 34+ messages in thread
From: David Hildenbrand @ 2019-06-03 9:06 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Denys Vlasenko, David Hildenbrand, Cornelia Huck,
Richard Henderson, Pino Toscano, Christian Borntraeger,
qemu-s390x, Richard Henderson
Very similar to VECTOR FP DIVIDE.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 3 +++
target/s390x/vec_fpu_helper.c | 17 +++++++++++++++++
4 files changed, 24 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 7526f8e8c6..22e02a0178 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -282,6 +282,8 @@ DEF_HELPER_FLAGS_4(gvec_vfll32, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vfll32s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vflr64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vflr64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
+DEF_HELPER_FLAGS_5(gvec_vfm64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
+DEF_HELPER_FLAGS_5(gvec_vfm64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index f03914d528..e56059ac34 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1234,6 +1234,8 @@
F(0xe7c4, VFLL, VRR_a, V, 0, 0, 0, 0, vfll, 0, IF_VEC)
/* VECTOR LOAD ROUNDED */
F(0xe7c5, VFLR, VRR_a, V, 0, 0, 0, 0, vcdg, 0, IF_VEC)
+/* VECTOR FP MULTIPLY */
+ F(0xe7e7, VFM, VRR_c, V, 0, 0, 0, 0, vfa, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 73e1b1062a..ae31a327cf 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -2563,6 +2563,9 @@ static DisasJumpType op_vfa(DisasContext *s, DisasOps *o)
case 0xe5:
fn = se ? gen_helper_gvec_vfd64s : gen_helper_gvec_vfd64;
break;
+ case 0xe7:
+ fn = se ? gen_helper_gvec_vfm64s : gen_helper_gvec_vfm64;
+ break;
default:
g_assert_not_reached();
}
diff --git a/target/s390x/vec_fpu_helper.c b/target/s390x/vec_fpu_helper.c
index 764f7379da..57b7fe4aff 100644
--- a/target/s390x/vec_fpu_helper.c
+++ b/target/s390x/vec_fpu_helper.c
@@ -487,3 +487,20 @@ void HELPER(gvec_vflr64s)(void *v1, const void *v2, CPUS390XState *env,
vflr64(v1, v2, env, true, XxC, erm, GETPC());
}
+
+static uint64_t vfm64(uint64_t a, uint64_t b, float_status *s)
+{
+ return float64_mul(a, b, s);
+}
+
+void HELPER(gvec_vfm64)(void *v1, const void *v2, const void *v3,
+ CPUS390XState *env, uint32_t desc)
+{
+ vop64_3(v1, v2, v3, env, false, vfm64, GETPC());
+}
+
+void HELPER(gvec_vfm64s)(void *v1, const void *v2, const void *v3,
+ CPUS390XState *env, uint32_t desc)
+{
+ vop64_3(v1, v2, v3, env, true, vfm64, GETPC());
+}
--
2.21.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Qemu-devel] [PATCH v2 16/22] s390x/tcg: Implement VECTOR FP MULTIPLY AND (ADD|SUBTRACT)
2019-06-03 9:06 [Qemu-devel] [PATCH v2 00/22] s390x/tcg: Vector Instruction Support Part 4 David Hildenbrand
` (14 preceding siblings ...)
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 15/22] s390x/tcg: Implement VECTOR FP MULTIPLY David Hildenbrand
@ 2019-06-03 9:06 ` David Hildenbrand
2019-06-03 16:16 ` Richard Henderson
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 17/22] s390x/tcg: Implement VECTOR FP PERFORM SIGN OPERATION David Hildenbrand
` (7 subsequent siblings)
23 siblings, 1 reply; 34+ messages in thread
From: David Hildenbrand @ 2019-06-03 9:06 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Denys Vlasenko, David Hildenbrand, Cornelia Huck,
Pino Toscano, Christian Borntraeger, qemu-s390x,
Richard Henderson
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 4 +++
target/s390x/insn-data.def | 4 +++
target/s390x/translate_vx.inc.c | 23 ++++++++++++++++
target/s390x/vec_fpu_helper.c | 48 +++++++++++++++++++++++++++++++++
4 files changed, 79 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 22e02a0178..bcaabb91a5 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -284,6 +284,10 @@ DEF_HELPER_FLAGS_4(gvec_vflr64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vflr64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vfm64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vfm64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
+DEF_HELPER_FLAGS_6(gvec_vfma64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env, i32)
+DEF_HELPER_FLAGS_6(gvec_vfma64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env, i32)
+DEF_HELPER_FLAGS_6(gvec_vfms64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env, i32)
+DEF_HELPER_FLAGS_6(gvec_vfms64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index e56059ac34..e86ade9e44 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1236,6 +1236,10 @@
F(0xe7c5, VFLR, VRR_a, V, 0, 0, 0, 0, vcdg, 0, IF_VEC)
/* VECTOR FP MULTIPLY */
F(0xe7e7, VFM, VRR_c, V, 0, 0, 0, 0, vfa, 0, IF_VEC)
+/* VECTOR FP MULTIPLY AND ADD */
+ F(0xe78f, VFMA, VRR_e, V, 0, 0, 0, 0, vfma, 0, IF_VEC)
+/* VECTOR FP MULTIPLY AND SUBTRACT */
+ F(0xe78e, VFMS, VRR_e, V, 0, 0, 0, 0, vfma, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index ae31a327cf..b624c7a8aa 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -2704,3 +2704,26 @@ static DisasJumpType op_vfll(DisasContext *s, DisasOps *o)
0, fn);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vfma(DisasContext *s, DisasOps *o)
+{
+ const uint8_t m5 = get_field(s->fields, m5);
+ const uint8_t fpf = get_field(s->fields, m6);
+ const bool se = extract32(m5, 3, 1);
+ gen_helper_gvec_4_ptr *fn;
+
+ if (fpf != FPF_LONG || extract32(m5, 0, 3)) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ if (s->fields->op2 == 0x8f) {
+ fn = se ? gen_helper_gvec_vfma64s : gen_helper_gvec_vfma64;
+ } else {
+ fn = se ? gen_helper_gvec_vfms64s : gen_helper_gvec_vfms64;
+ }
+ gen_gvec_4_ptr(get_field(s->fields, v1), get_field(s->fields, v2),
+ get_field(s->fields, v3), get_field(s->fields, v4), cpu_env,
+ 0, fn);
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_fpu_helper.c b/target/s390x/vec_fpu_helper.c
index 57b7fe4aff..7993a6fafa 100644
--- a/target/s390x/vec_fpu_helper.c
+++ b/target/s390x/vec_fpu_helper.c
@@ -504,3 +504,51 @@ void HELPER(gvec_vfm64s)(void *v1, const void *v2, const void *v3,
{
vop64_3(v1, v2, v3, env, true, vfm64, GETPC());
}
+
+static void vfma64(S390Vector *v1, const S390Vector *v2, const S390Vector *v3,
+ const S390Vector *v4, CPUS390XState *env, bool s, int flags,
+ uintptr_t retaddr)
+{
+ uint8_t vxc, vec_exc = 0;
+ S390Vector tmp = {};
+ int i;
+
+ for (i = 0; i < 2; i++) {
+ const uint64_t a = s390_vec_read_element64(v2, i);
+ const uint64_t b = s390_vec_read_element64(v3, i);
+ const uint64_t c = s390_vec_read_element64(v4, i);
+ uint64_t ret = float64_muladd(a, b, c, flags, &env->fpu_status);
+
+ s390_vec_write_element64(&tmp, i, ret);
+ vxc = check_ieee_exc(env, i, false, &vec_exc);
+ if (s || vxc) {
+ break;
+ }
+ }
+ handle_ieee_exc(env, vxc, vec_exc, retaddr);
+ *v1 = tmp;
+}
+
+void HELPER(gvec_vfma64)(void *v1, const void *v2, const void *v3,
+ const void *v4, CPUS390XState *env, uint32_t desc)
+{
+ vfma64(v1, v2, v3, v4, env, false, 0, GETPC());
+}
+
+void HELPER(gvec_vfma64s)(void *v1, const void *v2, const void *v3,
+ const void *v4, CPUS390XState *env, uint32_t desc)
+{
+ vfma64(v1, v2, v3, v4, env, true, 0, GETPC());
+}
+
+void HELPER(gvec_vfms64)(void *v1, const void *v2, const void *v3,
+ const void *v4, CPUS390XState *env, uint32_t desc)
+{
+ vfma64(v1, v2, v3, v4, env, false, float_muladd_negate_c, GETPC());
+}
+
+void HELPER(gvec_vfms64s)(void *v1, const void *v2, const void *v3,
+ const void *v4, CPUS390XState *env, uint32_t desc)
+{
+ vfma64(v1, v2, v3, v4, env, true, float_muladd_negate_c, GETPC());
+}
--
2.21.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Qemu-devel] [PATCH v2 17/22] s390x/tcg: Implement VECTOR FP PERFORM SIGN OPERATION
2019-06-03 9:06 [Qemu-devel] [PATCH v2 00/22] s390x/tcg: Vector Instruction Support Part 4 David Hildenbrand
` (15 preceding siblings ...)
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 16/22] s390x/tcg: Implement VECTOR FP MULTIPLY AND (ADD|SUBTRACT) David Hildenbrand
@ 2019-06-03 9:06 ` David Hildenbrand
2019-06-03 16:18 ` Richard Henderson
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 18/22] s390x/tcg: Implement VECTOR FP SQUARE ROOT David Hildenbrand
` (6 subsequent siblings)
23 siblings, 1 reply; 34+ messages in thread
From: David Hildenbrand @ 2019-06-03 9:06 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Denys Vlasenko, David Hildenbrand, Cornelia Huck,
Pino Toscano, Christian Borntraeger, qemu-s390x,
Richard Henderson
The only FP instruction we can implement without an helper.
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 52 +++++++++++++++++++++++++++++++++
2 files changed, 54 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index e86ade9e44..fa2e801747 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1240,6 +1240,8 @@
F(0xe78f, VFMA, VRR_e, V, 0, 0, 0, 0, vfma, 0, IF_VEC)
/* VECTOR FP MULTIPLY AND SUBTRACT */
F(0xe78e, VFMS, VRR_e, V, 0, 0, 0, 0, vfma, 0, IF_VEC)
+/* VECTOR FP PERFORM SIGN OPERATION */
+ F(0xe7cc, VFPSO, VRR_a, V, 0, 0, 0, 0, vfpso, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index b624c7a8aa..9b8606ba25 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -2727,3 +2727,55 @@ static DisasJumpType op_vfma(DisasContext *s, DisasOps *o)
0, fn);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vfpso(DisasContext *s, DisasOps *o)
+{
+ const uint8_t v1 = get_field(s->fields, v1);
+ const uint8_t v2 = get_field(s->fields, v2);
+ const uint8_t fpf = get_field(s->fields, m3);
+ const uint8_t m4 = get_field(s->fields, m4);
+ const uint8_t m5 = get_field(s->fields, m5);
+ TCGv_i64 tmp;
+
+ if (fpf != FPF_LONG || extract32(m4, 0, 3) || m5 > 2) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ if (extract32(m4, 3, 1)) {
+ tmp = tcg_temp_new_i64();
+ read_vec_element_i64(tmp, v2, 0, ES_64);
+ switch (m5) {
+ case 0:
+ /* sign bit is inverted (complement) */
+ tcg_gen_xori_i64(tmp, tmp, 1ull << 63);
+ break;
+ case 1:
+ /* sign bit is set to one (negative) */
+ tcg_gen_ori_i64(tmp, tmp, 1ull << 63);
+ break;
+ case 2:
+ /* sign bit is set to zero (positive) */
+ tcg_gen_andi_i64(tmp, tmp, (1ull << 63) - 1);
+ break;
+ }
+ write_vec_element_i64(tmp, v1, 0, ES_64);
+ tcg_temp_free_i64(tmp);
+ } else {
+ switch (m5) {
+ case 0:
+ /* sign bit is inverted (complement) */
+ gen_gvec_fn_2i(xori, ES_64, v1, v2, 1ull << 63);
+ break;
+ case 1:
+ /* sign bit is set to one (negative) */
+ gen_gvec_fn_2i(ori, ES_64, v1, v2, 1ull << 63);
+ break;
+ case 2:
+ /* sign bit is set to zero (positive) */
+ gen_gvec_fn_2i(andi, ES_64, v1, v2, (1ull << 63) - 1);
+ break;
+ }
+ }
+ return DISAS_NEXT;
+}
--
2.21.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Qemu-devel] [PATCH v2 18/22] s390x/tcg: Implement VECTOR FP SQUARE ROOT
2019-06-03 9:06 [Qemu-devel] [PATCH v2 00/22] s390x/tcg: Vector Instruction Support Part 4 David Hildenbrand
` (16 preceding siblings ...)
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 17/22] s390x/tcg: Implement VECTOR FP PERFORM SIGN OPERATION David Hildenbrand
@ 2019-06-03 9:06 ` David Hildenbrand
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 19/22] s390x/tcg: Implement VECTOR FP SUBTRACT David Hildenbrand
` (5 subsequent siblings)
23 siblings, 0 replies; 34+ messages in thread
From: David Hildenbrand @ 2019-06-03 9:06 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Denys Vlasenko, David Hildenbrand, Cornelia Huck,
Richard Henderson, Pino Toscano, Christian Borntraeger,
qemu-s390x, Richard Henderson
Simulate XxC=0 and ERM=0 (current mode), so we can use the existing
helper function.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 19 +++++++++++++++++++
target/s390x/vec_fpu_helper.c | 17 +++++++++++++++++
4 files changed, 40 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index bcaabb91a5..23b37af1e4 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -288,6 +288,8 @@ DEF_HELPER_FLAGS_6(gvec_vfma64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env
DEF_HELPER_FLAGS_6(gvec_vfma64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_6(gvec_vfms64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_6(gvec_vfms64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env, i32)
+DEF_HELPER_FLAGS_4(gvec_vfsq64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
+DEF_HELPER_FLAGS_4(gvec_vfsq64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index fa2e801747..354252d57c 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1242,6 +1242,8 @@
F(0xe78e, VFMS, VRR_e, V, 0, 0, 0, 0, vfma, 0, IF_VEC)
/* VECTOR FP PERFORM SIGN OPERATION */
F(0xe7cc, VFPSO, VRR_a, V, 0, 0, 0, 0, vfpso, 0, IF_VEC)
+/* VECTOR FP SQUARE ROOT */
+ F(0xe7ce, VFSQ, VRR_a, V, 0, 0, 0, 0, vfsq, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 9b8606ba25..75f3596c4b 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -2779,3 +2779,22 @@ static DisasJumpType op_vfpso(DisasContext *s, DisasOps *o)
}
return DISAS_NEXT;
}
+
+static DisasJumpType op_vfsq(DisasContext *s, DisasOps *o)
+{
+ const uint8_t fpf = get_field(s->fields, m3);
+ const uint8_t m4 = get_field(s->fields, m4);
+ gen_helper_gvec_2_ptr *fn = gen_helper_gvec_vfsq64;
+
+ if (fpf != FPF_LONG || extract32(m4, 0, 3)) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ if (extract32(m4, 3, 1)) {
+ fn = gen_helper_gvec_vfsq64s;
+ }
+ gen_gvec_2_ptr(get_field(s->fields, v1), get_field(s->fields, v2), cpu_env,
+ 0, fn);
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_fpu_helper.c b/target/s390x/vec_fpu_helper.c
index 7993a6fafa..18773eb559 100644
--- a/target/s390x/vec_fpu_helper.c
+++ b/target/s390x/vec_fpu_helper.c
@@ -552,3 +552,20 @@ void HELPER(gvec_vfms64s)(void *v1, const void *v2, const void *v3,
{
vfma64(v1, v2, v3, v4, env, true, float_muladd_negate_c, GETPC());
}
+
+static uint64_t vfsq64(uint64_t a, float_status *s)
+{
+ return float64_sqrt(a, s);
+}
+
+void HELPER(gvec_vfsq64)(void *v1, const void *v2, CPUS390XState *env,
+ uint32_t desc)
+{
+ vop64_2(v1, v2, env, false, false, 0, vfsq64, GETPC());
+}
+
+void HELPER(gvec_vfsq64s)(void *v1, const void *v2, CPUS390XState *env,
+ uint32_t desc)
+{
+ vop64_2(v1, v2, env, true, false, 0, vfsq64, GETPC());
+}
--
2.21.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Qemu-devel] [PATCH v2 19/22] s390x/tcg: Implement VECTOR FP SUBTRACT
2019-06-03 9:06 [Qemu-devel] [PATCH v2 00/22] s390x/tcg: Vector Instruction Support Part 4 David Hildenbrand
` (17 preceding siblings ...)
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 18/22] s390x/tcg: Implement VECTOR FP SQUARE ROOT David Hildenbrand
@ 2019-06-03 9:06 ` David Hildenbrand
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 20/22] s390x/tcg: Implement VECTOR FP TEST DATA CLASS IMMEDIATE David Hildenbrand
` (4 subsequent siblings)
23 siblings, 0 replies; 34+ messages in thread
From: David Hildenbrand @ 2019-06-03 9:06 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Denys Vlasenko, David Hildenbrand, Cornelia Huck,
Richard Henderson, Pino Toscano, Christian Borntraeger,
qemu-s390x, Richard Henderson
Similar to VECTOR FP ADD.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 3 +++
target/s390x/vec_fpu_helper.c | 17 +++++++++++++++++
4 files changed, 24 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 23b37af1e4..c788fc1b7f 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -290,6 +290,8 @@ DEF_HELPER_FLAGS_6(gvec_vfms64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env
DEF_HELPER_FLAGS_6(gvec_vfms64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vfsq64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vfsq64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
+DEF_HELPER_FLAGS_5(gvec_vfs64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
+DEF_HELPER_FLAGS_5(gvec_vfs64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 354252d57c..4426f40250 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1244,6 +1244,8 @@
F(0xe7cc, VFPSO, VRR_a, V, 0, 0, 0, 0, vfpso, 0, IF_VEC)
/* VECTOR FP SQUARE ROOT */
F(0xe7ce, VFSQ, VRR_a, V, 0, 0, 0, 0, vfsq, 0, IF_VEC)
+/* VECTOR FP SUBTRACT */
+ F(0xe7e2, VFS, VRR_c, V, 0, 0, 0, 0, vfa, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 75f3596c4b..c0a19aa9f3 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -2566,6 +2566,9 @@ static DisasJumpType op_vfa(DisasContext *s, DisasOps *o)
case 0xe7:
fn = se ? gen_helper_gvec_vfm64s : gen_helper_gvec_vfm64;
break;
+ case 0xe2:
+ fn = se ? gen_helper_gvec_vfs64s : gen_helper_gvec_vfs64;
+ break;
default:
g_assert_not_reached();
}
diff --git a/target/s390x/vec_fpu_helper.c b/target/s390x/vec_fpu_helper.c
index 18773eb559..ccdc975628 100644
--- a/target/s390x/vec_fpu_helper.c
+++ b/target/s390x/vec_fpu_helper.c
@@ -569,3 +569,20 @@ void HELPER(gvec_vfsq64s)(void *v1, const void *v2, CPUS390XState *env,
{
vop64_2(v1, v2, env, true, false, 0, vfsq64, GETPC());
}
+
+static uint64_t vfs64(uint64_t a, uint64_t b, float_status *s)
+{
+ return float64_sub(a, b, s);
+}
+
+void HELPER(gvec_vfs64)(void *v1, const void *v2, const void *v3,
+ CPUS390XState *env, uint32_t desc)
+{
+ vop64_3(v1, v2, v3, env, false, vfs64, GETPC());
+}
+
+void HELPER(gvec_vfs64s)(void *v1, const void *v2, const void *v3,
+ CPUS390XState *env, uint32_t desc)
+{
+ vop64_3(v1, v2, v3, env, true, vfs64, GETPC());
+}
--
2.21.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Qemu-devel] [PATCH v2 20/22] s390x/tcg: Implement VECTOR FP TEST DATA CLASS IMMEDIATE
2019-06-03 9:06 [Qemu-devel] [PATCH v2 00/22] s390x/tcg: Vector Instruction Support Part 4 David Hildenbrand
` (18 preceding siblings ...)
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 19/22] s390x/tcg: Implement VECTOR FP SUBTRACT David Hildenbrand
@ 2019-06-03 9:06 ` David Hildenbrand
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 21/22] s390x/tcg: Allow linux-user to use vector instructions David Hildenbrand
` (3 subsequent siblings)
23 siblings, 0 replies; 34+ messages in thread
From: David Hildenbrand @ 2019-06-03 9:06 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Denys Vlasenko, David Hildenbrand, Cornelia Huck,
Richard Henderson, Pino Toscano, Christian Borntraeger,
qemu-s390x, Richard Henderson
We can reuse float64_dcmask().
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 21 +++++++++++++++++++
target/s390x/vec_fpu_helper.c | 37 +++++++++++++++++++++++++++++++++
4 files changed, 62 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index c788fc1b7f..e9aff83b05 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -292,6 +292,8 @@ DEF_HELPER_FLAGS_4(gvec_vfsq64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vfsq64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vfs64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vfs64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
+DEF_HELPER_4(gvec_vftci64, void, ptr, cptr, env, i32)
+DEF_HELPER_4(gvec_vftci64s, void, ptr, cptr, env, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 4426f40250..f421184fcd 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1246,6 +1246,8 @@
F(0xe7ce, VFSQ, VRR_a, V, 0, 0, 0, 0, vfsq, 0, IF_VEC)
/* VECTOR FP SUBTRACT */
F(0xe7e2, VFS, VRR_c, V, 0, 0, 0, 0, vfa, 0, IF_VEC)
+/* VECTOR FP TEST DATA CLASS IMMEDIATE */
+ F(0xe74a, VFTCI, VRI_e, V, 0, 0, 0, 0, vftci, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index c0a19aa9f3..69c675e411 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -2801,3 +2801,24 @@ static DisasJumpType op_vfsq(DisasContext *s, DisasOps *o)
0, fn);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vftci(DisasContext *s, DisasOps *o)
+{
+ const uint16_t i3 = get_field(s->fields, i3);
+ const uint8_t fpf = get_field(s->fields, m4);
+ const uint8_t m5 = get_field(s->fields, m5);
+ gen_helper_gvec_2_ptr *fn = gen_helper_gvec_vftci64;
+
+ if (fpf != FPF_LONG || extract32(m5, 0, 3)) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ if (extract32(m5, 3, 1)) {
+ fn = gen_helper_gvec_vftci64s;
+ }
+ gen_gvec_2_ptr(get_field(s->fields, v1), get_field(s->fields, v2), cpu_env,
+ i3, fn);
+ set_cc_static(s);
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_fpu_helper.c b/target/s390x/vec_fpu_helper.c
index ccdc975628..a48bd704bc 100644
--- a/target/s390x/vec_fpu_helper.c
+++ b/target/s390x/vec_fpu_helper.c
@@ -586,3 +586,40 @@ void HELPER(gvec_vfs64s)(void *v1, const void *v2, const void *v3,
{
vop64_3(v1, v2, v3, env, true, vfs64, GETPC());
}
+
+static int vftci64(S390Vector *v1, const S390Vector *v2, CPUS390XState *env,
+ bool s, uint16_t i3)
+{
+ int i, match = 0;
+
+ for (i = 0; i < 2; i++) {
+ float64 a = s390_vec_read_element64(v2, i);
+
+ if (float64_dcmask(env, a) & i3) {
+ match++;
+ s390_vec_write_element64(v1, i, -1ull);
+ } else {
+ s390_vec_write_element64(v1, i, 0);
+ }
+ if (s) {
+ break;
+ }
+ }
+
+ if (match) {
+ return s || match == 2 ? 0 : 1;
+ }
+ return 3;
+}
+
+void HELPER(gvec_vftci64)(void *v1, const void *v2, CPUS390XState *env,
+ uint32_t desc)
+{
+ env->cc_op = vftci64(v1, v2, env, false, simd_data(desc));
+}
+
+void HELPER(gvec_vftci64s)(void *v1, const void *v2, CPUS390XState *env,
+ uint32_t desc)
+{
+ env->cc_op = vftci64(v1, v2, env, true, simd_data(desc));
+}
--
2.21.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Qemu-devel] [PATCH v2 21/22] s390x/tcg: Allow linux-user to use vector instructions
2019-06-03 9:06 [Qemu-devel] [PATCH v2 00/22] s390x/tcg: Vector Instruction Support Part 4 David Hildenbrand
` (19 preceding siblings ...)
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 20/22] s390x/tcg: Implement VECTOR FP TEST DATA CLASS IMMEDIATE David Hildenbrand
@ 2019-06-03 9:06 ` David Hildenbrand
2019-06-04 7:45 ` Laurent Vivier
2019-06-04 8:50 ` Laurent Vivier
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 22/22] s390x/tcg: We support the Vector Facility David Hildenbrand
` (2 subsequent siblings)
23 siblings, 2 replies; 34+ messages in thread
From: David Hildenbrand @ 2019-06-03 9:06 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Denys Vlasenko, David Hildenbrand, Cornelia Huck,
Richard Henderson, Pino Toscano, Christian Borntraeger,
qemu-s390x, Richard Henderson
Once we unlock S390_FEAT_VECTOR for TCG, we want linux-user to be
able to make use of it.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/cpu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index b1df63d82c..6af1a1530f 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -145,6 +145,9 @@ static void s390_cpu_full_reset(CPUState *s)
#if defined(CONFIG_USER_ONLY)
/* user mode should always be allowed to use the full FPU */
env->cregs[0] |= CR0_AFP;
+ if (s390_has_feat(S390_FEAT_VECTOR)) {
+ env->cregs[0] |= CR0_VECTOR;
+ }
#endif
/* architectured initial value for Breaking-Event-Address register */
--
2.21.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Qemu-devel] [PATCH v2 22/22] s390x/tcg: We support the Vector Facility
2019-06-03 9:06 [Qemu-devel] [PATCH v2 00/22] s390x/tcg: Vector Instruction Support Part 4 David Hildenbrand
` (20 preceding siblings ...)
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 21/22] s390x/tcg: Allow linux-user to use vector instructions David Hildenbrand
@ 2019-06-03 9:06 ` David Hildenbrand
2019-06-03 9:09 ` [Qemu-devel] [PATCH v2 00/22] s390x/tcg: Vector Instruction Support Part 4 David Hildenbrand
2019-06-03 9:17 ` [Qemu-devel] [PATCH v2 23/22] s390x: Bump the "qemu" CPU model up to a stripped-down z13 David Hildenbrand
23 siblings, 0 replies; 34+ messages in thread
From: David Hildenbrand @ 2019-06-03 9:06 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Denys Vlasenko, David Hildenbrand, Cornelia Huck,
Richard Henderson, Pino Toscano, Christian Borntraeger,
qemu-s390x, Richard Henderson
Let's add it to the max model, so we can enable it.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/gen-features.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/s390x/gen-features.c b/target/s390x/gen-features.c
index c346b76bdf..a818c80332 100644
--- a/target/s390x/gen-features.c
+++ b/target/s390x/gen-features.c
@@ -702,6 +702,7 @@ static uint16_t qemu_LATEST[] = {
static uint16_t qemu_MAX[] = {
/* z13+ features */
S390_FEAT_STFLE_53,
+ S390_FEAT_VECTOR,
/* generates a dependency warning, leave it out for now */
S390_FEAT_MSA_EXT_5,
};
--
2.21.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* Re: [Qemu-devel] [PATCH v2 01/22] s390x/tcg: Store only the necessary amount of doublewords for STFLE
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 01/22] s390x/tcg: Store only the necessary amount of doublewords for STFLE David Hildenbrand
@ 2019-06-03 9:07 ` David Hildenbrand
0 siblings, 0 replies; 34+ messages in thread
From: David Hildenbrand @ 2019-06-03 9:07 UTC (permalink / raw)
To: qemu-devel
Cc: Stefan Liebler, Thomas Huth, Denys Vlasenko, Andreas Krebbel,
Cornelia Huck, Richard Henderson, Pino Toscano,
Christian Borntraeger, qemu-s390x, Richard Henderson
On 03.06.19 11:06, David Hildenbrand wrote:
> The PoP (z14, 7-382) says:
> Doublewords to the right of the doubleword in which the
> highest-numbered facility bit is assigned for a model
> may or may not be stored.
>
> However, stack protection in certain binaries can't deal with that.
> "gzip" example code:
>
> f1b4: a7 08 00 03 lhi %r0,3
> f1b8: b2 b0 f0 a0 stfle 160(%r15)
> f1bc: e3 20 f0 b2 00 90 llgc %r2,178(%r15)
> f1c2: c0 2b 00 00 00 01 nilf %r2,1
> f1c8: b2 4f 00 10 ear %r1,%a0
> f1cc: b9 14 00 22 lgfr %r2,%r2
> f1d0: eb 11 00 20 00 0d sllg %r1,%r1,32
> f1d6: b2 4f 00 11 ear %r1,%a1
> f1da: d5 07 f0 b8 10 28 clc 184(8,%r15),40(%r1)
> f1e0: a7 74 00 06 jne f1ec <file_read@@Base+0x1bc>
> f1e4: eb ef f1 30 00 04 lmg %r14,%r15,304(%r15)
> f1ea: 07 fe br %r14
> f1ec: c0 e5 ff ff 9d 6e brasl %r14,2cc8 <__stack_chk_fail@plt>
>
> In QEMU, we currently have:
> max_bytes = 24
> the code asks for (3 + 1) doublewords == 32 bytes.
>
> If we write 32 bytes instead of only 24, and return "2 + 1" doublewords
> ("one less than the number of doulewords needed to contain all of the
> facility bits"), the example code detects a stack corruption.
>
> In my opinion, the code is wrong. However, it seems to work fine on
> real machines. So let's limit storing to the minimum of the requested
> and the maximum doublewords.
>
> Cc: Stefan Liebler <stli@linux.ibm.com>
> Cc: Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: David Hildenbrand <david@redhat.com>
> ---
> target/s390x/misc_helper.c | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/target/s390x/misc_helper.c b/target/s390x/misc_helper.c
> index 34476134a4..10aa617cf9 100644
> --- a/target/s390x/misc_helper.c
> +++ b/target/s390x/misc_helper.c
> @@ -678,7 +678,13 @@ uint32_t HELPER(stfle)(CPUS390XState *env, uint64_t addr)
>
> prepare_stfl();
> max_bytes = ROUND_UP(used_stfl_bytes, 8);
> - for (i = 0; i < count_bytes; ++i) {
> +
> + /*
> + * The PoP says that doublewords beyond the highest-numbered facility
> + * bit may or may not be stored. However, existing hardware appears to
> + * not store the words, and existing software depend on that.
> + */
> + for (i = 0; i < MIN(count_bytes, max_bytes); ++i) {
> cpu_stb_data_ra(env, addr + i, stfl_bytes[i], ra);
> }
>
>
Not intended to be included in this series, please ignore :)
--
Thanks,
David / dhildenb
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [Qemu-devel] [PATCH v2 00/22] s390x/tcg: Vector Instruction Support Part 4
2019-06-03 9:06 [Qemu-devel] [PATCH v2 00/22] s390x/tcg: Vector Instruction Support Part 4 David Hildenbrand
` (21 preceding siblings ...)
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 22/22] s390x/tcg: We support the Vector Facility David Hildenbrand
@ 2019-06-03 9:09 ` David Hildenbrand
2019-06-03 9:17 ` [Qemu-devel] [PATCH v2 23/22] s390x: Bump the "qemu" CPU model up to a stripped-down z13 David Hildenbrand
23 siblings, 0 replies; 34+ messages in thread
From: David Hildenbrand @ 2019-06-03 9:09 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Denys Vlasenko, Cornelia Huck, Pino Toscano,
Christian Borntraeger, qemu-s390x, Richard Henderson
On 03.06.19 11:06, David Hildenbrand wrote:
> This is the final part of vector instruction support for s390x.
>
> Part 1: Vector Support Instructions
> Part 2: Vector Integer Instructions
> Part 3: Vector String Instructions
> Part 4: Vector Floating-Point Instructions
>
> The current state can be found at (kept updated):
> https://github.com/davidhildenbrand/qemu/tree/vx
>
> It is based on:
> - [PATCH v2 0/5] s390x/tcg: Vector Instruction Support Part 3
> - [PATCH v1 0/2] s390x: Fix vector register alignment
>
> With the current state I can boot Linux kernel + user space compiled with
> SIMD support. This allows to boot distributions compiled exclusively for
> z13, requiring SIMD support. Also, it is now possible to build a complete
> kernel using rpmbuild as quite some issues have been sorted out.
>
> While the current state works fine for me with RHEL 8, I am experiencing
> some issues with newer userspace versions. I already found and fixed
> some stack overflow protection issues (stfle instruction). I still see
> random rpm database corruptions and rpmbuild doesn't work correctly
> (looks like another stack protection issue).
>
> In this part, all Vector Floating-Point Instructions introduced with the
> "Vector Facility" are added. Also, the "qemu" model is changed to a
> z13 machine.
>
> v1 -> v2:
> - get rid of make_float64() and float64_val().
> - fixed two cc calculation issues (thanks Richard)
> - Rework "VECTOR FP COMPARE (EQUAL|HIGH|HIGH OR EQUAL)"
> - Rework "VECTOR FP MULTIPLY AND (ADD|SUBTRACT)"
> - Use gvec expansion in "s390x/tcg: Implement VECTOR FP PERFORM SIGN
> OPERATION"
>
> Cc: Denys Vlasenko <dvlasenk@redhat.com>
> Cc: Christian Borntraeger <borntraeger@de.ibm.com>
> Cc: Pino Toscano <ptoscano@redhat.com>
>
> David Hildenbrand (22):
> s390x/tcg: Store only the necessary amount of doublewords for STFLE
> s390x/tcg: Introduce tcg_s390_vector_exception()
> s390x/tcg: Export float_comp_to_cc() and float(32|64|128)_dcmask()
> s390x/tcg: Implement VECTOR FP ADD
> s390x/tcg: Implement VECTOR FP COMPARE (AND SIGNAL) SCALAR
> s390x/tcg: Implement VECTOR FP COMPARE (EQUAL|HIGH|HIGH OR EQUAL)
> s390x/tcg: Implement VECTOR FP CONVERT FROM FIXED 64-BIT
> s390x/tcg: Implement VECTOR FP CONVERT FROM LOGICAL 64-BIT
> s390x/tcg: Implement VECTOR FP CONVERT TO FIXED 64-BIT
> s390x/tcg: Implement VECTOR FP CONVERT TO LOGICAL 64-BIT
> s390x/tcg: Implement VECTOR FP DIVIDE
> s390x/tcg: Implement VECTOR LOAD FP INTEGER
> s390x/tcg: Implement VECTOR LOAD LENGTHENED
> s390x/tcg: Implement VECTOR LOAD ROUNDED
> s390x/tcg: Implement VECTOR FP MULTIPLY
> s390x/tcg: Implement VECTOR FP MULTIPLY AND (ADD|SUBTRACT)
> s390x/tcg: Implement VECTOR FP PERFORM SIGN OPERATION
> s390x/tcg: Implement VECTOR FP SQUARE ROOT
> s390x/tcg: Implement VECTOR FP SUBTRACT
> s390x/tcg: Implement VECTOR FP TEST DATA CLASS IMMEDIATE
> s390x/tcg: Allow linux-user to use vector instructions
> s390x/tcg: We support the Vector Facility
>
> target/s390x/Makefile.objs | 1 +
> target/s390x/cpu.c | 3 +
> target/s390x/cpu.h | 1 +
> target/s390x/excp_helper.c | 15 +
> target/s390x/fpu_helper.c | 4 +-
> target/s390x/gen-features.c | 1 +
> target/s390x/helper.h | 46 +++
> target/s390x/insn-data.def | 45 +++
> target/s390x/internal.h | 4 +
> target/s390x/misc_helper.c | 8 +-
> target/s390x/tcg_s390x.h | 2 +
> target/s390x/translate_vx.inc.c | 284 +++++++++++++++
> target/s390x/vec_fpu_helper.c | 625 ++++++++++++++++++++++++++++++++
> 13 files changed, 1036 insertions(+), 3 deletions(-)
> create mode 100644 target/s390x/vec_fpu_helper.c
>
Still tired, the unchanged patch
"[PATCH v1 23/23] s390x: Bump the "qemu" CPU model up to a stripped-down
z13"
is missing from this series (already reviewed by Richard)
--
Thanks,
David / dhildenb
^ permalink raw reply [flat|nested] 34+ messages in thread
* [Qemu-devel] [PATCH v2 23/22] s390x: Bump the "qemu" CPU model up to a stripped-down z13
2019-06-03 9:06 [Qemu-devel] [PATCH v2 00/22] s390x/tcg: Vector Instruction Support Part 4 David Hildenbrand
` (22 preceding siblings ...)
2019-06-03 9:09 ` [Qemu-devel] [PATCH v2 00/22] s390x/tcg: Vector Instruction Support Part 4 David Hildenbrand
@ 2019-06-03 9:17 ` David Hildenbrand
23 siblings, 0 replies; 34+ messages in thread
From: David Hildenbrand @ 2019-06-03 9:17 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, David Hildenbrand, Cornelia Huck, Richard Henderson,
Christian Borntraeger, qemu-s390x, Richard Henderson
We don't care about the other two missing base features:
- S390_FEAT_DFP_PACKED_CONVERSION
- S390_FEAT_GROUP_GEN13_PTFF
Cc: Christian Borntraeger <borntraeger@de.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
hw/s390x/s390-virtio-ccw.c | 2 ++
target/s390x/cpu_models.c | 4 ++--
target/s390x/gen-features.c | 11 +++++++----
3 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c
index bbc6e8fa0b..4d643686cb 100644
--- a/hw/s390x/s390-virtio-ccw.c
+++ b/hw/s390x/s390-virtio-ccw.c
@@ -669,7 +669,9 @@ DEFINE_CCW_MACHINE(4_1, "4.1", true);
static void ccw_machine_4_0_instance_options(MachineState *machine)
{
+ static const S390FeatInit qemu_cpu_feat = { S390_FEAT_LIST_QEMU_V4_0 };
ccw_machine_4_1_instance_options(machine);
+ s390_set_qemu_cpu_model(0x2827, 12, 2, qemu_cpu_feat);
}
static void ccw_machine_4_0_class_options(MachineClass *mc)
diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c
index 21ea819483..b5d16e4c89 100644
--- a/target/s390x/cpu_models.c
+++ b/target/s390x/cpu_models.c
@@ -86,8 +86,8 @@ static S390CPUDef s390_cpu_defs[] = {
CPUDEF_INIT(0x8562, 15, 1, 47, 0x08000000U, "gen15b", "IBM 8562 GA1"),
};
-#define QEMU_MAX_CPU_TYPE 0x2827
-#define QEMU_MAX_CPU_GEN 12
+#define QEMU_MAX_CPU_TYPE 0x2964
+#define QEMU_MAX_CPU_GEN 13
#define QEMU_MAX_CPU_EC_GA 2
static const S390FeatInit qemu_max_cpu_feat_init = { S390_FEAT_LIST_QEMU_MAX };
static S390FeatBitmap qemu_max_cpu_feat;
diff --git a/target/s390x/gen-features.c b/target/s390x/gen-features.c
index a818c80332..dc320a06c2 100644
--- a/target/s390x/gen-features.c
+++ b/target/s390x/gen-features.c
@@ -689,7 +689,7 @@ static uint16_t qemu_V3_1[] = {
S390_FEAT_MSA_EXT_4,
};
-static uint16_t qemu_LATEST[] = {
+static uint16_t qemu_V4_0[] = {
/*
* Only BFP bits are implemented (HFP, DFP, PFPO and DIVIDE TO INTEGER not
* implemented yet).
@@ -698,11 +698,13 @@ static uint16_t qemu_LATEST[] = {
S390_FEAT_ZPCI,
};
-/* add all new definitions before this point */
-static uint16_t qemu_MAX[] = {
- /* z13+ features */
+static uint16_t qemu_LATEST[] = {
S390_FEAT_STFLE_53,
S390_FEAT_VECTOR,
+};
+
+/* add all new definitions before this point */
+static uint16_t qemu_MAX[] = {
/* generates a dependency warning, leave it out for now */
S390_FEAT_MSA_EXT_5,
};
@@ -821,6 +823,7 @@ static FeatGroupDefSpec FeatGroupDef[] = {
static FeatGroupDefSpec QemuFeatDef[] = {
QEMU_FEAT_INITIALIZER(V2_11),
QEMU_FEAT_INITIALIZER(V3_1),
+ QEMU_FEAT_INITIALIZER(V4_0),
QEMU_FEAT_INITIALIZER(LATEST),
QEMU_FEAT_INITIALIZER(MAX),
};
--
2.21.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* Re: [Qemu-devel] [PATCH v2 16/22] s390x/tcg: Implement VECTOR FP MULTIPLY AND (ADD|SUBTRACT)
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 16/22] s390x/tcg: Implement VECTOR FP MULTIPLY AND (ADD|SUBTRACT) David Hildenbrand
@ 2019-06-03 16:16 ` Richard Henderson
0 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2019-06-03 16:16 UTC (permalink / raw)
To: David Hildenbrand, qemu-devel
Cc: Thomas Huth, Denys Vlasenko, Cornelia Huck, Pino Toscano,
Christian Borntraeger, qemu-s390x, Richard Henderson
On 6/3/19 4:06 AM, David Hildenbrand wrote:
> Signed-off-by: David Hildenbrand <david@redhat.com>
> ---
> target/s390x/helper.h | 4 +++
> target/s390x/insn-data.def | 4 +++
> target/s390x/translate_vx.inc.c | 23 ++++++++++++++++
> target/s390x/vec_fpu_helper.c | 48 +++++++++++++++++++++++++++++++++
> 4 files changed, 79 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [Qemu-devel] [PATCH v2 03/22] s390x/tcg: Export float_comp_to_cc() and float(32|64|128)_dcmask()
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 03/22] s390x/tcg: Export float_comp_to_cc() and float(32|64|128)_dcmask() David Hildenbrand
@ 2019-06-03 16:17 ` Richard Henderson
0 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2019-06-03 16:17 UTC (permalink / raw)
To: David Hildenbrand, qemu-devel
Cc: Thomas Huth, Denys Vlasenko, Cornelia Huck, Pino Toscano,
Christian Borntraeger, qemu-s390x, Richard Henderson
On 6/3/19 4:06 AM, David Hildenbrand wrote:
> Vector floating-point instructions will require these functions, so
> allow to use them from other files.
>
> Signed-off-by: David Hildenbrand <david@redhat.com>
> ---
> target/s390x/fpu_helper.c | 4 ++--
> target/s390x/internal.h | 4 ++++
> 2 files changed, 6 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [Qemu-devel] [PATCH v2 17/22] s390x/tcg: Implement VECTOR FP PERFORM SIGN OPERATION
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 17/22] s390x/tcg: Implement VECTOR FP PERFORM SIGN OPERATION David Hildenbrand
@ 2019-06-03 16:18 ` Richard Henderson
0 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2019-06-03 16:18 UTC (permalink / raw)
To: David Hildenbrand, qemu-devel
Cc: Thomas Huth, Denys Vlasenko, Cornelia Huck, Pino Toscano,
Christian Borntraeger, qemu-s390x, Richard Henderson
On 6/3/19 4:06 AM, David Hildenbrand wrote:
> The only FP instruction we can implement without an helper.
>
> Signed-off-by: David Hildenbrand <david@redhat.com>
> ---
> target/s390x/insn-data.def | 2 ++
> target/s390x/translate_vx.inc.c | 52 +++++++++++++++++++++++++++++++++
> 2 files changed, 54 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [Qemu-devel] [PATCH v2 21/22] s390x/tcg: Allow linux-user to use vector instructions
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 21/22] s390x/tcg: Allow linux-user to use vector instructions David Hildenbrand
@ 2019-06-04 7:45 ` Laurent Vivier
2019-06-04 8:50 ` Laurent Vivier
1 sibling, 0 replies; 34+ messages in thread
From: Laurent Vivier @ 2019-06-04 7:45 UTC (permalink / raw)
To: David Hildenbrand, qemu-devel
Cc: Thomas Huth, Denys Vlasenko, Cornelia Huck, Richard Henderson,
Pino Toscano, Christian Borntraeger, qemu-s390x,
Richard Henderson
Le 03/06/2019 à 11:06, David Hildenbrand a écrit :
> Once we unlock S390_FEAT_VECTOR for TCG, we want linux-user to be
> able to make use of it.
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: David Hildenbrand <david@redhat.com>
> ---
> target/s390x/cpu.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
> index b1df63d82c..6af1a1530f 100644
> --- a/target/s390x/cpu.c
> +++ b/target/s390x/cpu.c
> @@ -145,6 +145,9 @@ static void s390_cpu_full_reset(CPUState *s)
> #if defined(CONFIG_USER_ONLY)
> /* user mode should always be allowed to use the full FPU */
> env->cregs[0] |= CR0_AFP;
> + if (s390_has_feat(S390_FEAT_VECTOR)) {
> + env->cregs[0] |= CR0_VECTOR;
> + }
> #endif
>
> /* architectured initial value for Breaking-Event-Address register */
>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [Qemu-devel] [PATCH v2 21/22] s390x/tcg: Allow linux-user to use vector instructions
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 21/22] s390x/tcg: Allow linux-user to use vector instructions David Hildenbrand
2019-06-04 7:45 ` Laurent Vivier
@ 2019-06-04 8:50 ` Laurent Vivier
2019-06-04 8:56 ` David Hildenbrand
1 sibling, 1 reply; 34+ messages in thread
From: Laurent Vivier @ 2019-06-04 8:50 UTC (permalink / raw)
To: David Hildenbrand, qemu-devel
Cc: Thomas Huth, Denys Vlasenko, Cornelia Huck, Richard Henderson,
Pino Toscano, Christian Borntraeger, qemu-s390x,
Richard Henderson
Le 03/06/2019 à 11:06, David Hildenbrand a écrit :
> Once we unlock S390_FEAT_VECTOR for TCG, we want linux-user to be
> able to make use of it.
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: David Hildenbrand <david@redhat.com>
> ---
> target/s390x/cpu.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
> index b1df63d82c..6af1a1530f 100644
> --- a/target/s390x/cpu.c
> +++ b/target/s390x/cpu.c
> @@ -145,6 +145,9 @@ static void s390_cpu_full_reset(CPUState *s)
> #if defined(CONFIG_USER_ONLY)
> /* user mode should always be allowed to use the full FPU */
> env->cregs[0] |= CR0_AFP;
> + if (s390_has_feat(S390_FEAT_VECTOR)) {
> + env->cregs[0] |= CR0_VECTOR;
> + }
> #endif
>
> /* architectured initial value for Breaking-Event-Address register */
>
Do we need to add some hwcaps in linux-user/elfload.c (HWCAP_S390_VXRS,
HWCAP_S390_VXRS_EXT,...)?
Thanks,
Laurent
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [Qemu-devel] [PATCH v2 21/22] s390x/tcg: Allow linux-user to use vector instructions
2019-06-04 8:50 ` Laurent Vivier
@ 2019-06-04 8:56 ` David Hildenbrand
0 siblings, 0 replies; 34+ messages in thread
From: David Hildenbrand @ 2019-06-04 8:56 UTC (permalink / raw)
To: Laurent Vivier, qemu-devel
Cc: Thomas Huth, Denys Vlasenko, Cornelia Huck, Richard Henderson,
Pino Toscano, Christian Borntraeger, qemu-s390x,
Richard Henderson
On 04.06.19 10:50, Laurent Vivier wrote:
> Le 03/06/2019 à 11:06, David Hildenbrand a écrit :
>> Once we unlock S390_FEAT_VECTOR for TCG, we want linux-user to be
>> able to make use of it.
>>
>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>> Signed-off-by: David Hildenbrand <david@redhat.com>
>> ---
>> target/s390x/cpu.c | 3 +++
>> 1 file changed, 3 insertions(+)
>>
>> diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
>> index b1df63d82c..6af1a1530f 100644
>> --- a/target/s390x/cpu.c
>> +++ b/target/s390x/cpu.c
>> @@ -145,6 +145,9 @@ static void s390_cpu_full_reset(CPUState *s)
>> #if defined(CONFIG_USER_ONLY)
>> /* user mode should always be allowed to use the full FPU */
>> env->cregs[0] |= CR0_AFP;
>> + if (s390_has_feat(S390_FEAT_VECTOR)) {
>> + env->cregs[0] |= CR0_VECTOR;
>> + }
>> #endif
>>
>> /* architectured initial value for Breaking-Event-Address register */
>>
>
> Do we need to add some hwcaps in linux-user/elfload.c (HWCAP_S390_VXRS,
> HWCAP_S390_VXRS_EXT,...)?
Good point, I will look into this. Thanks!
>
> Thanks,
> Laurent
>
--
Thanks,
David / dhildenb
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [Qemu-devel] [PATCH v2 06/22] s390x/tcg: Implement VECTOR FP COMPARE (EQUAL|HIGH|HIGH OR EQUAL)
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 06/22] s390x/tcg: Implement VECTOR FP COMPARE (EQUAL|HIGH|HIGH OR EQUAL) David Hildenbrand
@ 2019-06-05 9:19 ` David Hildenbrand
2019-06-05 14:47 ` Richard Henderson
0 siblings, 1 reply; 34+ messages in thread
From: David Hildenbrand @ 2019-06-05 9:19 UTC (permalink / raw)
To: qemu-devel, Richard Henderson
Cc: Thomas Huth, Denys Vlasenko, Cornelia Huck, Pino Toscano,
Christian Borntraeger, qemu-s390x
On 03.06.19 11:06, David Hildenbrand wrote:
> Provide for all three instructions all four combinations of cc bit and
> s bit.
>
> Signed-off-by: David Hildenbrand <david@redhat.com>
> ---
> target/s390x/helper.h | 12 ++++
> target/s390x/insn-data.def | 6 ++
> target/s390x/translate_vx.inc.c | 51 ++++++++++++++++
> target/s390x/vec_fpu_helper.c | 104 ++++++++++++++++++++++++++++++++
> 4 files changed, 173 insertions(+)
>
> diff --git a/target/s390x/helper.h b/target/s390x/helper.h
> index d34d6802a6..33d3bacf74 100644
> --- a/target/s390x/helper.h
> +++ b/target/s390x/helper.h
> @@ -254,6 +254,18 @@ DEF_HELPER_FLAGS_5(gvec_vfa64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
> DEF_HELPER_FLAGS_5(gvec_vfa64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
> DEF_HELPER_4(gvec_wfc64, void, cptr, cptr, env, i32)
> DEF_HELPER_4(gvec_wfk64, void, cptr, cptr, env, i32)
> +DEF_HELPER_FLAGS_5(gvec_vfce64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
> +DEF_HELPER_FLAGS_5(gvec_vfce64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
> +DEF_HELPER_5(gvec_vfce64_cc, void, ptr, cptr, cptr, env, i32)
> +DEF_HELPER_5(gvec_vfce64s_cc, void, ptr, cptr, cptr, env, i32)
> +DEF_HELPER_FLAGS_5(gvec_vfch64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
> +DEF_HELPER_FLAGS_5(gvec_vfch64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
> +DEF_HELPER_5(gvec_vfch64_cc, void, ptr, cptr, cptr, env, i32)
> +DEF_HELPER_5(gvec_vfch64s_cc, void, ptr, cptr, cptr, env, i32)
> +DEF_HELPER_FLAGS_5(gvec_vfche64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
> +DEF_HELPER_FLAGS_5(gvec_vfche64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
> +DEF_HELPER_5(gvec_vfche64_cc, void, ptr, cptr, cptr, env, i32)
> +DEF_HELPER_5(gvec_vfche64s_cc, void, ptr, cptr, cptr, env, i32)
>
> #ifndef CONFIG_USER_ONLY
> DEF_HELPER_3(servc, i32, env, i64, i64)
> diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
> index c45e101b10..446552f251 100644
> --- a/target/s390x/insn-data.def
> +++ b/target/s390x/insn-data.def
> @@ -1212,6 +1212,12 @@
> F(0xe7cb, WFC, VRR_a, V, 0, 0, 0, 0, wfc, 0, IF_VEC)
> /* VECTOR FP COMPARE AND SIGNAL SCALAR */
> F(0xe7ca, WFK, VRR_a, V, 0, 0, 0, 0, wfc, 0, IF_VEC)
> +/* VECTOR FP COMPARE EQUAL */
> + F(0xe7e8, VFCE, VRR_c, V, 0, 0, 0, 0, vfc, 0, IF_VEC)
> +/* VECTOR FP COMPARE HIGH */
> + F(0xe7eb, VFCH, VRR_c, V, 0, 0, 0, 0, vfc, 0, IF_VEC)
> +/* VECTOR FP COMPARE HIGH OR EQUAL */
> + F(0xe7ea, VFCHE, VRR_c, V, 0, 0, 0, 0, vfc, 0, IF_VEC)
>
> #ifndef CONFIG_USER_ONLY
> /* COMPARE AND SWAP AND PURGE */
> diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
> index 283e8aa07a..5571a71e1a 100644
> --- a/target/s390x/translate_vx.inc.c
> +++ b/target/s390x/translate_vx.inc.c
> @@ -2588,3 +2588,54 @@ static DisasJumpType op_wfc(DisasContext *s, DisasOps *o)
> set_cc_static(s);
> return DISAS_NEXT;
> }
> +
> +static DisasJumpType op_vfc(DisasContext *s, DisasOps *o)
> +{
> + const uint8_t fpf = get_field(s->fields, m4);
> + const uint8_t m5 = get_field(s->fields, m5);
> + const uint8_t m6 = get_field(s->fields, m6);
> + const bool se = extract32(m5, 3, 1);
> + const bool cs = extract32(m6, 0, 1);
> + gen_helper_gvec_3_ptr *fn;
> +
> + if (fpf != FPF_LONG || extract32(m5, 0, 3) || extract32(m6, 1, 3)) {
> + gen_program_exception(s, PGM_SPECIFICATION);
> + return DISAS_NORETURN;
> + }
> +
> + if (cs) {
> + switch (s->fields->op2) {
> + case 0xe8:
> + fn = se ? gen_helper_gvec_vfce64s_cc : gen_helper_gvec_vfce64_cc;
> + break;
> + case 0xeb:
> + fn = se ? gen_helper_gvec_vfch64s_cc : gen_helper_gvec_vfch64_cc;
> + break;
> + case 0xea:
> + fn = se ? gen_helper_gvec_vfche64s_cc : gen_helper_gvec_vfche64_cc;
> + break;
> + default:
> + g_assert_not_reached();
> + }
> + } else {
> + switch (s->fields->op2) {
> + case 0xe8:
> + fn = se ? gen_helper_gvec_vfce64s : gen_helper_gvec_vfce64;
> + break;
> + case 0xeb:
> + fn = se ? gen_helper_gvec_vfch64s : gen_helper_gvec_vfch64;
> + break;
> + case 0xea:
> + fn = se ? gen_helper_gvec_vfche64s : gen_helper_gvec_vfche64;
> + break;
> + default:
> + g_assert_not_reached();
> + }
> + }
> + gen_gvec_3_ptr(get_field(s->fields, v1), get_field(s->fields, v2),
> + get_field(s->fields, v3), cpu_env, 0, fn);
> + if (cs) {
> + set_cc_static(s);
> + }
> + return DISAS_NEXT;
> +}
> diff --git a/target/s390x/vec_fpu_helper.c b/target/s390x/vec_fpu_helper.c
> index f9357d9221..e72500d4d5 100644
> --- a/target/s390x/vec_fpu_helper.c
> +++ b/target/s390x/vec_fpu_helper.c
> @@ -149,3 +149,107 @@ void HELPER(gvec_wfk64)(const void *v1, const void *v2, CPUS390XState *env,
> {
> env->cc_op = wfc64(v1, v2, env, true, GETPC());
> }
> +
> +typedef int (*vfc64_fn)(float64 a, float64 b, float_status *status);
> +static int vfc64(S390Vector *v1, const S390Vector *v2, const S390Vector *v3,
> + CPUS390XState *env, bool s, vfc64_fn fn, uintptr_t retaddr)
> +{
> + uint8_t vxc, vec_exc = 0;
> + S390Vector tmp = {};
> + int match = 0;
> + int i;
> +
> + for (i = 0; i < 2; i++) {
> + const float64 a = s390_vec_read_element64(v2, i);
> + const float64 b = s390_vec_read_element64(v3, i);
> +
> + /* swap the order of the parameters, so we can use existing functions */
> + if (fn(b, a, &env->fpu_status)) {
> + match++;
> + s390_vec_write_element64(&tmp, i, -1ull);
> + }
> + vxc = check_ieee_exc(env, i, false, &vec_exc);
> + if (s || vxc) {
> + break;
> + }
> + }
> +
> + handle_ieee_exc(env, vxc, vec_exc, retaddr);
> + *v1 = tmp;
> + if (match) {
> + return s || match == 2 ? 0 : 1;
> + }
> + return 3;
> +}
> +
> +void HELPER(gvec_vfce64)(void *v1, const void *v2, const void *v3,
> + CPUS390XState *env, uint32_t desc)
> +{
> + vfc64(v1, v2, v3, env, false, float64_eq_quiet, GETPC());
> +}
> +
> +void HELPER(gvec_vfce64s)(void *v1, const void *v2, const void *v3,
> + CPUS390XState *env, uint32_t desc)
> +{
> + vfc64(v1, v2, v3, env, true, float64_eq_quiet, GETPC());
> +}
> +
> +void HELPER(gvec_vfce64_cc)(void *v1, const void *v2, const void *v3,
> + CPUS390XState *env, uint32_t desc)
> +{
> + env->cc_op = vfc64(v1, v2, v3, env, false, float64_eq_quiet, GETPC());
> +}
> +
> +void HELPER(gvec_vfce64s_cc)(void *v1, const void *v2, const void *v3,
> + CPUS390XState *env, uint32_t desc)
> +{
> + env->cc_op = vfc64(v1, v2, v3, env, true, float64_eq_quiet, GETPC());
> +}
> +
> +void HELPER(gvec_vfch64)(void *v1, const void *v2, const void *v3,
> + CPUS390XState *env, uint32_t desc)
> +{
> + vfc64(v1, v2, v3, env, false, float64_lt_quiet, GETPC());
> +}
> +
> +void HELPER(gvec_vfch64s)(void *v1, const void *v2, const void *v3,
> + CPUS390XState *env, uint32_t desc)
> +{
> + vfc64(v1, v2, v3, env, true, float64_lt_quiet, GETPC());
> +}
> +
> +void HELPER(gvec_vfch64_cc)(void *v1, const void *v2, const void *v3,
> + CPUS390XState *env, uint32_t desc)
> +{
> + env->cc_op = vfc64(v1, v2, v3, env, false, float64_lt_quiet, GETPC());
> +}
> +
> +void HELPER(gvec_vfch64s_cc)(void *v1, const void *v2, const void *v3,
> + CPUS390XState *env, uint32_t desc)
> +{
> + env->cc_op = vfc64(v1, v2, v3, env, true, float64_lt_quiet, GETPC());
> +}
> +
> +void HELPER(gvec_vfche64)(void *v1, const void *v2, const void *v3,
> + CPUS390XState *env, uint32_t desc)
> +{
> + vfc64(v1, v2, v3, env, false, float64_le_quiet, GETPC());
> +}
> +
> +void HELPER(gvec_vfche64s)(void *v1, const void *v2, const void *v3,
> + CPUS390XState *env, uint32_t desc)
> +{
> + vfc64(v1, v2, v3, env, true, float64_le_quiet, GETPC());
> +}
> +
> +void HELPER(gvec_vfche64_cc)(void *v1, const void *v2, const void *v3,
> + CPUS390XState *env, uint32_t desc)
> +{
> + env->cc_op = vfc64(v1, v2, v3, env, false, float64_le_quiet, GETPC());
> +}
> +
> +void HELPER(gvec_vfche64s_cc)(void *v1, const void *v2, const void *v3,
> + CPUS390XState *env, uint32_t desc)
> +{
> + env->cc_op = vfc64(v1, v2, v3, env, true, float64_le_quiet, GETPC());
> +}
>
Richard, still want to review this patch? I'm planning to send a pull
request soon.
--
Thanks,
David / dhildenb
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [Qemu-devel] [PATCH v2 06/22] s390x/tcg: Implement VECTOR FP COMPARE (EQUAL|HIGH|HIGH OR EQUAL)
2019-06-05 9:19 ` David Hildenbrand
@ 2019-06-05 14:47 ` Richard Henderson
0 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2019-06-05 14:47 UTC (permalink / raw)
To: David Hildenbrand, qemu-devel, Richard Henderson
Cc: Thomas Huth, Denys Vlasenko, Cornelia Huck, Pino Toscano,
Christian Borntraeger, qemu-s390x
On 6/5/19 4:19 AM, David Hildenbrand wrote:
> On 03.06.19 11:06, David Hildenbrand wrote:
>> Provide for all three instructions all four combinations of cc bit and
>> s bit.
>>
>> Signed-off-by: David Hildenbrand <david@redhat.com>
>> ---
>> target/s390x/helper.h | 12 ++++
>> target/s390x/insn-data.def | 6 ++
>> target/s390x/translate_vx.inc.c | 51 ++++++++++++++++
>> target/s390x/vec_fpu_helper.c | 104 ++++++++++++++++++++++++++++++++
>> 4 files changed, 173 insertions(+)
>>
>> diff --git a/target/s390x/helper.h b/target/s390x/helper.h
>> index d34d6802a6..33d3bacf74 100644
>> --- a/target/s390x/helper.h
>> +++ b/target/s390x/helper.h
>> @@ -254,6 +254,18 @@ DEF_HELPER_FLAGS_5(gvec_vfa64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
>> DEF_HELPER_FLAGS_5(gvec_vfa64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
>> DEF_HELPER_4(gvec_wfc64, void, cptr, cptr, env, i32)
>> DEF_HELPER_4(gvec_wfk64, void, cptr, cptr, env, i32)
>> +DEF_HELPER_FLAGS_5(gvec_vfce64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
>> +DEF_HELPER_FLAGS_5(gvec_vfce64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
>> +DEF_HELPER_5(gvec_vfce64_cc, void, ptr, cptr, cptr, env, i32)
>> +DEF_HELPER_5(gvec_vfce64s_cc, void, ptr, cptr, cptr, env, i32)
>> +DEF_HELPER_FLAGS_5(gvec_vfch64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
>> +DEF_HELPER_FLAGS_5(gvec_vfch64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
>> +DEF_HELPER_5(gvec_vfch64_cc, void, ptr, cptr, cptr, env, i32)
>> +DEF_HELPER_5(gvec_vfch64s_cc, void, ptr, cptr, cptr, env, i32)
>> +DEF_HELPER_FLAGS_5(gvec_vfche64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
>> +DEF_HELPER_FLAGS_5(gvec_vfche64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
>> +DEF_HELPER_5(gvec_vfche64_cc, void, ptr, cptr, cptr, env, i32)
>> +DEF_HELPER_5(gvec_vfche64s_cc, void, ptr, cptr, cptr, env, i32)
>>
>> #ifndef CONFIG_USER_ONLY
>> DEF_HELPER_3(servc, i32, env, i64, i64)
>> diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
>> index c45e101b10..446552f251 100644
>> --- a/target/s390x/insn-data.def
>> +++ b/target/s390x/insn-data.def
>> @@ -1212,6 +1212,12 @@
>> F(0xe7cb, WFC, VRR_a, V, 0, 0, 0, 0, wfc, 0, IF_VEC)
>> /* VECTOR FP COMPARE AND SIGNAL SCALAR */
>> F(0xe7ca, WFK, VRR_a, V, 0, 0, 0, 0, wfc, 0, IF_VEC)
>> +/* VECTOR FP COMPARE EQUAL */
>> + F(0xe7e8, VFCE, VRR_c, V, 0, 0, 0, 0, vfc, 0, IF_VEC)
>> +/* VECTOR FP COMPARE HIGH */
>> + F(0xe7eb, VFCH, VRR_c, V, 0, 0, 0, 0, vfc, 0, IF_VEC)
>> +/* VECTOR FP COMPARE HIGH OR EQUAL */
>> + F(0xe7ea, VFCHE, VRR_c, V, 0, 0, 0, 0, vfc, 0, IF_VEC)
>>
>> #ifndef CONFIG_USER_ONLY
>> /* COMPARE AND SWAP AND PURGE */
>> diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
>> index 283e8aa07a..5571a71e1a 100644
>> --- a/target/s390x/translate_vx.inc.c
>> +++ b/target/s390x/translate_vx.inc.c
>> @@ -2588,3 +2588,54 @@ static DisasJumpType op_wfc(DisasContext *s, DisasOps *o)
>> set_cc_static(s);
>> return DISAS_NEXT;
>> }
>> +
>> +static DisasJumpType op_vfc(DisasContext *s, DisasOps *o)
>> +{
>> + const uint8_t fpf = get_field(s->fields, m4);
>> + const uint8_t m5 = get_field(s->fields, m5);
>> + const uint8_t m6 = get_field(s->fields, m6);
>> + const bool se = extract32(m5, 3, 1);
>> + const bool cs = extract32(m6, 0, 1);
>> + gen_helper_gvec_3_ptr *fn;
>> +
>> + if (fpf != FPF_LONG || extract32(m5, 0, 3) || extract32(m6, 1, 3)) {
>> + gen_program_exception(s, PGM_SPECIFICATION);
>> + return DISAS_NORETURN;
>> + }
>> +
>> + if (cs) {
>> + switch (s->fields->op2) {
>> + case 0xe8:
>> + fn = se ? gen_helper_gvec_vfce64s_cc : gen_helper_gvec_vfce64_cc;
>> + break;
>> + case 0xeb:
>> + fn = se ? gen_helper_gvec_vfch64s_cc : gen_helper_gvec_vfch64_cc;
>> + break;
>> + case 0xea:
>> + fn = se ? gen_helper_gvec_vfche64s_cc : gen_helper_gvec_vfche64_cc;
>> + break;
>> + default:
>> + g_assert_not_reached();
>> + }
>> + } else {
>> + switch (s->fields->op2) {
>> + case 0xe8:
>> + fn = se ? gen_helper_gvec_vfce64s : gen_helper_gvec_vfce64;
>> + break;
>> + case 0xeb:
>> + fn = se ? gen_helper_gvec_vfch64s : gen_helper_gvec_vfch64;
>> + break;
>> + case 0xea:
>> + fn = se ? gen_helper_gvec_vfche64s : gen_helper_gvec_vfche64;
>> + break;
>> + default:
>> + g_assert_not_reached();
>> + }
>> + }
>> + gen_gvec_3_ptr(get_field(s->fields, v1), get_field(s->fields, v2),
>> + get_field(s->fields, v3), cpu_env, 0, fn);
>> + if (cs) {
>> + set_cc_static(s);
>> + }
>> + return DISAS_NEXT;
>> +}
>> diff --git a/target/s390x/vec_fpu_helper.c b/target/s390x/vec_fpu_helper.c
>> index f9357d9221..e72500d4d5 100644
>> --- a/target/s390x/vec_fpu_helper.c
>> +++ b/target/s390x/vec_fpu_helper.c
>> @@ -149,3 +149,107 @@ void HELPER(gvec_wfk64)(const void *v1, const void *v2, CPUS390XState *env,
>> {
>> env->cc_op = wfc64(v1, v2, env, true, GETPC());
>> }
>> +
>> +typedef int (*vfc64_fn)(float64 a, float64 b, float_status *status);
>> +static int vfc64(S390Vector *v1, const S390Vector *v2, const S390Vector *v3,
>> + CPUS390XState *env, bool s, vfc64_fn fn, uintptr_t retaddr)
>> +{
>> + uint8_t vxc, vec_exc = 0;
>> + S390Vector tmp = {};
>> + int match = 0;
>> + int i;
>> +
>> + for (i = 0; i < 2; i++) {
>> + const float64 a = s390_vec_read_element64(v2, i);
>> + const float64 b = s390_vec_read_element64(v3, i);
>> +
>> + /* swap the order of the parameters, so we can use existing functions */
>> + if (fn(b, a, &env->fpu_status)) {
>> + match++;
>> + s390_vec_write_element64(&tmp, i, -1ull);
>> + }
>> + vxc = check_ieee_exc(env, i, false, &vec_exc);
>> + if (s || vxc) {
>> + break;
>> + }
>> + }
>> +
>> + handle_ieee_exc(env, vxc, vec_exc, retaddr);
>> + *v1 = tmp;
>> + if (match) {
>> + return s || match == 2 ? 0 : 1;
>> + }
>> + return 3;
>> +}
>> +
>> +void HELPER(gvec_vfce64)(void *v1, const void *v2, const void *v3,
>> + CPUS390XState *env, uint32_t desc)
>> +{
>> + vfc64(v1, v2, v3, env, false, float64_eq_quiet, GETPC());
>> +}
>> +
>> +void HELPER(gvec_vfce64s)(void *v1, const void *v2, const void *v3,
>> + CPUS390XState *env, uint32_t desc)
>> +{
>> + vfc64(v1, v2, v3, env, true, float64_eq_quiet, GETPC());
>> +}
>> +
>> +void HELPER(gvec_vfce64_cc)(void *v1, const void *v2, const void *v3,
>> + CPUS390XState *env, uint32_t desc)
>> +{
>> + env->cc_op = vfc64(v1, v2, v3, env, false, float64_eq_quiet, GETPC());
>> +}
>> +
>> +void HELPER(gvec_vfce64s_cc)(void *v1, const void *v2, const void *v3,
>> + CPUS390XState *env, uint32_t desc)
>> +{
>> + env->cc_op = vfc64(v1, v2, v3, env, true, float64_eq_quiet, GETPC());
>> +}
>> +
>> +void HELPER(gvec_vfch64)(void *v1, const void *v2, const void *v3,
>> + CPUS390XState *env, uint32_t desc)
>> +{
>> + vfc64(v1, v2, v3, env, false, float64_lt_quiet, GETPC());
>> +}
>> +
>> +void HELPER(gvec_vfch64s)(void *v1, const void *v2, const void *v3,
>> + CPUS390XState *env, uint32_t desc)
>> +{
>> + vfc64(v1, v2, v3, env, true, float64_lt_quiet, GETPC());
>> +}
>> +
>> +void HELPER(gvec_vfch64_cc)(void *v1, const void *v2, const void *v3,
>> + CPUS390XState *env, uint32_t desc)
>> +{
>> + env->cc_op = vfc64(v1, v2, v3, env, false, float64_lt_quiet, GETPC());
>> +}
>> +
>> +void HELPER(gvec_vfch64s_cc)(void *v1, const void *v2, const void *v3,
>> + CPUS390XState *env, uint32_t desc)
>> +{
>> + env->cc_op = vfc64(v1, v2, v3, env, true, float64_lt_quiet, GETPC());
>> +}
>> +
>> +void HELPER(gvec_vfche64)(void *v1, const void *v2, const void *v3,
>> + CPUS390XState *env, uint32_t desc)
>> +{
>> + vfc64(v1, v2, v3, env, false, float64_le_quiet, GETPC());
>> +}
>> +
>> +void HELPER(gvec_vfche64s)(void *v1, const void *v2, const void *v3,
>> + CPUS390XState *env, uint32_t desc)
>> +{
>> + vfc64(v1, v2, v3, env, true, float64_le_quiet, GETPC());
>> +}
>> +
>> +void HELPER(gvec_vfche64_cc)(void *v1, const void *v2, const void *v3,
>> + CPUS390XState *env, uint32_t desc)
>> +{
>> + env->cc_op = vfc64(v1, v2, v3, env, false, float64_le_quiet, GETPC());
>> +}
>> +
>> +void HELPER(gvec_vfche64s_cc)(void *v1, const void *v2, const void *v3,
>> + CPUS390XState *env, uint32_t desc)
>> +{
>> + env->cc_op = vfc64(v1, v2, v3, env, true, float64_le_quiet, GETPC());
>> +}
>>
>
> Richard, still want to review this patch? I'm planning to send a pull
> request soon.
>
Somehow I bypassed this one. Anyway,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 34+ messages in thread
end of thread, other threads:[~2019-06-05 14:55 UTC | newest]
Thread overview: 34+ messages (download: mbox.gz / follow: Atom feed)
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2019-06-03 9:06 [Qemu-devel] [PATCH v2 00/22] s390x/tcg: Vector Instruction Support Part 4 David Hildenbrand
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 01/22] s390x/tcg: Store only the necessary amount of doublewords for STFLE David Hildenbrand
2019-06-03 9:07 ` David Hildenbrand
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 02/22] s390x/tcg: Introduce tcg_s390_vector_exception() David Hildenbrand
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 03/22] s390x/tcg: Export float_comp_to_cc() and float(32|64|128)_dcmask() David Hildenbrand
2019-06-03 16:17 ` Richard Henderson
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 04/22] s390x/tcg: Implement VECTOR FP ADD David Hildenbrand
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 05/22] s390x/tcg: Implement VECTOR FP COMPARE (AND SIGNAL) SCALAR David Hildenbrand
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 06/22] s390x/tcg: Implement VECTOR FP COMPARE (EQUAL|HIGH|HIGH OR EQUAL) David Hildenbrand
2019-06-05 9:19 ` David Hildenbrand
2019-06-05 14:47 ` Richard Henderson
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 07/22] s390x/tcg: Implement VECTOR FP CONVERT FROM FIXED 64-BIT David Hildenbrand
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 08/22] s390x/tcg: Implement VECTOR FP CONVERT FROM LOGICAL 64-BIT David Hildenbrand
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 09/22] s390x/tcg: Implement VECTOR FP CONVERT TO FIXED 64-BIT David Hildenbrand
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 10/22] s390x/tcg: Implement VECTOR FP CONVERT TO LOGICAL 64-BIT David Hildenbrand
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 11/22] s390x/tcg: Implement VECTOR FP DIVIDE David Hildenbrand
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 12/22] s390x/tcg: Implement VECTOR LOAD FP INTEGER David Hildenbrand
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 13/22] s390x/tcg: Implement VECTOR LOAD LENGTHENED David Hildenbrand
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 14/22] s390x/tcg: Implement VECTOR LOAD ROUNDED David Hildenbrand
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 15/22] s390x/tcg: Implement VECTOR FP MULTIPLY David Hildenbrand
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 16/22] s390x/tcg: Implement VECTOR FP MULTIPLY AND (ADD|SUBTRACT) David Hildenbrand
2019-06-03 16:16 ` Richard Henderson
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 17/22] s390x/tcg: Implement VECTOR FP PERFORM SIGN OPERATION David Hildenbrand
2019-06-03 16:18 ` Richard Henderson
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 18/22] s390x/tcg: Implement VECTOR FP SQUARE ROOT David Hildenbrand
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 19/22] s390x/tcg: Implement VECTOR FP SUBTRACT David Hildenbrand
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 20/22] s390x/tcg: Implement VECTOR FP TEST DATA CLASS IMMEDIATE David Hildenbrand
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 21/22] s390x/tcg: Allow linux-user to use vector instructions David Hildenbrand
2019-06-04 7:45 ` Laurent Vivier
2019-06-04 8:50 ` Laurent Vivier
2019-06-04 8:56 ` David Hildenbrand
2019-06-03 9:06 ` [Qemu-devel] [PATCH v2 22/22] s390x/tcg: We support the Vector Facility David Hildenbrand
2019-06-03 9:09 ` [Qemu-devel] [PATCH v2 00/22] s390x/tcg: Vector Instruction Support Part 4 David Hildenbrand
2019-06-03 9:17 ` [Qemu-devel] [PATCH v2 23/22] s390x: Bump the "qemu" CPU model up to a stripped-down z13 David Hildenbrand
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