* [PATCH] arm64: tegra: add CPU cache topology for Tegra186
@ 2019-06-04 2:35 ` Joseph Lo
0 siblings, 0 replies; 4+ messages in thread
From: Joseph Lo @ 2019-06-04 2:35 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter; +Cc: linux-tegra, linux-arm-kernel, Joseph Lo
Tegra186 has two CPU clusters with its own cache hierarchy. This patch
adds them with the cache information of each of the CPUs.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 426ac0bdf6a6..26055c7f26e7 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -1128,38 +1128,52 @@
cpu@0 {
compatible = "nvidia,tegra186-denver";
device_type = "cpu";
+ next-level-cache = <&L2_DENVER>;
reg = <0x000>;
};
cpu@1 {
compatible = "nvidia,tegra186-denver";
device_type = "cpu";
+ next-level-cache = <&L2_DENVER>;
reg = <0x001>;
};
cpu@2 {
compatible = "arm,cortex-a57";
device_type = "cpu";
+ next-level-cache = <&L2_A57>;
reg = <0x100>;
};
cpu@3 {
compatible = "arm,cortex-a57";
device_type = "cpu";
+ next-level-cache = <&L2_A57>;
reg = <0x101>;
};
cpu@4 {
compatible = "arm,cortex-a57";
device_type = "cpu";
+ next-level-cache = <&L2_A57>;
reg = <0x102>;
};
cpu@5 {
compatible = "arm,cortex-a57";
device_type = "cpu";
+ next-level-cache = <&L2_A57>;
reg = <0x103>;
};
+
+ L2_DENVER: l2-cache0 {
+ compatible = "cache";
+ };
+
+ L2_A57: l2-cache1 {
+ compatible = "cache";
+ };
};
bpmp: bpmp {
--
2.21.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH] arm64: tegra: add CPU cache topology for Tegra186
@ 2019-06-04 2:35 ` Joseph Lo
0 siblings, 0 replies; 4+ messages in thread
From: Joseph Lo @ 2019-06-04 2:35 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter; +Cc: linux-tegra, linux-arm-kernel, Joseph Lo
Tegra186 has two CPU clusters with its own cache hierarchy. This patch
adds them with the cache information of each of the CPUs.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 426ac0bdf6a6..26055c7f26e7 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -1128,38 +1128,52 @@
cpu@0 {
compatible = "nvidia,tegra186-denver";
device_type = "cpu";
+ next-level-cache = <&L2_DENVER>;
reg = <0x000>;
};
cpu@1 {
compatible = "nvidia,tegra186-denver";
device_type = "cpu";
+ next-level-cache = <&L2_DENVER>;
reg = <0x001>;
};
cpu@2 {
compatible = "arm,cortex-a57";
device_type = "cpu";
+ next-level-cache = <&L2_A57>;
reg = <0x100>;
};
cpu@3 {
compatible = "arm,cortex-a57";
device_type = "cpu";
+ next-level-cache = <&L2_A57>;
reg = <0x101>;
};
cpu@4 {
compatible = "arm,cortex-a57";
device_type = "cpu";
+ next-level-cache = <&L2_A57>;
reg = <0x102>;
};
cpu@5 {
compatible = "arm,cortex-a57";
device_type = "cpu";
+ next-level-cache = <&L2_A57>;
reg = <0x103>;
};
+
+ L2_DENVER: l2-cache0 {
+ compatible = "cache";
+ };
+
+ L2_A57: l2-cache1 {
+ compatible = "cache";
+ };
};
bpmp: bpmp {
--
2.21.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] arm64: tegra: add CPU cache topology for Tegra186
2019-06-04 2:35 ` Joseph Lo
@ 2019-06-04 9:05 ` Sudeep Holla
-1 siblings, 0 replies; 4+ messages in thread
From: Sudeep Holla @ 2019-06-04 9:05 UTC (permalink / raw)
To: Joseph Lo
Cc: linux-tegra, Thierry Reding, Sudeep Holla, linux-arm-kernel,
Jonathan Hunter
On Tue, Jun 04, 2019 at 10:35:35AM +0800, Joseph Lo wrote:
> Tegra186 has two CPU clusters with its own cache hierarchy. This patch
> adds them with the cache information of each of the CPUs.
>
Please add geometry information if you prefer to expose the same to the
user-space. We removed support to read the system registers to fetch
these information. In-fact it was for one of the Tegra platforms that
geometry in those registers don't match the actual values, at-least
that was the argument to drop the support for the same.
--
Regards,
Sudeep
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] arm64: tegra: add CPU cache topology for Tegra186
@ 2019-06-04 9:05 ` Sudeep Holla
0 siblings, 0 replies; 4+ messages in thread
From: Sudeep Holla @ 2019-06-04 9:05 UTC (permalink / raw)
To: Joseph Lo
Cc: linux-tegra, Thierry Reding, Sudeep Holla, linux-arm-kernel,
Jonathan Hunter
On Tue, Jun 04, 2019 at 10:35:35AM +0800, Joseph Lo wrote:
> Tegra186 has two CPU clusters with its own cache hierarchy. This patch
> adds them with the cache information of each of the CPUs.
>
Please add geometry information if you prefer to expose the same to the
user-space. We removed support to read the system registers to fetch
these information. In-fact it was for one of the Tegra platforms that
geometry in those registers don't match the actual values, at-least
that was the argument to drop the support for the same.
--
Regards,
Sudeep
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2019-06-04 9:06 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-06-04 2:35 [PATCH] arm64: tegra: add CPU cache topology for Tegra186 Joseph Lo
2019-06-04 2:35 ` Joseph Lo
2019-06-04 9:05 ` Sudeep Holla
2019-06-04 9:05 ` Sudeep Holla
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.