From: "Ondřej Jirman" <megous@megous.com> To: "Clément Péron" <peron.clem@gmail.com> Cc: linux-sunxi <linux-sunxi@googlegroups.com>, Maxime Ripard <maxime.ripard@bootlin.com>, Chen-Yu Tsai <wens@csie.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, "moderated list:ARM/Allwinner sunXi SoC support" <linux-arm-kernel@lists.infradead.org>, "open list:COMMON CLK FRAMEWORK" <linux-clk@vger.kernel.org>, open list <linux-kernel@vger.kernel.org> Subject: Re: [linux-sunxi] [PATCH v2] clk: sunxi-ng: sun50i-h6-r: Fix incorrect W1 clock gate register Date: Tue, 4 Jun 2019 18:21:44 +0200 [thread overview] Message-ID: <20190604162144.hba5bmkdnidco7pf@core.my.home> (raw) In-Reply-To: <CAJiuCcda0ZDDrbdOF7TpTeoUOgt7GeS6wcgy45DRCo_U2XX6bQ@mail.gmail.com> Hi Clément, On Tue, Jun 04, 2019 at 06:14:15PM +0200, Clément Péron wrote: > Hi Ondrej, > > On Tue, 4 Jun 2019 at 17:40, megous via linux-sunxi > <linux-sunxi@googlegroups.com> wrote: > > > > From: Ondrej Jirman <megous@megous.com> > > > > The current code defines W1 clock gate to be at 0x1cc, overlaying it > > with the IR gate. > > > > Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver > > causing interrupt floods on H6 (because interrupt flags can't be cleared, > > due to IR module's bus being disabled). > > > > Signed-off-by: Ondrej Jirman <megous@megous.com> > > Fixes: b7c7b05065aa77ae ("clk: sunxi-ng: add support for H6 PRCM CCU") > > --- > > drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c > > index 27554eaf6929..8d05d4f1f8a1 100644 > > --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c > > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c > > @@ -104,7 +104,7 @@ static SUNXI_CCU_GATE(r_apb2_i2c_clk, "r-apb2-i2c", "r-apb2", > > static SUNXI_CCU_GATE(r_apb1_ir_clk, "r-apb1-ir", "r-apb1", > > 0x1cc, BIT(0), 0); > > static SUNXI_CCU_GATE(r_apb1_w1_clk, "r-apb1-w1", "r-apb1", > > - 0x1cc, BIT(0), 0); > > + 0x1ec, BIT(0), 0); > Just for information where did you find this information? > Using the vendor kernel or user manual? Informed guess. All gates and resets are in the same register. And you can see below that reset register for w1 is 0x1ec. (reset register for ir is 0x1cc) regards, o. > Thanks, > Clément > > > > > /* Information of IR(RX) mod clock is gathered from BSP source code */ > > static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" }; > > -- > > 2.21.0 > > > > -- > > You received this message because you are subscribed to the Google Groups "linux-sunxi" group. > > To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com. > > To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20190604154036.23211-1-megous%40megous.com. > > For more options, visit https://groups.google.com/d/optout.
WARNING: multiple messages have this Message-ID (diff)
From: "Ondřej Jirman" <megous@megous.com> To: "Clément Péron" <peron.clem@gmail.com> Cc: Maxime Ripard <maxime.ripard@bootlin.com>, Michael Turquette <mturquette@baylibre.com>, Chen-Yu Tsai <wens@csie.org>, open list <linux-kernel@vger.kernel.org>, Stephen Boyd <sboyd@kernel.org>, linux-sunxi <linux-sunxi@googlegroups.com>, "open list:COMMON CLK FRAMEWORK" <linux-clk@vger.kernel.org>, "moderated list:ARM/Allwinner sunXi SoC support" <linux-arm-kernel@lists.infradead.org> Subject: Re: [linux-sunxi] [PATCH v2] clk: sunxi-ng: sun50i-h6-r: Fix incorrect W1 clock gate register Date: Tue, 4 Jun 2019 18:21:44 +0200 [thread overview] Message-ID: <20190604162144.hba5bmkdnidco7pf@core.my.home> (raw) In-Reply-To: <CAJiuCcda0ZDDrbdOF7TpTeoUOgt7GeS6wcgy45DRCo_U2XX6bQ@mail.gmail.com> Hi Clément, On Tue, Jun 04, 2019 at 06:14:15PM +0200, Clément Péron wrote: > Hi Ondrej, > > On Tue, 4 Jun 2019 at 17:40, megous via linux-sunxi > <linux-sunxi@googlegroups.com> wrote: > > > > From: Ondrej Jirman <megous@megous.com> > > > > The current code defines W1 clock gate to be at 0x1cc, overlaying it > > with the IR gate. > > > > Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver > > causing interrupt floods on H6 (because interrupt flags can't be cleared, > > due to IR module's bus being disabled). > > > > Signed-off-by: Ondrej Jirman <megous@megous.com> > > Fixes: b7c7b05065aa77ae ("clk: sunxi-ng: add support for H6 PRCM CCU") > > --- > > drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c > > index 27554eaf6929..8d05d4f1f8a1 100644 > > --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c > > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c > > @@ -104,7 +104,7 @@ static SUNXI_CCU_GATE(r_apb2_i2c_clk, "r-apb2-i2c", "r-apb2", > > static SUNXI_CCU_GATE(r_apb1_ir_clk, "r-apb1-ir", "r-apb1", > > 0x1cc, BIT(0), 0); > > static SUNXI_CCU_GATE(r_apb1_w1_clk, "r-apb1-w1", "r-apb1", > > - 0x1cc, BIT(0), 0); > > + 0x1ec, BIT(0), 0); > Just for information where did you find this information? > Using the vendor kernel or user manual? Informed guess. All gates and resets are in the same register. And you can see below that reset register for w1 is 0x1ec. (reset register for ir is 0x1cc) regards, o. > Thanks, > Clément > > > > > /* Information of IR(RX) mod clock is gathered from BSP source code */ > > static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" }; > > -- > > 2.21.0 > > > > -- > > You received this message because you are subscribed to the Google Groups "linux-sunxi" group. > > To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com. > > To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20190604154036.23211-1-megous%40megous.com. > > For more options, visit https://groups.google.com/d/optout. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-06-04 16:21 UTC|newest] Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-06-04 15:40 [PATCH v2] clk: sunxi-ng: sun50i-h6-r: Fix incorrect W1 clock gate register megous 2019-06-04 15:40 ` megous 2019-06-04 16:14 ` [linux-sunxi] " Clément Péron 2019-06-04 16:14 ` Clément Péron 2019-06-04 16:21 ` Ondřej Jirman [this message] 2019-06-04 16:21 ` Ondřej Jirman 2019-06-04 16:36 ` Clément Péron 2019-06-04 16:36 ` Clément Péron 2019-06-05 11:49 ` Maxime Ripard 2019-06-05 11:49 ` Maxime Ripard
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20190604162144.hba5bmkdnidco7pf@core.my.home \ --to=megous@megous.com \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-clk@vger.kernel.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-sunxi@googlegroups.com \ --cc=maxime.ripard@bootlin.com \ --cc=mturquette@baylibre.com \ --cc=peron.clem@gmail.com \ --cc=sboyd@kernel.org \ --cc=wens@csie.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.