[PATCH] drm/i915/icl: Enable SSC for ICL using panel_use_ssc

* [PATCH] drm/i915/icl: Enable SSC for ICL using panel_use_ssc
@ 2019-06-05 21:57 Aditya Swarup
  2019-06-05 22:48 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
                   ` (3 more replies)
  0 siblings, 4 replies; 5+ messages in thread
From: Aditya Swarup @ 2019-06-05 21:57 UTC (permalink / raw)
  To: intel-gfx; +Cc: Jani Nikula, Lucas De Marchi

To enable SSC for DPLL, we need to set the bit DPLL_CFGCR0_SSC_ENABLE_ICL
while configuring cfgcr0 register. This bit should be set only when we
are enabling SSC using kernel mod parameter panel_use_ssc.

Also, moving intel_panel_use_ssc() declaration to intel_drv.h.

Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c  | 8 --------
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 4 ++++
 drivers/gpu/drm/i915/intel_drv.h      | 8 ++++++++
 3 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 012ad08f38c3..34c82a17ab1b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7377,14 +7377,6 @@ intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
 		    constant_n);
 }
 
-static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
-{
-	if (i915_modparams.panel_use_ssc >= 0)
-		return i915_modparams.panel_use_ssc != 0;
-	return dev_priv->vbt.lvds_use_ssc
-		&& !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
-}
-
 static u32 pnv_dpll_compute_fp(struct dpll *dpll)
 {
 	return (1 << dpll->n) << 16 | dpll->m2;
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 897d93537414..6c460fb81d6a 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2527,6 +2527,10 @@ static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
 	cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(pll_params.dco_fraction) |
 		 pll_params.dco_integer;
 
+	if (intel_panel_use_ssc(dev_priv)) {
+		cfgcr0 |= DPLL_CFGCR0_SSC_ENABLE_ICL;
+	}
+
 	cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params.qdiv_ratio) |
 		 DPLL_CFGCR1_QDIV_MODE(pll_params.qdiv_mode) |
 		 DPLL_CFGCR1_KDIV(pll_params.kdiv) |
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 270f5bb43d9b..e9af27e841b3 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1497,6 +1497,14 @@ intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
 {
 	drm_wait_one_vblank(&dev_priv->drm, pipe);
 }
+static inline bool
+intel_panel_use_ssc(struct drm_i915_private *dev_priv)
+{
+	if (i915_modparams.panel_use_ssc >= 0)
+		return i915_modparams.panel_use_ssc != 0;
+	return dev_priv->vbt.lvds_use_ssc
+		&& !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
+}
 static inline void
 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
 {
-- 
2.17.1

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