[PATCH 00/21] Implicit dev_priv removal

[PATCH 00/21] Implicit dev_priv removal

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Mostly patches reworking the code and GEM init paths to remove some implicit
dev_priv dependencies (I915_READ/I915_WRITE), plus some small tweaks to tidy
GEM init paths to use more logical input parameters (enabled by the conversion
to uncore mmio accessors).

A few tiny fixups/tweaks as well which I spotted by doing the conversion.

Tvrtko Ursulin (21):
  drm/i915: Reset only affected engines when handling error capture
  drm/i915: Tidy engine mask types in hangcheck
  drm/i915: Make Gen6/7 RING_FAULT_REG access engine centric
  drm/i915: Extract engine fault reset to a helper
  drm/i915: Make i915_clear_error_registers take uncore
  drm/i915: Convert some more bits to use engine mmio accessors
  drm/i915: Make read_subslice_reg take uncore
  drm/i915: Tidy intel_execlists_submission_init
  drm/i915: Make i915_check_and_clear_faults take uncore
  drm/i915: Move scheduler caps init to i915_gem_init
  drm/i915: Remove impossible path from i915_gem_init_swizzling
  drm/i915: Convert i915_gem_init_swizzling to uncore
  drm/i915: Convert init_unused_rings to uncore
  drm/i915: Convert gt workarounds to uncore
  drm/i915: Convert intel_mocs_init_l3cc_table to uncore
  drm/i915: Convert i915_ppgtt_init_hw to uncore
  drm/i915: Consolidate some open coded mmio rmw
  drm/i915: Convert i915_gem_init_hw to uncore
  drm/i915: Convert intel_vgt_(de)balloon to uncore
  drm/i915: Make GuC GGTT reservation work on ggtt
  drm/i915: Unexport i915_gem_init/fini_aliasing_ppgtt

 drivers/gpu/drm/i915/gt/intel_engine.h      |  18 +++
 drivers/gpu/drm/i915/gt/intel_engine_cs.c   |  22 +--
 drivers/gpu/drm/i915/gt/intel_hangcheck.c   |   6 +-
 drivers/gpu/drm/i915/gt/intel_lrc.c         |  38 ++---
 drivers/gpu/drm/i915/gt/intel_mocs.c        |  20 ++-
 drivers/gpu/drm/i915/gt/intel_mocs.h        |   3 +-
 drivers/gpu/drm/i915/gt/intel_reset.c       |  21 +--
 drivers/gpu/drm/i915/gt/intel_reset.h       |   4 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c |  10 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.h |   6 +-
 drivers/gpu/drm/i915/i915_drv.c             |   6 +-
 drivers/gpu/drm/i915/i915_drv.h             |   2 +-
 drivers/gpu/drm/i915/i915_gem.c             | 140 ++++++++++-------
 drivers/gpu/drm/i915/i915_gem_gtt.c         | 163 +++++++++++---------
 drivers/gpu/drm/i915/i915_gem_gtt.h         |   7 +-
 drivers/gpu/drm/i915/i915_gpu_error.c       |   4 +-
 drivers/gpu/drm/i915/i915_reg.h             |   2 +-
 drivers/gpu/drm/i915/i915_vgpu.c            |  24 +--
 drivers/gpu/drm/i915/i915_vgpu.h            |   4 +-
 drivers/gpu/drm/i915/intel_guc.c            |  18 +--
 drivers/gpu/drm/i915/intel_guc.h            |   6 +-
 drivers/gpu/drm/i915/intel_guc_submission.c |   4 +-
 22 files changed, 298 insertions(+), 230 deletions(-)

-- 
2.20.1

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[PATCH 01/21] drm/i915: Reset only affected engines when handling error capture

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Pass down the engine mask to i915_clear_error_registers so only affected
engines can be reset on the Gen6/7 path.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_reset.c | 7 ++++---
 drivers/gpu/drm/i915/gt/intel_reset.h | 3 ++-
 drivers/gpu/drm/i915/i915_gem_gtt.c   | 2 +-
 3 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index 377bc546a68f..7bfb76eb0291 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -1160,7 +1160,8 @@ static void clear_register(struct intel_uncore *uncore, i915_reg_t reg)
 	intel_uncore_rmw(uncore, reg, 0, 0);
 }
 
-void i915_clear_error_registers(struct drm_i915_private *i915)
+void i915_clear_error_registers(struct drm_i915_private *i915,
+				intel_engine_mask_t engine_mask)
 {
 	struct intel_uncore *uncore = &i915->uncore;
 	u32 eir;
@@ -1193,7 +1194,7 @@ void i915_clear_error_registers(struct drm_i915_private *i915)
 		struct intel_engine_cs *engine;
 		enum intel_engine_id id;
 
-		for_each_engine(engine, i915, id) {
+		for_each_engine_masked(engine, i915, engine_mask, id) {
 			rmw_clear(uncore,
 				  RING_FAULT_REG(engine), RING_FAULT_VALID);
 			intel_uncore_posting_read(uncore,
@@ -1250,7 +1251,7 @@ void i915_handle_error(struct drm_i915_private *i915,
 
 	if (flags & I915_ERROR_CAPTURE) {
 		i915_capture_error_state(i915, engine_mask, msg);
-		i915_clear_error_registers(i915);
+		i915_clear_error_registers(i915, engine_mask);
 	}
 
 	/*
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.h b/drivers/gpu/drm/i915/gt/intel_reset.h
index b52efaab4941..4f3c1acac1a3 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.h
+++ b/drivers/gpu/drm/i915/gt/intel_reset.h
@@ -25,7 +25,8 @@ void i915_handle_error(struct drm_i915_private *i915,
 		       const char *fmt, ...);
 #define I915_ERROR_CAPTURE BIT(0)
 
-void i915_clear_error_registers(struct drm_i915_private *i915);
+void i915_clear_error_registers(struct drm_i915_private *i915,
+				intel_engine_mask_t engine_mask);
 
 void i915_reset(struct drm_i915_private *i915,
 		intel_engine_mask_t stalled_mask,
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 56a436858043..5ee3790f2895 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2358,7 +2358,7 @@ void i915_check_and_clear_faults(struct drm_i915_private *dev_priv)
 	else
 		return;
 
-	i915_clear_error_registers(dev_priv);
+	i915_clear_error_registers(dev_priv, ALL_ENGINES);
 }
 
 void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv)
-- 
2.20.1

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[PATCH 02/21] drm/i915: Tidy engine mask types in hangcheck

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

We can use intel_engine_mask_t to align with the rest of the codebase.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_hangcheck.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_hangcheck.c b/drivers/gpu/drm/i915/gt/intel_hangcheck.c
index 3a4d09b80fa0..174bb0a60309 100644
--- a/drivers/gpu/drm/i915/gt/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/intel_hangcheck.c
@@ -223,8 +223,8 @@ static void hangcheck_accumulate_sample(struct intel_engine_cs *engine,
 }
 
 static void hangcheck_declare_hang(struct drm_i915_private *i915,
-				   unsigned int hung,
-				   unsigned int stuck)
+				   intel_engine_mask_t hung,
+				   intel_engine_mask_t stuck)
 {
 	struct intel_engine_cs *engine;
 	intel_engine_mask_t tmp;
@@ -259,9 +259,9 @@ static void i915_hangcheck_elapsed(struct work_struct *work)
 	struct drm_i915_private *dev_priv =
 		container_of(work, typeof(*dev_priv),
 			     gpu_error.hangcheck_work.work);
+	intel_engine_mask_t hung = 0, stuck = 0, wedged = 0;
 	struct intel_engine_cs *engine;
 	enum intel_engine_id id;
-	unsigned int hung = 0, stuck = 0, wedged = 0;
 	intel_wakeref_t wakeref;
 
 	if (!i915_modparams.enable_hangcheck)
-- 
2.20.1

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[PATCH 03/21] drm/i915: Make Gen6/7 RING_FAULT_REG access engine centric

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Similar to earlier conversions, eliminate the implicit dev_priv by
introducing some helpers which take the engine parameter (since the
register itself is per engine).

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine.h | 18 ++++++++++++++++++
 drivers/gpu/drm/i915/gt/intel_reset.c  |  6 ++----
 drivers/gpu/drm/i915/i915_gem_gtt.c    |  2 +-
 drivers/gpu/drm/i915/i915_gpu_error.c  |  2 +-
 4 files changed, 22 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
index 1c0db151f0b1..a12b8ead4463 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -68,6 +68,24 @@ struct drm_printer;
 #define ENGINE_WRITE(...)	__ENGINE_WRITE_OP(write, __VA_ARGS__)
 #define ENGINE_WRITE_FW(...)	__ENGINE_WRITE_OP(write_fw, __VA_ARGS__)
 
+#define GEN6_RING_FAULT_REG_READ(engine__) \
+	intel_uncore_read((engine__)->uncore, RING_FAULT_REG(engine__))
+
+#define GEN6_RING_FAULT_REG_POSTING_READ(engine__) \
+	intel_uncore_posting_read((engine__)->uncore, RING_FAULT_REG(engine__))
+
+#define GEN6_RING_FAULT_REG_RMW(engine__, clear__, set__) \
+({ \
+	u32 __val; \
+\
+	__val = intel_uncore_read((engine__)->uncore, \
+				  RING_FAULT_REG(engine__)); \
+	__val &= ~clear__; \
+	__val |= set__; \
+	intel_uncore_write((engine__)->uncore, RING_FAULT_REG(engine__), \
+			   __val); \
+})
+
 /* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
  * do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
  */
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index 7bfb76eb0291..de53927c583f 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -1195,10 +1195,8 @@ void i915_clear_error_registers(struct drm_i915_private *i915,
 		enum intel_engine_id id;
 
 		for_each_engine_masked(engine, i915, engine_mask, id) {
-			rmw_clear(uncore,
-				  RING_FAULT_REG(engine), RING_FAULT_VALID);
-			intel_uncore_posting_read(uncore,
-						  RING_FAULT_REG(engine));
+			GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0);
+			GEN6_RING_FAULT_REG_POSTING_READ(engine);
 		}
 	}
 }
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 5ee3790f2895..84104e9cc507 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2305,7 +2305,7 @@ static void gen6_check_faults(struct drm_i915_private *dev_priv)
 	u32 fault;
 
 	for_each_engine(engine, dev_priv, id) {
-		fault = I915_READ(RING_FAULT_REG(engine));
+		fault = GEN6_RING_FAULT_REG_READ(engine);
 		if (fault & RING_FAULT_VALID) {
 			DRM_DEBUG_DRIVER("Unexpected fault\n"
 					 "\tAddr: 0x%08lx\n"
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 707811256501..2f85de034d8f 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1149,7 +1149,7 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
 		if (INTEL_GEN(dev_priv) >= 8)
 			ee->fault_reg = I915_READ(GEN8_RING_FAULT_REG);
 		else
-			ee->fault_reg = I915_READ(RING_FAULT_REG(engine));
+			ee->fault_reg = GEN6_RING_FAULT_REG_READ(engine);
 	}
 
 	if (INTEL_GEN(dev_priv) >= 4) {
-- 
2.20.1

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[PATCH 04/21] drm/i915: Extract engine fault reset to a helper

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Just tidying the flow a bit.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_reset.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index de53927c583f..a6ecfdc735c4 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -1160,6 +1160,12 @@ static void clear_register(struct intel_uncore *uncore, i915_reg_t reg)
 	intel_uncore_rmw(uncore, reg, 0, 0);
 }
 
+static void gen8_clear_engine_error_register(struct intel_engine_cs *engine)
+{
+	GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0);
+	GEN6_RING_FAULT_REG_POSTING_READ(engine);
+}
+
 void i915_clear_error_registers(struct drm_i915_private *i915,
 				intel_engine_mask_t engine_mask)
 {
@@ -1194,10 +1200,8 @@ void i915_clear_error_registers(struct drm_i915_private *i915,
 		struct intel_engine_cs *engine;
 		enum intel_engine_id id;
 
-		for_each_engine_masked(engine, i915, engine_mask, id) {
-			GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0);
-			GEN6_RING_FAULT_REG_POSTING_READ(engine);
-		}
+		for_each_engine_masked(engine, i915, engine_mask, id)
+			gen8_clear_engine_error_register(engine);
 	}
 }
 
-- 
2.20.1

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[PATCH 05/21] drm/i915: Make i915_clear_error_registers take uncore

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

The function mostly uses uncore so make the argument reflect that.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Suggested-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_reset.c | 8 ++++----
 drivers/gpu/drm/i915/gt/intel_reset.h | 5 +++--
 drivers/gpu/drm/i915/i915_gem_gtt.c   | 2 +-
 3 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index a6ecfdc735c4..ca5c6dd28203 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -1166,10 +1166,10 @@ static void gen8_clear_engine_error_register(struct intel_engine_cs *engine)
 	GEN6_RING_FAULT_REG_POSTING_READ(engine);
 }
 
-void i915_clear_error_registers(struct drm_i915_private *i915,
-				intel_engine_mask_t engine_mask)
+void uncore_clear_error_registers(struct intel_uncore *uncore,
+				  intel_engine_mask_t engine_mask)
 {
-	struct intel_uncore *uncore = &i915->uncore;
+	struct drm_i915_private *i915 = uncore_to_i915(uncore);
 	u32 eir;
 
 	if (!IS_GEN(i915, 2))
@@ -1253,7 +1253,7 @@ void i915_handle_error(struct drm_i915_private *i915,
 
 	if (flags & I915_ERROR_CAPTURE) {
 		i915_capture_error_state(i915, engine_mask, msg);
-		i915_clear_error_registers(i915, engine_mask);
+		uncore_clear_error_registers(&i915->uncore, engine_mask);
 	}
 
 	/*
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.h b/drivers/gpu/drm/i915/gt/intel_reset.h
index 4f3c1acac1a3..2c57dc6c26f7 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.h
+++ b/drivers/gpu/drm/i915/gt/intel_reset.h
@@ -12,6 +12,7 @@
 #include <linux/srcu.h>
 
 #include "gt/intel_engine_types.h"
+#include "intel_uncore.h"
 
 struct drm_i915_private;
 struct i915_request;
@@ -25,8 +26,8 @@ void i915_handle_error(struct drm_i915_private *i915,
 		       const char *fmt, ...);
 #define I915_ERROR_CAPTURE BIT(0)
 
-void i915_clear_error_registers(struct drm_i915_private *i915,
-				intel_engine_mask_t engine_mask);
+void uncore_clear_error_registers(struct intel_uncore *uncore,
+				  intel_engine_mask_t engine_mask);
 
 void i915_reset(struct drm_i915_private *i915,
 		intel_engine_mask_t stalled_mask,
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 84104e9cc507..0fe568cfabe0 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2358,7 +2358,7 @@ void i915_check_and_clear_faults(struct drm_i915_private *dev_priv)
 	else
 		return;
 
-	i915_clear_error_registers(dev_priv, ALL_ENGINES);
+	uncore_clear_error_registers(&dev_priv->uncore, ALL_ENGINES);
 }
 
 void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv)
-- 
2.20.1

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[PATCH 06/21] drm/i915: Convert some more bits to use engine mmio accessors

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Remove a couple dev_priv locals as a consequence.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_lrc.c         | 27 ++++++++++-----------
 drivers/gpu/drm/i915/i915_gem_gtt.c         |  5 ++--
 drivers/gpu/drm/i915/i915_gpu_error.c       |  2 +-
 drivers/gpu/drm/i915/i915_reg.h             |  2 +-
 drivers/gpu/drm/i915/intel_guc_submission.c |  4 +--
 5 files changed, 20 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index fed704802c57..f27b6c002627 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2021,31 +2021,30 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
 
 static void enable_execlists(struct intel_engine_cs *engine)
 {
-	struct drm_i915_private *dev_priv = engine->i915;
-
 	intel_engine_set_hwsp_writemask(engine, ~0u); /* HWSTAM */
 
-	if (INTEL_GEN(dev_priv) >= 11)
-		I915_WRITE(RING_MODE_GEN7(engine),
-			   _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE));
+	if (INTEL_GEN(engine->i915) >= 11)
+		ENGINE_WRITE(engine,
+			     RING_MODE_GEN7,
+			     _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE));
 	else
-		I915_WRITE(RING_MODE_GEN7(engine),
-			   _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
+		ENGINE_WRITE(engine,
+			     RING_MODE_GEN7,
+			     _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
 
-	I915_WRITE(RING_MI_MODE(engine->mmio_base),
-		   _MASKED_BIT_DISABLE(STOP_RING));
+	ENGINE_WRITE(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
 
-	I915_WRITE(RING_HWS_PGA(engine->mmio_base),
-		   i915_ggtt_offset(engine->status_page.vma));
-	POSTING_READ(RING_HWS_PGA(engine->mmio_base));
+	ENGINE_WRITE(engine,
+		     RING_HWS_PGA,
+		     i915_ggtt_offset(engine->status_page.vma));
+	ENGINE_POSTING_READ(engine, RING_HWS_PGA);
 }
 
 static bool unexpected_starting_state(struct intel_engine_cs *engine)
 {
-	struct drm_i915_private *dev_priv = engine->i915;
 	bool unexpected = false;
 
-	if (I915_READ(RING_MI_MODE(engine->mmio_base)) & STOP_RING) {
+	if (ENGINE_READ(engine, RING_MI_MODE) & STOP_RING) {
 		DRM_DEBUG_DRIVER("STOP_RING still set in RING_MI_MODE\n");
 		unexpected = true;
 	}
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 0fe568cfabe0..3ba970f2db28 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1713,8 +1713,9 @@ static void gen7_ppgtt_enable(struct drm_i915_private *dev_priv)
 
 	for_each_engine(engine, dev_priv, id) {
 		/* GFX_MODE is per-ring on gen7+ */
-		I915_WRITE(RING_MODE_GEN7(engine),
-			   _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
+		ENGINE_WRITE(engine,
+			     RING_MODE_GEN7,
+			     _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 	}
 }
 
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 2f85de034d8f..193a93857d99 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1219,7 +1219,7 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
 	if (HAS_PPGTT(dev_priv)) {
 		int i;
 
-		ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
+		ee->vm_info.gfx_mode = ENGINE_READ(engine, RING_MODE_GEN7);
 
 		if (IS_GEN(dev_priv, 6)) {
 			ee->vm_info.pp_dir_base =
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1b9ae48d1abe..8a8b34a13d2e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2698,7 +2698,7 @@ enum i915_power_well_id {
 
 #define GFX_MODE	_MMIO(0x2520)
 #define GFX_MODE_GEN7	_MMIO(0x229c)
-#define RING_MODE_GEN7(engine)	_MMIO((engine)->mmio_base + 0x29c)
+#define RING_MODE_GEN7(base)	_MMIO((base) + 0x29c)
 #define   GFX_RUN_LIST_ENABLE		(1 << 15)
 #define   GFX_INTERRUPT_STEERING	(1 << 14)
 #define   GFX_TLB_INVALIDATE_EXPLICIT	(1 << 13)
diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c
index a4f98ccef0fe..89592ef778b8 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -1306,7 +1306,7 @@ static void guc_interrupts_capture(struct drm_i915_private *dev_priv)
 	 */
 	irqs = _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING);
 	for_each_engine(engine, dev_priv, id)
-		I915_WRITE(RING_MODE_GEN7(engine), irqs);
+		ENGINE_WRITE(engine, RING_MODE_GEN7, irqs);
 
 	/* route USER_INTERRUPT to Host, all others are sent to GuC. */
 	irqs = GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
@@ -1353,7 +1353,7 @@ static void guc_interrupts_release(struct drm_i915_private *dev_priv)
 	irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_NEVER);
 	irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING);
 	for_each_engine(engine, dev_priv, id)
-		I915_WRITE(RING_MODE_GEN7(engine), irqs);
+		ENGINE_WRITE(engine, RING_MODE_GEN7, irqs);
 
 	/* route all GT interrupts to the host */
 	I915_WRITE(GUC_BCS_RCS_IER, 0);
-- 
2.20.1

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[PATCH 07/21] drm/i915: Make read_subslice_reg take uncore

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

The function mostly uses uncore so make it use it.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Suggested-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 6b838948ba24..0e9b74f52503 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -973,10 +973,10 @@ u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv)
 }
 
 static inline u32
-read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
-		  int subslice, i915_reg_t reg)
+read_subslice_reg(struct intel_uncore *uncore, int slice, int subslice,
+		  i915_reg_t reg)
 {
-	struct intel_uncore *uncore = &dev_priv->uncore;
+	struct drm_i915_private *i915 = uncore_to_i915(uncore);
 	u32 mcr_slice_subslice_mask;
 	u32 mcr_slice_subslice_select;
 	u32 default_mcr_s_ss_select;
@@ -984,7 +984,7 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
 	u32 ret;
 	enum forcewake_domains fw_domains;
 
-	if (INTEL_GEN(dev_priv) >= 11) {
+	if (INTEL_GEN(i915) >= 11) {
 		mcr_slice_subslice_mask = GEN11_MCR_SLICE_MASK |
 					  GEN11_MCR_SUBSLICE_MASK;
 		mcr_slice_subslice_select = GEN11_MCR_SLICE(slice) |
@@ -996,7 +996,7 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
 					    GEN8_MCR_SUBSLICE(subslice);
 	}
 
-	default_mcr_s_ss_select = intel_calculate_mcr_s_ss_select(dev_priv);
+	default_mcr_s_ss_select = intel_calculate_mcr_s_ss_select(i915);
 
 	fw_domains = intel_uncore_forcewake_for_reg(uncore, reg,
 						    FW_REG_READ);
@@ -1033,7 +1033,7 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
 void intel_engine_get_instdone(struct intel_engine_cs *engine,
 			       struct intel_instdone *instdone)
 {
-	struct drm_i915_private *dev_priv = engine->i915;
+	struct drm_i915_private *i915 = engine->i915;
 	struct intel_uncore *uncore = engine->uncore;
 	u32 mmio_base = engine->mmio_base;
 	int slice;
@@ -1041,7 +1041,7 @@ void intel_engine_get_instdone(struct intel_engine_cs *engine,
 
 	memset(instdone, 0, sizeof(*instdone));
 
-	switch (INTEL_GEN(dev_priv)) {
+	switch (INTEL_GEN(i915)) {
 	default:
 		instdone->instdone =
 			intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
@@ -1051,12 +1051,12 @@ void intel_engine_get_instdone(struct intel_engine_cs *engine,
 
 		instdone->slice_common =
 			intel_uncore_read(uncore, GEN7_SC_INSTDONE);
-		for_each_instdone_slice_subslice(dev_priv, slice, subslice) {
+		for_each_instdone_slice_subslice(i915, slice, subslice) {
 			instdone->sampler[slice][subslice] =
-				read_subslice_reg(dev_priv, slice, subslice,
+				read_subslice_reg(uncore, slice, subslice,
 						  GEN7_SAMPLER_INSTDONE);
 			instdone->row[slice][subslice] =
-				read_subslice_reg(dev_priv, slice, subslice,
+				read_subslice_reg(uncore, slice, subslice,
 						  GEN7_ROW_INSTDONE);
 		}
 		break;
-- 
2.20.1

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[PATCH 08/21] drm/i915: Tidy intel_execlists_submission_init

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Get to uncore from the engine for better logic organization and use
already available i915 everywhere.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Suggested-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index f27b6c002627..497ac036c4a9 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2738,8 +2738,9 @@ int intel_execlists_submission_setup(struct intel_engine_cs *engine)
 
 int intel_execlists_submission_init(struct intel_engine_cs *engine)
 {
-	struct drm_i915_private *i915 = engine->i915;
 	struct intel_engine_execlists * const execlists = &engine->execlists;
+	struct drm_i915_private *i915 = engine->i915;
+	struct intel_uncore *uncore = engine->uncore;
 	u32 base = engine->mmio_base;
 	int ret;
 
@@ -2759,12 +2760,12 @@ int intel_execlists_submission_init(struct intel_engine_cs *engine)
 		DRM_ERROR("WA batch buffer initialization failed\n");
 
 	if (HAS_LOGICAL_RING_ELSQ(i915)) {
-		execlists->submit_reg = i915->uncore.regs +
+		execlists->submit_reg = uncore->regs +
 			i915_mmio_reg_offset(RING_EXECLIST_SQ_CONTENTS(base));
-		execlists->ctrl_reg = i915->uncore.regs +
+		execlists->ctrl_reg = uncore->regs +
 			i915_mmio_reg_offset(RING_EXECLIST_CONTROL(base));
 	} else {
-		execlists->submit_reg = i915->uncore.regs +
+		execlists->submit_reg = uncore->regs +
 			i915_mmio_reg_offset(RING_ELSP(base));
 	}
 
@@ -2779,7 +2780,7 @@ int intel_execlists_submission_init(struct intel_engine_cs *engine)
 	execlists->csb_write =
 		&engine->status_page.addr[intel_hws_csb_write_index(i915)];
 
-	if (INTEL_GEN(engine->i915) < 11)
+	if (INTEL_GEN(i915) < 11)
 		execlists->csb_size = GEN8_CSB_ENTRIES;
 	else
 		execlists->csb_size = GEN11_CSB_ENTRIES;
-- 
2.20.1

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[PATCH 09/21] drm/i915: Make i915_check_and_clear_faults take uncore

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Continuing the conversion and elimination of implicit dev_priv.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Suggested-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c |  2 +-
 drivers/gpu/drm/i915/i915_drv.c           |  2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c       | 34 ++++++++++++-----------
 drivers/gpu/drm/i915/i915_gem_gtt.h       |  2 +-
 4 files changed, 21 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 0e9b74f52503..3554d0dd7b1a 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -453,7 +453,7 @@ int intel_engines_init_mmio(struct drm_i915_private *i915)
 
 	RUNTIME_INFO(i915)->num_engines = hweight32(mask);
 
-	i915_check_and_clear_faults(i915);
+	i915_check_and_clear_faults(&i915->uncore);
 
 	intel_setup_engine_capabilities(i915);
 
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1af6751e1b36..72acd5bc5101 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2340,7 +2340,7 @@ static int i915_drm_resume_early(struct drm_device *dev)
 
 	intel_uncore_resume_early(&dev_priv->uncore);
 
-	i915_check_and_clear_faults(dev_priv);
+	i915_check_and_clear_faults(&dev_priv->uncore);
 
 	if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
 		gen9_sanitize_dc_state(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 3ba970f2db28..0cecc43a64b0 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2299,14 +2299,14 @@ static bool needs_idle_maps(struct drm_i915_private *dev_priv)
 	return IS_GEN(dev_priv, 5) && IS_MOBILE(dev_priv) && intel_vtd_active();
 }
 
-static void gen6_check_faults(struct drm_i915_private *dev_priv)
+static void gen6_check_faults(struct intel_uncore *uncore)
 {
 	struct intel_engine_cs *engine;
 	enum intel_engine_id id;
-	u32 fault;
 
-	for_each_engine(engine, dev_priv, id) {
-		fault = GEN6_RING_FAULT_REG_READ(engine);
+	for_each_engine(engine, uncore_to_i915(uncore), id) {
+		u32 fault = GEN6_RING_FAULT_REG_READ(engine);
+
 		if (fault & RING_FAULT_VALID) {
 			DRM_DEBUG_DRIVER("Unexpected fault\n"
 					 "\tAddr: 0x%08lx\n"
@@ -2321,16 +2321,16 @@ static void gen6_check_faults(struct drm_i915_private *dev_priv)
 	}
 }
 
-static void gen8_check_faults(struct drm_i915_private *dev_priv)
+static void gen8_check_faults(struct intel_uncore *uncore)
 {
-	u32 fault = I915_READ(GEN8_RING_FAULT_REG);
+	u32 fault = intel_uncore_read(uncore, GEN8_RING_FAULT_REG);
 
 	if (fault & RING_FAULT_VALID) {
 		u32 fault_data0, fault_data1;
 		u64 fault_addr;
 
-		fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
-		fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
+		fault_data0 = intel_uncore_read(uncore, GEN8_FAULT_TLB_DATA0);
+		fault_data1 = intel_uncore_read(uncore, GEN8_FAULT_TLB_DATA1);
 		fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
 			     ((u64)fault_data0 << 12);
 
@@ -2349,17 +2349,19 @@ static void gen8_check_faults(struct drm_i915_private *dev_priv)
 	}
 }
 
-void i915_check_and_clear_faults(struct drm_i915_private *dev_priv)
+void i915_check_and_clear_faults(struct intel_uncore *uncore)
 {
+	struct drm_i915_private *i915 = uncore_to_i915(uncore);
+
 	/* From GEN8 onwards we only have one 'All Engine Fault Register' */
-	if (INTEL_GEN(dev_priv) >= 8)
-		gen8_check_faults(dev_priv);
-	else if (INTEL_GEN(dev_priv) >= 6)
-		gen6_check_faults(dev_priv);
+	if (INTEL_GEN(i915) >= 8)
+		gen8_check_faults(uncore);
+	else if (INTEL_GEN(i915) >= 6)
+		gen6_check_faults(uncore);
 	else
 		return;
 
-	uncore_clear_error_registers(&dev_priv->uncore, ALL_ENGINES);
+	uncore_clear_error_registers(uncore, ALL_ENGINES);
 }
 
 void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv)
@@ -2372,7 +2374,7 @@ void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv)
 	if (INTEL_GEN(dev_priv) < 6)
 		return;
 
-	i915_check_and_clear_faults(dev_priv);
+	i915_check_and_clear_faults(&dev_priv->uncore);
 
 	ggtt->vm.clear_range(&ggtt->vm, 0, ggtt->vm.total);
 
@@ -3650,7 +3652,7 @@ void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv)
 	struct i915_ggtt *ggtt = &dev_priv->ggtt;
 	struct i915_vma *vma, *vn;
 
-	i915_check_and_clear_faults(dev_priv);
+	i915_check_and_clear_faults(&dev_priv->uncore);
 
 	mutex_lock(&ggtt->vm.mutex);
 
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 152a03560c22..9ac701988030 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -649,7 +649,7 @@ int gen6_ppgtt_pin(struct i915_hw_ppgtt *base);
 void gen6_ppgtt_unpin(struct i915_hw_ppgtt *base);
 void gen6_ppgtt_unpin_all(struct i915_hw_ppgtt *base);
 
-void i915_check_and_clear_faults(struct drm_i915_private *dev_priv);
+void i915_check_and_clear_faults(struct intel_uncore *uncore);
 void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv);
 void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv);
 
-- 
2.20.1

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[PATCH 10/21] drm/i915: Move scheduler caps init to i915_gem_init

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

This step is more about the GEM and less about the hardware so move it to
the more appropriate place.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_gem.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 4739a6307c32..8eee9ecf0adf 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1311,7 +1311,6 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
 
 	intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
 
-	intel_engines_set_scheduler_caps(dev_priv);
 	return 0;
 
 cleanup_uc:
@@ -1567,6 +1566,8 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
 		goto err_context;
 	}
 
+	intel_engines_set_scheduler_caps(dev_priv);
+
 	intel_init_gt_powersave(dev_priv);
 
 	ret = intel_uc_init(dev_priv);
-- 
2.20.1

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[PATCH 11/21] drm/i915: Remove impossible path from i915_gem_init_swizzling

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Gen8+ does not have swizziling so function will exit on the top most check.

At the same time convert the BUG to MISSING_CASE for a little more debug
info.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_gem.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 8eee9ecf0adf..7512c804d4b7 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1216,10 +1216,8 @@ void i915_gem_init_swizzling(struct drm_i915_private *dev_priv)
 		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
 	else if (IS_GEN(dev_priv, 7))
 		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
-	else if (IS_GEN(dev_priv, 8))
-		I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
 	else
-		BUG();
+		MISSING_CASE(INTEL_GEN(dev_priv));
 }
 
 static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base)
-- 
2.20.1

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[PATCH 12/21] drm/i915: Convert i915_gem_init_swizzling to uncore

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

More removal of implicit dev_priv from using old mmio accessors.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c |  4 ++--
 drivers/gpu/drm/i915/i915_drv.h |  2 +-
 drivers/gpu/drm/i915/i915_gem.c | 37 +++++++++++++++++++++------------
 3 files changed, 27 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 72acd5bc5101..31e97f338d14 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2933,7 +2933,7 @@ static int intel_runtime_suspend(struct device *kdev)
 
 		intel_uc_resume(dev_priv);
 
-		i915_gem_init_swizzling(dev_priv);
+		i915_gem_init_swizzling(&dev_priv->uncore);
 		i915_gem_restore_fences(dev_priv);
 
 		enable_rpm_wakeref_asserts(dev_priv);
@@ -3034,7 +3034,7 @@ static int intel_runtime_resume(struct device *kdev)
 	 * No point of rolling back things in case of an error, as the best
 	 * we can do is to hope that things will still work (and disable RPM).
 	 */
-	i915_gem_init_swizzling(dev_priv);
+	i915_gem_init_swizzling(&dev_priv->uncore);
 	i915_gem_restore_fences(dev_priv);
 
 	/*
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 89bf1e34feaa..4df4f96c975f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2639,7 +2639,7 @@ bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
 void i915_gem_init_mmio(struct drm_i915_private *i915);
 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
-void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
+void i915_gem_init_swizzling(struct intel_uncore *uncore);
 void i915_gem_fini_hw(struct drm_i915_private *dev_priv);
 void i915_gem_fini(struct drm_i915_private *dev_priv);
 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 7512c804d4b7..f5bf1fe208a6 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1199,25 +1199,36 @@ void i915_gem_sanitize(struct drm_i915_private *i915)
 	mutex_unlock(&i915->drm.struct_mutex);
 }
 
-void i915_gem_init_swizzling(struct drm_i915_private *dev_priv)
+void i915_gem_init_swizzling(struct intel_uncore *uncore)
 {
-	if (INTEL_GEN(dev_priv) < 5 ||
-	    dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
+	struct drm_i915_private *i915 = uncore_to_i915(uncore);
+
+	if (INTEL_GEN(i915) < 5 ||
+	    i915->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
 		return;
 
-	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
-				 DISP_TILE_SURFACE_SWIZZLING);
+	intel_uncore_write(uncore,
+			   DISP_ARB_CTL,
+			   intel_uncore_read(uncore, DISP_ARB_CTL) |
+			   DISP_TILE_SURFACE_SWIZZLING);
 
-	if (IS_GEN(dev_priv, 5))
+	if (IS_GEN(i915, 5))
 		return;
 
-	I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
-	if (IS_GEN(dev_priv, 6))
-		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
-	else if (IS_GEN(dev_priv, 7))
-		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
+	intel_uncore_write(uncore,
+			   TILECTL,
+			   intel_uncore_read(uncore, TILECTL) | TILECTL_SWZCTL);
+
+	if (IS_GEN(i915, 6))
+		intel_uncore_write(uncore,
+				   ARB_MODE,
+				   _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
+	else if (IS_GEN(i915, 7))
+		intel_uncore_write(uncore,
+				   ARB_MODE,
+				   _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
 	else
-		MISSING_CASE(INTEL_GEN(dev_priv));
+		MISSING_CASE(INTEL_GEN(i915));
 }
 
 static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base)
@@ -1266,7 +1277,7 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
 	/* ...and determine whether they are sticking. */
 	intel_gt_verify_workarounds(dev_priv, "init");
 
-	i915_gem_init_swizzling(dev_priv);
+	i915_gem_init_swizzling(&dev_priv->uncore);
 
 	/*
 	 * At least 830 can leave some of the unused rings
-- 
2.20.1

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[PATCH 13/21] drm/i915: Convert init_unused_rings to uncore

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

More removal of implicit dev_priv from using old mmio accessors.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_gem.c | 40 +++++++++++++++++----------------
 1 file changed, 21 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index f5bf1fe208a6..4cffa7bea582 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1231,28 +1231,30 @@ void i915_gem_init_swizzling(struct intel_uncore *uncore)
 		MISSING_CASE(INTEL_GEN(i915));
 }
 
-static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base)
+static void init_unused_ring(struct intel_uncore *uncore, u32 base)
 {
-	I915_WRITE(RING_CTL(base), 0);
-	I915_WRITE(RING_HEAD(base), 0);
-	I915_WRITE(RING_TAIL(base), 0);
-	I915_WRITE(RING_START(base), 0);
+	intel_uncore_write(uncore, RING_CTL(base), 0);
+	intel_uncore_write(uncore, RING_HEAD(base), 0);
+	intel_uncore_write(uncore, RING_TAIL(base), 0);
+	intel_uncore_write(uncore, RING_START(base), 0);
 }
 
-static void init_unused_rings(struct drm_i915_private *dev_priv)
+static void init_unused_rings(struct intel_uncore *uncore)
 {
-	if (IS_I830(dev_priv)) {
-		init_unused_ring(dev_priv, PRB1_BASE);
-		init_unused_ring(dev_priv, SRB0_BASE);
-		init_unused_ring(dev_priv, SRB1_BASE);
-		init_unused_ring(dev_priv, SRB2_BASE);
-		init_unused_ring(dev_priv, SRB3_BASE);
-	} else if (IS_GEN(dev_priv, 2)) {
-		init_unused_ring(dev_priv, SRB0_BASE);
-		init_unused_ring(dev_priv, SRB1_BASE);
-	} else if (IS_GEN(dev_priv, 3)) {
-		init_unused_ring(dev_priv, PRB1_BASE);
-		init_unused_ring(dev_priv, PRB2_BASE);
+	struct drm_i915_private *i915 = uncore_to_i915(uncore);
+
+	if (IS_I830(i915)) {
+		init_unused_ring(uncore, PRB1_BASE);
+		init_unused_ring(uncore, SRB0_BASE);
+		init_unused_ring(uncore, SRB1_BASE);
+		init_unused_ring(uncore, SRB2_BASE);
+		init_unused_ring(uncore, SRB3_BASE);
+	} else if (IS_GEN(i915, 2)) {
+		init_unused_ring(uncore, SRB0_BASE);
+		init_unused_ring(uncore, SRB1_BASE);
+	} else if (IS_GEN(i915, 3)) {
+		init_unused_ring(uncore, PRB1_BASE);
+		init_unused_ring(uncore, PRB2_BASE);
 	}
 }
 
@@ -1285,7 +1287,7 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
 	 * will prevent c3 entry. Makes sure all unused rings
 	 * are totally idle.
 	 */
-	init_unused_rings(dev_priv);
+	init_unused_rings(&dev_priv->uncore);
 
 	BUG_ON(!dev_priv->kernel_context);
 	ret = i915_terminally_wedged(dev_priv);
-- 
2.20.1

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[PATCH 14/21] drm/i915: Convert gt workarounds to uncore

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

More conversion of i915_gem_init_hw to uncore.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 +++++-----
 drivers/gpu/drm/i915/gt/intel_workarounds.h |  6 +++---
 drivers/gpu/drm/i915/i915_gem.c             |  4 ++--
 3 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 165b0a45e009..da4b887eadb4 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -984,9 +984,9 @@ wa_list_apply(struct intel_uncore *uncore, const struct i915_wa_list *wal)
 	spin_unlock_irqrestore(&uncore->lock, flags);
 }
 
-void intel_gt_apply_workarounds(struct drm_i915_private *i915)
+void intel_gt_apply_workarounds(struct intel_uncore *uncore)
 {
-	wa_list_apply(&i915->uncore, &i915->gt_wa_list);
+	wa_list_apply(uncore, &uncore_to_i915(uncore)->gt_wa_list);
 }
 
 static bool wa_list_verify(struct intel_uncore *uncore,
@@ -1005,10 +1005,10 @@ static bool wa_list_verify(struct intel_uncore *uncore,
 	return ok;
 }
 
-bool intel_gt_verify_workarounds(struct drm_i915_private *i915,
-				 const char *from)
+bool intel_gt_verify_workarounds(struct intel_uncore *uncore, const char *from)
 {
-	return wa_list_verify(&i915->uncore, &i915->gt_wa_list, from);
+	return wa_list_verify(uncore,
+			      &uncore_to_i915(uncore)->gt_wa_list, from);
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.h b/drivers/gpu/drm/i915/gt/intel_workarounds.h
index 3761a6ee58bb..548e01347e0e 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.h
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.h
@@ -14,6 +14,7 @@
 struct drm_i915_private;
 struct i915_request;
 struct intel_engine_cs;
+struct intel_uncore;
 
 static inline void intel_wa_list_free(struct i915_wa_list *wal)
 {
@@ -25,9 +26,8 @@ void intel_engine_init_ctx_wa(struct intel_engine_cs *engine);
 int intel_engine_emit_ctx_wa(struct i915_request *rq);
 
 void intel_gt_init_workarounds(struct drm_i915_private *i915);
-void intel_gt_apply_workarounds(struct drm_i915_private *i915);
-bool intel_gt_verify_workarounds(struct drm_i915_private *i915,
-				 const char *from);
+void intel_gt_apply_workarounds(struct intel_uncore *uncore);
+bool intel_gt_verify_workarounds(struct intel_uncore *uncore, const char *from);
 
 void intel_engine_init_whitelist(struct intel_engine_cs *engine);
 void intel_engine_apply_whitelist(struct intel_engine_cs *engine);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 4cffa7bea582..3f9de1354da2 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1275,9 +1275,9 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
 			   LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
 
 	/* Apply the GT workarounds... */
-	intel_gt_apply_workarounds(dev_priv);
+	intel_gt_apply_workarounds(&dev_priv->uncore);
 	/* ...and determine whether they are sticking. */
-	intel_gt_verify_workarounds(dev_priv, "init");
+	intel_gt_verify_workarounds(&dev_priv->uncore, "init");
 
 	i915_gem_init_swizzling(&dev_priv->uncore);
 
-- 
2.20.1

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[PATCH 15/21] drm/i915: Convert intel_mocs_init_l3cc_table to uncore

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

More removal of implicit dev_priv from using old mmio accessors.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_mocs.c | 20 ++++++++++++--------
 drivers/gpu/drm/i915/gt/intel_mocs.h |  3 ++-
 drivers/gpu/drm/i915/i915_gem.c      |  2 +-
 3 files changed, 15 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 79df66022d3a..ead8a39a44ce 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -494,13 +494,13 @@ static int emit_mocs_l3cc_table(struct i915_request *rq,
  *
  * Return: Nothing.
  */
-void intel_mocs_init_l3cc_table(struct drm_i915_private *dev_priv)
+void intel_mocs_init_l3cc_table(struct intel_uncore *uncore)
 {
 	struct drm_i915_mocs_table table;
 	unsigned int i;
 	u16 unused_value;
 
-	if (!get_mocs_settings(dev_priv, &table))
+	if (!get_mocs_settings(uncore_to_i915(uncore), &table))
 		return;
 
 	/* Set unused values to PTE */
@@ -510,23 +510,27 @@ void intel_mocs_init_l3cc_table(struct drm_i915_private *dev_priv)
 		u16 low = get_entry_l3cc(&table, 2 * i);
 		u16 high = get_entry_l3cc(&table, 2 * i + 1);
 
-		I915_WRITE(GEN9_LNCFCMOCS(i),
-			   l3cc_combine(&table, low, high));
+		intel_uncore_write(uncore,
+				   GEN9_LNCFCMOCS(i),
+				   l3cc_combine(&table, low, high));
 	}
 
 	/* Odd table size - 1 left over */
 	if (table.size & 0x01) {
 		u16 low = get_entry_l3cc(&table, 2 * i);
 
-		I915_WRITE(GEN9_LNCFCMOCS(i),
-			   l3cc_combine(&table, low, unused_value));
+		intel_uncore_write(uncore,
+				   GEN9_LNCFCMOCS(i),
+				   l3cc_combine(&table, low, unused_value));
 		i++;
 	}
 
 	/* All remaining entries are also unused */
 	for (; i < table.n_entries / 2; i++)
-		I915_WRITE(GEN9_LNCFCMOCS(i),
-			   l3cc_combine(&table, unused_value, unused_value));
+		intel_uncore_write(uncore,
+				   GEN9_LNCFCMOCS(i),
+				   l3cc_combine(&table, unused_value,
+						unused_value));
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.h b/drivers/gpu/drm/i915/gt/intel_mocs.h
index 0913704a1af2..048066c29b7a 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.h
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.h
@@ -52,9 +52,10 @@
 struct drm_i915_private;
 struct i915_request;
 struct intel_engine_cs;
+struct intel_uncore;
 
 int intel_rcs_context_init_mocs(struct i915_request *rq);
-void intel_mocs_init_l3cc_table(struct drm_i915_private *dev_priv);
+void intel_mocs_init_l3cc_table(struct intel_uncore *uncore);
 void intel_mocs_init_engine(struct intel_engine_cs *engine);
 
 #endif
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 3f9de1354da2..d03481b8c1b4 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1313,7 +1313,7 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
 		goto out;
 	}
 
-	intel_mocs_init_l3cc_table(dev_priv);
+	intel_mocs_init_l3cc_table(&dev_priv->uncore);
 
 	/* Only when the HW is re-initialised, can we replay the requests */
 	ret = intel_engines_resume(dev_priv);
-- 
2.20.1

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[PATCH 16/21] drm/i915: Convert i915_ppgtt_init_hw to uncore

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

More removal of implicit dev_priv from using old mmio accessors.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_gem.c     |  2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c | 98 ++++++++++++++++++-----------
 drivers/gpu/drm/i915/i915_gem_gtt.h |  2 +-
 3 files changed, 63 insertions(+), 39 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index d03481b8c1b4..1c5e6c1a5360 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1294,7 +1294,7 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
 	if (ret)
 		goto out;
 
-	ret = i915_ppgtt_init_hw(dev_priv);
+	ret = i915_ppgtt_init_hw(&dev_priv->uncore);
 	if (ret) {
 		DRM_ERROR("Enabling PPGTT failed (%d)\n", ret);
 		goto out;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 0cecc43a64b0..b2c2dc99bf8a 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1693,25 +1693,28 @@ static inline void gen6_write_pde(const struct gen6_hw_ppgtt *ppgtt,
 		  ppgtt->pd_addr + pde);
 }
 
-static void gen7_ppgtt_enable(struct drm_i915_private *dev_priv)
+static void gen7_ppgtt_enable(struct intel_uncore *uncore)
 {
+	struct drm_i915_private *i915 = uncore_to_i915(uncore);
 	struct intel_engine_cs *engine;
 	u32 ecochk, ecobits;
 	enum intel_engine_id id;
 
-	ecobits = I915_READ(GAC_ECO_BITS);
-	I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
+	ecobits = intel_uncore_read(uncore, GAC_ECO_BITS);
+	intel_uncore_write(uncore,
+			   GAC_ECO_BITS,
+			   ecobits | ECOBITS_PPGTT_CACHE64B);
 
-	ecochk = I915_READ(GAM_ECOCHK);
-	if (IS_HASWELL(dev_priv)) {
+	ecochk = intel_uncore_read(uncore, GAM_ECOCHK);
+	if (IS_HASWELL(i915)) {
 		ecochk |= ECOCHK_PPGTT_WB_HSW;
 	} else {
 		ecochk |= ECOCHK_PPGTT_LLC_IVB;
 		ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
 	}
-	I915_WRITE(GAM_ECOCHK, ecochk);
+	intel_uncore_write(uncore, GAM_ECOCHK, ecochk);
 
-	for_each_engine(engine, dev_priv, id) {
+	for_each_engine(engine, i915, id) {
 		/* GFX_MODE is per-ring on gen7+ */
 		ENGINE_WRITE(engine,
 			     RING_MODE_GEN7,
@@ -1719,22 +1722,29 @@ static void gen7_ppgtt_enable(struct drm_i915_private *dev_priv)
 	}
 }
 
-static void gen6_ppgtt_enable(struct drm_i915_private *dev_priv)
+static void gen6_ppgtt_enable(struct intel_uncore *uncore)
 {
 	u32 ecochk, gab_ctl, ecobits;
 
-	ecobits = I915_READ(GAC_ECO_BITS);
-	I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
-		   ECOBITS_PPGTT_CACHE64B);
+	ecobits = intel_uncore_read(uncore, GAC_ECO_BITS);
+	intel_uncore_write(uncore,
+			   GAC_ECO_BITS,
+			   ecobits | ECOBITS_SNB_BIT | ECOBITS_PPGTT_CACHE64B);
 
-	gab_ctl = I915_READ(GAB_CTL);
-	I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
+	gab_ctl = intel_uncore_read(uncore, GAB_CTL);
+	intel_uncore_write(uncore,
+			   GAB_CTL,
+			   gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
 
-	ecochk = I915_READ(GAM_ECOCHK);
-	I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
+	ecochk = intel_uncore_read(uncore, GAM_ECOCHK);
+	intel_uncore_write(uncore,
+			   GAM_ECOCHK,
+			   ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
 
-	if (HAS_PPGTT(dev_priv)) /* may be disabled for VT-d */
-		I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
+	if (HAS_PPGTT(uncore_to_i915(uncore))) /* may be disabled for VT-d */
+		intel_uncore_write(uncore,
+				   GFX_MODE,
+				   _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 }
 
 /* PPGTT support for Sandybdrige/Gen6 and later */
@@ -2185,21 +2195,31 @@ static struct i915_hw_ppgtt *gen6_ppgtt_create(struct drm_i915_private *i915)
 	return ERR_PTR(err);
 }
 
-static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
+static void gtt_write_workarounds(struct intel_uncore *uncore)
 {
+	struct drm_i915_private *i915 = uncore_to_i915(uncore);
+
 	/* This function is for gtt related workarounds. This function is
 	 * called on driver load and after a GPU reset, so you can place
 	 * workarounds here even if they get overwritten by GPU reset.
 	 */
 	/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */
-	if (IS_BROADWELL(dev_priv))
-		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
-	else if (IS_CHERRYVIEW(dev_priv))
-		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
-	else if (IS_GEN9_LP(dev_priv))
-		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
-	else if (INTEL_GEN(dev_priv) >= 9)
-		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
+	if (IS_BROADWELL(i915))
+		intel_uncore_write(uncore,
+				   GEN8_L3_LRA_1_GPGPU,
+				   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
+	else if (IS_CHERRYVIEW(i915))
+		intel_uncore_write(uncore,
+				   GEN8_L3_LRA_1_GPGPU,
+				   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
+	else if (IS_GEN9_LP(i915))
+		intel_uncore_write(uncore,
+				   GEN8_L3_LRA_1_GPGPU,
+				   GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
+	else if (INTEL_GEN(i915) >= 9)
+		intel_uncore_write(uncore,
+				   GEN8_L3_LRA_1_GPGPU,
+				   GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
 
 	/*
 	 * To support 64K PTEs we need to first enable the use of the
@@ -2212,21 +2232,25 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
 	 * 32K pages, but we don't currently have any support for it in our
 	 * driver.
 	 */
-	if (HAS_PAGE_SIZES(dev_priv, I915_GTT_PAGE_SIZE_64K) &&
-	    INTEL_GEN(dev_priv) <= 10)
-		I915_WRITE(GEN8_GAMW_ECO_DEV_RW_IA,
-			   I915_READ(GEN8_GAMW_ECO_DEV_RW_IA) |
-			   GAMW_ECO_ENABLE_64K_IPS_FIELD);
+	if (HAS_PAGE_SIZES(i915, I915_GTT_PAGE_SIZE_64K) &&
+	    INTEL_GEN(i915) <= 10)
+		intel_uncore_write(uncore,
+				   GEN8_GAMW_ECO_DEV_RW_IA,
+				   intel_uncore_read(uncore,
+						     GEN8_GAMW_ECO_DEV_RW_IA) |
+				   GAMW_ECO_ENABLE_64K_IPS_FIELD);
 }
 
-int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv)
+int i915_ppgtt_init_hw(struct intel_uncore *uncore)
 {
-	gtt_write_workarounds(dev_priv);
+	struct drm_i915_private *i915 = uncore_to_i915(uncore);
+
+	gtt_write_workarounds(uncore);
 
-	if (IS_GEN(dev_priv, 6))
-		gen6_ppgtt_enable(dev_priv);
-	else if (IS_GEN(dev_priv, 7))
-		gen7_ppgtt_enable(dev_priv);
+	if (IS_GEN(i915, 6))
+		gen6_ppgtt_enable(uncore);
+	else if (IS_GEN(i915, 7))
+		gen7_ppgtt_enable(uncore);
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 9ac701988030..80703162c99a 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -628,7 +628,7 @@ void i915_ggtt_disable_guc(struct drm_i915_private *i915);
 int i915_gem_init_ggtt(struct drm_i915_private *dev_priv);
 void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv);
 
-int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv);
+int i915_ppgtt_init_hw(struct intel_uncore *uncore);
 
 struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_i915_private *dev_priv);
 void i915_ppgtt_release(struct kref *kref);
-- 
2.20.1

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[PATCH 17/21] drm/i915: Consolidate some open coded mmio rmw

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Replace some gen6/7 open coded rmw with intel_uncore_rmw.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 42 +++++++++++++----------------
 1 file changed, 18 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index b2c2dc99bf8a..fe9cd4ea9671 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1697,13 +1697,10 @@ static void gen7_ppgtt_enable(struct intel_uncore *uncore)
 {
 	struct drm_i915_private *i915 = uncore_to_i915(uncore);
 	struct intel_engine_cs *engine;
-	u32 ecochk, ecobits;
 	enum intel_engine_id id;
+	u32 ecochk;
 
-	ecobits = intel_uncore_read(uncore, GAC_ECO_BITS);
-	intel_uncore_write(uncore,
-			   GAC_ECO_BITS,
-			   ecobits | ECOBITS_PPGTT_CACHE64B);
+	intel_uncore_rmw(uncore, GAC_ECO_BITS, 0, ECOBITS_PPGTT_CACHE64B);
 
 	ecochk = intel_uncore_read(uncore, GAM_ECOCHK);
 	if (IS_HASWELL(i915)) {
@@ -1724,22 +1721,20 @@ static void gen7_ppgtt_enable(struct intel_uncore *uncore)
 
 static void gen6_ppgtt_enable(struct intel_uncore *uncore)
 {
-	u32 ecochk, gab_ctl, ecobits;
+	intel_uncore_rmw(uncore,
+			 GAC_ECO_BITS,
+			 0,
+			 ECOBITS_SNB_BIT | ECOBITS_PPGTT_CACHE64B);
 
-	ecobits = intel_uncore_read(uncore, GAC_ECO_BITS);
-	intel_uncore_write(uncore,
-			   GAC_ECO_BITS,
-			   ecobits | ECOBITS_SNB_BIT | ECOBITS_PPGTT_CACHE64B);
+	intel_uncore_rmw(uncore,
+			 GAB_CTL,
+			 0,
+			 GAB_CTL_CONT_AFTER_PAGEFAULT);
 
-	gab_ctl = intel_uncore_read(uncore, GAB_CTL);
-	intel_uncore_write(uncore,
-			   GAB_CTL,
-			   gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
-
-	ecochk = intel_uncore_read(uncore, GAM_ECOCHK);
-	intel_uncore_write(uncore,
-			   GAM_ECOCHK,
-			   ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
+	intel_uncore_rmw(uncore,
+			 GAM_ECOCHK,
+			 0,
+			 ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
 
 	if (HAS_PPGTT(uncore_to_i915(uncore))) /* may be disabled for VT-d */
 		intel_uncore_write(uncore,
@@ -2234,11 +2229,10 @@ static void gtt_write_workarounds(struct intel_uncore *uncore)
 	 */
 	if (HAS_PAGE_SIZES(i915, I915_GTT_PAGE_SIZE_64K) &&
 	    INTEL_GEN(i915) <= 10)
-		intel_uncore_write(uncore,
-				   GEN8_GAMW_ECO_DEV_RW_IA,
-				   intel_uncore_read(uncore,
-						     GEN8_GAMW_ECO_DEV_RW_IA) |
-				   GAMW_ECO_ENABLE_64K_IPS_FIELD);
+		intel_uncore_rmw(uncore,
+				 GEN8_GAMW_ECO_DEV_RW_IA,
+				 0,
+				 GAMW_ECO_ENABLE_64K_IPS_FIELD);
 }
 
 int i915_ppgtt_init_hw(struct intel_uncore *uncore)
-- 
2.20.1

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[PATCH 18/21] drm/i915: Convert i915_gem_init_hw to uncore

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

More removal of implicit dev_priv from using old mmio accessors.

Actually the top level function remains but is split into a part which
writes to i915 and part which operates on uncore to initialize the
hardware.

GuC and engines are the only odd ones out remaining.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_gem.c | 62 +++++++++++++++++++--------------
 1 file changed, 36 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 1c5e6c1a5360..d2b185aa4338 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1258,28 +1258,29 @@ static void init_unused_rings(struct intel_uncore *uncore)
 	}
 }
 
-int i915_gem_init_hw(struct drm_i915_private *dev_priv)
+static int init_hw(struct intel_uncore *uncore)
 {
+	struct drm_i915_private *i915 = uncore_to_i915(uncore);
 	int ret;
 
-	dev_priv->gt.last_init_time = ktime_get();
-
 	/* Double layer security blanket, see i915_gem_init() */
-	intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
+	intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
 
-	if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9)
-		I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
+	if (HAS_EDRAM(i915) && INTEL_GEN(i915) < 9)
+		intel_uncore_rmw(uncore, HSW_IDICR, 0, IDIHASHMSK(0xf));
 
-	if (IS_HASWELL(dev_priv))
-		I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
-			   LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
+	if (IS_HASWELL(i915))
+		intel_uncore_write(uncore,
+				   MI_PREDICATE_RESULT_2,
+				   IS_HSW_GT3(i915) ?
+				   LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
 
 	/* Apply the GT workarounds... */
-	intel_gt_apply_workarounds(&dev_priv->uncore);
+	intel_gt_apply_workarounds(uncore);
 	/* ...and determine whether they are sticking. */
-	intel_gt_verify_workarounds(&dev_priv->uncore, "init");
+	intel_gt_verify_workarounds(uncore, "init");
 
-	i915_gem_init_swizzling(&dev_priv->uncore);
+	i915_gem_init_swizzling(uncore);
 
 	/*
 	 * At least 830 can leave some of the unused rings
@@ -1287,51 +1288,60 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
 	 * will prevent c3 entry. Makes sure all unused rings
 	 * are totally idle.
 	 */
-	init_unused_rings(&dev_priv->uncore);
-
-	BUG_ON(!dev_priv->kernel_context);
-	ret = i915_terminally_wedged(dev_priv);
-	if (ret)
-		goto out;
+	init_unused_rings(uncore);
 
-	ret = i915_ppgtt_init_hw(&dev_priv->uncore);
+	ret = i915_ppgtt_init_hw(uncore);
 	if (ret) {
 		DRM_ERROR("Enabling PPGTT failed (%d)\n", ret);
 		goto out;
 	}
 
-	ret = intel_wopcm_init_hw(&dev_priv->wopcm);
+	ret = intel_wopcm_init_hw(&i915->wopcm);
 	if (ret) {
 		DRM_ERROR("Enabling WOPCM failed (%d)\n", ret);
 		goto out;
 	}
 
 	/* We can't enable contexts until all firmware is loaded */
-	ret = intel_uc_init_hw(dev_priv);
+	ret = intel_uc_init_hw(i915);
 	if (ret) {
 		DRM_ERROR("Enabling uc failed (%d)\n", ret);
 		goto out;
 	}
 
-	intel_mocs_init_l3cc_table(&dev_priv->uncore);
+	intel_mocs_init_l3cc_table(uncore);
 
 	/* Only when the HW is re-initialised, can we replay the requests */
-	ret = intel_engines_resume(dev_priv);
+	ret = intel_engines_resume(i915);
 	if (ret)
 		goto cleanup_uc;
 
-	intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
+	intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
 
 	return 0;
 
 cleanup_uc:
-	intel_uc_fini_hw(dev_priv);
+	intel_uc_fini_hw(i915);
 out:
-	intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
+	intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
 
 	return ret;
 }
 
+int i915_gem_init_hw(struct drm_i915_private *i915)
+{
+	int ret;
+
+	i915->gt.last_init_time = ktime_get();
+
+	BUG_ON(!i915->kernel_context);
+	ret = i915_terminally_wedged(i915);
+	if (ret)
+		return ret;
+
+	return init_hw(&i915->uncore);
+}
+
 static int __intel_engines_record_defaults(struct drm_i915_private *i915)
 {
 	struct intel_engine_cs *engine;
-- 
2.20.1

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[PATCH 19/21] drm/i915: Convert intel_vgt_(de)balloon to uncore

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

More removal of implicit dev_priv from using old mmio accessors.

Furthermore these calls really operate on ggtt so it logically makes sense
if they take it as parameter.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c |  4 ++--
 drivers/gpu/drm/i915/i915_vgpu.c    | 24 ++++++++++++++----------
 drivers/gpu/drm/i915/i915_vgpu.h    |  4 ++--
 3 files changed, 18 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index fe9cd4ea9671..d3b3676d10f3 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2914,7 +2914,7 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
 	ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,
 			       intel_guc_reserved_gtt_size(&dev_priv->guc));
 
-	ret = intel_vgt_balloon(dev_priv);
+	ret = intel_vgt_balloon(ggtt);
 	if (ret)
 		return ret;
 
@@ -2982,7 +2982,7 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv)
 	intel_guc_release_ggtt_top(&dev_priv->guc);
 
 	if (drm_mm_initialized(&ggtt->vm.mm)) {
-		intel_vgt_deballoon(dev_priv);
+		intel_vgt_deballoon(ggtt);
 		i915_address_space_fini(&ggtt->vm);
 	}
 
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 94d3992b599d..41ed9a3f52b4 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -117,17 +117,17 @@ static void vgt_deballoon_space(struct i915_ggtt *ggtt,
  * This function is called to deallocate the ballooned-out graphic memory, when
  * driver is unloaded or when ballooning fails.
  */
-void intel_vgt_deballoon(struct drm_i915_private *dev_priv)
+void intel_vgt_deballoon(struct i915_ggtt *ggtt)
 {
 	int i;
 
-	if (!intel_vgpu_active(dev_priv))
+	if (!intel_vgpu_active(ggtt->vm.i915))
 		return;
 
 	DRM_DEBUG("VGT deballoon.\n");
 
 	for (i = 0; i < 4; i++)
-		vgt_deballoon_space(&dev_priv->ggtt, &bl_info.space[i]);
+		vgt_deballoon_space(ggtt, &bl_info.space[i]);
 }
 
 static int vgt_balloon_space(struct i915_ggtt *ggtt,
@@ -195,22 +195,26 @@ static int vgt_balloon_space(struct i915_ggtt *ggtt,
  * Returns:
  * zero on success, non-zero if configuration invalid or ballooning failed
  */
-int intel_vgt_balloon(struct drm_i915_private *dev_priv)
+int intel_vgt_balloon(struct i915_ggtt *ggtt)
 {
-	struct i915_ggtt *ggtt = &dev_priv->ggtt;
+	struct intel_uncore *uncore = &ggtt->vm.i915->uncore;
 	unsigned long ggtt_end = ggtt->vm.total;
 
 	unsigned long mappable_base, mappable_size, mappable_end;
 	unsigned long unmappable_base, unmappable_size, unmappable_end;
 	int ret;
 
-	if (!intel_vgpu_active(dev_priv))
+	if (!intel_vgpu_active(ggtt->vm.i915))
 		return 0;
 
-	mappable_base = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.base));
-	mappable_size = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.size));
-	unmappable_base = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.base));
-	unmappable_size = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.size));
+	mappable_base =
+	  intel_uncore_read(uncore, vgtif_reg(avail_rs.mappable_gmadr.base));
+	mappable_size =
+	  intel_uncore_read(uncore, vgtif_reg(avail_rs.mappable_gmadr.size));
+	unmappable_base =
+	  intel_uncore_read(uncore, vgtif_reg(avail_rs.nonmappable_gmadr.base));
+	unmappable_size =
+	  intel_uncore_read(uncore, vgtif_reg(avail_rs.nonmappable_gmadr.size));
 
 	mappable_end = mappable_base + mappable_size;
 	unmappable_end = unmappable_base + unmappable_size;
diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
index ebe1b7bced98..e918f418503f 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.h
+++ b/drivers/gpu/drm/i915/i915_vgpu.h
@@ -42,7 +42,7 @@ intel_vgpu_has_huge_gtt(struct drm_i915_private *dev_priv)
 	return dev_priv->vgpu.caps & VGT_CAPS_HUGE_GTT;
 }
 
-int intel_vgt_balloon(struct drm_i915_private *dev_priv);
-void intel_vgt_deballoon(struct drm_i915_private *dev_priv);
+int intel_vgt_balloon(struct i915_ggtt *ggtt);
+void intel_vgt_deballoon(struct i915_ggtt *ggtt);
 
 #endif /* _I915_VGPU_H_ */
-- 
2.20.1

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[PATCH 20/21] drm/i915: Make GuC GGTT reservation work on ggtt

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

These functions operate on ggtt so make them take that directly as
parameter.

At the same time move the USES_GUC conditional down to
intel_guc_reserve_ggtt_top for symmetry with
intel_guc_reserved_gtt_size.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 14 ++++++--------
 drivers/gpu/drm/i915/intel_guc.c    | 18 ++++++++----------
 drivers/gpu/drm/i915/intel_guc.h    |  6 +++---
 3 files changed, 17 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index d3b3676d10f3..d967a4e9ceb0 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2912,7 +2912,7 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
 	 * why.
 	 */
 	ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,
-			       intel_guc_reserved_gtt_size(&dev_priv->guc));
+			       intel_guc_reserved_gtt_size(ggtt));
 
 	ret = intel_vgt_balloon(ggtt);
 	if (ret)
@@ -2926,11 +2926,9 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
 	if (ret)
 		return ret;
 
-	if (USES_GUC(dev_priv)) {
-		ret = intel_guc_reserve_ggtt_top(&dev_priv->guc);
-		if (ret)
-			goto err_reserve;
-	}
+	ret = intel_guc_reserve_ggtt_top(ggtt);
+	if (ret)
+		goto err_reserve;
 
 	/* Clear any non-preallocated blocks */
 	drm_mm_for_each_hole(entry, &ggtt->vm.mm, hole_start, hole_end) {
@@ -2952,7 +2950,7 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
 	return 0;
 
 err_appgtt:
-	intel_guc_release_ggtt_top(&dev_priv->guc);
+	intel_guc_release_ggtt_top(ggtt);
 err_reserve:
 	drm_mm_remove_node(&ggtt->error_capture);
 	return ret;
@@ -2979,7 +2977,7 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv)
 	if (drm_mm_node_allocated(&ggtt->error_capture))
 		drm_mm_remove_node(&ggtt->error_capture);
 
-	intel_guc_release_ggtt_top(&dev_priv->guc);
+	intel_guc_release_ggtt_top(ggtt);
 
 	if (drm_mm_initialized(&ggtt->vm.mm)) {
 		intel_vgt_deballoon(ggtt);
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index b88c349c4fa6..633248b7da25 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -719,7 +719,7 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
 
 /**
  * intel_guc_reserved_gtt_size()
- * @guc:	intel_guc structure
+ * @ggtt:	Pointer to struct i915_ggtt
  *
  * The GuC WOPCM mapping shadows the lower part of the GGTT, so if we are using
  * GuC we can't have any objects pinned in that region. This function returns
@@ -729,18 +729,19 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
  * 0 if GuC is not present or not in use.
  * Otherwise, the GuC WOPCM size.
  */
-u32 intel_guc_reserved_gtt_size(struct intel_guc *guc)
+u32 intel_guc_reserved_gtt_size(struct i915_ggtt *ggtt)
 {
-	return guc_to_i915(guc)->wopcm.guc.size;
+	return ggtt->vm.i915->wopcm.guc.size;
 }
 
-int intel_guc_reserve_ggtt_top(struct intel_guc *guc)
+int intel_guc_reserve_ggtt_top(struct i915_ggtt *ggtt)
 {
-	struct drm_i915_private *i915 = guc_to_i915(guc);
-	struct i915_ggtt *ggtt = &i915->ggtt;
 	u64 size;
 	int ret;
 
+	if (!USES_GUC(ggtt->vm.i915))
+		return 0;
+
 	size = ggtt->vm.total - GUC_GGTT_TOP;
 
 	ret = i915_gem_gtt_reserve(&ggtt->vm, &ggtt->uc_fw, size,
@@ -752,11 +753,8 @@ int intel_guc_reserve_ggtt_top(struct intel_guc *guc)
 	return ret;
 }
 
-void intel_guc_release_ggtt_top(struct intel_guc *guc)
+void intel_guc_release_ggtt_top(struct i915_ggtt *ggtt)
 {
-	struct drm_i915_private *i915 = guc_to_i915(guc);
-	struct i915_ggtt *ggtt = &i915->ggtt;
-
 	if (drm_mm_node_allocated(&ggtt->uc_fw))
 		drm_mm_remove_node(&ggtt->uc_fw);
 }
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index cbfed7a77c8b..55ea14176c5e 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -173,9 +173,9 @@ int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset);
 int intel_guc_suspend(struct intel_guc *guc);
 int intel_guc_resume(struct intel_guc *guc);
 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
-u32 intel_guc_reserved_gtt_size(struct intel_guc *guc);
-int intel_guc_reserve_ggtt_top(struct intel_guc *guc);
-void intel_guc_release_ggtt_top(struct intel_guc *guc);
+u32 intel_guc_reserved_gtt_size(struct i915_ggtt *ggtt);
+int intel_guc_reserve_ggtt_top(struct i915_ggtt *ggtt);
+void intel_guc_release_ggtt_top(struct i915_ggtt *ggtt);
 
 static inline bool intel_guc_is_loaded(struct intel_guc *guc)
 {
-- 
2.20.1

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[PATCH 21/21] drm/i915: Unexport i915_gem_init/fini_aliasing_ppgtt

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

These two are only used from within i915_gem_gtt.c and can trivially be
made static.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++++----
 drivers/gpu/drm/i915/i915_gem_gtt.h | 3 ---
 2 files changed, 4 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index d967a4e9ceb0..bd7a078f4b49 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2834,7 +2834,7 @@ static void i915_gtt_color_adjust(const struct drm_mm_node *node,
 		*end -= I915_GTT_PAGE_SIZE;
 }
 
-int i915_gem_init_aliasing_ppgtt(struct drm_i915_private *i915)
+static int init_aliasing_ppgtt(struct drm_i915_private *i915)
 {
 	struct i915_ggtt *ggtt = &i915->ggtt;
 	struct i915_hw_ppgtt *ppgtt;
@@ -2874,7 +2874,7 @@ int i915_gem_init_aliasing_ppgtt(struct drm_i915_private *i915)
 	return err;
 }
 
-void i915_gem_fini_aliasing_ppgtt(struct drm_i915_private *i915)
+static void fini_aliasing_ppgtt(struct drm_i915_private *i915)
 {
 	struct i915_ggtt *ggtt = &i915->ggtt;
 	struct i915_hw_ppgtt *ppgtt;
@@ -2942,7 +2942,7 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
 	ggtt->vm.clear_range(&ggtt->vm, ggtt->vm.total - PAGE_SIZE, PAGE_SIZE);
 
 	if (INTEL_PPGTT(dev_priv) == INTEL_PPGTT_ALIASING) {
-		ret = i915_gem_init_aliasing_ppgtt(dev_priv);
+		ret = init_aliasing_ppgtt(dev_priv);
 		if (ret)
 			goto err_appgtt;
 	}
@@ -2969,7 +2969,7 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv)
 	ggtt->vm.closed = true;
 
 	mutex_lock(&dev_priv->drm.struct_mutex);
-	i915_gem_fini_aliasing_ppgtt(dev_priv);
+	fini_aliasing_ppgtt(dev_priv);
 
 	list_for_each_entry_safe(vma, vn, &ggtt->vm.bound_list, vm_link)
 		WARN_ON(i915_vma_unbind(vma));
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 80703162c99a..6893ae015dce 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -617,9 +617,6 @@ const struct intel_ppat_entry *
 intel_ppat_get(struct drm_i915_private *i915, u8 value);
 void intel_ppat_put(const struct intel_ppat_entry *entry);
 
-int i915_gem_init_aliasing_ppgtt(struct drm_i915_private *i915);
-void i915_gem_fini_aliasing_ppgtt(struct drm_i915_private *i915);
-
 int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv);
 int i915_ggtt_init_hw(struct drm_i915_private *dev_priv);
 int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv);
-- 
2.20.1

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Re: [PATCH 01/21] drm/i915: Reset only affected engines when handling error capture

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-06 10:36:19)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Pass down the engine mask to i915_clear_error_registers so only affected
> engines can be reset on the Gen6/7 path.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

The only downside is that it makes it look more designed.
-Chris
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Re: [PATCH 02/21] drm/i915: Tidy engine mask types in hangcheck

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-06 10:36:20)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> We can use intel_engine_mask_t to align with the rest of the codebase.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Ok,
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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Re: [PATCH 03/21] drm/i915: Make Gen6/7 RING_FAULT_REG access engine centric

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-06 10:36:21)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Similar to earlier conversions, eliminate the implicit dev_priv by
> introducing some helpers which take the engine parameter (since the
> register itself is per engine).
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Only 2 (borderline 3) uses, marginal, but
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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Re: [PATCH 04/21] drm/i915: Extract engine fault reset to a helper

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-06 10:36:22)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Just tidying the flow a bit.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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Re: [PATCH 01/21] drm/i915: Reset only affected engines when handling error capture

[Tvrtko Ursulin]

On 06/06/2019 10:44, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-06-06 10:36:19)
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Pass down the engine mask to i915_clear_error_registers so only affected
>> engines can be reset on the Gen6/7 path.
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> 
> The only downside is that it makes it look more designed.

What do you mean?

Regards,

Tvrtko
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Re: [PATCH 05/21] drm/i915: Make i915_clear_error_registers take uncore

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-06 10:36:23)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> The function mostly uses uncore so make the argument reflect that.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Suggested-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_reset.c | 8 ++++----
>  drivers/gpu/drm/i915/gt/intel_reset.h | 5 +++--
>  drivers/gpu/drm/i915/i915_gem_gtt.c   | 2 +-
>  3 files changed, 8 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
> index a6ecfdc735c4..ca5c6dd28203 100644
> --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> @@ -1166,10 +1166,10 @@ static void gen8_clear_engine_error_register(struct intel_engine_cs *engine)
>         GEN6_RING_FAULT_REG_POSTING_READ(engine);
>  }
>  
> -void i915_clear_error_registers(struct drm_i915_private *i915,
> -                               intel_engine_mask_t engine_mask)
> +void uncore_clear_error_registers(struct intel_uncore *uncore,
> +                                 intel_engine_mask_t engine_mask)
>  {
> -       struct intel_uncore *uncore = &i915->uncore;
> +       struct drm_i915_private *i915 = uncore_to_i915(uncore);
>         u32 eir;
>  
>         if (!IS_GEN(i915, 2))
> @@ -1253,7 +1253,7 @@ void i915_handle_error(struct drm_i915_private *i915,
>  
>         if (flags & I915_ERROR_CAPTURE) {
>                 i915_capture_error_state(i915, engine_mask, msg);
> -               i915_clear_error_registers(i915, engine_mask);
> +               uncore_clear_error_registers(&i915->uncore, engine_mask);
>         }
>  
>         /*
> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.h b/drivers/gpu/drm/i915/gt/intel_reset.h
> index 4f3c1acac1a3..2c57dc6c26f7 100644
> --- a/drivers/gpu/drm/i915/gt/intel_reset.h
> +++ b/drivers/gpu/drm/i915/gt/intel_reset.h
> @@ -12,6 +12,7 @@
>  #include <linux/srcu.h>
>  
>  #include "gt/intel_engine_types.h"
> +#include "intel_uncore.h"
>  
>  struct drm_i915_private;
>  struct i915_request;
> @@ -25,8 +26,8 @@ void i915_handle_error(struct drm_i915_private *i915,
>                        const char *fmt, ...);
>  #define I915_ERROR_CAPTURE BIT(0)
>  
> -void i915_clear_error_registers(struct drm_i915_private *i915,
> -                               intel_engine_mask_t engine_mask);
> +void uncore_clear_error_registers(struct intel_uncore *uncore,
> +                                 intel_engine_mask_t engine_mask);

intel_uncore_*

>  
>  void i915_reset(struct drm_i915_private *i915,
>                 intel_engine_mask_t stalled_mask,
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 84104e9cc507..0fe568cfabe0 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2358,7 +2358,7 @@ void i915_check_and_clear_faults(struct drm_i915_private *dev_priv)
>         else
>                 return;
>  
> -       i915_clear_error_registers(dev_priv, ALL_ENGINES);
> +       uncore_clear_error_registers(&dev_priv->uncore, ALL_ENGINES);
>  }

And honestly I would prefer just to move i915_check_and_clear_faults if
that seems reasonable.
-Chris
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Re: [PATCH 05/21] drm/i915: Make i915_clear_error_registers take uncore

[Chris Wilson]

Quoting Chris Wilson (2019-06-06 10:50:17)
> Quoting Tvrtko Ursulin (2019-06-06 10:36:23)
> > -void i915_clear_error_registers(struct drm_i915_private *i915,
> > -                               intel_engine_mask_t engine_mask);
> > +void uncore_clear_error_registers(struct intel_uncore *uncore,
> > +                                 intel_engine_mask_t engine_mask);
> 
> intel_uncore_*

It also upsets the loose rule that functions should be exported from the
object_name.c
-Chris
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Re: [PATCH 06/21] drm/i915: Convert some more bits to use engine mmio accessors

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-06 10:36:24)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Remove a couple dev_priv locals as a consequence.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_lrc.c         | 27 ++++++++++-----------
>  drivers/gpu/drm/i915/i915_gem_gtt.c         |  5 ++--
>  drivers/gpu/drm/i915/i915_gpu_error.c       |  2 +-
>  drivers/gpu/drm/i915/i915_reg.h             |  2 +-
>  drivers/gpu/drm/i915/intel_guc_submission.c |  4 +--
>  5 files changed, 20 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index fed704802c57..f27b6c002627 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -2021,31 +2021,30 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
>  
>  static void enable_execlists(struct intel_engine_cs *engine)
>  {
> -       struct drm_i915_private *dev_priv = engine->i915;
> -
>         intel_engine_set_hwsp_writemask(engine, ~0u); /* HWSTAM */
>  
> -       if (INTEL_GEN(dev_priv) >= 11)
> -               I915_WRITE(RING_MODE_GEN7(engine),
> -                          _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE));
> +       if (INTEL_GEN(engine->i915) >= 11)
> +               ENGINE_WRITE(engine,
> +                            RING_MODE_GEN7,
> +                            _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE));
>         else
> -               I915_WRITE(RING_MODE_GEN7(engine),
> -                          _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
> +               ENGINE_WRITE(engine,
> +                            RING_MODE_GEN7,
> +                            _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
>  
> -       I915_WRITE(RING_MI_MODE(engine->mmio_base),
> -                  _MASKED_BIT_DISABLE(STOP_RING));
> +       ENGINE_WRITE(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
>  
> -       I915_WRITE(RING_HWS_PGA(engine->mmio_base),
> -                  i915_ggtt_offset(engine->status_page.vma));
> -       POSTING_READ(RING_HWS_PGA(engine->mmio_base));
> +       ENGINE_WRITE(engine,
> +                    RING_HWS_PGA,
> +                    i915_ggtt_offset(engine->status_page.vma));
> +       ENGINE_POSTING_READ(engine, RING_HWS_PGA);
>  }
>  
>  static bool unexpected_starting_state(struct intel_engine_cs *engine)
>  {
> -       struct drm_i915_private *dev_priv = engine->i915;
>         bool unexpected = false;
>  
> -       if (I915_READ(RING_MI_MODE(engine->mmio_base)) & STOP_RING) {
> +       if (ENGINE_READ(engine, RING_MI_MODE) & STOP_RING) {
>                 DRM_DEBUG_DRIVER("STOP_RING still set in RING_MI_MODE\n");
>                 unexpected = true;
>         }
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 0fe568cfabe0..3ba970f2db28 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -1713,8 +1713,9 @@ static void gen7_ppgtt_enable(struct drm_i915_private *dev_priv)
>  
>         for_each_engine(engine, dev_priv, id) {
>                 /* GFX_MODE is per-ring on gen7+ */
> -               I915_WRITE(RING_MODE_GEN7(engine),
> -                          _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
> +               ENGINE_WRITE(engine,
> +                            RING_MODE_GEN7,
> +                            _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
>         }
>  }
>  
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 2f85de034d8f..193a93857d99 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -1219,7 +1219,7 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
>         if (HAS_PPGTT(dev_priv)) {
>                 int i;
>  
> -               ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
> +               ee->vm_info.gfx_mode = ENGINE_READ(engine, RING_MODE_GEN7);
>  
>                 if (IS_GEN(dev_priv, 6)) {
>                         ee->vm_info.pp_dir_base =
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1b9ae48d1abe..8a8b34a13d2e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2698,7 +2698,7 @@ enum i915_power_well_id {
>  
>  #define GFX_MODE       _MMIO(0x2520)
>  #define GFX_MODE_GEN7  _MMIO(0x229c)
> -#define RING_MODE_GEN7(engine) _MMIO((engine)->mmio_base + 0x29c)
> +#define RING_MODE_GEN7(base)   _MMIO((base) + 0x29c)
>  #define   GFX_RUN_LIST_ENABLE          (1 << 15)
>  #define   GFX_INTERRUPT_STEERING       (1 << 14)
>  #define   GFX_TLB_INVALIDATE_EXPLICIT  (1 << 13)
> diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c
> index a4f98ccef0fe..89592ef778b8 100644
> --- a/drivers/gpu/drm/i915/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/intel_guc_submission.c
> @@ -1306,7 +1306,7 @@ static void guc_interrupts_capture(struct drm_i915_private *dev_priv)
>          */
>         irqs = _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING);
>         for_each_engine(engine, dev_priv, id)
> -               I915_WRITE(RING_MODE_GEN7(engine), irqs);
> +               ENGINE_WRITE(engine, RING_MODE_GEN7, irqs);
>  
>         /* route USER_INTERRUPT to Host, all others are sent to GuC. */
>         irqs = GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
> @@ -1353,7 +1353,7 @@ static void guc_interrupts_release(struct drm_i915_private *dev_priv)
>         irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_NEVER);
>         irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING);
>         for_each_engine(engine, dev_priv, id)
> -               I915_WRITE(RING_MODE_GEN7(engine), irqs);
> +               ENGINE_WRITE(engine, RING_MODE_GEN7, irqs);
>  
>         /* route all GT interrupts to the host */
>         I915_WRITE(GUC_BCS_RCS_IER, 0);

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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Re: [PATCH 07/21] drm/i915: Make read_subslice_reg take uncore

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-06 10:36:25)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> The function mostly uses uncore so make it use it.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Suggested-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

I'd probably pass engine and take uncore = engine->uncore.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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Re: [PATCH 08/21] drm/i915: Tidy intel_execlists_submission_init

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-06 10:36:26)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Get to uncore from the engine for better logic organization and use
> already available i915 everywhere.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Suggested-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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Re: [PATCH 09/21] drm/i915: Make i915_check_and_clear_faults take uncore

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-06 10:36:27)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Continuing the conversion and elimination of implicit dev_priv.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Suggested-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_engine_cs.c |  2 +-
>  drivers/gpu/drm/i915/i915_drv.c           |  2 +-
>  drivers/gpu/drm/i915/i915_gem_gtt.c       | 34 ++++++++++++-----------
>  drivers/gpu/drm/i915/i915_gem_gtt.h       |  2 +-
>  4 files changed, 21 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 0e9b74f52503..3554d0dd7b1a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -453,7 +453,7 @@ int intel_engines_init_mmio(struct drm_i915_private *i915)
>  
>         RUNTIME_INFO(i915)->num_engines = hweight32(mask);
>  
> -       i915_check_and_clear_faults(i915);
> +       i915_check_and_clear_faults(&i915->uncore);

I am not sold on that. Especially as it is then unwrapped back to i915.
-Chris
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Re: [PATCH 10/21] drm/i915: Move scheduler caps init to i915_gem_init

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-06 10:36:28)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> This step is more about the GEM and less about the hardware so move it to
> the more appropriate place.

Just happens to be the wrong place. It needs to be reset after we
restart the HW as the capabilities do change following wedging.
-Chris
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Re: [PATCH 11/21] drm/i915: Remove impossible path from i915_gem_init_swizzling

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-06 10:36:29)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Gen8+ does not have swizziling so function will exit on the top most check.
> 
> At the same time convert the BUG to MISSING_CASE for a little more debug
> info.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem.c | 4 +---
>  1 file changed, 1 insertion(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 8eee9ecf0adf..7512c804d4b7 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -1216,10 +1216,8 @@ void i915_gem_init_swizzling(struct drm_i915_private *dev_priv)
>                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
>         else if (IS_GEN(dev_priv, 7))
>                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
> -       else if (IS_GEN(dev_priv, 8))
> -               I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));

But that is the register we would need to set if we choose to reenable
swizzling for whatever mysterious reason.
-Chris
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Re: [PATCH 00/21] Implicit dev_priv removal

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-06-06 10:36:18)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Mostly patches reworking the code and GEM init paths to remove some implicit
> dev_priv dependencies (I915_READ/I915_WRITE), plus some small tweaks to tidy
> GEM init paths to use more logical input parameters (enabled by the conversion
> to uncore mmio accessors).

Passing intel_uncore to non intel_uncore functions during init, I
disagree with as it makes the layering violations worse for no apparent
gain.
-Chris
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✗ Fi.CI.CHECKPATCH: warning for Implicit dev_priv removal

[Patchwork]

== Series Details ==

Series: Implicit dev_priv removal
URL   : https://patchwork.freedesktop.org/series/61705/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
970f22aa796e drm/i915: Reset only affected engines when handling error capture
118c531673db drm/i915: Tidy engine mask types in hangcheck
487a7e723cb2 drm/i915: Make Gen6/7 RING_FAULT_REG access engine centric
-:21: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'engine__' - possible side-effects?
#21: FILE: drivers/gpu/drm/i915/gt/intel_engine.h:71:
+#define GEN6_RING_FAULT_REG_READ(engine__) \
+	intel_uncore_read((engine__)->uncore, RING_FAULT_REG(engine__))

-:24: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'engine__' - possible side-effects?
#24: FILE: drivers/gpu/drm/i915/gt/intel_engine.h:74:
+#define GEN6_RING_FAULT_REG_POSTING_READ(engine__) \
+	intel_uncore_posting_read((engine__)->uncore, RING_FAULT_REG(engine__))

-:27: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'engine__' - possible side-effects?
#27: FILE: drivers/gpu/drm/i915/gt/intel_engine.h:77:
+#define GEN6_RING_FAULT_REG_RMW(engine__, clear__, set__) \
+({ \
+	u32 __val; \
+\
+	__val = intel_uncore_read((engine__)->uncore, \
+				  RING_FAULT_REG(engine__)); \
+	__val &= ~clear__; \
+	__val |= set__; \
+	intel_uncore_write((engine__)->uncore, RING_FAULT_REG(engine__), \
+			   __val); \
+})

-:27: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'clear__' may be better as '(clear__)' to avoid precedence issues
#27: FILE: drivers/gpu/drm/i915/gt/intel_engine.h:77:
+#define GEN6_RING_FAULT_REG_RMW(engine__, clear__, set__) \
+({ \
+	u32 __val; \
+\
+	__val = intel_uncore_read((engine__)->uncore, \
+				  RING_FAULT_REG(engine__)); \
+	__val &= ~clear__; \
+	__val |= set__; \
+	intel_uncore_write((engine__)->uncore, RING_FAULT_REG(engine__), \
+			   __val); \
+})

total: 0 errors, 0 warnings, 4 checks, 52 lines checked
dcdc5de72696 drm/i915: Extract engine fault reset to a helper
b55202be923f drm/i915: Make i915_clear_error_registers take uncore
98b9f03fb517 drm/i915: Convert some more bits to use engine mmio accessors
c2931187c171 drm/i915: Make read_subslice_reg take uncore
757bf4f8daeb drm/i915: Tidy intel_execlists_submission_init
245580be209a drm/i915: Make i915_check_and_clear_faults take uncore
edcc073dabcf drm/i915: Move scheduler caps init to i915_gem_init
182392e93cd0 drm/i915: Remove impossible path from i915_gem_init_swizzling
f6f9bb0e5889 drm/i915: Convert i915_gem_init_swizzling to uncore
9d1ee9205692 drm/i915: Convert init_unused_rings to uncore
83da7c8ed5bc drm/i915: Convert gt workarounds to uncore
b320ea58c2e1 drm/i915: Convert intel_mocs_init_l3cc_table to uncore
f0e98038c584 drm/i915: Convert i915_ppgtt_init_hw to uncore
fd20c02086dd drm/i915: Consolidate some open coded mmio rmw
6e633291b272 drm/i915: Convert i915_gem_init_hw to uncore
-:126: WARNING:AVOID_BUG: Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON()
#126: FILE: drivers/gpu/drm/i915/i915_gem.c:1337:
+	BUG_ON(!i915->kernel_context);

total: 0 errors, 1 warnings, 0 checks, 115 lines checked
e465b03ce165 drm/i915: Convert intel_vgt_(de)balloon to uncore
1cda79f98e38 drm/i915: Make GuC GGTT reservation work on ggtt
d4566f34339d drm/i915: Unexport i915_gem_init/fini_aliasing_ppgtt

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✗ Fi.CI.SPARSE: warning for Implicit dev_priv removal

[Patchwork]

== Series Details ==

Series: Implicit dev_priv removal
URL   : https://patchwork.freedesktop.org/series/61705/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Reset only affected engines when handling error capture
Okay!

Commit: drm/i915: Tidy engine mask types in hangcheck
Okay!

Commit: drm/i915: Make Gen6/7 RING_FAULT_REG access engine centric
Okay!

Commit: drm/i915: Extract engine fault reset to a helper
Okay!

Commit: drm/i915: Make i915_clear_error_registers take uncore
Okay!

Commit: drm/i915: Convert some more bits to use engine mmio accessors
Okay!

Commit: drm/i915: Make read_subslice_reg take uncore
Okay!

Commit: drm/i915: Tidy intel_execlists_submission_init
Okay!

Commit: drm/i915: Make i915_check_and_clear_faults take uncore
Okay!

Commit: drm/i915: Move scheduler caps init to i915_gem_init
Okay!

Commit: drm/i915: Remove impossible path from i915_gem_init_swizzling
Okay!

Commit: drm/i915: Convert i915_gem_init_swizzling to uncore
Okay!

Commit: drm/i915: Convert init_unused_rings to uncore
Okay!

Commit: drm/i915: Convert gt workarounds to uncore
Okay!

Commit: drm/i915: Convert intel_mocs_init_l3cc_table to uncore
Okay!

Commit: drm/i915: Convert i915_ppgtt_init_hw to uncore
Okay!

Commit: drm/i915: Consolidate some open coded mmio rmw
Okay!

Commit: drm/i915: Convert i915_gem_init_hw to uncore
Okay!

Commit: drm/i915: Convert intel_vgt_(de)balloon to uncore
-O:drivers/gpu/drm/i915/i915_gem_gtt.c:2914:26: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_gem_gtt.c:2914:26: warning: expression using sizeof(void)

Commit: drm/i915: Make GuC GGTT reservation work on ggtt
-O:drivers/gpu/drm/i915/i915_gem_gtt.c:2914:26: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_gem_gtt.c:2914:26: warning: expression using sizeof(void)

Commit: drm/i915: Unexport i915_gem_init/fini_aliasing_ppgtt
Okay!

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Re: [PATCH 11/21] drm/i915: Remove impossible path from i915_gem_init_swizzling

[Tvrtko Ursulin]

On 06/06/2019 11:01, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-06-06 10:36:29)
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Gen8+ does not have swizziling so function will exit on the top most check.
>>
>> At the same time convert the BUG to MISSING_CASE for a little more debug
>> info.
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_gem.c | 4 +---
>>   1 file changed, 1 insertion(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
>> index 8eee9ecf0adf..7512c804d4b7 100644
>> --- a/drivers/gpu/drm/i915/i915_gem.c
>> +++ b/drivers/gpu/drm/i915/i915_gem.c
>> @@ -1216,10 +1216,8 @@ void i915_gem_init_swizzling(struct drm_i915_private *dev_priv)
>>                  I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
>>          else if (IS_GEN(dev_priv, 7))
>>                  I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
>> -       else if (IS_GEN(dev_priv, 8))
>> -               I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
> 
> But that is the register we would need to set if we choose to reenable
> swizzling for whatever mysterious reason.

On Gen8 after all this time? I can drop the patch if you think that's a 
possibility.

Regards,

Tvrtko


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Re: [PATCH 05/21] drm/i915: Make i915_clear_error_registers take uncore

[Tvrtko Ursulin]

On 06/06/2019 10:50, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-06-06 10:36:23)
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> The function mostly uses uncore so make the argument reflect that.
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Suggested-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> ---
>>   drivers/gpu/drm/i915/gt/intel_reset.c | 8 ++++----
>>   drivers/gpu/drm/i915/gt/intel_reset.h | 5 +++--
>>   drivers/gpu/drm/i915/i915_gem_gtt.c   | 2 +-
>>   3 files changed, 8 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
>> index a6ecfdc735c4..ca5c6dd28203 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_reset.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
>> @@ -1166,10 +1166,10 @@ static void gen8_clear_engine_error_register(struct intel_engine_cs *engine)
>>          GEN6_RING_FAULT_REG_POSTING_READ(engine);
>>   }
>>   
>> -void i915_clear_error_registers(struct drm_i915_private *i915,
>> -                               intel_engine_mask_t engine_mask)
>> +void uncore_clear_error_registers(struct intel_uncore *uncore,
>> +                                 intel_engine_mask_t engine_mask)
>>   {
>> -       struct intel_uncore *uncore = &i915->uncore;
>> +       struct drm_i915_private *i915 = uncore_to_i915(uncore);
>>          u32 eir;
>>   
>>          if (!IS_GEN(i915, 2))
>> @@ -1253,7 +1253,7 @@ void i915_handle_error(struct drm_i915_private *i915,
>>   
>>          if (flags & I915_ERROR_CAPTURE) {
>>                  i915_capture_error_state(i915, engine_mask, msg);
>> -               i915_clear_error_registers(i915, engine_mask);
>> +               uncore_clear_error_registers(&i915->uncore, engine_mask);
>>          }
>>   
>>          /*
>> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.h b/drivers/gpu/drm/i915/gt/intel_reset.h
>> index 4f3c1acac1a3..2c57dc6c26f7 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_reset.h
>> +++ b/drivers/gpu/drm/i915/gt/intel_reset.h
>> @@ -12,6 +12,7 @@
>>   #include <linux/srcu.h>
>>   
>>   #include "gt/intel_engine_types.h"
>> +#include "intel_uncore.h"
>>   
>>   struct drm_i915_private;
>>   struct i915_request;
>> @@ -25,8 +26,8 @@ void i915_handle_error(struct drm_i915_private *i915,
>>                         const char *fmt, ...);
>>   #define I915_ERROR_CAPTURE BIT(0)
>>   
>> -void i915_clear_error_registers(struct drm_i915_private *i915,
>> -                               intel_engine_mask_t engine_mask);
>> +void uncore_clear_error_registers(struct intel_uncore *uncore,
>> +                                 intel_engine_mask_t engine_mask);
> 
> intel_uncore_*
> 
>>   
>>   void i915_reset(struct drm_i915_private *i915,
>>                  intel_engine_mask_t stalled_mask,
>> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
>> index 84104e9cc507..0fe568cfabe0 100644
>> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
>> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
>> @@ -2358,7 +2358,7 @@ void i915_check_and_clear_faults(struct drm_i915_private *dev_priv)
>>          else
>>                  return;
>>   
>> -       i915_clear_error_registers(dev_priv, ALL_ENGINES);
>> +       uncore_clear_error_registers(&dev_priv->uncore, ALL_ENGINES);
>>   }
> 
> And honestly I would prefer just to move i915_check_and_clear_faults if
> that seems reasonable.

Move to intel_reset.c? AFAICS sounds reasonable.

Regards,

Tvrtko


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Re: [PATCH 09/21] drm/i915: Make i915_check_and_clear_faults take uncore

[Tvrtko Ursulin]

On 06/06/2019 10:57, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-06-06 10:36:27)
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Continuing the conversion and elimination of implicit dev_priv.
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Suggested-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> ---
>>   drivers/gpu/drm/i915/gt/intel_engine_cs.c |  2 +-
>>   drivers/gpu/drm/i915/i915_drv.c           |  2 +-
>>   drivers/gpu/drm/i915/i915_gem_gtt.c       | 34 ++++++++++++-----------
>>   drivers/gpu/drm/i915/i915_gem_gtt.h       |  2 +-
>>   4 files changed, 21 insertions(+), 19 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> index 0e9b74f52503..3554d0dd7b1a 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> @@ -453,7 +453,7 @@ int intel_engines_init_mmio(struct drm_i915_private *i915)
>>   
>>          RUNTIME_INFO(i915)->num_engines = hweight32(mask);
>>   
>> -       i915_check_and_clear_faults(i915);
>> +       i915_check_and_clear_faults(&i915->uncore);
> 
> I am not sold on that. Especially as it is then unwrapped back to i915.

It isn't really, not on the logical level. This is the body:

void i915_check_and_clear_faults(struct intel_uncore *uncore)
{
	struct drm_i915_private *i915 = uncore_to_i915(uncore);

	/* From GEN8 onwards we only have one 'All Engine Fault Register' */
	if (INTEL_GEN(i915) >= 8)
		gen8_check_faults(uncore);
	else if (INTEL_GEN(i915) >= 6)
		gen6_check_faults(uncore);
	else
		return;

	uncore_clear_error_registers(uncore, ALL_ENGINES);
}

So the idea being i915 is used only for "what gen am I checkes",
while the actual functionality operates on uncore.

Regards,

Tvrtko
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Re: [PATCH 00/21] Implicit dev_priv removal

[Tvrtko Ursulin]

On 06/06/2019 11:05, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-06-06 10:36:18)
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Mostly patches reworking the code and GEM init paths to remove some implicit
>> dev_priv dependencies (I915_READ/I915_WRITE), plus some small tweaks to tidy
>> GEM init paths to use more logical input parameters (enabled by the conversion
>> to uncore mmio accessors).
> 
> Passing intel_uncore to non intel_uncore functions during init, I
> disagree with as it makes the layering violations worse for no apparent
> gain.

For gem_init_hw it is questionable I agree.

Idea was that it logically makes sense to pass what is functionally 
used. And for majority this seems to be uncore with i915 being used only 
for "what gen am I" checks.

But I haven't converted the guc related bits, or the intel_engines_init 
also doesn't fit. So yes, it's not super clean so I can drop that bit 
for now.

Regards,

Tvrtko


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Re: [PATCH 20/21] drm/i915: Make GuC GGTT reservation work on ggtt

[Michal Wajdeczko]

On Thu, 06 Jun 2019 11:36:38 +0200, Tvrtko Ursulin  
<tvrtko.ursulin@linux.intel.com> wrote:

> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> These functions operate on ggtt so make them take that directly as
> parameter.

Not quite.

Function intel_guc_reserved_gtt_size() operates on struct intel_guc
and is defined in intel_guc.c for proper layering, so NAK here.

For other two intel_guc_reserve|release_ggtt_top() I would rather:
- rename them to i915_ggtt_reserve|release_guc_top(),
- move to i915_gem_ggtt.c
- make them static

Michal

>
> At the same time move the USES_GUC conditional down to
> intel_guc_reserve_ggtt_top for symmetry with
> intel_guc_reserved_gtt_size.
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 14 ++++++--------
>  drivers/gpu/drm/i915/intel_guc.c    | 18 ++++++++----------
>  drivers/gpu/drm/i915/intel_guc.h    |  6 +++---
>  3 files changed, 17 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c  
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index d3b3676d10f3..d967a4e9ceb0 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2912,7 +2912,7 @@ int i915_gem_init_ggtt(struct drm_i915_private  
> *dev_priv)
>  	 * why.
>  	 */
>  	ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,
> -			       intel_guc_reserved_gtt_size(&dev_priv->guc));
> +			       intel_guc_reserved_gtt_size(ggtt));
> 	ret = intel_vgt_balloon(ggtt);
>  	if (ret)
> @@ -2926,11 +2926,9 @@ int i915_gem_init_ggtt(struct drm_i915_private  
> *dev_priv)
>  	if (ret)
>  		return ret;
> -	if (USES_GUC(dev_priv)) {
> -		ret = intel_guc_reserve_ggtt_top(&dev_priv->guc);
> -		if (ret)
> -			goto err_reserve;
> -	}
> +	ret = intel_guc_reserve_ggtt_top(ggtt);
> +	if (ret)
> +		goto err_reserve;
> 	/* Clear any non-preallocated blocks */
>  	drm_mm_for_each_hole(entry, &ggtt->vm.mm, hole_start, hole_end) {
> @@ -2952,7 +2950,7 @@ int i915_gem_init_ggtt(struct drm_i915_private  
> *dev_priv)
>  	return 0;
> err_appgtt:
> -	intel_guc_release_ggtt_top(&dev_priv->guc);
> +	intel_guc_release_ggtt_top(ggtt);
>  err_reserve:
>  	drm_mm_remove_node(&ggtt->error_capture);
>  	return ret;
> @@ -2979,7 +2977,7 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private  
> *dev_priv)
>  	if (drm_mm_node_allocated(&ggtt->error_capture))
>  		drm_mm_remove_node(&ggtt->error_capture);
> -	intel_guc_release_ggtt_top(&dev_priv->guc);
> +	intel_guc_release_ggtt_top(ggtt);
> 	if (drm_mm_initialized(&ggtt->vm.mm)) {
>  		intel_vgt_deballoon(ggtt);
> diff --git a/drivers/gpu/drm/i915/intel_guc.c  
> b/drivers/gpu/drm/i915/intel_guc.c
> index b88c349c4fa6..633248b7da25 100644
> --- a/drivers/gpu/drm/i915/intel_guc.c
> +++ b/drivers/gpu/drm/i915/intel_guc.c
> @@ -719,7 +719,7 @@ struct i915_vma *intel_guc_allocate_vma(struct  
> intel_guc *guc, u32 size)
> /**
>   * intel_guc_reserved_gtt_size()
> - * @guc:	intel_guc structure
> + * @ggtt:	Pointer to struct i915_ggtt
>   *
>   * The GuC WOPCM mapping shadows the lower part of the GGTT, so if we  
> are using
>   * GuC we can't have any objects pinned in that region. This function  
> returns
> @@ -729,18 +729,19 @@ struct i915_vma *intel_guc_allocate_vma(struct  
> intel_guc *guc, u32 size)
>   * 0 if GuC is not present or not in use.
>   * Otherwise, the GuC WOPCM size.
>   */
> -u32 intel_guc_reserved_gtt_size(struct intel_guc *guc)
> +u32 intel_guc_reserved_gtt_size(struct i915_ggtt *ggtt)
>  {
> -	return guc_to_i915(guc)->wopcm.guc.size;
> +	return ggtt->vm.i915->wopcm.guc.size;
>  }
> -int intel_guc_reserve_ggtt_top(struct intel_guc *guc)
> +int intel_guc_reserve_ggtt_top(struct i915_ggtt *ggtt)
>  {
> -	struct drm_i915_private *i915 = guc_to_i915(guc);
> -	struct i915_ggtt *ggtt = &i915->ggtt;
>  	u64 size;
>  	int ret;
> +	if (!USES_GUC(ggtt->vm.i915))
> +		return 0;
> +
>  	size = ggtt->vm.total - GUC_GGTT_TOP;
> 	ret = i915_gem_gtt_reserve(&ggtt->vm, &ggtt->uc_fw, size,
> @@ -752,11 +753,8 @@ int intel_guc_reserve_ggtt_top(struct intel_guc  
> *guc)
>  	return ret;
>  }
> -void intel_guc_release_ggtt_top(struct intel_guc *guc)
> +void intel_guc_release_ggtt_top(struct i915_ggtt *ggtt)
>  {
> -	struct drm_i915_private *i915 = guc_to_i915(guc);
> -	struct i915_ggtt *ggtt = &i915->ggtt;
> -
>  	if (drm_mm_node_allocated(&ggtt->uc_fw))
>  		drm_mm_remove_node(&ggtt->uc_fw);
>  }
> diff --git a/drivers/gpu/drm/i915/intel_guc.h  
> b/drivers/gpu/drm/i915/intel_guc.h
> index cbfed7a77c8b..55ea14176c5e 100644
> --- a/drivers/gpu/drm/i915/intel_guc.h
> +++ b/drivers/gpu/drm/i915/intel_guc.h
> @@ -173,9 +173,9 @@ int intel_guc_auth_huc(struct intel_guc *guc, u32  
> rsa_offset);
>  int intel_guc_suspend(struct intel_guc *guc);
>  int intel_guc_resume(struct intel_guc *guc);
>  struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32  
> size);
> -u32 intel_guc_reserved_gtt_size(struct intel_guc *guc);
> -int intel_guc_reserve_ggtt_top(struct intel_guc *guc);
> -void intel_guc_release_ggtt_top(struct intel_guc *guc);
> +u32 intel_guc_reserved_gtt_size(struct i915_ggtt *ggtt);
> +int intel_guc_reserve_ggtt_top(struct i915_ggtt *ggtt);
> +void intel_guc_release_ggtt_top(struct i915_ggtt *ggtt);
> static inline bool intel_guc_is_loaded(struct intel_guc *guc)
>  {
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Re: [PATCH 20/21] drm/i915: Make GuC GGTT reservation work on ggtt

[Tvrtko Ursulin]

On 06/06/2019 12:58, Michal Wajdeczko wrote:
> On Thu, 06 Jun 2019 11:36:38 +0200, Tvrtko Ursulin 
> <tvrtko.ursulin@linux.intel.com> wrote:
> 
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> These functions operate on ggtt so make them take that directly as
>> parameter.
> 
> Not quite.
> 
> Function intel_guc_reserved_gtt_size() operates on struct intel_guc
> and is defined in intel_guc.c for proper layering, so NAK here.

But it doesn't really. It operates on intel_wopcm if we want to be true.

u32 intel_guc_reserved_gtt_size(struct i915_ggtt *ggtt)
{
	return ggtt->vm.i915->wopcm.guc.size;
}

And GuC portion it needs is just one part of struct intel_wopcm - so 
whether or not this function must live in intel_guc.c and so how hard we 
should see this as layering violation is not so clear in my opinion.

Unless it will need to actually use intel_guc in the future.

> For other two intel_guc_reserve|release_ggtt_top() I would rather:
> - rename them to i915_ggtt_reserve|release_guc_top(),
> - move to i915_gem_ggtt.c
> - make them static

Fair, will do.

Regards,

Tvrtko

> Michal
> 
>>
>> At the same time move the USES_GUC conditional down to
>> intel_guc_reserve_ggtt_top for symmetry with
>> intel_guc_reserved_gtt_size.
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_gem_gtt.c | 14 ++++++--------
>>  drivers/gpu/drm/i915/intel_guc.c    | 18 ++++++++----------
>>  drivers/gpu/drm/i915/intel_guc.h    |  6 +++---
>>  3 files changed, 17 insertions(+), 21 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
>> b/drivers/gpu/drm/i915/i915_gem_gtt.c
>> index d3b3676d10f3..d967a4e9ceb0 100644
>> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
>> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
>> @@ -2912,7 +2912,7 @@ int i915_gem_init_ggtt(struct drm_i915_private 
>> *dev_priv)
>>       * why.
>>       */
>>      ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,
>> -                   intel_guc_reserved_gtt_size(&dev_priv->guc));
>> +                   intel_guc_reserved_gtt_size(ggtt));
>>     ret = intel_vgt_balloon(ggtt);
>>      if (ret)
>> @@ -2926,11 +2926,9 @@ int i915_gem_init_ggtt(struct drm_i915_private 
>> *dev_priv)
>>      if (ret)
>>          return ret;
>> -    if (USES_GUC(dev_priv)) {
>> -        ret = intel_guc_reserve_ggtt_top(&dev_priv->guc);
>> -        if (ret)
>> -            goto err_reserve;
>> -    }
>> +    ret = intel_guc_reserve_ggtt_top(ggtt);
>> +    if (ret)
>> +        goto err_reserve;
>>     /* Clear any non-preallocated blocks */
>>      drm_mm_for_each_hole(entry, &ggtt->vm.mm, hole_start, hole_end) {
>> @@ -2952,7 +2950,7 @@ int i915_gem_init_ggtt(struct drm_i915_private 
>> *dev_priv)
>>      return 0;
>> err_appgtt:
>> -    intel_guc_release_ggtt_top(&dev_priv->guc);
>> +    intel_guc_release_ggtt_top(ggtt);
>>  err_reserve:
>>      drm_mm_remove_node(&ggtt->error_capture);
>>      return ret;
>> @@ -2979,7 +2977,7 @@ void i915_ggtt_cleanup_hw(struct 
>> drm_i915_private *dev_priv)
>>      if (drm_mm_node_allocated(&ggtt->error_capture))
>>          drm_mm_remove_node(&ggtt->error_capture);
>> -    intel_guc_release_ggtt_top(&dev_priv->guc);
>> +    intel_guc_release_ggtt_top(ggtt);
>>     if (drm_mm_initialized(&ggtt->vm.mm)) {
>>          intel_vgt_deballoon(ggtt);
>> diff --git a/drivers/gpu/drm/i915/intel_guc.c 
>> b/drivers/gpu/drm/i915/intel_guc.c
>> index b88c349c4fa6..633248b7da25 100644
>> --- a/drivers/gpu/drm/i915/intel_guc.c
>> +++ b/drivers/gpu/drm/i915/intel_guc.c
>> @@ -719,7 +719,7 @@ struct i915_vma *intel_guc_allocate_vma(struct 
>> intel_guc *guc, u32 size)
>> /**
>>   * intel_guc_reserved_gtt_size()
>> - * @guc:    intel_guc structure
>> + * @ggtt:    Pointer to struct i915_ggtt
>>   *
>>   * The GuC WOPCM mapping shadows the lower part of the GGTT, so if we 
>> are using
>>   * GuC we can't have any objects pinned in that region. This function 
>> returns
>> @@ -729,18 +729,19 @@ struct i915_vma *intel_guc_allocate_vma(struct 
>> intel_guc *guc, u32 size)
>>   * 0 if GuC is not present or not in use.
>>   * Otherwise, the GuC WOPCM size.
>>   */
>> -u32 intel_guc_reserved_gtt_size(struct intel_guc *guc)
>> +u32 intel_guc_reserved_gtt_size(struct i915_ggtt *ggtt)
>>  {
>> -    return guc_to_i915(guc)->wopcm.guc.size;
>> +    return ggtt->vm.i915->wopcm.guc.size;
>>  }
>> -int intel_guc_reserve_ggtt_top(struct intel_guc *guc)
>> +int intel_guc_reserve_ggtt_top(struct i915_ggtt *ggtt)
>>  {
>> -    struct drm_i915_private *i915 = guc_to_i915(guc);
>> -    struct i915_ggtt *ggtt = &i915->ggtt;
>>      u64 size;
>>      int ret;
>> +    if (!USES_GUC(ggtt->vm.i915))
>> +        return 0;
>> +
>>      size = ggtt->vm.total - GUC_GGTT_TOP;
>>     ret = i915_gem_gtt_reserve(&ggtt->vm, &ggtt->uc_fw, size,
>> @@ -752,11 +753,8 @@ int intel_guc_reserve_ggtt_top(struct intel_guc 
>> *guc)
>>      return ret;
>>  }
>> -void intel_guc_release_ggtt_top(struct intel_guc *guc)
>> +void intel_guc_release_ggtt_top(struct i915_ggtt *ggtt)
>>  {
>> -    struct drm_i915_private *i915 = guc_to_i915(guc);
>> -    struct i915_ggtt *ggtt = &i915->ggtt;
>> -
>>      if (drm_mm_node_allocated(&ggtt->uc_fw))
>>          drm_mm_remove_node(&ggtt->uc_fw);
>>  }
>> diff --git a/drivers/gpu/drm/i915/intel_guc.h 
>> b/drivers/gpu/drm/i915/intel_guc.h
>> index cbfed7a77c8b..55ea14176c5e 100644
>> --- a/drivers/gpu/drm/i915/intel_guc.h
>> +++ b/drivers/gpu/drm/i915/intel_guc.h
>> @@ -173,9 +173,9 @@ int intel_guc_auth_huc(struct intel_guc *guc, u32 
>> rsa_offset);
>>  int intel_guc_suspend(struct intel_guc *guc);
>>  int intel_guc_resume(struct intel_guc *guc);
>>  struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 
>> size);
>> -u32 intel_guc_reserved_gtt_size(struct intel_guc *guc);
>> -int intel_guc_reserve_ggtt_top(struct intel_guc *guc);
>> -void intel_guc_release_ggtt_top(struct intel_guc *guc);
>> +u32 intel_guc_reserved_gtt_size(struct i915_ggtt *ggtt);
>> +int intel_guc_reserve_ggtt_top(struct i915_ggtt *ggtt);
>> +void intel_guc_release_ggtt_top(struct i915_ggtt *ggtt);
>> static inline bool intel_guc_is_loaded(struct intel_guc *guc)
>>  {
> 
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✓ Fi.CI.BAT: success for Implicit dev_priv removal

[Patchwork]

== Series Details ==

Series: Implicit dev_priv removal
URL   : https://patchwork.freedesktop.org/series/61705/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6205 -> Patchwork_13190
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/

Known issues
------------

  Here are the changes found in Patchwork_13190 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_mmap_gtt@basic-read-no-prefault:
    - fi-icl-u3:          [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/fi-icl-u3/igt@gem_mmap_gtt@basic-read-no-prefault.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/fi-icl-u3/igt@gem_mmap_gtt@basic-read-no-prefault.html

  * igt@i915_module_load@reload:
    - fi-blb-e6850:       [PASS][3] -> [INCOMPLETE][4] ([fdo#107718])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/fi-blb-e6850/igt@i915_module_load@reload.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/fi-blb-e6850/igt@i915_module_load@reload.html

  * igt@i915_selftest@live_evict:
    - fi-bsw-kefka:       [PASS][5] -> [DMESG-WARN][6] ([fdo#107709])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/fi-bsw-kefka/igt@i915_selftest@live_evict.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/fi-bsw-kefka/igt@i915_selftest@live_evict.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size:
    - fi-icl-dsi:         [PASS][7] -> [DMESG-WARN][8] ([fdo#106107])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/fi-icl-dsi/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/fi-icl-dsi/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html

  
#### Possible fixes ####

  * igt@i915_selftest@live_hangcheck:
    - fi-icl-dsi:         [INCOMPLETE][9] ([fdo#107713] / [fdo#108569]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
    - fi-icl-u3:          [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12] +1 similar issue
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/fi-icl-u3/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/fi-icl-u3/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html

  * igt@prime_vgem@basic-fence-flip:
    - fi-ilk-650:         [DMESG-WARN][13] ([fdo#106387]) -> [PASS][14] +2 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/fi-ilk-650/igt@prime_vgem@basic-fence-flip.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/fi-ilk-650/igt@prime_vgem@basic-fence-flip.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
  [fdo#106387]: https://bugs.freedesktop.org/show_bug.cgi?id=106387
  [fdo#107709]: https://bugs.freedesktop.org/show_bug.cgi?id=107709
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271


Participating hosts (53 -> 47)
------------------------------

  Missing    (6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7560u fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_6205 -> Patchwork_13190

  CI_DRM_6205: 6021addc939f244fd19e8142aa5ce838e5fa2901 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5043: 3e2b20817b68ab41377c1b86207a1e7309fc3779 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13190: d4566f34339dba02be6572acdf7ef4943cd86d30 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

d4566f34339d drm/i915: Unexport i915_gem_init/fini_aliasing_ppgtt
1cda79f98e38 drm/i915: Make GuC GGTT reservation work on ggtt
e465b03ce165 drm/i915: Convert intel_vgt_(de)balloon to uncore
6e633291b272 drm/i915: Convert i915_gem_init_hw to uncore
fd20c02086dd drm/i915: Consolidate some open coded mmio rmw
f0e98038c584 drm/i915: Convert i915_ppgtt_init_hw to uncore
b320ea58c2e1 drm/i915: Convert intel_mocs_init_l3cc_table to uncore
83da7c8ed5bc drm/i915: Convert gt workarounds to uncore
9d1ee9205692 drm/i915: Convert init_unused_rings to uncore
f6f9bb0e5889 drm/i915: Convert i915_gem_init_swizzling to uncore
182392e93cd0 drm/i915: Remove impossible path from i915_gem_init_swizzling
edcc073dabcf drm/i915: Move scheduler caps init to i915_gem_init
245580be209a drm/i915: Make i915_check_and_clear_faults take uncore
757bf4f8daeb drm/i915: Tidy intel_execlists_submission_init
c2931187c171 drm/i915: Make read_subslice_reg take uncore
98b9f03fb517 drm/i915: Convert some more bits to use engine mmio accessors
b55202be923f drm/i915: Make i915_clear_error_registers take uncore
dcdc5de72696 drm/i915: Extract engine fault reset to a helper
487a7e723cb2 drm/i915: Make Gen6/7 RING_FAULT_REG access engine centric
118c531673db drm/i915: Tidy engine mask types in hangcheck
970f22aa796e drm/i915: Reset only affected engines when handling error capture

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/
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Re: [PATCH 20/21] drm/i915: Make GuC GGTT reservation work on ggtt

[Michal Wajdeczko]

On Thu, 06 Jun 2019 14:23:09 +0200, Tvrtko Ursulin  
<tvrtko.ursulin@linux.intel.com> wrote:

>
> On 06/06/2019 12:58, Michal Wajdeczko wrote:
>> On Thu, 06 Jun 2019 11:36:38 +0200, Tvrtko Ursulin  
>> <tvrtko.ursulin@linux.intel.com> wrote:
>>
>>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>
>>> These functions operate on ggtt so make them take that directly as
>>> parameter.
>>  Not quite.
>>  Function intel_guc_reserved_gtt_size() operates on struct intel_guc
>> and is defined in intel_guc.c for proper layering, so NAK here.
>
> But it doesn't really. It operates on intel_wopcm if we want to be true.

oops, I forgot that finally we placed wopcm directly under i915 (initially
it was declared inside intel_guc)

>
> u32 intel_guc_reserved_gtt_size(struct i915_ggtt *ggtt)
> {
> 	return ggtt->vm.i915->wopcm.guc.size;
> }
>
> And GuC portion it needs is just one part of struct intel_wopcm - so  
> whether or not this function must live in intel_guc.c and so how hard we  
> should see this as layering violation is not so clear in my opinion.

agreed. so we have two options:

move this function to intel_wopcm.h as:

static inline u32 intel_wopcm_guc_size(struct intel_wopcm *wopcm)
{
	GEM_BUG_ON(!wopcm->guc.size);
	return wopcm->guc.size;
}

and update existing callers or update just old one to:

u32 intel_guc_reserved_gtt_size(struct intel_guc *guc)
{
	return intel_wopcm_guc_size(&guc_to_i915(guc)->wopcm);
}

>
> Unless it will need to actually use intel_guc in the future.

There was a plan to create struct intel_uc with wopcm, guc and huc.
Not sure if it is still applicable.

>
>> For other two intel_guc_reserve|release_ggtt_top() I would rather:
>> - rename them to i915_ggtt_reserve|release_guc_top(),
>> - move to i915_gem_ggtt.c
>> - make them static
>
> Fair, will do.
>
> Regards,
>
> Tvrtko
>
>> Michal
>>
>>>
>>> At the same time move the USES_GUC conditional down to
>>> intel_guc_reserve_ggtt_top for symmetry with
>>> intel_guc_reserved_gtt_size.
>>>
>>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>> ---
>>>  drivers/gpu/drm/i915/i915_gem_gtt.c | 14 ++++++--------
>>>  drivers/gpu/drm/i915/intel_guc.c    | 18 ++++++++----------
>>>  drivers/gpu/drm/i915/intel_guc.h    |  6 +++---
>>>  3 files changed, 17 insertions(+), 21 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c  
>>> b/drivers/gpu/drm/i915/i915_gem_gtt.c
>>> index d3b3676d10f3..d967a4e9ceb0 100644
>>> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
>>> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
>>> @@ -2912,7 +2912,7 @@ int i915_gem_init_ggtt(struct drm_i915_private  
>>> *dev_priv)
>>>       * why.
>>>       */
>>>      ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,
>>> -                   intel_guc_reserved_gtt_size(&dev_priv->guc));
>>> +                   intel_guc_reserved_gtt_size(ggtt));
>>>     ret = intel_vgt_balloon(ggtt);
>>>      if (ret)
>>> @@ -2926,11 +2926,9 @@ int i915_gem_init_ggtt(struct drm_i915_private  
>>> *dev_priv)
>>>      if (ret)
>>>          return ret;
>>> -    if (USES_GUC(dev_priv)) {
>>> -        ret = intel_guc_reserve_ggtt_top(&dev_priv->guc);
>>> -        if (ret)
>>> -            goto err_reserve;
>>> -    }
>>> +    ret = intel_guc_reserve_ggtt_top(ggtt);
>>> +    if (ret)
>>> +        goto err_reserve;
>>>     /* Clear any non-preallocated blocks */
>>>      drm_mm_for_each_hole(entry, &ggtt->vm.mm, hole_start, hole_end) {
>>> @@ -2952,7 +2950,7 @@ int i915_gem_init_ggtt(struct drm_i915_private  
>>> *dev_priv)
>>>      return 0;
>>> err_appgtt:
>>> -    intel_guc_release_ggtt_top(&dev_priv->guc);
>>> +    intel_guc_release_ggtt_top(ggtt);
>>>  err_reserve:
>>>      drm_mm_remove_node(&ggtt->error_capture);
>>>      return ret;
>>> @@ -2979,7 +2977,7 @@ void i915_ggtt_cleanup_hw(struct  
>>> drm_i915_private *dev_priv)
>>>      if (drm_mm_node_allocated(&ggtt->error_capture))
>>>          drm_mm_remove_node(&ggtt->error_capture);
>>> -    intel_guc_release_ggtt_top(&dev_priv->guc);
>>> +    intel_guc_release_ggtt_top(ggtt);
>>>     if (drm_mm_initialized(&ggtt->vm.mm)) {
>>>          intel_vgt_deballoon(ggtt);
>>> diff --git a/drivers/gpu/drm/i915/intel_guc.c  
>>> b/drivers/gpu/drm/i915/intel_guc.c
>>> index b88c349c4fa6..633248b7da25 100644
>>> --- a/drivers/gpu/drm/i915/intel_guc.c
>>> +++ b/drivers/gpu/drm/i915/intel_guc.c
>>> @@ -719,7 +719,7 @@ struct i915_vma *intel_guc_allocate_vma(struct  
>>> intel_guc *guc, u32 size)
>>> /**
>>>   * intel_guc_reserved_gtt_size()
>>> - * @guc:    intel_guc structure
>>> + * @ggtt:    Pointer to struct i915_ggtt
>>>   *
>>>   * The GuC WOPCM mapping shadows the lower part of the GGTT, so if we  
>>> are using
>>>   * GuC we can't have any objects pinned in that region. This function  
>>> returns
>>> @@ -729,18 +729,19 @@ struct i915_vma *intel_guc_allocate_vma(struct  
>>> intel_guc *guc, u32 size)
>>>   * 0 if GuC is not present or not in use.
>>>   * Otherwise, the GuC WOPCM size.
>>>   */
>>> -u32 intel_guc_reserved_gtt_size(struct intel_guc *guc)
>>> +u32 intel_guc_reserved_gtt_size(struct i915_ggtt *ggtt)
>>>  {
>>> -    return guc_to_i915(guc)->wopcm.guc.size;
>>> +    return ggtt->vm.i915->wopcm.guc.size;
>>>  }
>>> -int intel_guc_reserve_ggtt_top(struct intel_guc *guc)
>>> +int intel_guc_reserve_ggtt_top(struct i915_ggtt *ggtt)
>>>  {
>>> -    struct drm_i915_private *i915 = guc_to_i915(guc);
>>> -    struct i915_ggtt *ggtt = &i915->ggtt;
>>>      u64 size;
>>>      int ret;
>>> +    if (!USES_GUC(ggtt->vm.i915))
>>> +        return 0;
>>> +
>>>      size = ggtt->vm.total - GUC_GGTT_TOP;
>>>     ret = i915_gem_gtt_reserve(&ggtt->vm, &ggtt->uc_fw, size,
>>> @@ -752,11 +753,8 @@ int intel_guc_reserve_ggtt_top(struct intel_guc  
>>> *guc)
>>>      return ret;
>>>  }
>>> -void intel_guc_release_ggtt_top(struct intel_guc *guc)
>>> +void intel_guc_release_ggtt_top(struct i915_ggtt *ggtt)
>>>  {
>>> -    struct drm_i915_private *i915 = guc_to_i915(guc);
>>> -    struct i915_ggtt *ggtt = &i915->ggtt;
>>> -
>>>      if (drm_mm_node_allocated(&ggtt->uc_fw))
>>>          drm_mm_remove_node(&ggtt->uc_fw);
>>>  }
>>> diff --git a/drivers/gpu/drm/i915/intel_guc.h  
>>> b/drivers/gpu/drm/i915/intel_guc.h
>>> index cbfed7a77c8b..55ea14176c5e 100644
>>> --- a/drivers/gpu/drm/i915/intel_guc.h
>>> +++ b/drivers/gpu/drm/i915/intel_guc.h
>>> @@ -173,9 +173,9 @@ int intel_guc_auth_huc(struct intel_guc *guc, u32  
>>> rsa_offset);
>>>  int intel_guc_suspend(struct intel_guc *guc);
>>>  int intel_guc_resume(struct intel_guc *guc);
>>>  struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32  
>>> size);
>>> -u32 intel_guc_reserved_gtt_size(struct intel_guc *guc);
>>> -int intel_guc_reserve_ggtt_top(struct intel_guc *guc);
>>> -void intel_guc_release_ggtt_top(struct intel_guc *guc);
>>> +u32 intel_guc_reserved_gtt_size(struct i915_ggtt *ggtt);
>>> +int intel_guc_reserve_ggtt_top(struct i915_ggtt *ggtt);
>>> +void intel_guc_release_ggtt_top(struct i915_ggtt *ggtt);
>>> static inline bool intel_guc_is_loaded(struct intel_guc *guc)
>>>  {
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Re: [PATCH 21/21] drm/i915: Unexport i915_gem_init/fini_aliasing_ppgtt

[Rodrigo Vivi]

On Thu, Jun 06, 2019 at 10:36:39AM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> These two are only used from within i915_gem_gtt.c and can trivially be
> made static.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++++----
>  drivers/gpu/drm/i915/i915_gem_gtt.h | 3 ---
>  2 files changed, 4 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index d967a4e9ceb0..bd7a078f4b49 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2834,7 +2834,7 @@ static void i915_gtt_color_adjust(const struct drm_mm_node *node,
>  		*end -= I915_GTT_PAGE_SIZE;
>  }
>  
> -int i915_gem_init_aliasing_ppgtt(struct drm_i915_private *i915)
> +static int init_aliasing_ppgtt(struct drm_i915_private *i915)
>  {
>  	struct i915_ggtt *ggtt = &i915->ggtt;
>  	struct i915_hw_ppgtt *ppgtt;
> @@ -2874,7 +2874,7 @@ int i915_gem_init_aliasing_ppgtt(struct drm_i915_private *i915)
>  	return err;
>  }
>  
> -void i915_gem_fini_aliasing_ppgtt(struct drm_i915_private *i915)
> +static void fini_aliasing_ppgtt(struct drm_i915_private *i915)
>  {
>  	struct i915_ggtt *ggtt = &i915->ggtt;
>  	struct i915_hw_ppgtt *ppgtt;
> @@ -2942,7 +2942,7 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
>  	ggtt->vm.clear_range(&ggtt->vm, ggtt->vm.total - PAGE_SIZE, PAGE_SIZE);
>  
>  	if (INTEL_PPGTT(dev_priv) == INTEL_PPGTT_ALIASING) {
> -		ret = i915_gem_init_aliasing_ppgtt(dev_priv);
> +		ret = init_aliasing_ppgtt(dev_priv);
>  		if (ret)
>  			goto err_appgtt;
>  	}
> @@ -2969,7 +2969,7 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv)
>  	ggtt->vm.closed = true;
>  
>  	mutex_lock(&dev_priv->drm.struct_mutex);
> -	i915_gem_fini_aliasing_ppgtt(dev_priv);
> +	fini_aliasing_ppgtt(dev_priv);
>  
>  	list_for_each_entry_safe(vma, vn, &ggtt->vm.bound_list, vm_link)
>  		WARN_ON(i915_vma_unbind(vma));
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
> index 80703162c99a..6893ae015dce 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.h
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
> @@ -617,9 +617,6 @@ const struct intel_ppat_entry *
>  intel_ppat_get(struct drm_i915_private *i915, u8 value);
>  void intel_ppat_put(const struct intel_ppat_entry *entry);
>  
> -int i915_gem_init_aliasing_ppgtt(struct drm_i915_private *i915);
> -void i915_gem_fini_aliasing_ppgtt(struct drm_i915_private *i915);
> -
>  int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv);
>  int i915_ggtt_init_hw(struct drm_i915_private *dev_priv);
>  int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv);
> -- 
> 2.20.1
> 
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH 20/21] drm/i915: Make GuC GGTT reservation work on ggtt

[Rodrigo Vivi]

On Thu, Jun 06, 2019 at 10:36:38AM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> These functions operate on ggtt so make them take that directly as
> parameter.

This patch makes me wonder where we really want and need to go.

We need to move out of dev_priv and global i915...
but do we need to go and reduce to all minimal stuff used like
uncore and ggtt or could we find a middle solution where
each group has its own "class"?

like this guc stuff would keep the intel_guc, but the i915_gem
stuff or intel_gt stuff would have their own structs where
we have everything needed for that group?

> 
> At the same time move the USES_GUC conditional down to
> intel_guc_reserve_ggtt_top for symmetry with
> intel_guc_reserved_gtt_size.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 14 ++++++--------
>  drivers/gpu/drm/i915/intel_guc.c    | 18 ++++++++----------
>  drivers/gpu/drm/i915/intel_guc.h    |  6 +++---
>  3 files changed, 17 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index d3b3676d10f3..d967a4e9ceb0 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2912,7 +2912,7 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
>  	 * why.
>  	 */
>  	ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,
> -			       intel_guc_reserved_gtt_size(&dev_priv->guc));
> +			       intel_guc_reserved_gtt_size(ggtt));
>  
>  	ret = intel_vgt_balloon(ggtt);
>  	if (ret)
> @@ -2926,11 +2926,9 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
>  	if (ret)
>  		return ret;
>  
> -	if (USES_GUC(dev_priv)) {
> -		ret = intel_guc_reserve_ggtt_top(&dev_priv->guc);
> -		if (ret)
> -			goto err_reserve;
> -	}
> +	ret = intel_guc_reserve_ggtt_top(ggtt);
> +	if (ret)
> +		goto err_reserve;
>  
>  	/* Clear any non-preallocated blocks */
>  	drm_mm_for_each_hole(entry, &ggtt->vm.mm, hole_start, hole_end) {
> @@ -2952,7 +2950,7 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
>  	return 0;
>  
>  err_appgtt:
> -	intel_guc_release_ggtt_top(&dev_priv->guc);
> +	intel_guc_release_ggtt_top(ggtt);
>  err_reserve:
>  	drm_mm_remove_node(&ggtt->error_capture);
>  	return ret;
> @@ -2979,7 +2977,7 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv)
>  	if (drm_mm_node_allocated(&ggtt->error_capture))
>  		drm_mm_remove_node(&ggtt->error_capture);
>  
> -	intel_guc_release_ggtt_top(&dev_priv->guc);
> +	intel_guc_release_ggtt_top(ggtt);
>  
>  	if (drm_mm_initialized(&ggtt->vm.mm)) {
>  		intel_vgt_deballoon(ggtt);
> diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
> index b88c349c4fa6..633248b7da25 100644
> --- a/drivers/gpu/drm/i915/intel_guc.c
> +++ b/drivers/gpu/drm/i915/intel_guc.c
> @@ -719,7 +719,7 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
>  
>  /**
>   * intel_guc_reserved_gtt_size()
> - * @guc:	intel_guc structure
> + * @ggtt:	Pointer to struct i915_ggtt
>   *
>   * The GuC WOPCM mapping shadows the lower part of the GGTT, so if we are using
>   * GuC we can't have any objects pinned in that region. This function returns
> @@ -729,18 +729,19 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
>   * 0 if GuC is not present or not in use.
>   * Otherwise, the GuC WOPCM size.
>   */
> -u32 intel_guc_reserved_gtt_size(struct intel_guc *guc)
> +u32 intel_guc_reserved_gtt_size(struct i915_ggtt *ggtt)
>  {
> -	return guc_to_i915(guc)->wopcm.guc.size;
> +	return ggtt->vm.i915->wopcm.guc.size;
>  }
>  
> -int intel_guc_reserve_ggtt_top(struct intel_guc *guc)
> +int intel_guc_reserve_ggtt_top(struct i915_ggtt *ggtt)
>  {
> -	struct drm_i915_private *i915 = guc_to_i915(guc);
> -	struct i915_ggtt *ggtt = &i915->ggtt;
>  	u64 size;
>  	int ret;
>  
> +	if (!USES_GUC(ggtt->vm.i915))
> +		return 0;
> +
>  	size = ggtt->vm.total - GUC_GGTT_TOP;
>  
>  	ret = i915_gem_gtt_reserve(&ggtt->vm, &ggtt->uc_fw, size,
> @@ -752,11 +753,8 @@ int intel_guc_reserve_ggtt_top(struct intel_guc *guc)
>  	return ret;
>  }
>  
> -void intel_guc_release_ggtt_top(struct intel_guc *guc)
> +void intel_guc_release_ggtt_top(struct i915_ggtt *ggtt)
>  {
> -	struct drm_i915_private *i915 = guc_to_i915(guc);
> -	struct i915_ggtt *ggtt = &i915->ggtt;
> -
>  	if (drm_mm_node_allocated(&ggtt->uc_fw))
>  		drm_mm_remove_node(&ggtt->uc_fw);
>  }
> diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
> index cbfed7a77c8b..55ea14176c5e 100644
> --- a/drivers/gpu/drm/i915/intel_guc.h
> +++ b/drivers/gpu/drm/i915/intel_guc.h
> @@ -173,9 +173,9 @@ int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset);
>  int intel_guc_suspend(struct intel_guc *guc);
>  int intel_guc_resume(struct intel_guc *guc);
>  struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
> -u32 intel_guc_reserved_gtt_size(struct intel_guc *guc);
> -int intel_guc_reserve_ggtt_top(struct intel_guc *guc);
> -void intel_guc_release_ggtt_top(struct intel_guc *guc);
> +u32 intel_guc_reserved_gtt_size(struct i915_ggtt *ggtt);
> +int intel_guc_reserve_ggtt_top(struct i915_ggtt *ggtt);
> +void intel_guc_release_ggtt_top(struct i915_ggtt *ggtt);
>  
>  static inline bool intel_guc_is_loaded(struct intel_guc *guc)
>  {
> -- 
> 2.20.1
> 
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Re: [PATCH 17/21] drm/i915: Consolidate some open coded mmio rmw

[Rodrigo Vivi]

On Thu, Jun 06, 2019 at 10:36:35AM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Replace some gen6/7 open coded rmw with intel_uncore_rmw.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 42 +++++++++++++----------------
>  1 file changed, 18 insertions(+), 24 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index b2c2dc99bf8a..fe9cd4ea9671 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -1697,13 +1697,10 @@ static void gen7_ppgtt_enable(struct intel_uncore *uncore)
>  {
>  	struct drm_i915_private *i915 = uncore_to_i915(uncore);
>  	struct intel_engine_cs *engine;
> -	u32 ecochk, ecobits;
>  	enum intel_engine_id id;
> +	u32 ecochk;
>  
> -	ecobits = intel_uncore_read(uncore, GAC_ECO_BITS);
> -	intel_uncore_write(uncore,
> -			   GAC_ECO_BITS,
> -			   ecobits | ECOBITS_PPGTT_CACHE64B);
> +	intel_uncore_rmw(uncore, GAC_ECO_BITS, 0, ECOBITS_PPGTT_CACHE64B);
>  
>  	ecochk = intel_uncore_read(uncore, GAM_ECOCHK);
>  	if (IS_HASWELL(i915)) {
> @@ -1724,22 +1721,20 @@ static void gen7_ppgtt_enable(struct intel_uncore *uncore)
>  
>  static void gen6_ppgtt_enable(struct intel_uncore *uncore)
>  {
> -	u32 ecochk, gab_ctl, ecobits;
> +	intel_uncore_rmw(uncore,
> +			 GAC_ECO_BITS,
> +			 0,
> +			 ECOBITS_SNB_BIT | ECOBITS_PPGTT_CACHE64B);
>  
> -	ecobits = intel_uncore_read(uncore, GAC_ECO_BITS);
> -	intel_uncore_write(uncore,
> -			   GAC_ECO_BITS,
> -			   ecobits | ECOBITS_SNB_BIT | ECOBITS_PPGTT_CACHE64B);
> +	intel_uncore_rmw(uncore,
> +			 GAB_CTL,
> +			 0,
> +			 GAB_CTL_CONT_AFTER_PAGEFAULT);
>  
> -	gab_ctl = intel_uncore_read(uncore, GAB_CTL);
> -	intel_uncore_write(uncore,
> -			   GAB_CTL,
> -			   gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
> -
> -	ecochk = intel_uncore_read(uncore, GAM_ECOCHK);
> -	intel_uncore_write(uncore,
> -			   GAM_ECOCHK,
> -			   ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
> +	intel_uncore_rmw(uncore,
> +			 GAM_ECOCHK,
> +			 0,
> +			 ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
>  
>  	if (HAS_PPGTT(uncore_to_i915(uncore))) /* may be disabled for VT-d */
>  		intel_uncore_write(uncore,
> @@ -2234,11 +2229,10 @@ static void gtt_write_workarounds(struct intel_uncore *uncore)
>  	 */
>  	if (HAS_PAGE_SIZES(i915, I915_GTT_PAGE_SIZE_64K) &&
>  	    INTEL_GEN(i915) <= 10)
> -		intel_uncore_write(uncore,
> -				   GEN8_GAMW_ECO_DEV_RW_IA,
> -				   intel_uncore_read(uncore,
> -						     GEN8_GAMW_ECO_DEV_RW_IA) |
> -				   GAMW_ECO_ENABLE_64K_IPS_FIELD);
> +		intel_uncore_rmw(uncore,
> +				 GEN8_GAMW_ECO_DEV_RW_IA,
> +				 0,
> +				 GAMW_ECO_ENABLE_64K_IPS_FIELD);
>  }
>  
>  int i915_ppgtt_init_hw(struct intel_uncore *uncore)
> -- 
> 2.20.1
> 
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✗ Fi.CI.IGT: failure for Implicit dev_priv removal

[Patchwork]

== Series Details ==

Series: Implicit dev_priv removal
URL   : https://patchwork.freedesktop.org/series/61705/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_6205_full -> Patchwork_13190_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_13190_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_13190_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_13190_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_exec_schedule@preempt-hang-blt:
    - shard-iclb:         [PASS][1] -> [SKIP][2] +17 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/shard-iclb7/igt@gem_exec_schedule@preempt-hang-blt.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/shard-iclb2/igt@gem_exec_schedule@preempt-hang-blt.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@gem_ctx_shared@q-in-order-blt}:
    - shard-iclb:         [PASS][3] -> [SKIP][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/shard-iclb6/igt@gem_ctx_shared@q-in-order-blt.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/shard-iclb4/igt@gem_ctx_shared@q-in-order-blt.html

  
Known issues
------------

  Here are the changes found in Patchwork_13190_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_eio@in-flight-suspend:
    - shard-skl:          [PASS][5] -> [INCOMPLETE][6] ([fdo#104108]) +1 similar issue
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/shard-skl5/igt@gem_eio@in-flight-suspend.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/shard-skl7/igt@gem_eio@in-flight-suspend.html

  * igt@gem_exec_schedule@preempt-bsd1:
    - shard-kbl:          [PASS][7] -> [SKIP][8] ([fdo#109271]) +95 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/shard-kbl2/igt@gem_exec_schedule@preempt-bsd1.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/shard-kbl3/igt@gem_exec_schedule@preempt-bsd1.html

  * igt@gem_exec_schedule@preempt-queue-contexts-render:
    - shard-glk:          [PASS][9] -> [SKIP][10] ([fdo#109271]) +63 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/shard-glk7/igt@gem_exec_schedule@preempt-queue-contexts-render.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/shard-glk9/igt@gem_exec_schedule@preempt-queue-contexts-render.html
    - shard-skl:          [PASS][11] -> [SKIP][12] ([fdo#109271]) +54 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/shard-skl4/igt@gem_exec_schedule@preempt-queue-contexts-render.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/shard-skl7/igt@gem_exec_schedule@preempt-queue-contexts-render.html

  * igt@gem_exec_schedule@semaphore-user:
    - shard-apl:          [PASS][13] -> [SKIP][14] ([fdo#109271]) +63 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/shard-apl4/igt@gem_exec_schedule@semaphore-user.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/shard-apl4/igt@gem_exec_schedule@semaphore-user.html

  * igt@gem_workarounds@suspend-resume:
    - shard-apl:          [PASS][15] -> [DMESG-WARN][16] ([fdo#108566]) +4 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/shard-apl5/igt@gem_workarounds@suspend-resume.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/shard-apl6/igt@gem_workarounds@suspend-resume.html

  * igt@i915_pm_rpm@debugfs-forcewake-user:
    - shard-iclb:         [PASS][17] -> [INCOMPLETE][18] ([fdo#107713] / [fdo#108840])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/shard-iclb7/igt@i915_pm_rpm@debugfs-forcewake-user.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/shard-iclb2/igt@i915_pm_rpm@debugfs-forcewake-user.html

  * igt@kms_cursor_edge_walk@pipe-b-64x64-right-edge:
    - shard-snb:          [PASS][19] -> [SKIP][20] ([fdo#109271] / [fdo#109278])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/shard-snb5/igt@kms_cursor_edge_walk@pipe-b-64x64-right-edge.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/shard-snb2/igt@kms_cursor_edge_walk@pipe-b-64x64-right-edge.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
    - shard-glk:          [PASS][21] -> [FAIL][22] ([fdo#102887])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/shard-glk5/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-cpu:
    - shard-snb:          [PASS][23] -> [SKIP][24] ([fdo#109271]) +4 similar issues
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/shard-snb5/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-cpu.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/shard-snb2/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-onoff:
    - shard-iclb:         [PASS][25] -> [FAIL][26] ([fdo#103167]) +1 similar issue
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-onoff.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-gtt:
    - shard-skl:          [PASS][27] -> [FAIL][28] ([fdo#103167])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/shard-skl6/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-gtt.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/shard-skl2/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_psr@psr2_dpms:
    - shard-iclb:         [PASS][29] -> [SKIP][30] ([fdo#109441]) +1 similar issue
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/shard-iclb2/igt@kms_psr@psr2_dpms.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/shard-iclb8/igt@kms_psr@psr2_dpms.html

  
#### Possible fixes ####

  * igt@gem_ctx_isolation@vcs0-s3:
    - shard-skl:          [INCOMPLETE][31] ([fdo#104108]) -> [PASS][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/shard-skl2/igt@gem_ctx_isolation@vcs0-s3.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/shard-skl9/igt@gem_ctx_isolation@vcs0-s3.html

  * igt@gem_ctx_param@set-priority-not-supported:
    - shard-apl:          [SKIP][33] ([fdo#109271]) -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/shard-apl8/igt@gem_ctx_param@set-priority-not-supported.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/shard-apl6/igt@gem_ctx_param@set-priority-not-supported.html
    - shard-kbl:          [SKIP][35] ([fdo#109271]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/shard-kbl1/igt@gem_ctx_param@set-priority-not-supported.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/shard-kbl6/igt@gem_ctx_param@set-priority-not-supported.html
    - shard-skl:          [SKIP][37] ([fdo#109271]) -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/shard-skl2/igt@gem_ctx_param@set-priority-not-supported.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/shard-skl9/igt@gem_ctx_param@set-priority-not-supported.html
    - shard-glk:          [SKIP][39] ([fdo#109271]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/shard-glk1/igt@gem_ctx_param@set-priority-not-supported.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/shard-glk3/igt@gem_ctx_param@set-priority-not-supported.html

  * igt@gem_mmap_gtt@forked-medium-copy:
    - shard-iclb:         [INCOMPLETE][41] ([fdo#107713]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/shard-iclb8/igt@gem_mmap_gtt@forked-medium-copy.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/shard-iclb4/igt@gem_mmap_gtt@forked-medium-copy.html

  * igt@i915_pm_rpm@legacy-planes-dpms:
    - shard-iclb:         [INCOMPLETE][43] ([fdo#107713] / [fdo#108840] / [fdo#109960]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/shard-iclb2/igt@i915_pm_rpm@legacy-planes-dpms.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/shard-iclb3/igt@i915_pm_rpm@legacy-planes-dpms.html

  * igt@kms_flip@2x-modeset-vs-vblank-race:
    - shard-glk:          [FAIL][45] ([fdo#103060]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/shard-glk5/igt@kms_flip@2x-modeset-vs-vblank-race.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/shard-glk3/igt@kms_flip@2x-modeset-vs-vblank-race.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-apl:          [DMESG-WARN][47] ([fdo#108566]) -> [PASS][48] +2 similar issues
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible.html
    - shard-snb:          [INCOMPLETE][49] ([fdo#105411]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/shard-snb1/igt@kms_flip@flip-vs-suspend-interruptible.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/shard-snb1/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt:
    - shard-iclb:         [FAIL][51] ([fdo#103167]) -> [PASS][52] +6 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html

  * igt@kms_psr@psr2_primary_mmap_gtt:
    - shard-iclb:         [SKIP][53] ([fdo#109441]) -> [PASS][54] +1 similar issue
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/shard-iclb3/igt@kms_psr@psr2_primary_mmap_gtt.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html

  * igt@perf@blocking:
    - shard-skl:          [FAIL][55] ([fdo#110728]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/shard-skl7/igt@perf@blocking.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/shard-skl8/igt@perf@blocking.html

  
#### Warnings ####

  * igt@gem_exec_schedule@semaphore-resolve:
    - shard-glk:          [FAIL][57] ([fdo#110519]) -> [SKIP][58] ([fdo#109271])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/shard-glk1/igt@gem_exec_schedule@semaphore-resolve.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/shard-glk3/igt@gem_exec_schedule@semaphore-resolve.html
    - shard-skl:          [FAIL][59] ([fdo#110519]) -> [SKIP][60] ([fdo#109271])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/shard-skl3/igt@gem_exec_schedule@semaphore-resolve.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/shard-skl9/igt@gem_exec_schedule@semaphore-resolve.html
    - shard-kbl:          [FAIL][61] ([fdo#110519]) -> [SKIP][62] ([fdo#109271])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/shard-kbl4/igt@gem_exec_schedule@semaphore-resolve.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/shard-kbl2/igt@gem_exec_schedule@semaphore-resolve.html
    - shard-apl:          [FAIL][63] ([fdo#110519]) -> [SKIP][64] ([fdo#109271])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/shard-apl4/igt@gem_exec_schedule@semaphore-resolve.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/shard-apl5/igt@gem_exec_schedule@semaphore-resolve.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-skl:          [FAIL][65] ([fdo#103167]) -> [FAIL][66] ([fdo#108040])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6205/shard-skl6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/shard-skl2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#102887]: https://bugs.freedesktop.org/show_bug.cgi?id=102887
  [fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#108040]: https://bugs.freedesktop.org/show_bug.cgi?id=108040
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109960]: https://bugs.freedesktop.org/show_bug.cgi?id=109960
  [fdo#110519]: https://bugs.freedesktop.org/show_bug.cgi?id=110519
  [fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
  [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854


Participating hosts (9 -> 9)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_6205 -> Patchwork_13190

  CI_DRM_6205: 6021addc939f244fd19e8142aa5ce838e5fa2901 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5043: 3e2b20817b68ab41377c1b86207a1e7309fc3779 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13190: d4566f34339dba02be6572acdf7ef4943cd86d30 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13190/
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