[PATCH] drm/i915: Deal with machines that expose less than three QGV points

[PATCH] drm/i915: Deal with machines that expose less than three QGV points

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

When SAGV is forced to disabled/min/med/max in the BIOS pcode will
only hand us a single QGV point instead of the normal three. Fix
the code to deal with that instead declaring the bandwidth limit
to be 0 MB/s (and thus preventing any planes from being enabled).

Also shrink the max_bw sturct a bit while at it, and change the
deratedbw type to unsigned since the code returns the bw as
an unsigned int.

Since we now keep track of how many qgv points we got from pcode
we can drop the earlier check added for the "pcode doesn't
support the memory subsystem query" case.

Cc: felix.j.degrood@intel.com
Cc: Mark Janes <mark.a.janes@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Clint Taylor <Clinton.A.Taylor@intel.com>
Fixes: c457d9cf256e ("drm/i915: Make sure we have enough memory bandwidth on ICL")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110838
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h |  5 +++--
 drivers/gpu/drm/i915/intel_bw.c | 15 ++++++++++-----
 2 files changed, 13 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 89bf1e34feaa..f4c7afebfa27 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1738,8 +1738,9 @@ struct drm_i915_private {
 	} dram_info;
 
 	struct intel_bw_info {
-		int num_planes;
-		int deratedbw[3];
+		unsigned int deratedbw[3]; /* for each QGV point */
+		u8 num_qgv_points;
+		u8 num_planes;
 	} max_bw[6];
 
 	struct drm_private_obj bw_obj;
diff --git a/drivers/gpu/drm/i915/intel_bw.c b/drivers/gpu/drm/i915/intel_bw.c
index 753ac3165061..7b908e10d32e 100644
--- a/drivers/gpu/drm/i915/intel_bw.c
+++ b/drivers/gpu/drm/i915/intel_bw.c
@@ -178,6 +178,8 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv)
 		clpchgroup = (sa->deburst * deinterleave / num_channels) << i;
 		bi->num_planes = (ipqdepth - clpchgroup) / clpchgroup + 1;
 
+		bi->num_qgv_points = qi.num_points;
+
 		for (j = 0; j < qi.num_points; j++) {
 			const struct intel_qgv_point *sp = &qi.points[j];
 			int ct, bw;
@@ -195,7 +197,7 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv)
 			bi->deratedbw[j] = min(maxdebw,
 					       bw * 9 / 10); /* 90% */
 
-			DRM_DEBUG_KMS("BW%d / QGV %d: num_planes=%d deratedbw=%d\n",
+			DRM_DEBUG_KMS("BW%d / QGV %d: num_planes=%d deratedbw=%u\n",
 				      i, j, bi->num_planes, bi->deratedbw[j]);
 		}
 
@@ -211,14 +213,17 @@ static unsigned int icl_max_bw(struct drm_i915_private *dev_priv,
 {
 	int i;
 
-	/* Did we initialize the bw limits successfully? */
-	if (dev_priv->max_bw[0].num_planes == 0)
-		return UINT_MAX;
-
 	for (i = 0; i < ARRAY_SIZE(dev_priv->max_bw); i++) {
 		const struct intel_bw_info *bi =
 			&dev_priv->max_bw[i];
 
+		/*
+		 * Pcode will not expose all QGV points when
+		 * SAGV is forced to off/min/med/max.
+		 */
+		if (qgv_point >= bi->num_qgv_points)
+			return UINT_MAX;
+
 		if (num_planes >= bi->num_planes)
 			return bi->deratedbw[qgv_point];
 	}
-- 
2.21.0

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✗ Fi.CI.SPARSE: warning for drm/i915: Deal with machines that expose less than three QGV points

[Patchwork]

== Series Details ==

Series: drm/i915: Deal with machines that expose less than three QGV points
URL   : https://patchwork.freedesktop.org/series/61713/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Deal with machines that expose less than three QGV points
-O:drivers/gpu/drm/i915/intel_bw.c:195:44: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_bw.c:195:44: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_bw.c:197:44: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_bw.c:197:44: warning: expression using sizeof(void)

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✓ Fi.CI.BAT: success for drm/i915: Deal with machines that expose less than three QGV points

[Patchwork]

== Series Details ==

Series: drm/i915: Deal with machines that expose less than three QGV points
URL   : https://patchwork.freedesktop.org/series/61713/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6206 -> Patchwork_13193
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13193/

Known issues
------------

  Here are the changes found in Patchwork_13193 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_flink_basic@flink-lifetime:
    - fi-icl-u3:          [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6206/fi-icl-u3/igt@gem_flink_basic@flink-lifetime.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13193/fi-icl-u3/igt@gem_flink_basic@flink-lifetime.html

  * igt@i915_selftest@live_hangcheck:
    - fi-icl-u2:          [PASS][3] -> [DMESG-FAIL][4] ([fdo#110429])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6206/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13193/fi-icl-u2/igt@i915_selftest@live_hangcheck.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-hsw-peppy:       [PASS][5] -> [DMESG-WARN][6] ([fdo#102614])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6206/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13193/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html

  
#### Possible fixes ####

  * igt@vgem_basic@unload:
    - fi-icl-u3:          [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6206/fi-icl-u3/igt@vgem_basic@unload.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13193/fi-icl-u3/igt@vgem_basic@unload.html

  
  [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#110429]: https://bugs.freedesktop.org/show_bug.cgi?id=110429


Participating hosts (55 -> 46)
------------------------------

  Missing    (9): fi-ilk-m540 fi-hsw-4200u fi-bsw-n3050 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-kbl-7560u fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_6206 -> Patchwork_13193

  CI_DRM_6206: 14ef563cbee376503d3551992d71f2f075e7462c @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5043: 3e2b20817b68ab41377c1b86207a1e7309fc3779 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13193: 4db3e33d99e94d919fa1a7a2dc06efa6cbdaa1d7 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

4db3e33d99e9 drm/i915: Deal with machines that expose less than three QGV points

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13193/
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Re: [PATCH] drm/i915: Deal with machines that expose less than three QGV points

[Degrood, Felix J]

Verified that patch fixes the issue.  My ICL with SAGV forced to max now boots to desktop with display.

This patch resolves my issue completely.  Thanks for your help!

~Felix DeGrood

-----Original Message-----
From: Ville Syrjala <ville.syrjala@linux.intel.com> 
Sent: Thursday, June 06, 2019 5:42 AM
To: intel-gfx@lists.freedesktop.org
Cc: Degrood, Felix J <felix.j.degrood@intel.com>; Janes, Mark A <mark.a.janes@intel.com>; Roper, Matthew D <matthew.d.roper@intel.com>; Taylor, Clinton A <clinton.a.taylor@intel.com>
Subject: [PATCH] drm/i915: Deal with machines that expose less than three QGV points

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

When SAGV is forced to disabled/min/med/max in the BIOS pcode will only hand us a single QGV point instead of the normal three. Fix the code to deal with that instead declaring the bandwidth limit to be 0 MB/s (and thus preventing any planes from being enabled).

Also shrink the max_bw sturct a bit while at it, and change the deratedbw type to unsigned since the code returns the bw as an unsigned int.

Since we now keep track of how many qgv points we got from pcode we can drop the earlier check added for the "pcode doesn't support the memory subsystem query" case.

Cc: felix.j.degrood@intel.com
Cc: Mark Janes <mark.a.janes@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Clint Taylor <Clinton.A.Taylor@intel.com>
Fixes: c457d9cf256e ("drm/i915: Make sure we have enough memory bandwidth on ICL")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110838
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h |  5 +++--  drivers/gpu/drm/i915/intel_bw.c | 15 ++++++++++-----
 2 files changed, 13 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 89bf1e34feaa..f4c7afebfa27 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1738,8 +1738,9 @@ struct drm_i915_private {
 	} dram_info;
 
 	struct intel_bw_info {
-		int num_planes;
-		int deratedbw[3];
+		unsigned int deratedbw[3]; /* for each QGV point */
+		u8 num_qgv_points;
+		u8 num_planes;
 	} max_bw[6];
 
 	struct drm_private_obj bw_obj;
diff --git a/drivers/gpu/drm/i915/intel_bw.c b/drivers/gpu/drm/i915/intel_bw.c index 753ac3165061..7b908e10d32e 100644
--- a/drivers/gpu/drm/i915/intel_bw.c
+++ b/drivers/gpu/drm/i915/intel_bw.c
@@ -178,6 +178,8 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv)
 		clpchgroup = (sa->deburst * deinterleave / num_channels) << i;
 		bi->num_planes = (ipqdepth - clpchgroup) / clpchgroup + 1;
 
+		bi->num_qgv_points = qi.num_points;
+
 		for (j = 0; j < qi.num_points; j++) {
 			const struct intel_qgv_point *sp = &qi.points[j];
 			int ct, bw;
@@ -195,7 +197,7 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv)
 			bi->deratedbw[j] = min(maxdebw,
 					       bw * 9 / 10); /* 90% */
 
-			DRM_DEBUG_KMS("BW%d / QGV %d: num_planes=%d deratedbw=%d\n",
+			DRM_DEBUG_KMS("BW%d / QGV %d: num_planes=%d deratedbw=%u\n",
 				      i, j, bi->num_planes, bi->deratedbw[j]);
 		}
 
@@ -211,14 +213,17 @@ static unsigned int icl_max_bw(struct drm_i915_private *dev_priv,  {
 	int i;
 
-	/* Did we initialize the bw limits successfully? */
-	if (dev_priv->max_bw[0].num_planes == 0)
-		return UINT_MAX;
-
 	for (i = 0; i < ARRAY_SIZE(dev_priv->max_bw); i++) {
 		const struct intel_bw_info *bi =
 			&dev_priv->max_bw[i];
 
+		/*
+		 * Pcode will not expose all QGV points when
+		 * SAGV is forced to off/min/med/max.
+		 */
+		if (qgv_point >= bi->num_qgv_points)
+			return UINT_MAX;
+
 		if (num_planes >= bi->num_planes)
 			return bi->deratedbw[qgv_point];
 	}
--
2.21.0

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✓ Fi.CI.IGT: success for drm/i915: Deal with machines that expose less than three QGV points

[Patchwork]

== Series Details ==

Series: drm/i915: Deal with machines that expose less than three QGV points
URL   : https://patchwork.freedesktop.org/series/61713/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6206_full -> Patchwork_13193_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_13193_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_mmap_gtt@forked-big-copy:
    - shard-iclb:         [PASS][1] -> [TIMEOUT][2] ([fdo#109673])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6206/shard-iclb1/igt@gem_mmap_gtt@forked-big-copy.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13193/shard-iclb3/igt@gem_mmap_gtt@forked-big-copy.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-apl:          [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +2 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6206/shard-apl1/igt@kms_flip@flip-vs-suspend-interruptible.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13193/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt:
    - shard-iclb:         [PASS][5] -> [FAIL][6] ([fdo#103167]) +6 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6206/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13193/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-cpu:
    - shard-skl:          [PASS][7] -> [FAIL][8] ([fdo#103167] / [fdo#110379])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6206/shard-skl6/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-cpu.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13193/shard-skl7/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-cpu.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [PASS][9] -> [FAIL][10] ([fdo#108145] / [fdo#110403])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6206/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13193/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_plane_lowres@pipe-a-tiling-x:
    - shard-iclb:         [PASS][11] -> [FAIL][12] ([fdo#103166]) +1 similar issue
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6206/shard-iclb4/igt@kms_plane_lowres@pipe-a-tiling-x.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13193/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-x.html

  * igt@kms_psr@psr2_sprite_plane_move:
    - shard-iclb:         [PASS][13] -> [SKIP][14] ([fdo#109441]) +2 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6206/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13193/shard-iclb1/igt@kms_psr@psr2_sprite_plane_move.html

  
#### Possible fixes ####

  * igt@gem_tiled_swapping@non-threaded:
    - shard-kbl:          [DMESG-WARN][15] ([fdo#108686]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6206/shard-kbl3/igt@gem_tiled_swapping@non-threaded.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13193/shard-kbl7/igt@gem_tiled_swapping@non-threaded.html

  * igt@i915_pm_rpm@universal-planes:
    - shard-iclb:         [INCOMPLETE][17] ([fdo#107713] / [fdo#108840]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6206/shard-iclb5/igt@i915_pm_rpm@universal-planes.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13193/shard-iclb7/igt@i915_pm_rpm@universal-planes.html

  * igt@i915_suspend@fence-restore-tiled2untiled:
    - shard-apl:          [DMESG-WARN][19] ([fdo#108566]) -> [PASS][20] +5 similar issues
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6206/shard-apl5/igt@i915_suspend@fence-restore-tiled2untiled.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13193/shard-apl5/igt@i915_suspend@fence-restore-tiled2untiled.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-skl:          [FAIL][21] ([fdo#105363]) -> [PASS][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6206/shard-skl5/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13193/shard-skl10/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-farfromfence:
    - shard-skl:          [FAIL][23] ([fdo#103167]) -> [PASS][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6206/shard-skl3/igt@kms_frontbuffer_tracking@fbc-farfromfence.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13193/shard-skl6/igt@kms_frontbuffer_tracking@fbc-farfromfence.html

  * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite:
    - shard-iclb:         [FAIL][25] ([fdo#103167]) -> [PASS][26] +2 similar issues
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6206/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13193/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
    - shard-skl:          [FAIL][27] ([fdo#108145]) -> [PASS][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6206/shard-skl3/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13193/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          [FAIL][29] ([fdo#108145] / [fdo#110403]) -> [PASS][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6206/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13193/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html

  * igt@perf@polling:
    - shard-iclb:         [FAIL][31] ([fdo#110728]) -> [PASS][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6206/shard-iclb7/igt@perf@polling.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13193/shard-iclb5/igt@perf@polling.html

  
  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
  [fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109673]: https://bugs.freedesktop.org/show_bug.cgi?id=109673
  [fdo#110379]: https://bugs.freedesktop.org/show_bug.cgi?id=110379
  [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
  [fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728


Participating hosts (9 -> 10)
------------------------------

  Additional (1): shard-hsw 


Build changes
-------------

  * Linux: CI_DRM_6206 -> Patchwork_13193

  CI_DRM_6206: 14ef563cbee376503d3551992d71f2f075e7462c @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5043: 3e2b20817b68ab41377c1b86207a1e7309fc3779 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13193: 4db3e33d99e94d919fa1a7a2dc06efa6cbdaa1d7 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13193/
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Re: [PATCH] drm/i915: Deal with machines that expose less than three QGV points

[Matt Roper]

On Thu, Jun 06, 2019 at 03:42:10PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> When SAGV is forced to disabled/min/med/max in the BIOS pcode will
> only hand us a single QGV point instead of the normal three. Fix
> the code to deal with that instead declaring the bandwidth limit
> to be 0 MB/s (and thus preventing any planes from being enabled).
> 
> Also shrink the max_bw sturct a bit while at it, and change the
> deratedbw type to unsigned since the code returns the bw as
> an unsigned int.
> 
> Since we now keep track of how many qgv points we got from pcode
> we can drop the earlier check added for the "pcode doesn't
> support the memory subsystem query" case.
> 
> Cc: felix.j.degrood@intel.com
> Cc: Mark Janes <mark.a.janes@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Clint Taylor <Clinton.A.Taylor@intel.com>
> Fixes: c457d9cf256e ("drm/i915: Make sure we have enough memory bandwidth on ICL")
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110838
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

This one slipped through the cracks, but it looks correct.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

You'll need to re-spin the patch since intel_bw.c is under the display/
folder now and enough time has passed that we probably want another CI
run anyway.


Matt

> ---
>  drivers/gpu/drm/i915/i915_drv.h |  5 +++--
>  drivers/gpu/drm/i915/intel_bw.c | 15 ++++++++++-----
>  2 files changed, 13 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 89bf1e34feaa..f4c7afebfa27 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1738,8 +1738,9 @@ struct drm_i915_private {
>  	} dram_info;
>  
>  	struct intel_bw_info {
> -		int num_planes;
> -		int deratedbw[3];
> +		unsigned int deratedbw[3]; /* for each QGV point */
> +		u8 num_qgv_points;
> +		u8 num_planes;
>  	} max_bw[6];
>  
>  	struct drm_private_obj bw_obj;
> diff --git a/drivers/gpu/drm/i915/intel_bw.c b/drivers/gpu/drm/i915/intel_bw.c
> index 753ac3165061..7b908e10d32e 100644
> --- a/drivers/gpu/drm/i915/intel_bw.c
> +++ b/drivers/gpu/drm/i915/intel_bw.c
> @@ -178,6 +178,8 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv)
>  		clpchgroup = (sa->deburst * deinterleave / num_channels) << i;
>  		bi->num_planes = (ipqdepth - clpchgroup) / clpchgroup + 1;
>  
> +		bi->num_qgv_points = qi.num_points;
> +
>  		for (j = 0; j < qi.num_points; j++) {
>  			const struct intel_qgv_point *sp = &qi.points[j];
>  			int ct, bw;
> @@ -195,7 +197,7 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv)
>  			bi->deratedbw[j] = min(maxdebw,
>  					       bw * 9 / 10); /* 90% */
>  
> -			DRM_DEBUG_KMS("BW%d / QGV %d: num_planes=%d deratedbw=%d\n",
> +			DRM_DEBUG_KMS("BW%d / QGV %d: num_planes=%d deratedbw=%u\n",
>  				      i, j, bi->num_planes, bi->deratedbw[j]);
>  		}
>  
> @@ -211,14 +213,17 @@ static unsigned int icl_max_bw(struct drm_i915_private *dev_priv,
>  {
>  	int i;
>  
> -	/* Did we initialize the bw limits successfully? */
> -	if (dev_priv->max_bw[0].num_planes == 0)
> -		return UINT_MAX;
> -
>  	for (i = 0; i < ARRAY_SIZE(dev_priv->max_bw); i++) {
>  		const struct intel_bw_info *bi =
>  			&dev_priv->max_bw[i];
>  
> +		/*
> +		 * Pcode will not expose all QGV points when
> +		 * SAGV is forced to off/min/med/max.
> +		 */
> +		if (qgv_point >= bi->num_qgv_points)
> +			return UINT_MAX;
> +
>  		if (num_planes >= bi->num_planes)
>  			return bi->deratedbw[qgv_point];
>  	}
> -- 
> 2.21.0
> 

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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Re: [PATCH] drm/i915: Deal with machines that expose less than three QGV points

[Ville Syrjälä]

On Wed, Jul 03, 2019 at 11:01:18AM -0700, Matt Roper wrote:
> On Thu, Jun 06, 2019 at 03:42:10PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > When SAGV is forced to disabled/min/med/max in the BIOS pcode will
> > only hand us a single QGV point instead of the normal three. Fix
> > the code to deal with that instead declaring the bandwidth limit
> > to be 0 MB/s (and thus preventing any planes from being enabled).
> > 
> > Also shrink the max_bw sturct a bit while at it, and change the
> > deratedbw type to unsigned since the code returns the bw as
> > an unsigned int.
> > 
> > Since we now keep track of how many qgv points we got from pcode
> > we can drop the earlier check added for the "pcode doesn't
> > support the memory subsystem query" case.
> > 
> > Cc: felix.j.degrood@intel.com
> > Cc: Mark Janes <mark.a.janes@intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Cc: Clint Taylor <Clinton.A.Taylor@intel.com>
> > Fixes: c457d9cf256e ("drm/i915: Make sure we have enough memory bandwidth on ICL")
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110838
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> This one slipped through the cracks, but it looks correct.

Yeah, also disappeared from my own radar due to patchwork getting
confused and moving the patch under Felix's authorship.

> 
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

Thanks.

> 
> You'll need to re-spin the patch since intel_bw.c is under the display/
> folder now and enough time has passed that we probably want another CI
> run anyway.

git am is smart enough to deal with file renames usually, and nothing
has changed really so I trust the earlier ci results. Pushed to dinq.

-- 
Ville Syrjälä
Intel
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