* [CI 1/5] drm/i915: Reset only affected engines when handling error capture
@ 2019-06-07 8:25 Tvrtko Ursulin
2019-06-07 8:25 ` [CI 2/5] drm/i915: Tidy engine mask types in hangcheck Tvrtko Ursulin
` (8 more replies)
0 siblings, 9 replies; 12+ messages in thread
From: Tvrtko Ursulin @ 2019-06-07 8:25 UTC (permalink / raw)
To: Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Pass down the engine mask to i915_clear_error_registers so only affected
engines can be reset on the Gen6/7 path.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_reset.c | 7 ++++---
drivers/gpu/drm/i915/gt/intel_reset.h | 3 ++-
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
3 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index 377bc546a68f..7bfb76eb0291 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -1160,7 +1160,8 @@ static void clear_register(struct intel_uncore *uncore, i915_reg_t reg)
intel_uncore_rmw(uncore, reg, 0, 0);
}
-void i915_clear_error_registers(struct drm_i915_private *i915)
+void i915_clear_error_registers(struct drm_i915_private *i915,
+ intel_engine_mask_t engine_mask)
{
struct intel_uncore *uncore = &i915->uncore;
u32 eir;
@@ -1193,7 +1194,7 @@ void i915_clear_error_registers(struct drm_i915_private *i915)
struct intel_engine_cs *engine;
enum intel_engine_id id;
- for_each_engine(engine, i915, id) {
+ for_each_engine_masked(engine, i915, engine_mask, id) {
rmw_clear(uncore,
RING_FAULT_REG(engine), RING_FAULT_VALID);
intel_uncore_posting_read(uncore,
@@ -1250,7 +1251,7 @@ void i915_handle_error(struct drm_i915_private *i915,
if (flags & I915_ERROR_CAPTURE) {
i915_capture_error_state(i915, engine_mask, msg);
- i915_clear_error_registers(i915);
+ i915_clear_error_registers(i915, engine_mask);
}
/*
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.h b/drivers/gpu/drm/i915/gt/intel_reset.h
index b52efaab4941..4f3c1acac1a3 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.h
+++ b/drivers/gpu/drm/i915/gt/intel_reset.h
@@ -25,7 +25,8 @@ void i915_handle_error(struct drm_i915_private *i915,
const char *fmt, ...);
#define I915_ERROR_CAPTURE BIT(0)
-void i915_clear_error_registers(struct drm_i915_private *i915);
+void i915_clear_error_registers(struct drm_i915_private *i915,
+ intel_engine_mask_t engine_mask);
void i915_reset(struct drm_i915_private *i915,
intel_engine_mask_t stalled_mask,
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 6fcf702d7ec1..c5a94396024f 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2359,7 +2359,7 @@ void i915_check_and_clear_faults(struct drm_i915_private *dev_priv)
else
return;
- i915_clear_error_registers(dev_priv);
+ i915_clear_error_registers(dev_priv, ALL_ENGINES);
}
void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv)
--
2.20.1
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* [CI 2/5] drm/i915: Tidy engine mask types in hangcheck
2019-06-07 8:25 [CI 1/5] drm/i915: Reset only affected engines when handling error capture Tvrtko Ursulin
@ 2019-06-07 8:25 ` Tvrtko Ursulin
2019-06-07 8:25 ` [CI 3/5] drm/i915: Make Gen6/7 RING_FAULT_REG access engine centric Tvrtko Ursulin
` (7 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Tvrtko Ursulin @ 2019-06-07 8:25 UTC (permalink / raw)
To: Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
We can use intel_engine_mask_t to align with the rest of the codebase.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_hangcheck.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_hangcheck.c b/drivers/gpu/drm/i915/gt/intel_hangcheck.c
index 3a4d09b80fa0..174bb0a60309 100644
--- a/drivers/gpu/drm/i915/gt/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/intel_hangcheck.c
@@ -223,8 +223,8 @@ static void hangcheck_accumulate_sample(struct intel_engine_cs *engine,
}
static void hangcheck_declare_hang(struct drm_i915_private *i915,
- unsigned int hung,
- unsigned int stuck)
+ intel_engine_mask_t hung,
+ intel_engine_mask_t stuck)
{
struct intel_engine_cs *engine;
intel_engine_mask_t tmp;
@@ -259,9 +259,9 @@ static void i915_hangcheck_elapsed(struct work_struct *work)
struct drm_i915_private *dev_priv =
container_of(work, typeof(*dev_priv),
gpu_error.hangcheck_work.work);
+ intel_engine_mask_t hung = 0, stuck = 0, wedged = 0;
struct intel_engine_cs *engine;
enum intel_engine_id id;
- unsigned int hung = 0, stuck = 0, wedged = 0;
intel_wakeref_t wakeref;
if (!i915_modparams.enable_hangcheck)
--
2.20.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [CI 3/5] drm/i915: Make Gen6/7 RING_FAULT_REG access engine centric
2019-06-07 8:25 [CI 1/5] drm/i915: Reset only affected engines when handling error capture Tvrtko Ursulin
2019-06-07 8:25 ` [CI 2/5] drm/i915: Tidy engine mask types in hangcheck Tvrtko Ursulin
@ 2019-06-07 8:25 ` Tvrtko Ursulin
2019-06-07 9:09 ` [CI v2 3/8] " Tvrtko Ursulin
2019-06-07 10:15 ` [CI v3 3/5] " Tvrtko Ursulin
2019-06-07 8:25 ` [CI 4/5] drm/i915: Extract engine fault reset to a helper Tvrtko Ursulin
` (6 subsequent siblings)
8 siblings, 2 replies; 12+ messages in thread
From: Tvrtko Ursulin @ 2019-06-07 8:25 UTC (permalink / raw)
To: Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Similar to earlier conversions, eliminate the implicit dev_priv by
introducing some helpers which take the engine parameter (since the
register itself is per engine).
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_engine.h | 18 ++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_reset.c | 6 ++----
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
4 files changed, 22 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
index 1c0db151f0b1..a12b8ead4463 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -68,6 +68,24 @@ struct drm_printer;
#define ENGINE_WRITE(...) __ENGINE_WRITE_OP(write, __VA_ARGS__)
#define ENGINE_WRITE_FW(...) __ENGINE_WRITE_OP(write_fw, __VA_ARGS__)
+#define GEN6_RING_FAULT_REG_READ(engine__) \
+ intel_uncore_read((engine__)->uncore, RING_FAULT_REG(engine__))
+
+#define GEN6_RING_FAULT_REG_POSTING_READ(engine__) \
+ intel_uncore_posting_read((engine__)->uncore, RING_FAULT_REG(engine__))
+
+#define GEN6_RING_FAULT_REG_RMW(engine__, clear__, set__) \
+({ \
+ u32 __val; \
+\
+ __val = intel_uncore_read((engine__)->uncore, \
+ RING_FAULT_REG(engine__)); \
+ __val &= ~clear__; \
+ __val |= set__; \
+ intel_uncore_write((engine__)->uncore, RING_FAULT_REG(engine__), \
+ __val); \
+})
+
/* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
* do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
*/
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index 7bfb76eb0291..de53927c583f 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -1195,10 +1195,8 @@ void i915_clear_error_registers(struct drm_i915_private *i915,
enum intel_engine_id id;
for_each_engine_masked(engine, i915, engine_mask, id) {
- rmw_clear(uncore,
- RING_FAULT_REG(engine), RING_FAULT_VALID);
- intel_uncore_posting_read(uncore,
- RING_FAULT_REG(engine));
+ GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0);
+ GEN6_RING_FAULT_REG_POSTING_READ(engine);
}
}
}
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index c5a94396024f..c82d8e3ac9df 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2306,7 +2306,7 @@ static void gen6_check_faults(struct drm_i915_private *dev_priv)
u32 fault;
for_each_engine(engine, dev_priv, id) {
- fault = I915_READ(RING_FAULT_REG(engine));
+ fault = GEN6_RING_FAULT_REG_READ(engine);
if (fault & RING_FAULT_VALID) {
DRM_DEBUG_DRIVER("Unexpected fault\n"
"\tAddr: 0x%08lx\n"
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 707811256501..2f85de034d8f 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1149,7 +1149,7 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
if (INTEL_GEN(dev_priv) >= 8)
ee->fault_reg = I915_READ(GEN8_RING_FAULT_REG);
else
- ee->fault_reg = I915_READ(RING_FAULT_REG(engine));
+ ee->fault_reg = GEN6_RING_FAULT_REG_READ(engine);
}
if (INTEL_GEN(dev_priv) >= 4) {
--
2.20.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [CI 4/5] drm/i915: Extract engine fault reset to a helper
2019-06-07 8:25 [CI 1/5] drm/i915: Reset only affected engines when handling error capture Tvrtko Ursulin
2019-06-07 8:25 ` [CI 2/5] drm/i915: Tidy engine mask types in hangcheck Tvrtko Ursulin
2019-06-07 8:25 ` [CI 3/5] drm/i915: Make Gen6/7 RING_FAULT_REG access engine centric Tvrtko Ursulin
@ 2019-06-07 8:25 ` Tvrtko Ursulin
2019-06-07 8:25 ` [CI 5/5] drm/i915: Unexport i915_gem_init/fini_aliasing_ppgtt Tvrtko Ursulin
` (5 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Tvrtko Ursulin @ 2019-06-07 8:25 UTC (permalink / raw)
To: Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Just tidying the flow a bit.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_reset.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index de53927c583f..a6ecfdc735c4 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -1160,6 +1160,12 @@ static void clear_register(struct intel_uncore *uncore, i915_reg_t reg)
intel_uncore_rmw(uncore, reg, 0, 0);
}
+static void gen8_clear_engine_error_register(struct intel_engine_cs *engine)
+{
+ GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0);
+ GEN6_RING_FAULT_REG_POSTING_READ(engine);
+}
+
void i915_clear_error_registers(struct drm_i915_private *i915,
intel_engine_mask_t engine_mask)
{
@@ -1194,10 +1200,8 @@ void i915_clear_error_registers(struct drm_i915_private *i915,
struct intel_engine_cs *engine;
enum intel_engine_id id;
- for_each_engine_masked(engine, i915, engine_mask, id) {
- GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0);
- GEN6_RING_FAULT_REG_POSTING_READ(engine);
- }
+ for_each_engine_masked(engine, i915, engine_mask, id)
+ gen8_clear_engine_error_register(engine);
}
}
--
2.20.1
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* [CI 5/5] drm/i915: Unexport i915_gem_init/fini_aliasing_ppgtt
2019-06-07 8:25 [CI 1/5] drm/i915: Reset only affected engines when handling error capture Tvrtko Ursulin
` (2 preceding siblings ...)
2019-06-07 8:25 ` [CI 4/5] drm/i915: Extract engine fault reset to a helper Tvrtko Ursulin
@ 2019-06-07 8:25 ` Tvrtko Ursulin
2019-06-07 9:32 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/5] drm/i915: Reset only affected engines when handling error capture Patchwork
` (4 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Tvrtko Ursulin @ 2019-06-07 8:25 UTC (permalink / raw)
To: Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
These two are only used from within i915_gem_gtt.c and can trivially be
made static.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++++----
drivers/gpu/drm/i915/i915_gem_gtt.h | 3 ---
2 files changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index c82d8e3ac9df..550cf4b63586 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2814,7 +2814,7 @@ static void i915_gtt_color_adjust(const struct drm_mm_node *node,
*end -= I915_GTT_PAGE_SIZE;
}
-int i915_gem_init_aliasing_ppgtt(struct drm_i915_private *i915)
+static int init_aliasing_ppgtt(struct drm_i915_private *i915)
{
struct i915_ggtt *ggtt = &i915->ggtt;
struct i915_hw_ppgtt *ppgtt;
@@ -2854,7 +2854,7 @@ int i915_gem_init_aliasing_ppgtt(struct drm_i915_private *i915)
return err;
}
-void i915_gem_fini_aliasing_ppgtt(struct drm_i915_private *i915)
+static void fini_aliasing_ppgtt(struct drm_i915_private *i915)
{
struct i915_ggtt *ggtt = &i915->ggtt;
struct i915_hw_ppgtt *ppgtt;
@@ -2924,7 +2924,7 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
ggtt->vm.clear_range(&ggtt->vm, ggtt->vm.total - PAGE_SIZE, PAGE_SIZE);
if (INTEL_PPGTT(dev_priv) == INTEL_PPGTT_ALIASING) {
- ret = i915_gem_init_aliasing_ppgtt(dev_priv);
+ ret = init_aliasing_ppgtt(dev_priv);
if (ret)
goto err_appgtt;
}
@@ -2951,7 +2951,7 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv)
ggtt->vm.closed = true;
mutex_lock(&dev_priv->drm.struct_mutex);
- i915_gem_fini_aliasing_ppgtt(dev_priv);
+ fini_aliasing_ppgtt(dev_priv);
list_for_each_entry_safe(vma, vn, &ggtt->vm.bound_list, vm_link)
WARN_ON(i915_vma_unbind(vma));
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 152a03560c22..12856f9dd1d1 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -617,9 +617,6 @@ const struct intel_ppat_entry *
intel_ppat_get(struct drm_i915_private *i915, u8 value);
void intel_ppat_put(const struct intel_ppat_entry *entry);
-int i915_gem_init_aliasing_ppgtt(struct drm_i915_private *i915);
-void i915_gem_fini_aliasing_ppgtt(struct drm_i915_private *i915);
-
int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv);
int i915_ggtt_init_hw(struct drm_i915_private *dev_priv);
int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv);
--
2.20.1
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* [CI v2 3/8] drm/i915: Make Gen6/7 RING_FAULT_REG access engine centric
2019-06-07 8:25 ` [CI 3/5] drm/i915: Make Gen6/7 RING_FAULT_REG access engine centric Tvrtko Ursulin
@ 2019-06-07 9:09 ` Tvrtko Ursulin
2019-06-07 10:15 ` [CI v3 3/5] " Tvrtko Ursulin
1 sibling, 0 replies; 12+ messages in thread
From: Tvrtko Ursulin @ 2019-06-07 9:09 UTC (permalink / raw)
To: Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Similar to earlier conversions, eliminate the implicit dev_priv by
introducing some helpers which take the engine parameter (since the
register itself is per engine).
v2:
* Always use parentheses in macro arguments.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_engine.h | 18 ++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_reset.c | 6 ++----
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
4 files changed, 22 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
index 1c0db151f0b1..201bbd2a4faf 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -68,6 +68,24 @@ struct drm_printer;
#define ENGINE_WRITE(...) __ENGINE_WRITE_OP(write, __VA_ARGS__)
#define ENGINE_WRITE_FW(...) __ENGINE_WRITE_OP(write_fw, __VA_ARGS__)
+#define GEN6_RING_FAULT_REG_READ(engine__) \
+ intel_uncore_read((engine__)->uncore, RING_FAULT_REG(engine__))
+
+#define GEN6_RING_FAULT_REG_POSTING_READ(engine__) \
+ intel_uncore_posting_read((engine__)->uncore, RING_FAULT_REG(engine__))
+
+#define GEN6_RING_FAULT_REG_RMW(engine__, clear__, set__) \
+({ \
+ u32 __val; \
+\
+ __val = intel_uncore_read((engine__)->uncore, \
+ RING_FAULT_REG(engine__)); \
+ __val &= ~(clear__); \
+ __val |= (set__); \
+ intel_uncore_write((engine__)->uncore, RING_FAULT_REG(engine__), \
+ __val); \
+})
+
/* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
* do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
*/
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index 7bfb76eb0291..de53927c583f 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -1195,10 +1195,8 @@ void i915_clear_error_registers(struct drm_i915_private *i915,
enum intel_engine_id id;
for_each_engine_masked(engine, i915, engine_mask, id) {
- rmw_clear(uncore,
- RING_FAULT_REG(engine), RING_FAULT_VALID);
- intel_uncore_posting_read(uncore,
- RING_FAULT_REG(engine));
+ GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0);
+ GEN6_RING_FAULT_REG_POSTING_READ(engine);
}
}
}
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index c5a94396024f..c82d8e3ac9df 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2306,7 +2306,7 @@ static void gen6_check_faults(struct drm_i915_private *dev_priv)
u32 fault;
for_each_engine(engine, dev_priv, id) {
- fault = I915_READ(RING_FAULT_REG(engine));
+ fault = GEN6_RING_FAULT_REG_READ(engine);
if (fault & RING_FAULT_VALID) {
DRM_DEBUG_DRIVER("Unexpected fault\n"
"\tAddr: 0x%08lx\n"
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 707811256501..2f85de034d8f 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1149,7 +1149,7 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
if (INTEL_GEN(dev_priv) >= 8)
ee->fault_reg = I915_READ(GEN8_RING_FAULT_REG);
else
- ee->fault_reg = I915_READ(RING_FAULT_REG(engine));
+ ee->fault_reg = GEN6_RING_FAULT_REG_READ(engine);
}
if (INTEL_GEN(dev_priv) >= 4) {
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/5] drm/i915: Reset only affected engines when handling error capture
2019-06-07 8:25 [CI 1/5] drm/i915: Reset only affected engines when handling error capture Tvrtko Ursulin
` (3 preceding siblings ...)
2019-06-07 8:25 ` [CI 5/5] drm/i915: Unexport i915_gem_init/fini_aliasing_ppgtt Tvrtko Ursulin
@ 2019-06-07 9:32 ` Patchwork
2019-06-07 10:20 ` ✓ Fi.CI.BAT: success " Patchwork
` (3 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2019-06-07 9:32 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx
== Series Details ==
Series: series starting with [CI,1/5] drm/i915: Reset only affected engines when handling error capture
URL : https://patchwork.freedesktop.org/series/61758/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
9a057903722f drm/i915: Reset only affected engines when handling error capture
2467bef6dc38 drm/i915: Tidy engine mask types in hangcheck
e71b4d115e62 drm/i915: Make Gen6/7 RING_FAULT_REG access engine centric
-:21: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'engine__' - possible side-effects?
#21: FILE: drivers/gpu/drm/i915/gt/intel_engine.h:71:
+#define GEN6_RING_FAULT_REG_READ(engine__) \
+ intel_uncore_read((engine__)->uncore, RING_FAULT_REG(engine__))
-:24: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'engine__' - possible side-effects?
#24: FILE: drivers/gpu/drm/i915/gt/intel_engine.h:74:
+#define GEN6_RING_FAULT_REG_POSTING_READ(engine__) \
+ intel_uncore_posting_read((engine__)->uncore, RING_FAULT_REG(engine__))
-:27: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'engine__' - possible side-effects?
#27: FILE: drivers/gpu/drm/i915/gt/intel_engine.h:77:
+#define GEN6_RING_FAULT_REG_RMW(engine__, clear__, set__) \
+({ \
+ u32 __val; \
+\
+ __val = intel_uncore_read((engine__)->uncore, \
+ RING_FAULT_REG(engine__)); \
+ __val &= ~clear__; \
+ __val |= set__; \
+ intel_uncore_write((engine__)->uncore, RING_FAULT_REG(engine__), \
+ __val); \
+})
-:27: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'clear__' may be better as '(clear__)' to avoid precedence issues
#27: FILE: drivers/gpu/drm/i915/gt/intel_engine.h:77:
+#define GEN6_RING_FAULT_REG_RMW(engine__, clear__, set__) \
+({ \
+ u32 __val; \
+\
+ __val = intel_uncore_read((engine__)->uncore, \
+ RING_FAULT_REG(engine__)); \
+ __val &= ~clear__; \
+ __val |= set__; \
+ intel_uncore_write((engine__)->uncore, RING_FAULT_REG(engine__), \
+ __val); \
+})
total: 0 errors, 0 warnings, 4 checks, 52 lines checked
bcda7ed91c02 drm/i915: Extract engine fault reset to a helper
1390b7f7f35b drm/i915: Unexport i915_gem_init/fini_aliasing_ppgtt
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* [CI v3 3/5] drm/i915: Make Gen6/7 RING_FAULT_REG access engine centric
2019-06-07 8:25 ` [CI 3/5] drm/i915: Make Gen6/7 RING_FAULT_REG access engine centric Tvrtko Ursulin
2019-06-07 9:09 ` [CI v2 3/8] " Tvrtko Ursulin
@ 2019-06-07 10:15 ` Tvrtko Ursulin
1 sibling, 0 replies; 12+ messages in thread
From: Tvrtko Ursulin @ 2019-06-07 10:15 UTC (permalink / raw)
To: Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Similar to earlier conversions, eliminate the implicit dev_priv by
introducing some helpers which take the engine parameter (since the
register itself is per engine).
v2:
* Always use parentheses in macro arguments.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_engine.h | 18 ++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_reset.c | 6 ++----
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
4 files changed, 22 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
index 1c0db151f0b1..201bbd2a4faf 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -68,6 +68,24 @@ struct drm_printer;
#define ENGINE_WRITE(...) __ENGINE_WRITE_OP(write, __VA_ARGS__)
#define ENGINE_WRITE_FW(...) __ENGINE_WRITE_OP(write_fw, __VA_ARGS__)
+#define GEN6_RING_FAULT_REG_READ(engine__) \
+ intel_uncore_read((engine__)->uncore, RING_FAULT_REG(engine__))
+
+#define GEN6_RING_FAULT_REG_POSTING_READ(engine__) \
+ intel_uncore_posting_read((engine__)->uncore, RING_FAULT_REG(engine__))
+
+#define GEN6_RING_FAULT_REG_RMW(engine__, clear__, set__) \
+({ \
+ u32 __val; \
+\
+ __val = intel_uncore_read((engine__)->uncore, \
+ RING_FAULT_REG(engine__)); \
+ __val &= ~(clear__); \
+ __val |= (set__); \
+ intel_uncore_write((engine__)->uncore, RING_FAULT_REG(engine__), \
+ __val); \
+})
+
/* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
* do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
*/
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index 7bfb76eb0291..de53927c583f 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -1195,10 +1195,8 @@ void i915_clear_error_registers(struct drm_i915_private *i915,
enum intel_engine_id id;
for_each_engine_masked(engine, i915, engine_mask, id) {
- rmw_clear(uncore,
- RING_FAULT_REG(engine), RING_FAULT_VALID);
- intel_uncore_posting_read(uncore,
- RING_FAULT_REG(engine));
+ GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0);
+ GEN6_RING_FAULT_REG_POSTING_READ(engine);
}
}
}
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index c5a94396024f..c82d8e3ac9df 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2306,7 +2306,7 @@ static void gen6_check_faults(struct drm_i915_private *dev_priv)
u32 fault;
for_each_engine(engine, dev_priv, id) {
- fault = I915_READ(RING_FAULT_REG(engine));
+ fault = GEN6_RING_FAULT_REG_READ(engine);
if (fault & RING_FAULT_VALID) {
DRM_DEBUG_DRIVER("Unexpected fault\n"
"\tAddr: 0x%08lx\n"
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 707811256501..2f85de034d8f 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1149,7 +1149,7 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
if (INTEL_GEN(dev_priv) >= 8)
ee->fault_reg = I915_READ(GEN8_RING_FAULT_REG);
else
- ee->fault_reg = I915_READ(RING_FAULT_REG(engine));
+ ee->fault_reg = GEN6_RING_FAULT_REG_READ(engine);
}
if (INTEL_GEN(dev_priv) >= 4) {
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [CI,1/5] drm/i915: Reset only affected engines when handling error capture
2019-06-07 8:25 [CI 1/5] drm/i915: Reset only affected engines when handling error capture Tvrtko Ursulin
` (4 preceding siblings ...)
2019-06-07 9:32 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/5] drm/i915: Reset only affected engines when handling error capture Patchwork
@ 2019-06-07 10:20 ` Patchwork
2019-06-07 10:41 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/5] drm/i915: Reset only affected engines when handling error capture (rev3) Patchwork
` (2 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2019-06-07 10:20 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx
== Series Details ==
Series: series starting with [CI,1/5] drm/i915: Reset only affected engines when handling error capture
URL : https://patchwork.freedesktop.org/series/61758/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6216 -> Patchwork_13199
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13199/
Known issues
------------
Here are the changes found in Patchwork_13199 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s4-devices:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6216/fi-icl-u3/igt@gem_exec_suspend@basic-s4-devices.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13199/fi-icl-u3/igt@gem_exec_suspend@basic-s4-devices.html
* igt@gem_workarounds@basic-read:
- fi-icl-dsi: [PASS][3] -> [DMESG-WARN][4] ([fdo#106107])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6216/fi-icl-dsi/igt@gem_workarounds@basic-read.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13199/fi-icl-dsi/igt@gem_workarounds@basic-read.html
#### Possible fixes ####
* igt@gem_close_race@basic-process:
- fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6216/fi-icl-u3/igt@gem_close_race@basic-process.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13199/fi-icl-u3/igt@gem_close_race@basic-process.html
* igt@gem_ctx_create@basic-files:
- fi-icl-y: [INCOMPLETE][7] ([fdo#107713] / [fdo#109100]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6216/fi-icl-y/igt@gem_ctx_create@basic-files.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13199/fi-icl-y/igt@gem_ctx_create@basic-files.html
* igt@gem_exec_basic@basic-all:
- fi-cml-u2: [INCOMPLETE][9] ([fdo#110566]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6216/fi-cml-u2/igt@gem_exec_basic@basic-all.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13199/fi-cml-u2/igt@gem_exec_basic@basic-all.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109831]: https://bugs.freedesktop.org/show_bug.cgi?id=109831
[fdo#109964]: https://bugs.freedesktop.org/show_bug.cgi?id=109964
[fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566
Participating hosts (54 -> 45)
------------------------------
Missing (9): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-icl-u2 fi-bsw-cyan fi-pnv-d510 fi-icl-guc fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_6216 -> Patchwork_13199
CI_DRM_6216: e58a2b1f565ec5d77c69724d2f43a7de6f7953b3 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5047: 3f4b1a49ed5e1c77ea42970d4d3156c997f66050 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13199: 1390b7f7f35b560c5e3b7eaf0a6bbe7a150ea124 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
1390b7f7f35b drm/i915: Unexport i915_gem_init/fini_aliasing_ppgtt
bcda7ed91c02 drm/i915: Extract engine fault reset to a helper
e71b4d115e62 drm/i915: Make Gen6/7 RING_FAULT_REG access engine centric
2467bef6dc38 drm/i915: Tidy engine mask types in hangcheck
9a057903722f drm/i915: Reset only affected engines when handling error capture
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13199/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/5] drm/i915: Reset only affected engines when handling error capture (rev3)
2019-06-07 8:25 [CI 1/5] drm/i915: Reset only affected engines when handling error capture Tvrtko Ursulin
` (5 preceding siblings ...)
2019-06-07 10:20 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-06-07 10:41 ` Patchwork
2019-06-07 11:04 ` ✓ Fi.CI.BAT: success " Patchwork
2019-06-09 18:41 ` ✗ Fi.CI.IGT: failure " Patchwork
8 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2019-06-07 10:41 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx
== Series Details ==
Series: series starting with [CI,1/5] drm/i915: Reset only affected engines when handling error capture (rev3)
URL : https://patchwork.freedesktop.org/series/61758/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0bcf26ea6446 drm/i915: Reset only affected engines when handling error capture
07ef2aa03eb8 drm/i915: Tidy engine mask types in hangcheck
8a1a473386ac drm/i915: Make Gen6/7 RING_FAULT_REG access engine centric
-:24: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'engine__' - possible side-effects?
#24: FILE: drivers/gpu/drm/i915/gt/intel_engine.h:71:
+#define GEN6_RING_FAULT_REG_READ(engine__) \
+ intel_uncore_read((engine__)->uncore, RING_FAULT_REG(engine__))
-:27: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'engine__' - possible side-effects?
#27: FILE: drivers/gpu/drm/i915/gt/intel_engine.h:74:
+#define GEN6_RING_FAULT_REG_POSTING_READ(engine__) \
+ intel_uncore_posting_read((engine__)->uncore, RING_FAULT_REG(engine__))
-:30: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'engine__' - possible side-effects?
#30: FILE: drivers/gpu/drm/i915/gt/intel_engine.h:77:
+#define GEN6_RING_FAULT_REG_RMW(engine__, clear__, set__) \
+({ \
+ u32 __val; \
+\
+ __val = intel_uncore_read((engine__)->uncore, \
+ RING_FAULT_REG(engine__)); \
+ __val &= ~(clear__); \
+ __val |= (set__); \
+ intel_uncore_write((engine__)->uncore, RING_FAULT_REG(engine__), \
+ __val); \
+})
total: 0 errors, 0 warnings, 3 checks, 52 lines checked
4f51349b0547 drm/i915: Extract engine fault reset to a helper
5b834e860f03 drm/i915: Unexport i915_gem_init/fini_aliasing_ppgtt
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [CI,1/5] drm/i915: Reset only affected engines when handling error capture (rev3)
2019-06-07 8:25 [CI 1/5] drm/i915: Reset only affected engines when handling error capture Tvrtko Ursulin
` (6 preceding siblings ...)
2019-06-07 10:41 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/5] drm/i915: Reset only affected engines when handling error capture (rev3) Patchwork
@ 2019-06-07 11:04 ` Patchwork
2019-06-09 18:41 ` ✗ Fi.CI.IGT: failure " Patchwork
8 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2019-06-07 11:04 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx
== Series Details ==
Series: series starting with [CI,1/5] drm/i915: Reset only affected engines when handling error capture (rev3)
URL : https://patchwork.freedesktop.org/series/61758/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6216 -> Patchwork_13202
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13202/
Known issues
------------
Here are the changes found in Patchwork_13202 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s3:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6216/fi-icl-u3/igt@gem_exec_suspend@basic-s3.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13202/fi-icl-u3/igt@gem_exec_suspend@basic-s3.html
* igt@gem_exec_suspend@basic-s4-devices:
- fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] ([fdo#107718])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6216/fi-blb-e6850/igt@gem_exec_suspend@basic-s4-devices.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13202/fi-blb-e6850/igt@gem_exec_suspend@basic-s4-devices.html
* igt@i915_module_load@reload-with-fault-injection:
- fi-snb-2600: [PASS][5] -> [INCOMPLETE][6] ([fdo#105411])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6216/fi-snb-2600/igt@i915_module_load@reload-with-fault-injection.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13202/fi-snb-2600/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_selftest@live_contexts:
- fi-skl-gvtdvm: [PASS][7] -> [DMESG-FAIL][8] ([fdo#110235])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6216/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13202/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-dsi: [PASS][9] -> [DMESG-WARN][10] ([fdo#106107])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6216/fi-icl-dsi/igt@kms_frontbuffer_tracking@basic.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13202/fi-icl-dsi/igt@kms_frontbuffer_tracking@basic.html
#### Possible fixes ####
* igt@gem_close_race@basic-process:
- fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6216/fi-icl-u3/igt@gem_close_race@basic-process.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13202/fi-icl-u3/igt@gem_close_race@basic-process.html
* igt@gem_ctx_create@basic-files:
- fi-icl-u2: [INCOMPLETE][13] ([fdo#107713] / [fdo#109100]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6216/fi-icl-u2/igt@gem_ctx_create@basic-files.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13202/fi-icl-u2/igt@gem_ctx_create@basic-files.html
- fi-icl-y: [INCOMPLETE][15] ([fdo#107713] / [fdo#109100]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6216/fi-icl-y/igt@gem_ctx_create@basic-files.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13202/fi-icl-y/igt@gem_ctx_create@basic-files.html
* igt@gem_exec_basic@basic-all:
- fi-cml-u2: [INCOMPLETE][17] ([fdo#110566]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6216/fi-cml-u2/igt@gem_exec_basic@basic-all.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13202/fi-cml-u2/igt@gem_exec_basic@basic-all.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [DMESG-WARN][19] ([fdo#102614]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6216/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13202/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#110235]: https://bugs.freedesktop.org/show_bug.cgi?id=110235
[fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566
Participating hosts (54 -> 48)
------------------------------
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_6216 -> Patchwork_13202
CI_DRM_6216: e58a2b1f565ec5d77c69724d2f43a7de6f7953b3 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5047: 3f4b1a49ed5e1c77ea42970d4d3156c997f66050 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13202: 5b834e860f03f7fd2163f374fb441f0330167ab1 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
5b834e860f03 drm/i915: Unexport i915_gem_init/fini_aliasing_ppgtt
4f51349b0547 drm/i915: Extract engine fault reset to a helper
8a1a473386ac drm/i915: Make Gen6/7 RING_FAULT_REG access engine centric
07ef2aa03eb8 drm/i915: Tidy engine mask types in hangcheck
0bcf26ea6446 drm/i915: Reset only affected engines when handling error capture
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13202/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* ✗ Fi.CI.IGT: failure for series starting with [CI,1/5] drm/i915: Reset only affected engines when handling error capture (rev3)
2019-06-07 8:25 [CI 1/5] drm/i915: Reset only affected engines when handling error capture Tvrtko Ursulin
` (7 preceding siblings ...)
2019-06-07 11:04 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-06-09 18:41 ` Patchwork
8 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2019-06-09 18:41 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx
== Series Details ==
Series: series starting with [CI,1/5] drm/i915: Reset only affected engines when handling error capture (rev3)
URL : https://patchwork.freedesktop.org/series/61758/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6216_full -> Patchwork_13202_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_13202_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_13202_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_13202_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_ctx_engines@execute-one:
- shard-glk: NOTRUN -> [DMESG-WARN][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13202/shard-glk9/igt@gem_ctx_engines@execute-one.html
Known issues
------------
Here are the changes found in Patchwork_13202_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_rc6_residency@rc6-accuracy:
- shard-kbl: [PASS][2] -> [SKIP][3] ([fdo#109271])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6216/shard-kbl7/igt@i915_pm_rc6_residency@rc6-accuracy.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13202/shard-kbl2/igt@i915_pm_rc6_residency@rc6-accuracy.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-iclb: [PASS][4] -> [INCOMPLETE][5] ([fdo#107713])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6216/shard-iclb2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13202/shard-iclb3/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size:
- shard-glk: [PASS][6] -> [INCOMPLETE][7] ([fdo#103359] / [k.org#198133])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6216/shard-glk9/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13202/shard-glk2/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-render:
- shard-iclb: [PASS][8] -> [FAIL][9] ([fdo#103167])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6216/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-render.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13202/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-render.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [PASS][10] -> [FAIL][11] ([fdo#108145])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6216/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13202/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: [PASS][12] -> [FAIL][13] ([fdo#103166]) +1 similar issue
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6216/shard-iclb3/igt@kms_plane_lowres@pipe-a-tiling-x.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13202/shard-iclb8/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_psr@psr2_sprite_blt:
- shard-iclb: [PASS][14] -> [SKIP][15] ([fdo#109441])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6216/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13202/shard-iclb1/igt@kms_psr@psr2_sprite_blt.html
* igt@kms_sysfs_edid_timing:
- shard-iclb: [PASS][16] -> [FAIL][17] ([fdo#100047])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6216/shard-iclb5/igt@kms_sysfs_edid_timing.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13202/shard-iclb3/igt@kms_sysfs_edid_timing.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: [PASS][18] -> [DMESG-WARN][19] ([fdo#108566]) +3 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6216/shard-apl3/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13202/shard-apl3/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
- shard-skl: [PASS][20] -> [INCOMPLETE][21] ([fdo#104108])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6216/shard-skl5/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13202/shard-skl4/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
#### Possible fixes ####
* igt@gem_ctx_engines@execute-one:
- shard-skl: [DMESG-WARN][22] -> [PASS][23]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6216/shard-skl1/igt@gem_ctx_engines@execute-one.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13202/shard-skl8/igt@gem_ctx_engines@execute-one.html
* igt@gem_ctx_isolation@rcs0-s3:
- shard-iclb: [INCOMPLETE][24] ([fdo#107713] / [fdo#109100]) -> [PASS][25]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6216/shard-iclb7/igt@gem_ctx_isolation@rcs0-s3.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13202/shard-iclb8/igt@gem_ctx_isolation@rcs0-s3.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-skl: [INCOMPLETE][26] ([fdo#104108]) -> [PASS][27]
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6216/shard-skl1/igt@gem_workarounds@suspend-resume-fd.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13202/shard-skl1/igt@gem_workarounds@suspend-resume-fd.html
* igt@kms_cursor_crc@pipe-b-cursor-64x64-sliding:
- shard-skl: [FAIL][28] ([fdo#103232]) -> [PASS][29]
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6216/shard-skl9/igt@kms_cursor_crc@pipe-b-cursor-64x64-sliding.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13202/shard-skl9/igt@kms_cursor_crc@pipe-b-cursor-64x64-sliding.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-apl: [DMESG-WARN][30] ([fdo#108566]) -> [PASS][31] +2 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6216/shard-apl1/igt@kms_frontbuffer_tracking@fbc-suspend.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13202/shard-apl7/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite:
- shard-iclb: [FAIL][32] ([fdo#103167]) -> [PASS][33] +4 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6216/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13202/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [FAIL][34] ([fdo#108145]) -> [PASS][35]
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6216/shard-skl8/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13202/shard-skl3/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [FAIL][36] ([fdo#108145] / [fdo#110403]) -> [PASS][37]
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6216/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13202/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_setmode@basic:
- shard-apl: [FAIL][38] ([fdo#99912]) -> [PASS][39]
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6216/shard-apl4/igt@kms_setmode@basic.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13202/shard-apl6/igt@kms_setmode@basic.html
- shard-skl: [FAIL][40] ([fdo#99912]) -> [PASS][41]
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6216/shard-skl3/igt@kms_setmode@basic.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13202/shard-skl4/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-c-query-idle-hang:
- shard-iclb: [INCOMPLETE][42] ([fdo#107713]) -> [PASS][43]
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6216/shard-iclb1/igt@kms_vblank@pipe-c-query-idle-hang.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13202/shard-iclb6/igt@kms_vblank@pipe-c-query-idle-hang.html
#### Warnings ####
* igt@gem_mmap_gtt@forked-big-copy-odd:
- shard-iclb: [INCOMPLETE][44] ([fdo#107713] / [fdo#109100]) -> [TIMEOUT][45] ([fdo#109673])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6216/shard-iclb5/igt@gem_mmap_gtt@forked-big-copy-odd.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13202/shard-iclb3/igt@gem_mmap_gtt@forked-big-copy-odd.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109673]: https://bugs.freedesktop.org/show_bug.cgi?id=109673
[fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
[fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_6216 -> Patchwork_13202
CI_DRM_6216: e58a2b1f565ec5d77c69724d2f43a7de6f7953b3 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5047: 3f4b1a49ed5e1c77ea42970d4d3156c997f66050 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13202: 5b834e860f03f7fd2163f374fb441f0330167ab1 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13202/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2019-06-09 18:41 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-06-07 8:25 [CI 1/5] drm/i915: Reset only affected engines when handling error capture Tvrtko Ursulin
2019-06-07 8:25 ` [CI 2/5] drm/i915: Tidy engine mask types in hangcheck Tvrtko Ursulin
2019-06-07 8:25 ` [CI 3/5] drm/i915: Make Gen6/7 RING_FAULT_REG access engine centric Tvrtko Ursulin
2019-06-07 9:09 ` [CI v2 3/8] " Tvrtko Ursulin
2019-06-07 10:15 ` [CI v3 3/5] " Tvrtko Ursulin
2019-06-07 8:25 ` [CI 4/5] drm/i915: Extract engine fault reset to a helper Tvrtko Ursulin
2019-06-07 8:25 ` [CI 5/5] drm/i915: Unexport i915_gem_init/fini_aliasing_ppgtt Tvrtko Ursulin
2019-06-07 9:32 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/5] drm/i915: Reset only affected engines when handling error capture Patchwork
2019-06-07 10:20 ` ✓ Fi.CI.BAT: success " Patchwork
2019-06-07 10:41 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/5] drm/i915: Reset only affected engines when handling error capture (rev3) Patchwork
2019-06-07 11:04 ` ✓ Fi.CI.BAT: success " Patchwork
2019-06-09 18:41 ` ✗ Fi.CI.IGT: failure " Patchwork
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