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* [OpenRISC] [PATCH v3 10/11] sim/testsuite/or1k: Add test case for l.adrp instruction
@ 2019-06-10 20:49 Stafford Horne
  2019-06-10 20:49 ` [OpenRISC] [PATCH v3 11/11] sim/testsuite/or1k: Add tests for unordered compares Stafford Horne
  2019-06-11 21:48 ` [OpenRISC] [PATCH v3 10/11] sim/testsuite/or1k: Add test case for l.adrp instruction Andrew Burgess
  0 siblings, 2 replies; 6+ messages in thread
From: Stafford Horne @ 2019-06-10 20:49 UTC (permalink / raw)
  To: openrisc

This is a simple test to ensure that the l.adrp instruction can be assembled and
simulated correctly.

sim/testsuite/sim/or1k/ChangeLog:

yyyy-mm-dd  Stafford Horne  <shorne@gmail.com>

	* adrp.S: New file.
---
Changes since v2:
 - new patch

 sim/testsuite/sim/or1k/adrp.S | 73 +++++++++++++++++++++++++++++++++++
 1 file changed, 73 insertions(+)
 create mode 100644 sim/testsuite/sim/or1k/adrp.S

diff --git a/sim/testsuite/sim/or1k/adrp.S b/sim/testsuite/sim/or1k/adrp.S
new file mode 100644
index 0000000000..ba384ccc84
--- /dev/null
+++ b/sim/testsuite/sim/or1k/adrp.S
@@ -0,0 +1,73 @@
+/* Tests the load page address instruction.
+
+   Copyright (C) 2017-2019 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+# mach: or1k
+# output: report(0x00002064);\n
+# output: report(0x00012138);\n
+# output: report(0x00002000);\n
+# output: report(0x00012000);\n
+# output: report(0x00002000);\n
+# output: report(0x00014000);\n
+# output: report(0x00000000);\n
+# output: exit(0)\n
+
+#include "or1k-asm-test-helpers.h"
+
+	STANDARD_TEST_ENVIRONMENT
+
+	.section .data
+	.org 0x10000
+	.align 4
+	.type   pi, @object
+	.size   pi, 4
+pi:
+	.float	3.14159
+
+	.section .text
+start_tests:
+	PUSH LINK_REGISTER_R9
+
+	/* Print out the PC.  To compare with that loaded by l.adrp.  */
+	l.jal	capture_pc
+	 l.nop
+capture_pc:
+	REPORT_REG_TO_CONSOLE r9
+
+	/* Print out our data address to compared with l.adrp offset.  */
+	l.movhi	r11, ha(pi)
+	l.addi	r11, r11, lo(pi)
+	REPORT_REG_TO_CONSOLE r11
+
+	/* Test l.adrp with symbols, loads page of symbol to register.  */
+	l.adrp	r4, start_tests
+	REPORT_REG_TO_CONSOLE r4
+
+	l.adrp	r4, pi
+	REPORT_REG_TO_CONSOLE r4
+
+	/* Test l.adrp with immediate, immediate is the page offset.  */
+	l.adrp	r4, 0x0
+	REPORT_REG_TO_CONSOLE r4
+
+	l.adrp	r4, 0x12000
+	REPORT_REG_TO_CONSOLE r4
+
+	l.adrp	r4, -0x2000
+	REPORT_REG_TO_CONSOLE r4
+
+	POP LINK_REGISTER_R9
+	RETURN_TO_LINK_REGISTER_R9
-- 
2.21.0


^ permalink raw reply related	[flat|nested] 6+ messages in thread

* [OpenRISC] [PATCH v3 11/11] sim/testsuite/or1k: Add tests for unordered compares
  2019-06-10 20:49 [OpenRISC] [PATCH v3 10/11] sim/testsuite/or1k: Add test case for l.adrp instruction Stafford Horne
@ 2019-06-10 20:49 ` Stafford Horne
  2019-06-11 21:49   ` Andrew Burgess
  2019-06-11 21:48 ` [OpenRISC] [PATCH v3 10/11] sim/testsuite/or1k: Add test case for l.adrp instruction Andrew Burgess
  1 sibling, 1 reply; 6+ messages in thread
From: Stafford Horne @ 2019-06-10 20:49 UTC (permalink / raw)
  To: openrisc

Add tests for 32-bit and 64-bit unordered compare instructions.

sim/testsuite/sim/or1k/ChangeLog:

yyyy-mm-dd  Stafford Horne  <shorne@gmail.com>

	* fpu-unordered.S: New file.
	* fpu64a32-unordered.S: New file.
---
Changes since v2:
 - new patch

 sim/testsuite/sim/or1k/fpu-unordered.S      |  97 +++++++++++++++++++
 sim/testsuite/sim/or1k/fpu64a32-unordered.S | 100 ++++++++++++++++++++
 2 files changed, 197 insertions(+)
 create mode 100644 sim/testsuite/sim/or1k/fpu-unordered.S
 create mode 100644 sim/testsuite/sim/or1k/fpu64a32-unordered.S

diff --git a/sim/testsuite/sim/or1k/fpu-unordered.S b/sim/testsuite/sim/or1k/fpu-unordered.S
new file mode 100644
index 0000000000..bf229878bb
--- /dev/null
+++ b/sim/testsuite/sim/or1k/fpu-unordered.S
@@ -0,0 +1,97 @@
+/* Tests some basic unordered fpu compare instructions.
+
+   Copyright (C) 2017-2019 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+# mach: or1k
+# output: report(0x40490fd0);\n
+# output: report(0x402df84d);\n
+# output: report(0x7fc00000);\n
+# output: \n
+# output: report(0x00000001);\n
+# output: \n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x00000001);\n
+# output: \n
+# output: report(0x00000001);\n
+# output: \n
+# output: exit(0)\n
+
+#include "or1k-asm-test-helpers.h"
+
+	STANDARD_TEST_ENVIRONMENT
+
+	.section .data
+	.align 4
+	.type   pi, @object
+	.size   pi, 4
+anchor:
+pi:
+	.float  3.14159
+
+	.type   e, @object
+	.size   e, 4
+e:
+	.float  2.71828
+
+	.section .text
+start_tests:
+	PUSH LINK_REGISTER_R9
+
+	/* Test unordered float comparisons.  Setting up:
+	 *  r11      pointer to data
+	 *  r12  pi  as float
+	 *  r13  e   as float
+	 *  r16  nan as float
+	 */
+	l.ori	r11, r0, ha(anchor)
+	l.addi	r11, r11, lo(anchor)
+	l.lwz	r12, 0(r11)
+
+	l.lwz	r13, 4(r11)
+
+	/* Make a NaN.  */
+	lf.sub.s r16, r13, r13
+	lf.div.s r16, r16, r16
+
+	/* Output to ensure we loaded it correctly.  */
+	REPORT_REG_TO_CONSOLE r12
+	REPORT_REG_TO_CONSOLE r13
+	REPORT_REG_TO_CONSOLE r16
+	PRINT_NEWLINE_TO_CONSOLE
+
+	lf.sfuge.s r12, r13
+	MOVE_FROM_SPR r2, SPR_SR
+	REPORT_BIT_TO_CONSOLE r2, SPR_SR_F
+	PRINT_NEWLINE_TO_CONSOLE
+
+	lf.sfun.s r12, r13
+	MOVE_FROM_SPR r2, SPR_SR
+	REPORT_BIT_TO_CONSOLE r2, SPR_SR_F
+	PRINT_NEWLINE_TO_CONSOLE
+
+	lf.sfun.s r12, r16
+	MOVE_FROM_SPR r2, SPR_SR
+	REPORT_BIT_TO_CONSOLE r2, SPR_SR_F
+	PRINT_NEWLINE_TO_CONSOLE
+
+	lf.sfueq.s r12, r12
+	MOVE_FROM_SPR r2, SPR_SR
+	REPORT_BIT_TO_CONSOLE r2, SPR_SR_F
+	PRINT_NEWLINE_TO_CONSOLE
+
+	POP LINK_REGISTER_R9
+	RETURN_TO_LINK_REGISTER_R9
diff --git a/sim/testsuite/sim/or1k/fpu64a32-unordered.S b/sim/testsuite/sim/or1k/fpu64a32-unordered.S
new file mode 100644
index 0000000000..31c9ee4a33
--- /dev/null
+++ b/sim/testsuite/sim/or1k/fpu64a32-unordered.S
@@ -0,0 +1,100 @@
+/* Tests some basic unordered fpu compare instructions.
+
+   Copyright (C) 2017-2019 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+# mach: or1k
+# output: report(0x400921f9);\n
+# output: report(0xf01b866e);\n
+# output: report(0x4005bf09);\n
+# output: report(0x95aaf790);\n
+# output: report(0x7ff80000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x00000001);\n
+# output: \n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x00000001);\n
+# output: \n
+# output: exit(0)\n
+
+#include "or1k-asm-test-helpers.h"
+
+	STANDARD_TEST_ENVIRONMENT
+
+	.section .data
+	.align 4
+	.type   pi, @object
+	.size   pi, 8
+anchor:
+pi:
+	.double  3.14159
+
+	.type   e, @object
+	.size   e, 8
+e:
+	.double  2.71828
+
+	.section .text
+start_tests:
+	PUSH LINK_REGISTER_R9
+
+	/* Test unordered double comparisons.  Setting up:
+	 *  r11      pointer to data
+	 *  r12,r13  pi  as double
+	 *  r14,r15  e   as double
+	 *  r16,r17  nan as double
+	 */
+	l.ori	r11, r0, ha(anchor)
+	l.addi	r11, r11, lo(anchor)
+	l.lwz	r12, 0(r11)
+	l.lwz	r13, 4(r11)
+
+	l.lwz	r14, 8(r11)
+	l.lwz	r15, 12(r11)
+
+	/* Make a NaN.  */
+	lf.sub.d r16,r18, r12,r13, r12,r13
+	lf.div.d r16,r18, r16,r18, r16,r18
+
+	/* Output to ensure we loaded it correctly.  */
+	REPORT_REG_TO_CONSOLE r12
+	REPORT_REG_TO_CONSOLE r13
+
+	REPORT_REG_TO_CONSOLE r14
+	REPORT_REG_TO_CONSOLE r15
+
+	REPORT_REG_TO_CONSOLE r16
+	REPORT_REG_TO_CONSOLE r18
+	PRINT_NEWLINE_TO_CONSOLE
+
+	lf.sfuge.d r12,r13, r14,r15
+	MOVE_FROM_SPR r2, SPR_SR
+	REPORT_BIT_TO_CONSOLE r2, SPR_SR_F
+	PRINT_NEWLINE_TO_CONSOLE
+
+	lf.sfun.d r12,r13, r14,r15
+	MOVE_FROM_SPR r2, SPR_SR
+	REPORT_BIT_TO_CONSOLE r2, SPR_SR_F
+	PRINT_NEWLINE_TO_CONSOLE
+
+	lf.sfun.d r12,r13, r16,r18
+	MOVE_FROM_SPR r2, SPR_SR
+	REPORT_BIT_TO_CONSOLE r2, SPR_SR_F
+	PRINT_NEWLINE_TO_CONSOLE
+
+	POP LINK_REGISTER_R9
+	RETURN_TO_LINK_REGISTER_R9
-- 
2.21.0


^ permalink raw reply related	[flat|nested] 6+ messages in thread

* [OpenRISC] [PATCH v3 10/11] sim/testsuite/or1k: Add test case for l.adrp instruction
  2019-06-10 20:49 [OpenRISC] [PATCH v3 10/11] sim/testsuite/or1k: Add test case for l.adrp instruction Stafford Horne
  2019-06-10 20:49 ` [OpenRISC] [PATCH v3 11/11] sim/testsuite/or1k: Add tests for unordered compares Stafford Horne
@ 2019-06-11 21:48 ` Andrew Burgess
  2019-06-12 13:09   ` Stafford Horne
  1 sibling, 1 reply; 6+ messages in thread
From: Andrew Burgess @ 2019-06-11 21:48 UTC (permalink / raw)
  To: openrisc

* Stafford Horne <shorne@gmail.com> [2019-06-11 05:49:39 +0900]:

> This is a simple test to ensure that the l.adrp instruction can be assembled and
> simulated correctly.
> 
> sim/testsuite/sim/or1k/ChangeLog:
> 
> yyyy-mm-dd  Stafford Horne  <shorne@gmail.com>
> 
> 	* adrp.S: New file.

This is fine with one nit below.

Thanks,
Andrew


> ---
> Changes since v2:
>  - new patch
> 
>  sim/testsuite/sim/or1k/adrp.S | 73 +++++++++++++++++++++++++++++++++++
>  1 file changed, 73 insertions(+)
>  create mode 100644 sim/testsuite/sim/or1k/adrp.S
> 
> diff --git a/sim/testsuite/sim/or1k/adrp.S b/sim/testsuite/sim/or1k/adrp.S
> new file mode 100644
> index 0000000000..ba384ccc84
> --- /dev/null
> +++ b/sim/testsuite/sim/or1k/adrp.S
> @@ -0,0 +1,73 @@
> +/* Tests the load page address instruction.
> +
> +   Copyright (C) 2017-2019 Free Software Foundation, Inc.

This date range should just be '2019'.

> +
> +   This program is free software; you can redistribute it and/or modify
> +   it under the terms of the GNU General Public License as published by
> +   the Free Software Foundation; either version 3 of the License, or
> +   (at your option) any later version.
> +
> +   This program is distributed in the hope that it will be useful,
> +   but WITHOUT ANY WARRANTY; without even the implied warranty of
> +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +   GNU General Public License for more details.
> +
> +   You should have received a copy of the GNU General Public License
> +   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
> +
> +# mach: or1k
> +# output: report(0x00002064);\n
> +# output: report(0x00012138);\n
> +# output: report(0x00002000);\n
> +# output: report(0x00012000);\n
> +# output: report(0x00002000);\n
> +# output: report(0x00014000);\n
> +# output: report(0x00000000);\n
> +# output: exit(0)\n
> +
> +#include "or1k-asm-test-helpers.h"
> +
> +	STANDARD_TEST_ENVIRONMENT
> +
> +	.section .data
> +	.org 0x10000
> +	.align 4
> +	.type   pi, @object
> +	.size   pi, 4
> +pi:
> +	.float	3.14159
> +
> +	.section .text
> +start_tests:
> +	PUSH LINK_REGISTER_R9
> +
> +	/* Print out the PC.  To compare with that loaded by l.adrp.  */
> +	l.jal	capture_pc
> +	 l.nop
> +capture_pc:
> +	REPORT_REG_TO_CONSOLE r9
> +
> +	/* Print out our data address to compared with l.adrp offset.  */
> +	l.movhi	r11, ha(pi)
> +	l.addi	r11, r11, lo(pi)
> +	REPORT_REG_TO_CONSOLE r11
> +
> +	/* Test l.adrp with symbols, loads page of symbol to register.  */
> +	l.adrp	r4, start_tests
> +	REPORT_REG_TO_CONSOLE r4
> +
> +	l.adrp	r4, pi
> +	REPORT_REG_TO_CONSOLE r4
> +
> +	/* Test l.adrp with immediate, immediate is the page offset.  */
> +	l.adrp	r4, 0x0
> +	REPORT_REG_TO_CONSOLE r4
> +
> +	l.adrp	r4, 0x12000
> +	REPORT_REG_TO_CONSOLE r4
> +
> +	l.adrp	r4, -0x2000
> +	REPORT_REG_TO_CONSOLE r4
> +
> +	POP LINK_REGISTER_R9
> +	RETURN_TO_LINK_REGISTER_R9
> -- 
> 2.21.0
> 

^ permalink raw reply	[flat|nested] 6+ messages in thread

* [OpenRISC] [PATCH v3 11/11] sim/testsuite/or1k: Add tests for unordered compares
  2019-06-10 20:49 ` [OpenRISC] [PATCH v3 11/11] sim/testsuite/or1k: Add tests for unordered compares Stafford Horne
@ 2019-06-11 21:49   ` Andrew Burgess
  2019-06-12 13:11     ` Stafford Horne
  0 siblings, 1 reply; 6+ messages in thread
From: Andrew Burgess @ 2019-06-11 21:49 UTC (permalink / raw)
  To: openrisc

* Stafford Horne <shorne@gmail.com> [2019-06-11 05:49:40 +0900]:

> Add tests for 32-bit and 64-bit unordered compare instructions.
> 
> sim/testsuite/sim/or1k/ChangeLog:
> 
> yyyy-mm-dd  Stafford Horne  <shorne@gmail.com>
> 
> 	* fpu-unordered.S: New file.
> 	* fpu64a32-unordered.S: New file.

This is fine with the nits below fixed.

Thanks,
Andrew


> ---
> Changes since v2:
>  - new patch
> 
>  sim/testsuite/sim/or1k/fpu-unordered.S      |  97 +++++++++++++++++++
>  sim/testsuite/sim/or1k/fpu64a32-unordered.S | 100 ++++++++++++++++++++
>  2 files changed, 197 insertions(+)
>  create mode 100644 sim/testsuite/sim/or1k/fpu-unordered.S
>  create mode 100644 sim/testsuite/sim/or1k/fpu64a32-unordered.S
> 
> diff --git a/sim/testsuite/sim/or1k/fpu-unordered.S b/sim/testsuite/sim/or1k/fpu-unordered.S
> new file mode 100644
> index 0000000000..bf229878bb
> --- /dev/null
> +++ b/sim/testsuite/sim/or1k/fpu-unordered.S
> @@ -0,0 +1,97 @@
> +/* Tests some basic unordered fpu compare instructions.
> +
> +   Copyright (C) 2017-2019 Free Software Foundation, Inc.

Date range should be '2019' only.


> +
> +   This program is free software; you can redistribute it and/or modify
> +   it under the terms of the GNU General Public License as published by
> +   the Free Software Foundation; either version 3 of the License, or
> +   (at your option) any later version.
> +
> +   This program is distributed in the hope that it will be useful,
> +   but WITHOUT ANY WARRANTY; without even the implied warranty of
> +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +   GNU General Public License for more details.
> +
> +   You should have received a copy of the GNU General Public License
> +   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
> +
> +# mach: or1k
> +# output: report(0x40490fd0);\n
> +# output: report(0x402df84d);\n
> +# output: report(0x7fc00000);\n
> +# output: \n
> +# output: report(0x00000001);\n
> +# output: \n
> +# output: report(0x00000000);\n
> +# output: \n
> +# output: report(0x00000001);\n
> +# output: \n
> +# output: report(0x00000001);\n
> +# output: \n
> +# output: exit(0)\n
> +
> +#include "or1k-asm-test-helpers.h"
> +
> +	STANDARD_TEST_ENVIRONMENT
> +
> +	.section .data
> +	.align 4
> +	.type   pi, @object
> +	.size   pi, 4
> +anchor:
> +pi:
> +	.float  3.14159
> +
> +	.type   e, @object
> +	.size   e, 4
> +e:
> +	.float  2.71828
> +
> +	.section .text
> +start_tests:
> +	PUSH LINK_REGISTER_R9
> +
> +	/* Test unordered float comparisons.  Setting up:
> +	 *  r11      pointer to data
> +	 *  r12  pi  as float
> +	 *  r13  e   as float
> +	 *  r16  nan as float
> +	 */
> +	l.ori	r11, r0, ha(anchor)
> +	l.addi	r11, r11, lo(anchor)
> +	l.lwz	r12, 0(r11)
> +
> +	l.lwz	r13, 4(r11)
> +
> +	/* Make a NaN.  */
> +	lf.sub.s r16, r13, r13
> +	lf.div.s r16, r16, r16
> +
> +	/* Output to ensure we loaded it correctly.  */
> +	REPORT_REG_TO_CONSOLE r12
> +	REPORT_REG_TO_CONSOLE r13
> +	REPORT_REG_TO_CONSOLE r16
> +	PRINT_NEWLINE_TO_CONSOLE
> +
> +	lf.sfuge.s r12, r13
> +	MOVE_FROM_SPR r2, SPR_SR
> +	REPORT_BIT_TO_CONSOLE r2, SPR_SR_F
> +	PRINT_NEWLINE_TO_CONSOLE
> +
> +	lf.sfun.s r12, r13
> +	MOVE_FROM_SPR r2, SPR_SR
> +	REPORT_BIT_TO_CONSOLE r2, SPR_SR_F
> +	PRINT_NEWLINE_TO_CONSOLE
> +
> +	lf.sfun.s r12, r16
> +	MOVE_FROM_SPR r2, SPR_SR
> +	REPORT_BIT_TO_CONSOLE r2, SPR_SR_F
> +	PRINT_NEWLINE_TO_CONSOLE
> +
> +	lf.sfueq.s r12, r12
> +	MOVE_FROM_SPR r2, SPR_SR
> +	REPORT_BIT_TO_CONSOLE r2, SPR_SR_F
> +	PRINT_NEWLINE_TO_CONSOLE
> +
> +	POP LINK_REGISTER_R9
> +	RETURN_TO_LINK_REGISTER_R9
> diff --git a/sim/testsuite/sim/or1k/fpu64a32-unordered.S b/sim/testsuite/sim/or1k/fpu64a32-unordered.S
> new file mode 100644
> index 0000000000..31c9ee4a33
> --- /dev/null
> +++ b/sim/testsuite/sim/or1k/fpu64a32-unordered.S
> @@ -0,0 +1,100 @@
> +/* Tests some basic unordered fpu compare instructions.
> +
> +   Copyright (C) 2017-2019 Free Software Foundation, Inc.

Date range should be '2019' only.

> +
> +   This program is free software; you can redistribute it and/or modify
> +   it under the terms of the GNU General Public License as published by
> +   the Free Software Foundation; either version 3 of the License, or
> +   (at your option) any later version.
> +
> +   This program is distributed in the hope that it will be useful,
> +   but WITHOUT ANY WARRANTY; without even the implied warranty of
> +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +   GNU General Public License for more details.
> +
> +   You should have received a copy of the GNU General Public License
> +   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
> +
> +# mach: or1k
> +# output: report(0x400921f9);\n
> +# output: report(0xf01b866e);\n
> +# output: report(0x4005bf09);\n
> +# output: report(0x95aaf790);\n
> +# output: report(0x7ff80000);\n
> +# output: report(0x00000000);\n
> +# output: \n
> +# output: report(0x00000001);\n
> +# output: \n
> +# output: report(0x00000000);\n
> +# output: \n
> +# output: report(0x00000001);\n
> +# output: \n
> +# output: exit(0)\n
> +
> +#include "or1k-asm-test-helpers.h"
> +
> +	STANDARD_TEST_ENVIRONMENT
> +
> +	.section .data
> +	.align 4
> +	.type   pi, @object
> +	.size   pi, 8
> +anchor:
> +pi:
> +	.double  3.14159
> +
> +	.type   e, @object
> +	.size   e, 8
> +e:
> +	.double  2.71828
> +
> +	.section .text
> +start_tests:
> +	PUSH LINK_REGISTER_R9
> +
> +	/* Test unordered double comparisons.  Setting up:
> +	 *  r11      pointer to data
> +	 *  r12,r13  pi  as double
> +	 *  r14,r15  e   as double
> +	 *  r16,r17  nan as double
> +	 */
> +	l.ori	r11, r0, ha(anchor)
> +	l.addi	r11, r11, lo(anchor)
> +	l.lwz	r12, 0(r11)
> +	l.lwz	r13, 4(r11)
> +
> +	l.lwz	r14, 8(r11)
> +	l.lwz	r15, 12(r11)
> +
> +	/* Make a NaN.  */
> +	lf.sub.d r16,r18, r12,r13, r12,r13
> +	lf.div.d r16,r18, r16,r18, r16,r18
> +
> +	/* Output to ensure we loaded it correctly.  */
> +	REPORT_REG_TO_CONSOLE r12
> +	REPORT_REG_TO_CONSOLE r13
> +
> +	REPORT_REG_TO_CONSOLE r14
> +	REPORT_REG_TO_CONSOLE r15
> +
> +	REPORT_REG_TO_CONSOLE r16
> +	REPORT_REG_TO_CONSOLE r18
> +	PRINT_NEWLINE_TO_CONSOLE
> +
> +	lf.sfuge.d r12,r13, r14,r15
> +	MOVE_FROM_SPR r2, SPR_SR
> +	REPORT_BIT_TO_CONSOLE r2, SPR_SR_F
> +	PRINT_NEWLINE_TO_CONSOLE
> +
> +	lf.sfun.d r12,r13, r14,r15
> +	MOVE_FROM_SPR r2, SPR_SR
> +	REPORT_BIT_TO_CONSOLE r2, SPR_SR_F
> +	PRINT_NEWLINE_TO_CONSOLE
> +
> +	lf.sfun.d r12,r13, r16,r18
> +	MOVE_FROM_SPR r2, SPR_SR
> +	REPORT_BIT_TO_CONSOLE r2, SPR_SR_F
> +	PRINT_NEWLINE_TO_CONSOLE
> +
> +	POP LINK_REGISTER_R9
> +	RETURN_TO_LINK_REGISTER_R9
> -- 
> 2.21.0
> 

^ permalink raw reply	[flat|nested] 6+ messages in thread

* [OpenRISC] [PATCH v3 10/11] sim/testsuite/or1k: Add test case for l.adrp instruction
  2019-06-11 21:48 ` [OpenRISC] [PATCH v3 10/11] sim/testsuite/or1k: Add test case for l.adrp instruction Andrew Burgess
@ 2019-06-12 13:09   ` Stafford Horne
  0 siblings, 0 replies; 6+ messages in thread
From: Stafford Horne @ 2019-06-12 13:09 UTC (permalink / raw)
  To: openrisc

On Tue, Jun 11, 2019 at 10:48:11PM +0100, Andrew Burgess wrote:
> * Stafford Horne <shorne@gmail.com> [2019-06-11 05:49:39 +0900]:
> 
> > This is a simple test to ensure that the l.adrp instruction can be assembled and
> > simulated correctly.
> > 
> > sim/testsuite/sim/or1k/ChangeLog:
> > 
> > yyyy-mm-dd  Stafford Horne  <shorne@gmail.com>
> > 
> > 	* adrp.S: New file.
> 
> This is fine with one nit below.
> 
> Thanks,
> Andrew
> 
> 
> > ---
> > Changes since v2:
> >  - new patch
> > 
> >  sim/testsuite/sim/or1k/adrp.S | 73 +++++++++++++++++++++++++++++++++++
> >  1 file changed, 73 insertions(+)
> >  create mode 100644 sim/testsuite/sim/or1k/adrp.S
> > 
> > diff --git a/sim/testsuite/sim/or1k/adrp.S b/sim/testsuite/sim/or1k/adrp.S
> > new file mode 100644
> > index 0000000000..ba384ccc84
> > --- /dev/null
> > +++ b/sim/testsuite/sim/or1k/adrp.S
> > @@ -0,0 +1,73 @@
> > +/* Tests the load page address instruction.
> > +
> > +   Copyright (C) 2017-2019 Free Software Foundation, Inc.
> 
> This date range should just be '2019'.

Oh, of course, bad copy from me. 

-Stafford 

^ permalink raw reply	[flat|nested] 6+ messages in thread

* [OpenRISC] [PATCH v3 11/11] sim/testsuite/or1k: Add tests for unordered compares
  2019-06-11 21:49   ` Andrew Burgess
@ 2019-06-12 13:11     ` Stafford Horne
  0 siblings, 0 replies; 6+ messages in thread
From: Stafford Horne @ 2019-06-12 13:11 UTC (permalink / raw)
  To: openrisc

On Tue, Jun 11, 2019 at 10:49:12PM +0100, Andrew Burgess wrote:
> * Stafford Horne <shorne@gmail.com> [2019-06-11 05:49:40 +0900]:
> 
> > Add tests for 32-bit and 64-bit unordered compare instructions.
> > 
> > sim/testsuite/sim/or1k/ChangeLog:
> > 
> > yyyy-mm-dd  Stafford Horne  <shorne@gmail.com>
> > 
> > 	* fpu-unordered.S: New file.
> > 	* fpu64a32-unordered.S: New file.
> 
> This is fine with the nits below fixed.

Sure, I will fix them.  Please note there are other patches for the sim that
have been updated (mostly regens from the binutils updates).

Also, this all depends on a cgen patch as well that is pending review.  So I
will wait to commit until cgen is reviewed.

-Stafford

^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2019-06-12 13:11 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-06-10 20:49 [OpenRISC] [PATCH v3 10/11] sim/testsuite/or1k: Add test case for l.adrp instruction Stafford Horne
2019-06-10 20:49 ` [OpenRISC] [PATCH v3 11/11] sim/testsuite/or1k: Add tests for unordered compares Stafford Horne
2019-06-11 21:49   ` Andrew Burgess
2019-06-12 13:11     ` Stafford Horne
2019-06-11 21:48 ` [OpenRISC] [PATCH v3 10/11] sim/testsuite/or1k: Add test case for l.adrp instruction Andrew Burgess
2019-06-12 13:09   ` Stafford Horne

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