* [PATCH 1/4] drm/i915: Refine placement of gt.reset_lockmap
@ 2019-06-13 6:20 Chris Wilson
2019-06-13 6:20 ` [PATCH 2/4] drm/i915: Avoid tainting i915_gem_park() with wakeref.lock Chris Wilson
` (4 more replies)
0 siblings, 5 replies; 8+ messages in thread
From: Chris Wilson @ 2019-06-13 6:20 UTC (permalink / raw)
To: intel-gfx
If we pull the lockmap into reset_prepare/reset_finish, it will
naturally cover i915_gem_set_wedged() as well as i915_reset(). And with
another tweak, we can pull __i915_gem_unset_wedged() underneath the
lockmap covering the mutexes used there.
As a bonus, it should hide the ugliness of the i915_reset exit path ;)
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_reset.c | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index 6368b37f26d1..952e11b4b5c5 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -723,6 +723,8 @@ static void reset_prepare(struct drm_i915_private *i915)
enum intel_engine_id id;
intel_gt_pm_get(i915);
+ lock_map_acquire(&i915->gt.reset_lockmap);
+
for_each_engine(engine, i915, id)
reset_prepare_engine(engine);
@@ -773,6 +775,8 @@ static void reset_finish(struct drm_i915_private *i915)
reset_finish_engine(engine);
intel_engine_signal_breadcrumbs(engine);
}
+
+ lock_map_release(&i915->gt.reset_lockmap);
intel_gt_pm_put(i915);
}
@@ -978,17 +982,17 @@ void i915_reset(struct drm_i915_private *i915,
might_sleep();
GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));
- lock_map_acquire(&i915->gt.reset_lockmap);
+
+ reset_prepare(i915);
/* Clear any previous failed attempts at recovery. Time to try again. */
if (!__i915_gem_unset_wedged(i915))
- goto unlock;
+ goto finish;
if (reason)
dev_notice(i915->drm.dev, "Resetting chip for %s\n", reason);
error->reset_count++;
- reset_prepare(i915);
if (!intel_has_gpu_reset(i915)) {
if (i915_modparams.reset)
@@ -1030,8 +1034,6 @@ void i915_reset(struct drm_i915_private *i915,
finish:
reset_finish(i915);
-unlock:
- lock_map_release(&i915->gt.reset_lockmap);
return;
taint:
--
2.20.1
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^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 2/4] drm/i915: Avoid tainting i915_gem_park() with wakeref.lock 2019-06-13 6:20 [PATCH 1/4] drm/i915: Refine placement of gt.reset_lockmap Chris Wilson @ 2019-06-13 6:20 ` Chris Wilson 2019-06-13 6:20 ` [PATCH 3/4] drm/i915: Move fence register tracking from i915->mm to ggtt Chris Wilson ` (3 subsequent siblings) 4 siblings, 0 replies; 8+ messages in thread From: Chris Wilson @ 2019-06-13 6:20 UTC (permalink / raw) To: intel-gfx While we need to flush the wakeref before parking, we do not need to perform the i915_gem_park() itself underneath the wakeref lock, merely the struct_mutex. If we rearrange the locks, we can avoid the unnecessary tainting. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/gem/i915_gem_pm.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_pm.c index f68c0ad1aa47..03af78151aeb 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c @@ -30,23 +30,22 @@ static void idle_work_handler(struct work_struct *work) { struct drm_i915_private *i915 = container_of(work, typeof(*i915), gem.idle_work); - bool restart = true; + bool park; - cancel_delayed_work(&i915->gem.retire_work); + cancel_delayed_work_sync(&i915->gem.retire_work); mutex_lock(&i915->drm.struct_mutex); intel_wakeref_lock(&i915->gt.wakeref); - if (!intel_wakeref_active(&i915->gt.wakeref) && !work_pending(work)) { - i915_gem_park(i915); - restart = false; - } + park = !intel_wakeref_active(&i915->gt.wakeref) && !work_pending(work); intel_wakeref_unlock(&i915->gt.wakeref); - - mutex_unlock(&i915->drm.struct_mutex); - if (restart) + if (park) + i915_gem_park(i915); + else queue_delayed_work(i915->wq, &i915->gem.retire_work, round_jiffies_up_relative(HZ)); + + mutex_unlock(&i915->drm.struct_mutex); } static void retire_work_handler(struct work_struct *work) -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 3/4] drm/i915: Move fence register tracking from i915->mm to ggtt 2019-06-13 6:20 [PATCH 1/4] drm/i915: Refine placement of gt.reset_lockmap Chris Wilson 2019-06-13 6:20 ` [PATCH 2/4] drm/i915: Avoid tainting i915_gem_park() with wakeref.lock Chris Wilson @ 2019-06-13 6:20 ` Chris Wilson 2019-06-13 6:20 ` [PATCH 4/4] drm/i915: Track ggtt fence reservations under its own mutex Chris Wilson ` (2 subsequent siblings) 4 siblings, 0 replies; 8+ messages in thread From: Chris Wilson @ 2019-06-13 6:20 UTC (permalink / raw) To: intel-gfx As the fence registers only apply to regions inside the GGTT is makes more sense that we track these as part of the i915_ggtt and not the general mm. In the next patch, we will then pull the register locking underneath the i915_ggtt.mutex. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> --- drivers/gpu/drm/i915/gem/i915_gem_mman.c | 4 +- drivers/gpu/drm/i915/gem/i915_gem_pm.c | 2 +- drivers/gpu/drm/i915/gt/intel_reset.c | 6 +- drivers/gpu/drm/i915/gvt/aperture_gm.c | 7 +- drivers/gpu/drm/i915/gvt/gvt.h | 4 +- drivers/gpu/drm/i915/i915_debugfs.c | 42 ++++++----- drivers/gpu/drm/i915/i915_drv.c | 3 +- drivers/gpu/drm/i915/i915_drv.h | 28 ------- drivers/gpu/drm/i915/i915_gem.c | 52 +++---------- drivers/gpu/drm/i915/i915_gem_fence_reg.c | 90 ++++++++++++++++------- drivers/gpu/drm/i915/i915_gem_fence_reg.h | 19 ++++- drivers/gpu/drm/i915/i915_gem_gtt.c | 2 + drivers/gpu/drm/i915/i915_gem_gtt.h | 14 +++- drivers/gpu/drm/i915/i915_gpu_error.c | 6 +- drivers/gpu/drm/i915/i915_vma.h | 2 +- 15 files changed, 144 insertions(+), 137 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c index c7b9b34de01b..a8b8b9c281f1 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c @@ -310,9 +310,9 @@ vm_fault_t i915_gem_fault(struct vm_fault *vmf) /* Mark as being mmapped into userspace for later revocation */ assert_rpm_wakelock_held(i915); if (!i915_vma_set_userfault(vma) && !obj->userfault_count++) - list_add(&obj->userfault_link, &i915->mm.userfault_list); + list_add(&obj->userfault_link, &i915->ggtt.userfault_list); if (CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND) - intel_wakeref_auto(&i915->mm.userfault_wakeref, + intel_wakeref_auto(&i915->ggtt.userfault_wakeref, msecs_to_jiffies_timeout(CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND)); GEM_BUG_ON(!obj->userfault_count); diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_pm.c index 03af78151aeb..a33f69610d6f 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c @@ -125,7 +125,7 @@ void i915_gem_suspend(struct drm_i915_private *i915) { GEM_TRACE("\n"); - intel_wakeref_auto(&i915->mm.userfault_wakeref, 0); + intel_wakeref_auto(&i915->ggtt.userfault_wakeref, 0); flush_workqueue(i915->wq); mutex_lock(&i915->drm.struct_mutex); diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c index 952e11b4b5c5..3b88bbd37275 100644 --- a/drivers/gpu/drm/i915/gt/intel_reset.c +++ b/drivers/gpu/drm/i915/gt/intel_reset.c @@ -695,19 +695,19 @@ static void revoke_mmaps(struct drm_i915_private *i915) { int i; - for (i = 0; i < i915->num_fence_regs; i++) { + for (i = 0; i < i915->ggtt.num_fences; i++) { struct drm_vma_offset_node *node; struct i915_vma *vma; u64 vma_offset; - vma = READ_ONCE(i915->fence_regs[i].vma); + vma = READ_ONCE(i915->ggtt.fence_regs[i].vma); if (!vma) continue; if (!i915_vma_has_userfault(vma)) continue; - GEM_BUG_ON(vma->fence != &i915->fence_regs[i]); + GEM_BUG_ON(vma->fence != &i915->ggtt.fence_regs[i]); node = &vma->obj->base.vma_node; vma_offset = vma->ggtt_view.partial.offset << PAGE_SHIFT; unmap_mapping_range(i915->drm.anon_inode->i_mapping, diff --git a/drivers/gpu/drm/i915/gvt/aperture_gm.c b/drivers/gpu/drm/i915/gvt/aperture_gm.c index 1fa2f65c3cd1..4098902bfaeb 100644 --- a/drivers/gpu/drm/i915/gvt/aperture_gm.c +++ b/drivers/gpu/drm/i915/gvt/aperture_gm.c @@ -35,6 +35,7 @@ */ #include "i915_drv.h" +#include "i915_gem_fence_reg.h" #include "gvt.h" static int alloc_gm(struct intel_vgpu *vgpu, bool high_gm) @@ -128,7 +129,7 @@ void intel_vgpu_write_fence(struct intel_vgpu *vgpu, { struct intel_gvt *gvt = vgpu->gvt; struct drm_i915_private *dev_priv = gvt->dev_priv; - struct drm_i915_fence_reg *reg; + struct i915_fence_reg *reg; i915_reg_t fence_reg_lo, fence_reg_hi; assert_rpm_wakelock_held(dev_priv); @@ -163,7 +164,7 @@ static void free_vgpu_fence(struct intel_vgpu *vgpu) { struct intel_gvt *gvt = vgpu->gvt; struct drm_i915_private *dev_priv = gvt->dev_priv; - struct drm_i915_fence_reg *reg; + struct i915_fence_reg *reg; u32 i; if (WARN_ON(!vgpu_fence_sz(vgpu))) @@ -187,7 +188,7 @@ static int alloc_vgpu_fence(struct intel_vgpu *vgpu) { struct intel_gvt *gvt = vgpu->gvt; struct drm_i915_private *dev_priv = gvt->dev_priv; - struct drm_i915_fence_reg *reg; + struct i915_fence_reg *reg; int i; intel_runtime_pm_get(dev_priv); diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h index b54f2bdc13a4..dfd10cf82b65 100644 --- a/drivers/gpu/drm/i915/gvt/gvt.h +++ b/drivers/gpu/drm/i915/gvt/gvt.h @@ -87,7 +87,7 @@ struct intel_vgpu_gm { /* Fences owned by a vGPU */ struct intel_vgpu_fence { - struct drm_i915_fence_reg *regs[INTEL_GVT_MAX_NUM_FENCES]; + struct i915_fence_reg *regs[INTEL_GVT_MAX_NUM_FENCES]; u32 base; u32 size; }; @@ -390,7 +390,7 @@ int intel_gvt_load_firmware(struct intel_gvt *gvt); #define gvt_hidden_gmadr_end(gvt) (gvt_hidden_gmadr_base(gvt) \ + gvt_hidden_sz(gvt) - 1) -#define gvt_fence_sz(gvt) (gvt->dev_priv->num_fence_regs) +#define gvt_fence_sz(gvt) ((gvt)->dev_priv->ggtt.num_fences) /* Aperture/GM space definitions for vGPU */ #define vgpu_aperture_offset(vgpu) ((vgpu)->gm.low_gm_node.start) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 026fb46020f6..323863504111 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -143,8 +143,6 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) unsigned int frontbuffer_bits; int pin_count = 0; - lockdep_assert_held(&obj->base.dev->struct_mutex); - seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x %s%s%s", &obj->base, get_active_flag(obj), @@ -160,17 +158,17 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : ""); if (obj->base.name) seq_printf(m, " (name: %d)", obj->base.name); - list_for_each_entry(vma, &obj->vma.list, obj_link) { - if (i915_vma_is_pinned(vma)) - pin_count++; - } - seq_printf(m, " (pinned x %d)", pin_count); - if (obj->pin_global) - seq_printf(m, " (global)"); + + spin_lock(&obj->vma.lock); list_for_each_entry(vma, &obj->vma.list, obj_link) { if (!drm_mm_node_allocated(&vma->node)) continue; + spin_unlock(&obj->vma.lock); + + if (i915_vma_is_pinned(vma)) + pin_count++; + seq_printf(m, " (%sgtt offset: %08llx, size: %08llx, pages: %s", i915_vma_is_ggtt(vma) ? "g" : "pp", vma->node.start, vma->node.size, @@ -221,9 +219,16 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) vma->fence->id, i915_active_request_isset(&vma->last_fence) ? "*" : ""); seq_puts(m, ")"); + + spin_lock(&obj->vma.lock); } + spin_unlock(&obj->vma.lock); + + seq_printf(m, " (pinned x %d)", pin_count); if (obj->stolen) seq_printf(m, " (stolen: %08llx)", obj->stolen->start); + if (obj->pin_global) + seq_printf(m, " (global)"); engine = i915_gem_object_last_write_engine(obj); if (engine) @@ -698,28 +703,25 @@ static int i915_interrupt_info(struct seq_file *m, void *data) static int i915_gem_fence_regs_info(struct seq_file *m, void *data) { - struct drm_i915_private *dev_priv = node_to_i915(m->private); - struct drm_device *dev = &dev_priv->drm; - int i, ret; + struct drm_i915_private *i915 = node_to_i915(m->private); + unsigned int i; - ret = mutex_lock_interruptible(&dev->struct_mutex); - if (ret) - return ret; + seq_printf(m, "Total fences = %d\n", i915->ggtt.num_fences); - seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); - for (i = 0; i < dev_priv->num_fence_regs; i++) { - struct i915_vma *vma = dev_priv->fence_regs[i].vma; + rcu_read_lock(); + for (i = 0; i < i915->ggtt.num_fences; i++) { + struct i915_vma *vma = i915->ggtt.fence_regs[i].vma; seq_printf(m, "Fence %d, pin count = %d, object = ", - i, dev_priv->fence_regs[i].pin_count); + i, i915->ggtt.fence_regs[i].pin_count); if (!vma) seq_puts(m, "unused"); else describe_obj(m, vma->obj); seq_putc(m, '\n'); } + rcu_read_unlock(); - mutex_unlock(&dev->struct_mutex); return 0; } diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 81ff2c78fd55..254f7b7df306 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -350,7 +350,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data, value = pdev->revision; break; case I915_PARAM_NUM_FENCES_AVAIL: - value = dev_priv->num_fence_regs; + value = dev_priv->ggtt.num_fences; break; case I915_PARAM_HAS_OVERLAY: value = dev_priv->overlay ? 1 : 0; @@ -1625,7 +1625,6 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv) intel_uncore_sanitize(dev_priv); intel_gt_init_workarounds(dev_priv); - i915_gem_load_init_fences(dev_priv); /* On the 945G/GM, the chipset reports the MSI capability on the * integrated graphics even though the support isn't actually there diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index eb98d285d290..90d94d904e65 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -757,14 +757,6 @@ struct i915_gem_mm { */ struct list_head shrink_list; - /** List of all objects in gtt_space, currently mmaped by userspace. - * All objects within this list must also be on bound_list. - */ - struct list_head userfault_list; - - /* Manual runtime pm autosuspend delay for user GGTT mmaps */ - struct intel_wakeref_auto userfault_wakeref; - /** * List of objects which are pending destruction. */ @@ -794,9 +786,6 @@ struct i915_gem_mm { struct notifier_block vmap_notifier; struct shrinker shrinker; - /** LRU list of objects with fence regs on them. */ - struct list_head fence_list; - /** * Workqueue to fault in userptr pages, flushed by the execbuf * when required but otherwise left to userspace to try again @@ -1485,9 +1474,6 @@ struct drm_i915_private { /* protects panel power sequencer state */ struct mutex pps_mutex; - struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ - int num_fence_regs; /* 8 on pre-965, 16 otherwise */ - unsigned int fsb_freq, mem_freq, is_ddr3; unsigned int skl_preferred_vco_freq; unsigned int max_cdclk_freq; @@ -2541,7 +2527,6 @@ void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv); void i915_gem_sanitize(struct drm_i915_private *i915); int i915_gem_init_early(struct drm_i915_private *dev_priv); void i915_gem_cleanup_early(struct drm_i915_private *dev_priv); -void i915_gem_load_init_fences(struct drm_i915_private *dev_priv); int i915_gem_freeze(struct drm_i915_private *dev_priv); int i915_gem_freeze_late(struct drm_i915_private *dev_priv); @@ -2661,19 +2646,6 @@ struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, struct dma_buf *i915_gem_prime_export(struct drm_device *dev, struct drm_gem_object *gem_obj, int flags); -/* i915_gem_fence_reg.c */ -struct drm_i915_fence_reg * -i915_reserve_fence(struct drm_i915_private *dev_priv); -void i915_unreserve_fence(struct drm_i915_fence_reg *fence); - -void i915_gem_restore_fences(struct drm_i915_private *dev_priv); - -void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv); -void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj, - struct sg_table *pages); -void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj, - struct sg_table *pages); - static inline struct i915_gem_context * __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id) { diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 4017ecf561f6..4bbded4aa936 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -884,7 +884,7 @@ i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, return 0; } -void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv) +void i915_gem_runtime_suspend(struct drm_i915_private *i915) { struct drm_i915_gem_object *obj, *on; int i; @@ -897,17 +897,19 @@ void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv) */ list_for_each_entry_safe(obj, on, - &dev_priv->mm.userfault_list, userfault_link) + &i915->ggtt.userfault_list, userfault_link) __i915_gem_object_release_mmap(obj); - /* The fence will be lost when the device powers down. If any were + /* + * The fence will be lost when the device powers down. If any were * in use by hardware (i.e. they are pinned), we should not be powering * down! All other fences will be reacquired by the user upon waking. */ - for (i = 0; i < dev_priv->num_fence_regs; i++) { - struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; + for (i = 0; i < i915->ggtt.num_fences; i++) { + struct i915_fence_reg *reg = &i915->ggtt.fence_regs[i]; - /* Ideally we want to assert that the fence register is not + /* + * Ideally we want to assert that the fence register is not * live at this point (i.e. that no piece of code will be * trying to write through fence + GTT, as that both violates * our tracking of activity and associated locking/barriers, @@ -1687,7 +1689,7 @@ void i915_gem_fini_hw(struct drm_i915_private *dev_priv) { GEM_BUG_ON(dev_priv->gt.awake); - intel_wakeref_auto_fini(&dev_priv->mm.userfault_wakeref); + intel_wakeref_auto_fini(&dev_priv->ggtt.userfault_wakeref); i915_gem_suspend_late(dev_priv); intel_disable_gt_powersave(dev_priv); @@ -1729,38 +1731,6 @@ void i915_gem_init_mmio(struct drm_i915_private *i915) i915_gem_sanitize(i915); } -void -i915_gem_load_init_fences(struct drm_i915_private *dev_priv) -{ - int i; - - if (INTEL_GEN(dev_priv) >= 7 && !IS_VALLEYVIEW(dev_priv) && - !IS_CHERRYVIEW(dev_priv)) - dev_priv->num_fence_regs = 32; - else if (INTEL_GEN(dev_priv) >= 4 || - IS_I945G(dev_priv) || IS_I945GM(dev_priv) || - IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) - dev_priv->num_fence_regs = 16; - else - dev_priv->num_fence_regs = 8; - - if (intel_vgpu_active(dev_priv)) - dev_priv->num_fence_regs = - I915_READ(vgtif_reg(avail_rs.fence_num)); - - /* Initialize fence registers to zero */ - for (i = 0; i < dev_priv->num_fence_regs; i++) { - struct drm_i915_fence_reg *fence = &dev_priv->fence_regs[i]; - - fence->i915 = dev_priv; - fence->id = i; - list_add_tail(&fence->link, &dev_priv->mm.fence_list); - } - i915_gem_restore_fences(dev_priv); - - i915_gem_detect_bit_6_swizzle(dev_priv); -} - static void i915_gem_init__mm(struct drm_i915_private *i915) { spin_lock_init(&i915->mm.obj_lock); @@ -1770,10 +1740,6 @@ static void i915_gem_init__mm(struct drm_i915_private *i915) INIT_LIST_HEAD(&i915->mm.purge_list); INIT_LIST_HEAD(&i915->mm.shrink_list); - INIT_LIST_HEAD(&i915->mm.fence_list); - - INIT_LIST_HEAD(&i915->mm.userfault_list); - intel_wakeref_auto_init(&i915->mm.userfault_wakeref, i915); i915_gem_init__objects(i915); } diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c index 10aa6e350bfa..1c9466676caf 100644 --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c @@ -25,6 +25,7 @@ #include "i915_drv.h" #include "i915_scatterlist.h" +#include "i915_vgpu.h" /** * DOC: fence register handling @@ -58,7 +59,7 @@ #define pipelined 0 -static void i965_write_fence_reg(struct drm_i915_fence_reg *fence, +static void i965_write_fence_reg(struct i915_fence_reg *fence, struct i915_vma *vma) { i915_reg_t fence_reg_lo, fence_reg_hi; @@ -115,7 +116,7 @@ static void i965_write_fence_reg(struct drm_i915_fence_reg *fence, } } -static void i915_write_fence_reg(struct drm_i915_fence_reg *fence, +static void i915_write_fence_reg(struct i915_fence_reg *fence, struct i915_vma *vma) { u32 val; @@ -155,7 +156,7 @@ static void i915_write_fence_reg(struct drm_i915_fence_reg *fence, } } -static void i830_write_fence_reg(struct drm_i915_fence_reg *fence, +static void i830_write_fence_reg(struct i915_fence_reg *fence, struct i915_vma *vma) { u32 val; @@ -187,7 +188,7 @@ static void i830_write_fence_reg(struct drm_i915_fence_reg *fence, } } -static void fence_write(struct drm_i915_fence_reg *fence, +static void fence_write(struct i915_fence_reg *fence, struct i915_vma *vma) { /* @@ -211,7 +212,7 @@ static void fence_write(struct drm_i915_fence_reg *fence, fence->dirty = false; } -static int fence_update(struct drm_i915_fence_reg *fence, +static int fence_update(struct i915_fence_reg *fence, struct i915_vma *vma) { intel_wakeref_t wakeref; @@ -256,7 +257,7 @@ static int fence_update(struct drm_i915_fence_reg *fence, old->fence = NULL; } - list_move(&fence->link, &fence->i915->mm.fence_list); + list_move(&fence->link, &fence->i915->ggtt.fence_list); } /* @@ -280,7 +281,7 @@ static int fence_update(struct drm_i915_fence_reg *fence, if (vma) { vma->fence = fence; - list_move_tail(&fence->link, &fence->i915->mm.fence_list); + list_move_tail(&fence->link, &fence->i915->ggtt.fence_list); } intel_runtime_pm_put(fence->i915, wakeref); @@ -300,7 +301,7 @@ static int fence_update(struct drm_i915_fence_reg *fence, */ int i915_vma_put_fence(struct i915_vma *vma) { - struct drm_i915_fence_reg *fence = vma->fence; + struct i915_fence_reg *fence = vma->fence; if (!fence) return 0; @@ -311,11 +312,11 @@ int i915_vma_put_fence(struct i915_vma *vma) return fence_update(fence, NULL); } -static struct drm_i915_fence_reg *fence_find(struct drm_i915_private *i915) +static struct i915_fence_reg *fence_find(struct drm_i915_private *i915) { - struct drm_i915_fence_reg *fence; + struct i915_fence_reg *fence; - list_for_each_entry(fence, &i915->mm.fence_list, link) { + list_for_each_entry(fence, &i915->ggtt.fence_list, link) { GEM_BUG_ON(fence->vma && fence->vma->fence != fence); if (fence->pin_count) @@ -349,10 +350,9 @@ static struct drm_i915_fence_reg *fence_find(struct drm_i915_private *i915) * * 0 on success, negative error code on failure. */ -int -i915_vma_pin_fence(struct i915_vma *vma) +int i915_vma_pin_fence(struct i915_vma *vma) { - struct drm_i915_fence_reg *fence; + struct i915_fence_reg *fence; struct i915_vma *set = i915_gem_object_is_tiled(vma->obj) ? vma : NULL; int err; @@ -369,7 +369,7 @@ i915_vma_pin_fence(struct i915_vma *vma) fence->pin_count++; if (!fence->dirty) { list_move_tail(&fence->link, - &fence->i915->mm.fence_list); + &fence->i915->ggtt.fence_list); return 0; } } else if (set) { @@ -404,10 +404,9 @@ i915_vma_pin_fence(struct i915_vma *vma) * This function walks the fence regs looking for a free one and remove * it from the fence_list. It is used to reserve fence for vGPU to use. */ -struct drm_i915_fence_reg * -i915_reserve_fence(struct drm_i915_private *i915) +struct i915_fence_reg *i915_reserve_fence(struct drm_i915_private *i915) { - struct drm_i915_fence_reg *fence; + struct i915_fence_reg *fence; int count; int ret; @@ -415,7 +414,7 @@ i915_reserve_fence(struct drm_i915_private *i915) /* Keep at least one fence available for the display engine. */ count = 0; - list_for_each_entry(fence, &i915->mm.fence_list, link) + list_for_each_entry(fence, &i915->ggtt.fence_list, link) count += !fence->pin_count; if (count <= 1) return ERR_PTR(-ENOSPC); @@ -441,11 +440,11 @@ i915_reserve_fence(struct drm_i915_private *i915) * * This function add a reserved fence register from vGPU to the fence_list. */ -void i915_unreserve_fence(struct drm_i915_fence_reg *fence) +void i915_unreserve_fence(struct i915_fence_reg *fence) { lockdep_assert_held(&fence->i915->drm.struct_mutex); - list_add(&fence->link, &fence->i915->mm.fence_list); + list_add(&fence->link, &fence->i915->ggtt.fence_list); } /** @@ -461,8 +460,8 @@ void i915_gem_restore_fences(struct drm_i915_private *i915) int i; rcu_read_lock(); /* keep obj alive as we dereference */ - for (i = 0; i < i915->num_fence_regs; i++) { - struct drm_i915_fence_reg *reg = &i915->fence_regs[i]; + for (i = 0; i < i915->ggtt.num_fences; i++) { + struct i915_fence_reg *reg = &i915->ggtt.fence_regs[i]; struct i915_vma *vma = READ_ONCE(reg->vma); GEM_BUG_ON(vma && vma->fence != reg); @@ -534,8 +533,7 @@ void i915_gem_restore_fences(struct drm_i915_private *i915) * Detects bit 6 swizzling of address lookup between IGD access and CPU * access through main memory. */ -void -i915_gem_detect_bit_6_swizzle(struct drm_i915_private *i915) +static void detect_bit_6_swizzle(struct drm_i915_private *i915) { struct intel_uncore *uncore = &i915->uncore; u32 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; @@ -708,8 +706,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_i915_private *i915) * bit 17 of its physical address and therefore being interpreted differently * by the GPU. */ -static void -i915_gem_swizzle_page(struct page *page) +static void i915_gem_swizzle_page(struct page *page) { char temp[64]; char *vaddr; @@ -798,3 +795,42 @@ i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj, i++; } } + +void i915_ggtt_init_fences(struct i915_ggtt *ggtt) +{ + struct drm_i915_private *i915 = ggtt->vm.i915; + int num_fences; + int i; + + INIT_LIST_HEAD(&ggtt->fence_list); + INIT_LIST_HEAD(&ggtt->userfault_list); + intel_wakeref_auto_init(&ggtt->userfault_wakeref, i915); + + detect_bit_6_swizzle(i915); + + if (INTEL_GEN(i915) >= 7 && + !(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))) + num_fences = 32; + else if (INTEL_GEN(i915) >= 4 || + IS_I945G(i915) || IS_I945GM(i915) || + IS_G33(i915) || IS_PINEVIEW(i915)) + num_fences = 16; + else + num_fences = 8; + + if (intel_vgpu_active(i915)) + num_fences = intel_uncore_read(&i915->uncore, + vgtif_reg(avail_rs.fence_num)); + + /* Initialize fence registers to zero */ + for (i = 0; i < num_fences; i++) { + struct i915_fence_reg *fence = &ggtt->fence_regs[i]; + + fence->i915 = i915; + fence->id = i; + list_add_tail(&fence->link, &ggtt->fence_list); + } + ggtt->num_fences = num_fences; + + i915_gem_restore_fences(i915); +} diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.h b/drivers/gpu/drm/i915/i915_gem_fence_reg.h index 09dcaf14121b..d2da98828179 100644 --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.h +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.h @@ -26,13 +26,17 @@ #define __I915_FENCE_REG_H__ #include <linux/list.h> +#include <linux/types.h> +struct drm_i915_gem_object; struct drm_i915_private; +struct i915_ggtt; struct i915_vma; +struct sg_table; #define I965_FENCE_PAGE 4096UL -struct drm_i915_fence_reg { +struct i915_fence_reg { struct list_head link; struct drm_i915_private *i915; struct i915_vma *vma; @@ -49,4 +53,17 @@ struct drm_i915_fence_reg { bool dirty; }; +/* i915_gem_fence_reg.c */ +struct i915_fence_reg *i915_reserve_fence(struct drm_i915_private *i915); +void i915_unreserve_fence(struct i915_fence_reg *fence); + +void i915_gem_restore_fences(struct drm_i915_private *i915); + +void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj, + struct sg_table *pages); +void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj, + struct sg_table *pages); + +void i915_ggtt_init_fences(struct i915_ggtt *ggtt); + #endif diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index e70675bfb51d..7be72388b052 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -3567,6 +3567,8 @@ int i915_ggtt_init_hw(struct drm_i915_private *dev_priv) ggtt->mtrr = arch_phys_wc_add(ggtt->gmadr.start, ggtt->mappable_end); + i915_ggtt_init_fences(ggtt); + /* * Initialise stolen early so that we may reserve preallocated * objects for the BIOS to KMS transition. diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index 89437d0a721c..63fa357c69de 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.h +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h @@ -39,6 +39,7 @@ #include <linux/pagevec.h> #include "gt/intel_reset.h" +#include "i915_gem_fence_reg.h" #include "i915_request.h" #include "i915_scatterlist.h" #include "i915_selftest.h" @@ -61,7 +62,6 @@ #define I915_MAX_NUM_FENCE_BITS 6 struct drm_i915_file_private; -struct drm_i915_fence_reg; struct drm_i915_gem_object; struct i915_vma; @@ -408,6 +408,18 @@ struct i915_ggtt { u32 pin_bias; + unsigned int num_fences; + struct i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; + struct list_head fence_list; + + /** List of all objects in gtt_space, currently mmaped by userspace. + * All objects within this list must also be on bound_list. + */ + struct list_head userfault_list; + + /* Manual runtime pm autosuspend delay for user GGTT mmaps */ + struct intel_wakeref_auto userfault_wakeref; + struct drm_mm_node error_capture; struct drm_mm_node uc_fw; }; diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index d7f164c9f2eb..26c9c0595bdf 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -1127,17 +1127,17 @@ static void gem_record_fences(struct i915_gpu_state *error) int i; if (INTEL_GEN(dev_priv) >= 6) { - for (i = 0; i < dev_priv->num_fence_regs; i++) + for (i = 0; i < dev_priv->ggtt.num_fences; i++) error->fence[i] = intel_uncore_read64(uncore, FENCE_REG_GEN6_LO(i)); } else if (INTEL_GEN(dev_priv) >= 4) { - for (i = 0; i < dev_priv->num_fence_regs; i++) + for (i = 0; i < dev_priv->ggtt.num_fences; i++) error->fence[i] = intel_uncore_read64(uncore, FENCE_REG_965_LO(i)); } else { - for (i = 0; i < dev_priv->num_fence_regs; i++) + for (i = 0; i < dev_priv->ggtt.num_fences; i++) error->fence[i] = intel_uncore_read(uncore, FENCE_REG(i)); } diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h index 0c57ab4fed5d..4b769db649bf 100644 --- a/drivers/gpu/drm/i915/i915_vma.h +++ b/drivers/gpu/drm/i915/i915_vma.h @@ -54,7 +54,7 @@ struct i915_vma { struct drm_i915_gem_object *obj; struct i915_address_space *vm; const struct i915_vma_ops *ops; - struct drm_i915_fence_reg *fence; + struct i915_fence_reg *fence; struct reservation_object *resv; /** Alias of obj->resv */ struct sg_table *pages; void __iomem *iomap; -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 4/4] drm/i915: Track ggtt fence reservations under its own mutex 2019-06-13 6:20 [PATCH 1/4] drm/i915: Refine placement of gt.reset_lockmap Chris Wilson 2019-06-13 6:20 ` [PATCH 2/4] drm/i915: Avoid tainting i915_gem_park() with wakeref.lock Chris Wilson 2019-06-13 6:20 ` [PATCH 3/4] drm/i915: Move fence register tracking from i915->mm to ggtt Chris Wilson @ 2019-06-13 6:20 ` Chris Wilson 2019-06-13 6:47 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915: Refine placement of gt.reset_lockmap Patchwork 2019-06-13 7:10 ` ✗ Fi.CI.BAT: failure " Patchwork 4 siblings, 0 replies; 8+ messages in thread From: Chris Wilson @ 2019-06-13 6:20 UTC (permalink / raw) To: intel-gfx We can reduce the locking for fence registers from the dev->struct_mutex to a local mutex. We could introduce a mutex for the sole purpose of tracking the fence acquisition, except there is a little bit of overlap with the fault tracking, so use the i915_ggtt.mutex as it covers both. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> --- drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 7 ++ drivers/gpu/drm/i915/gvt/aperture_gm.c | 10 +- drivers/gpu/drm/i915/i915_debugfs.c | 5 +- drivers/gpu/drm/i915/i915_gem_fence_reg.c | 108 ++++++++++++------- drivers/gpu/drm/i915/i915_gem_fence_reg.h | 2 +- drivers/gpu/drm/i915/i915_vma.h | 4 +- 6 files changed, 87 insertions(+), 49 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c index 45379a63e013..3752d3172543 100644 --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c @@ -1165,7 +1165,14 @@ static int evict_fence(void *data) goto out_unlock; } + err = i915_vma_pin(arg->vma, 0, 0, PIN_GLOBAL | PIN_MAPPABLE); + if (err) { + pr_err("Unable to pin vma for Y-tiled fence; err:%d\n", err); + goto out_unlock; + } + err = i915_vma_pin_fence(arg->vma); + i915_vma_unpin(arg->vma); if (err) { pr_err("Unable to pin Y-tiled fence; err:%d\n", err); goto out_unlock; diff --git a/drivers/gpu/drm/i915/gvt/aperture_gm.c b/drivers/gpu/drm/i915/gvt/aperture_gm.c index 4098902bfaeb..2bd9dcebd48c 100644 --- a/drivers/gpu/drm/i915/gvt/aperture_gm.c +++ b/drivers/gpu/drm/i915/gvt/aperture_gm.c @@ -172,14 +172,14 @@ static void free_vgpu_fence(struct intel_vgpu *vgpu) intel_runtime_pm_get(dev_priv); - mutex_lock(&dev_priv->drm.struct_mutex); + mutex_lock(&dev_priv->ggtt.vm.mutex); _clear_vgpu_fence(vgpu); for (i = 0; i < vgpu_fence_sz(vgpu); i++) { reg = vgpu->fence.regs[i]; i915_unreserve_fence(reg); vgpu->fence.regs[i] = NULL; } - mutex_unlock(&dev_priv->drm.struct_mutex); + mutex_unlock(&dev_priv->ggtt.vm.mutex); intel_runtime_pm_put_unchecked(dev_priv); } @@ -194,7 +194,7 @@ static int alloc_vgpu_fence(struct intel_vgpu *vgpu) intel_runtime_pm_get(dev_priv); /* Request fences from host */ - mutex_lock(&dev_priv->drm.struct_mutex); + mutex_lock(&dev_priv->ggtt.vm.mutex); for (i = 0; i < vgpu_fence_sz(vgpu); i++) { reg = i915_reserve_fence(dev_priv); @@ -206,7 +206,7 @@ static int alloc_vgpu_fence(struct intel_vgpu *vgpu) _clear_vgpu_fence(vgpu); - mutex_unlock(&dev_priv->drm.struct_mutex); + mutex_unlock(&dev_priv->ggtt.vm.mutex); intel_runtime_pm_put_unchecked(dev_priv); return 0; out_free_fence: @@ -219,7 +219,7 @@ static int alloc_vgpu_fence(struct intel_vgpu *vgpu) i915_unreserve_fence(reg); vgpu->fence.regs[i] = NULL; } - mutex_unlock(&dev_priv->drm.struct_mutex); + mutex_unlock(&dev_priv->ggtt.vm.mutex); intel_runtime_pm_put_unchecked(dev_priv); return -ENOSPC; } diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 323863504111..7a54f2d432af 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -710,10 +710,11 @@ static int i915_gem_fence_regs_info(struct seq_file *m, void *data) rcu_read_lock(); for (i = 0; i < i915->ggtt.num_fences; i++) { - struct i915_vma *vma = i915->ggtt.fence_regs[i].vma; + struct i915_fence_reg *reg = &i915->ggtt.fence_regs[i]; + struct i915_vma *vma = reg->vma; seq_printf(m, "Fence %d, pin count = %d, object = ", - i, i915->ggtt.fence_regs[i].pin_count); + i, atomic_read(®->pin_count)); if (!vma) seq_puts(m, "unused"); else diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c index 1c9466676caf..24bdffac6380 100644 --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c @@ -301,15 +301,24 @@ static int fence_update(struct i915_fence_reg *fence, */ int i915_vma_put_fence(struct i915_vma *vma) { + struct i915_ggtt *ggtt = i915_vm_to_ggtt(vma->vm); struct i915_fence_reg *fence = vma->fence; + int err; if (!fence) return 0; - if (fence->pin_count) + if (atomic_read(&fence->pin_count)) return -EBUSY; - return fence_update(fence, NULL); + err = mutex_lock_interruptible(&ggtt->vm.mutex); + if (err) + return err; + + err = fence_update(fence, NULL); + mutex_unlock(&ggtt->vm.mutex); + + return err; } static struct i915_fence_reg *fence_find(struct drm_i915_private *i915) @@ -319,7 +328,7 @@ static struct i915_fence_reg *fence_find(struct drm_i915_private *i915) list_for_each_entry(fence, &i915->ggtt.fence_list, link) { GEM_BUG_ON(fence->vma && fence->vma->fence != fence); - if (fence->pin_count) + if (atomic_read(&fence->pin_count)) continue; return fence; @@ -332,6 +341,48 @@ static struct i915_fence_reg *fence_find(struct drm_i915_private *i915) return ERR_PTR(-EDEADLK); } +static int __i915_vma_pin_fence(struct i915_vma *vma) +{ + struct i915_ggtt *ggtt = i915_vm_to_ggtt(vma->vm); + struct i915_fence_reg *fence; + struct i915_vma *set = i915_gem_object_is_tiled(vma->obj) ? vma : NULL; + int err; + + /* Just update our place in the LRU if our fence is getting reused. */ + if (vma->fence) { + fence = vma->fence; + GEM_BUG_ON(fence->vma != vma); + atomic_inc(&fence->pin_count); + if (!fence->dirty) { + list_move_tail(&fence->link, &ggtt->fence_list); + return 0; + } + } else if (set) { + fence = fence_find(vma->vm->i915); + if (IS_ERR(fence)) + return PTR_ERR(fence); + + GEM_BUG_ON(atomic_read(&fence->pin_count)); + atomic_inc(&fence->pin_count); + } else { + return 0; + } + + err = fence_update(fence, set); + if (err) + goto out_unpin; + + GEM_BUG_ON(fence->vma != set); + GEM_BUG_ON(vma->fence != (set ? fence : NULL)); + + if (set) + return 0; + +out_unpin: + atomic_dec(&fence->pin_count); + return err; +} + /** * i915_vma_pin_fence - set up fencing for a vma * @vma: vma to map through a fence reg @@ -352,8 +403,6 @@ static struct i915_fence_reg *fence_find(struct drm_i915_private *i915) */ int i915_vma_pin_fence(struct i915_vma *vma) { - struct i915_fence_reg *fence; - struct i915_vma *set = i915_gem_object_is_tiled(vma->obj) ? vma : NULL; int err; /* @@ -361,39 +410,16 @@ int i915_vma_pin_fence(struct i915_vma *vma) * must keep the device awake whilst using the fence. */ assert_rpm_wakelock_held(vma->vm->i915); + GEM_BUG_ON(!i915_vma_is_pinned(vma)); + GEM_BUG_ON(!i915_vma_is_ggtt(vma)); - /* Just update our place in the LRU if our fence is getting reused. */ - if (vma->fence) { - fence = vma->fence; - GEM_BUG_ON(fence->vma != vma); - fence->pin_count++; - if (!fence->dirty) { - list_move_tail(&fence->link, - &fence->i915->ggtt.fence_list); - return 0; - } - } else if (set) { - fence = fence_find(vma->vm->i915); - if (IS_ERR(fence)) - return PTR_ERR(fence); - - GEM_BUG_ON(fence->pin_count); - fence->pin_count++; - } else - return 0; - - err = fence_update(fence, set); + err = mutex_lock_interruptible(&vma->vm->mutex); if (err) - goto out_unpin; + return err; - GEM_BUG_ON(fence->vma != set); - GEM_BUG_ON(vma->fence != (set ? fence : NULL)); - - if (set) - return 0; + err = __i915_vma_pin_fence(vma); + mutex_unlock(&vma->vm->mutex); -out_unpin: - fence->pin_count--; return err; } @@ -406,16 +432,17 @@ int i915_vma_pin_fence(struct i915_vma *vma) */ struct i915_fence_reg *i915_reserve_fence(struct drm_i915_private *i915) { + struct i915_ggtt *ggtt = &i915->ggtt; struct i915_fence_reg *fence; int count; int ret; - lockdep_assert_held(&i915->drm.struct_mutex); + lockdep_assert_held(&ggtt->vm.mutex); /* Keep at least one fence available for the display engine. */ count = 0; - list_for_each_entry(fence, &i915->ggtt.fence_list, link) - count += !fence->pin_count; + list_for_each_entry(fence, &ggtt->fence_list, link) + count += !atomic_read(&fence->pin_count); if (count <= 1) return ERR_PTR(-ENOSPC); @@ -431,6 +458,7 @@ struct i915_fence_reg *i915_reserve_fence(struct drm_i915_private *i915) } list_del(&fence->link); + return fence; } @@ -442,9 +470,11 @@ struct i915_fence_reg *i915_reserve_fence(struct drm_i915_private *i915) */ void i915_unreserve_fence(struct i915_fence_reg *fence) { - lockdep_assert_held(&fence->i915->drm.struct_mutex); + struct i915_ggtt *ggtt = &fence->i915->ggtt; + + lockdep_assert_held(&ggtt->vm.mutex); - list_add(&fence->link, &fence->i915->ggtt.fence_list); + list_add(&fence->link, &ggtt->fence_list); } /** diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.h b/drivers/gpu/drm/i915/i915_gem_fence_reg.h index d2da98828179..d7c6ebf789c1 100644 --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.h +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.h @@ -40,7 +40,7 @@ struct i915_fence_reg { struct list_head link; struct drm_i915_private *i915; struct i915_vma *vma; - int pin_count; + atomic_t pin_count; int id; /** * Whether the tiling parameters for the currently diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h index 4b769db649bf..908118ade441 100644 --- a/drivers/gpu/drm/i915/i915_vma.h +++ b/drivers/gpu/drm/i915/i915_vma.h @@ -419,8 +419,8 @@ int __must_check i915_vma_put_fence(struct i915_vma *vma); static inline void __i915_vma_unpin_fence(struct i915_vma *vma) { - GEM_BUG_ON(vma->fence->pin_count <= 0); - vma->fence->pin_count--; + GEM_BUG_ON(atomic_read(&vma->fence->pin_count) <= 0); + atomic_dec(&vma->fence->pin_count); } /** -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 8+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915: Refine placement of gt.reset_lockmap 2019-06-13 6:20 [PATCH 1/4] drm/i915: Refine placement of gt.reset_lockmap Chris Wilson ` (2 preceding siblings ...) 2019-06-13 6:20 ` [PATCH 4/4] drm/i915: Track ggtt fence reservations under its own mutex Chris Wilson @ 2019-06-13 6:47 ` Patchwork 2019-06-13 7:10 ` ✗ Fi.CI.BAT: failure " Patchwork 4 siblings, 0 replies; 8+ messages in thread From: Patchwork @ 2019-06-13 6:47 UTC (permalink / raw) To: Chris Wilson; +Cc: intel-gfx == Series Details == Series: series starting with [1/4] drm/i915: Refine placement of gt.reset_lockmap URL : https://patchwork.freedesktop.org/series/61991/ State : warning == Summary == $ dim checkpatch origin/drm-tip 2fa70e0be054 drm/i915: Refine placement of gt.reset_lockmap c4b1fa3b38d7 drm/i915: Avoid tainting i915_gem_park() with wakeref.lock 6e042e229f1d drm/i915: Move fence register tracking from i915->mm to ggtt -:182: WARNING:PREFER_SEQ_PUTS: Prefer seq_puts to seq_printf #182: FILE: drivers/gpu/drm/i915/i915_debugfs.c:231: + seq_printf(m, " (global)"); total: 0 errors, 1 warnings, 0 checks, 644 lines checked 8d914dd82cd7 drm/i915: Track ggtt fence reservations under its own mutex _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* ✗ Fi.CI.BAT: failure for series starting with [1/4] drm/i915: Refine placement of gt.reset_lockmap 2019-06-13 6:20 [PATCH 1/4] drm/i915: Refine placement of gt.reset_lockmap Chris Wilson ` (3 preceding siblings ...) 2019-06-13 6:47 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915: Refine placement of gt.reset_lockmap Patchwork @ 2019-06-13 7:10 ` Patchwork 2019-06-13 7:15 ` Chris Wilson 4 siblings, 1 reply; 8+ messages in thread From: Patchwork @ 2019-06-13 7:10 UTC (permalink / raw) To: Chris Wilson; +Cc: intel-gfx == Series Details == Series: series starting with [1/4] drm/i915: Refine placement of gt.reset_lockmap URL : https://patchwork.freedesktop.org/series/61991/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6253 -> Patchwork_13265 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_13265 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_13265, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/ Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_13265: ### IGT changes ### #### Possible regressions #### * igt@i915_selftest@live_hangcheck: - fi-bdw-gvtdvm: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-bdw-gvtdvm/igt@i915_selftest@live_hangcheck.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-bdw-gvtdvm/igt@i915_selftest@live_hangcheck.html - fi-bdw-5557u: [PASS][3] -> [DMESG-WARN][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-bdw-5557u/igt@i915_selftest@live_hangcheck.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-bdw-5557u/igt@i915_selftest@live_hangcheck.html - fi-bwr-2160: [PASS][5] -> [DMESG-WARN][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-bwr-2160/igt@i915_selftest@live_hangcheck.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-bwr-2160/igt@i915_selftest@live_hangcheck.html - fi-kbl-r: [PASS][7] -> [DMESG-WARN][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-kbl-r/igt@i915_selftest@live_hangcheck.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-kbl-r/igt@i915_selftest@live_hangcheck.html - fi-kbl-7567u: [PASS][9] -> [DMESG-WARN][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-kbl-7567u/igt@i915_selftest@live_hangcheck.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-kbl-7567u/igt@i915_selftest@live_hangcheck.html - fi-skl-guc: [PASS][11] -> [DMESG-WARN][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-skl-guc/igt@i915_selftest@live_hangcheck.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-skl-guc/igt@i915_selftest@live_hangcheck.html - fi-cfl-8109u: [PASS][13] -> [DMESG-WARN][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-cfl-8109u/igt@i915_selftest@live_hangcheck.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-cfl-8109u/igt@i915_selftest@live_hangcheck.html - fi-snb-2520m: [PASS][15] -> [DMESG-WARN][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-snb-2520m/igt@i915_selftest@live_hangcheck.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-snb-2520m/igt@i915_selftest@live_hangcheck.html - fi-cfl-8700k: [PASS][17] -> [DMESG-WARN][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-cfl-8700k/igt@i915_selftest@live_hangcheck.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-cfl-8700k/igt@i915_selftest@live_hangcheck.html - fi-whl-u: [PASS][19] -> [DMESG-WARN][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-whl-u/igt@i915_selftest@live_hangcheck.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-whl-u/igt@i915_selftest@live_hangcheck.html - fi-icl-u2: NOTRUN -> [DMESG-WARN][21] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-icl-u2/igt@i915_selftest@live_hangcheck.html - fi-ilk-650: [PASS][22] -> [DMESG-WARN][23] [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-ilk-650/igt@i915_selftest@live_hangcheck.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-ilk-650/igt@i915_selftest@live_hangcheck.html - fi-elk-e7500: [PASS][24] -> [DMESG-WARN][25] [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-elk-e7500/igt@i915_selftest@live_hangcheck.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-elk-e7500/igt@i915_selftest@live_hangcheck.html - fi-cfl-guc: [PASS][26] -> [DMESG-WARN][27] [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-cfl-guc/igt@i915_selftest@live_hangcheck.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-cfl-guc/igt@i915_selftest@live_hangcheck.html - fi-skl-iommu: [PASS][28] -> [DMESG-WARN][29] [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html - fi-glk-dsi: [PASS][30] -> [DMESG-WARN][31] [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-glk-dsi/igt@i915_selftest@live_hangcheck.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-glk-dsi/igt@i915_selftest@live_hangcheck.html - fi-skl-gvtdvm: [PASS][32] -> [DMESG-WARN][33] [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-skl-gvtdvm/igt@i915_selftest@live_hangcheck.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-skl-gvtdvm/igt@i915_selftest@live_hangcheck.html - fi-kbl-x1275: [PASS][34] -> [DMESG-WARN][35] [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-kbl-x1275/igt@i915_selftest@live_hangcheck.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-kbl-x1275/igt@i915_selftest@live_hangcheck.html - fi-icl-u3: [PASS][36] -> [DMESG-WARN][37] [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-icl-u3/igt@i915_selftest@live_hangcheck.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-icl-u3/igt@i915_selftest@live_hangcheck.html - fi-cml-u: [PASS][38] -> [DMESG-WARN][39] [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-cml-u/igt@i915_selftest@live_hangcheck.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-cml-u/igt@i915_selftest@live_hangcheck.html - fi-kbl-7500u: [PASS][40] -> [DMESG-WARN][41] [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-kbl-7500u/igt@i915_selftest@live_hangcheck.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-kbl-7500u/igt@i915_selftest@live_hangcheck.html - fi-kbl-guc: [PASS][42] -> [DMESG-WARN][43] [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-kbl-guc/igt@i915_selftest@live_hangcheck.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-kbl-guc/igt@i915_selftest@live_hangcheck.html - fi-kbl-8809g: [PASS][44] -> [DMESG-WARN][45] [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-kbl-8809g/igt@i915_selftest@live_hangcheck.html [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-kbl-8809g/igt@i915_selftest@live_hangcheck.html - fi-apl-guc: [PASS][46] -> [DMESG-WARN][47] [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-apl-guc/igt@i915_selftest@live_hangcheck.html [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-apl-guc/igt@i915_selftest@live_hangcheck.html - fi-icl-y: [PASS][48] -> [DMESG-WARN][49] [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-icl-y/igt@i915_selftest@live_hangcheck.html [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-icl-y/igt@i915_selftest@live_hangcheck.html - fi-cml-u2: [PASS][50] -> [DMESG-WARN][51] [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-cml-u2/igt@i915_selftest@live_hangcheck.html [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-cml-u2/igt@i915_selftest@live_hangcheck.html - fi-skl-6600u: [PASS][52] -> [DMESG-WARN][53] [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-skl-6600u/igt@i915_selftest@live_hangcheck.html [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-skl-6600u/igt@i915_selftest@live_hangcheck.html - fi-byt-j1900: [PASS][54] -> [DMESG-WARN][55] [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-byt-j1900/igt@i915_selftest@live_hangcheck.html [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-byt-j1900/igt@i915_selftest@live_hangcheck.html - fi-hsw-4770: [PASS][56] -> [DMESG-WARN][57] [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-hsw-4770/igt@i915_selftest@live_hangcheck.html [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-hsw-4770/igt@i915_selftest@live_hangcheck.html - fi-skl-6770hq: [PASS][58] -> [DMESG-WARN][59] [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-skl-6770hq/igt@i915_selftest@live_hangcheck.html [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-skl-6770hq/igt@i915_selftest@live_hangcheck.html - fi-byt-n2820: [PASS][60] -> [DMESG-WARN][61] [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-byt-n2820/igt@i915_selftest@live_hangcheck.html [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-byt-n2820/igt@i915_selftest@live_hangcheck.html - fi-ivb-3770: [PASS][62] -> [DMESG-WARN][63] [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-ivb-3770/igt@i915_selftest@live_hangcheck.html [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-ivb-3770/igt@i915_selftest@live_hangcheck.html - fi-skl-6700k2: [PASS][64] -> [DMESG-WARN][65] [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-skl-6700k2/igt@i915_selftest@live_hangcheck.html [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-skl-6700k2/igt@i915_selftest@live_hangcheck.html - fi-skl-lmem: [PASS][66] -> [DMESG-WARN][67] [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-skl-lmem/igt@i915_selftest@live_hangcheck.html [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-skl-lmem/igt@i915_selftest@live_hangcheck.html - fi-skl-6260u: [PASS][68] -> [DMESG-WARN][69] [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-skl-6260u/igt@i915_selftest@live_hangcheck.html [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-skl-6260u/igt@i915_selftest@live_hangcheck.html - fi-snb-2600: [PASS][70] -> [DMESG-WARN][71] [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-snb-2600/igt@i915_selftest@live_hangcheck.html [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-snb-2600/igt@i915_selftest@live_hangcheck.html - fi-hsw-4770r: [PASS][72] -> [DMESG-WARN][73] [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-hsw-4770r/igt@i915_selftest@live_hangcheck.html [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-hsw-4770r/igt@i915_selftest@live_hangcheck.html Known issues ------------ Here are the changes found in Patchwork_13265 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: [PASS][74] -> [INCOMPLETE][75] ([fdo#107718]) [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html * igt@i915_selftest@live_hangcheck: - fi-bxt-j4205: [PASS][76] -> [DMESG-WARN][77] ([fdo#109385]) [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-bxt-j4205/igt@i915_selftest@live_hangcheck.html [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-bxt-j4205/igt@i915_selftest@live_hangcheck.html - fi-bsw-kefka: [PASS][78] -> [DMESG-WARN][79] ([fdo#109385]) [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-bsw-kefka/igt@i915_selftest@live_hangcheck.html [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-bsw-kefka/igt@i915_selftest@live_hangcheck.html - fi-bxt-dsi: [PASS][80] -> [DMESG-WARN][81] ([fdo#109385]) [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-bxt-dsi/igt@i915_selftest@live_hangcheck.html [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-bxt-dsi/igt@i915_selftest@live_hangcheck.html - fi-bsw-n3050: [PASS][82] -> [DMESG-WARN][83] ([fdo#109385]) [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-bsw-n3050/igt@i915_selftest@live_hangcheck.html [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-bsw-n3050/igt@i915_selftest@live_hangcheck.html #### Possible fixes #### * igt@gem_busy@busy-all: - fi-icl-guc: [INCOMPLETE][84] ([fdo#107713]) -> [PASS][85] [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-icl-guc/igt@gem_busy@busy-all.html [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-icl-guc/igt@gem_busy@busy-all.html * igt@gem_ctx_create@basic-files: - fi-icl-u2: [INCOMPLETE][86] ([fdo#107713] / [fdo#109100]) -> [PASS][87] [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-icl-u2/igt@gem_ctx_create@basic-files.html [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-icl-u2/igt@gem_ctx_create@basic-files.html [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100 [fdo#109385]: https://bugs.freedesktop.org/show_bug.cgi?id=109385 Participating hosts (53 -> 46) ------------------------------ Additional (1): fi-icl-dsi Missing (8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-hsw-peppy fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_6253 -> Patchwork_13265 CI_DRM_6253: 83fdc69645c5c6b511e36e171f1c75a6132f007c @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5054: 7a295df596fdf71e5c28ecb1fbfec002060e9293 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13265: 8d914dd82cd7269846d6c328edfdfb6ac9d626b3 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 8d914dd82cd7 drm/i915: Track ggtt fence reservations under its own mutex 6e042e229f1d drm/i915: Move fence register tracking from i915->mm to ggtt c4b1fa3b38d7 drm/i915: Avoid tainting i915_gem_park() with wakeref.lock 2fa70e0be054 drm/i915: Refine placement of gt.reset_lockmap == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/ _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: ✗ Fi.CI.BAT: failure for series starting with [1/4] drm/i915: Refine placement of gt.reset_lockmap 2019-06-13 7:10 ` ✗ Fi.CI.BAT: failure " Patchwork @ 2019-06-13 7:15 ` Chris Wilson 2019-06-13 7:19 ` Chris Wilson 0 siblings, 1 reply; 8+ messages in thread From: Chris Wilson @ 2019-06-13 7:15 UTC (permalink / raw) To: Patchwork; +Cc: intel-gfx Quoting Patchwork (2019-06-13 08:10:55) > == Series Details == > > Series: series starting with [1/4] drm/i915: Refine placement of gt.reset_lockmap > URL : https://patchwork.freedesktop.org/series/61991/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_6253 -> Patchwork_13265 > ==================================================== > > Summary > ------- > > **FAILURE** > > Serious unknown changes coming with Patchwork_13265 absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_13265, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/ > > Possible new issues > ------------------- > > Here are the unknown changes that may have been introduced in Patchwork_13265: > > ### IGT changes ### > > #### Possible regressions #### > > * igt@i915_selftest@live_hangcheck: > - fi-bdw-gvtdvm: [PASS][1] -> [DMESG-WARN][2] > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-bdw-gvtdvm/igt@i915_selftest@live_hangcheck.html > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-bdw-gvtdvm/igt@i915_selftest@live_hangcheck.html > - fi-bdw-5557u: [PASS][3] -> [DMESG-WARN][4] > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-bdw-5557u/igt@i915_selftest@live_hangcheck.html > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-bdw-5557u/igt@i915_selftest@live_hangcheck.html > - fi-bwr-2160: [PASS][5] -> [DMESG-WARN][6] > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-bwr-2160/igt@i915_selftest@live_hangcheck.html > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-bwr-2160/igt@i915_selftest@live_hangcheck.html > - fi-kbl-r: [PASS][7] -> [DMESG-WARN][8] > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-kbl-r/igt@i915_selftest@live_hangcheck.html > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-kbl-r/igt@i915_selftest@live_hangcheck.html > - fi-kbl-7567u: [PASS][9] -> [DMESG-WARN][10] > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-kbl-7567u/igt@i915_selftest@live_hangcheck.html > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-kbl-7567u/igt@i915_selftest@live_hangcheck.html > - fi-skl-guc: [PASS][11] -> [DMESG-WARN][12] > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-skl-guc/igt@i915_selftest@live_hangcheck.html > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-skl-guc/igt@i915_selftest@live_hangcheck.html > - fi-cfl-8109u: [PASS][13] -> [DMESG-WARN][14] > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-cfl-8109u/igt@i915_selftest@live_hangcheck.html > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-cfl-8109u/igt@i915_selftest@live_hangcheck.html > - fi-snb-2520m: [PASS][15] -> [DMESG-WARN][16] > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-snb-2520m/igt@i915_selftest@live_hangcheck.html > [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-snb-2520m/igt@i915_selftest@live_hangcheck.html > - fi-cfl-8700k: [PASS][17] -> [DMESG-WARN][18] > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-cfl-8700k/igt@i915_selftest@live_hangcheck.html > [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-cfl-8700k/igt@i915_selftest@live_hangcheck.html > - fi-whl-u: [PASS][19] -> [DMESG-WARN][20] > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-whl-u/igt@i915_selftest@live_hangcheck.html > [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-whl-u/igt@i915_selftest@live_hangcheck.html > - fi-icl-u2: NOTRUN -> [DMESG-WARN][21] > [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-icl-u2/igt@i915_selftest@live_hangcheck.html > - fi-ilk-650: [PASS][22] -> [DMESG-WARN][23] > [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-ilk-650/igt@i915_selftest@live_hangcheck.html > [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-ilk-650/igt@i915_selftest@live_hangcheck.html > - fi-elk-e7500: [PASS][24] -> [DMESG-WARN][25] > [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-elk-e7500/igt@i915_selftest@live_hangcheck.html > [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-elk-e7500/igt@i915_selftest@live_hangcheck.html > - fi-cfl-guc: [PASS][26] -> [DMESG-WARN][27] > [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-cfl-guc/igt@i915_selftest@live_hangcheck.html > [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-cfl-guc/igt@i915_selftest@live_hangcheck.html > - fi-skl-iommu: [PASS][28] -> [DMESG-WARN][29] > [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html > [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html > - fi-glk-dsi: [PASS][30] -> [DMESG-WARN][31] > [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-glk-dsi/igt@i915_selftest@live_hangcheck.html > [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-glk-dsi/igt@i915_selftest@live_hangcheck.html > - fi-skl-gvtdvm: [PASS][32] -> [DMESG-WARN][33] > [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-skl-gvtdvm/igt@i915_selftest@live_hangcheck.html > [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-skl-gvtdvm/igt@i915_selftest@live_hangcheck.html > - fi-kbl-x1275: [PASS][34] -> [DMESG-WARN][35] > [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-kbl-x1275/igt@i915_selftest@live_hangcheck.html > [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-kbl-x1275/igt@i915_selftest@live_hangcheck.html > - fi-icl-u3: [PASS][36] -> [DMESG-WARN][37] > [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-icl-u3/igt@i915_selftest@live_hangcheck.html > [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-icl-u3/igt@i915_selftest@live_hangcheck.html > - fi-cml-u: [PASS][38] -> [DMESG-WARN][39] > [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-cml-u/igt@i915_selftest@live_hangcheck.html > [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-cml-u/igt@i915_selftest@live_hangcheck.html > - fi-kbl-7500u: [PASS][40] -> [DMESG-WARN][41] > [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-kbl-7500u/igt@i915_selftest@live_hangcheck.html > [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-kbl-7500u/igt@i915_selftest@live_hangcheck.html > - fi-kbl-guc: [PASS][42] -> [DMESG-WARN][43] > [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-kbl-guc/igt@i915_selftest@live_hangcheck.html > [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-kbl-guc/igt@i915_selftest@live_hangcheck.html > - fi-kbl-8809g: [PASS][44] -> [DMESG-WARN][45] > [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-kbl-8809g/igt@i915_selftest@live_hangcheck.html > [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-kbl-8809g/igt@i915_selftest@live_hangcheck.html > - fi-apl-guc: [PASS][46] -> [DMESG-WARN][47] > [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-apl-guc/igt@i915_selftest@live_hangcheck.html > [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-apl-guc/igt@i915_selftest@live_hangcheck.html > - fi-icl-y: [PASS][48] -> [DMESG-WARN][49] > [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-icl-y/igt@i915_selftest@live_hangcheck.html > [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-icl-y/igt@i915_selftest@live_hangcheck.html > - fi-cml-u2: [PASS][50] -> [DMESG-WARN][51] > [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-cml-u2/igt@i915_selftest@live_hangcheck.html > [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-cml-u2/igt@i915_selftest@live_hangcheck.html > - fi-skl-6600u: [PASS][52] -> [DMESG-WARN][53] > [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-skl-6600u/igt@i915_selftest@live_hangcheck.html > [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-skl-6600u/igt@i915_selftest@live_hangcheck.html > - fi-byt-j1900: [PASS][54] -> [DMESG-WARN][55] > [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-byt-j1900/igt@i915_selftest@live_hangcheck.html > [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-byt-j1900/igt@i915_selftest@live_hangcheck.html > - fi-hsw-4770: [PASS][56] -> [DMESG-WARN][57] > [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-hsw-4770/igt@i915_selftest@live_hangcheck.html > [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-hsw-4770/igt@i915_selftest@live_hangcheck.html > - fi-skl-6770hq: [PASS][58] -> [DMESG-WARN][59] > [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-skl-6770hq/igt@i915_selftest@live_hangcheck.html > [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-skl-6770hq/igt@i915_selftest@live_hangcheck.html > - fi-byt-n2820: [PASS][60] -> [DMESG-WARN][61] > [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-byt-n2820/igt@i915_selftest@live_hangcheck.html > [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-byt-n2820/igt@i915_selftest@live_hangcheck.html > - fi-ivb-3770: [PASS][62] -> [DMESG-WARN][63] > [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-ivb-3770/igt@i915_selftest@live_hangcheck.html > [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-ivb-3770/igt@i915_selftest@live_hangcheck.html > - fi-skl-6700k2: [PASS][64] -> [DMESG-WARN][65] > [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-skl-6700k2/igt@i915_selftest@live_hangcheck.html > [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-skl-6700k2/igt@i915_selftest@live_hangcheck.html > - fi-skl-lmem: [PASS][66] -> [DMESG-WARN][67] > [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-skl-lmem/igt@i915_selftest@live_hangcheck.html > [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-skl-lmem/igt@i915_selftest@live_hangcheck.html > - fi-skl-6260u: [PASS][68] -> [DMESG-WARN][69] > [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-skl-6260u/igt@i915_selftest@live_hangcheck.html > [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-skl-6260u/igt@i915_selftest@live_hangcheck.html > - fi-snb-2600: [PASS][70] -> [DMESG-WARN][71] > [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-snb-2600/igt@i915_selftest@live_hangcheck.html > [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-snb-2600/igt@i915_selftest@live_hangcheck.html > - fi-hsw-4770r: [PASS][72] -> [DMESG-WARN][73] > [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-hsw-4770r/igt@i915_selftest@live_hangcheck.html > [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-hsw-4770r/igt@i915_selftest@live_hangcheck.html That's not even my struct_mutex!!!! All cross-links via amdgpu. :| -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: ✗ Fi.CI.BAT: failure for series starting with [1/4] drm/i915: Refine placement of gt.reset_lockmap 2019-06-13 7:15 ` Chris Wilson @ 2019-06-13 7:19 ` Chris Wilson 0 siblings, 0 replies; 8+ messages in thread From: Chris Wilson @ 2019-06-13 7:19 UTC (permalink / raw) To: Patchwork; +Cc: intel-gfx Quoting Chris Wilson (2019-06-13 08:15:47) > Quoting Patchwork (2019-06-13 08:10:55) > > == Series Details == > > > > Series: series starting with [1/4] drm/i915: Refine placement of gt.reset_lockmap > > URL : https://patchwork.freedesktop.org/series/61991/ > > State : failure > > > > == Summary == > > > > CI Bug Log - changes from CI_DRM_6253 -> Patchwork_13265 > > ==================================================== > > > > Summary > > ------- > > > > **FAILURE** > > > > Serious unknown changes coming with Patchwork_13265 absolutely need to be > > verified manually. > > > > If you think the reported changes have nothing to do with the changes > > introduced in Patchwork_13265, please notify your bug team to allow them > > to document this new failure mode, which will reduce false positives in CI. > > > > External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/ > > > > Possible new issues > > ------------------- > > > > Here are the unknown changes that may have been introduced in Patchwork_13265: > > > > ### IGT changes ### > > > > #### Possible regressions #### > > > > * igt@i915_selftest@live_hangcheck: > > - fi-bdw-gvtdvm: [PASS][1] -> [DMESG-WARN][2] > > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-bdw-gvtdvm/igt@i915_selftest@live_hangcheck.html > > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-bdw-gvtdvm/igt@i915_selftest@live_hangcheck.html > > - fi-bdw-5557u: [PASS][3] -> [DMESG-WARN][4] > > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-bdw-5557u/igt@i915_selftest@live_hangcheck.html > > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-bdw-5557u/igt@i915_selftest@live_hangcheck.html > > - fi-bwr-2160: [PASS][5] -> [DMESG-WARN][6] > > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-bwr-2160/igt@i915_selftest@live_hangcheck.html > > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-bwr-2160/igt@i915_selftest@live_hangcheck.html > > - fi-kbl-r: [PASS][7] -> [DMESG-WARN][8] > > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-kbl-r/igt@i915_selftest@live_hangcheck.html > > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-kbl-r/igt@i915_selftest@live_hangcheck.html > > - fi-kbl-7567u: [PASS][9] -> [DMESG-WARN][10] > > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-kbl-7567u/igt@i915_selftest@live_hangcheck.html > > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-kbl-7567u/igt@i915_selftest@live_hangcheck.html > > - fi-skl-guc: [PASS][11] -> [DMESG-WARN][12] > > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-skl-guc/igt@i915_selftest@live_hangcheck.html > > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-skl-guc/igt@i915_selftest@live_hangcheck.html > > - fi-cfl-8109u: [PASS][13] -> [DMESG-WARN][14] > > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-cfl-8109u/igt@i915_selftest@live_hangcheck.html > > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-cfl-8109u/igt@i915_selftest@live_hangcheck.html > > - fi-snb-2520m: [PASS][15] -> [DMESG-WARN][16] > > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-snb-2520m/igt@i915_selftest@live_hangcheck.html > > [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-snb-2520m/igt@i915_selftest@live_hangcheck.html > > - fi-cfl-8700k: [PASS][17] -> [DMESG-WARN][18] > > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-cfl-8700k/igt@i915_selftest@live_hangcheck.html > > [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-cfl-8700k/igt@i915_selftest@live_hangcheck.html > > - fi-whl-u: [PASS][19] -> [DMESG-WARN][20] > > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-whl-u/igt@i915_selftest@live_hangcheck.html > > [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-whl-u/igt@i915_selftest@live_hangcheck.html > > - fi-icl-u2: NOTRUN -> [DMESG-WARN][21] > > [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-icl-u2/igt@i915_selftest@live_hangcheck.html > > - fi-ilk-650: [PASS][22] -> [DMESG-WARN][23] > > [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-ilk-650/igt@i915_selftest@live_hangcheck.html > > [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-ilk-650/igt@i915_selftest@live_hangcheck.html > > - fi-elk-e7500: [PASS][24] -> [DMESG-WARN][25] > > [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-elk-e7500/igt@i915_selftest@live_hangcheck.html > > [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-elk-e7500/igt@i915_selftest@live_hangcheck.html > > - fi-cfl-guc: [PASS][26] -> [DMESG-WARN][27] > > [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-cfl-guc/igt@i915_selftest@live_hangcheck.html > > [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-cfl-guc/igt@i915_selftest@live_hangcheck.html > > - fi-skl-iommu: [PASS][28] -> [DMESG-WARN][29] > > [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html > > [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html > > - fi-glk-dsi: [PASS][30] -> [DMESG-WARN][31] > > [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-glk-dsi/igt@i915_selftest@live_hangcheck.html > > [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-glk-dsi/igt@i915_selftest@live_hangcheck.html > > - fi-skl-gvtdvm: [PASS][32] -> [DMESG-WARN][33] > > [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-skl-gvtdvm/igt@i915_selftest@live_hangcheck.html > > [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-skl-gvtdvm/igt@i915_selftest@live_hangcheck.html > > - fi-kbl-x1275: [PASS][34] -> [DMESG-WARN][35] > > [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-kbl-x1275/igt@i915_selftest@live_hangcheck.html > > [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-kbl-x1275/igt@i915_selftest@live_hangcheck.html > > - fi-icl-u3: [PASS][36] -> [DMESG-WARN][37] > > [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-icl-u3/igt@i915_selftest@live_hangcheck.html > > [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-icl-u3/igt@i915_selftest@live_hangcheck.html > > - fi-cml-u: [PASS][38] -> [DMESG-WARN][39] > > [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-cml-u/igt@i915_selftest@live_hangcheck.html > > [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-cml-u/igt@i915_selftest@live_hangcheck.html > > - fi-kbl-7500u: [PASS][40] -> [DMESG-WARN][41] > > [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-kbl-7500u/igt@i915_selftest@live_hangcheck.html > > [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-kbl-7500u/igt@i915_selftest@live_hangcheck.html > > - fi-kbl-guc: [PASS][42] -> [DMESG-WARN][43] > > [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-kbl-guc/igt@i915_selftest@live_hangcheck.html > > [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-kbl-guc/igt@i915_selftest@live_hangcheck.html > > - fi-kbl-8809g: [PASS][44] -> [DMESG-WARN][45] > > [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-kbl-8809g/igt@i915_selftest@live_hangcheck.html > > [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-kbl-8809g/igt@i915_selftest@live_hangcheck.html > > - fi-apl-guc: [PASS][46] -> [DMESG-WARN][47] > > [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-apl-guc/igt@i915_selftest@live_hangcheck.html > > [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-apl-guc/igt@i915_selftest@live_hangcheck.html > > - fi-icl-y: [PASS][48] -> [DMESG-WARN][49] > > [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-icl-y/igt@i915_selftest@live_hangcheck.html > > [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-icl-y/igt@i915_selftest@live_hangcheck.html > > - fi-cml-u2: [PASS][50] -> [DMESG-WARN][51] > > [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-cml-u2/igt@i915_selftest@live_hangcheck.html > > [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-cml-u2/igt@i915_selftest@live_hangcheck.html > > - fi-skl-6600u: [PASS][52] -> [DMESG-WARN][53] > > [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-skl-6600u/igt@i915_selftest@live_hangcheck.html > > [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-skl-6600u/igt@i915_selftest@live_hangcheck.html > > - fi-byt-j1900: [PASS][54] -> [DMESG-WARN][55] > > [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-byt-j1900/igt@i915_selftest@live_hangcheck.html > > [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-byt-j1900/igt@i915_selftest@live_hangcheck.html > > - fi-hsw-4770: [PASS][56] -> [DMESG-WARN][57] > > [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-hsw-4770/igt@i915_selftest@live_hangcheck.html > > [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-hsw-4770/igt@i915_selftest@live_hangcheck.html > > - fi-skl-6770hq: [PASS][58] -> [DMESG-WARN][59] > > [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-skl-6770hq/igt@i915_selftest@live_hangcheck.html > > [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-skl-6770hq/igt@i915_selftest@live_hangcheck.html > > - fi-byt-n2820: [PASS][60] -> [DMESG-WARN][61] > > [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-byt-n2820/igt@i915_selftest@live_hangcheck.html > > [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-byt-n2820/igt@i915_selftest@live_hangcheck.html > > - fi-ivb-3770: [PASS][62] -> [DMESG-WARN][63] > > [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-ivb-3770/igt@i915_selftest@live_hangcheck.html > > [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-ivb-3770/igt@i915_selftest@live_hangcheck.html > > - fi-skl-6700k2: [PASS][64] -> [DMESG-WARN][65] > > [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-skl-6700k2/igt@i915_selftest@live_hangcheck.html > > [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-skl-6700k2/igt@i915_selftest@live_hangcheck.html > > - fi-skl-lmem: [PASS][66] -> [DMESG-WARN][67] > > [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-skl-lmem/igt@i915_selftest@live_hangcheck.html > > [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-skl-lmem/igt@i915_selftest@live_hangcheck.html > > - fi-skl-6260u: [PASS][68] -> [DMESG-WARN][69] > > [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-skl-6260u/igt@i915_selftest@live_hangcheck.html > > [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-skl-6260u/igt@i915_selftest@live_hangcheck.html > > - fi-snb-2600: [PASS][70] -> [DMESG-WARN][71] > > [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-snb-2600/igt@i915_selftest@live_hangcheck.html > > [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-snb-2600/igt@i915_selftest@live_hangcheck.html > > - fi-hsw-4770r: [PASS][72] -> [DMESG-WARN][73] > > [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6253/fi-hsw-4770r/igt@i915_selftest@live_hangcheck.html > > [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13265/fi-hsw-4770r/igt@i915_selftest@live_hangcheck.html > > That's not even my struct_mutex!!!! All cross-links via amdgpu. :| I have no idea why lockdep thinks struct_mutex was taken there at all. But anyway semi-back to the drawing board. -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2019-06-13 7:19 UTC | newest] Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-06-13 6:20 [PATCH 1/4] drm/i915: Refine placement of gt.reset_lockmap Chris Wilson 2019-06-13 6:20 ` [PATCH 2/4] drm/i915: Avoid tainting i915_gem_park() with wakeref.lock Chris Wilson 2019-06-13 6:20 ` [PATCH 3/4] drm/i915: Move fence register tracking from i915->mm to ggtt Chris Wilson 2019-06-13 6:20 ` [PATCH 4/4] drm/i915: Track ggtt fence reservations under its own mutex Chris Wilson 2019-06-13 6:47 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915: Refine placement of gt.reset_lockmap Patchwork 2019-06-13 7:10 ` ✗ Fi.CI.BAT: failure " Patchwork 2019-06-13 7:15 ` Chris Wilson 2019-06-13 7:19 ` Chris Wilson
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