* [U-Boot] [PATCH 0/4] Update SiFive Unleashed Clock Driver
@ 2019-06-18 9:18 Anup Patel
2019-06-18 9:18 ` [U-Boot] [PATCH 1/4] clk: sifive: Factor-out PLL library as separate module Anup Patel
` (4 more replies)
0 siblings, 5 replies; 7+ messages in thread
From: Anup Patel @ 2019-06-18 9:18 UTC (permalink / raw)
To: u-boot
This series update SiFive Unleashed clock driver so that:
1. It is in sync with upstream Linux driver
2. It uses latest DT bindings as-per upstream Linux driver
With this series, we can now use latest DT bindings with U-Boot. I have
tested SiFive Serial driver and Cadence MACB ethernet driver with this
changes and both work fine.
The legacy FSBL will still pass DTB to U-Boot with older DT bindings
which will break the updated SiFive Unleashed clock driver. To tackle
this, we have embedded DTB in OpenSBI FW_PAYLOAD firmware for SiFive
Unleashed so that OpenSBI will override and pass updated DTB to U-Boot.
In fact, the updated DTB passed by OpenSBI can be used by latest Linux
(i.e. V5.2-rc1 or higher) as well.
The OpenSBI changes to embed SiFive Unleashed DTB can be found in
sifive_unleashed_dtb_fix_v1 branch of:
https://github.com/avpatel/opensbi.git
This series can be found in riscv_unleashed_clk_sync_v1 branch of:
https://github.com/avpatel/u-boot.git
Anup Patel (4):
clk: sifive: Factor-out PLL library as separate module
clk: sifive: Sync-up WRPLL library with upstream Linux
clk: sifive: Sync-up DT bindings header with upstream Linux
clk: sifive: Sync-up main driver with upstream Linux
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/analogbits/Kconfig | 4 +
drivers/clk/analogbits/Makefile | 3 +
.../{sifive => analogbits}/wrpll-cln28hpc.c | 168 ++++++++----------
drivers/clk/sifive/Kconfig | 3 -
drivers/clk/sifive/Makefile | 2 -
drivers/clk/sifive/fu540-prci.c | 123 +++++++------
include/dt-bindings/clk/sifive-fu540-prci.h | 29 ---
include/dt-bindings/clock/sifive-fu540-prci.h | 18 ++
.../linux/clk}/analogbits-wrpll-cln28hpc.h | 70 +++-----
11 files changed, 195 insertions(+), 227 deletions(-)
create mode 100644 drivers/clk/analogbits/Kconfig
create mode 100644 drivers/clk/analogbits/Makefile
rename drivers/clk/{sifive => analogbits}/wrpll-cln28hpc.c (69%)
delete mode 100644 include/dt-bindings/clk/sifive-fu540-prci.h
create mode 100644 include/dt-bindings/clock/sifive-fu540-prci.h
rename {drivers/clk/sifive => include/linux/clk}/analogbits-wrpll-cln28hpc.h (52%)
--
2.17.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH 1/4] clk: sifive: Factor-out PLL library as separate module
2019-06-18 9:18 [U-Boot] [PATCH 0/4] Update SiFive Unleashed Clock Driver Anup Patel
@ 2019-06-18 9:18 ` Anup Patel
2019-06-18 9:18 ` [U-Boot] [PATCH 2/4] clk: sifive: Sync-up WRPLL library with upstream Linux Anup Patel
` (3 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Anup Patel @ 2019-06-18 9:18 UTC (permalink / raw)
To: u-boot
To match SiFive clock driver with latest Linux, we factor-out PLL
library as separate module under drivers/clk/analogbits.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/analogbits/Kconfig | 4 ++++
drivers/clk/analogbits/Makefile | 3 +++
drivers/clk/{sifive => analogbits}/wrpll-cln28hpc.c | 3 +--
drivers/clk/sifive/Kconfig | 3 ---
drivers/clk/sifive/Makefile | 2 --
drivers/clk/sifive/fu540-prci.c | 3 +--
.../sifive => include/linux/clk}/analogbits-wrpll-cln28hpc.h | 0
9 files changed, 11 insertions(+), 9 deletions(-)
create mode 100644 drivers/clk/analogbits/Kconfig
create mode 100644 drivers/clk/analogbits/Makefile
rename drivers/clk/{sifive => analogbits}/wrpll-cln28hpc.c (99%)
rename {drivers/clk/sifive => include/linux/clk}/analogbits-wrpll-cln28hpc.h (100%)
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 96969b9e30..7b81eacf50 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -98,6 +98,7 @@ config CLK_STM32MP1
Enable the STM32 clock (RCC) driver. Enable support for
manipulating STM32MP1's on-SoC clocks.
+source "drivers/clk/analogbits/Kconfig"
source "drivers/clk/at91/Kconfig"
source "drivers/clk/exynos/Kconfig"
source "drivers/clk/imx/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 719b9b8e02..f0ced49e5a 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o
obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_rate.o
obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_factor.o
+obj-y += analogbits/
obj-y += imx/
obj-y += tegra/
obj-$(CONFIG_ARCH_ASPEED) += aspeed/
diff --git a/drivers/clk/analogbits/Kconfig b/drivers/clk/analogbits/Kconfig
new file mode 100644
index 0000000000..1d25e6f124
--- /dev/null
+++ b/drivers/clk/analogbits/Kconfig
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+
+config CLK_ANALOGBITS_WRPLL_CLN28HPC
+ bool
diff --git a/drivers/clk/analogbits/Makefile b/drivers/clk/analogbits/Makefile
new file mode 100644
index 0000000000..ec1bb4092b
--- /dev/null
+++ b/drivers/clk/analogbits/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-$(CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC) += wrpll-cln28hpc.o
diff --git a/drivers/clk/sifive/wrpll-cln28hpc.c b/drivers/clk/analogbits/wrpll-cln28hpc.c
similarity index 99%
rename from drivers/clk/sifive/wrpll-cln28hpc.c
rename to drivers/clk/analogbits/wrpll-cln28hpc.c
index d377849693..68eb1148b9 100644
--- a/drivers/clk/sifive/wrpll-cln28hpc.c
+++ b/drivers/clk/analogbits/wrpll-cln28hpc.c
@@ -35,8 +35,7 @@
#include <linux/err.h>
#include <linux/log2.h>
#include <linux/math64.h>
-
-#include "analogbits-wrpll-cln28hpc.h"
+#include <linux/clk/analogbits-wrpll-cln28hpc.h>
/* MIN_INPUT_FREQ: minimum input clock frequency, in Hz (Fref_min) */
#define MIN_INPUT_FREQ 7000000
diff --git a/drivers/clk/sifive/Kconfig b/drivers/clk/sifive/Kconfig
index 644881b948..d90be1943f 100644
--- a/drivers/clk/sifive/Kconfig
+++ b/drivers/clk/sifive/Kconfig
@@ -1,8 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
-config CLK_ANALOGBITS_WRPLL_CLN28HPC
- bool
-
config CLK_SIFIVE
bool "SiFive SoC driver support"
depends on CLK
diff --git a/drivers/clk/sifive/Makefile b/drivers/clk/sifive/Makefile
index f8263e79b7..0813360ca7 100644
--- a/drivers/clk/sifive/Makefile
+++ b/drivers/clk/sifive/Makefile
@@ -1,7 +1,5 @@
# SPDX-License-Identifier: GPL-2.0+
-obj-$(CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC) += wrpll-cln28hpc.o
-
obj-$(CONFIG_CLK_SIFIVE_FU540_PRCI) += fu540-prci.o
obj-$(CONFIG_CLK_SIFIVE_GEMGXL_MGMT) += gemgxl-mgmt.o
diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c
index 2d47ebc6b1..56084db2e6 100644
--- a/drivers/clk/sifive/fu540-prci.c
+++ b/drivers/clk/sifive/fu540-prci.c
@@ -37,10 +37,9 @@
#include <errno.h>
#include <linux/math64.h>
+#include <linux/clk/analogbits-wrpll-cln28hpc.h>
#include <dt-bindings/clk/sifive-fu540-prci.h>
-#include "analogbits-wrpll-cln28hpc.h"
-
/*
* EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects:
* hfclk and rtcclk
diff --git a/drivers/clk/sifive/analogbits-wrpll-cln28hpc.h b/include/linux/clk/analogbits-wrpll-cln28hpc.h
similarity index 100%
rename from drivers/clk/sifive/analogbits-wrpll-cln28hpc.h
rename to include/linux/clk/analogbits-wrpll-cln28hpc.h
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH 2/4] clk: sifive: Sync-up WRPLL library with upstream Linux
2019-06-18 9:18 [U-Boot] [PATCH 0/4] Update SiFive Unleashed Clock Driver Anup Patel
2019-06-18 9:18 ` [U-Boot] [PATCH 1/4] clk: sifive: Factor-out PLL library as separate module Anup Patel
@ 2019-06-18 9:18 ` Anup Patel
2019-06-18 9:18 ` [U-Boot] [PATCH 3/4] clk: sifive: Sync-up DT bindings header " Anup Patel
` (2 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Anup Patel @ 2019-06-18 9:18 UTC (permalink / raw)
To: u-boot
Now that SiFive clock driver is merged in upstream Linux, we
sync-up WRPLL library used by SiFive clock driver with upstream
Linux sources.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
drivers/clk/analogbits/wrpll-cln28hpc.c | 165 ++++++++----------
drivers/clk/sifive/fu540-prci.c | 26 +--
include/linux/clk/analogbits-wrpll-cln28hpc.h | 70 +++-----
3 files changed, 107 insertions(+), 154 deletions(-)
diff --git a/drivers/clk/analogbits/wrpll-cln28hpc.c b/drivers/clk/analogbits/wrpll-cln28hpc.c
index 68eb1148b9..776ead319a 100644
--- a/drivers/clk/analogbits/wrpll-cln28hpc.c
+++ b/drivers/clk/analogbits/wrpll-cln28hpc.c
@@ -1,20 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (c) 2019 Western Digital Corporation or its affiliates.
- *
- * Copyright (C) 2018 SiFive, Inc.
+ * Copyright (C) 2018-2019 SiFive, Inc.
* Wesley Terpstra
* Paul Walmsley
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
* This library supports configuration parsing and reprogramming of
* the CLN28HPC variant of the Analog Bits Wide Range PLL. The
* intention is for this library to be reusable for any device that
@@ -29,6 +18,7 @@
* References:
* - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
* - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
+ * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
*/
#include <linux/bug.h>
@@ -84,40 +74,38 @@
* range selection.
*
* Return: The RANGE value to be presented to the PLL configuration inputs,
- * or -1 upon error.
+ * or a negative return code upon error.
*/
static int __wrpll_calc_filter_range(unsigned long post_divr_freq)
{
- u8 range;
-
if (post_divr_freq < MIN_POST_DIVR_FREQ ||
post_divr_freq > MAX_POST_DIVR_FREQ) {
WARN(1, "%s: post-divider reference freq out of range: %lu",
__func__, post_divr_freq);
- return -1;
+ return -ERANGE;
}
- if (post_divr_freq < 11000000)
- range = 1;
- else if (post_divr_freq < 18000000)
- range = 2;
- else if (post_divr_freq < 30000000)
- range = 3;
- else if (post_divr_freq < 50000000)
- range = 4;
- else if (post_divr_freq < 80000000)
- range = 5;
- else if (post_divr_freq < 130000000)
- range = 6;
- else
- range = 7;
-
- return range;
+ switch (post_divr_freq) {
+ case 0 ... 10999999:
+ return 1;
+ case 11000000 ... 17999999:
+ return 2;
+ case 18000000 ... 29999999:
+ return 3;
+ case 30000000 ... 49999999:
+ return 4;
+ case 50000000 ... 79999999:
+ return 5;
+ case 80000000 ... 129999999:
+ return 6;
+ }
+
+ return 7;
}
/**
* __wrpll_calc_fbdiv() - return feedback fixed divide value
- * @c: ptr to a struct analogbits_wrpll_cfg record to read from
+ * @c: ptr to a struct wrpll_cfg record to read from
*
* The internal feedback path includes a fixed by-two divider; the
* external feedback path does not. Return the appropriate divider
@@ -132,7 +120,7 @@ static int __wrpll_calc_filter_range(unsigned long post_divr_freq)
* Return: 2 if internal feedback is enabled or 1 if external feedback
* is enabled.
*/
-static u8 __wrpll_calc_fbdiv(struct analogbits_wrpll_cfg *c)
+static u8 __wrpll_calc_fbdiv(const struct wrpll_cfg *c)
{
return (c->flags & WRPLL_FLAGS_INT_FEEDBACK_MASK) ? 2 : 1;
}
@@ -172,7 +160,7 @@ static u8 __wrpll_calc_divq(u32 target_rate, u64 *vco_rate)
*vco_rate = MIN_VCO_FREQ;
} else {
divq = ilog2(s);
- *vco_rate = target_rate << divq;
+ *vco_rate = (u64)target_rate << divq;
}
wcd_out:
@@ -181,7 +169,7 @@ wcd_out:
/**
* __wrpll_update_parent_rate() - update PLL data when parent rate changes
- * @c: ptr to a struct analogbits_wrpll_cfg record to write PLL data to
+ * @c: ptr to a struct wrpll_cfg record to write PLL data to
* @parent_rate: PLL input refclk rate (pre-R-divider)
*
* Pre-compute some data used by the PLL configuration algorithm when
@@ -189,46 +177,40 @@ wcd_out:
* computation when the parent rate remains constant - expected to be
* the common case.
*
- * Returns: 0 upon success or -1 if the reference clock rate is out of range.
+ * Returns: 0 upon success or -ERANGE if the reference clock rate is
+ * out of range.
*/
-static int __wrpll_update_parent_rate(struct analogbits_wrpll_cfg *c,
+static int __wrpll_update_parent_rate(struct wrpll_cfg *c,
unsigned long parent_rate)
{
u8 max_r_for_parent;
if (parent_rate > MAX_INPUT_FREQ || parent_rate < MIN_POST_DIVR_FREQ)
- return -1;
+ return -ERANGE;
- c->_parent_rate = parent_rate;
+ c->parent_rate = parent_rate;
max_r_for_parent = div_u64(parent_rate, MIN_POST_DIVR_FREQ);
- c->_max_r = min_t(u8, MAX_DIVR_DIVISOR, max_r_for_parent);
+ c->max_r = min_t(u8, MAX_DIVR_DIVISOR, max_r_for_parent);
- /* Round up */
- c->_init_r = div_u64(parent_rate + MAX_POST_DIVR_FREQ - 1,
- MAX_POST_DIVR_FREQ);
+ c->init_r = DIV_ROUND_UP_ULL(parent_rate, MAX_POST_DIVR_FREQ);
return 0;
}
-/*
- * Public functions
- */
-
/**
- * analogbits_wrpll_configure() - compute PLL configuration for a target rate
- * @c: ptr to a struct analogbits_wrpll_cfg record to write into
+ * wrpll_configure() - compute PLL configuration for a target rate
+ * @c: ptr to a struct wrpll_cfg record to write into
* @target_rate: target PLL output clock rate (post-Q-divider)
* @parent_rate: PLL input refclk rate (pre-R-divider)
*
- * Given a pointer to a PLL context @c, a desired PLL target output
- * rate @target_rate, and a reference clock input rate @parent_rate,
- * compute the appropriate PLL signal configuration values. PLL
- * reprogramming is not glitchless, so the caller should switch any
- * downstream logic to a different clock source or clock-gate it
- * before presenting these values to the PLL configuration signals.
+ * Compute the appropriate PLL signal configuration values and store
+ * in PLL context @c. PLL reprogramming is not glitchless, so the
+ * caller should switch any downstream logic to a different clock
+ * source or clock-gate it before presenting these values to the PLL
+ * configuration signals.
*
* The caller must pass this function a pre-initialized struct
- * analogbits_wrpll_cfg record: either initialized to zero (with the
+ * wrpll_cfg record: either initialized to zero (with the
* exception of the .name and .flags fields) or read from the PLL.
*
* Context: Any context. Caller must protect the memory pointed to by @c
@@ -236,41 +218,26 @@ static int __wrpll_update_parent_rate(struct analogbits_wrpll_cfg *c,
*
* Return: 0 upon success; anything else upon failure.
*/
-int analogbits_wrpll_configure_for_rate(struct analogbits_wrpll_cfg *c,
- u32 target_rate,
- unsigned long parent_rate)
+int wrpll_configure_for_rate(struct wrpll_cfg *c, u32 target_rate,
+ unsigned long parent_rate)
{
unsigned long ratio;
u64 target_vco_rate, delta, best_delta, f_pre_div, vco, vco_pre;
- u32 best_f, f, post_divr_freq, fbcfg;
+ u32 best_f, f, post_divr_freq;
u8 fbdiv, divq, best_r, r;
-
- if (!c)
- return -1;
+ int range;
if (c->flags == 0) {
WARN(1, "%s called with uninitialized PLL config", __func__);
- return -1;
- }
-
- fbcfg = WRPLL_FLAGS_INT_FEEDBACK_MASK | WRPLL_FLAGS_EXT_FEEDBACK_MASK;
- if ((c->flags & fbcfg) == fbcfg) {
- WARN(1, "%s called with invalid PLL config", __func__);
- return -1;
- }
-
- if (c->flags == WRPLL_FLAGS_EXT_FEEDBACK_MASK) {
- WARN(1, "%s: external feedback mode not currently supported",
- __func__);
- return -1;
+ return -EINVAL;
}
/* Initialize rounding data if it hasn't been initialized already */
- if (parent_rate != c->_parent_rate) {
+ if (parent_rate != c->parent_rate) {
if (__wrpll_update_parent_rate(c, parent_rate)) {
pr_err("%s: PLL input rate is out of range\n",
__func__);
- return -1;
+ return -ERANGE;
}
}
@@ -281,11 +248,12 @@ int analogbits_wrpll_configure_for_rate(struct analogbits_wrpll_cfg *c,
c->flags |= WRPLL_FLAGS_BYPASS_MASK;
return 0;
}
+
c->flags &= ~WRPLL_FLAGS_BYPASS_MASK;
/* Calculate the Q shift and target VCO rate */
divq = __wrpll_calc_divq(target_rate, &target_vco_rate);
- if (divq == 0)
+ if (!divq)
return -1;
c->divq = divq;
@@ -301,8 +269,7 @@ int analogbits_wrpll_configure_for_rate(struct analogbits_wrpll_cfg *c,
* Consider all values for R which land within
* [MIN_POST_DIVR_FREQ, MAX_POST_DIVR_FREQ]; prefer smaller R
*/
- for (r = c->_init_r; r <= c->_max_r; ++r) {
- /* What is the best F we can pick in this case? */
+ for (r = c->init_r; r <= c->max_r; ++r) {
f_pre_div = ratio * r;
f = (f_pre_div + (1 << ROUND_SHIFT)) >> ROUND_SHIFT;
f >>= (fbdiv - 1);
@@ -334,46 +301,54 @@ int analogbits_wrpll_configure_for_rate(struct analogbits_wrpll_cfg *c,
post_divr_freq = div_u64(parent_rate, best_r);
/* Pick the best PLL jitter filter */
- c->range = __wrpll_calc_filter_range(post_divr_freq);
+ range = __wrpll_calc_filter_range(post_divr_freq);
+ if (range < 0)
+ return range;
+ c->range = range;
return 0;
}
/**
- * analogbits_wrpll_calc_output_rate() - calculate the PLL's target output rate
- * @c: ptr to a struct analogbits_wrpll_cfg record to read from
+ * wrpll_calc_output_rate() - calculate the PLL's target output rate
+ * @c: ptr to a struct wrpll_cfg record to read from
* @parent_rate: PLL refclk rate
*
* Given a pointer to the PLL's current input configuration @c and the
* PLL's input reference clock rate @parent_rate (before the R
* pre-divider), calculate the PLL's output clock rate (after the Q
- * post-divider)
+ * post-divider).
*
* Context: Any context. Caller must protect the memory pointed to by @c
* from simultaneous modification.
*
- * Return: the PLL's output clock rate, in Hz.
+ * Return: the PLL's output clock rate, in Hz. The return value from
+ * this function is intended to be convenient to pass directly
+ * to the Linux clock framework; thus there is no explicit
+ * error return value.
*/
-unsigned long analogbits_wrpll_calc_output_rate(struct analogbits_wrpll_cfg *c,
- unsigned long parent_rate)
+unsigned long wrpll_calc_output_rate(const struct wrpll_cfg *c,
+ unsigned long parent_rate)
{
u8 fbdiv;
u64 n;
- WARN(c->flags & WRPLL_FLAGS_EXT_FEEDBACK_MASK,
- "external feedback mode not yet supported");
+ if (c->flags & WRPLL_FLAGS_EXT_FEEDBACK_MASK) {
+ WARN(1, "external feedback mode not yet supported");
+ return ULONG_MAX;
+ }
fbdiv = __wrpll_calc_fbdiv(c);
n = parent_rate * fbdiv * (c->divf + 1);
- n = div_u64(n, (c->divr + 1));
+ n = div_u64(n, c->divr + 1);
n >>= c->divq;
return n;
}
/**
- * analogbits_wrpll_calc_max_lock_us() - return the time for the PLL to lock
- * @c: ptr to a struct analogbits_wrpll_cfg record to read from
+ * wrpll_calc_max_lock_us() - return the time for the PLL to lock
+ * @c: ptr to a struct wrpll_cfg record to read from
*
* Return the minimum amount of time (in microseconds) that the caller
* must wait after reprogramming the PLL to ensure that it is locked
@@ -383,7 +358,7 @@ unsigned long analogbits_wrpll_calc_output_rate(struct analogbits_wrpll_cfg *c,
* Return: the minimum amount of time the caller must wait for the PLL
* to lock (in microseconds)
*/
-unsigned int analogbits_wrpll_calc_max_lock_us(struct analogbits_wrpll_cfg *c)
+unsigned int wrpll_calc_max_lock_us(const struct wrpll_cfg *c)
{
return MAX_LOCK_US;
}
diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c
index 56084db2e6..cdbf35e871 100644
--- a/drivers/clk/sifive/fu540-prci.c
+++ b/drivers/clk/sifive/fu540-prci.c
@@ -174,7 +174,7 @@ struct __prci_data {
* bypass mux is not glitchless.
*/
struct __prci_wrpll_data {
- struct analogbits_wrpll_cfg c;
+ struct wrpll_cfg c;
void (*bypass)(struct __prci_data *pd);
void (*no_bypass)(struct __prci_data *pd);
u8 cfg0_offs;
@@ -244,7 +244,7 @@ static void __prci_writel(u32 v, u32 offs, struct __prci_data *pd)
/**
* __prci_wrpll_unpack() - unpack WRPLL configuration registers into parameters
- * @c: ptr to a struct analogbits_wrpll_cfg record to write config into
+ * @c: ptr to a struct wrpll_cfg record to write config into
* @r: value read from the PRCI PLL configuration register
*
* Given a value @r read from an FU540 PRCI PLL configuration register,
@@ -256,7 +256,7 @@ static void __prci_writel(u32 v, u32 offs, struct __prci_data *pd)
*
* Context: Any context.
*/
-static void __prci_wrpll_unpack(struct analogbits_wrpll_cfg *c, u32 r)
+static void __prci_wrpll_unpack(struct wrpll_cfg *c, u32 r)
{
u32 v;
@@ -287,7 +287,7 @@ static void __prci_wrpll_unpack(struct analogbits_wrpll_cfg *c, u32 r)
/**
* __prci_wrpll_pack() - pack PLL configuration parameters into a register value
- * @c: pointer to a struct analogbits_wrpll_cfg record containing the PLL's cfg
+ * @c: pointer to a struct wrpll_cfg record containing the PLL's cfg
*
* Using a set of WRPLL configuration values pointed to by @c,
* assemble a PRCI PLL configuration register value, and return it to
@@ -300,7 +300,7 @@ static void __prci_wrpll_unpack(struct analogbits_wrpll_cfg *c, u32 r)
* Returns: a value suitable for writing into a PRCI PLL configuration
* register
*/
-static u32 __prci_wrpll_pack(struct analogbits_wrpll_cfg *c)
+static u32 __prci_wrpll_pack(struct wrpll_cfg *c)
{
u32 r = 0;
@@ -348,11 +348,11 @@ static void __prci_wrpll_read_cfg(struct __prci_data *pd,
*/
static void __prci_wrpll_write_cfg(struct __prci_data *pd,
struct __prci_wrpll_data *pwd,
- struct analogbits_wrpll_cfg *c)
+ struct wrpll_cfg *c)
{
__prci_writel(__prci_wrpll_pack(c), pwd->cfg0_offs, pd);
- memcpy(&pwd->c, c, sizeof(struct analogbits_wrpll_cfg));
+ memcpy(&pwd->c, c, sizeof(struct wrpll_cfg));
}
/* Core clock mux control */
@@ -403,7 +403,7 @@ static unsigned long sifive_fu540_prci_wrpll_recalc_rate(
{
struct __prci_wrpll_data *pwd = pc->pwd;
- return analogbits_wrpll_calc_output_rate(&pwd->c, parent_rate);
+ return wrpll_calc_output_rate(&pwd->c, parent_rate);
}
static unsigned long sifive_fu540_prci_wrpll_round_rate(
@@ -412,13 +412,13 @@ static unsigned long sifive_fu540_prci_wrpll_round_rate(
unsigned long *parent_rate)
{
struct __prci_wrpll_data *pwd = pc->pwd;
- struct analogbits_wrpll_cfg c;
+ struct wrpll_cfg c;
memcpy(&c, &pwd->c, sizeof(c));
- analogbits_wrpll_configure_for_rate(&c, rate, *parent_rate);
+ wrpll_configure_for_rate(&c, rate, *parent_rate);
- return analogbits_wrpll_calc_output_rate(&c, *parent_rate);
+ return wrpll_calc_output_rate(&c, *parent_rate);
}
static int sifive_fu540_prci_wrpll_set_rate(struct __prci_clock *pc,
@@ -429,7 +429,7 @@ static int sifive_fu540_prci_wrpll_set_rate(struct __prci_clock *pc,
struct __prci_data *pd = pc->pd;
int r;
- r = analogbits_wrpll_configure_for_rate(&pwd->c, rate, parent_rate);
+ r = wrpll_configure_for_rate(&pwd->c, rate, parent_rate);
if (r)
return -ERANGE;
@@ -438,7 +438,7 @@ static int sifive_fu540_prci_wrpll_set_rate(struct __prci_clock *pc,
__prci_wrpll_write_cfg(pd, pwd, &pwd->c);
- udelay(analogbits_wrpll_calc_max_lock_us(&pwd->c));
+ udelay(wrpll_calc_max_lock_us(&pwd->c));
if (pwd->no_bypass)
pwd->no_bypass(pd);
diff --git a/include/linux/clk/analogbits-wrpll-cln28hpc.h b/include/linux/clk/analogbits-wrpll-cln28hpc.h
index 4432e24749..03279097e1 100644
--- a/include/linux/clk/analogbits-wrpll-cln28hpc.h
+++ b/include/linux/clk/analogbits-wrpll-cln28hpc.h
@@ -1,19 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (c) 2019 Western Digital Corporation or its affiliates.
- *
- * Copyright (C) 2018 SiFive, Inc.
+ * Copyright (C) 2018-2019 SiFive, Inc.
* Wesley Terpstra
* Paul Walmsley
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#ifndef __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H
@@ -25,7 +14,7 @@
#define DIVQ_VALUES 6
/*
- * Bit definitions for struct analogbits_wrpll_cfg.flags
+ * Bit definitions for struct wrpll_cfg.flags
*
* WRPLL_FLAGS_BYPASS_FLAG: if set, the PLL is either in bypass, or should be
* programmed to enter bypass
@@ -34,10 +23,6 @@
* feedback mode
* WRPLL_FLAGS_EXT_FEEDBACK_FLAG: if set, the PLL is configured for external
* feedback mode (not yet supported by this driver)
- *
- * The flags WRPLL_FLAGS_INT_FEEDBACK_FLAG and WRPLL_FLAGS_EXT_FEEDBACK_FLAG are
- * mutually exclusive. If both bits are set, or both are zero, the struct
- * analogbits_wrpll_cfg record is uninitialized or corrupt.
*/
#define WRPLL_FLAGS_BYPASS_SHIFT 0
#define WRPLL_FLAGS_BYPASS_MASK BIT(WRPLL_FLAGS_BYPASS_SHIFT)
@@ -49,53 +34,46 @@
#define WRPLL_FLAGS_EXT_FEEDBACK_MASK BIT(WRPLL_FLAGS_EXT_FEEDBACK_SHIFT)
/**
- * struct analogbits_wrpll_cfg - WRPLL configuration values
- * @divr: reference divider value (6 bits), as presented to the PLL signals.
- * @divf: feedback divider value (9 bits), as presented to the PLL signals.
- * @divq: output divider value (3 bits), as presented to the PLL signals.
- * @flags: PLL configuration flags. See above for more information.
- * @range: PLL loop filter range. See below for more information.
- * @_output_rate_cache: cached output rates, swept across DIVQ.
- * @_parent_rate: PLL refclk rate for which values are valid
- * @_max_r: maximum possible R divider value, given @parent_rate
- * @_init_r: initial R divider value to start the search from
+ * struct wrpll_cfg - WRPLL configuration values
+ * @divr: reference divider value (6 bits), as presented to the PLL signals
+ * @divf: feedback divider value (9 bits), as presented to the PLL signals
+ * @divq: output divider value (3 bits), as presented to the PLL signals
+ * @flags: PLL configuration flags. See above for more information
+ * @range: PLL loop filter range. See below for more information
+ * @output_rate_cache: cached output rates, swept across DIVQ
+ * @parent_rate: PLL refclk rate for which values are valid
+ * @max_r: maximum possible R divider value, given @parent_rate
+ * @init_r: initial R divider value to start the search from
*
* @divr, @divq, @divq, @range represent what the PLL expects to see
* on its input signals. Thus @divr and @divf are the actual divisors
* minus one. @divq is a power-of-two divider; for example, 1 =
* divide-by-2 and 6 = divide-by-64. 0 is an invalid @divq value.
*
- * When initially passing a struct analogbits_wrpll_cfg record, the
+ * When initially passing a struct wrpll_cfg record, the
* record should be zero-initialized with the exception of the @flags
* field. The only flag bits that need to be set are either
* WRPLL_FLAGS_INT_FEEDBACK or WRPLL_FLAGS_EXT_FEEDBACK.
- *
- * Field names beginning with an underscore should be considered
- * private to the wrpll-cln28hpc.c code.
*/
-struct analogbits_wrpll_cfg {
+struct wrpll_cfg {
u8 divr;
u8 divq;
u8 range;
u8 flags;
u16 divf;
- u32 _output_rate_cache[DIVQ_VALUES];
- unsigned long _parent_rate;
- u8 _max_r;
- u8 _init_r;
+/* private: */
+ u32 output_rate_cache[DIVQ_VALUES];
+ unsigned long parent_rate;
+ u8 max_r;
+ u8 init_r;
};
-/*
- * Function prototypes
- */
-
-int analogbits_wrpll_configure_for_rate(struct analogbits_wrpll_cfg *c,
- u32 target_rate,
- unsigned long parent_rate);
+int wrpll_configure_for_rate(struct wrpll_cfg *c, u32 target_rate,
+ unsigned long parent_rate);
-unsigned int analogbits_wrpll_calc_max_lock_us(struct analogbits_wrpll_cfg *c);
+unsigned int wrpll_calc_max_lock_us(const struct wrpll_cfg *c);
-unsigned long analogbits_wrpll_calc_output_rate(struct analogbits_wrpll_cfg *c,
- unsigned long parent_rate);
+unsigned long wrpll_calc_output_rate(const struct wrpll_cfg *c,
+ unsigned long parent_rate);
#endif /* __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH 3/4] clk: sifive: Sync-up DT bindings header with upstream Linux
2019-06-18 9:18 [U-Boot] [PATCH 0/4] Update SiFive Unleashed Clock Driver Anup Patel
2019-06-18 9:18 ` [U-Boot] [PATCH 1/4] clk: sifive: Factor-out PLL library as separate module Anup Patel
2019-06-18 9:18 ` [U-Boot] [PATCH 2/4] clk: sifive: Sync-up WRPLL library with upstream Linux Anup Patel
@ 2019-06-18 9:18 ` Anup Patel
2019-06-18 9:18 ` [U-Boot] [PATCH 4/4] clk: sifive: Sync-up main driver " Anup Patel
2019-06-19 3:11 ` [U-Boot] [PATCH 0/4] Update SiFive Unleashed Clock Driver Troy Benjegerdes
4 siblings, 0 replies; 7+ messages in thread
From: Anup Patel @ 2019-06-18 9:18 UTC (permalink / raw)
To: u-boot
The location and license header of DT bindings header for SiFive
clock driver has changed in upstream Linux hence this patch.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
drivers/clk/sifive/fu540-prci.c | 2 +-
include/dt-bindings/clk/sifive-fu540-prci.h | 29 -------------------
include/dt-bindings/clock/sifive-fu540-prci.h | 18 ++++++++++++
3 files changed, 19 insertions(+), 30 deletions(-)
delete mode 100644 include/dt-bindings/clk/sifive-fu540-prci.h
create mode 100644 include/dt-bindings/clock/sifive-fu540-prci.h
diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c
index cdbf35e871..ceb318e062 100644
--- a/drivers/clk/sifive/fu540-prci.c
+++ b/drivers/clk/sifive/fu540-prci.c
@@ -38,7 +38,7 @@
#include <linux/math64.h>
#include <linux/clk/analogbits-wrpll-cln28hpc.h>
-#include <dt-bindings/clk/sifive-fu540-prci.h>
+#include <dt-bindings/clock/sifive-fu540-prci.h>
/*
* EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects:
diff --git a/include/dt-bindings/clk/sifive-fu540-prci.h b/include/dt-bindings/clk/sifive-fu540-prci.h
deleted file mode 100644
index 531523ea62..0000000000
--- a/include/dt-bindings/clk/sifive-fu540-prci.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2019 Western Digital Corporation or its affiliates.
- *
- * Copyright (C) 2018 SiFive, Inc.
- * Wesley Terpstra
- * Paul Walmsley
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __LINUX_CLK_SIFIVE_FU540_PRCI_H
-#define __LINUX_CLK_SIFIVE_FU540_PRCI_H
-
-/* Clock indexes for use by Device Tree data */
-
-#define PRCI_CLK_COREPLL 0
-#define PRCI_CLK_DDRPLL 1
-#define PRCI_CLK_GEMGXLPLL 2
-#define PRCI_CLK_TLCLK 3
-
-#endif
diff --git a/include/dt-bindings/clock/sifive-fu540-prci.h b/include/dt-bindings/clock/sifive-fu540-prci.h
new file mode 100644
index 0000000000..6a0b70a37d
--- /dev/null
+++ b/include/dt-bindings/clock/sifive-fu540-prci.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018-2019 SiFive, Inc.
+ * Wesley Terpstra
+ * Paul Walmsley
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU540_PRCI_H
+#define __DT_BINDINGS_CLOCK_SIFIVE_FU540_PRCI_H
+
+/* Clock indexes for use by Device Tree data and the PRCI driver */
+
+#define PRCI_CLK_COREPLL 0
+#define PRCI_CLK_DDRPLL 1
+#define PRCI_CLK_GEMGXLPLL 2
+#define PRCI_CLK_TLCLK 3
+
+#endif
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH 4/4] clk: sifive: Sync-up main driver with upstream Linux
2019-06-18 9:18 [U-Boot] [PATCH 0/4] Update SiFive Unleashed Clock Driver Anup Patel
` (2 preceding siblings ...)
2019-06-18 9:18 ` [U-Boot] [PATCH 3/4] clk: sifive: Sync-up DT bindings header " Anup Patel
@ 2019-06-18 9:18 ` Anup Patel
2019-06-19 3:11 ` [U-Boot] [PATCH 0/4] Update SiFive Unleashed Clock Driver Troy Benjegerdes
4 siblings, 0 replies; 7+ messages in thread
From: Anup Patel @ 2019-06-18 9:18 UTC (permalink / raw)
To: u-boot
The DT bindings of SiFive clock driver in upstream Linux has
changes. As-per latest DT bindings, the clock driver takes two
parent clocks and compatible string has also changed.
This patch sync-up SiFive clock driver implementation as-per
upstream Linux so that we now use latest DT bindings.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
drivers/clk/sifive/fu540-prci.c | 96 ++++++++++++++++++++-------------
1 file changed, 60 insertions(+), 36 deletions(-)
diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c
index ceb318e062..ce0769f2d1 100644
--- a/drivers/clk/sifive/fu540-prci.c
+++ b/drivers/clk/sifive/fu540-prci.c
@@ -158,30 +158,32 @@
* PRCI per-device instance data
*/
struct __prci_data {
- void *base;
- struct clk parent;
+ void *va;
+ struct clk parent_hfclk;
+ struct clk parent_rtcclk;
};
/**
* struct __prci_wrpll_data - WRPLL configuration and integration data
* @c: WRPLL current configuration record
- * @bypass: fn ptr to code to bypass the WRPLL (if applicable; else NULL)
- * @no_bypass: fn ptr to code to not bypass the WRPLL (if applicable; else NULL)
+ * @enable_bypass: fn ptr to code to bypass the WRPLL (if applicable; else NULL)
+ * @disable_bypass: fn ptr to code to not bypass the WRPLL (or NULL)
* @cfg0_offs: WRPLL CFG0 register offset (in bytes) from the PRCI base address
*
- * @bypass and @no_bypass are used for WRPLL instances that contain a separate
- * external glitchless clock mux downstream from the PLL. The WRPLL internal
- * bypass mux is not glitchless.
+ * @enable_bypass and @disable_bypass are used for WRPLL instances
+ * that contain a separate external glitchless clock mux downstream
+ * from the PLL. The WRPLL internal bypass mux is not glitchless.
*/
struct __prci_wrpll_data {
struct wrpll_cfg c;
- void (*bypass)(struct __prci_data *pd);
- void (*no_bypass)(struct __prci_data *pd);
+ void (*enable_bypass)(struct __prci_data *pd);
+ void (*disable_bypass)(struct __prci_data *pd);
u8 cfg0_offs;
};
struct __prci_clock;
+/* struct __prci_clock_ops - clock operations */
struct __prci_clock_ops {
int (*set_rate)(struct __prci_clock *pc,
unsigned long rate,
@@ -197,8 +199,7 @@ struct __prci_clock_ops {
* struct __prci_clock - describes a clock device managed by PRCI
* @name: user-readable clock name string - should match the manual
* @parent_name: parent name for this clock
- * @ops: struct clk_ops for the Linux clock framework to use for control
- * @hw: Linux-private clock data
+ * @ops: struct __prci_clock_ops for control
* @pwd: WRPLL-specific data, associated with this clock (if not NULL)
* @pd: PRCI-specific data associated with this clock (if not NULL)
*
@@ -232,12 +233,12 @@ struct __prci_clock {
*/
static u32 __prci_readl(struct __prci_data *pd, u32 offs)
{
- return readl(pd->base + offs);
+ return readl(pd->va + offs);
}
static void __prci_writel(u32 v, u32 offs, struct __prci_data *pd)
{
- return writel(v, pd->base + offs);
+ writel(v, pd->va + offs);
}
/* WRPLL-related private functions */
@@ -279,10 +280,8 @@ static void __prci_wrpll_unpack(struct wrpll_cfg *c, u32 r)
c->flags &= (WRPLL_FLAGS_INT_FEEDBACK_MASK |
WRPLL_FLAGS_EXT_FEEDBACK_MASK);
- if (r & PRCI_COREPLLCFG0_FSE_MASK)
- c->flags |= WRPLL_FLAGS_INT_FEEDBACK_MASK;
- else
- c->flags |= WRPLL_FLAGS_EXT_FEEDBACK_MASK;
+ /* external feedback mode not supported */
+ c->flags |= WRPLL_FLAGS_INT_FEEDBACK_MASK;
}
/**
@@ -300,7 +299,7 @@ static void __prci_wrpll_unpack(struct wrpll_cfg *c, u32 r)
* Returns: a value suitable for writing into a PRCI PLL configuration
* register
*/
-static u32 __prci_wrpll_pack(struct wrpll_cfg *c)
+static u32 __prci_wrpll_pack(const struct wrpll_cfg *c)
{
u32 r = 0;
@@ -308,8 +307,9 @@ static u32 __prci_wrpll_pack(struct wrpll_cfg *c)
r |= c->divf << PRCI_COREPLLCFG0_DIVF_SHIFT;
r |= c->divq << PRCI_COREPLLCFG0_DIVQ_SHIFT;
r |= c->range << PRCI_COREPLLCFG0_RANGE_SHIFT;
- if (c->flags & WRPLL_FLAGS_INT_FEEDBACK_MASK)
- r |= PRCI_COREPLLCFG0_FSE_MASK;
+
+ /* external feedback mode not supported */
+ r |= PRCI_COREPLLCFG0_FSE_MASK;
return r;
}
@@ -352,7 +352,7 @@ static void __prci_wrpll_write_cfg(struct __prci_data *pd,
{
__prci_writel(__prci_wrpll_pack(c), pwd->cfg0_offs, pd);
- memcpy(&pwd->c, c, sizeof(struct wrpll_cfg));
+ memcpy(&pwd->c, c, sizeof(*c));
}
/* Core clock mux control */
@@ -431,17 +431,17 @@ static int sifive_fu540_prci_wrpll_set_rate(struct __prci_clock *pc,
r = wrpll_configure_for_rate(&pwd->c, rate, parent_rate);
if (r)
- return -ERANGE;
+ return r;
- if (pwd->bypass)
- pwd->bypass(pd);
+ if (pwd->enable_bypass)
+ pwd->enable_bypass(pd);
__prci_wrpll_write_cfg(pd, pwd, &pwd->c);
udelay(wrpll_calc_max_lock_us(&pwd->c));
- if (pwd->no_bypass)
- pwd->no_bypass(pd);
+ if (pwd->disable_bypass)
+ pwd->disable_bypass(pd);
return 0;
}
@@ -483,8 +483,8 @@ static const struct __prci_clock_ops sifive_fu540_prci_tlclksel_clk_ops = {
static struct __prci_wrpll_data __prci_corepll_data = {
.cfg0_offs = PRCI_COREPLLCFG0_OFFSET,
- .bypass = __prci_coreclksel_use_hfclk,
- .no_bypass = __prci_coreclksel_use_corepll,
+ .enable_bypass = __prci_coreclksel_use_hfclk,
+ .disable_bypass = __prci_coreclksel_use_corepll,
};
static struct __prci_wrpll_data __prci_ddrpll_data = {
@@ -525,6 +525,27 @@ static struct __prci_clock __prci_init_clocks[] = {
},
};
+static ulong sifive_fu540_prci_parent_rate(struct __prci_clock *pc)
+{
+ ulong parent_rate;
+ struct __prci_clock *p;
+
+ if (strcmp(pc->parent_name, "corepll") == 0) {
+ p = &__prci_init_clocks[PRCI_CLK_COREPLL];
+ if (!p->pd || !p->ops->recalc_rate)
+ return -ENXIO;
+
+ return p->ops->recalc_rate(p, sifive_fu540_prci_parent_rate(p));
+ }
+
+ if (strcmp(pc->parent_name, "rtcclk") == 0)
+ parent_rate = clk_get_rate(&pc->pd->parent_rtcclk);
+ else
+ parent_rate = clk_get_rate(&pc->pd->parent_hfclk);
+
+ return parent_rate;
+}
+
static ulong sifive_fu540_prci_get_rate(struct clk *clk)
{
struct __prci_clock *pc;
@@ -536,7 +557,7 @@ static ulong sifive_fu540_prci_get_rate(struct clk *clk)
if (!pc->pd || !pc->ops->recalc_rate)
return -ENXIO;
- return pc->ops->recalc_rate(pc, clk_get_rate(&pc->pd->parent));
+ return pc->ops->recalc_rate(pc, sifive_fu540_prci_parent_rate(pc));
}
static ulong sifive_fu540_prci_set_rate(struct clk *clk, ulong rate)
@@ -551,7 +572,7 @@ static ulong sifive_fu540_prci_set_rate(struct clk *clk, ulong rate)
if (!pc->pd || !pc->ops->set_rate)
return -ENXIO;
- err = pc->ops->set_rate(pc, rate, clk_get_rate(&pc->pd->parent));
+ err = pc->ops->set_rate(pc, rate, sifive_fu540_prci_parent_rate(pc));
if (err)
return err;
@@ -564,11 +585,15 @@ static int sifive_fu540_prci_probe(struct udevice *dev)
struct __prci_clock *pc;
struct __prci_data *pd = dev_get_priv(dev);
- pd->base = (void *)dev_read_addr(dev);
- if (IS_ERR(pd->base))
- return PTR_ERR(pd->base);
+ pd->va = (void *)dev_read_addr(dev);
+ if (IS_ERR(pd->va))
+ return PTR_ERR(pd->va);
+
+ err = clk_get_by_index(dev, 0, &pd->parent_hfclk);
+ if (err)
+ return err;
- err = clk_get_by_index(dev, 0, &pd->parent);
+ err = clk_get_by_index(dev, 1, &pd->parent_rtcclk);
if (err)
return err;
@@ -588,8 +613,7 @@ static struct clk_ops sifive_fu540_prci_ops = {
};
static const struct udevice_id sifive_fu540_prci_ids[] = {
- { .compatible = "sifive,fu540-c000-prci0" },
- { .compatible = "sifive,aloeprci0" },
+ { .compatible = "sifive,fu540-c000-prci" },
{ }
};
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH 0/4] Update SiFive Unleashed Clock Driver
2019-06-18 9:18 [U-Boot] [PATCH 0/4] Update SiFive Unleashed Clock Driver Anup Patel
` (3 preceding siblings ...)
2019-06-18 9:18 ` [U-Boot] [PATCH 4/4] clk: sifive: Sync-up main driver " Anup Patel
@ 2019-06-19 3:11 ` Troy Benjegerdes
2019-06-19 5:42 ` Anup Patel
4 siblings, 1 reply; 7+ messages in thread
From: Troy Benjegerdes @ 2019-06-19 3:11 UTC (permalink / raw)
To: u-boot
> On Jun 18, 2019, at 4:18 AM, Anup Patel <Anup.Patel@wdc.com> wrote:
>
> This series update SiFive Unleashed clock driver so that:
> 1. It is in sync with upstream Linux driver
> 2. It uses latest DT bindings as-per upstream Linux driver
>
> With this series, we can now use latest DT bindings with U-Boot. I have
> tested SiFive Serial driver and Cadence MACB ethernet driver with this
> changes and both work fine.
>
> The legacy FSBL will still pass DTB to U-Boot with older DT bindings
> which will break the updated SiFive Unleashed clock driver. To tackle
> this, we have embedded DTB in OpenSBI FW_PAYLOAD firmware for SiFive
> Unleashed so that OpenSBI will override and pass updated DTB to U-Boot.
>
> In fact, the updated DTB passed by OpenSBI can be used by latest Linux
> (i.e. V5.2-rc1 or higher) as well.
>
> The OpenSBI changes to embed SiFive Unleashed DTB can be found in
> sifive_unleashed_dtb_fix_v1 branch of:
> https://github.com/avpatel/opensbi.git
>
> This series can be found in riscv_unleashed_clk_sync_v1 branch of:
> https://github.com/avpatel/u-boot.git
There are some discrepancies I’m finding in the clocking… If I use the
HiFive_U-Boot as FSBL, it does the following (with some extra debug
code)
U-Boot 2018.09-g8bbdd51-dirty (Jun 18 2019 - 19:46:55 -0700)
DRAM: 2 GiB
MMC:
In: serial
Out: serial
Err: serial
Net: gem_mdc_clk_div: macb_hz: 500000000
gmac0
Hit any key to stop autoboot: 0
Where as the close-to-u-boot master version does this:
U-Boot 2019.07-rc4-05661-gc998035-dirty (Jun 18 2019 - 19:51:10 -0700)
CPU: rv64imafdc
Model: sifive,hifive-unleashed-a00
DRAM: 8 GiB
In: serial at 10010000
Out: serial at 10010000
Err: serial at 10010000
Net: gem_mdc_clk_div: macb_hz: 933333324
For reference, I’ve checked all my changes into the ‘dev/new-dts’ branch
of github.com/tmagik/freedom-u-sdk, and the ‘make test_s’ target will build
and then copy various files to /var/lib/tftpboot to run the test, and assumes
you have a DHCP and TFTP server running locally.
Another issue with the mainline u-boot is it does not have the OTP driver
that the HiFive_U-Boot version does, so when it selects a random mac
address this causes TFTP to fail in one of my test environments.
FYI, the patch applied is:
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 5a6cba5..d21026d 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -813,6 +813,8 @@ static u32 macb_mdc_clk_div(int id, struct macb_device *macb)
unsigned long macb_hz = HIFIVE_ETHERNET_CLK_FREQ;//get_macb_pclk_rate(id);
#endif
+ printf("%s: macb_hz: %d\n", __func__, macb_hz);
+
if (macb_hz < 20000000)
config = MACB_BF(CLK, MACB_CLK_DIV8);
else if (macb_hz < 40000000)
@@ -835,6 +837,7 @@ static u32 gem_mdc_clk_div(int id, struct macb_device *macb)
unsigned long macb_hz = HIFIVE_ETHERNET_CLK_FREQ;//get_macb_pclk_rate(id);
#endif
+ printf("%s: macb_hz: %d\n", __func__, macb_hz);
if (macb_hz < 20000000)
config = GEM_BF(CLK, GEM_CLK_DIV8);
else if (macb_hz < 40000000)
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH 0/4] Update SiFive Unleashed Clock Driver
2019-06-19 3:11 ` [U-Boot] [PATCH 0/4] Update SiFive Unleashed Clock Driver Troy Benjegerdes
@ 2019-06-19 5:42 ` Anup Patel
0 siblings, 0 replies; 7+ messages in thread
From: Anup Patel @ 2019-06-19 5:42 UTC (permalink / raw)
To: u-boot
On Wed, Jun 19, 2019 at 8:41 AM Troy Benjegerdes
<troy.benjegerdes@sifive.com> wrote:
>
>
>
> > On Jun 18, 2019, at 4:18 AM, Anup Patel <Anup.Patel@wdc.com> wrote:
> >
> > This series update SiFive Unleashed clock driver so that:
> > 1. It is in sync with upstream Linux driver
> > 2. It uses latest DT bindings as-per upstream Linux driver
> >
> > With this series, we can now use latest DT bindings with U-Boot. I have
> > tested SiFive Serial driver and Cadence MACB ethernet driver with this
> > changes and both work fine.
> >
> > The legacy FSBL will still pass DTB to U-Boot with older DT bindings
> > which will break the updated SiFive Unleashed clock driver. To tackle
> > this, we have embedded DTB in OpenSBI FW_PAYLOAD firmware for SiFive
> > Unleashed so that OpenSBI will override and pass updated DTB to U-Boot.
> >
> > In fact, the updated DTB passed by OpenSBI can be used by latest Linux
> > (i.e. V5.2-rc1 or higher) as well.
> >
> > The OpenSBI changes to embed SiFive Unleashed DTB can be found in
> > sifive_unleashed_dtb_fix_v1 branch of:
> > https://github.com/avpatel/opensbi.git
> >
> > This series can be found in riscv_unleashed_clk_sync_v1 branch of:
> > https://github.com/avpatel/u-boot.git
>
> There are some discrepancies I’m finding in the clocking… If I use the
> HiFive_U-Boot as FSBL, it does the following (with some extra debug
> code)
>
> U-Boot 2018.09-g8bbdd51-dirty (Jun 18 2019 - 19:46:55 -0700)
>
> DRAM: 2 GiB
> MMC:
> In: serial
> Out: serial
> Err: serial
> Net: gem_mdc_clk_div: macb_hz: 500000000
> gmac0
> Hit any key to stop autoboot: 0
>
> Where as the close-to-u-boot master version does this:
>
> U-Boot 2019.07-rc4-05661-gc998035-dirty (Jun 18 2019 - 19:51:10 -0700)
>
> CPU: rv64imafdc
> Model: sifive,hifive-unleashed-a00
> DRAM: 8 GiB
> In: serial at 10010000
> Out: serial at 10010000
> Err: serial at 10010000
> Net: gem_mdc_clk_div: macb_hz: 933333324
>
> For reference, I’ve checked all my changes into the ‘dev/new-dts’ branch
> of github.com/tmagik/freedom-u-sdk, and the ‘make test_s’ target will build
> and then copy various files to /var/lib/tftpboot to run the test, and assumes
> you have a DHCP and TFTP server running locally.
>
> Another issue with the mainline u-boot is it does not have the OTP driver
> that the HiFive_U-Boot version does, so when it selects a random mac
> address this causes TFTP to fail in one of my test environments.
>
> FYI, the patch applied is:
>
> diff --git a/drivers/net/macb.c b/drivers/net/macb.c
> index 5a6cba5..d21026d 100644
> --- a/drivers/net/macb.c
> +++ b/drivers/net/macb.c
> @@ -813,6 +813,8 @@ static u32 macb_mdc_clk_div(int id, struct macb_device *macb)
> unsigned long macb_hz = HIFIVE_ETHERNET_CLK_FREQ;//get_macb_pclk_rate(id);
> #endif
>
> + printf("%s: macb_hz: %d\n", __func__, macb_hz);
> +
> if (macb_hz < 20000000)
> config = MACB_BF(CLK, MACB_CLK_DIV8);
> else if (macb_hz < 40000000)
> @@ -835,6 +837,7 @@ static u32 gem_mdc_clk_div(int id, struct macb_device *macb)
> unsigned long macb_hz = HIFIVE_ETHERNET_CLK_FREQ;//get_macb_pclk_rate(id);
> #endif
>
> + printf("%s: macb_hz: %d\n", __func__, macb_hz);
> if (macb_hz < 20000000)
> config = GEM_BF(CLK, GEM_CLK_DIV8);
> else if (macb_hz < 40000000)
We had noticed this difference when we first got upstream U-Boot
MACB driver working on SiFive Unleashed board.
The real issue is the hard-coding in HiFive_U-Boot because even the
Linux MACB driver sees different value. The clock frequency we see
upstream U-Boot matches Linux MACB driver because we are using
similar SiFive clock driver. (@Atish, please correct me if I am wrong
here?)
Eventually, we realized that hard-coding in HiFive_U-Boot for MACB
driver is just a HACK. There were lot of such hacks in HiFive_U-Boot
without any GIT history. We trust the upstream Linux drivers more
hence took those as reference for upstream U-Boot.
Regards,
Anup
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2019-06-19 5:42 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-06-18 9:18 [U-Boot] [PATCH 0/4] Update SiFive Unleashed Clock Driver Anup Patel
2019-06-18 9:18 ` [U-Boot] [PATCH 1/4] clk: sifive: Factor-out PLL library as separate module Anup Patel
2019-06-18 9:18 ` [U-Boot] [PATCH 2/4] clk: sifive: Sync-up WRPLL library with upstream Linux Anup Patel
2019-06-18 9:18 ` [U-Boot] [PATCH 3/4] clk: sifive: Sync-up DT bindings header " Anup Patel
2019-06-18 9:18 ` [U-Boot] [PATCH 4/4] clk: sifive: Sync-up main driver " Anup Patel
2019-06-19 3:11 ` [U-Boot] [PATCH 0/4] Update SiFive Unleashed Clock Driver Troy Benjegerdes
2019-06-19 5:42 ` Anup Patel
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