From: Anup Patel <Anup.Patel@wdc.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v3 0/5] Update SiFive Unleashed Drivers
Date: Wed, 19 Jun 2019 07:01:19 +0000 [thread overview]
Message-ID: <20190619070037.11730-1-anup.patel@wdc.com> (raw)
This series update SiFive Unleashed clock driver so that:
1. It is in sync with upstream Linux driver
2. It uses latest DT bindings as-per upstream Linux driver
With this series, we can now use latest DT bindings with U-Boot. I have
tested SiFive Serial driver and Cadence MACB ethernet driver with this
changes and both work fine.
The legacy FSBL will still pass DTB to U-Boot with older DT bindings
which will break the updated SiFive Unleashed clock driver. To tackle
this, we have embedded DTB in OpenSBI FW_PAYLOAD firmware for SiFive
Unleashed so that OpenSBI will override and pass updated DTB to U-Boot.
In fact, the updated DTB passed by OpenSBI can be used by latest Linux
(i.e. V5.2-rc1 or higher) as well.
The OpenSBI changes to embed SiFive Unleashed DTB can be found in
sifive_unleashed_dtb_fix_v3 branch of:
https://github.com/avpatel/opensbi.git
This series can be found in riscv_unleashed_clk_sync_v3 branch of:
https://github.com/avpatel/u-boot.git
Changes since v2:
- Dropped PATCH6 which adds new compatible string to MACB driver because
more changes are required in MACB driver for different ethernet speeds
Changes since v1:
- Dropped GEMGXL clock driver
- Added new compatible string for SiFive MACB ethernet
Anup Patel (5):
clk: sifive: Factor-out PLL library as separate module
clk: sifive: Sync-up WRPLL library with upstream Linux
clk: sifive: Sync-up DT bindings header with upstream Linux
clk: sifive: Sync-up main driver with upstream Linux
clk: sifive: Drop GEMGXL clock driver
board/sifive/fu540/Kconfig | 1 -
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/analogbits/Kconfig | 4 +
drivers/clk/analogbits/Makefile | 3 +
.../{sifive => analogbits}/wrpll-cln28hpc.c | 168 ++++++++----------
drivers/clk/sifive/Kconfig | 10 --
drivers/clk/sifive/Makefile | 4 -
drivers/clk/sifive/fu540-prci.c | 123 +++++++------
drivers/clk/sifive/gemgxl-mgmt.c | 60 -------
include/dt-bindings/clk/sifive-fu540-prci.h | 29 ---
include/dt-bindings/clock/sifive-fu540-prci.h | 18 ++
.../linux/clk}/analogbits-wrpll-cln28hpc.h | 70 +++-----
13 files changed, 195 insertions(+), 297 deletions(-)
create mode 100644 drivers/clk/analogbits/Kconfig
create mode 100644 drivers/clk/analogbits/Makefile
rename drivers/clk/{sifive => analogbits}/wrpll-cln28hpc.c (69%)
delete mode 100644 drivers/clk/sifive/gemgxl-mgmt.c
delete mode 100644 include/dt-bindings/clk/sifive-fu540-prci.h
create mode 100644 include/dt-bindings/clock/sifive-fu540-prci.h
rename {drivers/clk/sifive => include/linux/clk}/analogbits-wrpll-cln28hpc.h (52%)
--
2.17.1
next reply other threads:[~2019-06-19 7:01 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-19 7:01 Anup Patel [this message]
2019-06-19 7:01 ` [U-Boot] [PATCH v3 1/5] clk: sifive: Factor-out PLL library as separate module Anup Patel
2019-06-19 7:01 ` [U-Boot] [PATCH v3 2/5] clk: sifive: Sync-up WRPLL library with upstream Linux Anup Patel
2019-06-19 7:01 ` [U-Boot] [PATCH v3 3/5] clk: sifive: Sync-up DT bindings header " Anup Patel
2019-06-19 7:01 ` [U-Boot] [PATCH v3 4/5] clk: sifive: Sync-up main driver " Anup Patel
2019-06-19 7:01 ` [U-Boot] [PATCH v3 5/5] clk: sifive: Drop GEMGXL clock driver Anup Patel
2019-06-19 7:03 ` [U-Boot] [PATCH v3 0/5] Update SiFive Unleashed Drivers Bin Meng
2019-06-19 8:24 ` Anup Patel
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