From: Mark Rutland <mark.rutland@arm.com> To: Palmer Dabbelt <palmer@sifive.com> Cc: linux-riscv@lists.infradead.org, Paul Walmsley <paul.walmsley@sifive.com>, marco@decred.org, me@carlosedp.com, joel@sing.id.au, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2] RISC-V: Break load reservations during switch_to Date: Wed, 19 Jun 2019 08:36:01 +0100 [thread overview] Message-ID: <20190619073600.GA29918@lakrids.cambridge.arm.com> (raw) In-Reply-To: <20190607222222.15300-1-palmer@sifive.com> On Fri, Jun 07, 2019 at 03:22:22PM -0700, Palmer Dabbelt wrote: > The comment describes why in detail. This was found because QEMU never > gives up load reservations, the issue is unlikely to manifest on real > hardware. > > Thanks to Carlos Eduardo for finding the bug! > @@ -330,6 +330,17 @@ ENTRY(__switch_to) > add a3, a0, a4 > add a4, a1, a4 > REG_S ra, TASK_THREAD_RA_RA(a3) > + /* > + * The Linux ABI allows programs to depend on load reservations being > + * broken on context switches, but the ISA doesn't require that the > + * hardware ever breaks a load reservation. The only way to break a > + * load reservation is with a store conditional, so we emit one here. > + * Since nothing ever takes a load reservation on TASK_THREAD_RA_RA we > + * know this will always fail, but just to be on the safe side this > + * writes the same value that was unconditionally written by the > + * previous instruction. > + */ I suspect that you need to do the same as 32-bit ARM, and clear this in your exception return path, rather than in __switch_to, since handlers for interrupts and other exceptions could leave a dangling reservation. For ARM, the architecture permits a store-exclusive to succeed even if the address differed from the load-exclusive. I don't know if the same applies here, but regardless I believe the case above applies if an IRQ is taken from kernel context, since the handler can manipulate the same variable as the interrupted code. Thanks, Mark.
WARNING: multiple messages have this Message-ID (diff)
From: Mark Rutland <mark.rutland@arm.com> To: Palmer Dabbelt <palmer@sifive.com> Cc: me@carlosedp.com, linux-kernel@vger.kernel.org, joel@sing.id.au, Paul Walmsley <paul.walmsley@sifive.com>, linux-riscv@lists.infradead.org, marco@decred.org Subject: Re: [PATCH v2] RISC-V: Break load reservations during switch_to Date: Wed, 19 Jun 2019 08:36:01 +0100 [thread overview] Message-ID: <20190619073600.GA29918@lakrids.cambridge.arm.com> (raw) In-Reply-To: <20190607222222.15300-1-palmer@sifive.com> On Fri, Jun 07, 2019 at 03:22:22PM -0700, Palmer Dabbelt wrote: > The comment describes why in detail. This was found because QEMU never > gives up load reservations, the issue is unlikely to manifest on real > hardware. > > Thanks to Carlos Eduardo for finding the bug! > @@ -330,6 +330,17 @@ ENTRY(__switch_to) > add a3, a0, a4 > add a4, a1, a4 > REG_S ra, TASK_THREAD_RA_RA(a3) > + /* > + * The Linux ABI allows programs to depend on load reservations being > + * broken on context switches, but the ISA doesn't require that the > + * hardware ever breaks a load reservation. The only way to break a > + * load reservation is with a store conditional, so we emit one here. > + * Since nothing ever takes a load reservation on TASK_THREAD_RA_RA we > + * know this will always fail, but just to be on the safe side this > + * writes the same value that was unconditionally written by the > + * previous instruction. > + */ I suspect that you need to do the same as 32-bit ARM, and clear this in your exception return path, rather than in __switch_to, since handlers for interrupts and other exceptions could leave a dangling reservation. For ARM, the architecture permits a store-exclusive to succeed even if the address differed from the load-exclusive. I don't know if the same applies here, but regardless I believe the case above applies if an IRQ is taken from kernel context, since the handler can manipulate the same variable as the interrupted code. Thanks, Mark. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2019-06-19 7:36 UTC|newest] Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-06-07 22:22 [PATCH v2] RISC-V: Break load reservations during switch_to Palmer Dabbelt 2019-06-07 22:22 ` Palmer Dabbelt 2019-06-08 8:19 ` Christoph Hellwig 2019-06-08 8:19 ` Christoph Hellwig 2019-06-16 17:54 ` Joel Sing 2019-06-16 17:54 ` Joel Sing 2019-06-17 3:09 ` Palmer Dabbelt 2019-06-17 3:09 ` Palmer Dabbelt 2019-06-19 7:36 ` Mark Rutland [this message] 2019-06-19 7:36 ` Mark Rutland 2019-06-21 1:50 ` Palmer Dabbelt 2019-06-21 1:50 ` Palmer Dabbelt
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