* [PATCH 1/2] drm/i915/ehl/dsi: Set lane latency optimization for DW1
@ 2019-06-18 19:59 José Roberto de Souza
2019-06-18 20:00 ` [PATCH 2/2] drm/i915/ehl/dsi: Enable AFE over PPI strap José Roberto de Souza
` (4 more replies)
0 siblings, 5 replies; 12+ messages in thread
From: José Roberto de Souza @ 2019-06-18 19:59 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
From: Vandita Kulkarni <vandita.kulkarni@intel.com>
EHL has 2 additional steps in the DSI sequence, this is one of then
the lane latency optimization for DW1.
BSpec: 20597
Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 11 +++++++++++
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 74448e6bf749..ee85428b309f 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -403,6 +403,17 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
tmp &= ~FRC_LATENCY_OPTIM_MASK;
tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
+ /* For EHL set latency optimization for PCS_DW1 lanes */
+ if (IS_ELKHARTLAKE(dev_priv)) {
+ tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(port));
+ tmp &= ~LATENCY_OPTIM_MASK;
+ tmp |= LATENCY_OPTIM_VAL(0);
+ I915_WRITE(ICL_PORT_PCS_DW1_AUX(port), tmp);
+ tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
+ tmp &= ~LATENCY_OPTIM_MASK;
+ tmp |= LATENCY_OPTIM_VAL(0x1);
+ I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), tmp);
+ }
}
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d6483b5dc8e5..1f2c3ebdf87b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1896,6 +1896,8 @@ enum i915_power_well_id {
#define ICL_PORT_PCS_DW1_GRP(port) _MMIO(_ICL_PORT_PCS_DW_GRP(1, port))
#define ICL_PORT_PCS_DW1_LN0(port) _MMIO(_ICL_PORT_PCS_DW_LN(1, 0, port))
#define COMMON_KEEPER_EN (1 << 26)
+#define LATENCY_OPTIM_MASK (0x3 << 2)
+#define LATENCY_OPTIM_VAL(x) ((x) << 2)
/* CNL/ICL Port TX registers */
#define _CNL_PORT_TX_AE_GRP_OFFSET 0x162340
--
2.22.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/2] drm/i915/ehl/dsi: Enable AFE over PPI strap
2019-06-18 19:59 [PATCH 1/2] drm/i915/ehl/dsi: Set lane latency optimization for DW1 José Roberto de Souza
@ 2019-06-18 20:00 ` José Roberto de Souza
2019-06-19 5:19 ` Kulkarni, Vandita
2019-06-19 22:52 ` Matt Roper
2019-06-18 21:13 ` ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/ehl/dsi: Set lane latency optimization for DW1 Patchwork
` (3 subsequent siblings)
4 siblings, 2 replies; 12+ messages in thread
From: José Roberto de Souza @ 2019-06-18 20:00 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
The other additional step in the DSI sequqence for EHL.
BSpec: 20597
Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 8 ++++++++
drivers/gpu/drm/i915/i915_reg.h | 4 ++++
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index ee85428b309f..3a601c739fc6 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -542,6 +542,14 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp);
}
}
+
+ if (IS_ELKHARTLAKE(dev_priv)) {
+ for_each_dsi_port(port, intel_dsi->ports) {
+ tmp = I915_READ(ICL_DPHY_CHKN(port));
+ tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP;
+ I915_WRITE(ICL_DPHY_CHKN(port), tmp);
+ }
+ }
}
static void gen11_dsi_gate_clocks(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1f2c3ebdf87b..dc7b34cf8b42 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1993,6 +1993,10 @@ enum i915_power_well_id {
#define N_SCALAR(x) ((x) << 24)
#define N_SCALAR_MASK (0x7F << 24)
+#define _ICL_DPHY_CHKN_REG 0x194
+#define ICL_DPHY_CHKN(port) _MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG)
+#define ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP (1 << 7)
+
#define MG_PHY_PORT_LN(ln, port, ln0p1, ln0p2, ln1p1) \
_MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
--
2.22.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/ehl/dsi: Set lane latency optimization for DW1
2019-06-18 19:59 [PATCH 1/2] drm/i915/ehl/dsi: Set lane latency optimization for DW1 José Roberto de Souza
2019-06-18 20:00 ` [PATCH 2/2] drm/i915/ehl/dsi: Enable AFE over PPI strap José Roberto de Souza
@ 2019-06-18 21:13 ` Patchwork
2019-06-19 9:05 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/ehl/dsi: Set lane latency optimization for DW1 (rev3) Patchwork
` (2 subsequent siblings)
4 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2019-06-18 21:13 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/ehl/dsi: Set lane latency optimization for DW1
URL : https://patchwork.freedesktop.org/series/62340/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6299 -> Patchwork_13336
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_13336 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_13336, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13336/
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_13336:
### IGT changes ###
#### Possible regressions ####
* igt@gem_sync@basic-store-each:
- fi-cfl-8109u: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6299/fi-cfl-8109u/igt@gem_sync@basic-store-each.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13336/fi-cfl-8109u/igt@gem_sync@basic-store-each.html
Known issues
------------
Here are the changes found in Patchwork_13336 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_cpu_reloc@basic:
- fi-icl-guc: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713] / [fdo#110246])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6299/fi-icl-guc/igt@gem_cpu_reloc@basic.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13336/fi-icl-guc/igt@gem_cpu_reloc@basic.html
* igt@gem_mmap@basic:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6299/fi-icl-u3/igt@gem_mmap@basic.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13336/fi-icl-u3/igt@gem_mmap@basic.html
#### Possible fixes ####
* igt@gem_cpu_reloc@basic:
- fi-icl-dsi: [INCOMPLETE][7] ([fdo#107713] / [fdo#110246]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6299/fi-icl-dsi/igt@gem_cpu_reloc@basic.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13336/fi-icl-dsi/igt@gem_cpu_reloc@basic.html
* igt@gem_sync@basic-store-each:
- fi-kbl-7567u: [FAIL][9] -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6299/fi-kbl-7567u/igt@gem_sync@basic-store-each.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13336/fi-kbl-7567u/igt@gem_sync@basic-store-each.html
* igt@i915_module_load@reload:
- fi-blb-e6850: [INCOMPLETE][11] ([fdo#107718]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6299/fi-blb-e6850/igt@i915_module_load@reload.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13336/fi-blb-e6850/igt@i915_module_load@reload.html
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: [FAIL][13] ([fdo#108511]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6299/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13336/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live_contexts:
- fi-bdw-gvtdvm: [DMESG-FAIL][15] ([fdo#110235]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6299/fi-bdw-gvtdvm/igt@i915_selftest@live_contexts.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13336/fi-bdw-gvtdvm/igt@i915_selftest@live_contexts.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [DMESG-WARN][17] ([fdo#102614]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6299/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13336/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
[fdo#110235]: https://bugs.freedesktop.org/show_bug.cgi?id=110235
[fdo#110246]: https://bugs.freedesktop.org/show_bug.cgi?id=110246
Participating hosts (44 -> 36)
------------------------------
Additional (1): fi-bdw-5557u
Missing (9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-icl-u2 fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_6299 -> Patchwork_13336
CI_DRM_6299: 2a6cf9f4dc05b77beab4b7d9d1c9f16c7e55a001 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5059: 1f67ee0d09d6513f487f2be74aae9700e755258a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13336: b21627f00857f2c8651fe60110c2b6e367bb0fbc @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
b21627f00857 drm/i915/ehl/dsi: Enable AFE over PPI strap
97747021a921 drm/i915/ehl/dsi: Set lane latency optimization for DW1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13336/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] drm/i915/ehl/dsi: Enable AFE over PPI strap
2019-06-18 20:00 ` [PATCH 2/2] drm/i915/ehl/dsi: Enable AFE over PPI strap José Roberto de Souza
@ 2019-06-19 5:19 ` Kulkarni, Vandita
2019-06-19 5:21 ` Kulkarni, Vandita
2019-06-19 22:52 ` Matt Roper
1 sibling, 1 reply; 12+ messages in thread
From: Kulkarni, Vandita @ 2019-06-19 5:19 UTC (permalink / raw)
To: Souza, Jose, intel-gfx; +Cc: Nikula, Jani
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of José
> Roberto de Souza
> Sent: Wednesday, June 19, 2019 1:30 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>
> Subject: [Intel-gfx] [PATCH 2/2] drm/i915/ehl/dsi: Enable AFE over PPI strap
>
> The other additional step in the DSI sequqence for EHL.
>
> BSpec: 20597
> Cc: Uma Shankar <uma.shankar@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
Looks good to me.
Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Thanks.
Vandita
> drivers/gpu/drm/i915/display/icl_dsi.c | 8 ++++++++
> drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> 2 files changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index ee85428b309f..3a601c739fc6 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -542,6 +542,14 @@ static void gen11_dsi_setup_dphy_timings(struct
> intel_encoder *encoder)
> I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp);
> }
> }
> +
> + if (IS_ELKHARTLAKE(dev_priv)) {
> + for_each_dsi_port(port, intel_dsi->ports) {
> + tmp = I915_READ(ICL_DPHY_CHKN(port));
> + tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP;
> + I915_WRITE(ICL_DPHY_CHKN(port), tmp);
> + }
> + }
> }
>
> static void gen11_dsi_gate_clocks(struct intel_encoder *encoder) diff --git
> a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index
> 1f2c3ebdf87b..dc7b34cf8b42 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1993,6 +1993,10 @@ enum i915_power_well_id {
> #define N_SCALAR(x) ((x) << 24)
> #define N_SCALAR_MASK (0x7F << 24)
>
> +#define _ICL_DPHY_CHKN_REG 0x194
> +#define ICL_DPHY_CHKN(port)
> _MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG)
> +#define ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP (1 << 7)
> +
> #define MG_PHY_PORT_LN(ln, port, ln0p1, ln0p2, ln1p1) \
> _MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
>
> --
> 2.22.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] drm/i915/ehl/dsi: Enable AFE over PPI strap
2019-06-19 5:19 ` Kulkarni, Vandita
@ 2019-06-19 5:21 ` Kulkarni, Vandita
2019-06-19 23:25 ` Souza, Jose
0 siblings, 1 reply; 12+ messages in thread
From: Kulkarni, Vandita @ 2019-06-19 5:21 UTC (permalink / raw)
To: Souza, Jose, 'intel-gfx@lists.freedesktop.org'; +Cc: Nikula, Jani
> -----Original Message-----
> From: Kulkarni, Vandita
> Sent: Wednesday, June 19, 2019 10:49 AM
> To: José Roberto de Souza <jose.souza@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>
> Subject: RE: [Intel-gfx] [PATCH 2/2] drm/i915/ehl/dsi: Enable AFE over PPI strap
>
> > -----Original Message-----
> > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of
> > José Roberto de Souza
> > Sent: Wednesday, June 19, 2019 1:30 AM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Nikula, Jani <jani.nikula@intel.com>
> > Subject: [Intel-gfx] [PATCH 2/2] drm/i915/ehl/dsi: Enable AFE over PPI
> > strap
> >
> > The other additional step in the DSI sequqence for EHL.
A correction in "sequence" will be needed though.
Thanks,
Vandita
> >
> > BSpec: 20597
> > Cc: Uma Shankar <uma.shankar@intel.com>
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> Looks good to me.
> Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>
> Thanks.
> Vandita
> > drivers/gpu/drm/i915/display/icl_dsi.c | 8 ++++++++
> > drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> > 2 files changed, 12 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> > b/drivers/gpu/drm/i915/display/icl_dsi.c
> > index ee85428b309f..3a601c739fc6 100644
> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> > @@ -542,6 +542,14 @@ static void gen11_dsi_setup_dphy_timings(struct
> > intel_encoder *encoder)
> > I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp);
> > }
> > }
> > +
> > + if (IS_ELKHARTLAKE(dev_priv)) {
> > + for_each_dsi_port(port, intel_dsi->ports) {
> > + tmp = I915_READ(ICL_DPHY_CHKN(port));
> > + tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP;
> > + I915_WRITE(ICL_DPHY_CHKN(port), tmp);
> > + }
> > + }
> > }
> >
> > static void gen11_dsi_gate_clocks(struct intel_encoder *encoder) diff
> > --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index
> > 1f2c3ebdf87b..dc7b34cf8b42 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1993,6 +1993,10 @@ enum i915_power_well_id {
> > #define N_SCALAR(x) ((x) << 24)
> > #define N_SCALAR_MASK (0x7F << 24)
> >
> > +#define _ICL_DPHY_CHKN_REG 0x194
> > +#define ICL_DPHY_CHKN(port)
> > _MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG)
> > +#define ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP (1 << 7)
> > +
> > #define MG_PHY_PORT_LN(ln, port, ln0p1, ln0p2, ln1p1) \
> > _MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) -
> > (ln0p1)))
> >
> > --
> > 2.22.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/ehl/dsi: Set lane latency optimization for DW1 (rev3)
2019-06-18 19:59 [PATCH 1/2] drm/i915/ehl/dsi: Set lane latency optimization for DW1 José Roberto de Souza
2019-06-18 20:00 ` [PATCH 2/2] drm/i915/ehl/dsi: Enable AFE over PPI strap José Roberto de Souza
2019-06-18 21:13 ` ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/ehl/dsi: Set lane latency optimization for DW1 Patchwork
@ 2019-06-19 9:05 ` Patchwork
2019-06-19 22:38 ` [PATCH 1/2] drm/i915/ehl/dsi: Set lane latency optimization for DW1 Matt Roper
2019-06-19 23:53 ` ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/ehl/dsi: Set lane latency optimization for DW1 (rev3) Patchwork
4 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2019-06-19 9:05 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/ehl/dsi: Set lane latency optimization for DW1 (rev3)
URL : https://patchwork.freedesktop.org/series/62340/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6301 -> Patchwork_13343
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13343/
Known issues
------------
Here are the changes found in Patchwork_13343 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_basic@basic-all:
- fi-cml-u: [PASS][1] -> [INCOMPLETE][2] ([fdo#110566])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6301/fi-cml-u/igt@gem_exec_basic@basic-all.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13343/fi-cml-u/igt@gem_exec_basic@basic-all.html
* igt@gem_exec_suspend@basic-s3:
- fi-cfl-8109u: [PASS][3] -> [FAIL][4] ([fdo#103375])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6301/fi-cfl-8109u/igt@gem_exec_suspend@basic-s3.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13343/fi-cfl-8109u/igt@gem_exec_suspend@basic-s3.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u2: [PASS][5] -> [INCOMPLETE][6] ([fdo#107713] / [fdo#108569])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6301/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13343/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
#### Possible fixes ####
* igt@gem_ctx_create@basic-files:
- fi-icl-u3: [INCOMPLETE][7] ([fdo#107713] / [fdo#109100]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6301/fi-icl-u3/igt@gem_ctx_create@basic-files.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13343/fi-icl-u3/igt@gem_ctx_create@basic-files.html
* igt@i915_selftest@live_contexts:
- fi-bdw-gvtdvm: [DMESG-FAIL][9] ([fdo#110235]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6301/fi-bdw-gvtdvm/igt@i915_selftest@live_contexts.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13343/fi-bdw-gvtdvm/igt@i915_selftest@live_contexts.html
- fi-skl-gvtdvm: [DMESG-FAIL][11] ([fdo#110235]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6301/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13343/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#110235]: https://bugs.freedesktop.org/show_bug.cgi?id=110235
[fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566
Participating hosts (52 -> 43)
------------------------------
Missing (9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-skl-guc fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_6301 -> Patchwork_13343
CI_DRM_6301: d65ad97b4176e73b5c7edfad404cdd962b528baf @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5060: c6a0e43633a399899278353e452a52bb41ac96e1 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13343: e3e075adedf164a8eba30ba7492c052d741d2eba @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
e3e075adedf1 drm/i915/ehl/dsi: Enable AFE over PPI strap
3d6057b781da drm/i915/ehl/dsi: Set lane latency optimization for DW1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13343/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] drm/i915/ehl/dsi: Set lane latency optimization for DW1
2019-06-18 19:59 [PATCH 1/2] drm/i915/ehl/dsi: Set lane latency optimization for DW1 José Roberto de Souza
` (2 preceding siblings ...)
2019-06-19 9:05 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/ehl/dsi: Set lane latency optimization for DW1 (rev3) Patchwork
@ 2019-06-19 22:38 ` Matt Roper
2019-06-19 23:15 ` Souza, Jose
2019-06-19 23:53 ` ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/ehl/dsi: Set lane latency optimization for DW1 (rev3) Patchwork
4 siblings, 1 reply; 12+ messages in thread
From: Matt Roper @ 2019-06-19 22:38 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: Jani Nikula, intel-gfx
On Tue, Jun 18, 2019 at 12:59:59PM -0700, José Roberto de Souza wrote:
> From: Vandita Kulkarni <vandita.kulkarni@intel.com>
>
> EHL has 2 additional steps in the DSI sequence, this is one of then
> the lane latency optimization for DW1.
>
> BSpec: 20597
> Cc: Uma Shankar <uma.shankar@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 11 +++++++++++
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> 2 files changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 74448e6bf749..ee85428b309f 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -403,6 +403,17 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
> tmp &= ~FRC_LATENCY_OPTIM_MASK;
> tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
> I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
> + /* For EHL set latency optimization for PCS_DW1 lanes */
> + if (IS_ELKHARTLAKE(dev_priv)) {
> + tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(port));
> + tmp &= ~LATENCY_OPTIM_MASK;
> + tmp |= LATENCY_OPTIM_VAL(0);
> + I915_WRITE(ICL_PORT_PCS_DW1_AUX(port), tmp);
> + tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
> + tmp &= ~LATENCY_OPTIM_MASK;
> + tmp |= LATENCY_OPTIM_VAL(0x1);
> + I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), tmp);
> + }
Minor nitpick, but these sequences might be slightly easier to read if
there was a blank line separating each R/M/W chunk.
The changes here look correct according to the description on bspec page
20597 although it looks like the bspec authors forgot to update the
'Valid Values' section for these bits on page 20398; not sure if you
want to file a bspec defect about that or not.
> }
>
> }
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d6483b5dc8e5..1f2c3ebdf87b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1896,6 +1896,8 @@ enum i915_power_well_id {
> #define ICL_PORT_PCS_DW1_GRP(port) _MMIO(_ICL_PORT_PCS_DW_GRP(1, port))
> #define ICL_PORT_PCS_DW1_LN0(port) _MMIO(_ICL_PORT_PCS_DW_LN(1, 0, port))
> #define COMMON_KEEPER_EN (1 << 26)
> +#define LATENCY_OPTIM_MASK (0x3 << 2)
> +#define LATENCY_OPTIM_VAL(x) ((x) << 2)
Should we try to include part of the name of the register in these
definitions (e.g., DW1_LATENCY_OPTIM)? I'm not sure if we should worry
about people mixing up these vs the FRC_LATENCY_OPTIM defines farther
down for the TX_DW2 register.
Up to you on whether you think it's worth clarifying the naming. Either
way,
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>
> /* CNL/ICL Port TX registers */
> #define _CNL_PORT_TX_AE_GRP_OFFSET 0x162340
> --
> 2.22.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] drm/i915/ehl/dsi: Enable AFE over PPI strap
2019-06-18 20:00 ` [PATCH 2/2] drm/i915/ehl/dsi: Enable AFE over PPI strap José Roberto de Souza
2019-06-19 5:19 ` Kulkarni, Vandita
@ 2019-06-19 22:52 ` Matt Roper
2019-06-19 23:16 ` Souza, Jose
1 sibling, 1 reply; 12+ messages in thread
From: Matt Roper @ 2019-06-19 22:52 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: Jani Nikula, intel-gfx
On Tue, Jun 18, 2019 at 01:00:00PM -0700, José Roberto de Souza wrote:
> The other additional step in the DSI sequqence for EHL.
>
> BSpec: 20597
> Cc: Uma Shankar <uma.shankar@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 8 ++++++++
> drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> 2 files changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index ee85428b309f..3a601c739fc6 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -542,6 +542,14 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
> I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp);
> }
> }
> +
> + if (IS_ELKHARTLAKE(dev_priv)) {
> + for_each_dsi_port(port, intel_dsi->ports) {
> + tmp = I915_READ(ICL_DPHY_CHKN(port));
> + tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP;
> + I915_WRITE(ICL_DPHY_CHKN(port), tmp);
> + }
> + }
> }
>
> static void gen11_dsi_gate_clocks(struct intel_encoder *encoder)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1f2c3ebdf87b..dc7b34cf8b42 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1993,6 +1993,10 @@ enum i915_power_well_id {
> #define N_SCALAR(x) ((x) << 24)
> #define N_SCALAR_MASK (0x7F << 24)
>
> +#define _ICL_DPHY_CHKN_REG 0x194
> +#define ICL_DPHY_CHKN(port) _MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG)
> +#define ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP (1 << 7)
> +
Since this is a new register, should we be using REG_BIT() for the bit
definition as described at the top of the file?
Other than that, this all matches the bspec so
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> #define MG_PHY_PORT_LN(ln, port, ln0p1, ln0p2, ln1p1) \
> _MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
>
> --
> 2.22.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] drm/i915/ehl/dsi: Set lane latency optimization for DW1
2019-06-19 22:38 ` [PATCH 1/2] drm/i915/ehl/dsi: Set lane latency optimization for DW1 Matt Roper
@ 2019-06-19 23:15 ` Souza, Jose
0 siblings, 0 replies; 12+ messages in thread
From: Souza, Jose @ 2019-06-19 23:15 UTC (permalink / raw)
To: Roper, Matthew D; +Cc: Nikula, Jani, intel-gfx
On Wed, 2019-06-19 at 15:38 -0700, Matt Roper wrote:
> On Tue, Jun 18, 2019 at 12:59:59PM -0700, José Roberto de Souza
> wrote:
> > From: Vandita Kulkarni <vandita.kulkarni@intel.com>
> >
> > EHL has 2 additional steps in the DSI sequence, this is one of then
> > the lane latency optimization for DW1.
> >
> > BSpec: 20597
> > Cc: Uma Shankar <uma.shankar@intel.com>
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/icl_dsi.c | 11 +++++++++++
> > drivers/gpu/drm/i915/i915_reg.h | 2 ++
> > 2 files changed, 13 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> > b/drivers/gpu/drm/i915/display/icl_dsi.c
> > index 74448e6bf749..ee85428b309f 100644
> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> > @@ -403,6 +403,17 @@ static void
> > gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
> > tmp &= ~FRC_LATENCY_OPTIM_MASK;
> > tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
> > I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
> > + /* For EHL set latency optimization for PCS_DW1 lanes
> > */
> > + if (IS_ELKHARTLAKE(dev_priv)) {
> > + tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(port));
> > + tmp &= ~LATENCY_OPTIM_MASK;
> > + tmp |= LATENCY_OPTIM_VAL(0);
> > + I915_WRITE(ICL_PORT_PCS_DW1_AUX(port), tmp);
> > + tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
> > + tmp &= ~LATENCY_OPTIM_MASK;
> > + tmp |= LATENCY_OPTIM_VAL(0x1);
> > + I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), tmp);
> > + }
>
> Minor nitpick, but these sequences might be slightly easier to read
> if
> there was a blank line separating each R/M/W chunk.
Agreed, I was avoiding change the patch because it is not mine but this
will not hurt anyone.
>
> The changes here look correct according to the description on bspec
> page
> 20597 although it looks like the bspec authors forgot to update the
> 'Valid Values' section for these bits on page 20398; not sure if you
> want to file a bspec defect about that or not.
Well the missing value is 0, that is the default after reset so we are
safe here.
>
> > }
> >
> > }
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index d6483b5dc8e5..1f2c3ebdf87b 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1896,6 +1896,8 @@ enum i915_power_well_id {
> > #define ICL_PORT_PCS_DW1_GRP(port) _MMIO(_ICL_PORT_PCS_DW_GRP(1,
> > port))
> > #define ICL_PORT_PCS_DW1_LN0(port) _MMIO(_ICL_PORT_PCS_DW_LN(1, 0,
> > port))
> > #define COMMON_KEEPER_EN (1 << 26)
> > +#define LATENCY_OPTIM_MASK (0x3 << 2)
> > +#define LATENCY_OPTIM_VAL(x) ((x) << 2)
>
> Should we try to include part of the name of the register in these
> definitions (e.g., DW1_LATENCY_OPTIM)? I'm not sure if we should
> worry
> about people mixing up these vs the FRC_LATENCY_OPTIM defines farther
> down for the TX_DW2 register.
I also prefer to include the register name to the bits but the general
rule is keep consistent with around code or fix everything, as this is
not mine patch I left this way.
>
> Up to you on whether you think it's worth clarifying the
> naming. Either
> way,
>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Thanks
>
> >
> > /* CNL/ICL Port TX registers */
> > #define _CNL_PORT_TX_AE_GRP_OFFSET 0x162340
> > --
> > 2.22.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] drm/i915/ehl/dsi: Enable AFE over PPI strap
2019-06-19 22:52 ` Matt Roper
@ 2019-06-19 23:16 ` Souza, Jose
0 siblings, 0 replies; 12+ messages in thread
From: Souza, Jose @ 2019-06-19 23:16 UTC (permalink / raw)
To: Roper, Matthew D; +Cc: Nikula, Jani, intel-gfx
On Wed, 2019-06-19 at 15:52 -0700, Matt Roper wrote:
> On Tue, Jun 18, 2019 at 01:00:00PM -0700, José Roberto de Souza
> wrote:
> > The other additional step in the DSI sequqence for EHL.
> >
> > BSpec: 20597
> > Cc: Uma Shankar <uma.shankar@intel.com>
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/icl_dsi.c | 8 ++++++++
> > drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> > 2 files changed, 12 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> > b/drivers/gpu/drm/i915/display/icl_dsi.c
> > index ee85428b309f..3a601c739fc6 100644
> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> > @@ -542,6 +542,14 @@ static void
> > gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
> > I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp);
> > }
> > }
> > +
> > + if (IS_ELKHARTLAKE(dev_priv)) {
> > + for_each_dsi_port(port, intel_dsi->ports) {
> > + tmp = I915_READ(ICL_DPHY_CHKN(port));
> > + tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP;
> > + I915_WRITE(ICL_DPHY_CHKN(port), tmp);
> > + }
> > + }
> > }
> >
> > static void gen11_dsi_gate_clocks(struct intel_encoder *encoder)
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 1f2c3ebdf87b..dc7b34cf8b42 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1993,6 +1993,10 @@ enum i915_power_well_id {
> > #define N_SCALAR(x) ((x) << 24)
> > #define N_SCALAR_MASK (0x7F << 24)
> >
> > +#define _ICL_DPHY_CHKN_REG 0x194
> > +#define ICL_DPHY_CHKN(port) _MMIO(_ICL_COMB
> > OPHY(port) + _ICL_DPHY_CHKN_REG)
> > +#define ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP (1 << 7)
> > +
>
> Since this is a new register, should we be using REG_BIT() for the
> bit
> definition as described at the top of the file?
I will do that.
Thanks
>
> Other than that, this all matches the bspec so
>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>
>
> > #define MG_PHY_PORT_LN(ln, port, ln0p1, ln0p2, ln1p1) \
> > _MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) -
> > (ln0p1)))
> >
> > --
> > 2.22.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] drm/i915/ehl/dsi: Enable AFE over PPI strap
2019-06-19 5:21 ` Kulkarni, Vandita
@ 2019-06-19 23:25 ` Souza, Jose
0 siblings, 0 replies; 12+ messages in thread
From: Souza, Jose @ 2019-06-19 23:25 UTC (permalink / raw)
To: Kulkarni, Vandita, intel-gfx; +Cc: Nikula, Jani
On Wed, 2019-06-19 at 10:51 +0530, Kulkarni, Vandita wrote:
> > -----Original Message-----
> > From: Kulkarni, Vandita
> > Sent: Wednesday, June 19, 2019 10:49 AM
> > To: José Roberto de Souza <jose.souza@intel.com>; intel-
> > gfx@lists.freedesktop.org
> > Cc: Nikula, Jani <jani.nikula@intel.com>
> > Subject: RE: [Intel-gfx] [PATCH 2/2] drm/i915/ehl/dsi: Enable AFE
> > over PPI strap
> >
> > > -----Original Message-----
> > > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On
> > > Behalf Of
> > > José Roberto de Souza
> > > Sent: Wednesday, June 19, 2019 1:30 AM
> > > To: intel-gfx@lists.freedesktop.org
> > > Cc: Nikula, Jani <jani.nikula@intel.com>
> > > Subject: [Intel-gfx] [PATCH 2/2] drm/i915/ehl/dsi: Enable AFE
> > > over PPI
> > > strap
> > >
> > > The other additional step in the DSI sequqence for EHL.
> A correction in "sequence" will be needed though.
Thanks, I will fix that.
>
> Thanks,
> Vandita
> > > BSpec: 20597
> > > Cc: Uma Shankar <uma.shankar@intel.com>
> > > Cc: Jani Nikula <jani.nikula@intel.com>
> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > ---
> > Looks good to me.
> > Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> >
> > Thanks.
> > Vandita
> > > drivers/gpu/drm/i915/display/icl_dsi.c | 8 ++++++++
> > > drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> > > 2 files changed, 12 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> > > b/drivers/gpu/drm/i915/display/icl_dsi.c
> > > index ee85428b309f..3a601c739fc6 100644
> > > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> > > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> > > @@ -542,6 +542,14 @@ static void
> > > gen11_dsi_setup_dphy_timings(struct
> > > intel_encoder *encoder)
> > > I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp);
> > > }
> > > }
> > > +
> > > + if (IS_ELKHARTLAKE(dev_priv)) {
> > > + for_each_dsi_port(port, intel_dsi->ports) {
> > > + tmp = I915_READ(ICL_DPHY_CHKN(port));
> > > + tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP;
> > > + I915_WRITE(ICL_DPHY_CHKN(port), tmp);
> > > + }
> > > + }
> > > }
> > >
> > > static void gen11_dsi_gate_clocks(struct intel_encoder *encoder)
> > > diff
> > > --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h index
> > > 1f2c3ebdf87b..dc7b34cf8b42 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -1993,6 +1993,10 @@ enum i915_power_well_id {
> > > #define N_SCALAR(x) ((x) << 24)
> > > #define N_SCALAR_MASK (0x7F << 24)
> > >
> > > +#define _ICL_DPHY_CHKN_REG 0x194
> > > +#define ICL_DPHY_CHKN(port)
> > > _MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG)
> > > +#define ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP (1 << 7)
> > > +
> > > #define MG_PHY_PORT_LN(ln, port, ln0p1, ln0p2, ln1p1) \
> > > _MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) -
> > > (ln0p1)))
> > >
> > > --
> > > 2.22.0
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/ehl/dsi: Set lane latency optimization for DW1 (rev3)
2019-06-18 19:59 [PATCH 1/2] drm/i915/ehl/dsi: Set lane latency optimization for DW1 José Roberto de Souza
` (3 preceding siblings ...)
2019-06-19 22:38 ` [PATCH 1/2] drm/i915/ehl/dsi: Set lane latency optimization for DW1 Matt Roper
@ 2019-06-19 23:53 ` Patchwork
4 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2019-06-19 23:53 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/ehl/dsi: Set lane latency optimization for DW1 (rev3)
URL : https://patchwork.freedesktop.org/series/62340/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6301_full -> Patchwork_13343_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_13343_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_eio@suspend:
- shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([fdo#110913 ]) +2 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6301/shard-kbl4/igt@gem_eio@suspend.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13343/shard-kbl3/igt@gem_eio@suspend.html
* igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrashing:
- shard-apl: [PASS][3] -> [DMESG-WARN][4] ([fdo#110913 ])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6301/shard-apl3/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrashing.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13343/shard-apl6/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrashing.html
* igt@gem_persistent_relocs@forked-thrashing:
- shard-snb: [PASS][5] -> [DMESG-WARN][6] ([fdo#110789] / [fdo#110913 ])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6301/shard-snb7/igt@gem_persistent_relocs@forked-thrashing.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13343/shard-snb6/igt@gem_persistent_relocs@forked-thrashing.html
* igt@i915_suspend@fence-restore-untiled:
- shard-apl: [PASS][7] -> [DMESG-WARN][8] ([fdo#108566]) +7 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6301/shard-apl3/igt@i915_suspend@fence-restore-untiled.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13343/shard-apl6/igt@i915_suspend@fence-restore-untiled.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-wc:
- shard-hsw: [PASS][9] -> [SKIP][10] ([fdo#109271]) +23 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6301/shard-hsw5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-wc.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13343/shard-hsw1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt:
- shard-iclb: [PASS][11] -> [FAIL][12] ([fdo#103167]) +5 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6301/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13343/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_psr@psr2_dpms:
- shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#109441]) +2 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6301/shard-iclb2/igt@kms_psr@psr2_dpms.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13343/shard-iclb8/igt@kms_psr@psr2_dpms.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][15] -> [FAIL][16] ([fdo#99912])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6301/shard-apl6/igt@kms_setmode@basic.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13343/shard-apl4/igt@kms_setmode@basic.html
* igt@kms_sysfs_edid_timing:
- shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#100047])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6301/shard-iclb6/igt@kms_sysfs_edid_timing.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13343/shard-iclb2/igt@kms_sysfs_edid_timing.html
#### Possible fixes ####
* igt@gem_eio@wait-wedge-1us:
- shard-apl: [DMESG-WARN][19] ([fdo#110913 ]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6301/shard-apl2/igt@gem_eio@wait-wedge-1us.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13343/shard-apl1/igt@gem_eio@wait-wedge-1us.html
* igt@gem_eio@wait-wedge-immediate:
- shard-kbl: [DMESG-WARN][21] ([fdo#110913 ]) -> [PASS][22] +1 similar issue
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6301/shard-kbl3/igt@gem_eio@wait-wedge-immediate.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13343/shard-kbl1/igt@gem_eio@wait-wedge-immediate.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-apl: [DMESG-WARN][23] ([fdo#108566]) -> [PASS][24] +2 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6301/shard-apl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13343/shard-apl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-b-cursor-128x42-onscreen:
- shard-kbl: [FAIL][25] ([fdo#103232]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6301/shard-kbl3/igt@kms_cursor_crc@pipe-b-cursor-128x42-onscreen.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13343/shard-kbl1/igt@kms_cursor_crc@pipe-b-cursor-128x42-onscreen.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-glk: [FAIL][27] ([fdo#104873]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6301/shard-glk9/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13343/shard-glk8/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [SKIP][29] ([fdo#109349]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6301/shard-iclb3/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13343/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
* igt@kms_flip@2x-plain-flip-interruptible:
- shard-hsw: [SKIP][31] ([fdo#109271]) -> [PASS][32] +18 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6301/shard-hsw1/igt@kms_flip@2x-plain-flip-interruptible.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13343/shard-hsw6/igt@kms_flip@2x-plain-flip-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite:
- shard-iclb: [FAIL][33] ([fdo#103167]) -> [PASS][34] +6 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6301/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13343/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: [FAIL][35] ([fdo#103166]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6301/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-x.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13343/shard-iclb1/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_psr@psr2_primary_blt:
- shard-iclb: [SKIP][37] ([fdo#109441]) -> [PASS][38] +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6301/shard-iclb6/igt@kms_psr@psr2_primary_blt.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13343/shard-iclb2/igt@kms_psr@psr2_primary_blt.html
* igt@tools_test@tools_test:
- shard-glk: [SKIP][39] ([fdo#109271]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6301/shard-glk4/igt@tools_test@tools_test.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13343/shard-glk3/igt@tools_test@tools_test.html
[fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#104873]: https://bugs.freedesktop.org/show_bug.cgi?id=104873
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110789]: https://bugs.freedesktop.org/show_bug.cgi?id=110789
[fdo#110913 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110913
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_6301 -> Patchwork_13343
CI_DRM_6301: d65ad97b4176e73b5c7edfad404cdd962b528baf @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5060: c6a0e43633a399899278353e452a52bb41ac96e1 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13343: e3e075adedf164a8eba30ba7492c052d741d2eba @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13343/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2019-06-19 23:53 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-06-18 19:59 [PATCH 1/2] drm/i915/ehl/dsi: Set lane latency optimization for DW1 José Roberto de Souza
2019-06-18 20:00 ` [PATCH 2/2] drm/i915/ehl/dsi: Enable AFE over PPI strap José Roberto de Souza
2019-06-19 5:19 ` Kulkarni, Vandita
2019-06-19 5:21 ` Kulkarni, Vandita
2019-06-19 23:25 ` Souza, Jose
2019-06-19 22:52 ` Matt Roper
2019-06-19 23:16 ` Souza, Jose
2019-06-18 21:13 ` ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/ehl/dsi: Set lane latency optimization for DW1 Patchwork
2019-06-19 9:05 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/ehl/dsi: Set lane latency optimization for DW1 (rev3) Patchwork
2019-06-19 22:38 ` [PATCH 1/2] drm/i915/ehl/dsi: Set lane latency optimization for DW1 Matt Roper
2019-06-19 23:15 ` Souza, Jose
2019-06-19 23:53 ` ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/ehl/dsi: Set lane latency optimization for DW1 (rev3) Patchwork
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