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* [PATCH v2 1/2] drm/i915/guc: reorder enable/disable communication steps
@ 2019-06-21 18:21 Daniele Ceraolo Spurio
  2019-06-21 18:21 ` [PATCH v2 2/2] drm/i915/guc: handle GuC messages received with CTB disabled Daniele Ceraolo Spurio
                   ` (2 more replies)
  0 siblings, 3 replies; 6+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-06-21 18:21 UTC (permalink / raw)
  To: intel-gfx

Make sure we always have CT buffers enabled when the interrupts are
enabled, so we can always handle interrupts from GuC. Also move the
setting of the guc->send and guc->handler functions to the GuC
communication control functions for consistency.

The reorder also fixes the onion unwinding of intel_uc_init_hw, because
guc_enable_communication would've left interrupts enabled when failing
to enable CTB.

v2: always retunr the result of ctch_enable() in
    intel_guc_ct_enable() (Michal)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110943
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_ct.c | 22 ++++------------------
 drivers/gpu/drm/i915/intel_guc_ct.h |  4 ++++
 drivers/gpu/drm/i915/intel_uc.c     | 19 ++++++++++++++++---
 3 files changed, 24 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_ct.c b/drivers/gpu/drm/i915/intel_guc_ct.c
index 3921809f812b..9e383a47609f 100644
--- a/drivers/gpu/drm/i915/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/intel_guc_ct.c
@@ -529,8 +529,8 @@ static int ctch_send(struct intel_guc_ct *ct,
 /*
  * Command Transport (CT) buffer based GuC send function.
  */
-static int intel_guc_send_ct(struct intel_guc *guc, const u32 *action, u32 len,
-			     u32 *response_buf, u32 response_buf_size)
+int intel_guc_send_ct(struct intel_guc *guc, const u32 *action, u32 len,
+		      u32 *response_buf, u32 response_buf_size)
 {
 	struct intel_guc_ct *ct = &guc->ct;
 	struct intel_guc_ct_channel *ctch = &ct->host_channel;
@@ -834,7 +834,7 @@ static void ct_process_host_channel(struct intel_guc_ct *ct)
  * When we're communicating with the GuC over CT, GuC uses events
  * to notify us about new messages being posted on the RECV buffer.
  */
-static void intel_guc_to_host_event_handler_ct(struct intel_guc *guc)
+void intel_guc_to_host_event_handler_ct(struct intel_guc *guc)
 {
 	struct intel_guc_ct *ct = &guc->ct;
 
@@ -892,20 +892,11 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
 {
 	struct intel_guc *guc = ct_to_guc(ct);
 	struct intel_guc_ct_channel *ctch = &ct->host_channel;
-	int err;
 
 	if (ctch->enabled)
 		return 0;
 
-	err = ctch_enable(guc, ctch);
-	if (unlikely(err))
-		return err;
-
-	/* Switch into cmd transport buffer based send() */
-	guc->send = intel_guc_send_ct;
-	guc->handler = intel_guc_to_host_event_handler_ct;
-	DRM_INFO("CT: %s\n", enableddisabled(true));
-	return 0;
+	return ctch_enable(guc, ctch);
 }
 
 /**
@@ -921,9 +912,4 @@ void intel_guc_ct_disable(struct intel_guc_ct *ct)
 		return;
 
 	ctch_disable(guc, ctch);
-
-	/* Disable send */
-	guc->send = intel_guc_send_nop;
-	guc->handler = intel_guc_to_host_event_handler_nop;
-	DRM_INFO("CT: %s\n", enableddisabled(false));
 }
diff --git a/drivers/gpu/drm/i915/intel_guc_ct.h b/drivers/gpu/drm/i915/intel_guc_ct.h
index 41ba593a4df7..0ec17493d83b 100644
--- a/drivers/gpu/drm/i915/intel_guc_ct.h
+++ b/drivers/gpu/drm/i915/intel_guc_ct.h
@@ -101,4 +101,8 @@ static inline void intel_guc_ct_stop(struct intel_guc_ct *ct)
 	ct->host_channel.enabled = false;
 }
 
+int intel_guc_send_ct(struct intel_guc *guc, const u32 *action, u32 len,
+		      u32 *response_buf, u32 response_buf_size);
+void intel_guc_to_host_event_handler_ct(struct intel_guc *guc);
+
 #endif /* _INTEL_GUC_CT_H_ */
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index ae45651ac73c..c7f82c944dd6 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -235,9 +235,20 @@ static void guc_disable_interrupts(struct intel_guc *guc)
 
 static int guc_enable_communication(struct intel_guc *guc)
 {
+	int ret;
+
+	ret = intel_guc_ct_enable(&guc->ct);
+	if (ret)
+		return ret;
+
+	guc->send = intel_guc_send_ct;
+	guc->handler = intel_guc_to_host_event_handler_ct;
+
 	guc_enable_interrupts(guc);
 
-	return intel_guc_ct_enable(&guc->ct);
+	DRM_INFO("GuC communication enabled\n");
+
+	return 0;
 }
 
 static void guc_stop_communication(struct intel_guc *guc)
@@ -250,12 +261,14 @@ static void guc_stop_communication(struct intel_guc *guc)
 
 static void guc_disable_communication(struct intel_guc *guc)
 {
-	intel_guc_ct_disable(&guc->ct);
-
 	guc_disable_interrupts(guc);
 
 	guc->send = intel_guc_send_nop;
 	guc->handler = intel_guc_to_host_event_handler_nop;
+
+	intel_guc_ct_disable(&guc->ct);
+
+	DRM_INFO("GuC communication disabled\n");
 }
 
 int intel_uc_init_misc(struct drm_i915_private *i915)
-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 6+ messages in thread

* [PATCH v2 2/2] drm/i915/guc: handle GuC messages received with CTB disabled
  2019-06-21 18:21 [PATCH v2 1/2] drm/i915/guc: reorder enable/disable communication steps Daniele Ceraolo Spurio
@ 2019-06-21 18:21 ` Daniele Ceraolo Spurio
  2019-06-21 18:24   ` Chris Wilson
  2019-06-21 19:02 ` ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/guc: reorder enable/disable communication steps Patchwork
  2019-06-22  3:07 ` ✗ Fi.CI.IGT: failure " Patchwork
  2 siblings, 1 reply; 6+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-06-21 18:21 UTC (permalink / raw)
  To: intel-gfx

There is a very small chance of triggering a log flush event when
enabling or disabling CT buffers. Events triggered while CT buffers
are disabled are logged in the SCRATCH_15 register using the same bits
used in the CT message payload. Since our communication channel with
GuC is turned off, we can save the message and handle it after we turn
it back on.
GuC should be idle and not generate more events in the meantime because
we're not talking to it.

v2: clear the mmio register on stop_communication as well (Chris)

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/intel_guc.h |  5 +++
 drivers/gpu/drm/i915/intel_uc.c  | 74 ++++++++++++++++++++++++++++++++
 2 files changed, 79 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 08c906abdfa2..d6a75bc3d7f4 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -88,6 +88,9 @@ struct intel_guc {
 		enum forcewake_domains fw_domains;
 	} send_regs;
 
+	/* Store msg (e.g. log flush) that we see while CTBs are disabled */
+	u32 mmio_msg;
+
 	/* To serialize the intel_guc_send actions */
 	struct mutex send_mutex;
 
@@ -181,6 +184,8 @@ static inline bool intel_guc_is_loaded(struct intel_guc *guc)
 static inline int intel_guc_sanitize(struct intel_guc *guc)
 {
 	intel_uc_fw_sanitize(&guc->fw);
+	guc->mmio_msg = 0;
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index c7f82c944dd6..fdf00f1ebb57 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -218,6 +218,53 @@ static void guc_free_load_err_log(struct intel_guc *guc)
 		i915_gem_object_put(guc->load_err_log);
 }
 
+/*
+ * Events triggered while CT buffers are disabled are logged in the SCRATCH_15
+ * register using the same bits used in the CT message payload. Since our
+ * communication channel with guc is turned off at this point, we can save the
+ * message and handle it after we turn it back on.
+ */
+static void guc_clear_mmio_msg(struct intel_guc *guc)
+{
+	intel_uncore_write(&guc_to_i915(guc)->uncore, SOFT_SCRATCH(15), 0);
+}
+
+static void guc_get_mmio_msg(struct intel_guc *guc)
+{
+	u32 val;
+
+	spin_lock_irq(&guc->irq_lock);
+
+	val = intel_uncore_read(&guc_to_i915(guc)->uncore, SOFT_SCRATCH(15));
+	guc->mmio_msg |= val & guc->msg_enabled_mask;
+
+	/*
+	 * clear all events, including the ones we're not currently servicing,
+	 * to make sure we don't try to process a stale message if we enable
+	 * handling of more events later.
+	 */
+	guc_clear_mmio_msg(guc);
+
+	spin_unlock_irq(&guc->irq_lock);
+}
+
+static void guc_handle_mmio_msg(struct intel_guc *guc)
+{
+	struct drm_i915_private *i915 = guc_to_i915(guc);
+
+	/* we need communication to be enabled to reply to GuC */
+	GEM_BUG_ON(guc->handler == intel_guc_to_host_event_handler_nop);
+
+	if (!guc->mmio_msg)
+		return;
+
+	spin_lock_irq(&i915->irq_lock);
+	intel_guc_to_host_process_recv_msg(guc, &guc->mmio_msg, 1);
+	spin_unlock_irq(&i915->irq_lock);
+
+	guc->mmio_msg = 0;
+}
+
 static void guc_reset_interrupts(struct intel_guc *guc)
 {
 	guc->interrupts.reset(guc_to_i915(guc));
@@ -235,6 +282,7 @@ static void guc_disable_interrupts(struct intel_guc *guc)
 
 static int guc_enable_communication(struct intel_guc *guc)
 {
+	struct drm_i915_private *i915 = guc_to_i915(guc);
 	int ret;
 
 	ret = intel_guc_ct_enable(&guc->ct);
@@ -244,8 +292,17 @@ static int guc_enable_communication(struct intel_guc *guc)
 	guc->send = intel_guc_send_ct;
 	guc->handler = intel_guc_to_host_event_handler_ct;
 
+	/* check for mmio messages received before/during the CT enable */
+	guc_get_mmio_msg(guc);
+	guc_handle_mmio_msg(guc);
+
 	guc_enable_interrupts(guc);
 
+	/* check for CT messages received before we enabled interrupts */
+	spin_lock_irq(&i915->irq_lock);
+	intel_guc_to_host_event_handler_ct(guc);
+	spin_unlock_irq(&i915->irq_lock);
+
 	DRM_INFO("GuC communication enabled\n");
 
 	return 0;
@@ -257,10 +314,19 @@ static void guc_stop_communication(struct intel_guc *guc)
 
 	guc->send = intel_guc_send_nop;
 	guc->handler = intel_guc_to_host_event_handler_nop;
+
+	guc_clear_mmio_msg(guc);
 }
 
 static void guc_disable_communication(struct intel_guc *guc)
 {
+	/*
+	 * Events generated during or after CT disable are logged by guc in
+	 * via mmio. Make sure the register is clear before disabling CT since
+	 * all events we cared about have already been processed via CT.
+	 */
+	guc_clear_mmio_msg(guc);
+
 	guc_disable_interrupts(guc);
 
 	guc->send = intel_guc_send_nop;
@@ -268,6 +334,14 @@ static void guc_disable_communication(struct intel_guc *guc)
 
 	intel_guc_ct_disable(&guc->ct);
 
+	/*
+	 * Check for messages received during/after the CT disable. We do not
+	 * expect any messages to have arrived via CT between the interrupt
+	 * disable and the CT disable because GuC should've been idle until we
+	 * triggered the CT disable protocol.
+	 */
+	guc_get_mmio_msg(guc);
+
 	DRM_INFO("GuC communication disabled\n");
 }
 
-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 6+ messages in thread

* Re: [PATCH v2 2/2] drm/i915/guc: handle GuC messages received with CTB disabled
  2019-06-21 18:21 ` [PATCH v2 2/2] drm/i915/guc: handle GuC messages received with CTB disabled Daniele Ceraolo Spurio
@ 2019-06-21 18:24   ` Chris Wilson
  0 siblings, 0 replies; 6+ messages in thread
From: Chris Wilson @ 2019-06-21 18:24 UTC (permalink / raw)
  To: Daniele Ceraolo Spurio, intel-gfx

Quoting Daniele Ceraolo Spurio (2019-06-21 19:21:23)
> There is a very small chance of triggering a log flush event when
> enabling or disabling CT buffers. Events triggered while CT buffers
> are disabled are logged in the SCRATCH_15 register using the same bits
> used in the CT message payload. Since our communication channel with
> GuC is turned off, we can save the message and handle it after we turn
> it back on.
> GuC should be idle and not generate more events in the meantime because
> we're not talking to it.
> 
> v2: clear the mmio register on stop_communication as well (Chris)
> 
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>

I'll take your word that the guc leaves useful tidbits of info there.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 6+ messages in thread

* ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/guc: reorder enable/disable communication steps
  2019-06-21 18:21 [PATCH v2 1/2] drm/i915/guc: reorder enable/disable communication steps Daniele Ceraolo Spurio
  2019-06-21 18:21 ` [PATCH v2 2/2] drm/i915/guc: handle GuC messages received with CTB disabled Daniele Ceraolo Spurio
@ 2019-06-21 19:02 ` Patchwork
  2019-06-21 19:05   ` Chris Wilson
  2019-06-22  3:07 ` ✗ Fi.CI.IGT: failure " Patchwork
  2 siblings, 1 reply; 6+ messages in thread
From: Patchwork @ 2019-06-21 19:02 UTC (permalink / raw)
  To: Daniele Ceraolo Spurio; +Cc: intel-gfx

== Series Details ==

Series: series starting with [v2,1/2] drm/i915/guc: reorder enable/disable communication steps
URL   : https://patchwork.freedesktop.org/series/62545/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6326 -> Patchwork_13391
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13391/

Known issues
------------

  Here are the changes found in Patchwork_13391 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_basic@create-fd-close:
    - fi-icl-u3:          [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6326/fi-icl-u3/igt@gem_basic@create-fd-close.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13391/fi-icl-u3/igt@gem_basic@create-fd-close.html

  * igt@gem_ctx_create@basic-files:
    - fi-icl-u3:          [PASS][3] -> [INCOMPLETE][4] ([fdo#107713] / [fdo#109100])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6326/fi-icl-u3/igt@gem_ctx_create@basic-files.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13391/fi-icl-u3/igt@gem_ctx_create@basic-files.html

  
#### Possible fixes ####

  * igt@gem_cpu_reloc@basic:
    - fi-icl-u3:          [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6326/fi-icl-u3/igt@gem_cpu_reloc@basic.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13391/fi-icl-u3/igt@gem_cpu_reloc@basic.html

  
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100


Participating hosts (51 -> 41)
------------------------------

  Missing    (10): fi-kbl-soraka fi-cml-u2 fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_6326 -> Patchwork_13391

  CI_DRM_6326: 5ada613f14b49e08e2ef974dd5faf6d84ce95de8 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5064: 22850c1906550fb97b405c019275dcfb34be8cf7 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13391: a2b18d3689f5994d96f365e5e5bcf58572c08553 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

a2b18d3689f5 drm/i915/guc: handle GuC messages received with CTB disabled
d29fce1f4634 drm/i915/guc: reorder enable/disable communication steps

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13391/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/guc: reorder enable/disable communication steps
  2019-06-21 19:02 ` ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/guc: reorder enable/disable communication steps Patchwork
@ 2019-06-21 19:05   ` Chris Wilson
  0 siblings, 0 replies; 6+ messages in thread
From: Chris Wilson @ 2019-06-21 19:05 UTC (permalink / raw)
  To: Daniele Ceraolo Spurio, Patchwork; +Cc: intel-gfx

Quoting Patchwork (2019-06-21 20:02:53)
> == Series Details ==
> 
> Series: series starting with [v2,1/2] drm/i915/guc: reorder enable/disable communication steps
> URL   : https://patchwork.freedesktop.org/series/62545/
> State : success
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_6326 -> Patchwork_13391
> ====================================================
> 
> Summary
> -------
> 
>   **SUCCESS**
> 
>   No regressions found.
> 
>   External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13391/

And that's all the coverage we have. Thanks for the patches, pushed.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 6+ messages in thread

* ✗ Fi.CI.IGT: failure for series starting with [v2,1/2] drm/i915/guc: reorder enable/disable communication steps
  2019-06-21 18:21 [PATCH v2 1/2] drm/i915/guc: reorder enable/disable communication steps Daniele Ceraolo Spurio
  2019-06-21 18:21 ` [PATCH v2 2/2] drm/i915/guc: handle GuC messages received with CTB disabled Daniele Ceraolo Spurio
  2019-06-21 19:02 ` ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/guc: reorder enable/disable communication steps Patchwork
@ 2019-06-22  3:07 ` Patchwork
  2 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2019-06-22  3:07 UTC (permalink / raw)
  To: Daniele Ceraolo Spurio; +Cc: intel-gfx

== Series Details ==

Series: series starting with [v2,1/2] drm/i915/guc: reorder enable/disable communication steps
URL   : https://patchwork.freedesktop.org/series/62545/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_6326_full -> Patchwork_13391_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_13391_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_13391_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_13391_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_ctx_shared@q-promotion-render:
    - shard-skl:          NOTRUN -> [INCOMPLETE][1] +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13391/shard-skl2/igt@gem_ctx_shared@q-promotion-render.html

  * igt@gem_exec_fence@basic-await-default:
    - shard-apl:          NOTRUN -> [DMESG-WARN][2]
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13391/shard-apl5/igt@gem_exec_fence@basic-await-default.html

  * igt@gem_ringfill@basic-default-hang:
    - shard-snb:          NOTRUN -> [FAIL][3]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13391/shard-snb1/igt@gem_ringfill@basic-default-hang.html

  * igt@gem_ringfill@basic-default-interruptible:
    - shard-skl:          NOTRUN -> [FAIL][4]
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13391/shard-skl8/igt@gem_ringfill@basic-default-interruptible.html

  
Known issues
------------

  Here are the changes found in Patchwork_13391_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ppgtt@blt-vs-render-ctx0:
    - shard-snb:          [PASS][5] -> [DMESG-WARN][6] ([fdo#110789] / [fdo#110913 ])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6326/shard-snb2/igt@gem_ppgtt@blt-vs-render-ctx0.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13391/shard-snb2/igt@gem_ppgtt@blt-vs-render-ctx0.html

  * igt@kms_flip@2x-wf_vblank-ts-check-interruptible:
    - shard-hsw:          [PASS][7] -> [SKIP][8] ([fdo#109271]) +5 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6326/shard-hsw8/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13391/shard-hsw1/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html

  * igt@kms_psr@psr2_suspend:
    - shard-iclb:         [PASS][9] -> [SKIP][10] ([fdo#109441]) +1 similar issue
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6326/shard-iclb2/igt@kms_psr@psr2_suspend.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13391/shard-iclb6/igt@kms_psr@psr2_suspend.html

  * igt@kms_sysfs_edid_timing:
    - shard-iclb:         [PASS][11] -> [FAIL][12] ([fdo#100047])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6326/shard-iclb1/igt@kms_sysfs_edid_timing.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13391/shard-iclb2/igt@kms_sysfs_edid_timing.html

  
#### Possible fixes ####

  * igt@gem_partial_pwrite_pread@write-uncached:
    - shard-iclb:         [INCOMPLETE][13] ([fdo#107713]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6326/shard-iclb7/igt@gem_partial_pwrite_pread@write-uncached.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13391/shard-iclb4/igt@gem_partial_pwrite_pread@write-uncached.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-move:
    - shard-hsw:          [SKIP][15] ([fdo#109271]) -> [PASS][16] +3 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6326/shard-hsw1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-move.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13391/shard-hsw7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render:
    - shard-iclb:         [FAIL][17] ([fdo#103167]) -> [PASS][18] +5 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6326/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13391/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_psr@psr2_no_drrs:
    - shard-iclb:         [SKIP][19] ([fdo#109441]) -> [PASS][20] +1 similar issue
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6326/shard-iclb3/igt@kms_psr@psr2_no_drrs.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13391/shard-iclb2/igt@kms_psr@psr2_no_drrs.html

  
  [fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#110789]: https://bugs.freedesktop.org/show_bug.cgi?id=110789
  [fdo#110913 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110913 


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_6326 -> Patchwork_13391

  CI_DRM_6326: 5ada613f14b49e08e2ef974dd5faf6d84ce95de8 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5064: 22850c1906550fb97b405c019275dcfb34be8cf7 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13391: a2b18d3689f5994d96f365e5e5bcf58572c08553 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13391/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2019-06-22  3:07 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-06-21 18:21 [PATCH v2 1/2] drm/i915/guc: reorder enable/disable communication steps Daniele Ceraolo Spurio
2019-06-21 18:21 ` [PATCH v2 2/2] drm/i915/guc: handle GuC messages received with CTB disabled Daniele Ceraolo Spurio
2019-06-21 18:24   ` Chris Wilson
2019-06-21 19:02 ` ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/guc: reorder enable/disable communication steps Patchwork
2019-06-21 19:05   ` Chris Wilson
2019-06-22  3:07 ` ✗ Fi.CI.IGT: failure " Patchwork

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