[PATCH 1/2] drm/amdgpu: fix transform feedback GDS hang on gfx10 (v2)

[PATCH 1/2] drm/amdgpu: fix transform feedback GDS hang on gfx10 (v2)

[Marek Olšák]

From: Marek Olšák <marek.olsak@amd.com>

v2: update emit_ib_size
(though it's still wrong because it was wrong before)

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h |  3 ++-
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c  | 14 +++++++++++---
 2 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h
index dad2186f4ed5..df8a23554831 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h
@@ -24,21 +24,22 @@
 #ifndef __AMDGPU_GDS_H__
 #define __AMDGPU_GDS_H__
 
 struct amdgpu_ring;
 struct amdgpu_bo;
 
 struct amdgpu_gds {
 	uint32_t gds_size;
 	uint32_t gws_size;
 	uint32_t oa_size;
-	uint32_t			gds_compute_max_wave_id;
+	uint32_t gds_compute_max_wave_id;
+	uint32_t vgt_gs_max_wave_id;
 };
 
 struct amdgpu_gds_reg_offset {
 	uint32_t	mem_base;
 	uint32_t	mem_size;
 	uint32_t	gws;
 	uint32_t	oa;
 };
 
 #endif /* __AMDGPU_GDS_H__ */
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 16b2bcc590e7..6baaa65a1daa 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4211,20 +4211,29 @@ static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 }
 
 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
 				       struct amdgpu_job *job,
 				       struct amdgpu_ib *ib,
 				       uint32_t flags)
 {
 	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 	u32 header, control = 0;
 
+	/* Prevent a hw deadlock due to a wave ID mismatch between ME and GDS.
+	 * This resets the wave ID counters. (needed by transform feedback)
+	 * TODO: This might only be needed on a VMID switch when we change
+	 *       the GDS OA mapping, not sure.
+	 */
+	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
+	amdgpu_ring_write(ring, mmVGT_GS_MAX_WAVE_ID);
+	amdgpu_ring_write(ring, ring->adev->gds.vgt_gs_max_wave_id);
+
 	if (ib->flags & AMDGPU_IB_FLAG_CE)
 		header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
 	else
 		header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
 
 	control |= ib->length_dw | (vmid << 24);
 
 	if (amdgpu_mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
 		control |= INDIRECT_BUFFER_PRE_ENB(1);
 
@@ -4944,21 +4953,21 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
 		     */
 		5 + /* COND_EXEC */
 		7 + /* HDP_flush */
 		4 + /* VGT_flush */
 		14 + /*	CE_META */
 		31 + /*	DE_META */
 		3 + /* CNTX_CTRL */
 		5 + /* HDP_INVL */
 		8 + 8 + /* FENCE x2 */
 		2, /* SWITCH_BUFFER */
-	.emit_ib_size =	4, /* gfx_v10_0_ring_emit_ib_gfx */
+	.emit_ib_size =	7, /* gfx_v10_0_ring_emit_ib_gfx */
 	.emit_ib = gfx_v10_0_ring_emit_ib_gfx,
 	.emit_fence = gfx_v10_0_ring_emit_fence,
 	.emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
 	.emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
 	.emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
 	.emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
 	.test_ring = gfx_v10_0_ring_test_ring,
 	.test_ib = gfx_v10_0_ring_test_ib,
 	.insert_nop = amdgpu_ring_insert_nop,
 	.pad_ib = amdgpu_ring_generic_pad_ib,
@@ -5092,24 +5101,23 @@ static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
 	default:
 		break;
 	}
 }
 
 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
 {
 	/* init asic gds info */
 	switch (adev->asic_type) {
 	case CHIP_NAVI10:
-		adev->gds.gds_size = 0x10000;
-		break;
 	default:
 		adev->gds.gds_size = 0x10000;
+		adev->gds.vgt_gs_max_wave_id = 0x3ff;
 		break;
 	}
 
 	adev->gds.gws_size = 64;
 	adev->gds.oa_size = 16;
 }
 
 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
 							  u32 bitmap)
 {
-- 
2.17.1

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[PATCH 2/2] drm/amdgpu: handle AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID on gfx10

[Marek Olšák]

From: Marek Olšák <marek.olsak@amd.com>

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 6baaa65a1daa..5b807a19bbbf 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4257,20 +4257,36 @@ static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
 }
 
 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
 					   struct amdgpu_job *job,
 					   struct amdgpu_ib *ib,
 					   uint32_t flags)
 {
 	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 	u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
 
+	/* Currently, there is a high possibility to get wave ID mismatch
+	 * between ME and GDS, leading to a hw deadlock, because ME generates
+	 * different wave IDs than the GDS expects. This situation happens
+	 * randomly when at least 5 compute pipes use GDS ordered append.
+	 * The wave IDs generated by ME are also wrong after suspend/resume.
+	 * Those are probably bugs somewhere else in the kernel driver.
+	 *
+	 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
+	 * GDS to 0 for this ring (me/pipe).
+	 */
+	if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
+		amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
+		amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
+		amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
+	}
+
 	amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
 	BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
 	amdgpu_ring_write(ring,
 #ifdef __BIG_ENDIAN
 				(2 << 0) |
 #endif
 				lower_32_bits(ib->gpu_addr));
 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 	amdgpu_ring_write(ring, control);
 }
@@ -5103,20 +5119,21 @@ static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
 	}
 }
 
 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
 {
 	/* init asic gds info */
 	switch (adev->asic_type) {
 	case CHIP_NAVI10:
 	default:
 		adev->gds.gds_size = 0x10000;
+		adev->gds.gds_compute_max_wave_id = 0x4ff;
 		adev->gds.vgt_gs_max_wave_id = 0x3ff;
 		break;
 	}
 
 	adev->gds.gws_size = 64;
 	adev->gds.oa_size = 16;
 }
 
 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
 							  u32 bitmap)
-- 
2.17.1

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Re: [PATCH 1/2] drm/amdgpu: fix transform feedback GDS hang on gfx10 (v2)

[Christian König]

Am 27.06.19 um 00:35 schrieb Marek Olšák:
> From: Marek Olšák <marek.olsak@amd.com>
>
> v2: update emit_ib_size
> (though it's still wrong because it was wrong before)
>
> Signed-off-by: Marek Olšák <marek.olsak@amd.com>

Can't judge if this is really the right thing to do because I don't know 
the details of the hw bug.

But at least of hand I can't see any obvious problems with it, so feel 
free to add an Acked-by: Christian König <christian.koenig@amd.com> to 
the series.

Regards,
Christian.

> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h |  3 ++-
>   drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c  | 14 +++++++++++---
>   2 files changed, 13 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h
> index dad2186f4ed5..df8a23554831 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h
> @@ -24,21 +24,22 @@
>   #ifndef __AMDGPU_GDS_H__
>   #define __AMDGPU_GDS_H__
>   
>   struct amdgpu_ring;
>   struct amdgpu_bo;
>   
>   struct amdgpu_gds {
>   	uint32_t gds_size;
>   	uint32_t gws_size;
>   	uint32_t oa_size;
> -	uint32_t			gds_compute_max_wave_id;
> +	uint32_t gds_compute_max_wave_id;
> +	uint32_t vgt_gs_max_wave_id;
>   };
>   
>   struct amdgpu_gds_reg_offset {
>   	uint32_t	mem_base;
>   	uint32_t	mem_size;
>   	uint32_t	gws;
>   	uint32_t	oa;
>   };
>   
>   #endif /* __AMDGPU_GDS_H__ */
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 16b2bcc590e7..6baaa65a1daa 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -4211,20 +4211,29 @@ static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
>   }
>   
>   static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
>   				       struct amdgpu_job *job,
>   				       struct amdgpu_ib *ib,
>   				       uint32_t flags)
>   {
>   	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
>   	u32 header, control = 0;
>   
> +	/* Prevent a hw deadlock due to a wave ID mismatch between ME and GDS.
> +	 * This resets the wave ID counters. (needed by transform feedback)
> +	 * TODO: This might only be needed on a VMID switch when we change
> +	 *       the GDS OA mapping, not sure.
> +	 */
> +	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
> +	amdgpu_ring_write(ring, mmVGT_GS_MAX_WAVE_ID);
> +	amdgpu_ring_write(ring, ring->adev->gds.vgt_gs_max_wave_id);
> +
>   	if (ib->flags & AMDGPU_IB_FLAG_CE)
>   		header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
>   	else
>   		header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
>   
>   	control |= ib->length_dw | (vmid << 24);
>   
>   	if (amdgpu_mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
>   		control |= INDIRECT_BUFFER_PRE_ENB(1);
>   
> @@ -4944,21 +4953,21 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
>   		     */
>   		5 + /* COND_EXEC */
>   		7 + /* HDP_flush */
>   		4 + /* VGT_flush */
>   		14 + /*	CE_META */
>   		31 + /*	DE_META */
>   		3 + /* CNTX_CTRL */
>   		5 + /* HDP_INVL */
>   		8 + 8 + /* FENCE x2 */
>   		2, /* SWITCH_BUFFER */
> -	.emit_ib_size =	4, /* gfx_v10_0_ring_emit_ib_gfx */
> +	.emit_ib_size =	7, /* gfx_v10_0_ring_emit_ib_gfx */
>   	.emit_ib = gfx_v10_0_ring_emit_ib_gfx,
>   	.emit_fence = gfx_v10_0_ring_emit_fence,
>   	.emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
>   	.emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
>   	.emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
>   	.emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
>   	.test_ring = gfx_v10_0_ring_test_ring,
>   	.test_ib = gfx_v10_0_ring_test_ib,
>   	.insert_nop = amdgpu_ring_insert_nop,
>   	.pad_ib = amdgpu_ring_generic_pad_ib,
> @@ -5092,24 +5101,23 @@ static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
>   	default:
>   		break;
>   	}
>   }
>   
>   static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
>   {
>   	/* init asic gds info */
>   	switch (adev->asic_type) {
>   	case CHIP_NAVI10:
> -		adev->gds.gds_size = 0x10000;
> -		break;
>   	default:
>   		adev->gds.gds_size = 0x10000;
> +		adev->gds.vgt_gs_max_wave_id = 0x3ff;
>   		break;
>   	}
>   
>   	adev->gds.gws_size = 64;
>   	adev->gds.oa_size = 16;
>   }
>   
>   static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
>   							  u32 bitmap)
>   {

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Re: [PATCH 2/2] drm/amdgpu: handle AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID on gfx10

[zhoucm1]

any reason for not care .emit_ib_size in this one?

-David


On 2019年06月27日 06:35, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak@amd.com>
>
> Signed-off-by: Marek Olšák <marek.olsak@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 17 +++++++++++++++++
>   1 file changed, 17 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 6baaa65a1daa..5b807a19bbbf 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -4257,20 +4257,36 @@ static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
>   }
>   
>   static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
>   					   struct amdgpu_job *job,
>   					   struct amdgpu_ib *ib,
>   					   uint32_t flags)
>   {
>   	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
>   	u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
>   
> +	/* Currently, there is a high possibility to get wave ID mismatch
> +	 * between ME and GDS, leading to a hw deadlock, because ME generates
> +	 * different wave IDs than the GDS expects. This situation happens
> +	 * randomly when at least 5 compute pipes use GDS ordered append.
> +	 * The wave IDs generated by ME are also wrong after suspend/resume.
> +	 * Those are probably bugs somewhere else in the kernel driver.
> +	 *
> +	 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
> +	 * GDS to 0 for this ring (me/pipe).
> +	 */
> +	if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
> +		amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
> +		amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
> +		amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
> +	}
> +
>   	amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
>   	BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
>   	amdgpu_ring_write(ring,
>   #ifdef __BIG_ENDIAN
>   				(2 << 0) |
>   #endif
>   				lower_32_bits(ib->gpu_addr));
>   	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
>   	amdgpu_ring_write(ring, control);
>   }
> @@ -5103,20 +5119,21 @@ static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
>   	}
>   }
>   
>   static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
>   {
>   	/* init asic gds info */
>   	switch (adev->asic_type) {
>   	case CHIP_NAVI10:
>   	default:
>   		adev->gds.gds_size = 0x10000;
> +		adev->gds.gds_compute_max_wave_id = 0x4ff;
>   		adev->gds.vgt_gs_max_wave_id = 0x3ff;
>   		break;
>   	}
>   
>   	adev->gds.gws_size = 64;
>   	adev->gds.oa_size = 16;
>   }
>   
>   static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
>   							  u32 bitmap)

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Re: [PATCH 2/2] drm/amdgpu: handle AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID on gfx10

[Marek Olšák]

[-- Attachment #1.1: Type: text/plain, Size: 3547 bytes --]

Thanks. I'll push both patches with emit_ib_size updated for this patch.

Marek

On Thu, Jun 27, 2019 at 3:50 AM zhoucm1 <zhoucm1-5C7GfCeVMHo@public.gmane.org> wrote:

> any reason for not care .emit_ib_size in this one?
>
> -David
>
>
> On 2019年06月27日 06:35, Marek Olšák wrote:
> > From: Marek Olšák <marek.olsak-5C7GfCeVMHo@public.gmane.org>
> >
> > Signed-off-by: Marek Olšák <marek.olsak-5C7GfCeVMHo@public.gmane.org>
> > ---
> >   drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 17 +++++++++++++++++
> >   1 file changed, 17 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > index 6baaa65a1daa..5b807a19bbbf 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > @@ -4257,20 +4257,36 @@ static void gfx_v10_0_ring_emit_ib_gfx(struct
> amdgpu_ring *ring,
> >   }
> >
> >   static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
> >                                          struct amdgpu_job *job,
> >                                          struct amdgpu_ib *ib,
> >                                          uint32_t flags)
> >   {
> >       unsigned vmid = AMDGPU_JOB_GET_VMID(job);
> >       u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
> >
> > +     /* Currently, there is a high possibility to get wave ID mismatch
> > +      * between ME and GDS, leading to a hw deadlock, because ME
> generates
> > +      * different wave IDs than the GDS expects. This situation happens
> > +      * randomly when at least 5 compute pipes use GDS ordered append.
> > +      * The wave IDs generated by ME are also wrong after
> suspend/resume.
> > +      * Those are probably bugs somewhere else in the kernel driver.
> > +      *
> > +      * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME
> and
> > +      * GDS to 0 for this ring (me/pipe).
> > +      */
> > +     if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
> > +             amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG,
> 1));
> > +             amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
> > +             amdgpu_ring_write(ring,
> ring->adev->gds.gds_compute_max_wave_id);
> > +     }
> > +
> >       amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
> >       BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
> >       amdgpu_ring_write(ring,
> >   #ifdef __BIG_ENDIAN
> >                               (2 << 0) |
> >   #endif
> >                               lower_32_bits(ib->gpu_addr));
> >       amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
> >       amdgpu_ring_write(ring, control);
> >   }
> > @@ -5103,20 +5119,21 @@ static void gfx_v10_0_set_rlc_funcs(struct
> amdgpu_device *adev)
> >       }
> >   }
> >
> >   static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
> >   {
> >       /* init asic gds info */
> >       switch (adev->asic_type) {
> >       case CHIP_NAVI10:
> >       default:
> >               adev->gds.gds_size = 0x10000;
> > +             adev->gds.gds_compute_max_wave_id = 0x4ff;
> >               adev->gds.vgt_gs_max_wave_id = 0x3ff;
> >               break;
> >       }
> >
> >       adev->gds.gws_size = 64;
> >       adev->gds.oa_size = 16;
> >   }
> >
> >   static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct
> amdgpu_device *adev,
> >                                                         u32 bitmap)
>
>

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[PATCH 2/2] drm/amdgpu: handle AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID on gfx10

[Marek Olšák]

From: Marek Olšák <marek.olsak@amd.com>

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 75a34779a57c..77507b2a4652 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4259,20 +4259,36 @@ static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
 }
 
 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
 					   struct amdgpu_job *job,
 					   struct amdgpu_ib *ib,
 					   uint32_t flags)
 {
 	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 	u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
 
+	/* Currently, there is a high possibility to get wave ID mismatch
+	 * between ME and GDS, leading to a hw deadlock, because ME generates
+	 * different wave IDs than the GDS expects. This situation happens
+	 * randomly when at least 5 compute pipes use GDS ordered append.
+	 * The wave IDs generated by ME are also wrong after suspend/resume.
+	 * Those are probably bugs somewhere else in the kernel driver.
+	 *
+	 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
+	 * GDS to 0 for this ring (me/pipe).
+	 */
+	if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
+		amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
+		amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
+		amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
+	}
+
 	amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
 	BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
 	amdgpu_ring_write(ring,
 #ifdef __BIG_ENDIAN
 				(2 << 0) |
 #endif
 				lower_32_bits(ib->gpu_addr));
 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 	amdgpu_ring_write(ring, control);
 }
@@ -5105,20 +5121,21 @@ static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
 	}
 }
 
 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
 {
 	/* init asic gds info */
 	switch (adev->asic_type) {
 	case CHIP_NAVI10:
 	default:
 		adev->gds.gds_size = 0x10000;
+		adev->gds.gds_compute_max_wave_id = 0x4ff;
 		adev->gds.vgt_gs_max_wave_id = 0x3ff;
 		break;
 	}
 
 	adev->gds.gws_size = 64;
 	adev->gds.oa_size = 16;
 }
 
 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
 							  u32 bitmap)
-- 
2.17.1

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