From: Palmer Dabbelt <palmer@sifive.com> To: Peter Maydell <peter.maydell@linaro.org> Cc: Alistair Francis <alistair.francis@wdc.com>, Michael Clark <mjc@sifive.com>, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Palmer Dabbelt <palmer@sifive.com> Subject: [Qemu-devel] [PULL 04/34] target/riscv: Implement riscv_cpu_unassigned_access Date: Thu, 27 Jun 2019 08:19:41 -0700 [thread overview] Message-ID: <20190627152011.18686-5-palmer@sifive.com> (raw) In-Reply-To: <20190627152011.18686-1-palmer@sifive.com> From: Michael Clark <mjc@sifive.com> This patch adds support for the riscv_cpu_unassigned_access call and will raise a load or store access fault. Signed-off-by: Michael Clark <mjc@sifive.com> [Changes by AF: - Squash two patches and rewrite commit message - Set baddr to the access address ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 2 ++ target/riscv/cpu_helper.c | 16 ++++++++++++++++ 3 files changed, 19 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0632ac08cf35..5b9fae608cca 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -482,6 +482,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) cc->gdb_stop_before_watchpoint = true; cc->disas_set_info = riscv_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY + cc->do_unassigned_access = riscv_cpu_unassigned_access; cc->do_unaligned_access = riscv_cpu_do_unaligned_access; cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug; #endif diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index b47cde501766..2e743312536b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -259,6 +259,8 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +void riscv_cpu_unassigned_access(CPUState *cpu, hwaddr addr, bool is_write, + bool is_exec, int unused, unsigned size); char *riscv_isa_string(RISCVCPU *cpu); void riscv_cpu_list(void); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 8b6754b91798..0bbfb7f48b79 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -375,6 +375,22 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) return phys_addr; } +void riscv_cpu_unassigned_access(CPUState *cs, hwaddr addr, bool is_write, + bool is_exec, int unused, unsigned size) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + + if (is_write) { + cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT; + } else { + cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT; + } + + env->badaddr = addr; + riscv_raise_exception(&cpu->env, cs->exception_index, GETPC()); +} + void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -- 2.21.0
WARNING: multiple messages have this Message-ID (diff)
From: Palmer Dabbelt <palmer@sifive.com> To: Peter Maydell <peter.maydell@linaro.org> Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Michael Clark <mjc@sifive.com>, Alistair Francis <alistair.francis@wdc.com>, Palmer Dabbelt <palmer@sifive.com> Subject: [Qemu-riscv] [PULL 04/34] target/riscv: Implement riscv_cpu_unassigned_access Date: Thu, 27 Jun 2019 08:19:41 -0700 [thread overview] Message-ID: <20190627152011.18686-5-palmer@sifive.com> (raw) In-Reply-To: <20190627152011.18686-1-palmer@sifive.com> From: Michael Clark <mjc@sifive.com> This patch adds support for the riscv_cpu_unassigned_access call and will raise a load or store access fault. Signed-off-by: Michael Clark <mjc@sifive.com> [Changes by AF: - Squash two patches and rewrite commit message - Set baddr to the access address ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 2 ++ target/riscv/cpu_helper.c | 16 ++++++++++++++++ 3 files changed, 19 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0632ac08cf35..5b9fae608cca 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -482,6 +482,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) cc->gdb_stop_before_watchpoint = true; cc->disas_set_info = riscv_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY + cc->do_unassigned_access = riscv_cpu_unassigned_access; cc->do_unaligned_access = riscv_cpu_do_unaligned_access; cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug; #endif diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index b47cde501766..2e743312536b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -259,6 +259,8 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +void riscv_cpu_unassigned_access(CPUState *cpu, hwaddr addr, bool is_write, + bool is_exec, int unused, unsigned size); char *riscv_isa_string(RISCVCPU *cpu); void riscv_cpu_list(void); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 8b6754b91798..0bbfb7f48b79 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -375,6 +375,22 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) return phys_addr; } +void riscv_cpu_unassigned_access(CPUState *cs, hwaddr addr, bool is_write, + bool is_exec, int unused, unsigned size) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + + if (is_write) { + cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT; + } else { + cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT; + } + + env->badaddr = addr; + riscv_raise_exception(&cpu->env, cs->exception_index, GETPC()); +} + void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -- 2.21.0
next prev parent reply other threads:[~2019-06-27 15:31 UTC|newest] Thread overview: 113+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-06-27 15:19 [Qemu-devel] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 Palmer Dabbelt 2019-06-27 15:19 ` [Qemu-riscv] " Palmer Dabbelt 2019-06-27 15:19 ` [Qemu-devel] [PULL 01/34] target/riscv: Allow setting ISA extensions via CPU props Palmer Dabbelt 2019-06-27 15:19 ` [Qemu-riscv] " Palmer Dabbelt 2019-06-27 15:19 ` [Qemu-devel] [PULL 02/34] sifive_prci: Read and write PRCI registers Palmer Dabbelt 2019-06-27 15:19 ` [Qemu-riscv] " Palmer Dabbelt 2019-06-27 15:19 ` [Qemu-devel] [PULL 03/34] target/riscv: Fix PMP range boundary address bug Palmer Dabbelt 2019-06-27 15:19 ` [Qemu-riscv] " Palmer Dabbelt 2019-06-27 15:19 ` Palmer Dabbelt [this message] 2019-06-27 15:19 ` [Qemu-riscv] [PULL 04/34] target/riscv: Implement riscv_cpu_unassigned_access Palmer Dabbelt 2019-06-27 15:19 ` [Qemu-devel] [PULL 05/34] RISC-V: Only Check PMP if MMU translation succeeds Palmer Dabbelt 2019-06-27 15:19 ` [Qemu-riscv] " Palmer Dabbelt 2019-06-27 15:19 ` [Qemu-devel] [PULL 06/34] RISC-V: Raise access fault exceptions on PMP violations Palmer Dabbelt 2019-06-27 15:19 ` [Qemu-riscv] " Palmer Dabbelt 2019-06-27 15:19 ` [Qemu-devel] [PULL 07/34] RISC-V: Check for the effective memory privilege mode during PMP checks Palmer Dabbelt 2019-06-27 15:19 ` [Qemu-riscv] " Palmer Dabbelt 2019-06-27 15:19 ` [Qemu-devel] [PULL 08/34] RISC-V: Check PMP during Page Table Walks Palmer Dabbelt 2019-06-27 15:19 ` [Qemu-riscv] " Palmer Dabbelt 2019-06-27 15:19 ` [Qemu-devel] [PULL 09/34] RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off Palmer Dabbelt 2019-06-27 15:19 ` [Qemu-riscv] " Palmer Dabbelt 2019-06-27 15:19 ` [Qemu-devel] [PULL 10/34] RISC-V: Fix a PMP check with the correct access size Palmer Dabbelt 2019-06-27 15:19 ` [Qemu-riscv] " Palmer Dabbelt 2019-06-27 17:44 ` [Qemu-devel] " Jonathan Behrens 2019-06-27 17:44 ` Jonathan Behrens 2019-06-27 18:23 ` [Qemu-devel] " Richard Henderson 2019-06-27 18:23 ` [Qemu-riscv] [Qemu-devel] " Richard Henderson 2019-07-08 12:46 ` [Qemu-devel] [Qemu-riscv] " Palmer Dabbelt 2019-07-08 12:46 ` [Qemu-riscv] [Qemu-devel] " Palmer Dabbelt 2019-06-27 15:19 ` [Qemu-devel] [PULL 11/34] riscv: virt: Correct pci "bus-range" encoding Palmer Dabbelt 2019-06-27 15:19 ` [Qemu-riscv] " Palmer Dabbelt 2019-06-27 15:19 ` [Qemu-devel] [PULL 12/34] RISC-V: Fix a memory leak when realizing a sifive_e Palmer Dabbelt 2019-06-27 15:19 ` [Qemu-riscv] " Palmer Dabbelt 2019-06-27 15:19 ` [Qemu-devel] [PULL 13/34] target/riscv: Restructure deprecatd CPUs Palmer Dabbelt 2019-06-27 15:19 ` [Qemu-riscv] " Palmer Dabbelt 2019-06-27 15:19 ` [Qemu-devel] [PULL 14/34] target/riscv: Add the privledge spec version 1.11.0 Palmer Dabbelt 2019-06-27 15:19 ` [Qemu-riscv] " Palmer Dabbelt 2019-06-27 15:19 ` [Qemu-devel] [PULL 15/34] target/riscv: Add the mcountinhibit CSR Palmer Dabbelt 2019-06-27 15:19 ` [Qemu-riscv] " Palmer Dabbelt 2019-06-27 15:19 ` [Qemu-devel] [PULL 16/34] target/riscv: Set privledge spec 1.11.0 as default Palmer Dabbelt 2019-06-27 15:19 ` [Qemu-riscv] " Palmer Dabbelt 2019-06-27 15:19 ` [Qemu-devel] [PULL 17/34] qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1 Palmer Dabbelt 2019-06-27 15:19 ` [Qemu-riscv] " Palmer Dabbelt 2019-06-27 15:19 ` [Qemu-devel] [PULL 18/34] target/riscv: Require either I or E base extension Palmer Dabbelt 2019-06-27 15:19 ` [Qemu-riscv] " Palmer Dabbelt 2019-06-27 15:19 ` [Qemu-devel] [PULL 19/34] target/riscv: Remove user version information Palmer Dabbelt 2019-06-27 15:19 ` [Qemu-riscv] " Palmer Dabbelt 2019-06-27 15:19 ` [Qemu-devel] [PULL 20/34] target/riscv: Add support for disabling/enabling Counters Palmer Dabbelt 2019-06-27 15:19 ` [Qemu-riscv] " Palmer Dabbelt 2019-06-27 15:19 ` [Qemu-devel] [PULL 21/34] RISC-V: Add support for the Zifencei extension Palmer Dabbelt 2019-06-27 15:19 ` [Qemu-riscv] " Palmer Dabbelt 2019-06-27 15:19 ` [Qemu-devel] [PULL 22/34] RISC-V: Add support for the Zicsr extension Palmer Dabbelt 2019-06-27 15:19 ` [Qemu-riscv] " Palmer Dabbelt 2019-06-27 15:20 ` [Qemu-devel] [PULL 23/34] RISC-V: Clear load reservations on context switch and SC Palmer Dabbelt 2019-06-27 15:20 ` [Qemu-riscv] " Palmer Dabbelt 2019-06-27 15:20 ` [Qemu-devel] [PULL 24/34] RISC-V: Update syscall list for 32-bit support Palmer Dabbelt 2019-06-27 15:20 ` [Qemu-riscv] " Palmer Dabbelt 2019-06-27 15:20 ` [Qemu-devel] [PULL 25/34] riscv: virt: Add cpu-topology DT node Palmer Dabbelt 2019-06-27 15:20 ` [Qemu-riscv] " Palmer Dabbelt 2019-06-27 15:20 ` [Qemu-devel] [PULL 26/34] disas/riscv: Disassemble reserved compressed encodings as illegal Palmer Dabbelt 2019-06-27 15:20 ` [Qemu-riscv] " Palmer Dabbelt 2019-06-27 15:20 ` [Qemu-devel] [PULL 27/34] disas/riscv: Fix `rdinstreth` constraint Palmer Dabbelt 2019-06-27 15:20 ` [Qemu-riscv] " Palmer Dabbelt 2019-06-27 15:20 ` [Qemu-devel] [PULL 28/34] riscv: sifive_u: Do not create hard-coded phandles in DT Palmer Dabbelt 2019-06-27 15:20 ` [Qemu-riscv] " Palmer Dabbelt 2019-06-27 15:20 ` [Qemu-devel] [PULL 29/34] riscv: sifive_u: Update the plic hart config to support multicore Palmer Dabbelt 2019-06-27 15:20 ` [Qemu-riscv] " Palmer Dabbelt 2019-06-27 15:20 ` [Qemu-devel] [PULL 30/34] hw/riscv: Split out the boot functions Palmer Dabbelt 2019-06-27 15:20 ` [Qemu-riscv] " Palmer Dabbelt 2019-06-27 15:20 ` [Qemu-devel] [PULL 31/34] hw/riscv: Add support for loading a firmware Palmer Dabbelt 2019-06-27 15:20 ` [Qemu-riscv] " Palmer Dabbelt 2019-06-27 15:20 ` [Qemu-devel] [PULL 32/34] hw/riscv: Extend the kernel loading support Palmer Dabbelt 2019-06-27 15:20 ` [Qemu-riscv] " Palmer Dabbelt 2019-06-27 15:20 ` [Qemu-devel] [PULL 33/34] roms: Add OpenSBI version 0.3 Palmer Dabbelt 2019-06-27 15:20 ` [Qemu-riscv] " Palmer Dabbelt 2019-06-28 9:46 ` [Qemu-devel] " Jonathan Cameron 2019-06-28 9:46 ` [Qemu-riscv] " Jonathan Cameron 2019-06-28 16:12 ` Alistair Francis 2019-06-28 16:12 ` [Qemu-riscv] " Alistair Francis 2019-06-28 17:10 ` Palmer Dabbelt 2019-06-28 17:10 ` [Qemu-riscv] " Palmer Dabbelt 2019-07-01 12:40 ` Jonathan Cameron 2019-07-01 12:40 ` [Qemu-riscv] " Jonathan Cameron 2019-07-01 13:23 ` [Qemu-devel] [Qemu-riscv] " Anup Patel 2019-07-01 13:23 ` [Qemu-riscv] [Qemu-devel] " Anup Patel 2019-07-01 16:39 ` [Qemu-devel] [Qemu-riscv] " Alistair Francis 2019-07-01 16:39 ` [Qemu-riscv] [Qemu-devel] " Alistair Francis 2019-07-01 16:54 ` Peter Maydell 2019-07-01 16:54 ` [Qemu-riscv] " Peter Maydell 2019-07-01 17:50 ` [Qemu-devel] " Alistair Francis 2019-07-01 17:50 ` [Qemu-riscv] " Alistair Francis 2019-07-01 18:01 ` [Qemu-devel] " Peter Maydell 2019-07-01 18:01 ` [Qemu-riscv] " Peter Maydell 2019-07-01 18:09 ` [Qemu-devel] " Alistair Francis 2019-07-01 18:09 ` [Qemu-riscv] " Alistair Francis 2019-07-01 18:13 ` [Qemu-devel] " Peter Maydell 2019-07-01 18:13 ` [Qemu-riscv] " Peter Maydell 2019-07-01 18:19 ` [Qemu-devel] " Alistair Francis 2019-07-01 18:19 ` [Qemu-riscv] " Alistair Francis 2019-07-02 7:02 ` [Qemu-devel] " Anup Patel 2019-07-02 7:02 ` Anup Patel 2019-07-02 4:12 ` [Qemu-devel] " Markus Armbruster 2019-07-02 4:12 ` [Qemu-riscv] " Markus Armbruster 2019-07-02 10:32 ` Paolo Bonzini 2019-07-02 10:32 ` [Qemu-riscv] " Paolo Bonzini 2019-07-02 16:07 ` Alistair Francis 2019-07-02 16:07 ` [Qemu-riscv] " Alistair Francis 2019-07-04 16:00 ` Stefan Hajnoczi 2019-07-04 16:00 ` [Qemu-riscv] " Stefan Hajnoczi 2019-07-04 19:35 ` [Qemu-devel] " Alistair Francis 2019-07-04 19:35 ` [Qemu-riscv] " Alistair Francis 2019-06-27 15:20 ` [Qemu-devel] [PULL 34/34] hw/riscv: Load OpenSBI as the default firmware Palmer Dabbelt 2019-06-27 15:20 ` [Qemu-riscv] " Palmer Dabbelt 2019-06-28 17:31 [Qemu-devel] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v2 Palmer Dabbelt 2019-06-28 17:31 ` [Qemu-devel] [PULL 04/34] target/riscv: Implement riscv_cpu_unassigned_access Palmer Dabbelt
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