* [Qemu-devel] [PATCH v2 0/9] x86 CPU model versioning
@ 2019-06-28 0:28 Eduardo Habkost
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 1/9] qmp: Add "alias-of" field to query-cpu-definitions Eduardo Habkost
` (9 more replies)
0 siblings, 10 replies; 25+ messages in thread
From: Eduardo Habkost @ 2019-06-28 0:28 UTC (permalink / raw)
To: qemu-devel
Cc: Pavel Hrdina, Daniel P. Berrange, Tao Xu, Hu, Robert,
Dr. David Alan Gilbert, Paolo Bonzini, Igor Mammedov,
Jiri Denemark, Richard Henderson
Changes v1 -> v2:
* Patch "i386: Infrastructure for versioned CPU models" was
rewritten and split in two:
* i386: Register versioned CPU models
* i386: Make unversioned CPU models be aliases
* -IBRS, -noTSX, -IBPB CPU models are now aliases
* Enable rdctl-no, ibrs-all, skip-l1dfl-vmentry in
Cascadelake-Server-v2
* New patch added:
* i386: Get model-id from CPU object on "-cpu help"
---
Original description in v1:
This series implements basic infrastructure for CPU model
versioning, as discussed before[1][2][3]. This will finally
allow us to update CPU models in ways that introduce new software
or hardware requirements.
My original plan was to use "query-cpu-model-expansion
mode=static" to resolve aliases, but I dropped that plan because
it would increase complexity for management software a lot.
static CPU models are documented as not being affected by the
machine type and accelerator at all, which would make the
versioned CPU models very inconvenient to use in the command
line. e.g.: users would be forced to replace:
-cpu Haswell
with:
-cpu Haswell-4.1,+2apic,+monitor,+kvmclock,+kvm-nopiodelay,+kvm-asyncpf,+kvm-steal-time,+kvm-pv-eoi,+kvmclock-stable-bit,+x2apic,-acpi,-monitor,-svm
In the end, making the versioned CPU models static is not a
requirement at all: what we really need is to drop the
runnability guarantees from unversioned CPU model names, and
require management software to resolve the unversioned alias
before saving the VM configuration.
Guest ABI compatibility and live migration guarantees are going
to be kept: unversioned CPU models will still be usable with live
migration. Only runnability guarantees when updating the machine
type will be dropped. This means unversioned CPU models are
still reported as migration-safe in query-cpu-definitions.
The last patch in the series demonstrates how the new feature can
be used to update a CPU model: it adds a Cascadelake-Server-4.1.1
CPU model, including "arch-capabilities=on" and "stepping=5".
Unfortunately we can't enable arch-capabilities in the -4.1
version of Cascadelake-Server because it would break our existing
runnability guarantees.
[1] https://www.mail-archive.com/libvir-list@redhat.com/msg167342.html
[2] https://www.mail-archive.com/qemu-devel@nongnu.org/msg590034.html
[3] https://www.mail-archive.com/qemu-devel@nongnu.org/msg611244.html
---
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Pavel Hrdina <phrdina@redhat.com>
Cc: Jiri Denemark <jdenemar@redhat.com>
Cc: "Hu, Robert" <robert.hu@intel.com>
Cc: Tao Xu <tao3.xu@intel.com>
Cc: Richard Henderson <rth@twiddle.net>
Cc: "Dr. David Alan Gilbert" <dgilbert@redhat.com>
Cc: "Daniel P. Berrange" <berrange@redhat.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Eduardo Habkost (9):
qmp: Add "alias-of" field to query-cpu-definitions
i386: Add x-force-features option for testing
i386: Get model-id from CPU object on "-cpu help"
i386: Register versioned CPU models
i386: Define -IBRS, -noTSX, -IBRS versions of CPU models
i386: Replace -noTSX, -IBRS, -IBPB CPU models with aliases
i386: Make unversioned CPU models be aliases
docs: Deprecate CPU model runnability guarantees
i386: Add Cascadelake-Server-v2 CPU model
qapi/target.json | 9 +-
include/hw/i386/pc.h | 3 +
target/i386/cpu-qom.h | 10 +-
target/i386/cpu.h | 28 +
hw/i386/pc.c | 3 +
hw/i386/pc_piix.c | 4 +
hw/i386/pc_q35.c | 4 +
target/i386/cpu.c | 1028 +++++++++-----------
qemu-deprecated.texi | 19 +
tests/acceptance/x86_cpu_model_versions.py | 304 ++++++
10 files changed, 831 insertions(+), 581 deletions(-)
create mode 100644 tests/acceptance/x86_cpu_model_versions.py
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply [flat|nested] 25+ messages in thread
* [Qemu-devel] [PATCH v2 1/9] qmp: Add "alias-of" field to query-cpu-definitions
2019-06-28 0:28 [Qemu-devel] [PATCH v2 0/9] x86 CPU model versioning Eduardo Habkost
@ 2019-06-28 0:28 ` Eduardo Habkost
2019-07-02 9:26 ` Daniel P. Berrangé
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 2/9] i386: Add x-force-features option for testing Eduardo Habkost
` (8 subsequent siblings)
9 siblings, 1 reply; 25+ messages in thread
From: Eduardo Habkost @ 2019-06-28 0:28 UTC (permalink / raw)
To: qemu-devel
Cc: Daniel P. Berrange, Dr. David Alan Gilbert, Markus Armbruster,
Igor Mammedov, Jiri Denemark
Management software will be expected to resolve CPU model name
aliases using the new field.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
Changes v1 -> v2:
* (none)
Cc: Eric Blake <eblake@redhat.com>
Cc: Markus Armbruster <armbru@redhat.com>
---
qapi/target.json | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/qapi/target.json b/qapi/target.json
index 1d4d54b600..0197c7962c 100644
--- a/qapi/target.json
+++ b/qapi/target.json
@@ -475,6 +475,12 @@
# to introspect properties configurable using -cpu or -global.
# (since 2.9)
#
+# @alias-of: Name of CPU model this model is an alias for. The target of the
+# CPU model alias may change depending on the machine type.
+# Management software is supposed to translate CPU model aliases
+# in the VM configuration, because aliases may stop being
+# migration-safe in the future (since 4.1)
+#
# @unavailable-features is a list of QOM property names that
# represent CPU model attributes that prevent the CPU from running.
# If the QOM property is read-only, that means there's no known
@@ -498,7 +504,8 @@
'*migration-safe': 'bool',
'static': 'bool',
'*unavailable-features': [ 'str' ],
- 'typename': 'str' },
+ 'typename': 'str',
+ '*alias-of' : 'str' },
'if': 'defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_I386) || defined(TARGET_S390X) || defined(TARGET_MIPS)' }
##
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Qemu-devel] [PATCH v2 2/9] i386: Add x-force-features option for testing
2019-06-28 0:28 [Qemu-devel] [PATCH v2 0/9] x86 CPU model versioning Eduardo Habkost
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 1/9] qmp: Add "alias-of" field to query-cpu-definitions Eduardo Habkost
@ 2019-06-28 0:28 ` Eduardo Habkost
2019-07-02 9:30 ` Daniel P. Berrangé
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 3/9] i386: Get model-id from CPU object on "-cpu help" Eduardo Habkost
` (7 subsequent siblings)
9 siblings, 1 reply; 25+ messages in thread
From: Eduardo Habkost @ 2019-06-28 0:28 UTC (permalink / raw)
To: qemu-devel
Cc: Igor Mammedov, Jiri Denemark, Daniel P. Berrange, Dr. David Alan Gilbert
Add a new option that can be used to disable feature flag
filtering. This will allow CPU model compatibility test cases to
work without host hardware dependencies.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
Changes v1 -> v2:
* (none)
---
target/i386/cpu.h | 6 ++++++
target/i386/cpu.c | 8 ++++++--
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 0a96c78669..4727226a6a 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1417,6 +1417,12 @@ struct X86CPU {
bool check_cpuid;
bool enforce_cpuid;
+ /*
+ * Force features to be enabled even if the host doesn't support them.
+ * This is dangerous and should be done only for testing CPUID
+ * compatibility.
+ */
+ bool force_features;
bool expose_kvm;
bool expose_tcg;
bool migratable;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index ea52db0600..1bdb906e9f 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -5179,8 +5179,11 @@ static int x86_cpu_filter_features(X86CPU *cpu)
uint32_t host_feat =
x86_cpu_get_supported_feature_word(w, false);
uint32_t requested_features = env->features[w];
- env->features[w] &= host_feat;
- cpu->filtered_features[w] = requested_features & ~env->features[w];
+ uint32_t available_features = requested_features & host_feat;
+ if (!cpu->force_features) {
+ env->features[w] = available_features;
+ }
+ cpu->filtered_features[w] = requested_features & ~available_features;
if (cpu->filtered_features[w]) {
rv = 1;
}
@@ -5909,6 +5912,7 @@ static Property x86_cpu_properties[] = {
DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
+ DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false),
DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Qemu-devel] [PATCH v2 3/9] i386: Get model-id from CPU object on "-cpu help"
2019-06-28 0:28 [Qemu-devel] [PATCH v2 0/9] x86 CPU model versioning Eduardo Habkost
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 1/9] qmp: Add "alias-of" field to query-cpu-definitions Eduardo Habkost
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 2/9] i386: Add x-force-features option for testing Eduardo Habkost
@ 2019-06-28 0:28 ` Eduardo Habkost
2019-07-02 9:32 ` Daniel P. Berrangé
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 4/9] i386: Register versioned CPU models Eduardo Habkost
` (6 subsequent siblings)
9 siblings, 1 reply; 25+ messages in thread
From: Eduardo Habkost @ 2019-06-28 0:28 UTC (permalink / raw)
To: qemu-devel
Cc: Igor Mammedov, Jiri Denemark, Daniel P. Berrange, Dr. David Alan Gilbert
When introducing versioned CPU models, the string at
X86CPUDefinition::model_id might not be the model-id we'll really
use. Instantiate a CPU object and check the model-id property on
"-cpu help"
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
(New patch, added to series in v2)
---
target/i386/cpu.c | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 1bdb906e9f..49bf92d3f9 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3766,18 +3766,28 @@ static GSList *get_sorted_cpu_model_list(void)
return list;
}
+static char *x86_cpu_class_get_model_id(X86CPUClass *xc)
+{
+ Object *obj = object_new(object_class_get_name(OBJECT_CLASS(xc)));
+ char *r = object_property_get_str(obj, "model-id", &error_abort);
+ object_unref(obj);
+ return r;
+}
+
static void x86_cpu_list_entry(gpointer data, gpointer user_data)
{
ObjectClass *oc = data;
X86CPUClass *cc = X86_CPU_CLASS(oc);
char *name = x86_cpu_class_get_model_name(cc);
- const char *desc = cc->model_description;
- if (!desc && cc->cpu_def) {
- desc = cc->cpu_def->model_id;
+ char *desc = g_strdup(cc->model_description);
+
+ if (!desc) {
+ desc = x86_cpu_class_get_model_id(cc);
}
qemu_printf("x86 %-20s %-48s\n", name, desc);
g_free(name);
+ g_free(desc);
}
/* list available CPU models and flags */
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Qemu-devel] [PATCH v2 4/9] i386: Register versioned CPU models
2019-06-28 0:28 [Qemu-devel] [PATCH v2 0/9] x86 CPU model versioning Eduardo Habkost
` (2 preceding siblings ...)
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 3/9] i386: Get model-id from CPU object on "-cpu help" Eduardo Habkost
@ 2019-06-28 0:28 ` Eduardo Habkost
2019-07-02 9:38 ` Daniel P. Berrangé
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 5/9] i386: Define -IBRS, -noTSX, -IBRS versions of " Eduardo Habkost
` (5 subsequent siblings)
9 siblings, 1 reply; 25+ messages in thread
From: Eduardo Habkost @ 2019-06-28 0:28 UTC (permalink / raw)
To: qemu-devel
Cc: Igor Mammedov, Jiri Denemark, Daniel P. Berrange, Dr. David Alan Gilbert
Add support for registration of multiple versions of CPU models.
The existing CPU models will be registered with a "-v1" suffix.
The -noTSX, -IBRS, and -IBPB CPU model variants will become
versions of the original models in a separate patch, so
make sure we register no versions for them.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
Patch v1 was "[PATCH 4/6] i386: Infrastructure for versioned CPU
models", and was split into multiple patches.
Changes v1 -> v2:
* Make version numbers simple integers, completely independent
from machine type versions
* Don't register versions for -noTSX, -IBRS, and -IBPB CPU models
* Code for reporting alias-of on query-cpu-definitions is now in
a separate patch
* Code for machine-type compatibility is now in a separate patch
* New X86CPUVersion typedef
* New CPU_VERSION_* defines to make X86CPUModel::version
semantics clearer
---
target/i386/cpu-qom.h | 10 +-
target/i386/cpu.h | 10 +
target/i386/cpu.c | 223 +++++++++++++++++++--
tests/acceptance/x86_cpu_model_versions.py | 105 ++++++++++
4 files changed, 318 insertions(+), 30 deletions(-)
create mode 100644 tests/acceptance/x86_cpu_model_versions.py
diff --git a/target/i386/cpu-qom.h b/target/i386/cpu-qom.h
index 22f95eb3a4..1a52f02a4c 100644
--- a/target/i386/cpu-qom.h
+++ b/target/i386/cpu-qom.h
@@ -36,13 +36,7 @@
#define X86_CPU_GET_CLASS(obj) \
OBJECT_GET_CLASS(X86CPUClass, (obj), TYPE_X86_CPU)
-/**
- * X86CPUDefinition:
- *
- * CPU model definition data that was not converted to QOM per-subclass
- * property defaults yet.
- */
-typedef struct X86CPUDefinition X86CPUDefinition;
+typedef struct X86CPUModel X86CPUModel;
/**
* X86CPUClass:
@@ -64,7 +58,7 @@ typedef struct X86CPUClass {
/* CPU definition, automatically loaded by instance_init if not NULL.
* Should be eventually replaced by subclass-specific property defaults.
*/
- X86CPUDefinition *cpu_def;
+ X86CPUModel *model;
bool host_cpuid_required;
int ordering;
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 4727226a6a..12bc3cd4a8 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1929,6 +1929,16 @@ void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip,
*/
void x86_cpu_change_kvm_default(const char *prop, const char *value);
+/* Special values for X86CPUVersion: */
+
+/* Resolve to latest CPU version */
+#define CPU_VERSION_LATEST -1
+
+/* Don't resolve to any versioned CPU models, like old QEMU versions */
+#define CPU_VERSION_LEGACY 0
+
+typedef int X86CPUVersion;
+
/* Return name of 32-bit register, from a R_* constant */
const char *get_register_name_32(unsigned int reg);
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 49bf92d3f9..b304c87b0f 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1433,7 +1433,17 @@ static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
}
-struct X86CPUDefinition {
+typedef struct PropValue {
+ const char *prop, *value;
+} PropValue;
+
+typedef struct X86CPUVersionDefinition {
+ X86CPUVersion version;
+ PropValue *props;
+} X86CPUVersionDefinition;
+
+/* Base definition for a CPU model */
+typedef struct X86CPUDefinition {
const char *name;
uint32_t level;
uint32_t xlevel;
@@ -1445,8 +1455,41 @@ struct X86CPUDefinition {
FeatureWordArray features;
const char *model_id;
CPUCaches *cache_info;
+ /*
+ * Definitions for alternative versions of CPU model.
+ * List is terminated by item with version == 0.
+ * If NULL, version 1 will be registered automatically.
+ */
+ const X86CPUVersionDefinition *versions;
+} X86CPUDefinition;
+
+/* Reference to a specific CPU model version */
+struct X86CPUModel {
+ /* Base CPU definition */
+ X86CPUDefinition *cpudef;
+ /* CPU model version */
+ X86CPUVersion version;
};
+/* Get full model name for CPU version */
+static char *x86_cpu_versioned_model_name(X86CPUDefinition *cpudef,
+ X86CPUVersion version)
+{
+ assert(version > 0);
+ return g_strdup_printf("%s-v%d", cpudef->name, (int)version);
+}
+
+static const X86CPUVersionDefinition *x86_cpu_def_get_versions(X86CPUDefinition *def)
+{
+ /* When X86CPUDefinition::versions is NULL, we register only v1 */
+ static const X86CPUVersionDefinition default_version_list[] = {
+ { 1 },
+ { /* end of list */ }
+ };
+
+ return def->versions ?: default_version_list;
+}
+
static CPUCaches epyc_cache_info = {
.l1d_cache = &(CPUCacheInfo) {
.type = DATA_CACHE,
@@ -1833,6 +1876,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_EXT3_LAHF_LM,
.xlevel = 0x80000008,
.model_id = "Intel Core i7 9xx (Nehalem Core i7, IBRS update)",
+ /*
+ * This CPU model will eventually be replaced by an alias,
+ * don't register any versions for it.
+ */
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
},
{
.name = "Westmere",
@@ -1887,6 +1935,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Westmere E56xx/L56xx/X56xx (IBRS update)",
+ /*
+ * This CPU model will eventually be replaced by an alias,
+ * don't register any versions for it.
+ */
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
},
{
.name = "SandyBridge",
@@ -1951,6 +2004,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Xeon E312xx (Sandy Bridge, IBRS update)",
+ /*
+ * This CPU model will eventually be replaced by an alias,
+ * don't register any versions for it.
+ */
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
},
{
.name = "IvyBridge",
@@ -2021,6 +2079,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)",
+ /*
+ * This CPU model will eventually be replaced by an alias,
+ * don't register any versions for it.
+ */
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
},
{
.name = "Haswell-noTSX",
@@ -2057,6 +2120,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Core Processor (Haswell, no TSX)",
+ /*
+ * This CPU model will eventually be replaced by an alias,
+ * don't register any versions for it.
+ */
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
},
{
.name = "Haswell-noTSX-IBRS",
@@ -2095,6 +2163,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Core Processor (Haswell, no TSX, IBRS)",
+ /*
+ * This CPU model will eventually be replaced by an alias,
+ * don't register any versions for it.
+ */
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
},
{
.name = "Haswell",
@@ -2171,6 +2244,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Core Processor (Haswell, IBRS)",
+ /*
+ * This CPU model will eventually be replaced by an alias,
+ * don't register any versions for it.
+ */
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
},
{
.name = "Broadwell-noTSX",
@@ -2209,6 +2287,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Core Processor (Broadwell, no TSX)",
+ /*
+ * This CPU model will eventually be replaced by an alias,
+ * don't register any versions for it.
+ */
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
},
{
.name = "Broadwell-noTSX-IBRS",
@@ -2249,6 +2332,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Core Processor (Broadwell, no TSX, IBRS)",
+ /*
+ * This CPU model will eventually be replaced by an alias,
+ * don't register any versions for it.
+ */
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
},
{
.name = "Broadwell",
@@ -2327,6 +2415,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Core Processor (Broadwell, IBRS)",
+ /*
+ * This CPU model will eventually be replaced by an alias,
+ * don't register any versions for it.
+ */
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
},
{
.name = "Skylake-Client",
@@ -2419,6 +2512,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Core Processor (Skylake, IBRS)",
+ /*
+ * This CPU model will eventually be replaced by an alias,
+ * don't register any versions for it.
+ */
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
},
{
.name = "Skylake-Server",
@@ -2521,6 +2619,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Xeon Processor (Skylake, IBRS)",
+ /*
+ * This CPU model will eventually be replaced by an alias,
+ * don't register any versions for it.
+ */
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
},
{
.name = "Cascadelake-Server",
@@ -2958,6 +3061,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
.xlevel = 0x8000001E,
.model_id = "AMD EPYC Processor (with IBPB)",
.cache_info = &epyc_cache_info,
+ /*
+ * This CPU model will eventually be replaced by an alias,
+ * don't register any versions for it.
+ */
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
},
{
.name = "Dhyana",
@@ -3011,10 +3119,6 @@ static X86CPUDefinition builtin_x86_defs[] = {
},
};
-typedef struct PropValue {
- const char *prop, *value;
-} PropValue;
-
/* KVM-specific features that are automatically added/removed
* from all CPU models when KVM is enabled.
*/
@@ -3040,6 +3144,28 @@ static PropValue tcg_default_props[] = {
};
+static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model)
+{
+ int v = 0;
+ const X86CPUVersionDefinition *vdef =
+ x86_cpu_def_get_versions(model->cpudef);
+ while (vdef->version) {
+ v = vdef->version;
+ vdef++;
+ }
+ return v;
+}
+
+/* Return the actual version being used for a specific CPU model */
+static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model)
+{
+ X86CPUVersion v = model->version;
+ if (v == CPU_VERSION_LATEST) {
+ return x86_cpu_model_last_version(model);
+ }
+ return v;
+}
+
void x86_cpu_change_kvm_default(const char *prop, const char *value)
{
PropValue *pv;
@@ -3117,8 +3243,6 @@ static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
dc->props = max_x86_cpu_properties;
}
-static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp);
-
static void max_x86_cpu_initfn(Object *obj)
{
X86CPU *cpu = X86_CPU(obj);
@@ -3909,10 +4033,40 @@ static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
}
}
+/* Apply properties for the CPU model version specified in model */
+static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model)
+{
+ const X86CPUVersionDefinition *vdef;
+ X86CPUVersion version = x86_cpu_model_resolve_version(model);
+
+ if (version == CPU_VERSION_LEGACY) {
+ return;
+ }
+
+ for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) {
+ PropValue *p;
+
+ for (p = vdef->props; p && p->prop; p++) {
+ object_property_parse(OBJECT(cpu), p->value, p->prop,
+ &error_abort);
+ }
+
+ if (vdef->version == version) {
+ break;
+ }
+ }
+
+ /*
+ * If we reached the end of the list, version number was invalid
+ */
+ assert(vdef->version == version);
+}
+
/* Load data from X86CPUDefinition into a X86CPU object
*/
-static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
+static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model, Error **errp)
{
+ X86CPUDefinition *def = model->cpudef;
CPUX86State *env = &cpu->env;
const char *vendor;
char host_vendor[CPUID_VENDOR_SZ + 1];
@@ -3969,11 +4123,12 @@ static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
+ x86_cpu_apply_version_props(cpu, model);
}
#ifndef CONFIG_USER_ONLY
/* Return a QDict containing keys for all properties that can be included
- * in static expansion of CPU models. All properties set by x86_cpu_load_def()
+ * in static expansion of CPU models. All properties set by x86_cpu_load_model()
* must be included in the dictionary.
*/
static QDict *x86_cpu_static_props(void)
@@ -4187,23 +4342,33 @@ static gchar *x86_gdb_arch_name(CPUState *cs)
static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
{
- X86CPUDefinition *cpudef = data;
+ X86CPUModel *model = data;
X86CPUClass *xcc = X86_CPU_CLASS(oc);
- xcc->cpu_def = cpudef;
+ xcc->model = model;
xcc->migration_safe = true;
}
-static void x86_register_cpudef_type(X86CPUDefinition *def)
+static void x86_register_cpu_model_type(const char *name, X86CPUModel *model)
{
- char *typename = x86_cpu_type_name(def->name);
+ char *typename = x86_cpu_type_name(name);
TypeInfo ti = {
.name = typename,
.parent = TYPE_X86_CPU,
.class_init = x86_cpu_cpudef_class_init,
- .class_data = def,
+ .class_data = model,
};
+ type_register(&ti);
+ g_free(typename);
+}
+
+static void x86_register_cpudef_types(X86CPUDefinition *def)
+{
+ X86CPUModel *m;
+ const X86CPUVersionDefinition *vdef;
+ char *name;
+
/* AMD aliases are handled at runtime based on CPUID vendor, so
* they shouldn't be set on the CPU model table.
*/
@@ -4211,9 +4376,23 @@ static void x86_register_cpudef_type(X86CPUDefinition *def)
/* catch mistakes instead of silently truncating model_id when too long */
assert(def->model_id && strlen(def->model_id) <= 48);
+ /* Unversioned model: */
+ m = g_new0(X86CPUModel, 1);
+ m->cpudef = def;
+ m->version = CPU_VERSION_LEGACY;
+ x86_register_cpu_model_type(def->name, m);
+
+ /* Versioned models: */
+
+ for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) {
+ X86CPUModel *m = g_new0(X86CPUModel, 1);
+ m->cpudef = def;
+ m->version = vdef->version;
+ name = x86_cpu_versioned_model_name(def, vdef->version);
+ x86_register_cpu_model_type(name, m);
+ g_free(name);
+ }
- type_register(&ti);
- g_free(typename);
}
#if !defined(CONFIG_USER_ONLY)
@@ -5039,7 +5218,7 @@ static void x86_cpu_enable_xsave_components(X86CPU *cpu)
* involved in setting up CPUID data are:
*
* 1) Loading CPU model definition (X86CPUDefinition). This is
- * implemented by x86_cpu_load_def() and should be completely
+ * implemented by x86_cpu_load_model() and should be completely
* transparent, as it is done automatically by instance_init.
* No code should need to look at X86CPUDefinition structs
* outside instance_init.
@@ -5361,7 +5540,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
/* Cache information initialization */
if (!cpu->legacy_cache) {
- if (!xcc->cpu_def || !xcc->cpu_def->cache_info) {
+ if (!xcc->model || !xcc->model->cpudef->cache_info) {
char *name = x86_cpu_class_get_model_name(xcc);
error_setg(errp,
"CPU model '%s' doesn't support legacy-cache=off", name);
@@ -5369,7 +5548,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
return;
}
env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd =
- *xcc->cpu_def->cache_info;
+ *xcc->model->cpudef->cache_info;
} else {
/* Build legacy cache information */
env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache;
@@ -5728,8 +5907,8 @@ static void x86_cpu_initfn(Object *obj)
object_property_add_alias(obj, "sse4_1", obj, "sse4.1", &error_abort);
object_property_add_alias(obj, "sse4_2", obj, "sse4.2", &error_abort);
- if (xcc->cpu_def) {
- x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
+ if (xcc->model) {
+ x86_cpu_load_model(cpu, xcc->model, &error_abort);
}
}
@@ -6068,7 +6247,7 @@ static void x86_cpu_register_types(void)
type_register_static(&x86_cpu_type_info);
for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
- x86_register_cpudef_type(&builtin_x86_defs[i]);
+ x86_register_cpudef_types(&builtin_x86_defs[i]);
}
type_register_static(&max_x86_cpu_type_info);
type_register_static(&x86_base_cpu_type_info);
diff --git a/tests/acceptance/x86_cpu_model_versions.py b/tests/acceptance/x86_cpu_model_versions.py
new file mode 100644
index 0000000000..b85d6f8604
--- /dev/null
+++ b/tests/acceptance/x86_cpu_model_versions.py
@@ -0,0 +1,105 @@
+#!/usr/bin/env python
+#
+# Basic validation of x86 versioned CPU models and CPU model aliases
+#
+# Copyright (c) 2019 Red Hat Inc
+#
+# Author:
+# Eduardo Habkost <ehabkost@redhat.com>
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2 of the License, or (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, see <http://www.gnu.org/licenses/>.
+#
+
+
+import avocado_qemu
+import re
+
+class X86CPUModelAliases(avocado_qemu.Test):
+ """
+ Validation of PC CPU model versions and CPU model aliases
+
+ :avocado: tags=arch:x86_64
+ """
+ def validate_aliases(self, cpus):
+ for c in cpus.values():
+ if 'alias-of' in c:
+ # all aliases must point to a valid CPU model name:
+ self.assertIn(c['alias-of'], cpus,
+ '%s.alias-of (%s) is not a valid CPU model name' % (c['name'], c['alias-of']))
+ # aliases must not point to aliases
+ self.assertNotIn('alias-of', cpus[c['alias-of']],
+ '%s.alias-of (%s) points to another alias' % (c['name'], c['alias-of']))
+
+ # aliases must not be static
+ self.assertFalse(c['static'])
+
+ def validate_variant_aliases(self, cpus):
+ # -noTSX, -IBRS and -IBPB variants of CPU models are special:
+ # they shouldn't have their own versions:
+ self.assertNotIn("Haswell-noTSX-v1", cpus,
+ "Haswell-noTSX shouldn't be versioned")
+ self.assertNotIn("Broadwell-noTSX-v1", cpus,
+ "Broadwell-noTSX shouldn't be versioned")
+ self.assertNotIn("Nehalem-IBRS-v1", cpus,
+ "Nehalem-IBRS shouldn't be versioned")
+ self.assertNotIn("Westmere-IBRS-v1", cpus,
+ "Westmere-IBRS shouldn't be versioned")
+ self.assertNotIn("SandyBridge-IBRS-v1", cpus,
+ "SandyBridge-IBRS shouldn't be versioned")
+ self.assertNotIn("IvyBridge-IBRS-v1", cpus,
+ "IvyBridge-IBRS shouldn't be versioned")
+ self.assertNotIn("Haswell-noTSX-IBRS-v1", cpus,
+ "Haswell-noTSX-IBRS shouldn't be versioned")
+ self.assertNotIn("Haswell-IBRS-v1", cpus,
+ "Haswell-IBRS shouldn't be versioned")
+ self.assertNotIn("Broadwell-noTSX-IBRS-v1", cpus,
+ "Broadwell-noTSX-IBRS shouldn't be versioned")
+ self.assertNotIn("Broadwell-IBRS-v1", cpus,
+ "Broadwell-IBRS shouldn't be versioned")
+ self.assertNotIn("Skylake-Client-IBRS-v1", cpus,
+ "Skylake-Client-IBRS shouldn't be versioned")
+ self.assertNotIn("Skylake-Server-IBRS-v1", cpus,
+ "Skylake-Server-IBRS shouldn't be versioned")
+ self.assertNotIn("EPYC-IBPB-v1", cpus,
+ "EPYC-IBPB shouldn't be versioned")
+
+ def test_4_0_alias_compatibility(self):
+ """Check if pc-*-4.0 unversioned CPU model won't be reported as aliases"""
+ # pc-*-4.0 won't expose non-versioned CPU models as aliases
+ # We do this to help management software to keep compatibility
+ # with older QEMU versions that didn't have the versioned CPU model
+ self.vm.add_args('-S')
+ self.vm.set_machine('pc-i440fx-4.0')
+ self.vm.launch()
+ cpus = dict((m['name'], m) for m in self.vm.command('query-cpu-definitions'))
+
+ self.assertFalse(cpus['Cascadelake-Server']['static'],
+ 'unversioned Cascadelake-Server CPU model must not be static')
+ self.assertNotIn('alias-of', cpus['Cascadelake-Server'],
+ 'Cascadelake-Server must not be an alias')
+ self.assertNotIn('alias-of', cpus['Cascadelake-Server-v1'],
+ 'Cascadelake-Server-v1 must not be an alias')
+
+ self.assertFalse(cpus['qemu64']['static'],
+ 'unversioned qemu64 CPU model must not be static')
+ self.assertNotIn('alias-of', cpus['qemu64'],
+ 'qemu64 must not be an alias')
+ self.assertNotIn('alias-of', cpus['qemu64-v1'],
+ 'qemu64-v1 must not be an alias')
+
+ self.validate_variant_aliases(cpus)
+
+ # On pc-*-4.0, no CPU model should be reported as an alias:
+ for name,c in cpus.items():
+ self.assertNotIn('alias-of', c, "%s shouldn't be an alias" % (name))
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Qemu-devel] [PATCH v2 5/9] i386: Define -IBRS, -noTSX, -IBRS versions of CPU models
2019-06-28 0:28 [Qemu-devel] [PATCH v2 0/9] x86 CPU model versioning Eduardo Habkost
` (3 preceding siblings ...)
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 4/9] i386: Register versioned CPU models Eduardo Habkost
@ 2019-06-28 0:28 ` Eduardo Habkost
2019-07-02 9:40 ` Daniel P. Berrangé
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 6/9] i386: Replace -noTSX, -IBRS, -IBPB CPU models with aliases Eduardo Habkost
` (4 subsequent siblings)
9 siblings, 1 reply; 25+ messages in thread
From: Eduardo Habkost @ 2019-06-28 0:28 UTC (permalink / raw)
To: qemu-devel
Cc: Igor Mammedov, Jiri Denemark, Daniel P. Berrange, Dr. David Alan Gilbert
Add versions of CPU models that are equivalent to their -IBRS,
-noTSX and -IBRS variants.
The separate variants will eventually be removed and become
aliases for these CPU versions.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
(New patch, added to series in v2)
---
target/i386/cpu.c | 186 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 186 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index b304c87b0f..5d33e75890 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1851,6 +1851,20 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_EXT3_LAHF_LM,
.xlevel = 0x80000008,
.model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
+ .versions = (X86CPUVersionDefinition[]) {
+ { .version = 1 },
+ {
+ .version = 2,
+ /* Equivalent to Nehalem-IBRS */
+ .props = (PropValue[]) {
+ { "spec-ctrl", "on" },
+ { "model-id",
+ "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" },
+ { /* end of list */ }
+ }
+ },
+ { /* end of list */ }
+ }
},
{
.name = "Nehalem-IBRS",
@@ -1907,6 +1921,20 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
+ .versions = (X86CPUVersionDefinition[]) {
+ { .version = 1 },
+ {
+ .version = 2,
+ /* Equivalent to Westmere-IBRS */
+ .props = (PropValue[]) {
+ { "spec-ctrl", "on" },
+ { "model-id",
+ "Westmere E56xx/L56xx/X56xx (IBRS update)" },
+ { /* end of list */ }
+ }
+ },
+ { /* end of list */ }
+ }
},
{
.name = "Westmere-IBRS",
@@ -1971,6 +1999,20 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Xeon E312xx (Sandy Bridge)",
+ .versions = (X86CPUVersionDefinition[]) {
+ { .version = 1 },
+ {
+ .version = 2,
+ /* Equivalent to SandyBridge-IBRS */
+ .props = (PropValue[]) {
+ { "spec-ctrl", "on" },
+ { "model-id",
+ "Intel Xeon E312xx (Sandy Bridge, IBRS update)" },
+ { /* end of list */ }
+ }
+ },
+ { /* end of list */ }
+ }
},
{
.name = "SandyBridge-IBRS",
@@ -2043,6 +2085,20 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
+ .versions = (X86CPUVersionDefinition[]) {
+ { .version = 1 },
+ {
+ .version = 2,
+ /* Equivalent to IvyBridge-IBRS */
+ .props = (PropValue[]) {
+ { "spec-ctrl", "on" },
+ { "model-id",
+ "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" },
+ { /* end of list */ }
+ }
+ },
+ { /* end of list */ }
+ }
},
{
.name = "IvyBridge-IBRS",
@@ -2205,6 +2261,52 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Core Processor (Haswell)",
+ .versions = (X86CPUVersionDefinition[]) {
+ { .version = 1 },
+ {
+ .version = 2,
+ /* Equivalent to Haswell-noTSX */
+ .props = (PropValue[]) {
+ { "hle", "off" },
+ { "rtm", "off" },
+ { "stepping", "1" },
+ { "model-id", "Intel Core Processor (Haswell, no TSX)", },
+ { /* end of list */ }
+ },
+ },
+ {
+ .version = 3,
+ /* Equivalent to Haswell-IBRS */
+ .props = (PropValue[]) {
+ /* Restore TSX features removed by -v2 above */
+ { "hle", "on" },
+ { "rtm", "on" },
+ /*
+ * Haswell and Haswell-IBRS had stepping=4 in
+ * QEMU 4.0 and older
+ */
+ { "stepping", "4" },
+ { "spec-ctrl", "on" },
+ { "model-id",
+ "Intel Core Processor (Haswell, IBRS)" },
+ { /* end of list */ }
+ }
+ },
+ {
+ .version = 4,
+ /* Equivalent to Haswell-noTSX-IBRS */
+ .props = (PropValue[]) {
+ { "hle", "off" },
+ { "rtm", "off" },
+ /* spec-ctrl was already enabled by -v3 above */
+ { "stepping", "1" },
+ { "model-id",
+ "Intel Core Processor (Haswell, no TSX, IBRS)" },
+ { /* end of list */ }
+ }
+ },
+ { /* end of list */ }
+ }
},
{
.name = "Haswell-IBRS",
@@ -2375,6 +2477,45 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Core Processor (Broadwell)",
+ .versions = (X86CPUVersionDefinition[]) {
+ { .version = 1 },
+ {
+ .version = 2,
+ /* Equivalent to Broadwell-noTSX */
+ .props = (PropValue[]) {
+ { "hle", "off" },
+ { "rtm", "off" },
+ { "model-id", "Intel Core Processor (Broadwell, no TSX)", },
+ { /* end of list */ }
+ },
+ },
+ {
+ .version = 3,
+ /* Equivalent to Broadwell-IBRS */
+ .props = (PropValue[]) {
+ /* Restore TSX features removed by -v2 above */
+ { "hle", "on" },
+ { "rtm", "on" },
+ { "spec-ctrl", "on" },
+ { "model-id",
+ "Intel Core Processor (Broadwell, IBRS)" },
+ { /* end of list */ }
+ }
+ },
+ {
+ .version = 4,
+ /* Equivalent to Broadwell-noTSX-IBRS */
+ .props = (PropValue[]) {
+ { "hle", "off" },
+ { "rtm", "off" },
+ /* spec-ctrl was already enabled by -v3 above */
+ { "model-id",
+ "Intel Core Processor (Broadwell, no TSX, IBRS)" },
+ { /* end of list */ }
+ }
+ },
+ { /* end of list */ }
+ }
},
{
.name = "Broadwell-IBRS",
@@ -2465,6 +2606,20 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Core Processor (Skylake)",
+ .versions = (X86CPUVersionDefinition[]) {
+ { .version = 1 },
+ {
+ .version = 2,
+ /* Equivalent to Skylake-Client-IBRS */
+ .props = (PropValue[]) {
+ { "spec-ctrl", "on" },
+ { "model-id",
+ "Intel Core Processor (Skylake, IBRS)" },
+ { /* end of list */ }
+ }
+ },
+ { /* end of list */ }
+ }
},
{
.name = "Skylake-Client-IBRS",
@@ -2567,6 +2722,23 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Xeon Processor (Skylake)",
+ .versions = (X86CPUVersionDefinition[]) {
+ { .version = 1 },
+ {
+ .version = 2,
+ /* Equivalent to Skylake-Server-IBRS */
+ .props = (PropValue[]) {
+ /* clflushopt was not added to Skylake-Server-IBRS */
+ /* TODO: add -v3 including clflushopt */
+ { "clflushopt", "off" },
+ { "spec-ctrl", "on" },
+ { "model-id",
+ "Intel Xeon Processor (Skylake, IBRS)" },
+ { /* end of list */ }
+ }
+ },
+ { /* end of list */ }
+ }
},
{
.name = "Skylake-Server-IBRS",
@@ -3011,6 +3183,20 @@ static X86CPUDefinition builtin_x86_defs[] = {
.xlevel = 0x8000001E,
.model_id = "AMD EPYC Processor",
.cache_info = &epyc_cache_info,
+ .versions = (X86CPUVersionDefinition[]) {
+ { .version = 1 },
+ {
+ .version = 2,
+ /* Equivalent to EPYC-IBPB */
+ .props = (PropValue[]) {
+ { "ibpb", "on" },
+ { "model-id",
+ "AMD EPYC Processor (with IBPB)" },
+ { /* end of list */ }
+ }
+ },
+ { /* end of list */ }
+ }
},
{
.name = "EPYC-IBPB",
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Qemu-devel] [PATCH v2 6/9] i386: Replace -noTSX, -IBRS, -IBPB CPU models with aliases
2019-06-28 0:28 [Qemu-devel] [PATCH v2 0/9] x86 CPU model versioning Eduardo Habkost
` (4 preceding siblings ...)
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 5/9] i386: Define -IBRS, -noTSX, -IBRS versions of " Eduardo Habkost
@ 2019-06-28 0:28 ` Eduardo Habkost
2019-07-02 9:41 ` Daniel P. Berrangé
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 7/9] i386: Make unversioned CPU models be aliases Eduardo Habkost
` (3 subsequent siblings)
9 siblings, 1 reply; 25+ messages in thread
From: Eduardo Habkost @ 2019-06-28 0:28 UTC (permalink / raw)
To: qemu-devel
Cc: Igor Mammedov, Jiri Denemark, Daniel P. Berrange, Dr. David Alan Gilbert
The old CPU models will be just aliases for specific versions of
the original CPU models.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
(New patch, added to series in v2)
---
target/i386/cpu.c | 601 ++--------------------------------------------
1 file changed, 21 insertions(+), 580 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 5d33e75890..cddea91b1f 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1439,6 +1439,7 @@ typedef struct PropValue {
typedef struct X86CPUVersionDefinition {
X86CPUVersion version;
+ const char *alias;
PropValue *props;
} X86CPUVersionDefinition;
@@ -1855,7 +1856,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ .version = 1 },
{
.version = 2,
- /* Equivalent to Nehalem-IBRS */
+ .alias = "Nehalem-IBRS",
.props = (PropValue[]) {
{ "spec-ctrl", "on" },
{ "model-id",
@@ -1866,36 +1867,6 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ /* end of list */ }
}
},
- {
- .name = "Nehalem-IBRS",
- .level = 11,
- .vendor = CPUID_VENDOR_INTEL,
- .family = 6,
- .model = 26,
- .stepping = 3,
- .features[FEAT_1_EDX] =
- CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
- CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
- CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
- CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
- CPUID_DE | CPUID_FP87,
- .features[FEAT_1_ECX] =
- CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
- CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
- .features[FEAT_7_0_EDX] =
- CPUID_7_0_EDX_SPEC_CTRL,
- .features[FEAT_8000_0001_EDX] =
- CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
- .features[FEAT_8000_0001_ECX] =
- CPUID_EXT3_LAHF_LM,
- .xlevel = 0x80000008,
- .model_id = "Intel Core i7 9xx (Nehalem Core i7, IBRS update)",
- /*
- * This CPU model will eventually be replaced by an alias,
- * don't register any versions for it.
- */
- .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
- },
{
.name = "Westmere",
.level = 11,
@@ -1925,7 +1896,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ .version = 1 },
{
.version = 2,
- /* Equivalent to Westmere-IBRS */
+ .alias = "Westmere-IBRS",
.props = (PropValue[]) {
{ "spec-ctrl", "on" },
{ "model-id",
@@ -1936,39 +1907,6 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ /* end of list */ }
}
},
- {
- .name = "Westmere-IBRS",
- .level = 11,
- .vendor = CPUID_VENDOR_INTEL,
- .family = 6,
- .model = 44,
- .stepping = 1,
- .features[FEAT_1_EDX] =
- CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
- CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
- CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
- CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
- CPUID_DE | CPUID_FP87,
- .features[FEAT_1_ECX] =
- CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
- CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
- CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
- .features[FEAT_8000_0001_EDX] =
- CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
- .features[FEAT_8000_0001_ECX] =
- CPUID_EXT3_LAHF_LM,
- .features[FEAT_7_0_EDX] =
- CPUID_7_0_EDX_SPEC_CTRL,
- .features[FEAT_6_EAX] =
- CPUID_6_EAX_ARAT,
- .xlevel = 0x80000008,
- .model_id = "Westmere E56xx/L56xx/X56xx (IBRS update)",
- /*
- * This CPU model will eventually be replaced by an alias,
- * don't register any versions for it.
- */
- .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
- },
{
.name = "SandyBridge",
.level = 0xd,
@@ -2003,7 +1941,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ .version = 1 },
{
.version = 2,
- /* Equivalent to SandyBridge-IBRS */
+ .alias = "SandyBridge-IBRS",
.props = (PropValue[]) {
{ "spec-ctrl", "on" },
{ "model-id",
@@ -2014,44 +1952,6 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ /* end of list */ }
}
},
- {
- .name = "SandyBridge-IBRS",
- .level = 0xd,
- .vendor = CPUID_VENDOR_INTEL,
- .family = 6,
- .model = 42,
- .stepping = 1,
- .features[FEAT_1_EDX] =
- CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
- CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
- CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
- CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
- CPUID_DE | CPUID_FP87,
- .features[FEAT_1_ECX] =
- CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
- CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
- CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
- CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
- CPUID_EXT_SSE3,
- .features[FEAT_8000_0001_EDX] =
- CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
- CPUID_EXT2_SYSCALL,
- .features[FEAT_8000_0001_ECX] =
- CPUID_EXT3_LAHF_LM,
- .features[FEAT_7_0_EDX] =
- CPUID_7_0_EDX_SPEC_CTRL,
- .features[FEAT_XSAVE] =
- CPUID_XSAVE_XSAVEOPT,
- .features[FEAT_6_EAX] =
- CPUID_6_EAX_ARAT,
- .xlevel = 0x80000008,
- .model_id = "Intel Xeon E312xx (Sandy Bridge, IBRS update)",
- /*
- * This CPU model will eventually be replaced by an alias,
- * don't register any versions for it.
- */
- .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
- },
{
.name = "IvyBridge",
.level = 0xd,
@@ -2089,7 +1989,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ .version = 1 },
{
.version = 2,
- /* Equivalent to IvyBridge-IBRS */
+ .alias = "IvyBridge-IBRS",
.props = (PropValue[]) {
{ "spec-ctrl", "on" },
{ "model-id",
@@ -2100,131 +2000,6 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ /* end of list */ }
}
},
- {
- .name = "IvyBridge-IBRS",
- .level = 0xd,
- .vendor = CPUID_VENDOR_INTEL,
- .family = 6,
- .model = 58,
- .stepping = 9,
- .features[FEAT_1_EDX] =
- CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
- CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
- CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
- CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
- CPUID_DE | CPUID_FP87,
- .features[FEAT_1_ECX] =
- CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
- CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
- CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
- CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
- CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
- .features[FEAT_7_0_EBX] =
- CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
- CPUID_7_0_EBX_ERMS,
- .features[FEAT_8000_0001_EDX] =
- CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
- CPUID_EXT2_SYSCALL,
- .features[FEAT_8000_0001_ECX] =
- CPUID_EXT3_LAHF_LM,
- .features[FEAT_7_0_EDX] =
- CPUID_7_0_EDX_SPEC_CTRL,
- .features[FEAT_XSAVE] =
- CPUID_XSAVE_XSAVEOPT,
- .features[FEAT_6_EAX] =
- CPUID_6_EAX_ARAT,
- .xlevel = 0x80000008,
- .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)",
- /*
- * This CPU model will eventually be replaced by an alias,
- * don't register any versions for it.
- */
- .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
- },
- {
- .name = "Haswell-noTSX",
- .level = 0xd,
- .vendor = CPUID_VENDOR_INTEL,
- .family = 6,
- .model = 60,
- .stepping = 1,
- .features[FEAT_1_EDX] =
- CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
- CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
- CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
- CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
- CPUID_DE | CPUID_FP87,
- .features[FEAT_1_ECX] =
- CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
- CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
- CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
- CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
- CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
- CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
- .features[FEAT_8000_0001_EDX] =
- CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
- CPUID_EXT2_SYSCALL,
- .features[FEAT_8000_0001_ECX] =
- CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
- .features[FEAT_7_0_EBX] =
- CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
- CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
- CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
- .features[FEAT_XSAVE] =
- CPUID_XSAVE_XSAVEOPT,
- .features[FEAT_6_EAX] =
- CPUID_6_EAX_ARAT,
- .xlevel = 0x80000008,
- .model_id = "Intel Core Processor (Haswell, no TSX)",
- /*
- * This CPU model will eventually be replaced by an alias,
- * don't register any versions for it.
- */
- .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
- },
- {
- .name = "Haswell-noTSX-IBRS",
- .level = 0xd,
- .vendor = CPUID_VENDOR_INTEL,
- .family = 6,
- .model = 60,
- .stepping = 1,
- .features[FEAT_1_EDX] =
- CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
- CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
- CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
- CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
- CPUID_DE | CPUID_FP87,
- .features[FEAT_1_ECX] =
- CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
- CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
- CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
- CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
- CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
- CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
- .features[FEAT_8000_0001_EDX] =
- CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
- CPUID_EXT2_SYSCALL,
- .features[FEAT_8000_0001_ECX] =
- CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
- .features[FEAT_7_0_EDX] =
- CPUID_7_0_EDX_SPEC_CTRL,
- .features[FEAT_7_0_EBX] =
- CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
- CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
- CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
- .features[FEAT_XSAVE] =
- CPUID_XSAVE_XSAVEOPT,
- .features[FEAT_6_EAX] =
- CPUID_6_EAX_ARAT,
- .xlevel = 0x80000008,
- .model_id = "Intel Core Processor (Haswell, no TSX, IBRS)",
- /*
- * This CPU model will eventually be replaced by an alias,
- * don't register any versions for it.
- */
- .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
- },
{
.name = "Haswell",
.level = 0xd,
@@ -2265,7 +2040,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ .version = 1 },
{
.version = 2,
- /* Equivalent to Haswell-noTSX */
+ .alias = "Haswell-noTSX",
.props = (PropValue[]) {
{ "hle", "off" },
{ "rtm", "off" },
@@ -2276,7 +2051,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
},
{
.version = 3,
- /* Equivalent to Haswell-IBRS */
+ .alias = "Haswell-IBRS",
.props = (PropValue[]) {
/* Restore TSX features removed by -v2 above */
{ "hle", "on" },
@@ -2294,7 +2069,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
},
{
.version = 4,
- /* Equivalent to Haswell-noTSX-IBRS */
+ .alias = "Haswell-noTSX-IBRS",
.props = (PropValue[]) {
{ "hle", "off" },
{ "rtm", "off" },
@@ -2308,138 +2083,6 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ /* end of list */ }
}
},
- {
- .name = "Haswell-IBRS",
- .level = 0xd,
- .vendor = CPUID_VENDOR_INTEL,
- .family = 6,
- .model = 60,
- .stepping = 4,
- .features[FEAT_1_EDX] =
- CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
- CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
- CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
- CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
- CPUID_DE | CPUID_FP87,
- .features[FEAT_1_ECX] =
- CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
- CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
- CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
- CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
- CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
- CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
- .features[FEAT_8000_0001_EDX] =
- CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
- CPUID_EXT2_SYSCALL,
- .features[FEAT_8000_0001_ECX] =
- CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
- .features[FEAT_7_0_EDX] =
- CPUID_7_0_EDX_SPEC_CTRL,
- .features[FEAT_7_0_EBX] =
- CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
- CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
- CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
- CPUID_7_0_EBX_RTM,
- .features[FEAT_XSAVE] =
- CPUID_XSAVE_XSAVEOPT,
- .features[FEAT_6_EAX] =
- CPUID_6_EAX_ARAT,
- .xlevel = 0x80000008,
- .model_id = "Intel Core Processor (Haswell, IBRS)",
- /*
- * This CPU model will eventually be replaced by an alias,
- * don't register any versions for it.
- */
- .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
- },
- {
- .name = "Broadwell-noTSX",
- .level = 0xd,
- .vendor = CPUID_VENDOR_INTEL,
- .family = 6,
- .model = 61,
- .stepping = 2,
- .features[FEAT_1_EDX] =
- CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
- CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
- CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
- CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
- CPUID_DE | CPUID_FP87,
- .features[FEAT_1_ECX] =
- CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
- CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
- CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
- CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
- CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
- CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
- .features[FEAT_8000_0001_EDX] =
- CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
- CPUID_EXT2_SYSCALL,
- .features[FEAT_8000_0001_ECX] =
- CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
- .features[FEAT_7_0_EBX] =
- CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
- CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
- CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
- CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
- CPUID_7_0_EBX_SMAP,
- .features[FEAT_XSAVE] =
- CPUID_XSAVE_XSAVEOPT,
- .features[FEAT_6_EAX] =
- CPUID_6_EAX_ARAT,
- .xlevel = 0x80000008,
- .model_id = "Intel Core Processor (Broadwell, no TSX)",
- /*
- * This CPU model will eventually be replaced by an alias,
- * don't register any versions for it.
- */
- .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
- },
- {
- .name = "Broadwell-noTSX-IBRS",
- .level = 0xd,
- .vendor = CPUID_VENDOR_INTEL,
- .family = 6,
- .model = 61,
- .stepping = 2,
- .features[FEAT_1_EDX] =
- CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
- CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
- CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
- CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
- CPUID_DE | CPUID_FP87,
- .features[FEAT_1_ECX] =
- CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
- CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
- CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
- CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
- CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
- CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
- .features[FEAT_8000_0001_EDX] =
- CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
- CPUID_EXT2_SYSCALL,
- .features[FEAT_8000_0001_ECX] =
- CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
- .features[FEAT_7_0_EDX] =
- CPUID_7_0_EDX_SPEC_CTRL,
- .features[FEAT_7_0_EBX] =
- CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
- CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
- CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
- CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
- CPUID_7_0_EBX_SMAP,
- .features[FEAT_XSAVE] =
- CPUID_XSAVE_XSAVEOPT,
- .features[FEAT_6_EAX] =
- CPUID_6_EAX_ARAT,
- .xlevel = 0x80000008,
- .model_id = "Intel Core Processor (Broadwell, no TSX, IBRS)",
- /*
- * This CPU model will eventually be replaced by an alias,
- * don't register any versions for it.
- */
- .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
- },
{
.name = "Broadwell",
.level = 0xd,
@@ -2481,7 +2124,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ .version = 1 },
{
.version = 2,
- /* Equivalent to Broadwell-noTSX */
+ .alias = "Broadwell-noTSX",
.props = (PropValue[]) {
{ "hle", "off" },
{ "rtm", "off" },
@@ -2491,7 +2134,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
},
{
.version = 3,
- /* Equivalent to Broadwell-IBRS */
+ .alias = "Broadwell-IBRS",
.props = (PropValue[]) {
/* Restore TSX features removed by -v2 above */
{ "hle", "on" },
@@ -2504,7 +2147,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
},
{
.version = 4,
- /* Equivalent to Broadwell-noTSX-IBRS */
+ .alias = "Broadwell-noTSX-IBRS",
.props = (PropValue[]) {
{ "hle", "off" },
{ "rtm", "off" },
@@ -2517,51 +2160,6 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ /* end of list */ }
}
},
- {
- .name = "Broadwell-IBRS",
- .level = 0xd,
- .vendor = CPUID_VENDOR_INTEL,
- .family = 6,
- .model = 61,
- .stepping = 2,
- .features[FEAT_1_EDX] =
- CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
- CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
- CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
- CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
- CPUID_DE | CPUID_FP87,
- .features[FEAT_1_ECX] =
- CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
- CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
- CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
- CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
- CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
- CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
- .features[FEAT_8000_0001_EDX] =
- CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
- CPUID_EXT2_SYSCALL,
- .features[FEAT_8000_0001_ECX] =
- CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
- .features[FEAT_7_0_EDX] =
- CPUID_7_0_EDX_SPEC_CTRL,
- .features[FEAT_7_0_EBX] =
- CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
- CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
- CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
- CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
- CPUID_7_0_EBX_SMAP,
- .features[FEAT_XSAVE] =
- CPUID_XSAVE_XSAVEOPT,
- .features[FEAT_6_EAX] =
- CPUID_6_EAX_ARAT,
- .xlevel = 0x80000008,
- .model_id = "Intel Core Processor (Broadwell, IBRS)",
- /*
- * This CPU model will eventually be replaced by an alias,
- * don't register any versions for it.
- */
- .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
- },
{
.name = "Skylake-Client",
.level = 0xd,
@@ -2610,7 +2208,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ .version = 1 },
{
.version = 2,
- /* Equivalent to Skylake-Client-IBRS */
+ .alias = "Skylake-Client-IBRS",
.props = (PropValue[]) {
{ "spec-ctrl", "on" },
{ "model-id",
@@ -2621,58 +2219,6 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ /* end of list */ }
}
},
- {
- .name = "Skylake-Client-IBRS",
- .level = 0xd,
- .vendor = CPUID_VENDOR_INTEL,
- .family = 6,
- .model = 94,
- .stepping = 3,
- .features[FEAT_1_EDX] =
- CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
- CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
- CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
- CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
- CPUID_DE | CPUID_FP87,
- .features[FEAT_1_ECX] =
- CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
- CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
- CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
- CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
- CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
- CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
- .features[FEAT_8000_0001_EDX] =
- CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
- CPUID_EXT2_SYSCALL,
- .features[FEAT_8000_0001_ECX] =
- CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
- .features[FEAT_7_0_EDX] =
- CPUID_7_0_EDX_SPEC_CTRL,
- .features[FEAT_7_0_EBX] =
- CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
- CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
- CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
- CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
- CPUID_7_0_EBX_SMAP,
- /* Missing: XSAVES (not supported by some Linux versions,
- * including v4.1 to v4.12).
- * KVM doesn't yet expose any XSAVES state save component,
- * and the only one defined in Skylake (processor tracing)
- * probably will block migration anyway.
- */
- .features[FEAT_XSAVE] =
- CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
- CPUID_XSAVE_XGETBV1,
- .features[FEAT_6_EAX] =
- CPUID_6_EAX_ARAT,
- .xlevel = 0x80000008,
- .model_id = "Intel Core Processor (Skylake, IBRS)",
- /*
- * This CPU model will eventually be replaced by an alias,
- * don't register any versions for it.
- */
- .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
- },
{
.name = "Skylake-Server",
.level = 0xd,
@@ -2726,7 +2272,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ .version = 1 },
{
.version = 2,
- /* Equivalent to Skylake-Server-IBRS */
+ .alias = "Skylake-Server-IBRS",
.props = (PropValue[]) {
/* clflushopt was not added to Skylake-Server-IBRS */
/* TODO: add -v3 including clflushopt */
@@ -2740,63 +2286,6 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ /* end of list */ }
}
},
- {
- .name = "Skylake-Server-IBRS",
- .level = 0xd,
- .vendor = CPUID_VENDOR_INTEL,
- .family = 6,
- .model = 85,
- .stepping = 4,
- .features[FEAT_1_EDX] =
- CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
- CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
- CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
- CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
- CPUID_DE | CPUID_FP87,
- .features[FEAT_1_ECX] =
- CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
- CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
- CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
- CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
- CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
- CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
- .features[FEAT_8000_0001_EDX] =
- CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
- CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
- .features[FEAT_8000_0001_ECX] =
- CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
- .features[FEAT_7_0_EDX] =
- CPUID_7_0_EDX_SPEC_CTRL,
- .features[FEAT_7_0_EBX] =
- CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
- CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
- CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
- CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
- CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
- CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
- CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
- CPUID_7_0_EBX_AVX512VL,
- .features[FEAT_7_0_ECX] =
- CPUID_7_0_ECX_PKU,
- /* Missing: XSAVES (not supported by some Linux versions,
- * including v4.1 to v4.12).
- * KVM doesn't yet expose any XSAVES state save component,
- * and the only one defined in Skylake (processor tracing)
- * probably will block migration anyway.
- */
- .features[FEAT_XSAVE] =
- CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
- CPUID_XSAVE_XGETBV1,
- .features[FEAT_6_EAX] =
- CPUID_6_EAX_ARAT,
- .xlevel = 0x80000008,
- .model_id = "Intel Xeon Processor (Skylake, IBRS)",
- /*
- * This CPU model will eventually be replaced by an alias,
- * don't register any versions for it.
- */
- .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
- },
{
.name = "Cascadelake-Server",
.level = 0xd,
@@ -3187,7 +2676,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ .version = 1 },
{
.version = 2,
- /* Equivalent to EPYC-IBPB */
+ .alias = "EPYC-IBPB",
.props = (PropValue[]) {
{ "ibpb", "on" },
{ "model-id",
@@ -3198,61 +2687,6 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ /* end of list */ }
}
},
- {
- .name = "EPYC-IBPB",
- .level = 0xd,
- .vendor = CPUID_VENDOR_AMD,
- .family = 23,
- .model = 1,
- .stepping = 2,
- .features[FEAT_1_EDX] =
- CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
- CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
- CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
- CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
- CPUID_VME | CPUID_FP87,
- .features[FEAT_1_ECX] =
- CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
- CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
- CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
- CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
- CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
- .features[FEAT_8000_0001_EDX] =
- CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
- CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
- CPUID_EXT2_SYSCALL,
- .features[FEAT_8000_0001_ECX] =
- CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
- CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
- CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
- CPUID_EXT3_TOPOEXT,
- .features[FEAT_8000_0008_EBX] =
- CPUID_8000_0008_EBX_IBPB,
- .features[FEAT_7_0_EBX] =
- CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
- CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
- CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
- CPUID_7_0_EBX_SHA_NI,
- /* Missing: XSAVES (not supported by some Linux versions,
- * including v4.1 to v4.12).
- * KVM doesn't yet expose any XSAVES state save component.
- */
- .features[FEAT_XSAVE] =
- CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
- CPUID_XSAVE_XGETBV1,
- .features[FEAT_6_EAX] =
- CPUID_6_EAX_ARAT,
- .features[FEAT_SVM] =
- CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
- .xlevel = 0x8000001E,
- .model_id = "AMD EPYC Processor (with IBPB)",
- .cache_info = &epyc_cache_info,
- /*
- * This CPU model will eventually be replaced by an alias,
- * don't register any versions for it.
- */
- .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
- },
{
.name = "Dhyana",
.level = 0xd,
@@ -4577,6 +4011,13 @@ static void x86_register_cpudef_types(X86CPUDefinition *def)
name = x86_cpu_versioned_model_name(def, vdef->version);
x86_register_cpu_model_type(name, m);
g_free(name);
+
+ if (vdef->alias) {
+ X86CPUModel *am = g_new0(X86CPUModel, 1);
+ am->cpudef = def;
+ am->version = vdef->version;
+ x86_register_cpu_model_type(vdef->alias, am);
+ }
}
}
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Qemu-devel] [PATCH v2 7/9] i386: Make unversioned CPU models be aliases
2019-06-28 0:28 [Qemu-devel] [PATCH v2 0/9] x86 CPU model versioning Eduardo Habkost
` (5 preceding siblings ...)
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 6/9] i386: Replace -noTSX, -IBRS, -IBPB CPU models with aliases Eduardo Habkost
@ 2019-06-28 0:28 ` Eduardo Habkost
2019-07-02 9:45 ` Daniel P. Berrangé
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 8/9] docs: Deprecate CPU model runnability guarantees Eduardo Habkost
` (2 subsequent siblings)
9 siblings, 1 reply; 25+ messages in thread
From: Eduardo Habkost @ 2019-06-28 0:28 UTC (permalink / raw)
To: qemu-devel
Cc: Igor Mammedov, Jiri Denemark, Daniel P. Berrange, Dr. David Alan Gilbert
This will make unversioned CPU models behavior depend on the
machine type:
* "pc-*-4.0" and older will not report them as aliases.
This is done to keep compatibility with older QEMU versions
after management software starts translating aliases.
* "pc-*-4.1" will translate unversioned CPU models to -v1.
This is done to keep compatibility with existing management
software, that still relies on CPU model runnability promises.
* "none" will translate unversioned CPU models to their latest
version. This is planned become the default in future machine
types (probably in pc-*-4.3).
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
Patch v1 was "[PATCH 4/6] i386: Infrastructure for versioned CPU
models", and was split into multiple patches.
Changes v1 -> v2:
* Make version numbers simple integers, completely independent
from machine type versions
* New X86CPUVersion typedef
* New CPU_VERSION_* defines to make X86CPUModel::version
semantics clearer
---
include/hw/i386/pc.h | 3 +
target/i386/cpu.h | 12 ++
hw/i386/pc.c | 3 +
hw/i386/pc_piix.c | 4 +
hw/i386/pc_q35.c | 4 +
target/i386/cpu.c | 52 ++++++++-
tests/acceptance/x86_cpu_model_versions.py | 126 +++++++++++++++++++++
7 files changed, 203 insertions(+), 1 deletion(-)
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index ee79d71ccc..1946c1023f 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -109,6 +109,9 @@ typedef struct PCMachineClass {
/* Compat options: */
+ /* Default CPU model version. See x86_cpu_set_default_version(). */
+ int default_cpu_version;
+
/* ACPI compat: */
bool has_acpi_build;
bool rsdp_in_ram;
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 12bc3cd4a8..05393cf9d1 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1934,11 +1934,23 @@ void x86_cpu_change_kvm_default(const char *prop, const char *value);
/* Resolve to latest CPU version */
#define CPU_VERSION_LATEST -1
+/*
+ * Resolve to version defined by current machine type.
+ * See x86_cpu_set_default_version()
+ */
+#define CPU_VERSION_AUTO -2
+
/* Don't resolve to any versioned CPU models, like old QEMU versions */
#define CPU_VERSION_LEGACY 0
typedef int X86CPUVersion;
+/*
+ * Set default CPU model version for CPU models having
+ * version == CPU_VERSION_AUTO.
+ */
+void x86_cpu_set_default_version(X86CPUVersion version);
+
/* Return name of 32-bit register, from a R_* constant */
const char *get_register_name_32(unsigned int reg);
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 3f0f221a5b..1df569620a 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1649,6 +1649,9 @@ void pc_cpus_init(PCMachineState *pcms)
const CPUArchIdList *possible_cpus;
MachineState *ms = MACHINE(pcms);
MachineClass *mc = MACHINE_GET_CLASS(pcms);
+ PCMachineClass *pcmc = PC_MACHINE_CLASS(mc);
+
+ x86_cpu_set_default_version(pcmc->default_cpu_version);
/* Calculates the limit to CPU APIC ID values
*
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index c07c4a5b38..0a069bff54 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -430,9 +430,11 @@ static void pc_i440fx_machine_options(MachineClass *m)
static void pc_i440fx_4_1_machine_options(MachineClass *m)
{
+ PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
pc_i440fx_machine_options(m);
m->alias = "pc";
m->is_default = 1;
+ pcmc->default_cpu_version = 1;
}
DEFINE_I440FX_MACHINE(v4_1, "pc-i440fx-4.1", NULL,
@@ -440,9 +442,11 @@ DEFINE_I440FX_MACHINE(v4_1, "pc-i440fx-4.1", NULL,
static void pc_i440fx_4_0_machine_options(MachineClass *m)
{
+ PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
pc_i440fx_4_1_machine_options(m);
m->alias = NULL;
m->is_default = 0;
+ pcmc->default_cpu_version = CPU_VERSION_LEGACY;
compat_props_add(m->compat_props, hw_compat_4_0, hw_compat_4_0_len);
compat_props_add(m->compat_props, pc_compat_4_0, pc_compat_4_0_len);
}
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 57232aed6b..397e1fdd2f 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -367,8 +367,10 @@ static void pc_q35_machine_options(MachineClass *m)
static void pc_q35_4_1_machine_options(MachineClass *m)
{
+ PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
pc_q35_machine_options(m);
m->alias = "q35";
+ pcmc->default_cpu_version = 1;
}
DEFINE_Q35_MACHINE(v4_1, "pc-q35-4.1", NULL,
@@ -376,8 +378,10 @@ DEFINE_Q35_MACHINE(v4_1, "pc-q35-4.1", NULL,
static void pc_q35_4_0_1_machine_options(MachineClass *m)
{
+ PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
pc_q35_4_1_machine_options(m);
m->alias = NULL;
+ pcmc->default_cpu_version = CPU_VERSION_LEGACY;
/*
* This is the default machine for the 4.0-stable branch. It is basically
* a 4.0 that doesn't use split irqchip by default. It MUST hence apply the
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index cddea91b1f..10a09c971a 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1470,6 +1470,11 @@ struct X86CPUModel {
X86CPUDefinition *cpudef;
/* CPU model version */
X86CPUVersion version;
+ /*
+ * If true, this is an alias CPU model.
+ * This matters only for "-cpu help" and query-cpu-definitions
+ */
+ bool is_alias;
};
/* Get full model name for CPU version */
@@ -2764,6 +2769,15 @@ static PropValue tcg_default_props[] = {
};
+X86CPUVersion default_cpu_version = CPU_VERSION_LATEST;
+
+void x86_cpu_set_default_version(X86CPUVersion version)
+{
+ /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */
+ assert(version != CPU_VERSION_AUTO);
+ default_cpu_version = version;
+}
+
static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model)
{
int v = 0;
@@ -2780,6 +2794,9 @@ static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model)
static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model)
{
X86CPUVersion v = model->version;
+ if (v == CPU_VERSION_AUTO) {
+ v = default_cpu_version;
+ }
if (v == CPU_VERSION_LATEST) {
return x86_cpu_model_last_version(model);
}
@@ -3518,13 +3535,35 @@ static char *x86_cpu_class_get_model_id(X86CPUClass *xc)
return r;
}
+static char *x86_cpu_class_get_alias_of(X86CPUClass *cc)
+{
+ X86CPUVersion version;
+
+ if (!cc->model || !cc->model->is_alias) {
+ return NULL;
+ }
+ version = x86_cpu_model_resolve_version(cc->model);
+ if (version <= 0) {
+ return NULL;
+ }
+ return x86_cpu_versioned_model_name(cc->model->cpudef, version);
+}
+
static void x86_cpu_list_entry(gpointer data, gpointer user_data)
{
ObjectClass *oc = data;
X86CPUClass *cc = X86_CPU_CLASS(oc);
char *name = x86_cpu_class_get_model_name(cc);
char *desc = g_strdup(cc->model_description);
+ char *alias_of = x86_cpu_class_get_alias_of(cc);
+ if (!desc && alias_of) {
+ if (cc->model && cc->model->version == CPU_VERSION_AUTO) {
+ desc = g_strdup("(alias configured by machine type)");
+ } else {
+ desc = g_strdup_printf("(alias of %s)", alias_of);
+ }
+ }
if (!desc) {
desc = x86_cpu_class_get_model_id(cc);
}
@@ -3532,6 +3571,7 @@ static void x86_cpu_list_entry(gpointer data, gpointer user_data)
qemu_printf("x86 %-20s %-48s\n", name, desc);
g_free(name);
g_free(desc);
+ g_free(alias_of);
}
/* list available CPU models and flags */
@@ -3580,6 +3620,14 @@ static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
info->migration_safe = cc->migration_safe;
info->has_migration_safe = true;
info->q_static = cc->static_model;
+ /*
+ * Old machine types won't report aliases, so that alias translation
+ * doesn't break compatibility with previous QEMU versions.
+ */
+ if (default_cpu_version != CPU_VERSION_LEGACY) {
+ info->alias_of = x86_cpu_class_get_alias_of(cc);
+ info->has_alias_of = !!info->alias_of;
+ }
entry = g_malloc0(sizeof(*entry));
entry->value = info;
@@ -3999,7 +4047,8 @@ static void x86_register_cpudef_types(X86CPUDefinition *def)
/* Unversioned model: */
m = g_new0(X86CPUModel, 1);
m->cpudef = def;
- m->version = CPU_VERSION_LEGACY;
+ m->version = CPU_VERSION_AUTO;
+ m->is_alias = true;
x86_register_cpu_model_type(def->name, m);
/* Versioned models: */
@@ -4016,6 +4065,7 @@ static void x86_register_cpudef_types(X86CPUDefinition *def)
X86CPUModel *am = g_new0(X86CPUModel, 1);
am->cpudef = def;
am->version = vdef->version;
+ am->is_alias = true;
x86_register_cpu_model_type(vdef->alias, am);
}
}
diff --git a/tests/acceptance/x86_cpu_model_versions.py b/tests/acceptance/x86_cpu_model_versions.py
index b85d6f8604..165c0c7601 100644
--- a/tests/acceptance/x86_cpu_model_versions.py
+++ b/tests/acceptance/x86_cpu_model_versions.py
@@ -103,3 +103,129 @@ class X86CPUModelAliases(avocado_qemu.Test):
# On pc-*-4.0, no CPU model should be reported as an alias:
for name,c in cpus.items():
self.assertNotIn('alias-of', c, "%s shouldn't be an alias" % (name))
+
+ def test_4_1_alias(self):
+ """Check if unversioned CPU model is an alias pointing to right version"""
+ self.vm.add_args('-S')
+ self.vm.set_machine('pc-i440fx-4.1')
+ self.vm.launch()
+
+ cpus = dict((m['name'], m) for m in self.vm.command('query-cpu-definitions'))
+
+ self.assertFalse(cpus['Cascadelake-Server']['static'],
+ 'unversioned Cascadelake-Server CPU model must not be static')
+ self.assertEquals(cpus['Cascadelake-Server'].get('alias-of'), 'Cascadelake-Server-v1',
+ 'Cascadelake-Server must be an alias of Cascadelake-Server-v1')
+ self.assertNotIn('alias-of', cpus['Cascadelake-Server-v1'],
+ 'Cascadelake-Server-v1 must not be an alias')
+
+ self.assertFalse(cpus['qemu64']['static'],
+ 'unversioned qemu64 CPU model must not be static')
+ self.assertEquals(cpus['qemu64'].get('alias-of'), 'qemu64-v1',
+ 'qemu64 must be an alias of qemu64-v1')
+ self.assertNotIn('alias-of', cpus['qemu64-v1'],
+ 'qemu64-v1 must not be an alias')
+
+ self.validate_variant_aliases(cpus)
+
+ # On pc-*-4.1, -noTSX and -IBRS models should be aliases:
+ self.assertEquals(cpus["Haswell"].get('alias-of'),
+ "Haswell-v1",
+ "Haswell must be an alias")
+ self.assertEquals(cpus["Haswell-noTSX"].get('alias-of'),
+ "Haswell-v2",
+ "Haswell-noTSX must be an alias")
+ self.assertEquals(cpus["Haswell-IBRS"].get('alias-of'),
+ "Haswell-v3",
+ "Haswell-IBRS must be an alias")
+ self.assertEquals(cpus["Haswell-noTSX-IBRS"].get('alias-of'),
+ "Haswell-v4",
+ "Haswell-noTSX-IBRS must be an alias")
+
+ self.assertEquals(cpus["Broadwell"].get('alias-of'),
+ "Broadwell-v1",
+ "Broadwell must be an alias")
+ self.assertEquals(cpus["Broadwell-noTSX"].get('alias-of'),
+ "Broadwell-v2",
+ "Broadwell-noTSX must be an alias")
+ self.assertEquals(cpus["Broadwell-IBRS"].get('alias-of'),
+ "Broadwell-v3",
+ "Broadwell-IBRS must be an alias")
+ self.assertEquals(cpus["Broadwell-noTSX-IBRS"].get('alias-of'),
+ "Broadwell-v4",
+ "Broadwell-noTSX-IBRS must be an alias")
+
+ self.assertEquals(cpus["Nehalem"].get('alias-of'),
+ "Nehalem-v1",
+ "Nehalem must be an alias")
+ self.assertEquals(cpus["Nehalem-IBRS"].get('alias-of'),
+ "Nehalem-v2",
+ "Nehalem-IBRS must be an alias")
+
+ self.assertEquals(cpus["Westmere"].get('alias-of'),
+ "Westmere-v1",
+ "Westmere must be an alias")
+ self.assertEquals(cpus["Westmere-IBRS"].get('alias-of'),
+ "Westmere-v2",
+ "Westmere-IBRS must be an alias")
+
+ self.assertEquals(cpus["SandyBridge"].get('alias-of'),
+ "SandyBridge-v1",
+ "SandyBridge must be an alias")
+ self.assertEquals(cpus["SandyBridge-IBRS"].get('alias-of'),
+ "SandyBridge-v2",
+ "SandyBridge-IBRS must be an alias")
+
+ self.assertEquals(cpus["IvyBridge"].get('alias-of'),
+ "IvyBridge-v1",
+ "IvyBridge must be an alias")
+ self.assertEquals(cpus["IvyBridge-IBRS"].get('alias-of'),
+ "IvyBridge-v2",
+ "IvyBridge-IBRS must be an alias")
+
+ self.assertEquals(cpus["Skylake-Client"].get('alias-of'),
+ "Skylake-Client-v1",
+ "Skylake-Client must be an alias")
+ self.assertEquals(cpus["Skylake-Client-IBRS"].get('alias-of'),
+ "Skylake-Client-v2",
+ "Skylake-Client-IBRS must be an alias")
+
+ self.assertEquals(cpus["Skylake-Server"].get('alias-of'),
+ "Skylake-Server-v1",
+ "Skylake-Server must be an alias")
+ self.assertEquals(cpus["Skylake-Server-IBRS"].get('alias-of'),
+ "Skylake-Server-v2",
+ "Skylake-Server-IBRS must be an alias")
+
+ self.assertEquals(cpus["EPYC"].get('alias-of'),
+ "EPYC-v1",
+ "EPYC must be an alias")
+ self.assertEquals(cpus["EPYC-IBPB"].get('alias-of'),
+ "EPYC-v2",
+ "EPYC-IBPB must be an alias")
+
+ self.validate_aliases(cpus)
+
+ def test_none_alias(self):
+ """Check if unversioned CPU model is an alias pointing to some version"""
+ self.vm.add_args('-S')
+ self.vm.set_machine('none')
+ self.vm.launch()
+
+ cpus = dict((m['name'], m) for m in self.vm.command('query-cpu-definitions'))
+
+ self.assertFalse(cpus['Cascadelake-Server']['static'],
+ 'unversioned Cascadelake-Server CPU model must not be static')
+ self.assertTrue(re.match('Cascadelake-Server-v[0-9]+', cpus['Cascadelake-Server']['alias-of']),
+ 'Cascadelake-Server must be an alias of versioned CPU model')
+ self.assertNotIn('alias-of', cpus['Cascadelake-Server-v1'],
+ 'Cascadelake-Server-v1 must not be an alias')
+
+ self.assertFalse(cpus['qemu64']['static'],
+ 'unversioned qemu64 CPU model must not be static')
+ self.assertTrue(re.match('qemu64-v[0-9]+', cpus['qemu64']['alias-of']),
+ 'qemu64 must be an alias of versioned CPU model')
+ self.assertNotIn('alias-of', cpus['qemu64-v1'],
+ 'qemu64-v1 must not be an alias')
+
+ self.validate_aliases(cpus)
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Qemu-devel] [PATCH v2 8/9] docs: Deprecate CPU model runnability guarantees
2019-06-28 0:28 [Qemu-devel] [PATCH v2 0/9] x86 CPU model versioning Eduardo Habkost
` (6 preceding siblings ...)
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 7/9] i386: Make unversioned CPU models be aliases Eduardo Habkost
@ 2019-06-28 0:28 ` Eduardo Habkost
2019-07-02 9:46 ` Daniel P. Berrangé
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 9/9] i386: Add Cascadelake-Server-v2 CPU model Eduardo Habkost
2019-06-28 1:16 ` [Qemu-devel] [PATCH v2 0/9] x86 CPU model versioning no-reply
9 siblings, 1 reply; 25+ messages in thread
From: Eduardo Habkost @ 2019-06-28 0:28 UTC (permalink / raw)
To: qemu-devel
Cc: libvir-list, Igor Mammedov, Jiri Denemark, Daniel P. Berrange,
Dr. David Alan Gilbert
Document that CPU model runnability guarantees won't apply to
unversioned CPU models anymore.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
Changes v1 -> v2:
* (none)
Cc: libvir-list@redhat.com
---
qemu-deprecated.texi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/qemu-deprecated.texi b/qemu-deprecated.texi
index 9cba82d5ec..18f85f70e1 100644
--- a/qemu-deprecated.texi
+++ b/qemu-deprecated.texi
@@ -276,3 +276,22 @@ Note that if you are exposing the export via /dev/nbd0, it is easier
to just export the entire image and then mount only /dev/nbd0p1 than
it is to reinvoke @command{qemu-nbd -c /dev/nbd0} limited to just a
subset of the image.
+
+@section Backwards compatibility
+
+@subsection Runnability guarantee of CPU models (since 4.1.0)
+
+Previous versions of QEMU never changed existing CPU models in
+ways that introduced additional host software or hardware
+requirements to the VM. This allowed management software to
+safely change the machine type of an existing VM without
+introducing new requirements ("runnability guarantee"). This
+prevented CPU models from being updated to include CPU
+vulnerability mitigations, leaving guests vulnerable in the
+default configuration.
+
+The CPU model runnability guarantee won't apply anymore to
+existing CPU models. Management software that needs runnability
+guarantees must resolve the CPU model aliases using te
+``alias-of'' field returned by the ``query-cpu-definitions'' QMP
+command.
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Qemu-devel] [PATCH v2 9/9] i386: Add Cascadelake-Server-v2 CPU model
2019-06-28 0:28 [Qemu-devel] [PATCH v2 0/9] x86 CPU model versioning Eduardo Habkost
` (7 preceding siblings ...)
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 8/9] docs: Deprecate CPU model runnability guarantees Eduardo Habkost
@ 2019-06-28 0:28 ` Eduardo Habkost
2019-07-01 7:23 ` Xiaoyao Li
2019-07-02 9:47 ` Daniel P. Berrangé
2019-06-28 1:16 ` [Qemu-devel] [PATCH v2 0/9] x86 CPU model versioning no-reply
9 siblings, 2 replies; 25+ messages in thread
From: Eduardo Habkost @ 2019-06-28 0:28 UTC (permalink / raw)
To: qemu-devel
Cc: Daniel P. Berrange, jingqi.liu, Tao Xu, Dr. David Alan Gilbert,
Hu, Robert, Igor Mammedov, Jiri Denemark, Lai, Paul C
Add new version of Cascadelake-Server CPU model, setting
stepping=5 and enabling the IA32_ARCH_CAPABILITIES MSR
with some flags.
The new feature will introduce a new host software requirement,
breaking our CPU model runnability promises. This means we can't
enable the new CPU model version by default in QEMU 4.1, because
management software isn't ready yet to resolve CPU model aliases.
This is why "pc-*-4.1" will keep returning Cascadelake-Server-v1
if "-cpu Cascadelake-Server" is specified.
Includes a test case to ensure the right combinations of
machine-type + CPU model + command-line feature flags will work
as expected.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
Changes v1 -> v2:
* Enable rdctl-no, ibrs-all, skip-l1dfl-vmentry
(Suggested by Tao Xu)
Cc: "Hu, Robert" <robert.hu@intel.com>
Cc: Tao Xu <tao3.xu@intel.com>
Cc: jingqi.liu@intel.com,
Cc: "Lai, Paul C" <paul.c.lai@intel.com>
---
target/i386/cpu.c | 14 +++++
tests/acceptance/x86_cpu_model_versions.py | 73 ++++++++++++++++++++++
2 files changed, 87 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 10a09c971a..570890a7dd 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2343,6 +2343,20 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Xeon Processor (Cascadelake)",
+ .versions = (X86CPUVersionDefinition[]) {
+ { .version = 1 },
+ { .version = 2,
+ .props = (PropValue[]) {
+ { "stepping", "5" },
+ { "arch-capabilities", "on" },
+ { "rdctl-no", "on" },
+ { "ibrs-all", "on" },
+ { "skip-l1dfl-vmentry", "on" },
+ { /* end of list */ }
+ },
+ },
+ { /* end of list */ }
+ }
},
{
.name = "Icelake-Client",
diff --git a/tests/acceptance/x86_cpu_model_versions.py b/tests/acceptance/x86_cpu_model_versions.py
index 165c0c7601..1c9fd6a56e 100644
--- a/tests/acceptance/x86_cpu_model_versions.py
+++ b/tests/acceptance/x86_cpu_model_versions.py
@@ -25,6 +25,10 @@
import avocado_qemu
import re
+def get_cpu_prop(vm, prop):
+ cpu_path = vm.command('query-cpus')[0].get('qom_path')
+ return vm.command('qom-get', path=cpu_path, property=prop)
+
class X86CPUModelAliases(avocado_qemu.Test):
"""
Validation of PC CPU model versions and CPU model aliases
@@ -229,3 +233,72 @@ class X86CPUModelAliases(avocado_qemu.Test):
'qemu64-v1 must not be an alias')
self.validate_aliases(cpus)
+
+ def test_Cascadelake_arch_capabilities_result(self):
+ # machine-type only:
+ vm = self.get_vm()
+ vm.add_args('-S')
+ vm.set_machine('pc-i440fx-4.1')
+ vm.add_args('-cpu', 'Cascadelake-Server,x-force-features=on,check=off,enforce=off')
+ vm.launch()
+ self.assertFalse(get_cpu_prop(vm, 'arch-capabilities'),
+ 'pc-i440fx-4.1 + Cascadelake-Server should not have arch-capabilities')
+
+ vm = self.get_vm()
+ vm.add_args('-S')
+ vm.set_machine('pc-i440fx-4.0')
+ vm.add_args('-cpu', 'Cascadelake-Server,x-force-features=on,check=off,enforce=off')
+ vm.launch()
+ self.assertFalse(get_cpu_prop(vm, 'arch-capabilities'),
+ 'pc-i440fx-4.0 + Cascadelake-Server should not have arch-capabilities')
+
+ # command line must override machine-type if CPU model is not versioned:
+ vm = self.get_vm()
+ vm.add_args('-S')
+ vm.set_machine('pc-i440fx-4.0')
+ vm.add_args('-cpu', 'Cascadelake-Server,x-force-features=on,check=off,enforce=off,+arch-capabilities')
+ vm.launch()
+ self.assertTrue(get_cpu_prop(vm, 'arch-capabilities'),
+ 'pc-i440fx-4.0 + Cascadelake-Server,+arch-capabilities should have arch-capabilities')
+
+ vm = self.get_vm()
+ vm.add_args('-S')
+ vm.set_machine('pc-i440fx-4.1')
+ vm.add_args('-cpu', 'Cascadelake-Server,x-force-features=on,check=off,enforce=off,-arch-capabilities')
+ vm.launch()
+ self.assertFalse(get_cpu_prop(vm, 'arch-capabilities'),
+ 'pc-i440fx-4.1 + Cascadelake-Server,-arch-capabilities should not have arch-capabilities')
+
+ # versioned CPU model overrides machine-type:
+ vm = self.get_vm()
+ vm.add_args('-S')
+ vm.set_machine('pc-i440fx-4.0')
+ vm.add_args('-cpu', 'Cascadelake-Server-v1,x-force-features=on,check=off,enforce=off')
+ vm.launch()
+ self.assertFalse(get_cpu_prop(vm, 'arch-capabilities'),
+ 'pc-i440fx-4.1 + Cascadelake-Server-v1 should not have arch-capabilities')
+
+ vm = self.get_vm()
+ vm.add_args('-S')
+ vm.set_machine('pc-i440fx-4.0')
+ vm.add_args('-cpu', 'Cascadelake-Server-v2,x-force-features=on,check=off,enforce=off')
+ vm.launch()
+ self.assertTrue(get_cpu_prop(vm, 'arch-capabilities'),
+ 'pc-i440fx-4.1 + Cascadelake-Server-v1 should have arch-capabilities')
+
+ # command line must override machine-type and versioned CPU model:
+ vm = self.get_vm()
+ vm.add_args('-S')
+ vm.set_machine('pc-i440fx-4.0')
+ vm.add_args('-cpu', 'Cascadelake-Server,x-force-features=on,check=off,enforce=off,+arch-capabilities')
+ vm.launch()
+ self.assertTrue(get_cpu_prop(vm, 'arch-capabilities'),
+ 'pc-i440fx-4.0 + Cascadelake-Server-v1,+arch-capabilities should have arch-capabilities')
+
+ vm = self.get_vm()
+ vm.add_args('-S')
+ vm.set_machine('pc-i440fx-4.1')
+ vm.add_args('-cpu', 'Cascadelake-Server-v2,x-force-features=on,check=off,enforce=off,-arch-capabilities')
+ vm.launch()
+ self.assertFalse(get_cpu_prop(vm, 'arch-capabilities'),
+ 'pc-i440fx-4.1 + Cascadelake-Server-v2,-arch-capabilities should not have arch-capabilities')
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [Qemu-devel] [PATCH v2 0/9] x86 CPU model versioning
2019-06-28 0:28 [Qemu-devel] [PATCH v2 0/9] x86 CPU model versioning Eduardo Habkost
` (8 preceding siblings ...)
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 9/9] i386: Add Cascadelake-Server-v2 CPU model Eduardo Habkost
@ 2019-06-28 1:16 ` no-reply
9 siblings, 0 replies; 25+ messages in thread
From: no-reply @ 2019-06-28 1:16 UTC (permalink / raw)
To: ehabkost
Cc: phrdina, berrange, imammedo, tao3.xu, qemu-devel, dgilbert,
pbonzini, robert.hu, jdenemar, rth
Patchew URL: https://patchew.org/QEMU/20190628002844.24894-1-ehabkost@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190628002844.24894-1-ehabkost@redhat.com
Type: series
Subject: [Qemu-devel] [PATCH v2 0/9] x86 CPU model versioning
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Switched to a new branch 'test'
6b27417 i386: Add Cascadelake-Server-v2 CPU model
87c5623 docs: Deprecate CPU model runnability guarantees
c62ec5c i386: Make unversioned CPU models be aliases
c3d6af9 i386: Replace -noTSX, -IBRS, -IBPB CPU models with aliases
0f8c078 i386: Define -IBRS, -noTSX, -IBRS versions of CPU models
07fa113 i386: Register versioned CPU models
0ccbf3d i386: Get model-id from CPU object on "-cpu help"
4d81fc5 i386: Add x-force-features option for testing
2d612b1 qmp: Add "alias-of" field to query-cpu-definitions
=== OUTPUT BEGIN ===
1/9 Checking commit 2d612b193c4b (qmp: Add "alias-of" field to query-cpu-definitions)
2/9 Checking commit 4d81fc55d3dd (i386: Add x-force-features option for testing)
3/9 Checking commit 0ccbf3dcd0a0 (i386: Get model-id from CPU object on "-cpu help")
4/9 Checking commit 07fa113322f8 (i386: Register versioned CPU models)
WARNING: line over 80 characters
#97: FILE: target/i386/cpu.c:1481:
+static const X86CPUVersionDefinition *x86_cpu_def_get_versions(X86CPUDefinition *def)
WARNING: Block comments use a leading /* on a separate line
#102: FILE: target/i386/cpu.c:1486:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#119: FILE: target/i386/cpu.c:1882:
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
WARNING: Block comments use a leading /* on a separate line
#131: FILE: target/i386/cpu.c:1941:
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
WARNING: Block comments use a leading /* on a separate line
#143: FILE: target/i386/cpu.c:2010:
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
WARNING: Block comments use a leading /* on a separate line
#155: FILE: target/i386/cpu.c:2085:
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
WARNING: Block comments use a leading /* on a separate line
#167: FILE: target/i386/cpu.c:2126:
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
WARNING: Block comments use a leading /* on a separate line
#179: FILE: target/i386/cpu.c:2169:
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
WARNING: Block comments use a leading /* on a separate line
#191: FILE: target/i386/cpu.c:2250:
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
WARNING: Block comments use a leading /* on a separate line
#203: FILE: target/i386/cpu.c:2293:
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
WARNING: Block comments use a leading /* on a separate line
#215: FILE: target/i386/cpu.c:2338:
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
WARNING: Block comments use a leading /* on a separate line
#227: FILE: target/i386/cpu.c:2421:
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
WARNING: Block comments use a leading /* on a separate line
#239: FILE: target/i386/cpu.c:2518:
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
WARNING: Block comments use a leading /* on a separate line
#251: FILE: target/i386/cpu.c:2625:
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
WARNING: Block comments use a leading /* on a separate line
#263: FILE: target/i386/cpu.c:3067:
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
WARNING: line over 80 characters
#330: FILE: target/i386/cpu.c:4091:
+ for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) {
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#506:
new file mode 100644
ERROR: line over 90 characters
#549: FILE: tests/acceptance/x86_cpu_model_versions.py:39:
+ '%s.alias-of (%s) is not a valid CPU model name' % (c['name'], c['alias-of']))
ERROR: line over 90 characters
#552: FILE: tests/acceptance/x86_cpu_model_versions.py:42:
+ '%s.alias-of (%s) points to another alias' % (c['name'], c['alias-of']))
WARNING: line over 80 characters
#588: FILE: tests/acceptance/x86_cpu_model_versions.py:78:
+ """Check if pc-*-4.0 unversioned CPU model won't be reported as aliases"""
WARNING: line over 80 characters
#595: FILE: tests/acceptance/x86_cpu_model_versions.py:85:
+ cpus = dict((m['name'], m) for m in self.vm.command('query-cpu-definitions'))
WARNING: line over 80 characters
#598: FILE: tests/acceptance/x86_cpu_model_versions.py:88:
+ 'unversioned Cascadelake-Server CPU model must not be static')
total: 2 errors, 20 warnings, 550 lines checked
Patch 4/9 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
5/9 Checking commit 0f8c07835daf (i386: Define -IBRS, -noTSX, -IBRS versions of CPU models)
WARNING: Block comments use a leading /* on a separate line
#33: FILE: target/i386/cpu.c:1862:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#36: FILE: target/i386/cpu.c:1865:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#54: FILE: target/i386/cpu.c:1932:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#57: FILE: target/i386/cpu.c:1935:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#75: FILE: target/i386/cpu.c:2010:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#78: FILE: target/i386/cpu.c:2013:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#96: FILE: target/i386/cpu.c:2096:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#99: FILE: target/i386/cpu.c:2099:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#118: FILE: target/i386/cpu.c:2273:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#136: FILE: target/i386/cpu.c:2291:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#149: FILE: target/i386/cpu.c:2304:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#152: FILE: target/i386/cpu.c:2307:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#170: FILE: target/i386/cpu.c:2488:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#183: FILE: target/i386/cpu.c:2501:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#195: FILE: target/i386/cpu.c:2513:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#198: FILE: target/i386/cpu.c:2516:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#216: FILE: target/i386/cpu.c:2617:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#219: FILE: target/i386/cpu.c:2620:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#240: FILE: target/i386/cpu.c:2736:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#243: FILE: target/i386/cpu.c:2739:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#261: FILE: target/i386/cpu.c:3194:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#264: FILE: target/i386/cpu.c:3197:
+ { /* end of list */ }
total: 0 errors, 22 warnings, 240 lines checked
Patch 5/9 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/9 Checking commit c3d6af98d417 (i386: Replace -noTSX, -IBRS, -IBPB CPU models with aliases)
7/9 Checking commit c62ec5c338fc (i386: Make unversioned CPU models be aliases)
WARNING: line over 80 characters
#264: FILE: tests/acceptance/x86_cpu_model_versions.py:108:
+ """Check if unversioned CPU model is an alias pointing to right version"""
WARNING: line over 80 characters
#269: FILE: tests/acceptance/x86_cpu_model_versions.py:113:
+ cpus = dict((m['name'], m) for m in self.vm.command('query-cpu-definitions'))
WARNING: line over 80 characters
#272: FILE: tests/acceptance/x86_cpu_model_versions.py:116:
+ 'unversioned Cascadelake-Server CPU model must not be static')
ERROR: line over 90 characters
#273: FILE: tests/acceptance/x86_cpu_model_versions.py:117:
+ self.assertEquals(cpus['Cascadelake-Server'].get('alias-of'), 'Cascadelake-Server-v1',
WARNING: line over 80 characters
#274: FILE: tests/acceptance/x86_cpu_model_versions.py:118:
+ 'Cascadelake-Server must be an alias of Cascadelake-Server-v1')
WARNING: line over 80 characters
#366: FILE: tests/acceptance/x86_cpu_model_versions.py:210:
+ """Check if unversioned CPU model is an alias pointing to some version"""
WARNING: line over 80 characters
#371: FILE: tests/acceptance/x86_cpu_model_versions.py:215:
+ cpus = dict((m['name'], m) for m in self.vm.command('query-cpu-definitions'))
WARNING: line over 80 characters
#374: FILE: tests/acceptance/x86_cpu_model_versions.py:218:
+ 'unversioned Cascadelake-Server CPU model must not be static')
ERROR: line over 90 characters
#375: FILE: tests/acceptance/x86_cpu_model_versions.py:219:
+ self.assertTrue(re.match('Cascadelake-Server-v[0-9]+', cpus['Cascadelake-Server']['alias-of']),
WARNING: line over 80 characters
#376: FILE: tests/acceptance/x86_cpu_model_versions.py:220:
+ 'Cascadelake-Server must be an alias of versioned CPU model')
total: 2 errors, 8 warnings, 319 lines checked
Patch 7/9 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
8/9 Checking commit 87c5623c397d (docs: Deprecate CPU model runnability guarantees)
9/9 Checking commit 6b274179ee3f (i386: Add Cascadelake-Server-v2 CPU model)
WARNING: Block comments use a leading /* on a separate line
#42: FILE: target/i386/cpu.c:2354:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#45: FILE: target/i386/cpu.c:2357:
+ { /* end of list */ }
ERROR: line over 90 characters
#75: FILE: tests/acceptance/x86_cpu_model_versions.py:242:
+ vm.add_args('-cpu', 'Cascadelake-Server,x-force-features=on,check=off,enforce=off')
ERROR: line over 90 characters
#78: FILE: tests/acceptance/x86_cpu_model_versions.py:245:
+ 'pc-i440fx-4.1 + Cascadelake-Server should not have arch-capabilities')
ERROR: line over 90 characters
#83: FILE: tests/acceptance/x86_cpu_model_versions.py:250:
+ vm.add_args('-cpu', 'Cascadelake-Server,x-force-features=on,check=off,enforce=off')
ERROR: line over 90 characters
#86: FILE: tests/acceptance/x86_cpu_model_versions.py:253:
+ 'pc-i440fx-4.0 + Cascadelake-Server should not have arch-capabilities')
ERROR: line over 90 characters
#92: FILE: tests/acceptance/x86_cpu_model_versions.py:259:
+ vm.add_args('-cpu', 'Cascadelake-Server,x-force-features=on,check=off,enforce=off,+arch-capabilities')
ERROR: line over 90 characters
#95: FILE: tests/acceptance/x86_cpu_model_versions.py:262:
+ 'pc-i440fx-4.0 + Cascadelake-Server,+arch-capabilities should have arch-capabilities')
ERROR: line over 90 characters
#100: FILE: tests/acceptance/x86_cpu_model_versions.py:267:
+ vm.add_args('-cpu', 'Cascadelake-Server,x-force-features=on,check=off,enforce=off,-arch-capabilities')
ERROR: line over 90 characters
#103: FILE: tests/acceptance/x86_cpu_model_versions.py:270:
+ 'pc-i440fx-4.1 + Cascadelake-Server,-arch-capabilities should not have arch-capabilities')
ERROR: line over 90 characters
#109: FILE: tests/acceptance/x86_cpu_model_versions.py:276:
+ vm.add_args('-cpu', 'Cascadelake-Server-v1,x-force-features=on,check=off,enforce=off')
ERROR: line over 90 characters
#112: FILE: tests/acceptance/x86_cpu_model_versions.py:279:
+ 'pc-i440fx-4.1 + Cascadelake-Server-v1 should not have arch-capabilities')
ERROR: line over 90 characters
#117: FILE: tests/acceptance/x86_cpu_model_versions.py:284:
+ vm.add_args('-cpu', 'Cascadelake-Server-v2,x-force-features=on,check=off,enforce=off')
ERROR: line over 90 characters
#120: FILE: tests/acceptance/x86_cpu_model_versions.py:287:
+ 'pc-i440fx-4.1 + Cascadelake-Server-v1 should have arch-capabilities')
ERROR: line over 90 characters
#126: FILE: tests/acceptance/x86_cpu_model_versions.py:293:
+ vm.add_args('-cpu', 'Cascadelake-Server,x-force-features=on,check=off,enforce=off,+arch-capabilities')
ERROR: line over 90 characters
#129: FILE: tests/acceptance/x86_cpu_model_versions.py:296:
+ 'pc-i440fx-4.0 + Cascadelake-Server-v1,+arch-capabilities should have arch-capabilities')
ERROR: line over 90 characters
#134: FILE: tests/acceptance/x86_cpu_model_versions.py:301:
+ vm.add_args('-cpu', 'Cascadelake-Server-v2,x-force-features=on,check=off,enforce=off,-arch-capabilities')
ERROR: line over 90 characters
#137: FILE: tests/acceptance/x86_cpu_model_versions.py:304:
+ 'pc-i440fx-4.1 + Cascadelake-Server-v2,-arch-capabilities should not have arch-capabilities')
total: 16 errors, 2 warnings, 102 lines checked
Patch 9/9 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190628002844.24894-1-ehabkost@redhat.com/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Qemu-devel] [PATCH v2 9/9] i386: Add Cascadelake-Server-v2 CPU model
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 9/9] i386: Add Cascadelake-Server-v2 CPU model Eduardo Habkost
@ 2019-07-01 7:23 ` Xiaoyao Li
2019-07-01 20:38 ` Eduardo Habkost
2019-07-02 9:47 ` Daniel P. Berrangé
1 sibling, 1 reply; 25+ messages in thread
From: Xiaoyao Li @ 2019-07-01 7:23 UTC (permalink / raw)
To: Eduardo Habkost, qemu-devel
Cc: Daniel P. Berrange, jingqi.liu, Tao Xu, Dr. David Alan Gilbert,
Hu, Robert, Igor Mammedov, Jiri Denemark, Lai, Paul C
On 6/28/2019 8:28 AM, Eduardo Habkost wrote:
> Add new version of Cascadelake-Server CPU model, setting
> stepping=5 and enabling the IA32_ARCH_CAPABILITIES MSR
> with some flags.
>
> The new feature will introduce a new host software requirement,
> breaking our CPU model runnability promises. This means we can't
> enable the new CPU model version by default in QEMU 4.1, because
> management software isn't ready yet to resolve CPU model aliases.
> This is why "pc-*-4.1" will keep returning Cascadelake-Server-v1
> if "-cpu Cascadelake-Server" is specified.
>
> Includes a test case to ensure the right combinations of
> machine-type + CPU model + command-line feature flags will work
> as expected.
>
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> ---
> Changes v1 -> v2:
> * Enable rdctl-no, ibrs-all, skip-l1dfl-vmentry
> (Suggested by Tao Xu)
>
> Cc: "Hu, Robert" <robert.hu@intel.com>
> Cc: Tao Xu <tao3.xu@intel.com>
> Cc: jingqi.liu@intel.com,
> Cc: "Lai, Paul C" <paul.c.lai@intel.com>
> ---
> target/i386/cpu.c | 14 +++++
> tests/acceptance/x86_cpu_model_versions.py | 73 ++++++++++++++++++++++
> 2 files changed, 87 insertions(+)
>
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 10a09c971a..570890a7dd 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -2343,6 +2343,20 @@ static X86CPUDefinition builtin_x86_defs[] = {
> CPUID_6_EAX_ARAT,
> .xlevel = 0x80000008,
> .model_id = "Intel Xeon Processor (Cascadelake)",
> + .versions = (X86CPUVersionDefinition[]) {
> + { .version = 1 },
> + { .version = 2,
> + .props = (PropValue[]) {
> + { "stepping", "5" },
Stepping should be 6?
> + { "arch-capabilities", "on" },
> + { "rdctl-no", "on" },
> + { "ibrs-all", "on" },
> + { "skip-l1dfl-vmentry", "on" },
rdmsr 0x10AH returns 0x2b from host Cascadelake, we'd better add feature
"mds-no" too. Otherwise we will need another version for that feature.
> + { /* end of list */ }
> + },
> + },
> + { /* end of list */ }
> + }
> },
> {
> .name = "Icelake-Client",
> diff --git a/tests/acceptance/x86_cpu_model_versions.py b/tests/acceptance/x86_cpu_model_versions.py
> index 165c0c7601..1c9fd6a56e 100644
> --- a/tests/acceptance/x86_cpu_model_versions.py
> +++ b/tests/acceptance/x86_cpu_model_versions.py
> @@ -25,6 +25,10 @@
> import avocado_qemu
> import re
>
> +def get_cpu_prop(vm, prop):
> + cpu_path = vm.command('query-cpus')[0].get('qom_path')
> + return vm.command('qom-get', path=cpu_path, property=prop)
> +
> class X86CPUModelAliases(avocado_qemu.Test):
> """
> Validation of PC CPU model versions and CPU model aliases
> @@ -229,3 +233,72 @@ class X86CPUModelAliases(avocado_qemu.Test):
> 'qemu64-v1 must not be an alias')
>
> self.validate_aliases(cpus)
> +
> + def test_Cascadelake_arch_capabilities_result(self):
> + # machine-type only:
> + vm = self.get_vm()
> + vm.add_args('-S')
> + vm.set_machine('pc-i440fx-4.1')
> + vm.add_args('-cpu', 'Cascadelake-Server,x-force-features=on,check=off,enforce=off')
> + vm.launch()
> + self.assertFalse(get_cpu_prop(vm, 'arch-capabilities'),
> + 'pc-i440fx-4.1 + Cascadelake-Server should not have arch-capabilities')
> +
> + vm = self.get_vm()
> + vm.add_args('-S')
> + vm.set_machine('pc-i440fx-4.0')
> + vm.add_args('-cpu', 'Cascadelake-Server,x-force-features=on,check=off,enforce=off')
> + vm.launch()
> + self.assertFalse(get_cpu_prop(vm, 'arch-capabilities'),
> + 'pc-i440fx-4.0 + Cascadelake-Server should not have arch-capabilities')
> +
> + # command line must override machine-type if CPU model is not versioned:
> + vm = self.get_vm()
> + vm.add_args('-S')
> + vm.set_machine('pc-i440fx-4.0')
> + vm.add_args('-cpu', 'Cascadelake-Server,x-force-features=on,check=off,enforce=off,+arch-capabilities')
> + vm.launch()
> + self.assertTrue(get_cpu_prop(vm, 'arch-capabilities'),
> + 'pc-i440fx-4.0 + Cascadelake-Server,+arch-capabilities should have arch-capabilities')
> +
> + vm = self.get_vm()
> + vm.add_args('-S')
> + vm.set_machine('pc-i440fx-4.1')
> + vm.add_args('-cpu', 'Cascadelake-Server,x-force-features=on,check=off,enforce=off,-arch-capabilities')
> + vm.launch()
> + self.assertFalse(get_cpu_prop(vm, 'arch-capabilities'),
> + 'pc-i440fx-4.1 + Cascadelake-Server,-arch-capabilities should not have arch-capabilities')
> +
> + # versioned CPU model overrides machine-type:
> + vm = self.get_vm()
> + vm.add_args('-S')
> + vm.set_machine('pc-i440fx-4.0')
> + vm.add_args('-cpu', 'Cascadelake-Server-v1,x-force-features=on,check=off,enforce=off')
> + vm.launch()
> + self.assertFalse(get_cpu_prop(vm, 'arch-capabilities'),
> + 'pc-i440fx-4.1 + Cascadelake-Server-v1 should not have arch-capabilities')
> +
> + vm = self.get_vm()
> + vm.add_args('-S')
> + vm.set_machine('pc-i440fx-4.0')
> + vm.add_args('-cpu', 'Cascadelake-Server-v2,x-force-features=on,check=off,enforce=off')
> + vm.launch()
> + self.assertTrue(get_cpu_prop(vm, 'arch-capabilities'),
> + 'pc-i440fx-4.1 + Cascadelake-Server-v1 should have arch-capabilities')
> +
> + # command line must override machine-type and versioned CPU model:
> + vm = self.get_vm()
> + vm.add_args('-S')
> + vm.set_machine('pc-i440fx-4.0')
> + vm.add_args('-cpu', 'Cascadelake-Server,x-force-features=on,check=off,enforce=off,+arch-capabilities')
> + vm.launch()
> + self.assertTrue(get_cpu_prop(vm, 'arch-capabilities'),
> + 'pc-i440fx-4.0 + Cascadelake-Server-v1,+arch-capabilities should have arch-capabilities')
> +
> + vm = self.get_vm()
> + vm.add_args('-S')
> + vm.set_machine('pc-i440fx-4.1')
> + vm.add_args('-cpu', 'Cascadelake-Server-v2,x-force-features=on,check=off,enforce=off,-arch-capabilities')
> + vm.launch()
> + self.assertFalse(get_cpu_prop(vm, 'arch-capabilities'),
> + 'pc-i440fx-4.1 + Cascadelake-Server-v2,-arch-capabilities should not have arch-capabilities')
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Qemu-devel] [PATCH v2 9/9] i386: Add Cascadelake-Server-v2 CPU model
2019-07-01 7:23 ` Xiaoyao Li
@ 2019-07-01 20:38 ` Eduardo Habkost
0 siblings, 0 replies; 25+ messages in thread
From: Eduardo Habkost @ 2019-07-01 20:38 UTC (permalink / raw)
To: Xiaoyao Li
Cc: Daniel P. Berrange, jingqi.liu, Tao Xu, qemu-devel,
Dr. David Alan Gilbert, Igor Mammedov, Hu, Robert, Jiri Denemark,
Lai, Paul C
On Mon, Jul 01, 2019 at 03:23:31PM +0800, Xiaoyao Li wrote:
> On 6/28/2019 8:28 AM, Eduardo Habkost wrote:
> > Add new version of Cascadelake-Server CPU model, setting
> > stepping=5 and enabling the IA32_ARCH_CAPABILITIES MSR
> > with some flags.
> >
> > The new feature will introduce a new host software requirement,
> > breaking our CPU model runnability promises. This means we can't
> > enable the new CPU model version by default in QEMU 4.1, because
> > management software isn't ready yet to resolve CPU model aliases.
> > This is why "pc-*-4.1" will keep returning Cascadelake-Server-v1
> > if "-cpu Cascadelake-Server" is specified.
> >
> > Includes a test case to ensure the right combinations of
> > machine-type + CPU model + command-line feature flags will work
> > as expected.
> >
> > Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> > ---
> > Changes v1 -> v2:
> > * Enable rdctl-no, ibrs-all, skip-l1dfl-vmentry
> > (Suggested by Tao Xu)
> >
> > Cc: "Hu, Robert" <robert.hu@intel.com>
> > Cc: Tao Xu <tao3.xu@intel.com>
> > Cc: jingqi.liu@intel.com,
> > Cc: "Lai, Paul C" <paul.c.lai@intel.com>
> > ---
> > target/i386/cpu.c | 14 +++++
> > tests/acceptance/x86_cpu_model_versions.py | 73 ++++++++++++++++++++++
> > 2 files changed, 87 insertions(+)
> >
> > diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> > index 10a09c971a..570890a7dd 100644
> > --- a/target/i386/cpu.c
> > +++ b/target/i386/cpu.c
> > @@ -2343,6 +2343,20 @@ static X86CPUDefinition builtin_x86_defs[] = {
> > CPUID_6_EAX_ARAT,
> > .xlevel = 0x80000008,
> > .model_id = "Intel Xeon Processor (Cascadelake)",
> > + .versions = (X86CPUVersionDefinition[]) {
> > + { .version = 1 },
> > + { .version = 2,
> > + .props = (PropValue[]) {
> > + { "stepping", "5" },
>
> Stepping should be 6?
Yes, my mistake.
>
> > + { "arch-capabilities", "on" },
> > + { "rdctl-no", "on" },
> > + { "ibrs-all", "on" },
> > + { "skip-l1dfl-vmentry", "on" },
>
> rdmsr 0x10AH returns 0x2b from host Cascadelake, we'd better add feature
> "mds-no" too. Otherwise we will need another version for that feature.
Thanks for the info, I will update it in the next version.
> [...]
--
Eduardo
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Qemu-devel] [PATCH v2 1/9] qmp: Add "alias-of" field to query-cpu-definitions
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 1/9] qmp: Add "alias-of" field to query-cpu-definitions Eduardo Habkost
@ 2019-07-02 9:26 ` Daniel P. Berrangé
0 siblings, 0 replies; 25+ messages in thread
From: Daniel P. Berrangé @ 2019-07-02 9:26 UTC (permalink / raw)
To: Eduardo Habkost
Cc: Jiri Denemark, Markus Armbruster, Igor Mammedov, qemu-devel,
Dr. David Alan Gilbert
On Thu, Jun 27, 2019 at 09:28:36PM -0300, Eduardo Habkost wrote:
> Management software will be expected to resolve CPU model name
> aliases using the new field.
>
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> ---
> Changes v1 -> v2:
> * (none)
>
> Cc: Eric Blake <eblake@redhat.com>
> Cc: Markus Armbruster <armbru@redhat.com>
> ---
> qapi/target.json | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Regards,
Daniel
--
|: https://berrange.com -o- https://www.flickr.com/photos/dberrange :|
|: https://libvirt.org -o- https://fstop138.berrange.com :|
|: https://entangle-photo.org -o- https://www.instagram.com/dberrange :|
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Qemu-devel] [PATCH v2 2/9] i386: Add x-force-features option for testing
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 2/9] i386: Add x-force-features option for testing Eduardo Habkost
@ 2019-07-02 9:30 ` Daniel P. Berrangé
0 siblings, 0 replies; 25+ messages in thread
From: Daniel P. Berrangé @ 2019-07-02 9:30 UTC (permalink / raw)
To: Eduardo Habkost
Cc: Igor Mammedov, Jiri Denemark, qemu-devel, Dr. David Alan Gilbert
On Thu, Jun 27, 2019 at 09:28:37PM -0300, Eduardo Habkost wrote:
> Add a new option that can be used to disable feature flag
> filtering. This will allow CPU model compatibility test cases to
> work without host hardware dependencies.
>
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> ---
> Changes v1 -> v2:
> * (none)
> ---
> target/i386/cpu.h | 6 ++++++
> target/i386/cpu.c | 8 ++++++--
> 2 files changed, 12 insertions(+), 2 deletions(-)
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Regards,
Daniel
--
|: https://berrange.com -o- https://www.flickr.com/photos/dberrange :|
|: https://libvirt.org -o- https://fstop138.berrange.com :|
|: https://entangle-photo.org -o- https://www.instagram.com/dberrange :|
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Qemu-devel] [PATCH v2 3/9] i386: Get model-id from CPU object on "-cpu help"
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 3/9] i386: Get model-id from CPU object on "-cpu help" Eduardo Habkost
@ 2019-07-02 9:32 ` Daniel P. Berrangé
0 siblings, 0 replies; 25+ messages in thread
From: Daniel P. Berrangé @ 2019-07-02 9:32 UTC (permalink / raw)
To: Eduardo Habkost
Cc: Igor Mammedov, Jiri Denemark, qemu-devel, Dr. David Alan Gilbert
On Thu, Jun 27, 2019 at 09:28:38PM -0300, Eduardo Habkost wrote:
> When introducing versioned CPU models, the string at
> X86CPUDefinition::model_id might not be the model-id we'll really
> use. Instantiate a CPU object and check the model-id property on
> "-cpu help"
It would help understanding to illustrate this with an example
of the different string that results before/after this change.
>
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> ---
> (New patch, added to series in v2)
> ---
> target/i386/cpu.c | 16 +++++++++++++---
> 1 file changed, 13 insertions(+), 3 deletions(-)
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Regards,
Daniel
--
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Qemu-devel] [PATCH v2 4/9] i386: Register versioned CPU models
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 4/9] i386: Register versioned CPU models Eduardo Habkost
@ 2019-07-02 9:38 ` Daniel P. Berrangé
0 siblings, 0 replies; 25+ messages in thread
From: Daniel P. Berrangé @ 2019-07-02 9:38 UTC (permalink / raw)
To: Eduardo Habkost
Cc: Igor Mammedov, Jiri Denemark, qemu-devel, Dr. David Alan Gilbert
On Thu, Jun 27, 2019 at 09:28:39PM -0300, Eduardo Habkost wrote:
> Add support for registration of multiple versions of CPU models.
>
> The existing CPU models will be registered with a "-v1" suffix.
>
> The -noTSX, -IBRS, and -IBPB CPU model variants will become
> versions of the original models in a separate patch, so
> make sure we register no versions for them.
>
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> ---
> Patch v1 was "[PATCH 4/6] i386: Infrastructure for versioned CPU
> models", and was split into multiple patches.
>
> Changes v1 -> v2:
> * Make version numbers simple integers, completely independent
> from machine type versions
> * Don't register versions for -noTSX, -IBRS, and -IBPB CPU models
> * Code for reporting alias-of on query-cpu-definitions is now in
> a separate patch
> * Code for machine-type compatibility is now in a separate patch
> * New X86CPUVersion typedef
> * New CPU_VERSION_* defines to make X86CPUModel::version
> semantics clearer
> ---
> target/i386/cpu-qom.h | 10 +-
> target/i386/cpu.h | 10 +
> target/i386/cpu.c | 223 +++++++++++++++++++--
> tests/acceptance/x86_cpu_model_versions.py | 105 ++++++++++
> 4 files changed, 318 insertions(+), 30 deletions(-)
> create mode 100644 tests/acceptance/x86_cpu_model_versions.py
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Regards,
Daniel
--
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Qemu-devel] [PATCH v2 5/9] i386: Define -IBRS, -noTSX, -IBRS versions of CPU models
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 5/9] i386: Define -IBRS, -noTSX, -IBRS versions of " Eduardo Habkost
@ 2019-07-02 9:40 ` Daniel P. Berrangé
2019-07-02 9:50 ` Daniel P. Berrangé
0 siblings, 1 reply; 25+ messages in thread
From: Daniel P. Berrangé @ 2019-07-02 9:40 UTC (permalink / raw)
To: Eduardo Habkost
Cc: Igor Mammedov, Jiri Denemark, qemu-devel, Dr. David Alan Gilbert
On Thu, Jun 27, 2019 at 09:28:40PM -0300, Eduardo Habkost wrote:
> Add versions of CPU models that are equivalent to their -IBRS,
> -noTSX and -IBRS variants.
>
> The separate variants will eventually be removed and become
> aliases for these CPU versions.
>
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> ---
> (New patch, added to series in v2)
> ---
> target/i386/cpu.c | 186 ++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 186 insertions(+)
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Regards,
Daniel
--
|: https://berrange.com -o- https://www.flickr.com/photos/dberrange :|
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Qemu-devel] [PATCH v2 6/9] i386: Replace -noTSX, -IBRS, -IBPB CPU models with aliases
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 6/9] i386: Replace -noTSX, -IBRS, -IBPB CPU models with aliases Eduardo Habkost
@ 2019-07-02 9:41 ` Daniel P. Berrangé
0 siblings, 0 replies; 25+ messages in thread
From: Daniel P. Berrangé @ 2019-07-02 9:41 UTC (permalink / raw)
To: Eduardo Habkost
Cc: Igor Mammedov, Jiri Denemark, qemu-devel, Dr. David Alan Gilbert
On Thu, Jun 27, 2019 at 09:28:41PM -0300, Eduardo Habkost wrote:
> The old CPU models will be just aliases for specific versions of
> the original CPU models.
>
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> ---
> (New patch, added to series in v2)
> ---
> target/i386/cpu.c | 601 ++--------------------------------------------
> 1 file changed, 21 insertions(+), 580 deletions(-)
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Regards,
Daniel
--
|: https://berrange.com -o- https://www.flickr.com/photos/dberrange :|
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Qemu-devel] [PATCH v2 7/9] i386: Make unversioned CPU models be aliases
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 7/9] i386: Make unversioned CPU models be aliases Eduardo Habkost
@ 2019-07-02 9:45 ` Daniel P. Berrangé
2019-07-02 13:57 ` Daniel P. Berrangé
0 siblings, 1 reply; 25+ messages in thread
From: Daniel P. Berrangé @ 2019-07-02 9:45 UTC (permalink / raw)
To: Eduardo Habkost
Cc: Igor Mammedov, Jiri Denemark, qemu-devel, Dr. David Alan Gilbert
On Thu, Jun 27, 2019 at 09:28:42PM -0300, Eduardo Habkost wrote:
> This will make unversioned CPU models behavior depend on the
> machine type:
>
> * "pc-*-4.0" and older will not report them as aliases.
> This is done to keep compatibility with older QEMU versions
> after management software starts translating aliases.
>
> * "pc-*-4.1" will translate unversioned CPU models to -v1.
> This is done to keep compatibility with existing management
> software, that still relies on CPU model runnability promises.
>
> * "none" will translate unversioned CPU models to their latest
> version. This is planned become the default in future machine
> types (probably in pc-*-4.3).
>
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> ---
> Patch v1 was "[PATCH 4/6] i386: Infrastructure for versioned CPU
> models", and was split into multiple patches.
>
> Changes v1 -> v2:
> * Make version numbers simple integers, completely independent
> from machine type versions
> * New X86CPUVersion typedef
> * New CPU_VERSION_* defines to make X86CPUModel::version
> semantics clearer
> ---
> include/hw/i386/pc.h | 3 +
> target/i386/cpu.h | 12 ++
> hw/i386/pc.c | 3 +
> hw/i386/pc_piix.c | 4 +
> hw/i386/pc_q35.c | 4 +
> target/i386/cpu.c | 52 ++++++++-
> tests/acceptance/x86_cpu_model_versions.py | 126 +++++++++++++++++++++
> 7 files changed, 203 insertions(+), 1 deletion(-)
>
> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> index ee79d71ccc..1946c1023f 100644
> --- a/include/hw/i386/pc.h
> +++ b/include/hw/i386/pc.h
> @@ -109,6 +109,9 @@ typedef struct PCMachineClass {
>
> /* Compat options: */
>
> + /* Default CPU model version. See x86_cpu_set_default_version(). */
> + int default_cpu_version;
> +
> /* ACPI compat: */
> bool has_acpi_build;
> bool rsdp_in_ram;
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index 12bc3cd4a8..05393cf9d1 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -1934,11 +1934,23 @@ void x86_cpu_change_kvm_default(const char *prop, const char *value);
> /* Resolve to latest CPU version */
> #define CPU_VERSION_LATEST -1
>
> +/*
> + * Resolve to version defined by current machine type.
> + * See x86_cpu_set_default_version()
> + */
> +#define CPU_VERSION_AUTO -2
> +
> /* Don't resolve to any versioned CPU models, like old QEMU versions */
> #define CPU_VERSION_LEGACY 0
>
> typedef int X86CPUVersion;
>
> +/*
> + * Set default CPU model version for CPU models having
> + * version == CPU_VERSION_AUTO.
> + */
> +void x86_cpu_set_default_version(X86CPUVersion version);
> +
> /* Return name of 32-bit register, from a R_* constant */
> const char *get_register_name_32(unsigned int reg);
>
> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> index 3f0f221a5b..1df569620a 100644
> --- a/hw/i386/pc.c
> +++ b/hw/i386/pc.c
> @@ -1649,6 +1649,9 @@ void pc_cpus_init(PCMachineState *pcms)
> const CPUArchIdList *possible_cpus;
> MachineState *ms = MACHINE(pcms);
> MachineClass *mc = MACHINE_GET_CLASS(pcms);
> + PCMachineClass *pcmc = PC_MACHINE_CLASS(mc);
> +
> + x86_cpu_set_default_version(pcmc->default_cpu_version);
>
> /* Calculates the limit to CPU APIC ID values
> *
> diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
> index c07c4a5b38..0a069bff54 100644
> --- a/hw/i386/pc_piix.c
> +++ b/hw/i386/pc_piix.c
> @@ -430,9 +430,11 @@ static void pc_i440fx_machine_options(MachineClass *m)
>
> static void pc_i440fx_4_1_machine_options(MachineClass *m)
> {
> + PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
> pc_i440fx_machine_options(m);
> m->alias = "pc";
> m->is_default = 1;
> + pcmc->default_cpu_version = 1;
> }
>
> DEFINE_I440FX_MACHINE(v4_1, "pc-i440fx-4.1", NULL,
> @@ -440,9 +442,11 @@ DEFINE_I440FX_MACHINE(v4_1, "pc-i440fx-4.1", NULL,
>
> static void pc_i440fx_4_0_machine_options(MachineClass *m)
> {
> + PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
> pc_i440fx_4_1_machine_options(m);
> m->alias = NULL;
> m->is_default = 0;
> + pcmc->default_cpu_version = CPU_VERSION_LEGACY;
> compat_props_add(m->compat_props, hw_compat_4_0, hw_compat_4_0_len);
> compat_props_add(m->compat_props, pc_compat_4_0, pc_compat_4_0_len);
> }
> diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
> index 57232aed6b..397e1fdd2f 100644
> --- a/hw/i386/pc_q35.c
> +++ b/hw/i386/pc_q35.c
> @@ -367,8 +367,10 @@ static void pc_q35_machine_options(MachineClass *m)
>
> static void pc_q35_4_1_machine_options(MachineClass *m)
> {
> + PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
> pc_q35_machine_options(m);
> m->alias = "q35";
> + pcmc->default_cpu_version = 1;
How will this work in future if we need to introduce a v2 of some,
but not all CPU models, and then further a v3 of some others.
Can we select Haswell-v1, Skylake-Server-v2, CascadeLake-v3
as defaults in some way ?
Regards,
Daniel
--
|: https://berrange.com -o- https://www.flickr.com/photos/dberrange :|
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Qemu-devel] [PATCH v2 8/9] docs: Deprecate CPU model runnability guarantees
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 8/9] docs: Deprecate CPU model runnability guarantees Eduardo Habkost
@ 2019-07-02 9:46 ` Daniel P. Berrangé
0 siblings, 0 replies; 25+ messages in thread
From: Daniel P. Berrangé @ 2019-07-02 9:46 UTC (permalink / raw)
To: Eduardo Habkost
Cc: libvir-list, Igor Mammedov, Jiri Denemark, qemu-devel,
Dr. David Alan Gilbert
On Thu, Jun 27, 2019 at 09:28:43PM -0300, Eduardo Habkost wrote:
> Document that CPU model runnability guarantees won't apply to
> unversioned CPU models anymore.
>
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> ---
> Changes v1 -> v2:
> * (none)
>
> Cc: libvir-list@redhat.com
> ---
> qemu-deprecated.texi | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Regards,
Daniel
--
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Qemu-devel] [PATCH v2 9/9] i386: Add Cascadelake-Server-v2 CPU model
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 9/9] i386: Add Cascadelake-Server-v2 CPU model Eduardo Habkost
2019-07-01 7:23 ` Xiaoyao Li
@ 2019-07-02 9:47 ` Daniel P. Berrangé
2019-07-02 13:55 ` Eduardo Habkost
1 sibling, 1 reply; 25+ messages in thread
From: Daniel P. Berrangé @ 2019-07-02 9:47 UTC (permalink / raw)
To: Eduardo Habkost
Cc: jingqi.liu, Tao Xu, qemu-devel, Dr. David Alan Gilbert, Hu,
Robert, Igor Mammedov, Jiri Denemark, Lai, Paul C
On Thu, Jun 27, 2019 at 09:28:44PM -0300, Eduardo Habkost wrote:
> Add new version of Cascadelake-Server CPU model, setting
> stepping=5 and enabling the IA32_ARCH_CAPABILITIES MSR
> with some flags.
>
> The new feature will introduce a new host software requirement,
> breaking our CPU model runnability promises. This means we can't
> enable the new CPU model version by default in QEMU 4.1, because
> management software isn't ready yet to resolve CPU model aliases.
> This is why "pc-*-4.1" will keep returning Cascadelake-Server-v1
> if "-cpu Cascadelake-Server" is specified.
Hmm, yes, we don't actually need to answer the question I
raised in the earlier patch for another 2 releases yet,
as we'll be sticking with v1 for all machines for a while.
>
> Includes a test case to ensure the right combinations of
> machine-type + CPU model + command-line feature flags will work
> as expected.
>
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> ---
> Changes v1 -> v2:
> * Enable rdctl-no, ibrs-all, skip-l1dfl-vmentry
> (Suggested by Tao Xu)
>
> Cc: "Hu, Robert" <robert.hu@intel.com>
> Cc: Tao Xu <tao3.xu@intel.com>
> Cc: jingqi.liu@intel.com,
> Cc: "Lai, Paul C" <paul.c.lai@intel.com>
> ---
> target/i386/cpu.c | 14 +++++
> tests/acceptance/x86_cpu_model_versions.py | 73 ++++++++++++++++++++++
> 2 files changed, 87 insertions(+)
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Regards,
Daniel
--
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Qemu-devel] [PATCH v2 5/9] i386: Define -IBRS, -noTSX, -IBRS versions of CPU models
2019-07-02 9:40 ` Daniel P. Berrangé
@ 2019-07-02 9:50 ` Daniel P. Berrangé
0 siblings, 0 replies; 25+ messages in thread
From: Daniel P. Berrangé @ 2019-07-02 9:50 UTC (permalink / raw)
To: Eduardo Habkost
Cc: Igor Mammedov, Jiri Denemark, qemu-devel, Dr. David Alan Gilbert
On Tue, Jul 02, 2019 at 10:40:00AM +0100, Daniel P. Berrangé wrote:
> On Thu, Jun 27, 2019 at 09:28:40PM -0300, Eduardo Habkost wrote:
> > Add versions of CPU models that are equivalent to their -IBRS,
> > -noTSX and -IBRS variants.
> >
> > The separate variants will eventually be removed and become
> > aliases for these CPU versions.
> >
> > Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> > ---
> > (New patch, added to series in v2)
> > ---
> > target/i386/cpu.c | 186 ++++++++++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 186 insertions(+)
>
> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
We could in fact add a further version of all the CPU models
which adds the "ssbd" / "virt-ssbd" and "mds" features, so
that there's a version apps can pick that covers all the
currently known hardware flaws.
Anyway, it can be done as a patch at the end of this series
or separately as desired.
Regards,
Daniel
--
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Qemu-devel] [PATCH v2 9/9] i386: Add Cascadelake-Server-v2 CPU model
2019-07-02 9:47 ` Daniel P. Berrangé
@ 2019-07-02 13:55 ` Eduardo Habkost
0 siblings, 0 replies; 25+ messages in thread
From: Eduardo Habkost @ 2019-07-02 13:55 UTC (permalink / raw)
To: Daniel P. Berrangé
Cc: jingqi.liu, Tao Xu, qemu-devel, Dr. David Alan Gilbert, Hu,
Robert, Igor Mammedov, Jiri Denemark, Lai, Paul C
On Tue, Jul 02, 2019 at 10:47:17AM +0100, Daniel P. Berrangé wrote:
> On Thu, Jun 27, 2019 at 09:28:44PM -0300, Eduardo Habkost wrote:
> > Add new version of Cascadelake-Server CPU model, setting
> > stepping=5 and enabling the IA32_ARCH_CAPABILITIES MSR
> > with some flags.
> >
> > The new feature will introduce a new host software requirement,
> > breaking our CPU model runnability promises. This means we can't
> > enable the new CPU model version by default in QEMU 4.1, because
> > management software isn't ready yet to resolve CPU model aliases.
> > This is why "pc-*-4.1" will keep returning Cascadelake-Server-v1
> > if "-cpu Cascadelake-Server" is specified.
>
> Hmm, yes, we don't actually need to answer the question I
> raised in the earlier patch for another 2 releases yet,
> as we'll be sticking with v1 for all machines for a while.
After these 2 releases have passed, we'll set default version to
CPU_VERSION_LATEST. I don't see the need to set per-model
defaults.
--
Eduardo
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Qemu-devel] [PATCH v2 7/9] i386: Make unversioned CPU models be aliases
2019-07-02 9:45 ` Daniel P. Berrangé
@ 2019-07-02 13:57 ` Daniel P. Berrangé
0 siblings, 0 replies; 25+ messages in thread
From: Daniel P. Berrangé @ 2019-07-02 13:57 UTC (permalink / raw)
To: Eduardo Habkost
Cc: Igor Mammedov, Jiri Denemark, qemu-devel, Dr. David Alan Gilbert
On Tue, Jul 02, 2019 at 10:45:25AM +0100, Daniel P. Berrangé wrote:
> On Thu, Jun 27, 2019 at 09:28:42PM -0300, Eduardo Habkost wrote:
> > This will make unversioned CPU models behavior depend on the
> > machine type:
> >
> > * "pc-*-4.0" and older will not report them as aliases.
> > This is done to keep compatibility with older QEMU versions
> > after management software starts translating aliases.
> >
> > * "pc-*-4.1" will translate unversioned CPU models to -v1.
> > This is done to keep compatibility with existing management
> > software, that still relies on CPU model runnability promises.
> >
> > * "none" will translate unversioned CPU models to their latest
> > version. This is planned become the default in future machine
> > types (probably in pc-*-4.3).
> >
> > Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> > ---
> > Patch v1 was "[PATCH 4/6] i386: Infrastructure for versioned CPU
> > models", and was split into multiple patches.
> >
> > Changes v1 -> v2:
> > * Make version numbers simple integers, completely independent
> > from machine type versions
> > * New X86CPUVersion typedef
> > * New CPU_VERSION_* defines to make X86CPUModel::version
> > semantics clearer
> > ---
> > include/hw/i386/pc.h | 3 +
> > target/i386/cpu.h | 12 ++
> > hw/i386/pc.c | 3 +
> > hw/i386/pc_piix.c | 4 +
> > hw/i386/pc_q35.c | 4 +
> > target/i386/cpu.c | 52 ++++++++-
> > tests/acceptance/x86_cpu_model_versions.py | 126 +++++++++++++++++++++
> > 7 files changed, 203 insertions(+), 1 deletion(-)
> > diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
> > index 57232aed6b..397e1fdd2f 100644
> > --- a/hw/i386/pc_q35.c
> > +++ b/hw/i386/pc_q35.c
> > @@ -367,8 +367,10 @@ static void pc_q35_machine_options(MachineClass *m)
> >
> > static void pc_q35_4_1_machine_options(MachineClass *m)
> > {
> > + PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
> > pc_q35_machine_options(m);
> > m->alias = "q35";
> > + pcmc->default_cpu_version = 1;
>
> How will this work in future if we need to introduce a v2 of some,
> but not all CPU models, and then further a v3 of some others.
>
> Can we select Haswell-v1, Skylake-Server-v2, CascadeLake-v3
> as defaults in some way ?
Answered in reply to a later patch so
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Regards,
Daniel
--
|: https://berrange.com -o- https://www.flickr.com/photos/dberrange :|
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^ permalink raw reply [flat|nested] 25+ messages in thread
end of thread, other threads:[~2019-07-02 13:59 UTC | newest]
Thread overview: 25+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-06-28 0:28 [Qemu-devel] [PATCH v2 0/9] x86 CPU model versioning Eduardo Habkost
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 1/9] qmp: Add "alias-of" field to query-cpu-definitions Eduardo Habkost
2019-07-02 9:26 ` Daniel P. Berrangé
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 2/9] i386: Add x-force-features option for testing Eduardo Habkost
2019-07-02 9:30 ` Daniel P. Berrangé
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 3/9] i386: Get model-id from CPU object on "-cpu help" Eduardo Habkost
2019-07-02 9:32 ` Daniel P. Berrangé
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 4/9] i386: Register versioned CPU models Eduardo Habkost
2019-07-02 9:38 ` Daniel P. Berrangé
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 5/9] i386: Define -IBRS, -noTSX, -IBRS versions of " Eduardo Habkost
2019-07-02 9:40 ` Daniel P. Berrangé
2019-07-02 9:50 ` Daniel P. Berrangé
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 6/9] i386: Replace -noTSX, -IBRS, -IBPB CPU models with aliases Eduardo Habkost
2019-07-02 9:41 ` Daniel P. Berrangé
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 7/9] i386: Make unversioned CPU models be aliases Eduardo Habkost
2019-07-02 9:45 ` Daniel P. Berrangé
2019-07-02 13:57 ` Daniel P. Berrangé
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 8/9] docs: Deprecate CPU model runnability guarantees Eduardo Habkost
2019-07-02 9:46 ` Daniel P. Berrangé
2019-06-28 0:28 ` [Qemu-devel] [PATCH v2 9/9] i386: Add Cascadelake-Server-v2 CPU model Eduardo Habkost
2019-07-01 7:23 ` Xiaoyao Li
2019-07-01 20:38 ` Eduardo Habkost
2019-07-02 9:47 ` Daniel P. Berrangé
2019-07-02 13:55 ` Eduardo Habkost
2019-06-28 1:16 ` [Qemu-devel] [PATCH v2 0/9] x86 CPU model versioning no-reply
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