* [U-Boot] [PATCH v2 0/5] SiFive SPI MMC Support
@ 2019-06-29 6:56 Anup Patel
2019-06-29 6:56 ` [U-Boot] [PATCH v2 1/5] spi: Add SiFive SPI driver Anup Patel
` (5 more replies)
0 siblings, 6 replies; 16+ messages in thread
From: Anup Patel @ 2019-06-29 6:56 UTC (permalink / raw)
To: u-boot
This patchset adds:
1. SiFive SPI driver
2. New MMC SPI driver based on DM_MMC and DM_SPI
3. Enables SiFive SPI driver and MMC SPI driver for SiFive Unleashed board
With this patch series, we can now load files from SD card on SiFive
Unleashed board. Many thanks to Bhargav for porting SiFive SPI driver
and updating MMC SPI driver for us.
These patches can be also found in riscv_unleashed_mmc_spi_v2 branch of:
https//github.com/avpatel/u-boot.git
Changes since v1:
- Make response matching part belongs to mmc_spi_sendcmd()
- Match response to zero for SEND_STATUS (CMD13)
- Add separate patch for updating SiFive FU540 Documentation
Anup Patel (2):
mmc: skip select_mode_and_width for MMC SPI host
doc: sifive-fu540: Update README for SiFive SPI and MMC SPI drivers
Bhargav Shah (3):
spi: Add SiFive SPI driver
mmc: mmc_spi: Re-write driver using DM framework
riscv: sifive: fu540: Enable SiFive SPI and MMC SPI drivers
board/sifive/fu540/Kconfig | 8 +
doc/README.sifive-fu540 | 4 +-
drivers/mmc/Kconfig | 18 ++
drivers/mmc/mmc.c | 14 ++
drivers/mmc/mmc_spi.c | 469 ++++++++++++++++++++++++-------------
drivers/spi/Kconfig | 8 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-sifive.c | 405 ++++++++++++++++++++++++++++++++
8 files changed, 757 insertions(+), 170 deletions(-)
create mode 100644 drivers/spi/spi-sifive.c
--
2.17.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH v2 1/5] spi: Add SiFive SPI driver
2019-06-29 6:56 [U-Boot] [PATCH v2 0/5] SiFive SPI MMC Support Anup Patel
@ 2019-06-29 6:56 ` Anup Patel
2019-07-05 6:28 ` Bin Meng
2019-06-29 6:56 ` [U-Boot] [PATCH v2 2/5] mmc: skip select_mode_and_width for MMC SPI host Anup Patel
` (4 subsequent siblings)
5 siblings, 1 reply; 16+ messages in thread
From: Anup Patel @ 2019-06-29 6:56 UTC (permalink / raw)
To: u-boot
From: Bhargav Shah <bhargavshah1988@gmail.com>
This patch adds SiFive SPI driver. The driver is 100% DM driver
and it determines input clock using clk framework.
The SiFive SPI block is found on SiFive FU540 SOC and is used to
access flash and MMC devices on SiFive Unleashed board.
This driver implementation is inspired from the Linux SiFive SPI
driver available in Linux-5.2 or higher and SiFive FSBL sources.
Signed-off-by: Bhargav Shah <bhargavshah1988@gmail.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
drivers/spi/Kconfig | 8 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-sifive.c | 405 +++++++++++++++++++++++++++++++++++++++
3 files changed, 414 insertions(+)
create mode 100644 drivers/spi/spi-sifive.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index eb32f082fe..2712bad310 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -224,6 +224,14 @@ config SANDBOX_SPI
};
};
+config SIFIVE_SPI
+ bool "SiFive SPI driver"
+ help
+ This driver supports the SiFive SPI IP. If unsure say N.
+ Enable the SiFive SPI controller driver.
+
+ The SiFive SPI controller driver is found on various SiFive SoCs.
+
config SPI_SUNXI
bool "Allwinner SoC SPI controllers"
help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 8be9a4baa2..09a9d3697e 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -49,6 +49,7 @@ obj-$(CONFIG_PL022_SPI) += pl022_spi.o
obj-$(CONFIG_RENESAS_RPC_SPI) += renesas_rpc_spi.o
obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o
obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
+obj-$(CONFIG_SIFIVE_SPI) += spi-sifive.o
obj-$(CONFIG_SPI_SUNXI) += spi-sunxi.o
obj-$(CONFIG_SH_SPI) += sh_spi.o
obj-$(CONFIG_SH_QSPI) += sh_qspi.o
diff --git a/drivers/spi/spi-sifive.c b/drivers/spi/spi-sifive.c
new file mode 100644
index 0000000000..70eebc0463
--- /dev/null
+++ b/drivers/spi/spi-sifive.c
@@ -0,0 +1,405 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 SiFive, Inc.
+ * Copyright 2019 Bhargav Shah <bhargavshah1988@gmail.com>
+ *
+ * SiFive SPI controller driver (master mode only)
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <malloc.h>
+#include <spi.h>
+#include <asm/io.h>
+#include <linux/log2.h>
+#include <clk.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SIFIVE_SPI_MAX_CS 32
+
+#define SIFIVE_SPI_DEFAULT_DEPTH 8
+#define SIFIVE_SPI_DEFAULT_BITS 8
+
+/* register offsets */
+#define SIFIVE_SPI_REG_SCKDIV 0x00 /* Serial clock divisor */
+#define SIFIVE_SPI_REG_SCKMODE 0x04 /* Serial clock mode */
+#define SIFIVE_SPI_REG_CSID 0x10 /* Chip select ID */
+#define SIFIVE_SPI_REG_CSDEF 0x14 /* Chip select default */
+#define SIFIVE_SPI_REG_CSMODE 0x18 /* Chip select mode */
+#define SIFIVE_SPI_REG_DELAY0 0x28 /* Delay control 0 */
+#define SIFIVE_SPI_REG_DELAY1 0x2c /* Delay control 1 */
+#define SIFIVE_SPI_REG_FMT 0x40 /* Frame format */
+#define SIFIVE_SPI_REG_TXDATA 0x48 /* Tx FIFO data */
+#define SIFIVE_SPI_REG_RXDATA 0x4c /* Rx FIFO data */
+#define SIFIVE_SPI_REG_TXMARK 0x50 /* Tx FIFO watermark */
+#define SIFIVE_SPI_REG_RXMARK 0x54 /* Rx FIFO watermark */
+#define SIFIVE_SPI_REG_FCTRL 0x60 /* SPI flash interface control */
+#define SIFIVE_SPI_REG_FFMT 0x64 /* SPI flash instruction format */
+#define SIFIVE_SPI_REG_IE 0x70 /* Interrupt Enable Register */
+#define SIFIVE_SPI_REG_IP 0x74 /* Interrupt Pendings Register */
+
+/* sckdiv bits */
+#define SIFIVE_SPI_SCKDIV_DIV_MASK 0xfffU
+
+/* sckmode bits */
+#define SIFIVE_SPI_SCKMODE_PHA BIT(0)
+#define SIFIVE_SPI_SCKMODE_POL BIT(1)
+#define SIFIVE_SPI_SCKMODE_MODE_MASK (SIFIVE_SPI_SCKMODE_PHA | \
+ SIFIVE_SPI_SCKMODE_POL)
+
+/* csmode bits */
+#define SIFIVE_SPI_CSMODE_MODE_AUTO 0U
+#define SIFIVE_SPI_CSMODE_MODE_HOLD 2U
+#define SIFIVE_SPI_CSMODE_MODE_OFF 3U
+
+/* delay0 bits */
+#define SIFIVE_SPI_DELAY0_CSSCK(x) ((u32)(x))
+#define SIFIVE_SPI_DELAY0_CSSCK_MASK 0xffU
+#define SIFIVE_SPI_DELAY0_SCKCS(x) ((u32)(x) << 16)
+#define SIFIVE_SPI_DELAY0_SCKCS_MASK (0xffU << 16)
+
+/* delay1 bits */
+#define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x))
+#define SIFIVE_SPI_DELAY1_INTERCS_MASK 0xffU
+#define SIFIVE_SPI_DELAY1_INTERXFR(x) ((u32)(x) << 16)
+#define SIFIVE_SPI_DELAY1_INTERXFR_MASK (0xffU << 16)
+
+/* fmt bits */
+#define SIFIVE_SPI_FMT_PROTO_SINGLE 0U
+#define SIFIVE_SPI_FMT_PROTO_DUAL 1U
+#define SIFIVE_SPI_FMT_PROTO_QUAD 2U
+#define SIFIVE_SPI_FMT_PROTO_MASK 3U
+#define SIFIVE_SPI_FMT_ENDIAN BIT(2)
+#define SIFIVE_SPI_FMT_DIR BIT(3)
+#define SIFIVE_SPI_FMT_LEN(x) ((u32)(x) << 16)
+#define SIFIVE_SPI_FMT_LEN_MASK (0xfU << 16)
+
+/* txdata bits */
+#define SIFIVE_SPI_TXDATA_DATA_MASK 0xffU
+#define SIFIVE_SPI_TXDATA_FULL BIT(31)
+
+/* rxdata bits */
+#define SIFIVE_SPI_RXDATA_DATA_MASK 0xffU
+#define SIFIVE_SPI_RXDATA_EMPTY BIT(31)
+
+/* ie and ip bits */
+#define SIFIVE_SPI_IP_TXWM BIT(0)
+#define SIFIVE_SPI_IP_RXWM BIT(1)
+
+struct sifive_spi {
+ void *regs; /* base address of the registers */
+ u32 fifo_depth;
+ u32 bits_per_word;
+ u32 cs_inactive; /* Level of the CS pins when inactive*/
+ u32 freq;
+ u32 num_cs;
+};
+
+static void sifive_spi_write(struct sifive_spi *spi, int offset, u32 value)
+{
+ writel(value, spi->regs + offset);
+}
+
+static u32 sifive_spi_read(struct sifive_spi *spi, int offset)
+{
+ return readl(spi->regs + offset);
+}
+
+static void sifive_spi_prep_device(struct sifive_spi *spi,
+ struct dm_spi_slave_platdata *slave)
+{
+ /* Update the chip select polarity */
+ if (slave->mode & SPI_CS_HIGH)
+ spi->cs_inactive &= ~BIT(slave->cs);
+ else
+ spi->cs_inactive |= BIT(slave->cs);
+ sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, spi->cs_inactive);
+
+ /* Select the correct device */
+ sifive_spi_write(spi, SIFIVE_SPI_REG_CSID, slave->cs);
+}
+
+static int sifive_spi_set_cs(struct sifive_spi *spi,
+ struct dm_spi_slave_platdata *slave)
+{
+ u32 cs_mode = SIFIVE_SPI_CSMODE_MODE_HOLD;
+
+ if (slave->cs > spi->num_cs)
+ return -EINVAL;
+
+ if (slave->mode & SPI_CS_HIGH)
+ cs_mode = SIFIVE_SPI_CSMODE_MODE_AUTO;
+
+ sifive_spi_write(spi, SIFIVE_SPI_REG_CSMODE, cs_mode);
+
+ return 0;
+}
+
+static void sifive_spi_clear_cs(struct sifive_spi *spi)
+{
+ sifive_spi_write(spi, SIFIVE_SPI_REG_CSMODE,
+ SIFIVE_SPI_CSMODE_MODE_AUTO);
+}
+
+static void sifive_spi_prep_transfer(struct sifive_spi *spi,
+ bool is_rx_xfer,
+ struct dm_spi_slave_platdata *slave)
+{
+ u32 cr;
+
+ /* Modify the SPI protocol mode */
+ cr = sifive_spi_read(spi, SIFIVE_SPI_REG_FMT);
+
+ /* Bits per word ? */
+ cr &= ~SIFIVE_SPI_FMT_LEN_MASK;
+ cr |= SIFIVE_SPI_FMT_LEN(SIFIVE_SPI_DEFAULT_BITS);
+
+ /* LSB first? */
+ cr &= ~SIFIVE_SPI_FMT_ENDIAN;
+ if (slave->mode & SPI_LSB_FIRST)
+ cr |= SIFIVE_SPI_FMT_ENDIAN;
+
+ /* Number of wires ? */
+ cr &= ~SIFIVE_SPI_FMT_PROTO_MASK;
+ if ((slave->mode & SPI_TX_QUAD) || (slave->mode & SPI_RX_QUAD))
+ cr |= SIFIVE_SPI_FMT_PROTO_QUAD;
+ else if ((slave->mode & SPI_TX_DUAL) || (slave->mode & SPI_RX_DUAL))
+ cr |= SIFIVE_SPI_FMT_PROTO_DUAL;
+ else
+ cr |= SIFIVE_SPI_FMT_PROTO_SINGLE;
+
+ /* SPI direction in/out ? */
+ cr &= ~SIFIVE_SPI_FMT_DIR;
+ if (!is_rx_xfer)
+ cr |= SIFIVE_SPI_FMT_DIR;
+
+ sifive_spi_write(spi, SIFIVE_SPI_REG_FMT, cr);
+}
+
+static void sifive_spi_rx(struct sifive_spi *spi, u8 *rx_ptr)
+{
+ u32 data;
+
+ do {
+ data = sifive_spi_read(spi, SIFIVE_SPI_REG_RXDATA);
+ } while (data & SIFIVE_SPI_RXDATA_EMPTY);
+
+ if (rx_ptr)
+ *rx_ptr = data & SIFIVE_SPI_RXDATA_DATA_MASK;
+}
+
+static void sifive_spi_tx(struct sifive_spi *spi, const u8 *tx_ptr)
+{
+ u32 data;
+ u8 tx_data = (tx_ptr) ? *tx_ptr & SIFIVE_SPI_TXDATA_DATA_MASK :
+ SIFIVE_SPI_TXDATA_DATA_MASK;
+
+ do {
+ data = sifive_spi_read(spi, SIFIVE_SPI_REG_TXDATA);
+ } while (data & SIFIVE_SPI_TXDATA_FULL);
+
+ sifive_spi_write(spi, SIFIVE_SPI_REG_TXDATA, tx_data);
+}
+
+static u8 sifive_spi_txrx(struct sifive_spi *spi, const u8 *tx_ptr)
+{
+ u8 rx = 0;
+
+ sifive_spi_tx(spi, tx_ptr);
+ sifive_spi_rx(spi, &rx);
+
+ return rx;
+}
+
+static int sifive_spi_claim_bus(struct udevice *dev)
+{
+ int ret;
+ struct udevice *bus = dev->parent;
+ struct sifive_spi *spi = dev_get_priv(bus);
+ struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
+
+ sifive_spi_prep_device(spi, slave);
+
+ ret = sifive_spi_set_cs(spi, slave);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int sifive_spi_release_bus(struct udevice *dev)
+{
+ struct sifive_spi *spi = dev_get_priv(dev->parent);
+
+ sifive_spi_clear_cs(spi);
+
+ return 0;
+}
+
+static int sifive_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ struct udevice *bus = dev->parent;
+ struct sifive_spi *spi = dev_get_priv(bus);
+ struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
+ const unsigned char *tx_ptr = dout;
+ unsigned char *rx_ptr = din;
+ u32 remaining_len;
+
+ sifive_spi_prep_transfer(spi, true, slave);
+
+ remaining_len = bitlen / 8;
+
+ while (remaining_len) {
+ int n_words, tx_words, rx_words;
+
+ n_words = min(remaining_len, spi->fifo_depth);
+
+ /* Enqueue n_words for transmission */
+ if (tx_ptr) {
+ for (tx_words = 0; tx_words < n_words; ++tx_words) {
+ sifive_spi_txrx(spi, tx_ptr);
+ tx_ptr++;
+ }
+ }
+
+ /* Read out all the data from the RX FIFO */
+ if (rx_ptr) {
+ for (rx_words = 0; rx_words < n_words; ++rx_words) {
+ *rx_ptr = sifive_spi_txrx(spi, NULL);
+ rx_ptr++;
+ }
+ }
+
+ remaining_len -= n_words;
+ }
+
+ return 0;
+}
+
+static int sifive_spi_set_speed(struct udevice *bus, uint speed)
+{
+ struct sifive_spi *spi = dev_get_priv(bus);
+ u32 scale;
+
+ if (speed > spi->freq)
+ speed = spi->freq;
+
+ /* Cofigure max speed */
+ scale = (DIV_ROUND_UP(spi->freq >> 1, speed) - 1)
+ & SIFIVE_SPI_SCKDIV_DIV_MASK;
+ sifive_spi_write(spi, SIFIVE_SPI_REG_SCKDIV, scale);
+ return 0;
+}
+
+static int sifive_spi_set_mode(struct udevice *bus, uint mode)
+{
+ struct sifive_spi *spi = dev_get_priv(bus);
+ u32 cr;
+
+ /* Switch clock mode bits */
+ cr = sifive_spi_read(spi, SIFIVE_SPI_REG_SCKMODE) &
+ ~SIFIVE_SPI_SCKMODE_MODE_MASK;
+ if (mode & SPI_CPHA)
+ cr |= SIFIVE_SPI_SCKMODE_PHA;
+ if (mode & SPI_CPOL)
+ cr |= SIFIVE_SPI_SCKMODE_POL;
+
+ sifive_spi_write(spi, SIFIVE_SPI_REG_SCKMODE, cr);
+
+ return 0;
+}
+
+static int sifive_cs_info(struct udevice *bus, uint cs,
+ struct spi_cs_info *info)
+{
+ return 0;
+}
+
+static void sifive_spi_init_hw(struct sifive_spi *spi)
+{
+ u32 cs_bits;
+
+ /* probe the number of CS lines */
+ spi->cs_inactive = sifive_spi_read(spi, SIFIVE_SPI_REG_CSDEF);
+ sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, 0xffffffffU);
+ cs_bits = sifive_spi_read(spi, SIFIVE_SPI_REG_CSDEF);
+ sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, spi->cs_inactive);
+ if (!cs_bits) {
+ printf("Could not auto probe CS lines\n");
+ return;
+ }
+
+ spi->num_cs = ilog2(cs_bits) + 1;
+ if (spi->num_cs > SIFIVE_SPI_MAX_CS) {
+ printf("Invalid number of spi slaves\n");
+ return;
+ }
+
+ /* Watermark interrupts are disabled by default */
+ sifive_spi_write(spi, SIFIVE_SPI_REG_IE, 0);
+
+ /* Set CS/SCK Delays and Inactive Time to defaults */
+ sifive_spi_write(spi, SIFIVE_SPI_REG_DELAY0,
+ SIFIVE_SPI_DELAY0_CSSCK(1) |
+ SIFIVE_SPI_DELAY0_SCKCS(1));
+ sifive_spi_write(spi, SIFIVE_SPI_REG_DELAY1,
+ SIFIVE_SPI_DELAY1_INTERCS(1) |
+ SIFIVE_SPI_DELAY1_INTERXFR(0));
+
+ /* Exit specialized memory-mapped SPI flash mode */
+ sifive_spi_write(spi, SIFIVE_SPI_REG_FCTRL, 0);
+}
+
+static int sifive_spi_probe(struct udevice *bus)
+{
+ struct sifive_spi *spi = dev_get_priv(bus);
+ struct clk clkdev;
+ int ret;
+
+ spi->regs = (void *)(ulong)dev_remap_addr(bus);
+ if (!spi->regs)
+ return -ENODEV;
+
+ spi->fifo_depth = dev_read_u32_default(bus,
+ "sifive,fifo-depth",
+ SIFIVE_SPI_DEFAULT_DEPTH);
+
+ spi->bits_per_word = dev_read_u32_default(bus,
+ "sifive,max-bits-per-word",
+ SIFIVE_SPI_DEFAULT_BITS);
+
+ ret = clk_get_by_index(bus, 0, &clkdev);
+ if (ret)
+ return ret;
+ spi->freq = clk_get_rate(&clkdev);
+
+ /* init the sifive spi hw */
+ sifive_spi_init_hw(spi);
+
+ return 0;
+}
+
+static const struct dm_spi_ops sifive_spi_ops = {
+ .claim_bus = sifive_spi_claim_bus,
+ .release_bus = sifive_spi_release_bus,
+ .xfer = sifive_spi_xfer,
+ .set_speed = sifive_spi_set_speed,
+ .set_mode = sifive_spi_set_mode,
+ .cs_info = sifive_cs_info,
+};
+
+static const struct udevice_id sifive_spi_ids[] = {
+ { .compatible = "sifive,spi0" },
+ { }
+};
+
+U_BOOT_DRIVER(sifive_spi) = {
+ .name = "sifive_spi",
+ .id = UCLASS_SPI,
+ .of_match = sifive_spi_ids,
+ .ops = &sifive_spi_ops,
+ .priv_auto_alloc_size = sizeof(struct sifive_spi),
+ .probe = sifive_spi_probe,
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH v2 2/5] mmc: skip select_mode_and_width for MMC SPI host
2019-06-29 6:56 [U-Boot] [PATCH v2 0/5] SiFive SPI MMC Support Anup Patel
2019-06-29 6:56 ` [U-Boot] [PATCH v2 1/5] spi: Add SiFive SPI driver Anup Patel
@ 2019-06-29 6:56 ` Anup Patel
2019-07-05 6:28 ` Bin Meng
2019-06-29 6:57 ` [U-Boot] [PATCH v2 3/5] mmc: mmc_spi: Re-write driver using DM framework Anup Patel
` (3 subsequent siblings)
5 siblings, 1 reply; 16+ messages in thread
From: Anup Patel @ 2019-06-29 6:56 UTC (permalink / raw)
To: u-boot
The MMC mode and width are fixed for MMC SPI host hence we skip
sd_select_mode_and_width() and mmc_select_mode_and_width() for
MMC SPI host.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
drivers/mmc/mmc.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 456c1b4cc9..95008c72c3 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -1672,6 +1672,13 @@ static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps)
mmc_dump_capabilities("host", mmc->host_caps);
#endif
+ if (mmc_host_is_spi(mmc)) {
+ mmc_set_bus_width(mmc, 1);
+ mmc_select_mode(mmc, SD_LEGACY);
+ mmc_set_clock(mmc, mmc->tran_speed, MMC_CLK_ENABLE);
+ return 0;
+ }
+
/* Restrict card's capabilities by what the host can do */
caps = card_caps & mmc->host_caps;
@@ -1934,6 +1941,13 @@ static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
mmc_dump_capabilities("host", mmc->host_caps);
#endif
+ if (mmc_host_is_spi(mmc)) {
+ mmc_set_bus_width(mmc, 1);
+ mmc_select_mode(mmc, MMC_LEGACY);
+ mmc_set_clock(mmc, mmc->tran_speed, MMC_CLK_ENABLE);
+ return 0;
+ }
+
/* Restrict card's capabilities by what the host can do */
card_caps &= mmc->host_caps;
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH v2 3/5] mmc: mmc_spi: Re-write driver using DM framework
2019-06-29 6:56 [U-Boot] [PATCH v2 0/5] SiFive SPI MMC Support Anup Patel
2019-06-29 6:56 ` [U-Boot] [PATCH v2 1/5] spi: Add SiFive SPI driver Anup Patel
2019-06-29 6:56 ` [U-Boot] [PATCH v2 2/5] mmc: skip select_mode_and_width for MMC SPI host Anup Patel
@ 2019-06-29 6:57 ` Anup Patel
2019-07-05 6:28 ` Bin Meng
2019-06-29 6:57 ` [U-Boot] [PATCH v2 4/5] riscv: sifive: fu540: Enable SiFive SPI and MMC SPI drivers Anup Patel
` (2 subsequent siblings)
5 siblings, 1 reply; 16+ messages in thread
From: Anup Patel @ 2019-06-29 6:57 UTC (permalink / raw)
To: u-boot
From: Bhargav Shah <bhargavshah1988@gmail.com>
This patch rewrites MMC SPI driver using U-Boot DM
framework and get it's working on SiFive Unleashed
board.
Signed-off-by: Bhargav Shah <bhargavshah1988@gmail.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
drivers/mmc/Kconfig | 18 ++
drivers/mmc/mmc_spi.c | 469 +++++++++++++++++++++++++++---------------
2 files changed, 320 insertions(+), 167 deletions(-)
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index c23299ea96..f750dad00a 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -46,6 +46,24 @@ config SPL_DM_MMC
if MMC
+config MMC_SPI
+ bool "Support for SPI-based MMC controller"
+ depends on DM_MMC && DM_SPI
+ help
+ This selects SPI-based MMC controllers.
+ If you have an MMC controller on a SPI bus, say Y here.
+
+ If unsure, say N.
+
+config MMC_SPI_CRC_ON
+ bool "Support CRC for SPI-based MMC controller"
+ depends on MMC_SPI
+ default y
+ help
+ This enables CRC for SPI-based MMC controllers.
+
+ If unsure, say N.
+
config ARM_PL180_MMCI
bool "ARM AMBA Multimedia Card Interface and compatible support"
depends on DM_MMC && OF_CONTROL
diff --git a/drivers/mmc/mmc_spi.c b/drivers/mmc/mmc_spi.c
index 4f57990d9c..f3d687ae80 100644
--- a/drivers/mmc/mmc_spi.c
+++ b/drivers/mmc/mmc_spi.c
@@ -2,6 +2,8 @@
* generic mmc spi driver
*
* Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
+ * Copyright 2019 Bhargav Shah <bhargavshah1988@gmail.com>
+ *
* Licensed under the GPL-2 or later.
*/
#include <common.h>
@@ -9,21 +11,23 @@
#include <malloc.h>
#include <part.h>
#include <mmc.h>
-#include <spi.h>
+#include <stdlib.h>
#include <u-boot/crc.h>
#include <linux/crc7.h>
#include <asm/byteorder.h>
+#include <dm.h>
+#include <spi.h>
/* MMC/SD in SPI mode reports R1 status always */
-#define R1_SPI_IDLE (1 << 0)
-#define R1_SPI_ERASE_RESET (1 << 1)
-#define R1_SPI_ILLEGAL_COMMAND (1 << 2)
-#define R1_SPI_COM_CRC (1 << 3)
-#define R1_SPI_ERASE_SEQ (1 << 4)
-#define R1_SPI_ADDRESS (1 << 5)
-#define R1_SPI_PARAMETER (1 << 6)
+#define R1_SPI_IDLE BIT(0)
+#define R1_SPI_ERASE_RESET BIT(1)
+#define R1_SPI_ILLEGAL_COMMAND BIT(2)
+#define R1_SPI_COM_CRC BIT(3)
+#define R1_SPI_ERASE_SEQ BIT(4)
+#define R1_SPI_ADDRESS BIT(5)
+#define R1_SPI_PARAMETER BIT(6)
/* R1 bit 7 is always zero, reuse this bit for error */
-#define R1_SPI_ERROR (1 << 7)
+#define R1_SPI_ERROR BIT(7)
/* Response tokens used to ack each block written: */
#define SPI_MMC_RESPONSE_CODE(x) ((x) & 0x1f)
@@ -34,28 +38,45 @@
/* Read and write blocks start with these tokens and end with crc;
* on error, read tokens act like a subset of R2_SPI_* values.
*/
-#define SPI_TOKEN_SINGLE 0xfe /* single block r/w, multiblock read */
-#define SPI_TOKEN_MULTI_WRITE 0xfc /* multiblock write */
-#define SPI_TOKEN_STOP_TRAN 0xfd /* terminate multiblock write */
+/* single block write multiblock read */
+#define SPI_TOKEN_SINGLE 0xfe
+/* multiblock write */
+#define SPI_TOKEN_MULTI_WRITE 0xfc
+/* terminate multiblock write */
+#define SPI_TOKEN_STOP_TRAN 0xfd
/* MMC SPI commands start with a start bit "0" and a transmit bit "1" */
-#define MMC_SPI_CMD(x) (0x40 | (x & 0x3f))
+#define MMC_SPI_CMD(x) (0x40 | (x))
/* bus capability */
-#define MMC_SPI_VOLTAGE (MMC_VDD_32_33 | MMC_VDD_33_34)
-#define MMC_SPI_MIN_CLOCK 400000 /* 400KHz to meet MMC spec */
+#define MMC_SPI_VOLTAGE (MMC_VDD_32_33 | MMC_VDD_33_34)
+#define MMC_SPI_MIN_CLOCK 400000 /* 400KHz to meet MMC spec */
+#define MMC_SPI_MAX_CLOCK 25000000 /* SD/MMC legacy speed */
/* timeout value */
-#define CTOUT 8
-#define RTOUT 3000000 /* 1 sec */
-#define WTOUT 3000000 /* 1 sec */
+#define CMD_TIMEOUT 8
+#define READ_TIMEOUT 3000000 /* 1 sec */
+#define WRITE_TIMEOUT 3000000 /* 1 sec */
-static uint mmc_spi_sendcmd(struct mmc *mmc, ushort cmdidx, u32 cmdarg)
+struct mmc_spi_priv {
+ struct spi_slave *spi;
+ struct mmc_config cfg;
+ struct mmc mmc;
+};
+
+static int mmc_spi_sendcmd(struct udevice *dev,
+ ushort cmdidx, u32 cmdarg, u32 resp_type,
+ u8 *resp, u32 resp_size,
+ bool resp_match, u8 resp_match_value)
{
- struct spi_slave *spi = mmc->priv;
- u8 cmdo[7];
- u8 r1;
- int i;
+ int i, rpos = 0, ret = 0;
+ u8 cmdo[7], r;
+
+ debug("%s: cmd%d cmdarg=0x%x resp_type=0x%x "
+ "resp_size=%d resp_match=%d resp_match_value=0x%x\n",
+ __func__, cmdidx, cmdarg, resp_type,
+ resp_size, resp_match, resp_match_value);
+
cmdo[0] = 0xff;
cmdo[1] = MMC_SPI_CMD(cmdidx);
cmdo[2] = cmdarg >> 24;
@@ -63,37 +84,79 @@ static uint mmc_spi_sendcmd(struct mmc *mmc, ushort cmdidx, u32 cmdarg)
cmdo[4] = cmdarg >> 8;
cmdo[5] = cmdarg;
cmdo[6] = (crc7(0, &cmdo[1], 5) << 1) | 0x01;
- spi_xfer(spi, sizeof(cmdo) * 8, cmdo, NULL, 0);
- for (i = 0; i < CTOUT; i++) {
- spi_xfer(spi, 1 * 8, NULL, &r1, 0);
- if (i && (r1 & 0x80) == 0) /* r1 response */
- break;
+ ret = dm_spi_xfer(dev, sizeof(cmdo) * 8, cmdo, NULL, 0);
+ if (ret)
+ return ret;
+
+ ret = dm_spi_xfer(dev, 1 * 8, NULL, &r, 0);
+ if (ret)
+ return ret;
+
+ if (!resp || !resp_size)
+ return 0;
+
+ debug("%s: cmd%d", __func__, cmdidx);
+
+ if (resp_match) {
+ r = ~resp_match_value;
+ i = CMD_TIMEOUT;
+ while (i--) {
+ ret = dm_spi_xfer(dev, 1 * 8, NULL, &r, 0);
+ if (ret)
+ return ret;
+ debug(" resp%d=0x%x", rpos, r);
+ rpos++;
+ if (r == resp_match_value)
+ break;
+ }
+ if (!i && (r != resp_match_value))
+ return -ETIMEDOUT;
+ }
+
+ for (i = 0; i < resp_size; i++) {
+ if (i == 0 && resp_match) {
+ resp[i] = resp_match_value;
+ continue;
+ }
+ ret = dm_spi_xfer(dev, 1 * 8, NULL, &r, 0);
+ if (ret)
+ return ret;
+ debug(" resp%d=0x%x", rpos, r);
+ rpos++;
+ resp[i] = r;
}
- debug("%s:cmd%d resp%d %x\n", __func__, cmdidx, i, r1);
- return r1;
+
+ debug("\n");
+
+ return 0;
}
-static uint mmc_spi_readdata(struct mmc *mmc, void *xbuf,
- u32 bcnt, u32 bsize)
+static int mmc_spi_readdata(struct udevice *dev,
+ void *xbuf, u32 bcnt, u32 bsize)
{
- struct spi_slave *spi = mmc->priv;
- u8 *buf = xbuf;
- u8 r1;
u16 crc;
- int i;
+ u8 *buf = xbuf, r1;
+ int i, ret = 0;
+
while (bcnt--) {
- for (i = 0; i < RTOUT; i++) {
- spi_xfer(spi, 1 * 8, NULL, &r1, 0);
- if (r1 != 0xff) /* data token */
+ for (i = 0; i < READ_TIMEOUT; i++) {
+ ret = dm_spi_xfer(dev, 1 * 8, NULL, &r1, 0);
+ if (ret)
+ return ret;
+ if (r1 == SPI_TOKEN_SINGLE)
break;
}
- debug("%s:tok%d %x\n", __func__, i, r1);
+ debug("%s: data tok%d 0x%x\n", __func__, i, r1);
if (r1 == SPI_TOKEN_SINGLE) {
- spi_xfer(spi, bsize * 8, NULL, buf, 0);
- spi_xfer(spi, 2 * 8, NULL, &crc, 0);
+ ret = dm_spi_xfer(dev, bsize * 8, NULL, buf, 0);
+ if (ret)
+ return ret;
+ ret = dm_spi_xfer(dev, 2 * 8, NULL, &crc, 0);
+ if (ret)
+ return ret;
#ifdef CONFIG_MMC_SPI_CRC_ON
- if (be_to_cpu16(crc16_ccitt(0, buf, bsize)) != crc) {
- debug("%s: CRC error\n", mmc->cfg->name);
+ if (be16_to_cpu(crc16_ccitt(0, buf, bsize)) != crc) {
+ debug("%s: data crc error\n", __func__);
r1 = R1_SPI_COM_CRC;
break;
}
@@ -105,48 +168,56 @@ static uint mmc_spi_readdata(struct mmc *mmc, void *xbuf,
}
buf += bsize;
}
- return r1;
+
+ if (r1 & R1_SPI_COM_CRC)
+ ret = -ECOMM;
+ else if (r1) /* other errors */
+ ret = -ETIMEDOUT;
+
+ return ret;
}
-static uint mmc_spi_writedata(struct mmc *mmc, const void *xbuf,
- u32 bcnt, u32 bsize, int multi)
+static int mmc_spi_writedata(struct udevice *dev, const void *xbuf,
+ u32 bcnt, u32 bsize, int multi)
{
- struct spi_slave *spi = mmc->priv;
const u8 *buf = xbuf;
- u8 r1;
+ u8 r1, tok[2];
u16 crc;
- u8 tok[2];
- int i;
+ int i, ret = 0;
+
tok[0] = 0xff;
tok[1] = multi ? SPI_TOKEN_MULTI_WRITE : SPI_TOKEN_SINGLE;
+
while (bcnt--) {
#ifdef CONFIG_MMC_SPI_CRC_ON
crc = cpu_to_be16(crc16_ccitt(0, (u8 *)buf, bsize));
#endif
- spi_xfer(spi, 2 * 8, tok, NULL, 0);
- spi_xfer(spi, bsize * 8, buf, NULL, 0);
- spi_xfer(spi, 2 * 8, &crc, NULL, 0);
- for (i = 0; i < CTOUT; i++) {
- spi_xfer(spi, 1 * 8, NULL, &r1, 0);
+ dm_spi_xfer(dev, 2 * 8, tok, NULL, 0);
+ dm_spi_xfer(dev, bsize * 8, buf, NULL, 0);
+ dm_spi_xfer(dev, 2 * 8, &crc, NULL, 0);
+ for (i = 0; i < CMD_TIMEOUT; i++) {
+ dm_spi_xfer(dev, 1 * 8, NULL, &r1, 0);
if ((r1 & 0x10) == 0) /* response token */
break;
}
- debug("%s:tok%d %x\n", __func__, i, r1);
+ debug("%s: data tok%d 0x%x\n", __func__, i, r1);
if (SPI_MMC_RESPONSE_CODE(r1) == SPI_RESPONSE_ACCEPTED) {
- for (i = 0; i < WTOUT; i++) { /* wait busy */
- spi_xfer(spi, 1 * 8, NULL, &r1, 0);
+ debug("%s: data accepted\n", __func__);
+ for (i = 0; i < WRITE_TIMEOUT; i++) { /* wait busy */
+ dm_spi_xfer(dev, 1 * 8, NULL, &r1, 0);
if (i && r1 == 0xff) {
r1 = 0;
break;
}
}
- if (i == WTOUT) {
- debug("%s:wtout %x\n", __func__, r1);
+ if (i == WRITE_TIMEOUT) {
+ debug("%s: data write timeout 0x%x\n",
+ __func__, r1);
r1 = R1_SPI_ERROR;
break;
}
} else {
- debug("%s: err %x\n", __func__, r1);
+ debug("%s: data error 0x%x\n", __func__, r1);
r1 = R1_SPI_COM_CRC;
break;
}
@@ -154,140 +225,204 @@ static uint mmc_spi_writedata(struct mmc *mmc, const void *xbuf,
}
if (multi && bcnt == -1) { /* stop multi write */
tok[1] = SPI_TOKEN_STOP_TRAN;
- spi_xfer(spi, 2 * 8, tok, NULL, 0);
- for (i = 0; i < WTOUT; i++) { /* wait busy */
- spi_xfer(spi, 1 * 8, NULL, &r1, 0);
+ dm_spi_xfer(dev, 2 * 8, tok, NULL, 0);
+ for (i = 0; i < WRITE_TIMEOUT; i++) { /* wait busy */
+ dm_spi_xfer(dev, 1 * 8, NULL, &r1, 0);
if (i && r1 == 0xff) {
r1 = 0;
break;
}
}
- if (i == WTOUT) {
- debug("%s:wstop %x\n", __func__, r1);
+ if (i == WRITE_TIMEOUT) {
+ debug("%s: data write timeout 0x%x\n", __func__, r1);
r1 = R1_SPI_ERROR;
}
}
- return r1;
-}
-static int mmc_spi_request(struct mmc *mmc, struct mmc_cmd *cmd,
- struct mmc_data *data)
-{
- struct spi_slave *spi = mmc->priv;
- u8 r1;
- int i;
- int ret = 0;
- debug("%s:cmd%d %x %x\n", __func__,
- cmd->cmdidx, cmd->resp_type, cmd->cmdarg);
- spi_claim_bus(spi);
- spi_cs_activate(spi);
- r1 = mmc_spi_sendcmd(mmc, cmd->cmdidx, cmd->cmdarg);
- if (r1 == 0xff) { /* no response */
- ret = -ENOMEDIUM;
- goto done;
- } else if (r1 & R1_SPI_COM_CRC) {
+ if (r1 & R1_SPI_COM_CRC)
ret = -ECOMM;
- goto done;
- } else if (r1 & ~R1_SPI_IDLE) { /* other errors */
+ else if (r1) /* other errors */
ret = -ETIMEDOUT;
+
+ return ret;
+}
+
+static int dm_mmc_spi_set_ios(struct udevice *dev)
+{
+ return 0;
+}
+
+static int dm_mmc_spi_request(struct udevice *dev, struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+ int i, multi, ret = 0;
+ u8 *resp = NULL;
+ u32 resp_size = 0;
+ bool resp_match = false;
+ u8 resp8 = 0, resp40[5] = { 0 }, resp_match_value = 0;
+
+ dm_spi_claim_bus(dev);
+
+ for (i = 0; i < 4; i++)
+ cmd->response[i] = 0;
+
+ switch (cmd->cmdidx) {
+ case SD_CMD_APP_SEND_OP_COND:
+ case MMC_CMD_SEND_OP_COND:
+ resp = &resp8;
+ resp_size = sizeof(resp8);
+ cmd->cmdarg = 0x40000000;
+ break;
+ case SD_CMD_SEND_IF_COND:
+ resp = (u8 *)&resp40[0];
+ resp_size = sizeof(resp40);
+ resp_match = true;
+ resp_match_value = R1_SPI_IDLE;
+ break;
+ case MMC_CMD_SPI_READ_OCR:
+ resp = (u8 *)&resp40[0];
+ resp_size = sizeof(resp40);
+ break;
+ case MMC_CMD_SEND_STATUS:
+ case MMC_CMD_SET_BLOCKLEN:
+ case MMC_CMD_SPI_CRC_ON_OFF:
+ case MMC_CMD_STOP_TRANSMISSION:
+ resp = &resp8;
+ resp_size = sizeof(resp8);
+ resp_match = true;
+ resp_match_value = 0x0;
+ break;
+ case MMC_CMD_SEND_CSD:
+ case MMC_CMD_SEND_CID:
+ case MMC_CMD_READ_SINGLE_BLOCK:
+ case MMC_CMD_READ_MULTIPLE_BLOCK:
+ case MMC_CMD_WRITE_SINGLE_BLOCK:
+ case MMC_CMD_WRITE_MULTIPLE_BLOCK:
+ break;
+ default:
+ resp = &resp8;
+ resp_size = sizeof(resp8);
+ resp_match = true;
+ resp_match_value = R1_SPI_IDLE;
+ break;
+ };
+
+ ret = mmc_spi_sendcmd(dev, cmd->cmdidx, cmd->cmdarg, cmd->resp_type,
+ resp, resp_size, resp_match, resp_match_value);
+ if (ret)
goto done;
- } else if (cmd->resp_type == MMC_RSP_R2) {
- r1 = mmc_spi_readdata(mmc, cmd->response, 1, 16);
+
+ switch (cmd->cmdidx) {
+ case SD_CMD_APP_SEND_OP_COND:
+ case MMC_CMD_SEND_OP_COND:
+ cmd->response[0] = (resp8 & R1_SPI_IDLE) ? 0 : OCR_BUSY;
+ break;
+ case SD_CMD_SEND_IF_COND:
+ case MMC_CMD_SPI_READ_OCR:
+ cmd->response[0] = resp40[4];
+ cmd->response[0] |= (uint)resp40[3] << 8;
+ cmd->response[0] |= (uint)resp40[2] << 16;
+ cmd->response[0] |= (uint)resp40[1] << 24;
+ break;
+ case MMC_CMD_SEND_STATUS:
+ cmd->response[0] = (resp8 & 0xff) ?
+ MMC_STATUS_ERROR : MMC_STATUS_RDY_FOR_DATA;
+ break;
+ case MMC_CMD_SEND_CID:
+ case MMC_CMD_SEND_CSD:
+ ret = mmc_spi_readdata(dev, cmd->response, 1, 16);
+ if (ret)
+ return ret;
for (i = 0; i < 4; i++)
- cmd->response[i] = be32_to_cpu(cmd->response[i]);
- debug("r128 %x %x %x %x\n", cmd->response[0], cmd->response[1],
- cmd->response[2], cmd->response[3]);
- } else if (!data) {
- switch (cmd->cmdidx) {
- case SD_CMD_APP_SEND_OP_COND:
- case MMC_CMD_SEND_OP_COND:
- cmd->response[0] = (r1 & R1_SPI_IDLE) ? 0 : OCR_BUSY;
- break;
- case SD_CMD_SEND_IF_COND:
- case MMC_CMD_SPI_READ_OCR:
- spi_xfer(spi, 4 * 8, NULL, cmd->response, 0);
- cmd->response[0] = be32_to_cpu(cmd->response[0]);
- debug("r32 %x\n", cmd->response[0]);
- break;
- case MMC_CMD_SEND_STATUS:
- spi_xfer(spi, 1 * 8, NULL, cmd->response, 0);
- cmd->response[0] = (cmd->response[0] & 0xff) ?
- MMC_STATUS_ERROR : MMC_STATUS_RDY_FOR_DATA;
- break;
- }
- } else {
- debug("%s:data %x %x %x\n", __func__,
- data->flags, data->blocks, data->blocksize);
+ cmd->response[i] =
+ cpu_to_be32(cmd->response[i]);
+ break;
+ default:
+ cmd->response[0] = resp8;
+ break;
+ }
+
+ debug("%s: cmd%d resp0=0x%x resp1=0x%x resp2=0x%x resp3=0x%x\n",
+ __func__, cmd->cmdidx, cmd->response[0], cmd->response[1],
+ cmd->response[2], cmd->response[3]);
+
+ if (data) {
+ debug("%s: data flags=0x%x blocks=%d block_size=%d\n",
+ __func__, data->flags, data->blocks, data->blocksize);
+ multi = (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK);
if (data->flags == MMC_DATA_READ)
- r1 = mmc_spi_readdata(mmc, data->dest,
- data->blocks, data->blocksize);
+ ret = mmc_spi_readdata(dev, data->dest,
+ data->blocks, data->blocksize);
else if (data->flags == MMC_DATA_WRITE)
- r1 = mmc_spi_writedata(mmc, data->src,
- data->blocks, data->blocksize,
- (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK));
- if (r1 & R1_SPI_COM_CRC)
- ret = -ECOMM;
- else if (r1) /* other errors */
- ret = -ETIMEDOUT;
+ ret = mmc_spi_writedata(dev, data->src,
+ data->blocks, data->blocksize,
+ multi);
}
+
done:
- spi_cs_deactivate(spi);
- spi_release_bus(spi);
+ dm_spi_release_bus(dev);
+
return ret;
}
-static int mmc_spi_set_ios(struct mmc *mmc)
+static int mmc_spi_probe(struct udevice *dev)
{
- struct spi_slave *spi = mmc->priv;
+ struct mmc_spi_priv *priv = dev_get_priv(dev);
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ char *name;
+
+ priv->spi = dev_get_parent_priv(dev);
+ if (!priv->spi->max_hz)
+ priv->spi->max_hz = MMC_SPI_MAX_CLOCK;
+ priv->spi->speed = 0;
+ priv->spi->mode = SPI_MODE_0;
+ priv->spi->wordlen = 8;
+
+ name = malloc(strlen(dev->parent->name) + strlen(dev->name) + 4);
+ if (!name)
+ return -ENOMEM;
+ sprintf(name, "%s:%s", dev->parent->name, dev->name);
+
+ priv->cfg.name = name;
+ priv->cfg.host_caps = MMC_MODE_SPI;
+ priv->cfg.voltages = MMC_SPI_VOLTAGE;
+ priv->cfg.f_min = MMC_SPI_MIN_CLOCK;
+ priv->cfg.f_max = priv->spi->max_hz;
+ priv->cfg.part_type = PART_TYPE_DOS;
+ priv->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
+
+ priv->mmc.cfg = &priv->cfg;
+ priv->mmc.priv = priv;
+ priv->mmc.dev = dev;
+
+ upriv->mmc = &priv->mmc;
- debug("%s: clock %u\n", __func__, mmc->clock);
- if (mmc->clock)
- spi_set_speed(spi, mmc->clock);
return 0;
}
-static int mmc_spi_init_p(struct mmc *mmc)
+static int mmc_spi_bind(struct udevice *dev)
{
- struct spi_slave *spi = mmc->priv;
- spi_set_speed(spi, MMC_SPI_MIN_CLOCK);
- spi_claim_bus(spi);
- /* cs deactivated for 100+ clock */
- spi_xfer(spi, 18 * 8, NULL, NULL, 0);
- spi_release_bus(spi);
- return 0;
+ struct mmc_spi_priv *priv = dev_get_priv(dev);
+
+ return mmc_bind(dev, &priv->mmc, &priv->cfg);
}
-static const struct mmc_ops mmc_spi_ops = {
- .send_cmd = mmc_spi_request,
- .set_ios = mmc_spi_set_ios,
- .init = mmc_spi_init_p,
+static const struct dm_mmc_ops mmc_spi_ops = {
+ .send_cmd = dm_mmc_spi_request,
+ .set_ios = dm_mmc_spi_set_ios,
};
-static struct mmc_config mmc_spi_cfg = {
- .name = "MMC_SPI",
- .ops = &mmc_spi_ops,
- .host_caps = MMC_MODE_SPI,
- .voltages = MMC_SPI_VOLTAGE,
- .f_min = MMC_SPI_MIN_CLOCK,
- .part_type = PART_TYPE_DOS,
- .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
+static const struct udevice_id dm_mmc_spi_match[] = {
+ { .compatible = "mmc-spi-slot" },
+ { /* sentinel */ }
};
-struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode)
-{
- struct mmc *mmc;
- struct spi_slave *spi;
-
- spi = spi_setup_slave(bus, cs, speed, mode);
- if (spi == NULL)
- return NULL;
-
- mmc_spi_cfg.f_max = speed;
-
- mmc = mmc_create(&mmc_spi_cfg, spi);
- if (mmc == NULL) {
- spi_free_slave(spi);
- return NULL;
- }
- return mmc;
-}
+U_BOOT_DRIVER(mmc_spi) = {
+ .name = "mmc_spi",
+ .id = UCLASS_MMC,
+ .of_match = dm_mmc_spi_match,
+ .ops = &mmc_spi_ops,
+ .probe = mmc_spi_probe,
+ .bind = mmc_spi_bind,
+ .priv_auto_alloc_size = sizeof(struct mmc_spi_priv),
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH v2 4/5] riscv: sifive: fu540: Enable SiFive SPI and MMC SPI drivers
2019-06-29 6:56 [U-Boot] [PATCH v2 0/5] SiFive SPI MMC Support Anup Patel
` (2 preceding siblings ...)
2019-06-29 6:57 ` [U-Boot] [PATCH v2 3/5] mmc: mmc_spi: Re-write driver using DM framework Anup Patel
@ 2019-06-29 6:57 ` Anup Patel
2019-07-05 6:29 ` Bin Meng
2019-06-29 6:57 ` [U-Boot] [PATCH v2 5/5] doc: sifive-fu540: Update README for " Anup Patel
2019-07-05 15:45 ` [U-Boot] [U-Boot,v9,0/9] Update SiFive Unleashed Drivers Sagar Shrikant Kadam
5 siblings, 1 reply; 16+ messages in thread
From: Anup Patel @ 2019-06-29 6:57 UTC (permalink / raw)
To: u-boot
From: Bhargav Shah <bhargavshah1988@gmail.com>
This patch enables SiFive SPI and MMC SPI drivers for the
SiFive Unleashed board.
Signed-off-by: Bhargav Shah <bhargavshah1988@gmail.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
board/sifive/fu540/Kconfig | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
index f46437901d..d6d5c7d170 100644
--- a/board/sifive/fu540/Kconfig
+++ b/board/sifive/fu540/Kconfig
@@ -38,6 +38,14 @@ config BOARD_SPECIFIC_OPTIONS # dummy
imply PHY_LIB
imply PHY_MSCC
imply SIFIVE_SERIAL
+ imply SPI
+ imply DM_SPI
+ imply SIFIVE_SPI
+ imply MMC
+ imply DM_MMC
+ imply MMC_SPI
+ imply MMC_BROKEN_CD
+ imply CMD_MMC
imply SMP
endif
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH v2 5/5] doc: sifive-fu540: Update README for SiFive SPI and MMC SPI drivers
2019-06-29 6:56 [U-Boot] [PATCH v2 0/5] SiFive SPI MMC Support Anup Patel
` (3 preceding siblings ...)
2019-06-29 6:57 ` [U-Boot] [PATCH v2 4/5] riscv: sifive: fu540: Enable SiFive SPI and MMC SPI drivers Anup Patel
@ 2019-06-29 6:57 ` Anup Patel
2019-07-05 6:29 ` Bin Meng
2019-07-05 15:45 ` [U-Boot] [U-Boot,v9,0/9] Update SiFive Unleashed Drivers Sagar Shrikant Kadam
5 siblings, 1 reply; 16+ messages in thread
From: Anup Patel @ 2019-06-29 6:57 UTC (permalink / raw)
To: u-boot
This patch removes SiFive SPI driver and MMC SPI drive from the TODO
list in SiFive FU540 README.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
doc/README.sifive-fu540 | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/doc/README.sifive-fu540 b/doc/README.sifive-fu540
index 33e03dc861..944ba1c8a0 100644
--- a/doc/README.sifive-fu540
+++ b/doc/README.sifive-fu540
@@ -13,9 +13,7 @@ The support for following drivers are already enabled:
3. Cadence MACB ethernet driver for networking support.
TODO:
-1. SPI host driver is still missing.
-2. SPI MMC driver does not compile and needs a re-write using U-Boot DM.
-2. U-Boot expects the serial console device entry to be present under /chosen
+1. U-Boot expects the serial console device entry to be present under /chosen
DT node. Example:
chosen {
stdout-path = "/soc/serial at 10010000:115200";
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH v2 1/5] spi: Add SiFive SPI driver
2019-06-29 6:56 ` [U-Boot] [PATCH v2 1/5] spi: Add SiFive SPI driver Anup Patel
@ 2019-07-05 6:28 ` Bin Meng
2019-07-05 10:48 ` Anup Patel
0 siblings, 1 reply; 16+ messages in thread
From: Bin Meng @ 2019-07-05 6:28 UTC (permalink / raw)
To: u-boot
On Sat, Jun 29, 2019 at 2:56 PM Anup Patel <Anup.Patel@wdc.com> wrote:
>
> From: Bhargav Shah <bhargavshah1988@gmail.com>
>
> This patch adds SiFive SPI driver. The driver is 100% DM driver
> and it determines input clock using clk framework.
>
> The SiFive SPI block is found on SiFive FU540 SOC and is used to
> access flash and MMC devices on SiFive Unleashed board.
>
> This driver implementation is inspired from the Linux SiFive SPI
> driver available in Linux-5.2 or higher and SiFive FSBL sources.
>
> Signed-off-by: Bhargav Shah <bhargavshah1988@gmail.com>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
> drivers/spi/Kconfig | 8 +
> drivers/spi/Makefile | 1 +
> drivers/spi/spi-sifive.c | 405 +++++++++++++++++++++++++++++++++++++++
> 3 files changed, 414 insertions(+)
> create mode 100644 drivers/spi/spi-sifive.c
>
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index eb32f082fe..2712bad310 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -224,6 +224,14 @@ config SANDBOX_SPI
> };
> };
>
> +config SIFIVE_SPI
> + bool "SiFive SPI driver"
> + help
> + This driver supports the SiFive SPI IP. If unsure say N.
> + Enable the SiFive SPI controller driver.
> +
> + The SiFive SPI controller driver is found on various SiFive SoCs.
> +
> config SPI_SUNXI
> bool "Allwinner SoC SPI controllers"
> help
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index 8be9a4baa2..09a9d3697e 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -49,6 +49,7 @@ obj-$(CONFIG_PL022_SPI) += pl022_spi.o
> obj-$(CONFIG_RENESAS_RPC_SPI) += renesas_rpc_spi.o
> obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o
> obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
> +obj-$(CONFIG_SIFIVE_SPI) += spi-sifive.o
> obj-$(CONFIG_SPI_SUNXI) += spi-sunxi.o
> obj-$(CONFIG_SH_SPI) += sh_spi.o
> obj-$(CONFIG_SH_QSPI) += sh_qspi.o
> diff --git a/drivers/spi/spi-sifive.c b/drivers/spi/spi-sifive.c
> new file mode 100644
> index 0000000000..70eebc0463
> --- /dev/null
> +++ b/drivers/spi/spi-sifive.c
> @@ -0,0 +1,405 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2018 SiFive, Inc.
> + * Copyright 2019 Bhargav Shah <bhargavshah1988@gmail.com>
> + *
> + * SiFive SPI controller driver (master mode only)
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <malloc.h>
> +#include <spi.h>
> +#include <asm/io.h>
> +#include <linux/log2.h>
> +#include <clk.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
This is not needed.
> +
> +#define SIFIVE_SPI_MAX_CS 32
> +
> +#define SIFIVE_SPI_DEFAULT_DEPTH 8
> +#define SIFIVE_SPI_DEFAULT_BITS 8
> +
> +/* register offsets */
> +#define SIFIVE_SPI_REG_SCKDIV 0x00 /* Serial clock divisor */
> +#define SIFIVE_SPI_REG_SCKMODE 0x04 /* Serial clock mode */
> +#define SIFIVE_SPI_REG_CSID 0x10 /* Chip select ID */
> +#define SIFIVE_SPI_REG_CSDEF 0x14 /* Chip select default */
> +#define SIFIVE_SPI_REG_CSMODE 0x18 /* Chip select mode */
> +#define SIFIVE_SPI_REG_DELAY0 0x28 /* Delay control 0 */
> +#define SIFIVE_SPI_REG_DELAY1 0x2c /* Delay control 1 */
> +#define SIFIVE_SPI_REG_FMT 0x40 /* Frame format */
> +#define SIFIVE_SPI_REG_TXDATA 0x48 /* Tx FIFO data */
> +#define SIFIVE_SPI_REG_RXDATA 0x4c /* Rx FIFO data */
> +#define SIFIVE_SPI_REG_TXMARK 0x50 /* Tx FIFO watermark */
> +#define SIFIVE_SPI_REG_RXMARK 0x54 /* Rx FIFO watermark */
> +#define SIFIVE_SPI_REG_FCTRL 0x60 /* SPI flash interface control */
> +#define SIFIVE_SPI_REG_FFMT 0x64 /* SPI flash instruction format */
> +#define SIFIVE_SPI_REG_IE 0x70 /* Interrupt Enable Register */
> +#define SIFIVE_SPI_REG_IP 0x74 /* Interrupt Pendings Register */
> +
> +/* sckdiv bits */
> +#define SIFIVE_SPI_SCKDIV_DIV_MASK 0xfffU
> +
> +/* sckmode bits */
> +#define SIFIVE_SPI_SCKMODE_PHA BIT(0)
> +#define SIFIVE_SPI_SCKMODE_POL BIT(1)
> +#define SIFIVE_SPI_SCKMODE_MODE_MASK (SIFIVE_SPI_SCKMODE_PHA | \
> + SIFIVE_SPI_SCKMODE_POL)
> +
> +/* csmode bits */
> +#define SIFIVE_SPI_CSMODE_MODE_AUTO 0U
> +#define SIFIVE_SPI_CSMODE_MODE_HOLD 2U
> +#define SIFIVE_SPI_CSMODE_MODE_OFF 3U
> +
> +/* delay0 bits */
> +#define SIFIVE_SPI_DELAY0_CSSCK(x) ((u32)(x))
> +#define SIFIVE_SPI_DELAY0_CSSCK_MASK 0xffU
> +#define SIFIVE_SPI_DELAY0_SCKCS(x) ((u32)(x) << 16)
> +#define SIFIVE_SPI_DELAY0_SCKCS_MASK (0xffU << 16)
> +
> +/* delay1 bits */
> +#define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x))
> +#define SIFIVE_SPI_DELAY1_INTERCS_MASK 0xffU
> +#define SIFIVE_SPI_DELAY1_INTERXFR(x) ((u32)(x) << 16)
> +#define SIFIVE_SPI_DELAY1_INTERXFR_MASK (0xffU << 16)
> +
> +/* fmt bits */
> +#define SIFIVE_SPI_FMT_PROTO_SINGLE 0U
> +#define SIFIVE_SPI_FMT_PROTO_DUAL 1U
> +#define SIFIVE_SPI_FMT_PROTO_QUAD 2U
> +#define SIFIVE_SPI_FMT_PROTO_MASK 3U
> +#define SIFIVE_SPI_FMT_ENDIAN BIT(2)
> +#define SIFIVE_SPI_FMT_DIR BIT(3)
> +#define SIFIVE_SPI_FMT_LEN(x) ((u32)(x) << 16)
> +#define SIFIVE_SPI_FMT_LEN_MASK (0xfU << 16)
> +
> +/* txdata bits */
> +#define SIFIVE_SPI_TXDATA_DATA_MASK 0xffU
> +#define SIFIVE_SPI_TXDATA_FULL BIT(31)
> +
> +/* rxdata bits */
> +#define SIFIVE_SPI_RXDATA_DATA_MASK 0xffU
> +#define SIFIVE_SPI_RXDATA_EMPTY BIT(31)
> +
> +/* ie and ip bits */
> +#define SIFIVE_SPI_IP_TXWM BIT(0)
> +#define SIFIVE_SPI_IP_RXWM BIT(1)
> +
> +struct sifive_spi {
> + void *regs; /* base address of the registers */
> + u32 fifo_depth;
> + u32 bits_per_word;
> + u32 cs_inactive; /* Level of the CS pins when inactive*/
> + u32 freq;
> + u32 num_cs;
> +};
> +
> +static void sifive_spi_write(struct sifive_spi *spi, int offset, u32 value)
> +{
> + writel(value, spi->regs + offset);
> +}
> +
> +static u32 sifive_spi_read(struct sifive_spi *spi, int offset)
> +{
> + return readl(spi->regs + offset);
> +}
> +
> +static void sifive_spi_prep_device(struct sifive_spi *spi,
> + struct dm_spi_slave_platdata *slave)
> +{
> + /* Update the chip select polarity */
> + if (slave->mode & SPI_CS_HIGH)
> + spi->cs_inactive &= ~BIT(slave->cs);
> + else
> + spi->cs_inactive |= BIT(slave->cs);
> + sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, spi->cs_inactive);
> +
> + /* Select the correct device */
> + sifive_spi_write(spi, SIFIVE_SPI_REG_CSID, slave->cs);
> +}
> +
> +static int sifive_spi_set_cs(struct sifive_spi *spi,
> + struct dm_spi_slave_platdata *slave)
> +{
> + u32 cs_mode = SIFIVE_SPI_CSMODE_MODE_HOLD;
> +
> + if (slave->cs > spi->num_cs)
> + return -EINVAL;
> +
> + if (slave->mode & SPI_CS_HIGH)
> + cs_mode = SIFIVE_SPI_CSMODE_MODE_AUTO;
> +
> + sifive_spi_write(spi, SIFIVE_SPI_REG_CSMODE, cs_mode);
> +
> + return 0;
> +}
> +
> +static void sifive_spi_clear_cs(struct sifive_spi *spi)
> +{
> + sifive_spi_write(spi, SIFIVE_SPI_REG_CSMODE,
> + SIFIVE_SPI_CSMODE_MODE_AUTO);
> +}
> +
> +static void sifive_spi_prep_transfer(struct sifive_spi *spi,
> + bool is_rx_xfer,
> + struct dm_spi_slave_platdata *slave)
> +{
> + u32 cr;
> +
> + /* Modify the SPI protocol mode */
> + cr = sifive_spi_read(spi, SIFIVE_SPI_REG_FMT);
> +
> + /* Bits per word ? */
> + cr &= ~SIFIVE_SPI_FMT_LEN_MASK;
> + cr |= SIFIVE_SPI_FMT_LEN(SIFIVE_SPI_DEFAULT_BITS);
This should be: cr |= SIFIVE_SPI_FMT_LEN(spi->bits_per_word);
> +
> + /* LSB first? */
> + cr &= ~SIFIVE_SPI_FMT_ENDIAN;
> + if (slave->mode & SPI_LSB_FIRST)
> + cr |= SIFIVE_SPI_FMT_ENDIAN;
> +
> + /* Number of wires ? */
> + cr &= ~SIFIVE_SPI_FMT_PROTO_MASK;
> + if ((slave->mode & SPI_TX_QUAD) || (slave->mode & SPI_RX_QUAD))
> + cr |= SIFIVE_SPI_FMT_PROTO_QUAD;
> + else if ((slave->mode & SPI_TX_DUAL) || (slave->mode & SPI_RX_DUAL))
> + cr |= SIFIVE_SPI_FMT_PROTO_DUAL;
> + else
> + cr |= SIFIVE_SPI_FMT_PROTO_SINGLE;
> +
> + /* SPI direction in/out ? */
> + cr &= ~SIFIVE_SPI_FMT_DIR;
> + if (!is_rx_xfer)
> + cr |= SIFIVE_SPI_FMT_DIR;
> +
> + sifive_spi_write(spi, SIFIVE_SPI_REG_FMT, cr);
> +}
> +
> +static void sifive_spi_rx(struct sifive_spi *spi, u8 *rx_ptr)
> +{
> + u32 data;
> +
> + do {
> + data = sifive_spi_read(spi, SIFIVE_SPI_REG_RXDATA);
> + } while (data & SIFIVE_SPI_RXDATA_EMPTY);
> +
> + if (rx_ptr)
> + *rx_ptr = data & SIFIVE_SPI_RXDATA_DATA_MASK;
> +}
> +
> +static void sifive_spi_tx(struct sifive_spi *spi, const u8 *tx_ptr)
> +{
> + u32 data;
> + u8 tx_data = (tx_ptr) ? *tx_ptr & SIFIVE_SPI_TXDATA_DATA_MASK :
> + SIFIVE_SPI_TXDATA_DATA_MASK;
> +
> + do {
> + data = sifive_spi_read(spi, SIFIVE_SPI_REG_TXDATA);
> + } while (data & SIFIVE_SPI_TXDATA_FULL);
> +
> + sifive_spi_write(spi, SIFIVE_SPI_REG_TXDATA, tx_data);
> +}
> +
> +static u8 sifive_spi_txrx(struct sifive_spi *spi, const u8 *tx_ptr)
> +{
> + u8 rx = 0;
> +
> + sifive_spi_tx(spi, tx_ptr);
> + sifive_spi_rx(spi, &rx);
> +
> + return rx;
> +}
> +
> +static int sifive_spi_claim_bus(struct udevice *dev)
> +{
> + int ret;
> + struct udevice *bus = dev->parent;
> + struct sifive_spi *spi = dev_get_priv(bus);
> + struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
> +
> + sifive_spi_prep_device(spi, slave);
> +
> + ret = sifive_spi_set_cs(spi, slave);
> + if (ret)
> + return ret;
> +
> + return 0;
> +}
> +
> +static int sifive_spi_release_bus(struct udevice *dev)
> +{
> + struct sifive_spi *spi = dev_get_priv(dev->parent);
> +
> + sifive_spi_clear_cs(spi);
> +
> + return 0;
> +}
> +
> +static int sifive_spi_xfer(struct udevice *dev, unsigned int bitlen,
> + const void *dout, void *din, unsigned long flags)
> +{
> + struct udevice *bus = dev->parent;
> + struct sifive_spi *spi = dev_get_priv(bus);
> + struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
> + const unsigned char *tx_ptr = dout;
> + unsigned char *rx_ptr = din;
> + u32 remaining_len;
> +
> + sifive_spi_prep_transfer(spi, true, slave);
> +
> + remaining_len = bitlen / 8;
> +
> + while (remaining_len) {
> + int n_words, tx_words, rx_words;
> +
> + n_words = min(remaining_len, spi->fifo_depth);
> +
> + /* Enqueue n_words for transmission */
> + if (tx_ptr) {
> + for (tx_words = 0; tx_words < n_words; ++tx_words) {
> + sifive_spi_txrx(spi, tx_ptr);
> + tx_ptr++;
> + }
> + }
> +
> + /* Read out all the data from the RX FIFO */
> + if (rx_ptr) {
> + for (rx_words = 0; rx_words < n_words; ++rx_words) {
> + *rx_ptr = sifive_spi_txrx(spi, NULL);
> + rx_ptr++;
> + }
> + }
> +
> + remaining_len -= n_words;
> + }
> +
> + return 0;
> +}
> +
> +static int sifive_spi_set_speed(struct udevice *bus, uint speed)
> +{
> + struct sifive_spi *spi = dev_get_priv(bus);
> + u32 scale;
> +
> + if (speed > spi->freq)
> + speed = spi->freq;
> +
> + /* Cofigure max speed */
> + scale = (DIV_ROUND_UP(spi->freq >> 1, speed) - 1)
> + & SIFIVE_SPI_SCKDIV_DIV_MASK;
> + sifive_spi_write(spi, SIFIVE_SPI_REG_SCKDIV, scale);
> + return 0;
> +}
> +
> +static int sifive_spi_set_mode(struct udevice *bus, uint mode)
> +{
> + struct sifive_spi *spi = dev_get_priv(bus);
> + u32 cr;
> +
> + /* Switch clock mode bits */
> + cr = sifive_spi_read(spi, SIFIVE_SPI_REG_SCKMODE) &
> + ~SIFIVE_SPI_SCKMODE_MODE_MASK;
> + if (mode & SPI_CPHA)
> + cr |= SIFIVE_SPI_SCKMODE_PHA;
> + if (mode & SPI_CPOL)
> + cr |= SIFIVE_SPI_SCKMODE_POL;
> +
> + sifive_spi_write(spi, SIFIVE_SPI_REG_SCKMODE, cr);
> +
> + return 0;
> +}
> +
> +static int sifive_cs_info(struct udevice *bus, uint cs,
For consistency, this function should be named as: sifive_spi_cs_info()
> + struct spi_cs_info *info)
> +{
> + return 0;
> +}
> +
Other than above, the driver looks pretty good.
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Regards,
Bin
^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH v2 2/5] mmc: skip select_mode_and_width for MMC SPI host
2019-06-29 6:56 ` [U-Boot] [PATCH v2 2/5] mmc: skip select_mode_and_width for MMC SPI host Anup Patel
@ 2019-07-05 6:28 ` Bin Meng
0 siblings, 0 replies; 16+ messages in thread
From: Bin Meng @ 2019-07-05 6:28 UTC (permalink / raw)
To: u-boot
On Sat, Jun 29, 2019 at 2:57 PM Anup Patel <Anup.Patel@wdc.com> wrote:
>
> The MMC mode and width are fixed for MMC SPI host hence we skip
> sd_select_mode_and_width() and mmc_select_mode_and_width() for
> MMC SPI host.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
> drivers/mmc/mmc.c | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH v2 3/5] mmc: mmc_spi: Re-write driver using DM framework
2019-06-29 6:57 ` [U-Boot] [PATCH v2 3/5] mmc: mmc_spi: Re-write driver using DM framework Anup Patel
@ 2019-07-05 6:28 ` Bin Meng
2019-07-05 10:53 ` Anup Patel
0 siblings, 1 reply; 16+ messages in thread
From: Bin Meng @ 2019-07-05 6:28 UTC (permalink / raw)
To: u-boot
On Sat, Jun 29, 2019 at 2:57 PM Anup Patel <Anup.Patel@wdc.com> wrote:
>
> From: Bhargav Shah <bhargavshah1988@gmail.com>
>
> This patch rewrites MMC SPI driver using U-Boot DM
> framework and get it's working on SiFive Unleashed
> board.
>
> Signed-off-by: Bhargav Shah <bhargavshah1988@gmail.com>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
> drivers/mmc/Kconfig | 18 ++
> drivers/mmc/mmc_spi.c | 469 +++++++++++++++++++++++++++---------------
> 2 files changed, 320 insertions(+), 167 deletions(-)
>
> diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
> index c23299ea96..f750dad00a 100644
> --- a/drivers/mmc/Kconfig
> +++ b/drivers/mmc/Kconfig
> @@ -46,6 +46,24 @@ config SPL_DM_MMC
>
> if MMC
>
> +config MMC_SPI
> + bool "Support for SPI-based MMC controller"
> + depends on DM_MMC && DM_SPI
> + help
> + This selects SPI-based MMC controllers.
> + If you have an MMC controller on a SPI bus, say Y here.
> +
> + If unsure, say N.
> +
> +config MMC_SPI_CRC_ON
> + bool "Support CRC for SPI-based MMC controller"
> + depends on MMC_SPI
> + default y
> + help
> + This enables CRC for SPI-based MMC controllers.
> +
> + If unsure, say N.
> +
scripts/config_whitelist.txt should be updated to remove the non-DM
version macros: CONFIG_MMC_SPI_xxx
cmd/mmc_spi.c should be completely dropped as it is for non-DM version
MMC SPI driver.
mmc_spi_init() declaration in mmc.h should be removed.
With commit: f51d7fc8ce455ef201f86e1fab4d380444b96789 ("board:
Arcturus: DM: Disable drivers without DM support"), UCP1020 board
removes most legacy non-DM SPI MMC support, but still has
CONFIG_MMC_SPI in UCP1020.h. That should be removed too.
+Oleksandr Zhadan and Michael Durrant who maintains UCP1020 board for
the awareness.
[snip]
Other than above,
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Regards,
Bin
^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH v2 4/5] riscv: sifive: fu540: Enable SiFive SPI and MMC SPI drivers
2019-06-29 6:57 ` [U-Boot] [PATCH v2 4/5] riscv: sifive: fu540: Enable SiFive SPI and MMC SPI drivers Anup Patel
@ 2019-07-05 6:29 ` Bin Meng
2019-07-05 6:51 ` Bin Meng
0 siblings, 1 reply; 16+ messages in thread
From: Bin Meng @ 2019-07-05 6:29 UTC (permalink / raw)
To: u-boot
On Sat, Jun 29, 2019 at 2:57 PM Anup Patel <Anup.Patel@wdc.com> wrote:
>
> From: Bhargav Shah <bhargavshah1988@gmail.com>
>
> This patch enables SiFive SPI and MMC SPI drivers for the
> SiFive Unleashed board.
>
> Signed-off-by: Bhargav Shah <bhargavshah1988@gmail.com>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
> board/sifive/fu540/Kconfig | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH v2 5/5] doc: sifive-fu540: Update README for SiFive SPI and MMC SPI drivers
2019-06-29 6:57 ` [U-Boot] [PATCH v2 5/5] doc: sifive-fu540: Update README for " Anup Patel
@ 2019-07-05 6:29 ` Bin Meng
0 siblings, 0 replies; 16+ messages in thread
From: Bin Meng @ 2019-07-05 6:29 UTC (permalink / raw)
To: u-boot
On Sat, Jun 29, 2019 at 2:57 PM Anup Patel <Anup.Patel@wdc.com> wrote:
>
> This patch removes SiFive SPI driver and MMC SPI drive from the TODO
> list in SiFive FU540 README.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
> doc/README.sifive-fu540 | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH v2 4/5] riscv: sifive: fu540: Enable SiFive SPI and MMC SPI drivers
2019-07-05 6:29 ` Bin Meng
@ 2019-07-05 6:51 ` Bin Meng
2019-07-05 10:54 ` Anup Patel
0 siblings, 1 reply; 16+ messages in thread
From: Bin Meng @ 2019-07-05 6:51 UTC (permalink / raw)
To: u-boot
On Fri, Jul 5, 2019 at 2:29 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Sat, Jun 29, 2019 at 2:57 PM Anup Patel <Anup.Patel@wdc.com> wrote:
> >
> > From: Bhargav Shah <bhargavshah1988@gmail.com>
> >
> > This patch enables SiFive SPI and MMC SPI drivers for the
> > SiFive Unleashed board.
> >
> > Signed-off-by: Bhargav Shah <bhargavshah1988@gmail.com>
> > Signed-off-by: Anup Patel <anup.patel@wdc.com>
> > ---
> > board/sifive/fu540/Kconfig | 8 ++++++++
> > 1 file changed, 8 insertions(+)
> >
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> Tested-by: Bin Meng <bmeng.cn@gmail.com>
Ah, I just noticed that DM_SPI and DM_MMC is already turned on
arch/Kconfig for RISC-V. Please remove these 2.
Regards,
Bin
^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH v2 1/5] spi: Add SiFive SPI driver
2019-07-05 6:28 ` Bin Meng
@ 2019-07-05 10:48 ` Anup Patel
0 siblings, 0 replies; 16+ messages in thread
From: Anup Patel @ 2019-07-05 10:48 UTC (permalink / raw)
To: u-boot
On Fri, Jul 5, 2019 at 11:58 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Sat, Jun 29, 2019 at 2:56 PM Anup Patel <Anup.Patel@wdc.com> wrote:
> >
> > From: Bhargav Shah <bhargavshah1988@gmail.com>
> >
> > This patch adds SiFive SPI driver. The driver is 100% DM driver
> > and it determines input clock using clk framework.
> >
> > The SiFive SPI block is found on SiFive FU540 SOC and is used to
> > access flash and MMC devices on SiFive Unleashed board.
> >
> > This driver implementation is inspired from the Linux SiFive SPI
> > driver available in Linux-5.2 or higher and SiFive FSBL sources.
> >
> > Signed-off-by: Bhargav Shah <bhargavshah1988@gmail.com>
> > Signed-off-by: Anup Patel <anup.patel@wdc.com>
> > ---
> > drivers/spi/Kconfig | 8 +
> > drivers/spi/Makefile | 1 +
> > drivers/spi/spi-sifive.c | 405 +++++++++++++++++++++++++++++++++++++++
> > 3 files changed, 414 insertions(+)
> > create mode 100644 drivers/spi/spi-sifive.c
> >
> > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> > index eb32f082fe..2712bad310 100644
> > --- a/drivers/spi/Kconfig
> > +++ b/drivers/spi/Kconfig
> > @@ -224,6 +224,14 @@ config SANDBOX_SPI
> > };
> > };
> >
> > +config SIFIVE_SPI
> > + bool "SiFive SPI driver"
> > + help
> > + This driver supports the SiFive SPI IP. If unsure say N.
> > + Enable the SiFive SPI controller driver.
> > +
> > + The SiFive SPI controller driver is found on various SiFive SoCs.
> > +
> > config SPI_SUNXI
> > bool "Allwinner SoC SPI controllers"
> > help
> > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> > index 8be9a4baa2..09a9d3697e 100644
> > --- a/drivers/spi/Makefile
> > +++ b/drivers/spi/Makefile
> > @@ -49,6 +49,7 @@ obj-$(CONFIG_PL022_SPI) += pl022_spi.o
> > obj-$(CONFIG_RENESAS_RPC_SPI) += renesas_rpc_spi.o
> > obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o
> > obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
> > +obj-$(CONFIG_SIFIVE_SPI) += spi-sifive.o
> > obj-$(CONFIG_SPI_SUNXI) += spi-sunxi.o
> > obj-$(CONFIG_SH_SPI) += sh_spi.o
> > obj-$(CONFIG_SH_QSPI) += sh_qspi.o
> > diff --git a/drivers/spi/spi-sifive.c b/drivers/spi/spi-sifive.c
> > new file mode 100644
> > index 0000000000..70eebc0463
> > --- /dev/null
> > +++ b/drivers/spi/spi-sifive.c
> > @@ -0,0 +1,405 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2018 SiFive, Inc.
> > + * Copyright 2019 Bhargav Shah <bhargavshah1988@gmail.com>
> > + *
> > + * SiFive SPI controller driver (master mode only)
> > + */
> > +
> > +#include <common.h>
> > +#include <dm.h>
> > +#include <malloc.h>
> > +#include <spi.h>
> > +#include <asm/io.h>
> > +#include <linux/log2.h>
> > +#include <clk.h>
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
>
> This is not needed.
Okay, I will drop it.
>
> > +
> > +#define SIFIVE_SPI_MAX_CS 32
> > +
> > +#define SIFIVE_SPI_DEFAULT_DEPTH 8
> > +#define SIFIVE_SPI_DEFAULT_BITS 8
> > +
> > +/* register offsets */
> > +#define SIFIVE_SPI_REG_SCKDIV 0x00 /* Serial clock divisor */
> > +#define SIFIVE_SPI_REG_SCKMODE 0x04 /* Serial clock mode */
> > +#define SIFIVE_SPI_REG_CSID 0x10 /* Chip select ID */
> > +#define SIFIVE_SPI_REG_CSDEF 0x14 /* Chip select default */
> > +#define SIFIVE_SPI_REG_CSMODE 0x18 /* Chip select mode */
> > +#define SIFIVE_SPI_REG_DELAY0 0x28 /* Delay control 0 */
> > +#define SIFIVE_SPI_REG_DELAY1 0x2c /* Delay control 1 */
> > +#define SIFIVE_SPI_REG_FMT 0x40 /* Frame format */
> > +#define SIFIVE_SPI_REG_TXDATA 0x48 /* Tx FIFO data */
> > +#define SIFIVE_SPI_REG_RXDATA 0x4c /* Rx FIFO data */
> > +#define SIFIVE_SPI_REG_TXMARK 0x50 /* Tx FIFO watermark */
> > +#define SIFIVE_SPI_REG_RXMARK 0x54 /* Rx FIFO watermark */
> > +#define SIFIVE_SPI_REG_FCTRL 0x60 /* SPI flash interface control */
> > +#define SIFIVE_SPI_REG_FFMT 0x64 /* SPI flash instruction format */
> > +#define SIFIVE_SPI_REG_IE 0x70 /* Interrupt Enable Register */
> > +#define SIFIVE_SPI_REG_IP 0x74 /* Interrupt Pendings Register */
> > +
> > +/* sckdiv bits */
> > +#define SIFIVE_SPI_SCKDIV_DIV_MASK 0xfffU
> > +
> > +/* sckmode bits */
> > +#define SIFIVE_SPI_SCKMODE_PHA BIT(0)
> > +#define SIFIVE_SPI_SCKMODE_POL BIT(1)
> > +#define SIFIVE_SPI_SCKMODE_MODE_MASK (SIFIVE_SPI_SCKMODE_PHA | \
> > + SIFIVE_SPI_SCKMODE_POL)
> > +
> > +/* csmode bits */
> > +#define SIFIVE_SPI_CSMODE_MODE_AUTO 0U
> > +#define SIFIVE_SPI_CSMODE_MODE_HOLD 2U
> > +#define SIFIVE_SPI_CSMODE_MODE_OFF 3U
> > +
> > +/* delay0 bits */
> > +#define SIFIVE_SPI_DELAY0_CSSCK(x) ((u32)(x))
> > +#define SIFIVE_SPI_DELAY0_CSSCK_MASK 0xffU
> > +#define SIFIVE_SPI_DELAY0_SCKCS(x) ((u32)(x) << 16)
> > +#define SIFIVE_SPI_DELAY0_SCKCS_MASK (0xffU << 16)
> > +
> > +/* delay1 bits */
> > +#define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x))
> > +#define SIFIVE_SPI_DELAY1_INTERCS_MASK 0xffU
> > +#define SIFIVE_SPI_DELAY1_INTERXFR(x) ((u32)(x) << 16)
> > +#define SIFIVE_SPI_DELAY1_INTERXFR_MASK (0xffU << 16)
> > +
> > +/* fmt bits */
> > +#define SIFIVE_SPI_FMT_PROTO_SINGLE 0U
> > +#define SIFIVE_SPI_FMT_PROTO_DUAL 1U
> > +#define SIFIVE_SPI_FMT_PROTO_QUAD 2U
> > +#define SIFIVE_SPI_FMT_PROTO_MASK 3U
> > +#define SIFIVE_SPI_FMT_ENDIAN BIT(2)
> > +#define SIFIVE_SPI_FMT_DIR BIT(3)
> > +#define SIFIVE_SPI_FMT_LEN(x) ((u32)(x) << 16)
> > +#define SIFIVE_SPI_FMT_LEN_MASK (0xfU << 16)
> > +
> > +/* txdata bits */
> > +#define SIFIVE_SPI_TXDATA_DATA_MASK 0xffU
> > +#define SIFIVE_SPI_TXDATA_FULL BIT(31)
> > +
> > +/* rxdata bits */
> > +#define SIFIVE_SPI_RXDATA_DATA_MASK 0xffU
> > +#define SIFIVE_SPI_RXDATA_EMPTY BIT(31)
> > +
> > +/* ie and ip bits */
> > +#define SIFIVE_SPI_IP_TXWM BIT(0)
> > +#define SIFIVE_SPI_IP_RXWM BIT(1)
> > +
> > +struct sifive_spi {
> > + void *regs; /* base address of the registers */
> > + u32 fifo_depth;
> > + u32 bits_per_word;
> > + u32 cs_inactive; /* Level of the CS pins when inactive*/
> > + u32 freq;
> > + u32 num_cs;
> > +};
> > +
> > +static void sifive_spi_write(struct sifive_spi *spi, int offset, u32 value)
> > +{
> > + writel(value, spi->regs + offset);
> > +}
> > +
> > +static u32 sifive_spi_read(struct sifive_spi *spi, int offset)
> > +{
> > + return readl(spi->regs + offset);
> > +}
> > +
> > +static void sifive_spi_prep_device(struct sifive_spi *spi,
> > + struct dm_spi_slave_platdata *slave)
> > +{
> > + /* Update the chip select polarity */
> > + if (slave->mode & SPI_CS_HIGH)
> > + spi->cs_inactive &= ~BIT(slave->cs);
> > + else
> > + spi->cs_inactive |= BIT(slave->cs);
> > + sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, spi->cs_inactive);
> > +
> > + /* Select the correct device */
> > + sifive_spi_write(spi, SIFIVE_SPI_REG_CSID, slave->cs);
> > +}
> > +
> > +static int sifive_spi_set_cs(struct sifive_spi *spi,
> > + struct dm_spi_slave_platdata *slave)
> > +{
> > + u32 cs_mode = SIFIVE_SPI_CSMODE_MODE_HOLD;
> > +
> > + if (slave->cs > spi->num_cs)
> > + return -EINVAL;
> > +
> > + if (slave->mode & SPI_CS_HIGH)
> > + cs_mode = SIFIVE_SPI_CSMODE_MODE_AUTO;
> > +
> > + sifive_spi_write(spi, SIFIVE_SPI_REG_CSMODE, cs_mode);
> > +
> > + return 0;
> > +}
> > +
> > +static void sifive_spi_clear_cs(struct sifive_spi *spi)
> > +{
> > + sifive_spi_write(spi, SIFIVE_SPI_REG_CSMODE,
> > + SIFIVE_SPI_CSMODE_MODE_AUTO);
> > +}
> > +
> > +static void sifive_spi_prep_transfer(struct sifive_spi *spi,
> > + bool is_rx_xfer,
> > + struct dm_spi_slave_platdata *slave)
> > +{
> > + u32 cr;
> > +
> > + /* Modify the SPI protocol mode */
> > + cr = sifive_spi_read(spi, SIFIVE_SPI_REG_FMT);
> > +
> > + /* Bits per word ? */
> > + cr &= ~SIFIVE_SPI_FMT_LEN_MASK;
> > + cr |= SIFIVE_SPI_FMT_LEN(SIFIVE_SPI_DEFAULT_BITS);
>
> This should be: cr |= SIFIVE_SPI_FMT_LEN(spi->bits_per_word);
Ahh, I missed this one. Thanks for catching. I will update.
>
> > +
> > + /* LSB first? */
> > + cr &= ~SIFIVE_SPI_FMT_ENDIAN;
> > + if (slave->mode & SPI_LSB_FIRST)
> > + cr |= SIFIVE_SPI_FMT_ENDIAN;
> > +
> > + /* Number of wires ? */
> > + cr &= ~SIFIVE_SPI_FMT_PROTO_MASK;
> > + if ((slave->mode & SPI_TX_QUAD) || (slave->mode & SPI_RX_QUAD))
> > + cr |= SIFIVE_SPI_FMT_PROTO_QUAD;
> > + else if ((slave->mode & SPI_TX_DUAL) || (slave->mode & SPI_RX_DUAL))
> > + cr |= SIFIVE_SPI_FMT_PROTO_DUAL;
> > + else
> > + cr |= SIFIVE_SPI_FMT_PROTO_SINGLE;
> > +
> > + /* SPI direction in/out ? */
> > + cr &= ~SIFIVE_SPI_FMT_DIR;
> > + if (!is_rx_xfer)
> > + cr |= SIFIVE_SPI_FMT_DIR;
> > +
> > + sifive_spi_write(spi, SIFIVE_SPI_REG_FMT, cr);
> > +}
> > +
> > +static void sifive_spi_rx(struct sifive_spi *spi, u8 *rx_ptr)
> > +{
> > + u32 data;
> > +
> > + do {
> > + data = sifive_spi_read(spi, SIFIVE_SPI_REG_RXDATA);
> > + } while (data & SIFIVE_SPI_RXDATA_EMPTY);
> > +
> > + if (rx_ptr)
> > + *rx_ptr = data & SIFIVE_SPI_RXDATA_DATA_MASK;
> > +}
> > +
> > +static void sifive_spi_tx(struct sifive_spi *spi, const u8 *tx_ptr)
> > +{
> > + u32 data;
> > + u8 tx_data = (tx_ptr) ? *tx_ptr & SIFIVE_SPI_TXDATA_DATA_MASK :
> > + SIFIVE_SPI_TXDATA_DATA_MASK;
> > +
> > + do {
> > + data = sifive_spi_read(spi, SIFIVE_SPI_REG_TXDATA);
> > + } while (data & SIFIVE_SPI_TXDATA_FULL);
> > +
> > + sifive_spi_write(spi, SIFIVE_SPI_REG_TXDATA, tx_data);
> > +}
> > +
> > +static u8 sifive_spi_txrx(struct sifive_spi *spi, const u8 *tx_ptr)
> > +{
> > + u8 rx = 0;
> > +
> > + sifive_spi_tx(spi, tx_ptr);
> > + sifive_spi_rx(spi, &rx);
> > +
> > + return rx;
> > +}
> > +
> > +static int sifive_spi_claim_bus(struct udevice *dev)
> > +{
> > + int ret;
> > + struct udevice *bus = dev->parent;
> > + struct sifive_spi *spi = dev_get_priv(bus);
> > + struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
> > +
> > + sifive_spi_prep_device(spi, slave);
> > +
> > + ret = sifive_spi_set_cs(spi, slave);
> > + if (ret)
> > + return ret;
> > +
> > + return 0;
> > +}
> > +
> > +static int sifive_spi_release_bus(struct udevice *dev)
> > +{
> > + struct sifive_spi *spi = dev_get_priv(dev->parent);
> > +
> > + sifive_spi_clear_cs(spi);
> > +
> > + return 0;
> > +}
> > +
> > +static int sifive_spi_xfer(struct udevice *dev, unsigned int bitlen,
> > + const void *dout, void *din, unsigned long flags)
> > +{
> > + struct udevice *bus = dev->parent;
> > + struct sifive_spi *spi = dev_get_priv(bus);
> > + struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
> > + const unsigned char *tx_ptr = dout;
> > + unsigned char *rx_ptr = din;
> > + u32 remaining_len;
> > +
> > + sifive_spi_prep_transfer(spi, true, slave);
> > +
> > + remaining_len = bitlen / 8;
> > +
> > + while (remaining_len) {
> > + int n_words, tx_words, rx_words;
> > +
> > + n_words = min(remaining_len, spi->fifo_depth);
> > +
> > + /* Enqueue n_words for transmission */
> > + if (tx_ptr) {
> > + for (tx_words = 0; tx_words < n_words; ++tx_words) {
> > + sifive_spi_txrx(spi, tx_ptr);
> > + tx_ptr++;
> > + }
> > + }
> > +
> > + /* Read out all the data from the RX FIFO */
> > + if (rx_ptr) {
> > + for (rx_words = 0; rx_words < n_words; ++rx_words) {
> > + *rx_ptr = sifive_spi_txrx(spi, NULL);
> > + rx_ptr++;
> > + }
> > + }
> > +
> > + remaining_len -= n_words;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int sifive_spi_set_speed(struct udevice *bus, uint speed)
> > +{
> > + struct sifive_spi *spi = dev_get_priv(bus);
> > + u32 scale;
> > +
> > + if (speed > spi->freq)
> > + speed = spi->freq;
> > +
> > + /* Cofigure max speed */
> > + scale = (DIV_ROUND_UP(spi->freq >> 1, speed) - 1)
> > + & SIFIVE_SPI_SCKDIV_DIV_MASK;
> > + sifive_spi_write(spi, SIFIVE_SPI_REG_SCKDIV, scale);
> > + return 0;
> > +}
> > +
> > +static int sifive_spi_set_mode(struct udevice *bus, uint mode)
> > +{
> > + struct sifive_spi *spi = dev_get_priv(bus);
> > + u32 cr;
> > +
> > + /* Switch clock mode bits */
> > + cr = sifive_spi_read(spi, SIFIVE_SPI_REG_SCKMODE) &
> > + ~SIFIVE_SPI_SCKMODE_MODE_MASK;
> > + if (mode & SPI_CPHA)
> > + cr |= SIFIVE_SPI_SCKMODE_PHA;
> > + if (mode & SPI_CPOL)
> > + cr |= SIFIVE_SPI_SCKMODE_POL;
> > +
> > + sifive_spi_write(spi, SIFIVE_SPI_REG_SCKMODE, cr);
> > +
> > + return 0;
> > +}
> > +
> > +static int sifive_cs_info(struct udevice *bus, uint cs,
>
> For consistency, this function should be named as: sifive_spi_cs_info()
Sure, I will rename it.
>
> > + struct spi_cs_info *info)
> > +{
> > + return 0;
> > +}
> > +
>
> Other than above, the driver looks pretty good.
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> Tested-by: Bin Meng <bmeng.cn@gmail.com>
>
> Regards,
> Bin
Thanks,
Anup
^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH v2 3/5] mmc: mmc_spi: Re-write driver using DM framework
2019-07-05 6:28 ` Bin Meng
@ 2019-07-05 10:53 ` Anup Patel
0 siblings, 0 replies; 16+ messages in thread
From: Anup Patel @ 2019-07-05 10:53 UTC (permalink / raw)
To: u-boot
On Fri, Jul 5, 2019 at 11:59 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Sat, Jun 29, 2019 at 2:57 PM Anup Patel <Anup.Patel@wdc.com> wrote:
> >
> > From: Bhargav Shah <bhargavshah1988@gmail.com>
> >
> > This patch rewrites MMC SPI driver using U-Boot DM
> > framework and get it's working on SiFive Unleashed
> > board.
> >
> > Signed-off-by: Bhargav Shah <bhargavshah1988@gmail.com>
> > Signed-off-by: Anup Patel <anup.patel@wdc.com>
> > ---
> > drivers/mmc/Kconfig | 18 ++
> > drivers/mmc/mmc_spi.c | 469 +++++++++++++++++++++++++++---------------
> > 2 files changed, 320 insertions(+), 167 deletions(-)
> >
> > diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
> > index c23299ea96..f750dad00a 100644
> > --- a/drivers/mmc/Kconfig
> > +++ b/drivers/mmc/Kconfig
> > @@ -46,6 +46,24 @@ config SPL_DM_MMC
> >
> > if MMC
> >
> > +config MMC_SPI
> > + bool "Support for SPI-based MMC controller"
> > + depends on DM_MMC && DM_SPI
> > + help
> > + This selects SPI-based MMC controllers.
> > + If you have an MMC controller on a SPI bus, say Y here.
> > +
> > + If unsure, say N.
> > +
> > +config MMC_SPI_CRC_ON
> > + bool "Support CRC for SPI-based MMC controller"
> > + depends on MMC_SPI
> > + default y
> > + help
> > + This enables CRC for SPI-based MMC controllers.
> > +
> > + If unsure, say N.
> > +
>
> scripts/config_whitelist.txt should be updated to remove the non-DM
> version macros: CONFIG_MMC_SPI_xxx
Okay, I will update.
>
> cmd/mmc_spi.c should be completely dropped as it is for non-DM version
> MMC SPI driver.
>
> mmc_spi_init() declaration in mmc.h should be removed.
Okay, I will drop cmd/mmc_spi.c and also remove mmc_spi_init() from
mmc.h as a separate patch.
>
> With commit: f51d7fc8ce455ef201f86e1fab4d380444b96789 ("board:
> Arcturus: DM: Disable drivers without DM support"), UCP1020 board
> removes most legacy non-DM SPI MMC support, but still has
> CONFIG_MMC_SPI in UCP1020.h. That should be removed too.
> +Oleksandr Zhadan and Michael Durrant who maintains UCP1020 board for
> the awareness.
Okay, I will remove CONFIG_MMC_SPI from UCP1020.h
>
> [snip]
>
> Other than above,
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> Tested-by: Bin Meng <bmeng.cn@gmail.com>
>
> Regards,
> Bin
Thanks,
Anup
^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH v2 4/5] riscv: sifive: fu540: Enable SiFive SPI and MMC SPI drivers
2019-07-05 6:51 ` Bin Meng
@ 2019-07-05 10:54 ` Anup Patel
0 siblings, 0 replies; 16+ messages in thread
From: Anup Patel @ 2019-07-05 10:54 UTC (permalink / raw)
To: u-boot
On Fri, Jul 5, 2019 at 12:22 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Fri, Jul 5, 2019 at 2:29 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > On Sat, Jun 29, 2019 at 2:57 PM Anup Patel <Anup.Patel@wdc.com> wrote:
> > >
> > > From: Bhargav Shah <bhargavshah1988@gmail.com>
> > >
> > > This patch enables SiFive SPI and MMC SPI drivers for the
> > > SiFive Unleashed board.
> > >
> > > Signed-off-by: Bhargav Shah <bhargavshah1988@gmail.com>
> > > Signed-off-by: Anup Patel <anup.patel@wdc.com>
> > > ---
> > > board/sifive/fu540/Kconfig | 8 ++++++++
> > > 1 file changed, 8 insertions(+)
> > >
> >
> > Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> > Tested-by: Bin Meng <bmeng.cn@gmail.com>
>
> Ah, I just noticed that DM_SPI and DM_MMC is already turned on
> arch/Kconfig for RISC-V. Please remove these 2.
Good catch. I will update Kconfig accordingly.
>
> Regards,
> Bin
Thanks,
Anup
^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [U-Boot,v9,0/9] Update SiFive Unleashed Drivers
2019-06-29 6:56 [U-Boot] [PATCH v2 0/5] SiFive SPI MMC Support Anup Patel
` (4 preceding siblings ...)
2019-06-29 6:57 ` [U-Boot] [PATCH v2 5/5] doc: sifive-fu540: Update README for " Anup Patel
@ 2019-07-05 15:45 ` Sagar Shrikant Kadam
5 siblings, 0 replies; 16+ messages in thread
From: Sagar Shrikant Kadam @ 2019-07-05 15:45 UTC (permalink / raw)
To: u-boot
Hi Anup,
Tested the entire V9 series with OpenSBI and mainline u-boot based
on commit fc6c0e29a28f6 ("Prepare v2019.07-rc4") along with few
Ramon Fried's patches present in your riscv_unleashed_clk_sync_v9 branch:
between commit fc6c0e29a28f6 ("Prepare v2019.07-rc4") and
commit 1a417ef71ce1 ("net: macb: apply sane DMA configuration").
With tftp able to boot complete linux.
MDIO and mii utils in U-boot correctly display details of Microsemi PHY
VSC8541-01 device as below:
=> mdio list
ethernet at 10090000:
0 - Microsemi VSC8541 <--> ethernet at 10090000
=> mii info 0
PHY 0x00: OUI = 0x01C1, Model = 0x37, Rev = 0x01, 100baseT, FDX
PHY address read from OTP:
Address in ROM is 70:b3:d5:92:f0:1f
Tested-by: Sagar Kadam <sagar.kadam@sifive.com>
BR,
Sagar Kadam
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2019-07-05 15:45 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-06-29 6:56 [U-Boot] [PATCH v2 0/5] SiFive SPI MMC Support Anup Patel
2019-06-29 6:56 ` [U-Boot] [PATCH v2 1/5] spi: Add SiFive SPI driver Anup Patel
2019-07-05 6:28 ` Bin Meng
2019-07-05 10:48 ` Anup Patel
2019-06-29 6:56 ` [U-Boot] [PATCH v2 2/5] mmc: skip select_mode_and_width for MMC SPI host Anup Patel
2019-07-05 6:28 ` Bin Meng
2019-06-29 6:57 ` [U-Boot] [PATCH v2 3/5] mmc: mmc_spi: Re-write driver using DM framework Anup Patel
2019-07-05 6:28 ` Bin Meng
2019-07-05 10:53 ` Anup Patel
2019-06-29 6:57 ` [U-Boot] [PATCH v2 4/5] riscv: sifive: fu540: Enable SiFive SPI and MMC SPI drivers Anup Patel
2019-07-05 6:29 ` Bin Meng
2019-07-05 6:51 ` Bin Meng
2019-07-05 10:54 ` Anup Patel
2019-06-29 6:57 ` [U-Boot] [PATCH v2 5/5] doc: sifive-fu540: Update README for " Anup Patel
2019-07-05 6:29 ` Bin Meng
2019-07-05 15:45 ` [U-Boot] [U-Boot,v9,0/9] Update SiFive Unleashed Drivers Sagar Shrikant Kadam
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