[PATCH v3 0/5] EHL port programming

[PATCH v3 0/5] EHL port programming

[Matt Roper]

Previous series revision here:
  https://lists.freedesktop.org/archives/intel-gfx/2019-June/202776.html

This revision incorporates Jose's feedback on patches #2, #3, and #4.

Matt Roper (5):
  drm/i915/icl: Drop port parameter to icl_get_combo_buf_trans()
  drm/i915/ehl: Add third combo PHY offset
  drm/i915/ehl: Don't program PHY_MISC on EHL PHY C
  drm/i915/gen11: Start distinguishing 'phy' from 'port'
  drm/i915/ehl: Enable DDI-D

 drivers/gpu/drm/i915/display/icl_dsi.c        |  24 ++-
 drivers/gpu/drm/i915/display/intel_bios.c     |   4 +-
 .../gpu/drm/i915/display/intel_combo_phy.c    | 159 ++++++++++--------
 .../gpu/drm/i915/display/intel_combo_phy.h    |   3 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      | 102 ++++++-----
 drivers/gpu/drm/i915/display/intel_display.c  |  32 ++--
 drivers/gpu/drm/i915/display/intel_display.h  |  16 ++
 drivers/gpu/drm/i915/display/intel_dp.c       |  12 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |   8 +-
 drivers/gpu/drm/i915/i915_reg.h               |  20 ++-
 drivers/gpu/drm/i915/intel_drv.h              |   4 +-
 11 files changed, 239 insertions(+), 145 deletions(-)

-- 
2.17.2

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[PATCH v3 1/5] drm/i915/icl: Drop port parameter to icl_get_combo_buf_trans()

[Matt Roper]

The port parameter hasn't been used since the last bspec phy programming
update.  Drop it to make some upcoming changes simpler.

References: 9659c1af451a ("drm/i915/icl: combo port vswing programming changes per BSPEC")
Cc: Clint Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 7925a176f900..593806d44ad4 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -846,8 +846,8 @@ cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 }
 
 static const struct cnl_ddi_buf_trans *
-icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
-			int type, int rate, int *n_entries)
+icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
+			int *n_entries)
 {
 	if (type == INTEL_OUTPUT_HDMI) {
 		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
@@ -872,7 +872,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
 
 	if (INTEL_GEN(dev_priv) >= 11) {
 		if (intel_port_is_combophy(dev_priv, port))
-			icl_get_combo_buf_trans(dev_priv, port, INTEL_OUTPUT_HDMI,
+			icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
 						0, &n_entries);
 		else
 			n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
@@ -2231,7 +2231,7 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
 
 	if (INTEL_GEN(dev_priv) >= 11) {
 		if (intel_port_is_combophy(dev_priv, port))
-			icl_get_combo_buf_trans(dev_priv, port, encoder->type,
+			icl_get_combo_buf_trans(dev_priv, encoder->type,
 						intel_dp->link_rate, &n_entries);
 		else
 			n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
@@ -2420,8 +2420,8 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
 	u32 n_entries, val;
 	int ln;
 
-	ddi_translations = icl_get_combo_buf_trans(dev_priv, port, type,
-						   rate, &n_entries);
+	ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate,
+						   &n_entries);
 	if (!ddi_translations)
 		return;
 
-- 
2.17.2

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[PATCH v3 2/5] drm/i915/ehl: Add third combo PHY offset

[Matt Roper]

v2: Rename register to _EHL_COMBOPHY_C.  (Jose)

Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7e6009cefb18..c814cc1b3ae5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1793,8 +1793,10 @@ enum i915_power_well_id {
  */
 #define _ICL_COMBOPHY_A			0x162000
 #define _ICL_COMBOPHY_B			0x6C000
+#define _EHL_COMBOPHY_C			0x160000
 #define _ICL_COMBOPHY(port)		_PICK(port, _ICL_COMBOPHY_A, \
-					      _ICL_COMBOPHY_B)
+					      _ICL_COMBOPHY_B, \
+					      _EHL_COMBOPHY_C)
 
 /* CNL/ICL Port CL_DW registers */
 #define _ICL_PORT_CL_DW(dw, port)	(_ICL_COMBOPHY(port) + \
-- 
2.17.2

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[PATCH v3 3/5] drm/i915/ehl: Don't program PHY_MISC on EHL PHY C

[Matt Roper]

Although EHL added a third combo PHY, no PHY_MISC register was added for
PHY C.  The bspec indicates that there's no need to program the "DE to
IO Comp Pwr Down" setting for this PHY that we usually need to set in
PHY_MISC.

v2:
 - Add IS_ELKHARTLAKE() guards since future platforms that have a PHY C
   are likely to reinstate the PHY_MISC register.  (Jose)
 - Use goto's to skip PHY_MISC programming & minimize code deltas. (Jose)

Bspec: 33148
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 .../gpu/drm/i915/display/intel_combo_phy.c    | 28 +++++++++++++++++--
 1 file changed, 25 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 075bab2500eb..d3d5244765e6 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -183,9 +183,13 @@ static void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv)
 static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv,
 				  enum port port)
 {
-	return !(I915_READ(ICL_PHY_MISC(port)) &
-		 ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) &&
-		(I915_READ(ICL_PORT_COMP_DW0(port)) & COMP_INIT);
+	/* The PHY C added by EHL has no PHY_MISC register */
+	if (IS_ELKHARTLAKE(dev_priv) && port == PORT_C)
+		return I915_READ(ICL_PORT_COMP_DW0(port)) & COMP_INIT;
+	else
+		return !(I915_READ(ICL_PHY_MISC(port)) &
+			 ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) &&
+			(I915_READ(ICL_PORT_COMP_DW0(port)) & COMP_INIT);
 }
 
 static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
@@ -299,6 +303,14 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
 			continue;
 		}
 
+		/*
+		 * Although EHL adds a combo PHY C, there's no PHY_MISC
+		 * register for it and no need to program the
+		 * DE_IO_COMP_PWR_DOWN setting on PHY C.
+		 */
+		if (IS_ELKHARTLAKE(dev_priv) && port == PORT_C)
+			goto skip_phy_misc;
+
 		/*
 		 * EHL's combo PHY A can be hooked up to either an external
 		 * display (via DDI-D) or an internal display (via DDI-A or
@@ -313,6 +325,7 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
 		val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
 		I915_WRITE(ICL_PHY_MISC(port), val);
 
+skip_phy_misc:
 		cnl_set_procmon_ref_values(dev_priv, port);
 
 		if (port == PORT_A) {
@@ -343,10 +356,19 @@ static void icl_combo_phys_uninit(struct drm_i915_private *dev_priv)
 			DRM_WARN("Port %c combo PHY HW state changed unexpectedly\n",
 				 port_name(port));
 
+		/*
+		 * Although EHL adds a combo PHY C, there's no PHY_MISC
+		 * register for it and no need to program the
+		 * DE_IO_COMP_PWR_DOWN setting on PHY C.
+		 */
+		if (IS_ELKHARTLAKE(dev_priv) && port == PORT_C)
+			goto skip_phy_misc;
+
 		val = I915_READ(ICL_PHY_MISC(port));
 		val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
 		I915_WRITE(ICL_PHY_MISC(port), val);
 
+skip_phy_misc:
 		val = I915_READ(ICL_PORT_COMP_DW0(port));
 		val &= ~COMP_INIT;
 		I915_WRITE(ICL_PORT_COMP_DW0(port), val);
-- 
2.17.2

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Re: [PATCH v3 3/5] drm/i915/ehl: Don't program PHY_MISC on EHL PHY C

[Souza, Jose]

On Tue, 2019-06-25 at 17:03 -0700, Matt Roper wrote:
> Although EHL added a third combo PHY, no PHY_MISC register was added
> for
> PHY C.  The bspec indicates that there's no need to program the "DE
> to
> IO Comp Pwr Down" setting for this PHY that we usually need to set in
> PHY_MISC.
> 
> v2:
>  - Add IS_ELKHARTLAKE() guards since future platforms that have a PHY
> C
>    are likely to reinstate the PHY_MISC register.  (Jose)
>  - Use goto's to skip PHY_MISC programming & minimize code deltas.
> (Jose)
> 

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> Bspec: 33148
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_combo_phy.c    | 28
> +++++++++++++++++--
>  1 file changed, 25 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> index 075bab2500eb..d3d5244765e6 100644
> --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> @@ -183,9 +183,13 @@ static void cnl_combo_phys_uninit(struct
> drm_i915_private *dev_priv)
>  static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv,
>  				  enum port port)
>  {
> -	return !(I915_READ(ICL_PHY_MISC(port)) &
> -		 ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) &&
> -		(I915_READ(ICL_PORT_COMP_DW0(port)) & COMP_INIT);
> +	/* The PHY C added by EHL has no PHY_MISC register */
> +	if (IS_ELKHARTLAKE(dev_priv) && port == PORT_C)
> +		return I915_READ(ICL_PORT_COMP_DW0(port)) & COMP_INIT;
> +	else
> +		return !(I915_READ(ICL_PHY_MISC(port)) &
> +			 ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) &&
> +			(I915_READ(ICL_PORT_COMP_DW0(port)) &
> COMP_INIT);
>  }
>  
>  static bool icl_combo_phy_verify_state(struct drm_i915_private
> *dev_priv,
> @@ -299,6 +303,14 @@ static void icl_combo_phys_init(struct
> drm_i915_private *dev_priv)
>  			continue;
>  		}
>  
> +		/*
> +		 * Although EHL adds a combo PHY C, there's no PHY_MISC
> +		 * register for it and no need to program the
> +		 * DE_IO_COMP_PWR_DOWN setting on PHY C.
> +		 */
> +		if (IS_ELKHARTLAKE(dev_priv) && port == PORT_C)
> +			goto skip_phy_misc;
> +
>  		/*
>  		 * EHL's combo PHY A can be hooked up to either an
> external
>  		 * display (via DDI-D) or an internal display (via DDI-
> A or
> @@ -313,6 +325,7 @@ static void icl_combo_phys_init(struct
> drm_i915_private *dev_priv)
>  		val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
>  		I915_WRITE(ICL_PHY_MISC(port), val);
>  
> +skip_phy_misc:
>  		cnl_set_procmon_ref_values(dev_priv, port);
>  
>  		if (port == PORT_A) {
> @@ -343,10 +356,19 @@ static void icl_combo_phys_uninit(struct
> drm_i915_private *dev_priv)
>  			DRM_WARN("Port %c combo PHY HW state changed
> unexpectedly\n",
>  				 port_name(port));
>  
> +		/*
> +		 * Although EHL adds a combo PHY C, there's no PHY_MISC
> +		 * register for it and no need to program the
> +		 * DE_IO_COMP_PWR_DOWN setting on PHY C.
> +		 */
> +		if (IS_ELKHARTLAKE(dev_priv) && port == PORT_C)
> +			goto skip_phy_misc;
> +
>  		val = I915_READ(ICL_PHY_MISC(port));
>  		val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
>  		I915_WRITE(ICL_PHY_MISC(port), val);
>  
> +skip_phy_misc:
>  		val = I915_READ(ICL_PORT_COMP_DW0(port));
>  		val &= ~COMP_INIT;
>  		I915_WRITE(ICL_PORT_COMP_DW0(port), val);
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Re: [PATCH v3 3/5] drm/i915/ehl: Don't program PHY_MISC on EHL PHY C

[Souza, Jose]

On Tue, 2019-06-25 at 17:03 -0700, Matt Roper wrote:
> Although EHL added a third combo PHY, no PHY_MISC register was added
> for
> PHY C.  The bspec indicates that there's no need to program the "DE
> to
> IO Comp Pwr Down" setting for this PHY that we usually need to set in
> PHY_MISC.
> 
> v2:
>  - Add IS_ELKHARTLAKE() guards since future platforms that have a PHY
> C
>    are likely to reinstate the PHY_MISC register.  (Jose)
>  - Use goto's to skip PHY_MISC programming & minimize code deltas.
> (Jose)

I found more registers that also needs the conversion, here a few:

dsi_program_swing_and_deemphasis()
	ICL_PORT_TX_DW5_LN0

icl_ddi_combo_vswing_program()
	ICL_PORT_TX_DW5_LN0
	ICL_PORT_TX_DW4_LN

icl_combo_phy_ddi_vswing_sequence()
	ICL_PORT_TX_DW4_LN
	ICL_PORT_CL_DW5
	ICL_PORT_TX_DW4_LN
	ICL_PORT_TX_DW5_GRP


Suggestion: send the other patches separated, merge those patches and
then we work on this one.


> 
> Bspec: 33148
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_combo_phy.c    | 28
> +++++++++++++++++--
>  1 file changed, 25 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> index 075bab2500eb..d3d5244765e6 100644
> --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> @@ -183,9 +183,13 @@ static void cnl_combo_phys_uninit(struct
> drm_i915_private *dev_priv)
>  static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv,
>  				  enum port port)
>  {
> -	return !(I915_READ(ICL_PHY_MISC(port)) &
> -		 ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) &&
> -		(I915_READ(ICL_PORT_COMP_DW0(port)) & COMP_INIT);
> +	/* The PHY C added by EHL has no PHY_MISC register */
> +	if (IS_ELKHARTLAKE(dev_priv) && port == PORT_C)
> +		return I915_READ(ICL_PORT_COMP_DW0(port)) & COMP_INIT;
> +	else
> +		return !(I915_READ(ICL_PHY_MISC(port)) &
> +			 ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) &&
> +			(I915_READ(ICL_PORT_COMP_DW0(port)) &
> COMP_INIT);
>  }
>  
>  static bool icl_combo_phy_verify_state(struct drm_i915_private
> *dev_priv,
> @@ -299,6 +303,14 @@ static void icl_combo_phys_init(struct
> drm_i915_private *dev_priv)
>  			continue;
>  		}
>  
> +		/*
> +		 * Although EHL adds a combo PHY C, there's no PHY_MISC
> +		 * register for it and no need to program the
> +		 * DE_IO_COMP_PWR_DOWN setting on PHY C.
> +		 */
> +		if (IS_ELKHARTLAKE(dev_priv) && port == PORT_C)
> +			goto skip_phy_misc;
> +
>  		/*
>  		 * EHL's combo PHY A can be hooked up to either an
> external
>  		 * display (via DDI-D) or an internal display (via DDI-
> A or
> @@ -313,6 +325,7 @@ static void icl_combo_phys_init(struct
> drm_i915_private *dev_priv)
>  		val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
>  		I915_WRITE(ICL_PHY_MISC(port), val);
>  
> +skip_phy_misc:
>  		cnl_set_procmon_ref_values(dev_priv, port);
>  
>  		if (port == PORT_A) {
> @@ -343,10 +356,19 @@ static void icl_combo_phys_uninit(struct
> drm_i915_private *dev_priv)
>  			DRM_WARN("Port %c combo PHY HW state changed
> unexpectedly\n",
>  				 port_name(port));
>  
> +		/*
> +		 * Although EHL adds a combo PHY C, there's no PHY_MISC
> +		 * register for it and no need to program the
> +		 * DE_IO_COMP_PWR_DOWN setting on PHY C.
> +		 */
> +		if (IS_ELKHARTLAKE(dev_priv) && port == PORT_C)
> +			goto skip_phy_misc;
> +
>  		val = I915_READ(ICL_PHY_MISC(port));
>  		val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
>  		I915_WRITE(ICL_PHY_MISC(port), val);
>  
> +skip_phy_misc:
>  		val = I915_READ(ICL_PORT_COMP_DW0(port));
>  		val &= ~COMP_INIT;
>  		I915_WRITE(ICL_PORT_COMP_DW0(port), val);
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Re: [PATCH v3 3/5] drm/i915/ehl: Don't program PHY_MISC on EHL PHY C

[Matt Roper]

On Fri, Jun 28, 2019 at 04:52:31PM -0700, Souza, Jose wrote:
> On Tue, 2019-06-25 at 17:03 -0700, Matt Roper wrote:
> > Although EHL added a third combo PHY, no PHY_MISC register was added
> > for
> > PHY C.  The bspec indicates that there's no need to program the "DE
> > to
> > IO Comp Pwr Down" setting for this PHY that we usually need to set in
> > PHY_MISC.
> > 
> > v2:
> >  - Add IS_ELKHARTLAKE() guards since future platforms that have a PHY
> > C
> >    are likely to reinstate the PHY_MISC register.  (Jose)
> >  - Use goto's to skip PHY_MISC programming & minimize code deltas.
> > (Jose)
> 
> I found more registers that also needs the conversion, here a few:
> 
> dsi_program_swing_and_deemphasis()
> 	ICL_PORT_TX_DW5_LN0
> 
> icl_ddi_combo_vswing_program()
> 	ICL_PORT_TX_DW5_LN0
> 	ICL_PORT_TX_DW4_LN
> 
> icl_combo_phy_ddi_vswing_sequence()
> 	ICL_PORT_TX_DW4_LN
> 	ICL_PORT_CL_DW5
> 	ICL_PORT_TX_DW4_LN
> 	ICL_PORT_TX_DW5_GRP
> 
> 
> Suggestion: send the other patches separated, merge those patches and
> then we work on this one.

Sounds good.  Although I think you meant to leave this comment on patch
#4 (port -> phy) rather than patch #3 (skip programming a specific
register), right?

Since patches #1-3 all have r-b's and the series as a whole has a clean
CI, I'll go ahead and apply those three, then work on respinning this
one.  I'll hold off applying #5 until #4 is ready; no point enabling
DDI-D until its PHY programming gets routed to the proper
registers/bits.


Matt

> 
> 
> > 
> > Bspec: 33148
> > Cc: José Roberto de Souza <jose.souza@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> >  .../gpu/drm/i915/display/intel_combo_phy.c    | 28
> > +++++++++++++++++--
> >  1 file changed, 25 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> > b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> > index 075bab2500eb..d3d5244765e6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> > @@ -183,9 +183,13 @@ static void cnl_combo_phys_uninit(struct
> > drm_i915_private *dev_priv)
> >  static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv,
> >  				  enum port port)
> >  {
> > -	return !(I915_READ(ICL_PHY_MISC(port)) &
> > -		 ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) &&
> > -		(I915_READ(ICL_PORT_COMP_DW0(port)) & COMP_INIT);
> > +	/* The PHY C added by EHL has no PHY_MISC register */
> > +	if (IS_ELKHARTLAKE(dev_priv) && port == PORT_C)
> > +		return I915_READ(ICL_PORT_COMP_DW0(port)) & COMP_INIT;
> > +	else
> > +		return !(I915_READ(ICL_PHY_MISC(port)) &
> > +			 ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) &&
> > +			(I915_READ(ICL_PORT_COMP_DW0(port)) &
> > COMP_INIT);
> >  }
> >  
> >  static bool icl_combo_phy_verify_state(struct drm_i915_private
> > *dev_priv,
> > @@ -299,6 +303,14 @@ static void icl_combo_phys_init(struct
> > drm_i915_private *dev_priv)
> >  			continue;
> >  		}
> >  
> > +		/*
> > +		 * Although EHL adds a combo PHY C, there's no PHY_MISC
> > +		 * register for it and no need to program the
> > +		 * DE_IO_COMP_PWR_DOWN setting on PHY C.
> > +		 */
> > +		if (IS_ELKHARTLAKE(dev_priv) && port == PORT_C)
> > +			goto skip_phy_misc;
> > +
> >  		/*
> >  		 * EHL's combo PHY A can be hooked up to either an
> > external
> >  		 * display (via DDI-D) or an internal display (via DDI-
> > A or
> > @@ -313,6 +325,7 @@ static void icl_combo_phys_init(struct
> > drm_i915_private *dev_priv)
> >  		val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
> >  		I915_WRITE(ICL_PHY_MISC(port), val);
> >  
> > +skip_phy_misc:
> >  		cnl_set_procmon_ref_values(dev_priv, port);
> >  
> >  		if (port == PORT_A) {
> > @@ -343,10 +356,19 @@ static void icl_combo_phys_uninit(struct
> > drm_i915_private *dev_priv)
> >  			DRM_WARN("Port %c combo PHY HW state changed
> > unexpectedly\n",
> >  				 port_name(port));
> >  
> > +		/*
> > +		 * Although EHL adds a combo PHY C, there's no PHY_MISC
> > +		 * register for it and no need to program the
> > +		 * DE_IO_COMP_PWR_DOWN setting on PHY C.
> > +		 */
> > +		if (IS_ELKHARTLAKE(dev_priv) && port == PORT_C)
> > +			goto skip_phy_misc;
> > +
> >  		val = I915_READ(ICL_PHY_MISC(port));
> >  		val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
> >  		I915_WRITE(ICL_PHY_MISC(port), val);
> >  
> > +skip_phy_misc:
> >  		val = I915_READ(ICL_PORT_COMP_DW0(port));
> >  		val &= ~COMP_INIT;
> >  		I915_WRITE(ICL_PORT_COMP_DW0(port), val);

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v3 4/5] drm/i915/gen11: Start distinguishing 'phy' from 'port'

[Matt Roper]

Our past DDI-based Intel platforms have had a fixed DDI<->PHY mapping.
Because of this, both the bspec documentation and our i915 code has used
the term "port" when talking about either DDI's or PHY's; it was always
easy to tell what terms like "Port A" were referring to from the
context.

Unfortunately this is starting to break down now that EHL allows PHY-A
to be driven by either DDI-A or DDI-D.  Is a setup with DDI-D driving
PHY-A considered "Port A" or "Port D?"  The answer depends on which
register we're working with, and even the bspec doesn't do a great job
of clarifying this.

Let's try to be more explicit about whether we're talking about the DDI
or the PHY on gen11+ by using 'port' to refer to the DDI and creating a
new 'enum phy' namespace to refer to the PHY in use.

A few general notes:

 - ICL_PORT_COMP_* and ICL_PORT_CL_* belong to the actual combo PHY so
   they should always be programmed according to the PHY in use,
   regardless of which DDI is driving it.

 - The pipe part of the hardware expects "port" to refer to the
   DDI, so registers like TRANS_CLK_SEL and TRANS_DDI_FUNC_CTL should
   set bits according to the desired DDI (e.g., DDI-D) rather than the
   PHY (PHY-A).

 - Non-pipe registers refer to the PHY.  Notably, DPCLKA_CFGCR0_ICL
   needs to set bits according to the PHY rather than DDI, even though
   the bit descriptions in the bspec use the term 'DDI.'  Also, since
   the CNL DPCLKA_CFGCR0 bit defines are still port-based, we create
   separate ICL-specific defines that accept the PHY rather than trying
   to share the same bit definitions between CNL and ICL.

Most of the changes here are on the combo PHY side.  I didn't touch most
of the TC port code yet, so it still refers to everything as ports.
That's okay for now since there's no TC on EHL, but we'll probably want
to separate out the DDI vs PHY terminology for TC in the future as well
to avoid confusion.

v2:
 - Convert a few more 'port' uses to 'phy.' (Sparse)

v3:
 - Switch DDI_CLK_SEL() back to 'port.' (Jose)
 - Add a code comment clarifying why DPCLKA_CFGCR0_ICL needs to use PHY
   for its bit definitions, even though the register description is
   given in terms of DDI.
 - To avoid confusion, switch CNL's DPCLKA_CFGCR0 defines back to using
   port and create separate ICL+ definitions that work in terms of PHY.

Suggested-by: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c        |  24 ++-
 drivers/gpu/drm/i915/display/intel_bios.c     |   4 +-
 .../gpu/drm/i915/display/intel_combo_phy.c    | 143 +++++++++---------
 .../gpu/drm/i915/display/intel_combo_phy.h    |   3 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      |  90 +++++++----
 drivers/gpu/drm/i915/display/intel_display.c  |  31 ++--
 drivers/gpu/drm/i915/display/intel_display.h  |  16 ++
 drivers/gpu/drm/i915/display/intel_dp.c       |  12 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |   8 +-
 drivers/gpu/drm/i915/i915_reg.h               |  16 +-
 drivers/gpu/drm/i915/intel_drv.h              |   4 +-
 11 files changed, 210 insertions(+), 141 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index b8673debf932..79b1e7c137df 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -365,10 +365,13 @@ static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder)
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	enum port port;
+	enum phy phy;
 
-	for_each_dsi_port(port, intel_dsi->ports)
-		intel_combo_phy_power_up_lanes(dev_priv, port, true,
+	for_each_dsi_port(port, intel_dsi->ports) {
+		phy = intel_port_to_phy(dev_priv, port);
+		intel_combo_phy_power_up_lanes(dev_priv, phy, true,
 					       intel_dsi->lane_count, false);
+	}
 }
 
 static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
@@ -560,11 +563,13 @@ static void gen11_dsi_gate_clocks(struct intel_encoder *encoder)
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	u32 tmp;
 	enum port port;
+	enum phy phy;
 
 	mutex_lock(&dev_priv->dpll_lock);
 	tmp = I915_READ(DPCLKA_CFGCR0_ICL);
 	for_each_dsi_port(port, intel_dsi->ports) {
-		tmp |= DPCLKA_CFGCR0_DDI_CLK_OFF(port);
+		phy = intel_port_to_phy(dev_priv, port);
+		tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
 	}
 
 	I915_WRITE(DPCLKA_CFGCR0_ICL, tmp);
@@ -577,11 +582,13 @@ static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	u32 tmp;
 	enum port port;
+	enum phy phy;
 
 	mutex_lock(&dev_priv->dpll_lock);
 	tmp = I915_READ(DPCLKA_CFGCR0_ICL);
 	for_each_dsi_port(port, intel_dsi->ports) {
-		tmp &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
+		phy = intel_port_to_phy(dev_priv, port);
+		tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
 	}
 
 	I915_WRITE(DPCLKA_CFGCR0_ICL, tmp);
@@ -595,19 +602,22 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder,
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 	enum port port;
+	enum phy phy;
 	u32 val;
 
 	mutex_lock(&dev_priv->dpll_lock);
 
 	val = I915_READ(DPCLKA_CFGCR0_ICL);
 	for_each_dsi_port(port, intel_dsi->ports) {
-		val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
-		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
+		phy = intel_port_to_phy(dev_priv, port);
+		val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+		val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
 	}
 	I915_WRITE(DPCLKA_CFGCR0_ICL, val);
 
 	for_each_dsi_port(port, intel_dsi->ports) {
-		val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
+		phy = intel_port_to_phy(dev_priv, port);
+		val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
 	}
 	I915_WRITE(DPCLKA_CFGCR0_ICL, val);
 
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 0c9808132d67..4fdbb5c35d87 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -28,6 +28,7 @@
 #include <drm/drm_dp_helper.h>
 #include <drm/i915_drm.h>
 
+#include "display/intel_display.h"
 #include "display/intel_gmbus.h"
 
 #include "i915_drv.h"
@@ -1733,12 +1734,13 @@ init_vbt_missing_defaults(struct drm_i915_private *dev_priv)
 	for (port = PORT_A; port < I915_MAX_PORTS; port++) {
 		struct ddi_vbt_port_info *info =
 			&dev_priv->vbt.ddi_port_info[port];
+		enum phy phy = intel_port_to_phy(dev_priv, port);
 
 		/*
 		 * VBT has the TypeC mode (native,TBT/USB) and we don't want
 		 * to detect it.
 		 */
-		if (intel_port_is_tc(dev_priv, port))
+		if (intel_phy_is_tc(dev_priv, phy))
 			continue;
 
 		info->supports_dvi = (port != PORT_A && port != PORT_E);
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index d3d5244765e6..ac8218a040ab 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -6,13 +6,13 @@
 #include "intel_combo_phy.h"
 #include "intel_drv.h"
 
-#define for_each_combo_port(__dev_priv, __port) \
-	for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)	\
-		for_each_if(intel_port_is_combophy(__dev_priv, __port))
+#define for_each_combo_phy(__dev_priv, __phy) \
+	for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++)	\
+		for_each_if(intel_phy_is_combo(__dev_priv, __phy))
 
-#define for_each_combo_port_reverse(__dev_priv, __port) \
-	for ((__port) = I915_MAX_PORTS; (__port)-- > PORT_A;) \
-		for_each_if(intel_port_is_combophy(__dev_priv, __port))
+#define for_each_combo_phy_reverse(__dev_priv, __phy) \
+	for ((__phy) = I915_MAX_PHYS; (__phy)-- > PHY_A;) \
+		for_each_if(intel_phy_is_combo(__dev_priv, __phy))
 
 enum {
 	PROCMON_0_85V_DOT_0,
@@ -38,18 +38,17 @@ static const struct cnl_procmon {
 };
 
 /*
- * CNL has just one set of registers, while ICL has two sets: one for port A and
- * the other for port B. The CNL registers are equivalent to the ICL port A
- * registers, that's why we call the ICL macros even though the function has CNL
- * on its name.
+ * CNL has just one set of registers, while gen11 has a set for each combo PHY.
+ * The CNL registers are equivalent to the gen11 PHY A registers, that's why we
+ * call the ICL macros even though the function has CNL on its name.
  */
 static const struct cnl_procmon *
-cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum port port)
+cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy)
 {
 	const struct cnl_procmon *procmon;
 	u32 val;
 
-	val = I915_READ(ICL_PORT_COMP_DW3(port));
+	val = I915_READ(ICL_PORT_COMP_DW3(phy));
 	switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {
 	default:
 		MISSING_CASE(val);
@@ -75,32 +74,32 @@ cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum port port)
 }
 
 static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv,
-				       enum port port)
+				       enum phy phy)
 {
 	const struct cnl_procmon *procmon;
 	u32 val;
 
-	procmon = cnl_get_procmon_ref_values(dev_priv, port);
+	procmon = cnl_get_procmon_ref_values(dev_priv, phy);
 
-	val = I915_READ(ICL_PORT_COMP_DW1(port));
+	val = I915_READ(ICL_PORT_COMP_DW1(phy));
 	val &= ~((0xff << 16) | 0xff);
 	val |= procmon->dw1;
-	I915_WRITE(ICL_PORT_COMP_DW1(port), val);
+	I915_WRITE(ICL_PORT_COMP_DW1(phy), val);
 
-	I915_WRITE(ICL_PORT_COMP_DW9(port), procmon->dw9);
-	I915_WRITE(ICL_PORT_COMP_DW10(port), procmon->dw10);
+	I915_WRITE(ICL_PORT_COMP_DW9(phy), procmon->dw9);
+	I915_WRITE(ICL_PORT_COMP_DW10(phy), procmon->dw10);
 }
 
 static bool check_phy_reg(struct drm_i915_private *dev_priv,
-			  enum port port, i915_reg_t reg, u32 mask,
+			  enum phy phy, i915_reg_t reg, u32 mask,
 			  u32 expected_val)
 {
 	u32 val = I915_READ(reg);
 
 	if ((val & mask) != expected_val) {
-		DRM_DEBUG_DRIVER("Port %c combo PHY reg %08x state mismatch: "
+		DRM_DEBUG_DRIVER("Combo PHY %c reg %08x state mismatch: "
 				 "current %08x mask %08x expected %08x\n",
-				 port_name(port),
+				 phy_name(phy),
 				 reg.reg, val, mask, expected_val);
 		return false;
 	}
@@ -109,18 +108,18 @@ static bool check_phy_reg(struct drm_i915_private *dev_priv,
 }
 
 static bool cnl_verify_procmon_ref_values(struct drm_i915_private *dev_priv,
-					  enum port port)
+					  enum phy phy)
 {
 	const struct cnl_procmon *procmon;
 	bool ret;
 
-	procmon = cnl_get_procmon_ref_values(dev_priv, port);
+	procmon = cnl_get_procmon_ref_values(dev_priv, phy);
 
-	ret = check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW1(port),
+	ret = check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW1(phy),
 			    (0xff << 16) | 0xff, procmon->dw1);
-	ret &= check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW9(port),
+	ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW9(phy),
 			     -1U, procmon->dw9);
-	ret &= check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW10(port),
+	ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW10(phy),
 			     -1U, procmon->dw10);
 
 	return ret;
@@ -134,15 +133,15 @@ static bool cnl_combo_phy_enabled(struct drm_i915_private *dev_priv)
 
 static bool cnl_combo_phy_verify_state(struct drm_i915_private *dev_priv)
 {
-	enum port port = PORT_A;
+	enum phy phy = PHY_A;
 	bool ret;
 
 	if (!cnl_combo_phy_enabled(dev_priv))
 		return false;
 
-	ret = cnl_verify_procmon_ref_values(dev_priv, port);
+	ret = cnl_verify_procmon_ref_values(dev_priv, phy);
 
-	ret &= check_phy_reg(dev_priv, port, CNL_PORT_CL1CM_DW5,
+	ret &= check_phy_reg(dev_priv, phy, CNL_PORT_CL1CM_DW5,
 			     CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE);
 
 	return ret;
@@ -157,7 +156,7 @@ static void cnl_combo_phys_init(struct drm_i915_private *dev_priv)
 	I915_WRITE(CHICKEN_MISC_2, val);
 
 	/* Dummy PORT_A to get the correct CNL register from the ICL macro */
-	cnl_set_procmon_ref_values(dev_priv, PORT_A);
+	cnl_set_procmon_ref_values(dev_priv, PHY_A);
 
 	val = I915_READ(CNL_PORT_COMP_DW0);
 	val |= COMP_INIT;
@@ -181,39 +180,39 @@ static void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv)
 }
 
 static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv,
-				  enum port port)
+				  enum phy phy)
 {
 	/* The PHY C added by EHL has no PHY_MISC register */
-	if (IS_ELKHARTLAKE(dev_priv) && port == PORT_C)
-		return I915_READ(ICL_PORT_COMP_DW0(port)) & COMP_INIT;
+	if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C)
+		return I915_READ(ICL_PORT_COMP_DW0(phy)) & COMP_INIT;
 	else
-		return !(I915_READ(ICL_PHY_MISC(port)) &
+		return !(I915_READ(ICL_PHY_MISC(phy)) &
 			 ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) &&
-			(I915_READ(ICL_PORT_COMP_DW0(port)) & COMP_INIT);
+			(I915_READ(ICL_PORT_COMP_DW0(phy)) & COMP_INIT);
 }
 
 static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
-				       enum port port)
+				       enum phy phy)
 {
 	bool ret;
 
-	if (!icl_combo_phy_enabled(dev_priv, port))
+	if (!icl_combo_phy_enabled(dev_priv, phy))
 		return false;
 
-	ret = cnl_verify_procmon_ref_values(dev_priv, port);
+	ret = cnl_verify_procmon_ref_values(dev_priv, phy);
 
-	if (port == PORT_A)
-		ret &= check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW8(port),
+	if (phy == PHY_A)
+		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),
 				     IREFGEN, IREFGEN);
 
-	ret &= check_phy_reg(dev_priv, port, ICL_PORT_CL_DW5(port),
+	ret &= check_phy_reg(dev_priv, phy, ICL_PORT_CL_DW5(phy),
 			     CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE);
 
 	return ret;
 }
 
 void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv,
-				    enum port port, bool is_dsi,
+				    enum phy phy, bool is_dsi,
 				    int lane_count, bool lane_reversal)
 {
 	u8 lane_mask;
@@ -258,10 +257,10 @@ void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv,
 		}
 	}
 
-	val = I915_READ(ICL_PORT_CL_DW10(port));
+	val = I915_READ(ICL_PORT_CL_DW10(phy));
 	val &= ~PWR_DOWN_LN_MASK;
 	val |= lane_mask << PWR_DOWN_LN_SHIFT;
-	I915_WRITE(ICL_PORT_CL_DW10(port), val);
+	I915_WRITE(ICL_PORT_CL_DW10(phy), val);
 }
 
 static u32 ehl_combo_phy_a_mux(struct drm_i915_private *i915, u32 val)
@@ -292,14 +291,14 @@ static u32 ehl_combo_phy_a_mux(struct drm_i915_private *i915, u32 val)
 
 static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
 {
-	enum port port;
+	enum phy phy;
 
-	for_each_combo_port(dev_priv, port) {
+	for_each_combo_phy(dev_priv, phy) {
 		u32 val;
 
-		if (icl_combo_phy_verify_state(dev_priv, port)) {
-			DRM_DEBUG_DRIVER("Port %c combo PHY already enabled, won't reprogram it.\n",
-					 port_name(port));
+		if (icl_combo_phy_verify_state(dev_priv, phy)) {
+			DRM_DEBUG_DRIVER("Combo PHY %c already enabled, won't reprogram it.\n",
+					 phy_name(phy));
 			continue;
 		}
 
@@ -308,7 +307,7 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
 		 * register for it and no need to program the
 		 * DE_IO_COMP_PWR_DOWN setting on PHY C.
 		 */
-		if (IS_ELKHARTLAKE(dev_priv) && port == PORT_C)
+		if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C)
 			goto skip_phy_misc;
 
 		/*
@@ -319,59 +318,59 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
 		 * based on whether our VBT indicates the presence of any
 		 * "internal" child devices.
 		 */
-		val = I915_READ(ICL_PHY_MISC(port));
-		if (IS_ELKHARTLAKE(dev_priv) && port == PORT_A)
+		val = I915_READ(ICL_PHY_MISC(phy));
+		if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_A)
 			val = ehl_combo_phy_a_mux(dev_priv, val);
 		val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
-		I915_WRITE(ICL_PHY_MISC(port), val);
+		I915_WRITE(ICL_PHY_MISC(phy), val);
 
 skip_phy_misc:
-		cnl_set_procmon_ref_values(dev_priv, port);
+		cnl_set_procmon_ref_values(dev_priv, phy);
 
-		if (port == PORT_A) {
-			val = I915_READ(ICL_PORT_COMP_DW8(port));
+		if (phy == PHY_A) {
+			val = I915_READ(ICL_PORT_COMP_DW8(phy));
 			val |= IREFGEN;
-			I915_WRITE(ICL_PORT_COMP_DW8(port), val);
+			I915_WRITE(ICL_PORT_COMP_DW8(phy), val);
 		}
 
-		val = I915_READ(ICL_PORT_COMP_DW0(port));
+		val = I915_READ(ICL_PORT_COMP_DW0(phy));
 		val |= COMP_INIT;
-		I915_WRITE(ICL_PORT_COMP_DW0(port), val);
+		I915_WRITE(ICL_PORT_COMP_DW0(phy), val);
 
-		val = I915_READ(ICL_PORT_CL_DW5(port));
+		val = I915_READ(ICL_PORT_CL_DW5(phy));
 		val |= CL_POWER_DOWN_ENABLE;
-		I915_WRITE(ICL_PORT_CL_DW5(port), val);
+		I915_WRITE(ICL_PORT_CL_DW5(phy), val);
 	}
 }
 
 static void icl_combo_phys_uninit(struct drm_i915_private *dev_priv)
 {
-	enum port port;
+	enum phy phy;
 
-	for_each_combo_port_reverse(dev_priv, port) {
+	for_each_combo_phy_reverse(dev_priv, phy) {
 		u32 val;
 
-		if (port == PORT_A &&
-		    !icl_combo_phy_verify_state(dev_priv, port))
-			DRM_WARN("Port %c combo PHY HW state changed unexpectedly\n",
-				 port_name(port));
+		if (phy == PHY_A &&
+		    !icl_combo_phy_verify_state(dev_priv, phy))
+			DRM_WARN("Combo PHY %c HW state changed unexpectedly\n",
+				 phy_name(phy));
 
 		/*
 		 * Although EHL adds a combo PHY C, there's no PHY_MISC
 		 * register for it and no need to program the
 		 * DE_IO_COMP_PWR_DOWN setting on PHY C.
 		 */
-		if (IS_ELKHARTLAKE(dev_priv) && port == PORT_C)
+		if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C)
 			goto skip_phy_misc;
 
-		val = I915_READ(ICL_PHY_MISC(port));
+		val = I915_READ(ICL_PHY_MISC(phy));
 		val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
-		I915_WRITE(ICL_PHY_MISC(port), val);
+		I915_WRITE(ICL_PHY_MISC(phy), val);
 
 skip_phy_misc:
-		val = I915_READ(ICL_PORT_COMP_DW0(port));
+		val = I915_READ(ICL_PORT_COMP_DW0(phy));
 		val &= ~COMP_INIT;
-		I915_WRITE(ICL_PORT_COMP_DW0(port), val);
+		I915_WRITE(ICL_PORT_COMP_DW0(phy), val);
 	}
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.h b/drivers/gpu/drm/i915/display/intel_combo_phy.h
index e6e195a83b19..80a1386b4c87 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.h
@@ -10,11 +10,12 @@
 #include <drm/i915_drm.h>
 
 struct drm_i915_private;
+enum phy;
 
 void intel_combo_phy_init(struct drm_i915_private *dev_priv);
 void intel_combo_phy_uninit(struct drm_i915_private *dev_priv);
 void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv,
-				    enum port port, bool is_dsi,
+				    enum phy phy, bool is_dsi,
 				    int lane_count, bool lane_reversal);
 
 #endif /* __INTEL_COMBO_PHY_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 593806d44ad4..ea56fb6d632d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -867,11 +867,12 @@ icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
 {
 	int n_entries, level, default_entry;
+	enum phy phy = intel_port_to_phy(dev_priv, port);
 
 	level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 
 	if (INTEL_GEN(dev_priv) >= 11) {
-		if (intel_port_is_combophy(dev_priv, port))
+		if (intel_phy_is_combo(dev_priv, phy))
 			icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
 						0, &n_entries);
 		else
@@ -1486,9 +1487,10 @@ static void icl_ddi_clock_get(struct intel_encoder *encoder,
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
 	enum port port = encoder->port;
+	enum phy phy = intel_port_to_phy(dev_priv, port);
 	int link_clock;
 
-	if (intel_port_is_combophy(dev_priv, port)) {
+	if (intel_phy_is_combo(dev_priv, phy)) {
 		link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
 	} else {
 		enum intel_dpll_id pll_id = intel_get_shared_dpll_id(dev_priv,
@@ -2085,6 +2087,7 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_digital_port *dig_port;
+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 
 	/*
 	 * TODO: Add support for MST encoders. Atm, the following should never
@@ -2102,7 +2105,7 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
 	 * ports.
 	 */
 	if (intel_crtc_has_dp_encoder(crtc_state) ||
-	    intel_port_is_tc(dev_priv, encoder->port))
+	    intel_phy_is_tc(dev_priv, phy))
 		intel_display_power_get(dev_priv,
 					intel_ddi_main_link_aux_domain(dig_port));
 
@@ -2227,10 +2230,11 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 	enum port port = encoder->port;
+	enum phy phy = intel_port_to_phy(dev_priv, port);
 	int n_entries;
 
 	if (INTEL_GEN(dev_priv) >= 11) {
-		if (intel_port_is_combophy(dev_priv, port))
+		if (intel_phy_is_combo(dev_priv, phy))
 			icl_get_combo_buf_trans(dev_priv, encoder->type,
 						intel_dp->link_rate, &n_entries);
 		else
@@ -2663,9 +2667,9 @@ static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
 				    enum intel_output_type type)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	enum port port = encoder->port;
+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 
-	if (intel_port_is_combophy(dev_priv, port))
+	if (intel_phy_is_combo(dev_priv, phy))
 		icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
 	else
 		icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
@@ -2728,12 +2732,13 @@ u32 ddi_signal_levels(struct intel_dp *intel_dp)
 
 static inline
 u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
-			      enum port port)
+			      enum phy phy)
 {
-	if (intel_port_is_combophy(dev_priv, port)) {
-		return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
-	} else if (intel_port_is_tc(dev_priv, port)) {
-		enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
+	if (intel_phy_is_combo(dev_priv, phy)) {
+		return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
+	} else if (intel_phy_is_tc(dev_priv, phy)) {
+		enum tc_port tc_port = intel_port_to_tc(dev_priv,
+							(enum port)phy);
 
 		return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
 	}
@@ -2746,22 +2751,32 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
-	enum port port = encoder->port;
+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 	u32 val;
 
 	mutex_lock(&dev_priv->dpll_lock);
 
 	val = I915_READ(DPCLKA_CFGCR0_ICL);
-	WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);
+	WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
 
-	if (intel_port_is_combophy(dev_priv, port)) {
-		val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
-		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
+	if (intel_phy_is_combo(dev_priv, phy)) {
+		/*
+		 * Even though this register references DDIs, note that we
+		 * want to pass the PHY rather than the port (DDI).  For
+		 * ICL, port=phy in all cases so it doesn't matter, but for
+		 * EHL the bspec notes the following:
+		 *
+		 *   "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA
+		 *   Clock Select chooses the PLL for both DDIA and DDID and
+		 *   drives port A in all cases."
+		 */
+		val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+		val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
 		I915_WRITE(DPCLKA_CFGCR0_ICL, val);
 		POSTING_READ(DPCLKA_CFGCR0_ICL);
 	}
 
-	val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
+	val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
 	I915_WRITE(DPCLKA_CFGCR0_ICL, val);
 
 	mutex_unlock(&dev_priv->dpll_lock);
@@ -2770,13 +2785,13 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	enum port port = encoder->port;
+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 	u32 val;
 
 	mutex_lock(&dev_priv->dpll_lock);
 
 	val = I915_READ(DPCLKA_CFGCR0_ICL);
-	val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
+	val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
 	I915_WRITE(DPCLKA_CFGCR0_ICL, val);
 
 	mutex_unlock(&dev_priv->dpll_lock);
@@ -2837,9 +2852,11 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
 
 	val = I915_READ(DPCLKA_CFGCR0_ICL);
 	for_each_port_masked(port, port_mask) {
+		enum phy phy = intel_port_to_phy(dev_priv, port);
+
 		bool ddi_clk_ungated = !(val &
 					 icl_dpclka_cfgcr0_clk_off(dev_priv,
-								   port));
+								   phy));
 
 		if (ddi_clk_needed == ddi_clk_ungated)
 			continue;
@@ -2851,9 +2868,9 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
 		if (WARN_ON(ddi_clk_needed))
 			continue;
 
-		DRM_NOTE("Port %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
-			 port_name(port));
-		val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
+		DRM_NOTE("PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
+			 phy_name(port));
+		val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
 		I915_WRITE(DPCLKA_CFGCR0_ICL, val);
 	}
 }
@@ -2863,6 +2880,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
+	enum phy phy = intel_port_to_phy(dev_priv, port);
 	u32 val;
 	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 
@@ -2872,7 +2890,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
 	mutex_lock(&dev_priv->dpll_lock);
 
 	if (INTEL_GEN(dev_priv) >= 11) {
-		if (!intel_port_is_combophy(dev_priv, port))
+		if (!intel_phy_is_combo(dev_priv, phy))
 			I915_WRITE(DDI_CLK_SEL(port),
 				   icl_pll_to_ddi_clk_sel(encoder, crtc_state));
 	} else if (IS_CANNONLAKE(dev_priv)) {
@@ -2912,9 +2930,10 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
+	enum phy phy = intel_port_to_phy(dev_priv, port);
 
 	if (INTEL_GEN(dev_priv) >= 11) {
-		if (!intel_port_is_combophy(dev_priv, port))
+		if (!intel_phy_is_combo(dev_priv, phy))
 			I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
 	} else if (IS_CANNONLAKE(dev_priv)) {
 		I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
@@ -3110,6 +3129,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
+	enum phy phy = intel_port_to_phy(dev_priv, port);
 	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
 	bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
 	int level = intel_ddi_dp_level(intel_dp);
@@ -3138,11 +3158,11 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
 	else
 		intel_prepare_dp_ddi_buffers(encoder, crtc_state);
 
-	if (intel_port_is_combophy(dev_priv, port)) {
+	if (intel_phy_is_combo(dev_priv, phy)) {
 		bool lane_reversal =
 			dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
 
-		intel_combo_phy_power_up_lanes(dev_priv, port, false,
+		intel_combo_phy_power_up_lanes(dev_priv, phy, false,
 					       crtc_state->lane_count,
 					       lane_reversal);
 	}
@@ -3630,7 +3650,7 @@ intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
 	enum port port = encoder->port;
 
 	if (intel_crtc_has_dp_encoder(crtc_state) ||
-	    intel_port_is_tc(dev_priv, encoder->port))
+	    intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
 		intel_display_power_get(dev_priv,
 					intel_ddi_main_link_aux_domain(dig_port));
 
@@ -3656,9 +3676,10 @@ intel_ddi_post_pll_disable(struct intel_encoder *encoder,
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 
 	if (intel_crtc_has_dp_encoder(crtc_state) ||
-	    intel_port_is_tc(dev_priv, encoder->port))
+	    intel_phy_is_tc(dev_priv, phy))
 		intel_display_power_put_unchecked(dev_priv,
 						  intel_ddi_main_link_aux_domain(dig_port));
 }
@@ -3934,8 +3955,9 @@ static void intel_ddi_encoder_reset(struct drm_encoder *drm_encoder)
 {
 	struct intel_digital_port *dig_port = enc_to_dig_port(drm_encoder);
 	struct drm_i915_private *i915 = to_i915(drm_encoder->dev);
+	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
 
-	if (intel_port_is_tc(i915, dig_port->base.port))
+	if (intel_phy_is_tc(i915, phy))
 		intel_digital_port_connected(&dig_port->base);
 
 	intel_dp_encoder_reset(drm_encoder);
@@ -3945,10 +3967,11 @@ static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
 {
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	struct drm_i915_private *i915 = to_i915(encoder->dev);
+	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
 
 	intel_dp_encoder_flush_work(encoder);
 
-	if (intel_port_is_tc(i915, dig_port->base.port))
+	if (intel_phy_is_tc(i915, phy))
 		icl_tc_phy_disconnect(i915, dig_port);
 
 	drm_encoder_cleanup(encoder);
@@ -4198,6 +4221,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 	struct drm_encoder *encoder;
 	bool init_hdmi, init_dp, init_lspcon = false;
 	enum pipe pipe;
+	enum phy phy = intel_port_to_phy(dev_priv, port);
 
 	init_hdmi = port_info->supports_dvi || port_info->supports_hdmi;
 	init_dp = port_info->supports_dp;
@@ -4261,7 +4285,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 	intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
 	intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
 
-	intel_dig_port->tc_legacy_port = intel_port_is_tc(dev_priv, port) &&
+	intel_dig_port->tc_legacy_port = intel_phy_is_tc(dev_priv, phy) &&
 					 !port_info->supports_typec_usb &&
 					 !port_info->supports_tbt;
 
@@ -4324,7 +4348,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 
 	intel_infoframe_init(intel_dig_port);
 
-	if (intel_port_is_tc(dev_priv, port))
+	if (intel_phy_is_tc(dev_priv, phy))
 		intel_digital_port_connected(intel_encoder);
 
 	return;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 8592a7d422de..afbfef2fffde 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6560,31 +6560,39 @@ static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
 	I915_WRITE(BCLRPAT(crtc->pipe), 0);
 }
 
-bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
+bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
 {
-	if (port == PORT_NONE)
+	if (phy == PHY_NONE)
 		return false;
 
 	if (IS_ELKHARTLAKE(dev_priv))
-		return port <= PORT_C;
+		return phy <= PHY_C;
 
 	if (INTEL_GEN(dev_priv) >= 11)
-		return port <= PORT_B;
+		return phy <= PHY_B;
 
 	return false;
 }
 
-bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
+bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
 {
 	if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
-		return port >= PORT_C && port <= PORT_F;
+		return phy >= PHY_C && phy <= PHY_F;
 
 	return false;
 }
 
+enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
+{
+	if (IS_ELKHARTLAKE(i915) && port == PORT_D)
+		return PHY_A;
+
+	return (enum phy)port;
+}
+
 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
 {
-	if (!intel_port_is_tc(dev_priv, port))
+	if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
 		return PORT_TC_NONE;
 
 	return port - PORT_C;
@@ -9936,15 +9944,16 @@ static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
 				enum port port,
 				struct intel_crtc_state *pipe_config)
 {
+	enum phy phy = intel_port_to_phy(dev_priv, port);
 	enum intel_dpll_id id;
 	u32 temp;
 
 	/* TODO: TBT pll not implemented. */
-	if (intel_port_is_combophy(dev_priv, port)) {
+	if (intel_phy_is_combo(dev_priv, phy)) {
 		temp = I915_READ(DPCLKA_CFGCR0_ICL) &
-		       DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
-		id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
-	} else if (intel_port_is_tc(dev_priv, port)) {
+		       ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+		id = temp >> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
+	} else if (intel_phy_is_tc(dev_priv, phy)) {
 		id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv, port));
 	} else {
 		WARN(1, "Invalid port %x\n", port);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index ee6b8194a459..f89b0b779f18 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -229,6 +229,21 @@ struct intel_link_m_n {
 	u32 link_n;
 };
 
+enum phy {
+	PHY_NONE = -1,
+
+	PHY_A = 0,
+	PHY_B,
+	PHY_C,
+	PHY_D,
+	PHY_E,
+	PHY_F,
+
+	I915_MAX_PHYS
+};
+
+#define phy_name(a) ((a) + 'A')
+
 #define for_each_pipe(__dev_priv, __p) \
 	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
 
@@ -357,5 +372,6 @@ void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
 			      u32 pixel_format, u64 modifier);
 bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
+enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
 
 #endif
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 4336df46fe78..577538132a80 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -329,9 +329,9 @@ static int icl_max_source_rate(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
-	enum port port = dig_port->base.port;
+	enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
 
-	if (intel_port_is_combophy(dev_priv, port) &&
+	if (intel_phy_is_combo(dev_priv, phy) &&
 	    !IS_ELKHARTLAKE(dev_priv) &&
 	    !intel_dp_is_edp(intel_dp))
 		return 540000;
@@ -5425,10 +5425,11 @@ static bool icl_digital_port_connected(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 
-	if (intel_port_is_combophy(dev_priv, encoder->port))
+	if (intel_phy_is_combo(dev_priv, phy))
 		return icl_combo_port_connected(dev_priv, dig_port);
-	else if (intel_port_is_tc(dev_priv, encoder->port))
+	else if (intel_phy_is_tc(dev_priv, phy))
 		return icl_tc_port_connected(dev_priv, dig_port);
 	else
 		MISSING_CASE(encoder->hpd_pin);
@@ -7332,6 +7333,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 	struct drm_device *dev = intel_encoder->base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	enum port port = intel_encoder->port;
+	enum phy phy = intel_port_to_phy(dev_priv, port);
 	int type;
 
 	/* Initialize the work for modeset in case of link train failure */
@@ -7358,7 +7360,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 		 * Currently we don't support eDP on TypeC ports, although in
 		 * theory it could work on TypeC legacy ports.
 		 */
-		WARN_ON(intel_port_is_tc(dev_priv, port));
+		WARN_ON(intel_phy_is_tc(dev_priv, phy));
 		type = DRM_MODE_CONNECTOR_eDP;
 	} else {
 		type = DRM_MODE_CONNECTOR_DisplayPort;
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 2d4e7b9a7b9d..7bf697848055 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2513,7 +2513,8 @@ static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
 	struct skl_wrpll_params pll_params = { 0 };
 	bool ret;
 
-	if (intel_port_is_tc(dev_priv, encoder->port))
+	if (intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv,
+							encoder->port)))
 		ret = icl_calc_tbt_pll(crtc_state, &pll_params);
 	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
 		 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
@@ -2800,14 +2801,15 @@ icl_get_dpll(struct intel_crtc_state *crtc_state,
 	struct intel_digital_port *intel_dig_port;
 	struct intel_shared_dpll *pll;
 	enum port port = encoder->port;
+	enum phy phy = intel_port_to_phy(dev_priv, port);
 	enum intel_dpll_id min, max;
 	bool ret;
 
-	if (intel_port_is_combophy(dev_priv, port)) {
+	if (intel_phy_is_combo(dev_priv, phy)) {
 		min = DPLL_ID_ICL_DPLL0;
 		max = DPLL_ID_ICL_DPLL1;
 		ret = icl_calc_dpll_state(crtc_state, encoder);
-	} else if (intel_port_is_tc(dev_priv, port)) {
+	} else if (intel_phy_is_tc(dev_priv, phy)) {
 		if (encoder->type == INTEL_OUTPUT_DP_MST) {
 			struct intel_dp_mst_encoder *mst_encoder;
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c814cc1b3ae5..43ba079498b2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1794,12 +1794,12 @@ enum i915_power_well_id {
 #define _ICL_COMBOPHY_A			0x162000
 #define _ICL_COMBOPHY_B			0x6C000
 #define _EHL_COMBOPHY_C			0x160000
-#define _ICL_COMBOPHY(port)		_PICK(port, _ICL_COMBOPHY_A, \
+#define _ICL_COMBOPHY(phy)		_PICK(phy, _ICL_COMBOPHY_A, \
 					      _ICL_COMBOPHY_B, \
 					      _EHL_COMBOPHY_C)
 
 /* CNL/ICL Port CL_DW registers */
-#define _ICL_PORT_CL_DW(dw, port)	(_ICL_COMBOPHY(port) + \
+#define _ICL_PORT_CL_DW(dw, phy)	(_ICL_COMBOPHY(phy) + \
 					 4 * (dw))
 
 #define CNL_PORT_CL1CM_DW5		_MMIO(0x162014)
@@ -9680,17 +9680,21 @@ enum skl_power_gate {
  * CNL Clocks
  */
 #define DPCLKA_CFGCR0				_MMIO(0x6C200)
-#define DPCLKA_CFGCR0_ICL			_MMIO(0x164280)
 #define  DPCLKA_CFGCR0_DDI_CLK_OFF(port)	(1 << ((port) ==  PORT_F ? 23 : \
 						      (port) + 10))
-#define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port)   (1 << ((port) + 10))
-#define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \
-						      21 : (tc_port) + 12))
 #define  DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)	((port) == PORT_F ? 21 : \
 						(port) * 2)
 #define  DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port)	(3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
 #define  DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port)	((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
 
+#define DPCLKA_CFGCR0_ICL			_MMIO(0x164280)
+#define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)	(1 << _PICK(phy, 10, 11, 24))
+#define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \
+						      21 : (tc_port) + 12))
+#define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)	((phy) * 2)
+#define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)	(3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
+#define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy)	((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
+
 /* CNL PLL */
 #define DPLL0_ENABLE		0x46010
 #define DPLL1_ENABLE		0x46014
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1d58f7ec5d84..8c174bb767ba 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1473,8 +1473,8 @@ void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
 void intel_encoder_destroy(struct drm_encoder *encoder);
 struct drm_display_mode *
 intel_encoder_current_mode(struct intel_encoder *encoder);
-bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
-bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
+bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy);
+bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy);
 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
 			      enum port port);
 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
-- 
2.17.2

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[PATCH v3 5/5] drm/i915/ehl: Enable DDI-D

[Matt Roper]

EHL has four DDI's (DDI-A and DDI-D share combo PHY A).

Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index afbfef2fffde..50ad21df2f80 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15127,6 +15127,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
 		intel_ddi_init(dev_priv, PORT_A);
 		intel_ddi_init(dev_priv, PORT_B);
 		intel_ddi_init(dev_priv, PORT_C);
+		intel_ddi_init(dev_priv, PORT_D);
 		icl_dsi_init(dev_priv);
 	} else if (INTEL_GEN(dev_priv) >= 11) {
 		intel_ddi_init(dev_priv, PORT_A);
-- 
2.17.2

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Re: [PATCH v3 5/5] drm/i915/ehl: Enable DDI-D

[Souza, Jose]

On Tue, 2019-06-25 at 17:03 -0700, Matt Roper wrote:
> EHL has four DDI's (DDI-A and DDI-D share combo PHY A).

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> 
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index afbfef2fffde..50ad21df2f80 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -15127,6 +15127,7 @@ static void intel_setup_outputs(struct
> drm_i915_private *dev_priv)
>  		intel_ddi_init(dev_priv, PORT_A);
>  		intel_ddi_init(dev_priv, PORT_B);
>  		intel_ddi_init(dev_priv, PORT_C);
> +		intel_ddi_init(dev_priv, PORT_D);
>  		icl_dsi_init(dev_priv);
>  	} else if (INTEL_GEN(dev_priv) >= 11) {
>  		intel_ddi_init(dev_priv, PORT_A);
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✗ Fi.CI.CHECKPATCH: warning for EHL port programming (rev3)

[Patchwork]

== Series Details ==

Series: EHL port programming (rev3)
URL   : https://patchwork.freedesktop.org/series/62492/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
1ef07c06355c drm/i915/icl: Drop port parameter to icl_get_combo_buf_trans()
-:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#10: 
References: 9659c1af451a ("drm/i915/icl: combo port vswing programming changes per BSPEC")

-:10: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 9659c1af451a ("drm/i915/icl: combo port vswing programming changes per BSPEC")'
#10: 
References: 9659c1af451a ("drm/i915/icl: combo port vswing programming changes per BSPEC")

total: 1 errors, 1 warnings, 0 checks, 36 lines checked
a737be214a1b drm/i915/ehl: Add third combo PHY offset
f52bd63ed2e0 drm/i915/ehl: Don't program PHY_MISC on EHL PHY C
1d39822bbc7c drm/i915/gen11: Start distinguishing 'phy' from 'port'
-:182: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__phy' - possible side-effects?
#182: FILE: drivers/gpu/drm/i915/display/intel_combo_phy.c:9:
+#define for_each_combo_phy(__dev_priv, __phy) \
+	for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++)	\
+		for_each_if(intel_phy_is_combo(__dev_priv, __phy))

-:189: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__phy' - possible side-effects?
#189: FILE: drivers/gpu/drm/i915/display/intel_combo_phy.c:13:
+#define for_each_combo_phy_reverse(__dev_priv, __phy) \
+	for ((__phy) = I915_MAX_PHYS; (__phy)-- > PHY_A;) \
+		for_each_if(intel_phy_is_combo(__dev_priv, __phy))

-:1021: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'tc_port' - possible side-effects?
#1021: FILE: drivers/gpu/drm/i915/i915_reg.h:9692:
+#define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \
+						      21 : (tc_port) + 12))

-:1024: WARNING:LONG_LINE: line over 100 characters
#1024: FILE: drivers/gpu/drm/i915/i915_reg.h:9695:
+#define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)	(3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))

-:1025: WARNING:LONG_LINE: line over 100 characters
#1025: FILE: drivers/gpu/drm/i915/i915_reg.h:9696:
+#define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy)	((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))

total: 0 errors, 2 warnings, 3 checks, 879 lines checked
823c40cd4f30 drm/i915/ehl: Enable DDI-D

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✓ Fi.CI.BAT: success for EHL port programming (rev3)

[Patchwork]

== Series Details ==

Series: EHL port programming (rev3)
URL   : https://patchwork.freedesktop.org/series/62492/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6351 -> Patchwork_13432
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/

Known issues
------------

  Here are the changes found in Patchwork_13432 that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@debugfs_test@read_all_entries:
    - fi-ilk-650:         [DMESG-WARN][1] ([fdo#106387]) -> [PASS][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/fi-ilk-650/igt@debugfs_test@read_all_entries.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/fi-ilk-650/igt@debugfs_test@read_all_entries.html

  * igt@gem_ctx_create@basic-files:
    - fi-icl-u3:          [INCOMPLETE][3] ([fdo#107713] / [fdo#109100]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/fi-icl-u3/igt@gem_ctx_create@basic-files.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/fi-icl-u3/igt@gem_ctx_create@basic-files.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-icl-u2:          [FAIL][5] ([fdo#103167]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html

  
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#106387]: https://bugs.freedesktop.org/show_bug.cgi?id=106387
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100


Participating hosts (51 -> 45)
------------------------------

  Additional (2): fi-gdg-551 fi-bwr-2160 
  Missing    (8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-icl-y fi-icl-dsi fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_6351 -> Patchwork_13432

  CI_DRM_6351: 841a5e9b5d0b617cea39d2de4492cf3474d3f555 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5068: 15ad664534413628f06c0f172aac11598bfdb895 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13432: 823c40cd4f30b2666d77f5b217ad0e810e500d26 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

823c40cd4f30 drm/i915/ehl: Enable DDI-D
1d39822bbc7c drm/i915/gen11: Start distinguishing 'phy' from 'port'
f52bd63ed2e0 drm/i915/ehl: Don't program PHY_MISC on EHL PHY C
a737be214a1b drm/i915/ehl: Add third combo PHY offset
1ef07c06355c drm/i915/icl: Drop port parameter to icl_get_combo_buf_trans()

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/
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✓ Fi.CI.IGT: success for EHL port programming (rev3)

[Patchwork]

== Series Details ==

Series: EHL port programming (rev3)
URL   : https://patchwork.freedesktop.org/series/62492/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6351_full -> Patchwork_13432_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_13432_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_isolation@bcs0-s3:
    - shard-apl:          [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-apl8/igt@gem_ctx_isolation@bcs0-s3.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-apl5/igt@gem_ctx_isolation@bcs0-s3.html

  * igt@gem_eio@wait-wedge-10ms:
    - shard-apl:          [PASS][3] -> [DMESG-WARN][4] ([fdo#110913 ]) +3 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-apl8/igt@gem_eio@wait-wedge-10ms.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-apl4/igt@gem_eio@wait-wedge-10ms.html

  * igt@gem_exec_balancer@smoke:
    - shard-iclb:         [PASS][5] -> [SKIP][6] ([fdo#110854])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-iclb2/igt@gem_exec_balancer@smoke.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-iclb7/igt@gem_exec_balancer@smoke.html

  * igt@gem_partial_pwrite_pread@writes-after-reads-display:
    - shard-hsw:          [PASS][7] -> [DMESG-WARN][8] ([fdo#110789] / [fdo#110913 ]) +2 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-hsw1/igt@gem_partial_pwrite_pread@writes-after-reads-display.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-hsw7/igt@gem_partial_pwrite_pread@writes-after-reads-display.html

  * igt@gem_partial_pwrite_pread@writes-after-reads-uncached:
    - shard-kbl:          [PASS][9] -> [DMESG-WARN][10] ([fdo#110913 ]) +2 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-kbl1/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-kbl1/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html

  * igt@gem_persistent_relocs@forked-faulting-reloc-thrash-inactive:
    - shard-glk:          [PASS][11] -> [DMESG-WARN][12] ([fdo#110913 ])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-glk6/igt@gem_persistent_relocs@forked-faulting-reloc-thrash-inactive.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-glk4/igt@gem_persistent_relocs@forked-faulting-reloc-thrash-inactive.html

  * igt@i915_pm_rc6_residency@rc6-accuracy:
    - shard-kbl:          [PASS][13] -> [SKIP][14] ([fdo#109271])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-kbl7/igt@i915_pm_rc6_residency@rc6-accuracy.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-kbl7/igt@i915_pm_rc6_residency@rc6-accuracy.html

  * igt@i915_selftest@mock_requests:
    - shard-skl:          [PASS][15] -> [INCOMPLETE][16] ([fdo#110550])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-skl9/igt@i915_selftest@mock_requests.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-skl7/igt@i915_selftest@mock_requests.html

  * igt@kms_flip@2x-plain-flip:
    - shard-hsw:          [PASS][17] -> [SKIP][18] ([fdo#109271]) +21 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-hsw8/igt@kms_flip@2x-plain-flip.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-hsw1/igt@kms_flip@2x-plain-flip.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-skl:          [PASS][19] -> [FAIL][20] ([fdo#105363])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-skl10/igt@kms_flip@flip-vs-expired-vblank.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-skl4/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
    - shard-iclb:         [PASS][21] -> [FAIL][22] ([fdo#103167]) +3 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-cpu:
    - shard-skl:          [PASS][23] -> [FAIL][24] ([fdo#103167] / [fdo#110379])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-skl5/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-cpu.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-skl8/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-cpu.html

  * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
    - shard-skl:          [PASS][25] -> [FAIL][26] ([fdo#108145])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html

  * igt@kms_psr@psr2_primary_mmap_gtt:
    - shard-iclb:         [PASS][27] -> [SKIP][28] ([fdo#109441])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-iclb3/igt@kms_psr@psr2_primary_mmap_gtt.html

  
#### Possible fixes ####

  * igt@gem_eio@context-create:
    - shard-hsw:          [DMESG-WARN][29] ([fdo#110789] / [fdo#110913 ]) -> [PASS][30] +2 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-hsw7/igt@gem_eio@context-create.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-hsw6/igt@gem_eio@context-create.html

  * igt@gem_exec_schedule@preempt-queue-chain-bsd:
    - shard-apl:          [INCOMPLETE][31] ([fdo#103927]) -> [PASS][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-apl2/igt@gem_exec_schedule@preempt-queue-chain-bsd.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-apl8/igt@gem_exec_schedule@preempt-queue-chain-bsd.html

  * igt@gem_partial_pwrite_pread@writes-after-reads-display:
    - shard-apl:          [DMESG-WARN][33] ([fdo#110913 ]) -> [PASS][34] +2 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-apl8/igt@gem_partial_pwrite_pread@writes-after-reads-display.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-apl4/igt@gem_partial_pwrite_pread@writes-after-reads-display.html

  * igt@gem_persistent_relocs@forked-faulting-reloc-thrashing:
    - shard-kbl:          [DMESG-WARN][35] ([fdo#110913 ]) -> [PASS][36] +2 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-kbl2/igt@gem_persistent_relocs@forked-faulting-reloc-thrashing.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-kbl6/igt@gem_persistent_relocs@forked-faulting-reloc-thrashing.html

  * igt@gem_userptr_blits@sync-unmap-after-close:
    - shard-glk:          [DMESG-WARN][37] ([fdo#110913 ]) -> [PASS][38] +2 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-glk6/igt@gem_userptr_blits@sync-unmap-after-close.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-glk4/igt@gem_userptr_blits@sync-unmap-after-close.html

  * igt@i915_pm_rpm@universal-planes-dpms:
    - shard-hsw:          [INCOMPLETE][39] ([fdo#103540] / [fdo#107807]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-hsw5/igt@i915_pm_rpm@universal-planes-dpms.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-hsw1/igt@i915_pm_rpm@universal-planes-dpms.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-skl:          [INCOMPLETE][41] ([fdo#110741]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-skl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-skl5/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic:
    - shard-hsw:          [SKIP][43] ([fdo#109271]) -> [PASS][44] +21 similar issues
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-hsw1/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-hsw8/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic.html

  * igt@kms_flip@2x-flip-vs-expired-vblank:
    - shard-glk:          [FAIL][45] ([fdo#105363]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-glk3/igt@kms_flip@2x-flip-vs-expired-vblank.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank.html

  * igt@kms_flip@2x-modeset-vs-vblank-race:
    - shard-glk:          [FAIL][47] ([fdo#103060]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-glk9/igt@kms_flip@2x-modeset-vs-vblank-race.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-glk3/igt@kms_flip@2x-modeset-vs-vblank-race.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-iclb:         [FAIL][49] ([fdo#105363]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-iclb5/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-iclb7/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
    - shard-iclb:         [FAIL][51] ([fdo#103167]) -> [PASS][52] +10 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
    - shard-skl:          [FAIL][53] ([fdo#103167]) -> [PASS][54] +1 similar issue
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-skl1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-skl8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-wc:
    - shard-iclb:         [DMESG-WARN][55] ([fdo#110913 ]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-iclb1/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-wc.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-iclb1/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-wc.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
    - shard-skl:          [INCOMPLETE][57] ([fdo#104108]) -> [PASS][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-skl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-skl5/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
    - shard-skl:          [FAIL][59] ([fdo#108145]) -> [PASS][60] +1 similar issue
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-skl8/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html

  * igt@kms_plane_lowres@pipe-a-tiling-x:
    - shard-iclb:         [FAIL][61] ([fdo#103166]) -> [PASS][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-iclb2/igt@kms_plane_lowres@pipe-a-tiling-x.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-iclb4/igt@kms_plane_lowres@pipe-a-tiling-x.html

  * igt@kms_psr2_su@frontbuffer:
    - shard-iclb:         [SKIP][63] ([fdo#109642]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-iclb6/igt@kms_psr2_su@frontbuffer.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-iclb2/igt@kms_psr2_su@frontbuffer.html

  * igt@kms_psr@no_drrs:
    - shard-iclb:         [FAIL][65] ([fdo#108341]) -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-iclb1/igt@kms_psr@no_drrs.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-iclb3/igt@kms_psr@no_drrs.html

  * igt@kms_sysfs_edid_timing:
    - shard-iclb:         [FAIL][67] ([fdo#100047]) -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-iclb3/igt@kms_sysfs_edid_timing.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-iclb1/igt@kms_sysfs_edid_timing.html

  * igt@kms_vblank@pipe-a-query-busy-hang:
    - shard-iclb:         [INCOMPLETE][69] ([fdo#107713]) -> [PASS][70]
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-iclb7/igt@kms_vblank@pipe-a-query-busy-hang.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-iclb1/igt@kms_vblank@pipe-a-query-busy-hang.html

  * igt@kms_vblank@pipe-a-query-forked-busy-hang:
    - shard-snb:          [SKIP][71] ([fdo#109271]) -> [PASS][72] +9 similar issues
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-snb5/igt@kms_vblank@pipe-a-query-forked-busy-hang.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-snb2/igt@kms_vblank@pipe-a-query-forked-busy-hang.html

  
#### Warnings ####

  * igt@kms_vblank@pipe-c-wait-forked-busy-hang:
    - shard-snb:          [SKIP][73] ([fdo#109271]) -> [SKIP][74] ([fdo#109271] / [fdo#109278])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-snb5/igt@kms_vblank@pipe-c-wait-forked-busy-hang.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-snb2/igt@kms_vblank@pipe-c-wait-forked-busy-hang.html

  
  [fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
  [fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#110379]: https://bugs.freedesktop.org/show_bug.cgi?id=110379
  [fdo#110550]: https://bugs.freedesktop.org/show_bug.cgi?id=110550
  [fdo#110741]: https://bugs.freedesktop.org/show_bug.cgi?id=110741
  [fdo#110789]: https://bugs.freedesktop.org/show_bug.cgi?id=110789
  [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
  [fdo#110913 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110913 


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_6351 -> Patchwork_13432

  CI_DRM_6351: 841a5e9b5d0b617cea39d2de4492cf3474d3f555 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5068: 15ad664534413628f06c0f172aac11598bfdb895 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13432: 823c40cd4f30b2666d77f5b217ad0e810e500d26 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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Re: ✓ Fi.CI.IGT: success for EHL port programming (rev3)

[Matt Roper]

On Wed, Jun 26, 2019 at 11:05:08AM +0000, Patchwork wrote:
> == Series Details ==
> 
> Series: EHL port programming (rev3)
> URL   : https://patchwork.freedesktop.org/series/62492/
> State : success
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_6351_full -> Patchwork_13432_full
> ====================================================
> 
> Summary
> -------
> 
>   **SUCCESS**
> 
>   No regressions found.
> 

Patches #1-3 of this series applied to dinq.  Thanks Clint and Jose for
the reviews.


Matt

>   
> 
> Known issues
> ------------
> 
>   Here are the changes found in Patchwork_13432_full that come from known issues:
> 
> ### IGT changes ###
> 
> #### Issues hit ####
> 
>   * igt@gem_ctx_isolation@bcs0-s3:
>     - shard-apl:          [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +1 similar issue
>    [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-apl8/igt@gem_ctx_isolation@bcs0-s3.html
>    [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-apl5/igt@gem_ctx_isolation@bcs0-s3.html
> 
>   * igt@gem_eio@wait-wedge-10ms:
>     - shard-apl:          [PASS][3] -> [DMESG-WARN][4] ([fdo#110913 ]) +3 similar issues
>    [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-apl8/igt@gem_eio@wait-wedge-10ms.html
>    [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-apl4/igt@gem_eio@wait-wedge-10ms.html
> 
>   * igt@gem_exec_balancer@smoke:
>     - shard-iclb:         [PASS][5] -> [SKIP][6] ([fdo#110854])
>    [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-iclb2/igt@gem_exec_balancer@smoke.html
>    [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-iclb7/igt@gem_exec_balancer@smoke.html
> 
>   * igt@gem_partial_pwrite_pread@writes-after-reads-display:
>     - shard-hsw:          [PASS][7] -> [DMESG-WARN][8] ([fdo#110789] / [fdo#110913 ]) +2 similar issues
>    [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-hsw1/igt@gem_partial_pwrite_pread@writes-after-reads-display.html
>    [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-hsw7/igt@gem_partial_pwrite_pread@writes-after-reads-display.html
> 
>   * igt@gem_partial_pwrite_pread@writes-after-reads-uncached:
>     - shard-kbl:          [PASS][9] -> [DMESG-WARN][10] ([fdo#110913 ]) +2 similar issues
>    [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-kbl1/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
>    [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-kbl1/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
> 
>   * igt@gem_persistent_relocs@forked-faulting-reloc-thrash-inactive:
>     - shard-glk:          [PASS][11] -> [DMESG-WARN][12] ([fdo#110913 ])
>    [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-glk6/igt@gem_persistent_relocs@forked-faulting-reloc-thrash-inactive.html
>    [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-glk4/igt@gem_persistent_relocs@forked-faulting-reloc-thrash-inactive.html
> 
>   * igt@i915_pm_rc6_residency@rc6-accuracy:
>     - shard-kbl:          [PASS][13] -> [SKIP][14] ([fdo#109271])
>    [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-kbl7/igt@i915_pm_rc6_residency@rc6-accuracy.html
>    [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-kbl7/igt@i915_pm_rc6_residency@rc6-accuracy.html
> 
>   * igt@i915_selftest@mock_requests:
>     - shard-skl:          [PASS][15] -> [INCOMPLETE][16] ([fdo#110550])
>    [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-skl9/igt@i915_selftest@mock_requests.html
>    [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-skl7/igt@i915_selftest@mock_requests.html
> 
>   * igt@kms_flip@2x-plain-flip:
>     - shard-hsw:          [PASS][17] -> [SKIP][18] ([fdo#109271]) +21 similar issues
>    [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-hsw8/igt@kms_flip@2x-plain-flip.html
>    [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-hsw1/igt@kms_flip@2x-plain-flip.html
> 
>   * igt@kms_flip@flip-vs-expired-vblank:
>     - shard-skl:          [PASS][19] -> [FAIL][20] ([fdo#105363])
>    [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-skl10/igt@kms_flip@flip-vs-expired-vblank.html
>    [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-skl4/igt@kms_flip@flip-vs-expired-vblank.html
> 
>   * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
>     - shard-iclb:         [PASS][21] -> [FAIL][22] ([fdo#103167]) +3 similar issues
>    [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
>    [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
> 
>   * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-cpu:
>     - shard-skl:          [PASS][23] -> [FAIL][24] ([fdo#103167] / [fdo#110379])
>    [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-skl5/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-cpu.html
>    [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-skl8/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-cpu.html
> 
>   * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
>     - shard-skl:          [PASS][25] -> [FAIL][26] ([fdo#108145])
>    [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
>    [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
> 
>   * igt@kms_psr@psr2_primary_mmap_gtt:
>     - shard-iclb:         [PASS][27] -> [SKIP][28] ([fdo#109441])
>    [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html
>    [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-iclb3/igt@kms_psr@psr2_primary_mmap_gtt.html
> 
>   
> #### Possible fixes ####
> 
>   * igt@gem_eio@context-create:
>     - shard-hsw:          [DMESG-WARN][29] ([fdo#110789] / [fdo#110913 ]) -> [PASS][30] +2 similar issues
>    [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-hsw7/igt@gem_eio@context-create.html
>    [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-hsw6/igt@gem_eio@context-create.html
> 
>   * igt@gem_exec_schedule@preempt-queue-chain-bsd:
>     - shard-apl:          [INCOMPLETE][31] ([fdo#103927]) -> [PASS][32]
>    [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-apl2/igt@gem_exec_schedule@preempt-queue-chain-bsd.html
>    [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-apl8/igt@gem_exec_schedule@preempt-queue-chain-bsd.html
> 
>   * igt@gem_partial_pwrite_pread@writes-after-reads-display:
>     - shard-apl:          [DMESG-WARN][33] ([fdo#110913 ]) -> [PASS][34] +2 similar issues
>    [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-apl8/igt@gem_partial_pwrite_pread@writes-after-reads-display.html
>    [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-apl4/igt@gem_partial_pwrite_pread@writes-after-reads-display.html
> 
>   * igt@gem_persistent_relocs@forked-faulting-reloc-thrashing:
>     - shard-kbl:          [DMESG-WARN][35] ([fdo#110913 ]) -> [PASS][36] +2 similar issues
>    [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-kbl2/igt@gem_persistent_relocs@forked-faulting-reloc-thrashing.html
>    [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-kbl6/igt@gem_persistent_relocs@forked-faulting-reloc-thrashing.html
> 
>   * igt@gem_userptr_blits@sync-unmap-after-close:
>     - shard-glk:          [DMESG-WARN][37] ([fdo#110913 ]) -> [PASS][38] +2 similar issues
>    [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-glk6/igt@gem_userptr_blits@sync-unmap-after-close.html
>    [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-glk4/igt@gem_userptr_blits@sync-unmap-after-close.html
> 
>   * igt@i915_pm_rpm@universal-planes-dpms:
>     - shard-hsw:          [INCOMPLETE][39] ([fdo#103540] / [fdo#107807]) -> [PASS][40]
>    [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-hsw5/igt@i915_pm_rpm@universal-planes-dpms.html
>    [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-hsw1/igt@i915_pm_rpm@universal-planes-dpms.html
> 
>   * igt@kms_cursor_crc@pipe-c-cursor-suspend:
>     - shard-skl:          [INCOMPLETE][41] ([fdo#110741]) -> [PASS][42]
>    [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-skl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
>    [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-skl5/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
> 
>   * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic:
>     - shard-hsw:          [SKIP][43] ([fdo#109271]) -> [PASS][44] +21 similar issues
>    [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-hsw1/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic.html
>    [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-hsw8/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic.html
> 
>   * igt@kms_flip@2x-flip-vs-expired-vblank:
>     - shard-glk:          [FAIL][45] ([fdo#105363]) -> [PASS][46]
>    [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-glk3/igt@kms_flip@2x-flip-vs-expired-vblank.html
>    [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank.html
> 
>   * igt@kms_flip@2x-modeset-vs-vblank-race:
>     - shard-glk:          [FAIL][47] ([fdo#103060]) -> [PASS][48]
>    [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-glk9/igt@kms_flip@2x-modeset-vs-vblank-race.html
>    [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-glk3/igt@kms_flip@2x-modeset-vs-vblank-race.html
> 
>   * igt@kms_flip@flip-vs-expired-vblank-interruptible:
>     - shard-iclb:         [FAIL][49] ([fdo#105363]) -> [PASS][50]
>    [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-iclb5/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
>    [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-iclb7/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
> 
>   * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
>     - shard-iclb:         [FAIL][51] ([fdo#103167]) -> [PASS][52] +10 similar issues
>    [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
>    [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
>     - shard-skl:          [FAIL][53] ([fdo#103167]) -> [PASS][54] +1 similar issue
>    [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-skl1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
>    [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-skl8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
> 
>   * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-wc:
>     - shard-iclb:         [DMESG-WARN][55] ([fdo#110913 ]) -> [PASS][56]
>    [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-iclb1/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-wc.html
>    [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-iclb1/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-wc.html
> 
>   * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
>     - shard-skl:          [INCOMPLETE][57] ([fdo#104108]) -> [PASS][58]
>    [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-skl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
>    [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-skl5/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
> 
>   * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
>     - shard-skl:          [FAIL][59] ([fdo#108145]) -> [PASS][60] +1 similar issue
>    [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-skl8/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
>    [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
> 
>   * igt@kms_plane_lowres@pipe-a-tiling-x:
>     - shard-iclb:         [FAIL][61] ([fdo#103166]) -> [PASS][62]
>    [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-iclb2/igt@kms_plane_lowres@pipe-a-tiling-x.html
>    [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-iclb4/igt@kms_plane_lowres@pipe-a-tiling-x.html
> 
>   * igt@kms_psr2_su@frontbuffer:
>     - shard-iclb:         [SKIP][63] ([fdo#109642]) -> [PASS][64]
>    [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-iclb6/igt@kms_psr2_su@frontbuffer.html
>    [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
> 
>   * igt@kms_psr@no_drrs:
>     - shard-iclb:         [FAIL][65] ([fdo#108341]) -> [PASS][66]
>    [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-iclb1/igt@kms_psr@no_drrs.html
>    [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-iclb3/igt@kms_psr@no_drrs.html
> 
>   * igt@kms_sysfs_edid_timing:
>     - shard-iclb:         [FAIL][67] ([fdo#100047]) -> [PASS][68]
>    [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-iclb3/igt@kms_sysfs_edid_timing.html
>    [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-iclb1/igt@kms_sysfs_edid_timing.html
> 
>   * igt@kms_vblank@pipe-a-query-busy-hang:
>     - shard-iclb:         [INCOMPLETE][69] ([fdo#107713]) -> [PASS][70]
>    [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-iclb7/igt@kms_vblank@pipe-a-query-busy-hang.html
>    [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-iclb1/igt@kms_vblank@pipe-a-query-busy-hang.html
> 
>   * igt@kms_vblank@pipe-a-query-forked-busy-hang:
>     - shard-snb:          [SKIP][71] ([fdo#109271]) -> [PASS][72] +9 similar issues
>    [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-snb5/igt@kms_vblank@pipe-a-query-forked-busy-hang.html
>    [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-snb2/igt@kms_vblank@pipe-a-query-forked-busy-hang.html
> 
>   
> #### Warnings ####
> 
>   * igt@kms_vblank@pipe-c-wait-forked-busy-hang:
>     - shard-snb:          [SKIP][73] ([fdo#109271]) -> [SKIP][74] ([fdo#109271] / [fdo#109278])
>    [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6351/shard-snb5/igt@kms_vblank@pipe-c-wait-forked-busy-hang.html
>    [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/shard-snb2/igt@kms_vblank@pipe-c-wait-forked-busy-hang.html
> 
>   
>   [fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
>   [fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
>   [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
>   [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
>   [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
>   [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
>   [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
>   [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
>   [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
>   [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
>   [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
>   [fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341
>   [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
>   [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
>   [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
>   [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
>   [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
>   [fdo#110379]: https://bugs.freedesktop.org/show_bug.cgi?id=110379
>   [fdo#110550]: https://bugs.freedesktop.org/show_bug.cgi?id=110550
>   [fdo#110741]: https://bugs.freedesktop.org/show_bug.cgi?id=110741
>   [fdo#110789]: https://bugs.freedesktop.org/show_bug.cgi?id=110789
>   [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
>   [fdo#110913 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110913 
> 
> 
> Participating hosts (10 -> 10)
> ------------------------------
> 
>   No changes in participating hosts
> 
> 
> Build changes
> -------------
> 
>   * Linux: CI_DRM_6351 -> Patchwork_13432
> 
>   CI_DRM_6351: 841a5e9b5d0b617cea39d2de4492cf3474d3f555 @ git://anongit.freedesktop.org/gfx-ci/linux
>   IGT_5068: 15ad664534413628f06c0f172aac11598bfdb895 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
>   Patchwork_13432: 823c40cd4f30b2666d77f5b217ad0e810e500d26 @ git://anongit.freedesktop.org/gfx-ci/linux
>   piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
> 
> == Logs ==
> 
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13432/

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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