* [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05
@ 2019-07-05 22:14 Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 01/42] hw/boards: Add struct CpuTopology to MachineState Eduardo Habkost
` (43 more replies)
0 siblings, 44 replies; 49+ messages in thread
From: Eduardo Habkost @ 2019-07-05 22:14 UTC (permalink / raw)
To: Peter Maydell, Paolo Bonzini, qemu-devel, Marcel Apfelbaum,
Richard Henderson
Changes v5 -> v6:
* Rebase and solve conflicts with other pull requests
(for the 4th time)
* Included Cascadelake-Server-v2 update
Changes v4 -> v5:
* Rebase and solve conflicts with commit 374f63f6810a ("Merge remote-tracking
branch 'remotes/armbru/tags/pull-monitor-2019-07-02-v2' into staging")
Changes v3 -> v4:
* Fix ppc64 "make check" failure
Changes v2 -> v3:
* Fix "make check" warnings (Igor Mammedov)
* Fix conflicts of "hw/arm: Replace global smp variables with
machine smp properties" with recent arm changes (Eduardo Habkost)
* x86 versioned CPU models (Eduardo Habkost)
* SnowRidge CPU model (Paul Lai)
* Add deprecation information to query-machines (Eduardo Habkost)
Changes v1 -> v2:
* Fix s390x build failure
The following changes since commit d2c5f91ca944aaade642624397e1853801bbc744:
Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-pull-request' into staging (2019-07-05 16:16:15 +0100)
are available in the Git repository at:
git://github.com/ehabkost/qemu.git tags/machine-next-pull-request
for you to fetch changes up to af135030e3405af5ce234a9f92cf8cc4e55fec96:
tests: use -numa memdev option in tests instead of legacy 'mem' option (2019-07-05 17:12:45 -0300)
----------------------------------------------------------------
Machine and x86 queue, 2019-07-05
* CPU die topology support (Like Xu)
* Deprecation of features (Igor Mammedov):
* 'mem' parameter of '-numa node' option
* implict memory distribution between NUMA nodes
* deprecate -mem-path fallback to anonymous RAM
* x86 versioned CPU models (Eduardo Habkost)
* SnowRidge CPU model (Paul Lai)
* Add deprecation information to query-machines (Eduardo Habkost)
* Other i386 fixes
----------------------------------------------------------------
Queue for Machine Core patches
Eduardo Habkost (15):
hppa: Delete unused hppa_cpu_list() function
i386: Don't print warning if phys-bits was set automatically
i386: Fix signedness of hyperv_spinlock_attempts
i386: Remove unused host_cpudef variable
qmp: Add deprecation information to query-machines
qmp: Add "alias-of" field to query-cpu-definitions
i386: Add x-force-features option for testing
i386: Get model-id from CPU object on "-cpu help"
i386: Register versioned CPU models
i386: Define -IBRS, -noTSX, -IBRS versions of CPU models
i386: Replace -noTSX, -IBRS, -IBPB CPU models with aliases
i386: Make unversioned CPU models be aliases
docs: Deprecate CPU model runnability guarantees
i386: Add Cascadelake-Server-v2 CPU model
numa: Make deprecation warnings conditional on !qtest_enabled()
Igor Mammedov (7):
pc: fix possible NULL pointer dereference in
pc_machine_get_device_memory_region_size()
machine: show if CLI option '-numa node,mem' is supported in QAPI
schema
numa: deprecate 'mem' parameter of '-numa node' option
numa: deprecate implict memory distribution between nodes
deprecate -mem-path fallback to anonymous RAM
numa: allow memory-less nodes when using memdev as backend
tests: use -numa memdev option in tests instead of legacy 'mem' option
Like Xu (17):
hw/boards: Add struct CpuTopology to MachineState
machine: Refactor smp-related call chains to pass MachineState
general: Replace global smp variables with smp machine properties
hw/ppc: Replace global smp variables with machine smp properties
hw/riscv: Replace global smp variables with machine smp properties
hw/s390x: Replace global smp variables with machine smp properties
hw/i386: Replace global smp variables with machine smp properties
hw/arm: Replace global smp variables with machine smp properties
hw: Replace global smp variables with MachineState for all remaining
archs
vl.c: Replace smp global variables with smp machine properties
i386: Add die-level cpu topology to x86CPU on PCMachine
hw/i386: Adjust nr_dies with configured smp_dies for PCMachine
i386/cpu: Consolidate die-id validity in smp context
i386: Update new x86_apicid parsing rules with die_offset support
target/i386: Add CPUID.1F generation support for multi-dies PCMachine
machine: Refactor smp_parse() in vl.c as MachineClass::smp_parse()
vl.c: Add -smp, dies=* command line support and update doc
Paul Lai (1):
i386: Introduce SnowRidge CPU model
Roman Kagan (1):
i386: make 'hv-spinlocks' a regular uint32 property
Wei Yang (1):
x86/cpu: use FeatureWordArray to define filtered_features
qapi/machine-target.json | 9 +-
qapi/machine.json | 17 +-
include/hw/boards.h | 27 +-
include/hw/firmware/smbios.h | 5 +-
include/hw/i386/pc.h | 8 +-
include/hw/i386/topology.h | 76 +-
target/hppa/cpu.h | 2 -
target/i386/cpu-qom.h | 10 +-
target/i386/cpu.h | 36 +-
accel/kvm/kvm-all.c | 4 +-
backends/hostmem.c | 6 +-
cpus.c | 7 +-
exec.c | 3 +-
gdbstub.c | 4 +
hw/alpha/dp264.c | 1 +
hw/arm/aspeed.c | 2 +-
hw/arm/fsl-imx6.c | 6 +-
hw/arm/fsl-imx6ul.c | 6 +-
hw/arm/fsl-imx7.c | 7 +-
hw/arm/highbank.c | 1 +
hw/arm/mcimx6ul-evk.c | 2 +-
hw/arm/mcimx7d-sabre.c | 2 +-
hw/arm/raspi.c | 4 +-
hw/arm/realview.c | 1 +
hw/arm/sabrelite.c | 2 +-
hw/arm/sbsa-ref.c | 4 +
hw/arm/vexpress.c | 16 +-
hw/arm/virt.c | 11 +-
hw/arm/xlnx-zynqmp.c | 16 +-
hw/core/machine-hmp-cmds.c | 3 +
hw/core/machine-qmp-cmds.c | 4 +-
hw/core/machine.c | 88 ++
hw/core/numa.c | 36 +-
hw/cpu/core.c | 4 +-
hw/hppa/machine.c | 4 +-
hw/i386/acpi-build.c | 13 +-
hw/i386/kvmvapic.c | 7 +-
hw/i386/pc.c | 178 ++-
hw/i386/pc_piix.c | 4 +
hw/i386/pc_q35.c | 4 +
hw/i386/xen/xen-hvm.c | 4 +
hw/mips/boston.c | 2 +-
hw/mips/mips_malta.c | 24 +-
hw/openrisc/openrisc_sim.c | 1 +
hw/ppc/e500.c | 3 +
hw/ppc/mac_newworld.c | 3 +-
hw/ppc/mac_oldworld.c | 3 +-
hw/ppc/pnv.c | 9 +-
hw/ppc/prep.c | 4 +-
hw/ppc/spapr.c | 38 +-
hw/ppc/spapr_rtas.c | 4 +-
hw/riscv/sifive_e.c | 6 +-
hw/riscv/sifive_plic.c | 3 +
hw/riscv/sifive_u.c | 11 +-
hw/riscv/spike.c | 3 +
hw/riscv/virt.c | 1 +
hw/s390x/s390-virtio-ccw.c | 9 +-
hw/s390x/sclp.c | 2 +-
hw/smbios/smbios.c | 26 +-
hw/sparc/sun4m.c | 2 +
hw/sparc64/sun4u.c | 4 +-
hw/xtensa/sim.c | 2 +-
hw/xtensa/xtfpga.c | 1 +
migration/postcopy-ram.c | 8 +-
target/arm/cpu.c | 8 +-
target/hppa/cpu.c | 17 -
target/i386/cpu.c | 1171 ++++++++++----------
target/i386/kvm.c | 12 +
target/openrisc/sys_helper.c | 6 +-
target/s390x/cpu.c | 3 +
target/s390x/excp_helper.c | 5 +
target/s390x/kvm.c | 10 +-
tcg/tcg.c | 13 +-
tests/bios-tables-test.c | 40 +-
tests/test-x86-cpuid.c | 84 +-
vl.c | 96 +-
qemu-deprecated.texi | 52 +
qemu-options.hx | 17 +-
tests/acceptance/x86_cpu_model_versions.py | 304 +++++
79 files changed, 1701 insertions(+), 950 deletions(-)
create mode 100644 tests/acceptance/x86_cpu_model_versions.py
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply [flat|nested] 49+ messages in thread
* [Qemu-devel] [PULL v6 01/42] hw/boards: Add struct CpuTopology to MachineState
2019-07-05 22:14 [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 Eduardo Habkost
@ 2019-07-05 22:14 ` Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 02/42] machine: Refactor smp-related call chains to pass MachineState Eduardo Habkost
` (42 subsequent siblings)
43 siblings, 0 replies; 49+ messages in thread
From: Eduardo Habkost @ 2019-07-05 22:14 UTC (permalink / raw)
To: Peter Maydell, Paolo Bonzini, qemu-devel, Marcel Apfelbaum,
Richard Henderson
Cc: Like Xu
From: Like Xu <like.xu@linux.intel.com>
The cpu topology property CpuTopology is added to the MachineState
and its members are initialized with the leagcy global smp variables.
From this commit, the code in the system emulation mode is supposed to
use cpu topology variables from MachineState instead of the global ones
defined in vl.c and there is no semantic change.
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Suggested-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Like Xu <like.xu@linux.intel.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20190518205428.90532-2-like.xu@linux.intel.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
include/hw/boards.h | 15 +++++++++++++++
vl.c | 5 +++++
2 files changed, 20 insertions(+)
diff --git a/include/hw/boards.h b/include/hw/boards.h
index c6ad196b14..9597140936 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -232,6 +232,20 @@ typedef struct DeviceMemoryState {
MemoryRegion mr;
} DeviceMemoryState;
+/**
+ * CpuTopology:
+ * @cpus: the number of present logical processors on the machine
+ * @cores: the number of cores in one package
+ * @threads: the number of threads in one core
+ * @max_cpus: the maximum number of logical processors on the machine
+ */
+typedef struct CpuTopology {
+ unsigned int cpus;
+ unsigned int cores;
+ unsigned int threads;
+ unsigned int max_cpus;
+} CpuTopology;
+
/**
* MachineState:
*/
@@ -274,6 +288,7 @@ struct MachineState {
const char *cpu_type;
AccelState *accelerator;
CPUArchIdList *possible_cpus;
+ CpuTopology smp;
struct NVDIMMState *nvdimms_state;
};
diff --git a/vl.c b/vl.c
index ddefa75c1d..43113386f7 100644
--- a/vl.c
+++ b/vl.c
@@ -4014,6 +4014,11 @@ int main(int argc, char **argv, char **envp)
smp_parse(qemu_opts_find(qemu_find_opts("smp-opts"), NULL));
+ current_machine->smp.cpus = smp_cpus;
+ current_machine->smp.max_cpus = max_cpus;
+ current_machine->smp.cores = smp_cores;
+ current_machine->smp.threads = smp_threads;
+
/* sanity-check smp_cpus and max_cpus against machine_class */
if (smp_cpus < machine_class->min_cpus) {
error_report("Invalid SMP CPUs %d. The min CPUs "
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PULL v6 02/42] machine: Refactor smp-related call chains to pass MachineState
2019-07-05 22:14 [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 01/42] hw/boards: Add struct CpuTopology to MachineState Eduardo Habkost
@ 2019-07-05 22:14 ` Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 03/42] general: Replace global smp variables with smp machine properties Eduardo Habkost
` (41 subsequent siblings)
43 siblings, 0 replies; 49+ messages in thread
From: Eduardo Habkost @ 2019-07-05 22:14 UTC (permalink / raw)
To: Peter Maydell, Paolo Bonzini, qemu-devel, Marcel Apfelbaum,
Richard Henderson
Cc: Like Xu
From: Like Xu <like.xu@linux.intel.com>
To get rid of the global smp_* variables we're currently using, it's recommended
to pass MachineState in the list of incoming parameters for functions that use
global smp variables, thus some redundant parameters are dropped. It's applied
for legacy smbios_*(), *_machine_reset(), hot_add_cpu() and mips *_create_cpu().
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Like Xu <like.xu@linux.intel.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20190518205428.90532-3-like.xu@linux.intel.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
include/hw/boards.h | 4 ++--
include/hw/firmware/smbios.h | 5 +++--
include/hw/i386/pc.h | 2 +-
hw/arm/virt.c | 2 +-
hw/core/machine-qmp-cmds.c | 2 +-
hw/hppa/machine.c | 2 +-
hw/i386/acpi-build.c | 2 +-
hw/i386/pc.c | 9 ++++-----
hw/mips/mips_malta.c | 22 +++++++++++-----------
hw/ppc/pnv.c | 3 +--
hw/ppc/spapr.c | 3 +--
hw/s390x/s390-virtio-ccw.c | 6 +++---
hw/smbios/smbios.c | 26 +++++++++++++++-----------
vl.c | 2 +-
14 files changed, 46 insertions(+), 44 deletions(-)
diff --git a/include/hw/boards.h b/include/hw/boards.h
index 9597140936..d84f48c4af 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -173,8 +173,8 @@ struct MachineClass {
const char *deprecation_reason;
void (*init)(MachineState *state);
- void (*reset)(void);
- void (*hot_add_cpu)(const int64_t id, Error **errp);
+ void (*reset)(MachineState *state);
+ void (*hot_add_cpu)(MachineState *state, const int64_t id, Error **errp);
int (*kvm_type)(MachineState *machine, const char *arg);
BlockInterfaceType block_default_type;
diff --git a/include/hw/firmware/smbios.h b/include/hw/firmware/smbios.h
index 6fef32a3c9..02a0ced0a0 100644
--- a/include/hw/firmware/smbios.h
+++ b/include/hw/firmware/smbios.h
@@ -268,8 +268,9 @@ void smbios_set_cpuid(uint32_t version, uint32_t features);
void smbios_set_defaults(const char *manufacturer, const char *product,
const char *version, bool legacy_mode,
bool uuid_encoded, SmbiosEntryPointType ep_type);
-uint8_t *smbios_get_table_legacy(size_t *length);
-void smbios_get_tables(const struct smbios_phys_mem_area *mem_array,
+uint8_t *smbios_get_table_legacy(MachineState *ms, size_t *length);
+void smbios_get_tables(MachineState *ms,
+ const struct smbios_phys_mem_area *mem_array,
const unsigned int mem_array_size,
uint8_t **tables, size_t *tables_len,
uint8_t **anchor, size_t *anchor_len);
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 853502f277..de3bd32f52 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -189,7 +189,7 @@ void pc_register_ferr_irq(qemu_irq irq);
void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
void pc_cpus_init(PCMachineState *pcms);
-void pc_hot_add_cpu(const int64_t id, Error **errp);
+void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp);
void pc_guest_info_init(PCMachineState *pcms);
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index ed009fa447..7b63a924a3 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -1345,7 +1345,7 @@ static void virt_build_smbios(VirtMachineState *vms)
vmc->smbios_old_sys_ver ? "1.0" : mc->name, false,
true, SMBIOS_ENTRY_POINT_30);
- smbios_get_tables(NULL, 0, &smbios_tables, &smbios_tables_len,
+ smbios_get_tables(MACHINE(vms), NULL, 0, &smbios_tables, &smbios_tables_len,
&smbios_anchor, &smbios_anchor_len);
if (smbios_anchor) {
diff --git a/hw/core/machine-qmp-cmds.c b/hw/core/machine-qmp-cmds.c
index 1e08252af7..14dbad1d6e 100644
--- a/hw/core/machine-qmp-cmds.c
+++ b/hw/core/machine-qmp-cmds.c
@@ -264,7 +264,7 @@ void qmp_cpu_add(int64_t id, Error **errp)
mc = MACHINE_GET_CLASS(current_machine);
if (mc->hot_add_cpu) {
- mc->hot_add_cpu(id, errp);
+ mc->hot_add_cpu(current_machine, id, errp);
} else {
error_setg(errp, "Not supported");
}
diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c
index d1b1d3caa4..416e67bab1 100644
--- a/hw/hppa/machine.c
+++ b/hw/hppa/machine.c
@@ -240,7 +240,7 @@ static void machine_hppa_init(MachineState *machine)
cpu[0]->env.gr[21] = smp_cpus;
}
-static void hppa_machine_reset(void)
+static void hppa_machine_reset(MachineState *ms)
{
int i;
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 31a1c1e3ad..8ae7d88b11 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -184,7 +184,7 @@ static void acpi_get_pm_info(AcpiPmInfo *pm)
pm->pcihp_io_len = 0;
assert(obj);
- init_common_fadt_data(obj, &pm->fadt);
+ init_common_fadt_data(machine, obj, &pm->fadt);
if (piix) {
/* w2k requires FADT(rev1) or it won't boot, keep PC compatible */
pm->fadt.rev = 1;
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index b380bd7d74..0b0b55afd2 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -954,7 +954,7 @@ static void pc_build_smbios(PCMachineState *pcms)
/* tell smbios about cpuid version and features */
smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]);
- smbios_tables = smbios_get_table_legacy(&smbios_tables_len);
+ smbios_tables = smbios_get_table_legacy(ms, &smbios_tables_len);
if (smbios_tables) {
fw_cfg_add_bytes(pcms->fw_cfg, FW_CFG_SMBIOS_ENTRIES,
smbios_tables, smbios_tables_len);
@@ -971,7 +971,7 @@ static void pc_build_smbios(PCMachineState *pcms)
array_count++;
}
}
- smbios_get_tables(mem_array, array_count,
+ smbios_get_tables(ms, mem_array, array_count,
&smbios_tables, &smbios_tables_len,
&smbios_anchor, &smbios_anchor_len);
g_free(mem_array);
@@ -1526,9 +1526,8 @@ static void pc_new_cpu(const char *typename, int64_t apic_id, Error **errp)
error_propagate(errp, local_err);
}
-void pc_hot_add_cpu(const int64_t id, Error **errp)
+void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp)
{
- MachineState *ms = MACHINE(qdev_get_machine());
PCMachineState *pcms = PC_MACHINE(ms);
int64_t apic_id = x86_cpu_apic_id_from_index(pcms, id);
Error *local_err = NULL;
@@ -2684,7 +2683,7 @@ static void pc_machine_initfn(Object *obj)
pc_system_flash_create(pcms);
}
-static void pc_machine_reset(void)
+static void pc_machine_reset(MachineState *machine)
{
CPUState *cs;
X86CPU *cpu;
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 37ec89b07e..132127882d 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -1124,15 +1124,15 @@ static void main_cpu_reset(void *opaque)
}
}
-static void create_cpu_without_cps(const char *cpu_type,
+static void create_cpu_without_cps(MachineState *ms,
qemu_irq *cbus_irq, qemu_irq *i8259_irq)
{
CPUMIPSState *env;
MIPSCPU *cpu;
int i;
- for (i = 0; i < smp_cpus; i++) {
- cpu = MIPS_CPU(cpu_create(cpu_type));
+ for (i = 0; i < ms->smp.cpus; i++) {
+ cpu = MIPS_CPU(cpu_create(ms->cpu_type));
/* Init internal devices */
cpu_mips_irq_init_cpu(cpu);
@@ -1146,15 +1146,15 @@ static void create_cpu_without_cps(const char *cpu_type,
*cbus_irq = env->irq[4];
}
-static void create_cps(MaltaState *s, const char *cpu_type,
+static void create_cps(MachineState *ms, MaltaState *s,
qemu_irq *cbus_irq, qemu_irq *i8259_irq)
{
Error *err = NULL;
sysbus_init_child_obj(OBJECT(s), "cps", OBJECT(&s->cps), sizeof(s->cps),
TYPE_MIPS_CPS);
- object_property_set_str(OBJECT(&s->cps), cpu_type, "cpu-type", &err);
- object_property_set_int(OBJECT(&s->cps), smp_cpus, "num-vp", &err);
+ object_property_set_str(OBJECT(&s->cps), ms->cpu_type, "cpu-type", &err);
+ object_property_set_int(OBJECT(&s->cps), ms->smp.cpus, "num-vp", &err);
object_property_set_bool(OBJECT(&s->cps), true, "realized", &err);
if (err != NULL) {
error_report("%s", error_get_pretty(err));
@@ -1167,13 +1167,13 @@ static void create_cps(MaltaState *s, const char *cpu_type,
*cbus_irq = NULL;
}
-static void mips_create_cpu(MaltaState *s, const char *cpu_type,
+static void mips_create_cpu(MachineState *ms, MaltaState *s,
qemu_irq *cbus_irq, qemu_irq *i8259_irq)
{
- if ((smp_cpus > 1) && cpu_supports_cps_smp(cpu_type)) {
- create_cps(s, cpu_type, cbus_irq, i8259_irq);
+ if ((ms->smp.cpus > 1) && cpu_supports_cps_smp(ms->cpu_type)) {
+ create_cps(ms, s, cbus_irq, i8259_irq);
} else {
- create_cpu_without_cps(cpu_type, cbus_irq, i8259_irq);
+ create_cpu_without_cps(ms, cbus_irq, i8259_irq);
}
}
@@ -1217,7 +1217,7 @@ void mips_malta_init(MachineState *machine)
qdev_init_nofail(dev);
/* create CPU */
- mips_create_cpu(s, machine->cpu_type, &cbus_irq, &i8259_irq);
+ mips_create_cpu(machine, s, &cbus_irq, &i8259_irq);
/* allocate RAM */
if (ram_size > 2 * GiB) {
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index b87e01e5b9..e364f79efd 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -529,9 +529,8 @@ static void pnv_powerdown_notify(Notifier *n, void *opaque)
}
}
-static void pnv_reset(void)
+static void pnv_reset(MachineState *machine)
{
- MachineState *machine = MACHINE(qdev_get_machine());
PnvMachineState *pnv = PNV_MACHINE(machine);
void *fdt;
Object *obj;
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index b502fcac2e..6cf0ac400b 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1691,9 +1691,8 @@ static int spapr_reset_drcs(Object *child, void *opaque)
return 0;
}
-static void spapr_machine_reset(void)
+static void spapr_machine_reset(MachineState *machine)
{
- MachineState *machine = MACHINE(qdev_get_machine());
SpaprMachineState *spapr = SPAPR_MACHINE(machine);
PowerPCCPU *first_ppc_cpu;
uint32_t rtas_limit;
diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c
index 87b2039f1b..e09bf8f1b6 100644
--- a/hw/s390x/s390-virtio-ccw.c
+++ b/hw/s390x/s390-virtio-ccw.c
@@ -339,7 +339,7 @@ static inline void s390_do_cpu_ipl(CPUState *cs, run_on_cpu_data arg)
s390_cpu_set_state(S390_CPU_STATE_OPERATING, cpu);
}
-static void s390_machine_reset(void)
+static void s390_machine_reset(MachineState *machine)
{
enum s390_reset reset_type;
CPUState *cs, *t;
@@ -440,9 +440,9 @@ static HotplugHandler *s390_get_hotplug_handler(MachineState *machine,
return NULL;
}
-static void s390_hot_add_cpu(const int64_t id, Error **errp)
+static void s390_hot_add_cpu(MachineState *machine,
+ const int64_t id, Error **errp)
{
- MachineState *machine = MACHINE(qdev_get_machine());
ObjectClass *oc;
g_assert(machine->possible_cpus->cpus[0].cpu);
diff --git a/hw/smbios/smbios.c b/hw/smbios/smbios.c
index a36448fc8d..7bcd67b098 100644
--- a/hw/smbios/smbios.c
+++ b/hw/smbios/smbios.c
@@ -27,6 +27,7 @@
#include "sysemu/cpus.h"
#include "hw/firmware/smbios.h"
#include "hw/loader.h"
+#include "hw/boards.h"
#include "exec/cpu-common.h"
#include "smbios_build.h"
@@ -341,9 +342,10 @@ static void smbios_register_config(void)
opts_init(smbios_register_config);
-static void smbios_validate_table(void)
+static void smbios_validate_table(MachineState *ms)
{
- uint32_t expect_t4_count = smbios_legacy ? smp_cpus : smbios_smp_sockets;
+ uint32_t expect_t4_count = smbios_legacy ?
+ ms->smp.cpus : smbios_smp_sockets;
if (smbios_type4_count && smbios_type4_count != expect_t4_count) {
error_report("Expected %d SMBIOS Type 4 tables, got %d instead",
@@ -428,7 +430,7 @@ static void smbios_build_type_1_fields(void)
}
}
-uint8_t *smbios_get_table_legacy(size_t *length)
+uint8_t *smbios_get_table_legacy(MachineState *ms, size_t *length)
{
if (!smbios_legacy) {
*length = 0;
@@ -438,7 +440,7 @@ uint8_t *smbios_get_table_legacy(size_t *length)
if (!smbios_immutable) {
smbios_build_type_0_fields();
smbios_build_type_1_fields();
- smbios_validate_table();
+ smbios_validate_table(ms);
smbios_immutable = true;
}
*length = smbios_entries_len;
@@ -570,7 +572,7 @@ static void smbios_build_type_3_table(void)
SMBIOS_BUILD_TABLE_POST;
}
-static void smbios_build_type_4_table(unsigned instance)
+static void smbios_build_type_4_table(MachineState *ms, unsigned instance)
{
char sock_str[128];
@@ -597,8 +599,8 @@ static void smbios_build_type_4_table(unsigned instance)
SMBIOS_TABLE_SET_STR(4, serial_number_str, type4.serial);
SMBIOS_TABLE_SET_STR(4, asset_tag_number_str, type4.asset);
SMBIOS_TABLE_SET_STR(4, part_number_str, type4.part);
- t->core_count = t->core_enabled = smp_cores;
- t->thread_count = smp_threads;
+ t->core_count = t->core_enabled = ms->smp.cores;
+ t->thread_count = ms->smp.threads;
t->processor_characteristics = cpu_to_le16(0x02); /* Unknown */
t->processor_family2 = cpu_to_le16(0x01); /* Other */
@@ -839,7 +841,8 @@ static void smbios_entry_point_setup(void)
}
}
-void smbios_get_tables(const struct smbios_phys_mem_area *mem_array,
+void smbios_get_tables(MachineState *ms,
+ const struct smbios_phys_mem_area *mem_array,
const unsigned int mem_array_size,
uint8_t **tables, size_t *tables_len,
uint8_t **anchor, size_t *anchor_len)
@@ -858,11 +861,12 @@ void smbios_get_tables(const struct smbios_phys_mem_area *mem_array,
smbios_build_type_2_table();
smbios_build_type_3_table();
- smbios_smp_sockets = DIV_ROUND_UP(smp_cpus, smp_cores * smp_threads);
+ smbios_smp_sockets = DIV_ROUND_UP(ms->smp.cpus,
+ ms->smp.cores * ms->smp.threads);
assert(smbios_smp_sockets >= 1);
for (i = 0; i < smbios_smp_sockets; i++) {
- smbios_build_type_4_table(i);
+ smbios_build_type_4_table(ms, i);
}
smbios_build_type_11_table();
@@ -888,7 +892,7 @@ void smbios_get_tables(const struct smbios_phys_mem_area *mem_array,
smbios_build_type_38_table();
smbios_build_type_127_table();
- smbios_validate_table();
+ smbios_validate_table(ms);
smbios_entry_point_setup();
smbios_immutable = true;
}
diff --git a/vl.c b/vl.c
index 43113386f7..d657faec03 100644
--- a/vl.c
+++ b/vl.c
@@ -1580,7 +1580,7 @@ void qemu_system_reset(ShutdownCause reason)
cpu_synchronize_all_states();
if (mc && mc->reset) {
- mc->reset();
+ mc->reset(current_machine);
} else {
qemu_devices_reset();
}
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PULL v6 03/42] general: Replace global smp variables with smp machine properties
2019-07-05 22:14 [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 01/42] hw/boards: Add struct CpuTopology to MachineState Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 02/42] machine: Refactor smp-related call chains to pass MachineState Eduardo Habkost
@ 2019-07-05 22:14 ` Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 04/42] hw/ppc: Replace global smp variables with machine smp properties Eduardo Habkost
` (40 subsequent siblings)
43 siblings, 0 replies; 49+ messages in thread
From: Eduardo Habkost @ 2019-07-05 22:14 UTC (permalink / raw)
To: Peter Maydell, Paolo Bonzini, qemu-devel, Marcel Apfelbaum,
Richard Henderson
Cc: Like Xu
From: Like Xu <like.xu@linux.intel.com>
Basically, the context could get the MachineState reference via call
chains or unrecommended qdev_get_machine() in !CONFIG_USER_ONLY mode.
A local variable of the same name would be introduced in the declaration
phase out of less effort OR replace it on the spot if it's only used
once in the context. No semantic changes.
Signed-off-by: Like Xu <like.xu@linux.intel.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20190518205428.90532-4-like.xu@linux.intel.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
accel/kvm/kvm-all.c | 4 ++--
backends/hostmem.c | 6 ++++--
cpus.c | 7 +++++--
exec.c | 3 ++-
gdbstub.c | 4 ++++
hw/core/numa.c | 1 +
hw/cpu/core.c | 4 +++-
migration/postcopy-ram.c | 8 +++++++-
target/openrisc/sys_helper.c | 6 +++++-
tcg/tcg.c | 13 ++++++++++++-
10 files changed, 45 insertions(+), 11 deletions(-)
diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c
index e3cf72883b..3d86ae5052 100644
--- a/accel/kvm/kvm-all.c
+++ b/accel/kvm/kvm-all.c
@@ -1542,8 +1542,8 @@ static int kvm_init(MachineState *ms)
const char *name;
int num;
} num_cpus[] = {
- { "SMP", smp_cpus },
- { "hotpluggable", max_cpus },
+ { "SMP", ms->smp.cpus },
+ { "hotpluggable", ms->smp.max_cpus },
{ NULL, }
}, *nc = num_cpus;
int soft_vcpus_limit, hard_vcpus_limit;
diff --git a/backends/hostmem.c b/backends/hostmem.c
index 04baf479a1..463102aa15 100644
--- a/backends/hostmem.c
+++ b/backends/hostmem.c
@@ -222,6 +222,7 @@ static void host_memory_backend_set_prealloc(Object *obj, bool value,
{
Error *local_err = NULL;
HostMemoryBackend *backend = MEMORY_BACKEND(obj);
+ MachineState *ms = MACHINE(qdev_get_machine());
if (backend->force_prealloc) {
if (value) {
@@ -241,7 +242,7 @@ static void host_memory_backend_set_prealloc(Object *obj, bool value,
void *ptr = memory_region_get_ram_ptr(&backend->mr);
uint64_t sz = memory_region_size(&backend->mr);
- os_mem_prealloc(fd, ptr, sz, smp_cpus, &local_err);
+ os_mem_prealloc(fd, ptr, sz, ms->smp.cpus, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
@@ -311,6 +312,7 @@ host_memory_backend_memory_complete(UserCreatable *uc, Error **errp)
{
HostMemoryBackend *backend = MEMORY_BACKEND(uc);
HostMemoryBackendClass *bc = MEMORY_BACKEND_GET_CLASS(uc);
+ MachineState *ms = MACHINE(qdev_get_machine());
Error *local_err = NULL;
void *ptr;
uint64_t sz;
@@ -375,7 +377,7 @@ host_memory_backend_memory_complete(UserCreatable *uc, Error **errp)
*/
if (backend->prealloc) {
os_mem_prealloc(memory_region_get_fd(&backend->mr), ptr, sz,
- smp_cpus, &local_err);
+ ms->smp.cpus, &local_err);
if (local_err) {
goto out;
}
diff --git a/cpus.c b/cpus.c
index eef7b007ae..927a00aa90 100644
--- a/cpus.c
+++ b/cpus.c
@@ -54,6 +54,7 @@
#include "tcg.h"
#include "hw/nmi.h"
#include "sysemu/replay.h"
+#include "hw/boards.h"
#ifdef CONFIG_LINUX
@@ -2075,8 +2076,10 @@ static void qemu_dummy_start_vcpu(CPUState *cpu)
void qemu_init_vcpu(CPUState *cpu)
{
- cpu->nr_cores = smp_cores;
- cpu->nr_threads = smp_threads;
+ MachineState *ms = MACHINE(qdev_get_machine());
+
+ cpu->nr_cores = ms->smp.cores;
+ cpu->nr_threads = ms->smp.threads;
cpu->stopped = true;
cpu->random_seed = qemu_guest_random_seed_thread_part1();
diff --git a/exec.c b/exec.c
index e7622d1956..50ea9c5aaa 100644
--- a/exec.c
+++ b/exec.c
@@ -1874,6 +1874,7 @@ static void *file_ram_alloc(RAMBlock *block,
bool truncate,
Error **errp)
{
+ MachineState *ms = MACHINE(qdev_get_machine());
void *area;
block->page_size = qemu_fd_getpagesize(fd);
@@ -1930,7 +1931,7 @@ static void *file_ram_alloc(RAMBlock *block,
}
if (mem_prealloc) {
- os_mem_prealloc(fd, area, memory, smp_cpus, errp);
+ os_mem_prealloc(fd, area, memory, ms->smp.cpus, errp);
if (errp && *errp) {
qemu_ram_munmap(fd, area, memory);
return NULL;
diff --git a/gdbstub.c b/gdbstub.c
index 8618e34311..687c02e598 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -34,6 +34,7 @@
#include "sysemu/sysemu.h"
#include "exec/gdbstub.h"
#include "hw/cpu/cluster.h"
+#include "hw/boards.h"
#endif
#define MAX_PACKET_LENGTH 4096
@@ -1171,6 +1172,9 @@ static int gdb_handle_vcont(GDBState *s, const char *p)
CPU_FOREACH(cpu) {
max_cpus = max_cpus <= cpu->cpu_index ? cpu->cpu_index + 1 : max_cpus;
}
+#else
+ MachineState *ms = MACHINE(qdev_get_machine());
+ unsigned int max_cpus = ms->smp.max_cpus;
#endif
/* uninitialised CPUs stay 0 */
newstates = g_new0(char, max_cpus);
diff --git a/hw/core/numa.c b/hw/core/numa.c
index 66119d181b..4252af7100 100644
--- a/hw/core/numa.c
+++ b/hw/core/numa.c
@@ -60,6 +60,7 @@ static void parse_numa_node(MachineState *ms, NumaNodeOptions *node,
uint16_t nodenr;
uint16List *cpus = NULL;
MachineClass *mc = MACHINE_GET_CLASS(ms);
+ unsigned int max_cpus = ms->smp.max_cpus;
if (node->has_nodeid) {
nodenr = node->nodeid;
diff --git a/hw/cpu/core.c b/hw/cpu/core.c
index e57c73f0ce..9874c5c870 100644
--- a/hw/cpu/core.c
+++ b/hw/cpu/core.c
@@ -13,6 +13,7 @@
#include "qemu/module.h"
#include "qapi/error.h"
#include "sysemu/cpus.h"
+#include "hw/boards.h"
static void core_prop_get_core_id(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
@@ -71,13 +72,14 @@ static void core_prop_set_nr_threads(Object *obj, Visitor *v, const char *name,
static void cpu_core_instance_init(Object *obj)
{
+ MachineState *ms = MACHINE(qdev_get_machine());
CPUCore *core = CPU_CORE(obj);
object_property_add(obj, "core-id", "int", core_prop_get_core_id,
core_prop_set_core_id, NULL, NULL, NULL);
object_property_add(obj, "nr-threads", "int", core_prop_get_nr_threads,
core_prop_set_nr_threads, NULL, NULL, NULL);
- core->nr_threads = smp_threads;
+ core->nr_threads = ms->smp.threads;
}
static void cpu_core_class_init(ObjectClass *oc, void *data)
diff --git a/migration/postcopy-ram.c b/migration/postcopy-ram.c
index e2aa57a701..9faacacc9e 100644
--- a/migration/postcopy-ram.c
+++ b/migration/postcopy-ram.c
@@ -29,6 +29,7 @@
#include "sysemu/balloon.h"
#include "qemu/error-report.h"
#include "trace.h"
+#include "hw/boards.h"
/* Arbitrary limit on size of each discard command,
* keeps them around ~200 bytes
@@ -128,6 +129,8 @@ static void migration_exit_cb(Notifier *n, void *data)
static struct PostcopyBlocktimeContext *blocktime_context_new(void)
{
+ MachineState *ms = MACHINE(qdev_get_machine());
+ unsigned int smp_cpus = ms->smp.cpus;
PostcopyBlocktimeContext *ctx = g_new0(PostcopyBlocktimeContext, 1);
ctx->page_fault_vcpu_time = g_new0(uint32_t, smp_cpus);
ctx->vcpu_addr = g_new0(uintptr_t, smp_cpus);
@@ -141,10 +144,11 @@ static struct PostcopyBlocktimeContext *blocktime_context_new(void)
static uint32List *get_vcpu_blocktime_list(PostcopyBlocktimeContext *ctx)
{
+ MachineState *ms = MACHINE(qdev_get_machine());
uint32List *list = NULL, *entry = NULL;
int i;
- for (i = smp_cpus - 1; i >= 0; i--) {
+ for (i = ms->smp.cpus - 1; i >= 0; i--) {
entry = g_new0(uint32List, 1);
entry->value = ctx->vcpu_blocktime[i];
entry->next = list;
@@ -807,6 +811,8 @@ static void mark_postcopy_blocktime_end(uintptr_t addr)
{
MigrationIncomingState *mis = migration_incoming_get_current();
PostcopyBlocktimeContext *dc = mis->blocktime_ctx;
+ MachineState *ms = MACHINE(qdev_get_machine());
+ unsigned int smp_cpus = ms->smp.cpus;
int i, affected_cpu = 0;
bool vcpu_total_blocktime = false;
uint32_t read_vcpu_time, low_time_offset;
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index 8f11cb8202..1053409a04 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -24,6 +24,9 @@
#include "exec/helper-proto.h"
#include "exception.h"
#include "sysemu/sysemu.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/boards.h"
+#endif
#define TO_SPR(group, number) (((group) << 11) + (number))
@@ -194,6 +197,7 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
target_ulong spr)
{
#ifndef CONFIG_USER_ONLY
+ MachineState *ms = MACHINE(qdev_get_machine());
OpenRISCCPU *cpu = env_archcpu(env);
CPUState *cs = env_cpu(env);
int idx;
@@ -241,7 +245,7 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
return cpu->parent_obj.cpu_index;
case TO_SPR(0, 129): /* NUMCORES */
- return max_cpus;
+ return ms->smp.max_cpus;
case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */
idx = (spr - 1024);
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 02a2680169..be2c33c400 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -45,6 +45,10 @@
#include "exec/cpu-common.h"
#include "exec/exec-all.h"
+#if !defined(CONFIG_USER_ONLY)
+#include "hw/boards.h"
+#endif
+
#include "tcg-op.h"
#if UINTPTR_MAX == UINT32_MAX
@@ -620,6 +624,10 @@ static size_t tcg_n_regions(void)
size_t i;
/* Use a single region if all we have is one vCPU thread */
+#if !defined(CONFIG_USER_ONLY)
+ MachineState *ms = MACHINE(qdev_get_machine());
+ unsigned int max_cpus = ms->smp.max_cpus;
+#endif
if (max_cpus == 1 || !qemu_tcg_mttcg_enabled()) {
return 1;
}
@@ -752,6 +760,7 @@ void tcg_register_thread(void)
#else
void tcg_register_thread(void)
{
+ MachineState *ms = MACHINE(qdev_get_machine());
TCGContext *s = g_malloc(sizeof(*s));
unsigned int i, n;
bool err;
@@ -769,7 +778,7 @@ void tcg_register_thread(void)
/* Claim an entry in tcg_ctxs */
n = atomic_fetch_inc(&n_tcg_ctxs);
- g_assert(n < max_cpus);
+ g_assert(n < ms->smp.max_cpus);
atomic_set(&tcg_ctxs[n], s);
tcg_ctx = s;
@@ -979,6 +988,8 @@ void tcg_context_init(TCGContext *s)
tcg_ctxs = &tcg_ctx;
n_tcg_ctxs = 1;
#else
+ MachineState *ms = MACHINE(qdev_get_machine());
+ unsigned int max_cpus = ms->smp.max_cpus;
tcg_ctxs = g_new(TCGContext *, max_cpus);
#endif
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PULL v6 04/42] hw/ppc: Replace global smp variables with machine smp properties
2019-07-05 22:14 [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 Eduardo Habkost
` (2 preceding siblings ...)
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 03/42] general: Replace global smp variables with smp machine properties Eduardo Habkost
@ 2019-07-05 22:14 ` Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 05/42] hw/riscv: " Eduardo Habkost
` (39 subsequent siblings)
43 siblings, 0 replies; 49+ messages in thread
From: Eduardo Habkost @ 2019-07-05 22:14 UTC (permalink / raw)
To: Peter Maydell, Paolo Bonzini, qemu-devel, Marcel Apfelbaum,
Richard Henderson
Cc: Like Xu
From: Like Xu <like.xu@linux.intel.com>
The global smp variables in ppc are replaced with smp machine properties.
A local variable of the same name would be introduced in the declaration
phase if it's used widely in the context OR replace it on the spot if it's
only used once. No semantic changes.
Signed-off-by: Like Xu <like.xu@linux.intel.com>
Message-Id: <20190518205428.90532-5-like.xu@linux.intel.com>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
hw/ppc/e500.c | 3 +++
hw/ppc/mac_newworld.c | 3 ++-
hw/ppc/mac_oldworld.c | 3 ++-
hw/ppc/pnv.c | 6 ++++--
hw/ppc/prep.c | 4 ++--
hw/ppc/spapr.c | 34 ++++++++++++++++++++++++++--------
hw/ppc/spapr_rtas.c | 4 +++-
7 files changed, 42 insertions(+), 15 deletions(-)
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index bfda1266af..a3eac7f057 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -308,6 +308,7 @@ static int ppce500_load_device_tree(PPCE500MachineState *pms,
bool dry_run)
{
MachineState *machine = MACHINE(pms);
+ unsigned int smp_cpus = machine->smp.cpus;
const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);
CPUPPCState *env = first_cpu->env_ptr;
int ret = -1;
@@ -735,6 +736,7 @@ static DeviceState *ppce500_init_mpic_qemu(PPCE500MachineState *pms,
SysBusDevice *s;
int i, j, k;
MachineState *machine = MACHINE(pms);
+ unsigned int smp_cpus = machine->smp.cpus;
const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);
dev = qdev_create(NULL, TYPE_OPENPIC);
@@ -847,6 +849,7 @@ void ppce500_init(MachineState *machine)
struct boot_info *boot_info;
int dt_size;
int i;
+ unsigned int smp_cpus = machine->smp.cpus;
/* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and
* 4 respectively */
unsigned int pci_irq_nrs[PCI_NUM_PINS] = {1, 2, 3, 4};
diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
index c8d3245524..09bc6068f3 100644
--- a/hw/ppc/mac_newworld.c
+++ b/hw/ppc/mac_newworld.c
@@ -136,6 +136,7 @@ static void ppc_core99_init(MachineState *machine)
DeviceState *dev, *pic_dev;
hwaddr nvram_addr = 0xFFF04000;
uint64_t tbfreq;
+ unsigned int smp_cpus = machine->smp.cpus;
linux_boot = (kernel_filename != NULL);
@@ -463,7 +464,7 @@ static void ppc_core99_init(MachineState *machine)
sysbus_mmio_map(s, 1, CFG_ADDR + 2);
fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
- fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
+ fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus);
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch);
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c
index da751addc4..9ffde5b6f7 100644
--- a/hw/ppc/mac_oldworld.c
+++ b/hw/ppc/mac_oldworld.c
@@ -101,6 +101,7 @@ static void ppc_heathrow_init(MachineState *machine)
DeviceState *dev, *pic_dev;
BusState *adb_bus;
int bios_size;
+ unsigned int smp_cpus = machine->smp.cpus;
uint16_t ppc_boot_device;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
void *fw_cfg;
@@ -324,7 +325,7 @@ static void ppc_heathrow_init(MachineState *machine)
sysbus_mmio_map(s, 1, CFG_ADDR + 2);
fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
- fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
+ fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus);
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW);
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index e364f79efd..bd4531c822 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -688,7 +688,8 @@ static void pnv_init(MachineState *machine)
object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal);
object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id",
&error_fatal);
- object_property_set_int(chip, smp_cores, "nr-cores", &error_fatal);
+ object_property_set_int(chip, machine->smp.cores,
+ "nr-cores", &error_fatal);
object_property_set_bool(chip, true, "realized", &error_fatal);
}
g_free(chip_typename);
@@ -1149,6 +1150,7 @@ static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
{
+ MachineState *ms = MACHINE(qdev_get_machine());
Error *error = NULL;
PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
const char *typename = pnv_chip_core_typename(chip);
@@ -1182,7 +1184,7 @@ static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid);
object_initialize_child(OBJECT(chip), core_name, pnv_core, typesize,
typename, &error_fatal, NULL);
- object_property_set_int(OBJECT(pnv_core), smp_threads, "nr-threads",
+ object_property_set_int(OBJECT(pnv_core), ms->smp.threads, "nr-threads",
&error_fatal);
object_property_set_int(OBJECT(pnv_core), core_hwid,
CPU_CORE_PROP_CORE_ID, &error_fatal);
diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
index a248ce480d..ab3c1df1fc 100644
--- a/hw/ppc/prep.c
+++ b/hw/ppc/prep.c
@@ -428,7 +428,7 @@ static void ppc_prep_init(MachineState *machine)
linux_boot = (kernel_filename != NULL);
/* init CPUs */
- for (i = 0; i < smp_cpus; i++) {
+ for (i = 0; i < machine->smp.cpus; i++) {
cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
env = &cpu->env;
@@ -770,7 +770,7 @@ static void ibm_40p_init(MachineState *machine)
boot_device = machine->boot_order[0];
}
- fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
+ fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus);
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_PREP);
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 6cf0ac400b..51256ac9ca 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -106,6 +106,9 @@
*/
static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index)
{
+ MachineState *ms = MACHINE(spapr);
+ unsigned int smp_threads = ms->smp.threads;
+
assert(spapr->vsmt);
return
(cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads;
@@ -153,8 +156,10 @@ static void pre_2_10_vmstate_unregister_dummy_icp(int i)
int spapr_max_server_number(SpaprMachineState *spapr)
{
+ MachineState *ms = MACHINE(spapr);
+
assert(spapr->vsmt);
- return DIV_ROUND_UP(max_cpus * spapr->vsmt, smp_threads);
+ return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads);
}
static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
@@ -287,6 +292,7 @@ static void spapr_populate_pa_features(SpaprMachineState *spapr,
static int spapr_fixup_cpu_dt(void *fdt, SpaprMachineState *spapr)
{
+ MachineState *ms = MACHINE(spapr);
int ret = 0, offset, cpus_offset;
CPUState *cs;
char cpu_model[32];
@@ -296,7 +302,7 @@ static int spapr_fixup_cpu_dt(void *fdt, SpaprMachineState *spapr)
PowerPCCPU *cpu = POWERPC_CPU(cs);
DeviceClass *dc = DEVICE_GET_CLASS(cs);
int index = spapr_get_vcpu_id(cpu);
- int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu));
+ int compat_smt = MIN(ms->smp.threads, ppc_compat_max_vthreads(cpu));
if (!spapr_is_thread0_in_vcore(spapr, cpu)) {
continue;
@@ -442,6 +448,7 @@ static int spapr_populate_memory(SpaprMachineState *spapr, void *fdt)
static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
SpaprMachineState *spapr)
{
+ MachineState *ms = MACHINE(spapr);
PowerPCCPU *cpu = POWERPC_CPU(cs);
CPUPPCState *env = &cpu->env;
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
@@ -453,7 +460,8 @@ static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
uint32_t page_sizes_prop[64];
size_t page_sizes_prop_size;
- uint32_t vcpus_per_socket = smp_threads * smp_cores;
+ unsigned int smp_threads = ms->smp.threads;
+ uint32_t vcpus_per_socket = smp_threads * ms->smp.cores;
uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu));
SpaprDrc *drc;
@@ -1026,6 +1034,7 @@ int spapr_h_cas_compose_response(SpaprMachineState *spapr,
static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt)
{
+ MachineState *ms = MACHINE(spapr);
int rtas;
GString *hypertas = g_string_sized_new(256);
GString *qemu_hypertas = g_string_sized_new(256);
@@ -1036,7 +1045,7 @@ static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt)
cpu_to_be32(max_device_addr >> 32),
cpu_to_be32(max_device_addr & 0xffffffff),
0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE),
- cpu_to_be32(max_cpus / smp_threads),
+ cpu_to_be32(ms->smp.max_cpus / ms->smp.threads),
};
uint32_t maxdomain = cpu_to_be32(spapr->gpu_numa_id > 1 ? 1 : 0);
uint32_t maxdomains[] = {
@@ -2543,7 +2552,7 @@ static void spapr_validate_node_memory(MachineState *machine, Error **errp)
/* find cpu slot in machine->possible_cpus by core_id */
static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
{
- int index = id / smp_threads;
+ int index = id / ms->smp.threads;
if (index >= ms->possible_cpus->len) {
return NULL;
@@ -2556,10 +2565,12 @@ static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp)
{
+ MachineState *ms = MACHINE(spapr);
Error *local_err = NULL;
bool vsmt_user = !!spapr->vsmt;
int kvm_smt = kvmppc_smt_threads();
int ret;
+ unsigned int smp_threads = ms->smp.threads;
if (!kvm_enabled() && (smp_threads > 1)) {
error_setg(&local_err, "TCG cannot support more than 1 thread/core "
@@ -2633,6 +2644,9 @@ static void spapr_init_cpus(SpaprMachineState *spapr)
SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
const char *type = spapr_get_cpu_core_type(machine->cpu_type);
const CPUArchIdList *possible_cpus;
+ unsigned int smp_cpus = machine->smp.cpus;
+ unsigned int smp_threads = machine->smp.threads;
+ unsigned int max_cpus = machine->smp.max_cpus;
int boot_cores_nr = smp_cpus / smp_threads;
int i;
@@ -3859,6 +3873,7 @@ static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
const char *type = object_get_typename(OBJECT(dev));
CPUArchId *core_slot;
int index;
+ unsigned int smp_threads = machine->smp.threads;
if (dev->hotplugged && !mc->has_hotpluggable_cpus) {
error_setg(&local_err, "CPU hotplug not supported for this machine");
@@ -4124,14 +4139,16 @@ spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index)
static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx)
{
- return idx / smp_cores % nb_numa_nodes;
+ return idx / ms->smp.cores % nb_numa_nodes;
}
static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine)
{
int i;
+ unsigned int smp_threads = machine->smp.threads;
+ unsigned int smp_cpus = machine->smp.cpus;
const char *core_type;
- int spapr_max_cores = max_cpus / smp_threads;
+ int spapr_max_cores = machine->smp.max_cpus / smp_threads;
MachineClass *mc = MACHINE_GET_CLASS(machine);
if (!mc->has_hotpluggable_cpus) {
@@ -4254,6 +4271,7 @@ int spapr_get_vcpu_id(PowerPCCPU *cpu)
void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp)
{
SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
+ MachineState *ms = MACHINE(spapr);
int vcpu_id;
vcpu_id = spapr_vcpu_id(spapr, cpu_index);
@@ -4262,7 +4280,7 @@ void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp)
error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id);
error_append_hint(errp, "Adjust the number of cpus to %d "
"or try to raise the number of threads per core\n",
- vcpu_id * smp_threads / spapr->vsmt);
+ vcpu_id * ms->smp.threads / spapr->vsmt);
return;
}
diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c
index 5bc1a93271..a618a2ac0f 100644
--- a/hw/ppc/spapr_rtas.c
+++ b/hw/ppc/spapr_rtas.c
@@ -235,6 +235,8 @@ static void rtas_ibm_get_system_parameter(PowerPCCPU *cpu,
target_ulong args,
uint32_t nret, target_ulong rets)
{
+ MachineState *ms = MACHINE(qdev_get_machine());
+ unsigned int max_cpus = ms->smp.max_cpus;
target_ulong parameter = rtas_ld(args, 0);
target_ulong buffer = rtas_ld(args, 1);
target_ulong length = rtas_ld(args, 2);
@@ -248,7 +250,7 @@ static void rtas_ibm_get_system_parameter(PowerPCCPU *cpu,
"MaxPlatProcs=%d",
max_cpus,
current_machine->ram_size / MiB,
- smp_cpus,
+ ms->smp.cpus,
max_cpus);
ret = sysparm_st(buffer, length, param_val, strlen(param_val) + 1);
g_free(param_val);
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PULL v6 05/42] hw/riscv: Replace global smp variables with machine smp properties
2019-07-05 22:14 [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 Eduardo Habkost
` (3 preceding siblings ...)
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 04/42] hw/ppc: Replace global smp variables with machine smp properties Eduardo Habkost
@ 2019-07-05 22:14 ` Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 06/42] hw/s390x: " Eduardo Habkost
` (38 subsequent siblings)
43 siblings, 0 replies; 49+ messages in thread
From: Eduardo Habkost @ 2019-07-05 22:14 UTC (permalink / raw)
To: Peter Maydell, Paolo Bonzini, qemu-devel, Marcel Apfelbaum,
Richard Henderson
Cc: Like Xu
From: Like Xu <like.xu@linux.intel.com>
The global smp variables in riscv are replaced with smp machine properties.
A local variable of the same name would be introduced in the declaration
phase if it's used widely in the context OR replace it on the spot if it's
only used once. No semantic changes.
Signed-off-by: Like Xu <like.xu@linux.intel.com>
Message-Id: <20190518205428.90532-6-like.xu@linux.intel.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
[ehabkost: fix spike_board_init()]
[ehabkost: fix riscv_sifive_e_soc_init()]
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
hw/riscv/sifive_e.c | 6 ++++--
hw/riscv/sifive_plic.c | 3 +++
hw/riscv/sifive_u.c | 11 +++++++----
hw/riscv/spike.c | 3 +++
hw/riscv/virt.c | 1 +
5 files changed, 18 insertions(+), 6 deletions(-)
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index d27f626529..2a499d8ed2 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -124,6 +124,7 @@ static void riscv_sifive_e_init(MachineState *machine)
static void riscv_sifive_e_soc_init(Object *obj)
{
+ MachineState *ms = MACHINE(qdev_get_machine());
SiFiveESoCState *s = RISCV_E_SOC(obj);
object_initialize_child(obj, "cpus", &s->cpus,
@@ -131,7 +132,7 @@ static void riscv_sifive_e_soc_init(Object *obj)
&error_abort, NULL);
object_property_set_str(OBJECT(&s->cpus), SIFIVE_E_CPU, "cpu-type",
&error_abort);
- object_property_set_int(OBJECT(&s->cpus), smp_cpus, "num-harts",
+ object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts",
&error_abort);
sysbus_init_child_obj(obj, "riscv.sifive.e.gpio0",
&s->gpio, sizeof(s->gpio),
@@ -140,6 +141,7 @@ static void riscv_sifive_e_soc_init(Object *obj)
static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
{
+ MachineState *ms = MACHINE(qdev_get_machine());
const struct MemmapEntry *memmap = sifive_e_memmap;
Error *err = NULL;
@@ -168,7 +170,7 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
SIFIVE_E_PLIC_CONTEXT_STRIDE,
memmap[SIFIVE_E_PLIC].size);
sifive_clint_create(memmap[SIFIVE_E_CLINT].base,
- memmap[SIFIVE_E_CLINT].size, smp_cpus,
+ memmap[SIFIVE_E_CLINT].size, ms->smp.cpus,
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
sifive_mmio_emulate(sys_mem, "riscv.sifive.e.aon",
memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
index 70a4413599..0950e89e15 100644
--- a/hw/riscv/sifive_plic.c
+++ b/hw/riscv/sifive_plic.c
@@ -24,6 +24,7 @@
#include "qemu/error-report.h"
#include "hw/sysbus.h"
#include "hw/pci/msi.h"
+#include "hw/boards.h"
#include "target/riscv/cpu.h"
#include "sysemu/sysemu.h"
#include "hw/riscv/sifive_plic.h"
@@ -439,6 +440,8 @@ static void sifive_plic_irq_request(void *opaque, int irq, int level)
static void sifive_plic_realize(DeviceState *dev, Error **errp)
{
+ MachineState *ms = MACHINE(qdev_get_machine());
+ unsigned int smp_cpus = ms->smp.cpus;
SiFivePLICState *plic = SIFIVE_PLIC(dev);
int i;
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 4208671552..ca53a9290d 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -315,13 +315,14 @@ static void riscv_sifive_u_init(MachineState *machine)
static void riscv_sifive_u_soc_init(Object *obj)
{
+ MachineState *ms = MACHINE(qdev_get_machine());
SiFiveUSoCState *s = RISCV_U_SOC(obj);
object_initialize_child(obj, "cpus", &s->cpus, sizeof(s->cpus),
TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
object_property_set_str(OBJECT(&s->cpus), SIFIVE_U_CPU, "cpu-type",
&error_abort);
- object_property_set_int(OBJECT(&s->cpus), smp_cpus, "num-harts",
+ object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts",
&error_abort);
sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem),
@@ -330,6 +331,7 @@ static void riscv_sifive_u_soc_init(Object *obj)
static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
{
+ MachineState *ms = MACHINE(qdev_get_machine());
SiFiveUSoCState *s = RISCV_U_SOC(dev);
const struct MemmapEntry *memmap = sifive_u_memmap;
MemoryRegion *system_memory = get_system_memory();
@@ -351,9 +353,10 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
mask_rom);
/* create PLIC hart topology configuration string */
- plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) * smp_cpus;
+ plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) *
+ ms->smp.cpus;
plic_hart_config = g_malloc0(plic_hart_config_len);
- for (i = 0; i < smp_cpus; i++) {
+ for (i = 0; i < ms->smp.cpus; i++) {
if (i != 0) {
strncat(plic_hart_config, ",", plic_hart_config_len);
}
@@ -379,7 +382,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
- memmap[SIFIVE_U_CLINT].size, smp_cpus,
+ memmap[SIFIVE_U_CLINT].size, ms->smp.cpus,
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) {
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index e68be00a5f..2991b341a2 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -159,6 +159,7 @@ static void spike_board_init(MachineState *machine)
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
int i;
+ unsigned int smp_cpus = machine->smp.cpus;
/* Initialize SOC */
object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
@@ -241,6 +242,7 @@ static void spike_v1_10_0_board_init(MachineState *machine)
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
int i;
+ unsigned int smp_cpus = machine->smp.cpus;
if (!qtest_enabled()) {
info_report("The Spike v1.10.0 machine has been deprecated. "
@@ -329,6 +331,7 @@ static void spike_v1_09_1_board_init(MachineState *machine)
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
int i;
+ unsigned int smp_cpus = machine->smp.cpus;
if (!qtest_enabled()) {
info_report("The Spike v1.09.1 machine has been deprecated. "
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index d8181a4ff1..ecdc77d728 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -371,6 +371,7 @@ static void riscv_virt_board_init(MachineState *machine)
char *plic_hart_config;
size_t plic_hart_config_len;
int i;
+ unsigned int smp_cpus = machine->smp.cpus;
void *fdt;
/* Initialize SOC */
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PULL v6 06/42] hw/s390x: Replace global smp variables with machine smp properties
2019-07-05 22:14 [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 Eduardo Habkost
` (4 preceding siblings ...)
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 05/42] hw/riscv: " Eduardo Habkost
@ 2019-07-05 22:14 ` Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 07/42] hw/i386: " Eduardo Habkost
` (37 subsequent siblings)
43 siblings, 0 replies; 49+ messages in thread
From: Eduardo Habkost @ 2019-07-05 22:14 UTC (permalink / raw)
To: Peter Maydell, Paolo Bonzini, qemu-devel, Marcel Apfelbaum,
Richard Henderson
Cc: Like Xu
From: Like Xu <like.xu@linux.intel.com>
The global smp variables in s390x are replaced with smp machine properties.
A local variable of the same name would be introduced in the declaration
phase if it's used widely in the context OR replace it on the spot if it's
only used once. No semantic changes.
Signed-off-by: Like Xu <like.xu@linux.intel.com>
Message-Id: <20190518205428.90532-7-like.xu@linux.intel.com>
Acked-by: Christian Borntraeger <borntraeger@de.ibm.com>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
[ehabkost: fix build failure at VCPU_IRQ_BUF_SIZE]
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
fixup! hw/s390x: Replace global smp variables with machine smp properties
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
hw/s390x/s390-virtio-ccw.c | 3 ++-
hw/s390x/sclp.c | 2 +-
target/s390x/cpu.c | 3 +++
target/s390x/excp_helper.c | 5 +++++
target/s390x/kvm.c | 10 ++++++----
5 files changed, 17 insertions(+), 6 deletions(-)
diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c
index e09bf8f1b6..5b6a9a4e55 100644
--- a/hw/s390x/s390-virtio-ccw.c
+++ b/hw/s390x/s390-virtio-ccw.c
@@ -84,7 +84,7 @@ static void s390_init_cpus(MachineState *machine)
/* initialize possible_cpus */
mc->possible_cpu_arch_ids(machine);
- for (i = 0; i < smp_cpus; i++) {
+ for (i = 0; i < machine->smp.cpus; i++) {
s390x_new_cpu(machine->cpu_type, i, &error_fatal);
}
}
@@ -411,6 +411,7 @@ static CpuInstanceProperties s390_cpu_index_to_props(MachineState *ms,
static const CPUArchIdList *s390_possible_cpu_arch_ids(MachineState *ms)
{
int i;
+ unsigned int max_cpus = ms->smp.max_cpus;
if (ms->possible_cpus) {
g_assert(ms->possible_cpus && ms->possible_cpus->len == max_cpus);
diff --git a/hw/s390x/sclp.c b/hw/s390x/sclp.c
index 4510a800cb..fac7c3bb6c 100644
--- a/hw/s390x/sclp.c
+++ b/hw/s390x/sclp.c
@@ -64,7 +64,7 @@ static void read_SCP_info(SCLPDevice *sclp, SCCB *sccb)
prepare_cpu_entries(sclp, read_info->entries, &cpu_count);
read_info->entries_cpu = cpu_to_be16(cpu_count);
read_info->offset_cpu = cpu_to_be16(offsetof(ReadInfo, entries));
- read_info->highest_cpu = cpu_to_be16(max_cpus - 1);
+ read_info->highest_cpu = cpu_to_be16(machine->smp.max_cpus - 1);
read_info->ibc_val = cpu_to_be32(s390_get_ibc_val());
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 8540e7a2cb..736a7903e2 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -37,6 +37,7 @@
#include "hw/qdev-properties.h"
#ifndef CONFIG_USER_ONLY
#include "hw/hw.h"
+#include "hw/boards.h"
#include "sysemu/arch_init.h"
#include "sysemu/sysemu.h"
#include "sysemu/tcg.h"
@@ -197,6 +198,8 @@ static void s390_cpu_realizefn(DeviceState *dev, Error **errp)
}
#if !defined(CONFIG_USER_ONLY)
+ MachineState *ms = MACHINE(qdev_get_machine());
+ unsigned int max_cpus = ms->smp.max_cpus;
if (cpu->env.core_id >= max_cpus) {
error_setg(&err, "Unable to add CPU with core-id: %" PRIu32
", maximum core-id: %d", cpu->env.core_id,
diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c
index 202456cdc5..892f659d5a 100644
--- a/target/s390x/excp_helper.c
+++ b/target/s390x/excp_helper.c
@@ -31,6 +31,7 @@
#ifndef CONFIG_USER_ONLY
#include "sysemu/sysemu.h"
#include "hw/s390x/s390_flic.h"
+#include "hw/boards.h"
#endif
void QEMU_NORETURN tcg_s390_program_interrupt(CPUS390XState *env, uint32_t code,
@@ -315,6 +316,10 @@ static void do_ext_interrupt(CPUS390XState *env)
g_assert(cpu_addr < S390_MAX_CPUS);
lowcore->cpu_addr = cpu_to_be16(cpu_addr);
clear_bit(cpu_addr, env->emergency_signals);
+#ifndef CONFIG_USER_ONLY
+ MachineState *ms = MACHINE(qdev_get_machine());
+ unsigned int max_cpus = ms->smp.max_cpus;
+#endif
if (bitmap_empty(env->emergency_signals, max_cpus)) {
env->pending_int &= ~INTERRUPT_EMERGENCY_SIGNAL;
}
diff --git a/target/s390x/kvm.c b/target/s390x/kvm.c
index 0267c6c2f6..6e814c230b 100644
--- a/target/s390x/kvm.c
+++ b/target/s390x/kvm.c
@@ -119,8 +119,8 @@
* Needs to be big enough to contain max_cpus emergency signals
* and in addition NR_LOCAL_IRQS interrupts
*/
-#define VCPU_IRQ_BUF_SIZE (sizeof(struct kvm_s390_irq) * \
- (max_cpus + NR_LOCAL_IRQS))
+#define VCPU_IRQ_BUF_SIZE(max_cpus) (sizeof(struct kvm_s390_irq) * \
+ (max_cpus + NR_LOCAL_IRQS))
static CPUWatchpoint hw_watchpoint;
/*
@@ -362,9 +362,10 @@ unsigned long kvm_arch_vcpu_id(CPUState *cpu)
int kvm_arch_init_vcpu(CPUState *cs)
{
+ unsigned int max_cpus = MACHINE(qdev_get_machine())->smp.max_cpus;
S390CPU *cpu = S390_CPU(cs);
kvm_s390_set_cpu_state(cpu, cpu->env.cpu_state);
- cpu->irqstate = g_malloc0(VCPU_IRQ_BUF_SIZE);
+ cpu->irqstate = g_malloc0(VCPU_IRQ_BUF_SIZE(max_cpus));
return 0;
}
@@ -1950,9 +1951,10 @@ int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state)
void kvm_s390_vcpu_interrupt_pre_save(S390CPU *cpu)
{
+ unsigned int max_cpus = MACHINE(qdev_get_machine())->smp.max_cpus;
struct kvm_s390_irq_state irq_state = {
.buf = (uint64_t) cpu->irqstate,
- .len = VCPU_IRQ_BUF_SIZE,
+ .len = VCPU_IRQ_BUF_SIZE(max_cpus),
};
CPUState *cs = CPU(cpu);
int32_t bytes;
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PULL v6 07/42] hw/i386: Replace global smp variables with machine smp properties
2019-07-05 22:14 [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 Eduardo Habkost
` (5 preceding siblings ...)
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 06/42] hw/s390x: " Eduardo Habkost
@ 2019-07-05 22:14 ` Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 08/42] hw/arm: " Eduardo Habkost
` (36 subsequent siblings)
43 siblings, 0 replies; 49+ messages in thread
From: Eduardo Habkost @ 2019-07-05 22:14 UTC (permalink / raw)
To: Peter Maydell, Paolo Bonzini, qemu-devel, Marcel Apfelbaum,
Richard Henderson
Cc: Like Xu
From: Like Xu <like.xu@linux.intel.com>
The global smp variables in i386 are replaced with smp machine properties.
To avoid calling qdev_get_machine() as much as possible, some related funtions
for acpi data generations are refactored. No semantic changes.
A local variable of the same name would be introduced in the declaration
phase if it's used widely in the context OR replace it on the spot if it's
only used once. No semantic changes.
Signed-off-by: Like Xu <like.xu@linux.intel.com>
Message-Id: <20190518205428.90532-8-like.xu@linux.intel.com>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
hw/i386/acpi-build.c | 11 +++++++----
hw/i386/kvmvapic.c | 7 +++++--
hw/i386/pc.c | 18 ++++++++++++------
hw/i386/xen/xen-hvm.c | 4 ++++
target/i386/cpu.c | 4 +++-
5 files changed, 31 insertions(+), 13 deletions(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 8ae7d88b11..d281ffa89e 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -43,6 +43,7 @@
#include "sysemu/tpm.h"
#include "hw/acpi/tpm.h"
#include "hw/acpi/vmgenid.h"
+#include "hw/boards.h"
#include "sysemu/tpm_backend.h"
#include "hw/timer/mc146818rtc_regs.h"
#include "hw/mem/memory-device.h"
@@ -123,7 +124,8 @@ typedef struct FwCfgTPMConfig {
static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg);
-static void init_common_fadt_data(Object *o, AcpiFadtData *data)
+static void init_common_fadt_data(MachineState *ms, Object *o,
+ AcpiFadtData *data)
{
uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL);
AmlAddressSpace as = AML_AS_SYSTEM_IO;
@@ -139,7 +141,8 @@ static void init_common_fadt_data(Object *o, AcpiFadtData *data)
* CPUs for more than 8 CPUs, "Clustered Logical" mode has to be
* used
*/
- ((max_cpus > 8) ? (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0),
+ ((ms->smp.max_cpus > 8) ?
+ (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0),
.int_model = 1 /* Multiple APIC */,
.rtc_century = RTC_CENTURY,
.plvl2_lat = 0xfff /* C2 state not supported */,
@@ -173,7 +176,7 @@ static Object *object_resolve_type_unambiguous(const char *typename)
return o;
}
-static void acpi_get_pm_info(AcpiPmInfo *pm)
+static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm)
{
Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM);
Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE);
@@ -2612,7 +2615,7 @@ void acpi_build(AcpiBuildTables *tables, MachineState *machine)
AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
Object *vmgenid_dev;
- acpi_get_pm_info(&pm);
+ acpi_get_pm_info(machine, &pm);
acpi_get_misc_info(&misc);
acpi_get_pci_holes(&pci_hole, &pci_hole64);
acpi_get_slic_oem(&slic_oem);
diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c
index ca8df462b6..9c2ab4aac5 100644
--- a/hw/i386/kvmvapic.c
+++ b/hw/i386/kvmvapic.c
@@ -18,6 +18,7 @@
#include "sysemu/kvm.h"
#include "hw/i386/apic_internal.h"
#include "hw/sysbus.h"
+#include "hw/boards.h"
#include "tcg/tcg.h"
#define VAPIC_IO_PORT 0x7e
@@ -442,11 +443,12 @@ static void do_patch_instruction(CPUState *cs, run_on_cpu_data data)
static void patch_instruction(VAPICROMState *s, X86CPU *cpu, target_ulong ip)
{
+ MachineState *ms = MACHINE(qdev_get_machine());
CPUState *cs = CPU(cpu);
VAPICHandlers *handlers;
PatchInfo *info;
- if (smp_cpus == 1) {
+ if (ms->smp.cpus == 1) {
handlers = &s->rom_state.up;
} else {
handlers = &s->rom_state.mp;
@@ -747,6 +749,7 @@ static void do_vapic_enable(CPUState *cs, run_on_cpu_data data)
static void kvmvapic_vm_state_change(void *opaque, int running,
RunState state)
{
+ MachineState *ms = MACHINE(qdev_get_machine());
VAPICROMState *s = opaque;
uint8_t *zero;
@@ -755,7 +758,7 @@ static void kvmvapic_vm_state_change(void *opaque, int running,
}
if (s->state == VAPIC_ACTIVE) {
- if (smp_cpus == 1) {
+ if (ms->smp.cpus == 1) {
run_on_cpu(first_cpu, do_vapic_enable, RUN_ON_CPU_HOST_PTR(s));
} else {
zero = g_malloc0(s->rom_state.vapic_size);
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 0b0b55afd2..269e44f0d0 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -925,11 +925,13 @@ bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length)
static uint32_t x86_cpu_apic_id_from_index(PCMachineState *pcms,
unsigned int cpu_index)
{
+ MachineState *ms = MACHINE(pcms);
PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
uint32_t correct_id;
static bool warned;
- correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
+ correct_id = x86_apicid_from_cpu_idx(ms->smp.cores,
+ ms->smp.threads, cpu_index);
if (pcmc->compat_apic_id_mode) {
if (cpu_index != correct_id && !warned && !qtest_enabled()) {
error_report("APIC IDs set in compatibility mode, "
@@ -1565,9 +1567,10 @@ void pc_cpus_init(PCMachineState *pcms)
*
* This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
*/
- pcms->apic_id_limit = x86_cpu_apic_id_from_index(pcms, max_cpus - 1) + 1;
+ pcms->apic_id_limit = x86_cpu_apic_id_from_index(pcms,
+ ms->smp.max_cpus - 1) + 1;
possible_cpus = mc->possible_cpu_arch_ids(ms);
- for (i = 0; i < smp_cpus; i++) {
+ for (i = 0; i < ms->smp.cpus; i++) {
pc_new_cpu(possible_cpus->cpus[i].type, possible_cpus->cpus[i].arch_id,
&error_fatal);
}
@@ -2291,6 +2294,8 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
X86CPU *cpu = X86_CPU(dev);
MachineState *ms = MACHINE(hotplug_dev);
PCMachineState *pcms = PC_MACHINE(hotplug_dev);
+ unsigned int smp_cores = ms->smp.cores;
+ unsigned int smp_threads = ms->smp.threads;
if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) {
error_setg(errp, "Invalid CPU type, expected cpu type: '%s'",
@@ -2300,7 +2305,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
/* if APIC ID is not set, set it based on socket/core/thread properties */
if (cpu->apic_id == UNASSIGNED_APIC_ID) {
- int max_socket = (max_cpus - 1) / smp_threads / smp_cores;
+ int max_socket = (ms->smp.max_cpus - 1) / smp_threads / smp_cores;
if (cpu->socket_id < 0) {
error_setg(errp, "CPU socket-id is not set");
@@ -2718,7 +2723,7 @@ static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx)
assert(idx < ms->possible_cpus->len);
x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
- smp_cores, smp_threads, &topo);
+ ms->smp.cores, ms->smp.threads, &topo);
return topo.pkg_id % nb_numa_nodes;
}
@@ -2726,6 +2731,7 @@ static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms)
{
PCMachineState *pcms = PC_MACHINE(ms);
int i;
+ unsigned int max_cpus = ms->smp.max_cpus;
if (ms->possible_cpus) {
/*
@@ -2746,7 +2752,7 @@ static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms)
ms->possible_cpus->cpus[i].vcpus_count = 1;
ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(pcms, i);
x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
- smp_cores, smp_threads, &topo);
+ ms->smp.cores, ms->smp.threads, &topo);
ms->possible_cpus->cpus[i].props.has_socket_id = true;
ms->possible_cpus->cpus[i].props.socket_id = topo.pkg_id;
ms->possible_cpus->cpus[i].props.has_core_id = true;
diff --git a/hw/i386/xen/xen-hvm.c b/hw/i386/xen/xen-hvm.c
index 469f1260a4..e8e79e0917 100644
--- a/hw/i386/xen/xen-hvm.c
+++ b/hw/i386/xen/xen-hvm.c
@@ -756,6 +756,8 @@ static ioreq_t *cpu_get_ioreq_from_shared_memory(XenIOState *state, int vcpu)
/* retval--the number of ioreq packet */
static ioreq_t *cpu_get_ioreq(XenIOState *state)
{
+ MachineState *ms = MACHINE(qdev_get_machine());
+ unsigned int max_cpus = ms->smp.max_cpus;
int i;
evtchn_port_t port;
@@ -1383,6 +1385,8 @@ static int xen_map_ioreq_server(XenIOState *state)
void xen_hvm_init(PCMachineState *pcms, MemoryRegion **ram_memory)
{
+ MachineState *ms = MACHINE(pcms);
+ unsigned int max_cpus = ms->smp.max_cpus;
int i, rc;
xen_pfn_t ioreq_pfn;
XenIOState *state;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 2a9f4e2d12..4b5cd49338 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -56,6 +56,7 @@
#include "hw/hw.h"
#include "hw/xen/xen.h"
#include "hw/i386/apic_internal.h"
+#include "hw/boards.h"
#endif
#include "disas/capstone.h"
@@ -5384,9 +5385,10 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
}
#ifndef CONFIG_USER_ONLY
+ MachineState *ms = MACHINE(qdev_get_machine());
qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
- if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
+ if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) {
x86_cpu_apic_create(cpu, &local_err);
if (local_err != NULL) {
goto out;
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PULL v6 08/42] hw/arm: Replace global smp variables with machine smp properties
2019-07-05 22:14 [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 Eduardo Habkost
` (6 preceding siblings ...)
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 07/42] hw/i386: " Eduardo Habkost
@ 2019-07-05 22:14 ` Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 09/42] hw: Replace global smp variables with MachineState for all remaining archs Eduardo Habkost
` (35 subsequent siblings)
43 siblings, 0 replies; 49+ messages in thread
From: Eduardo Habkost @ 2019-07-05 22:14 UTC (permalink / raw)
To: Peter Maydell, Paolo Bonzini, qemu-devel, Marcel Apfelbaum,
Richard Henderson
Cc: Like Xu
From: Like Xu <like.xu@linux.intel.com>
The global smp variables in arm are replaced with smp machine properties.
The init_cpus() and *_create_rpu() are refactored to pass MachineState.
A local variable of the same name would be introduced in the declaration
phase if it's used widely in the context OR replace it on the spot if it's
only used once. No semantic changes.
Signed-off-by: Like Xu <like.xu@linux.intel.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20190518205428.90532-9-like.xu@linux.intel.com>
[ehabkost: Fix hw/arm/sbsa-ref.c and hw/arm/aspeed.c]
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
hw/arm/aspeed.c | 2 +-
hw/arm/fsl-imx6.c | 6 +++++-
hw/arm/fsl-imx6ul.c | 6 +++++-
hw/arm/fsl-imx7.c | 7 +++++--
hw/arm/highbank.c | 1 +
hw/arm/mcimx6ul-evk.c | 2 +-
hw/arm/mcimx7d-sabre.c | 2 +-
hw/arm/raspi.c | 4 ++--
hw/arm/realview.c | 1 +
hw/arm/sabrelite.c | 2 +-
hw/arm/sbsa-ref.c | 4 ++++
hw/arm/vexpress.c | 16 ++++++++++------
hw/arm/virt.c | 8 +++++++-
hw/arm/xlnx-zynqmp.c | 16 ++++++++++------
target/arm/cpu.c | 8 +++++++-
15 files changed, 61 insertions(+), 24 deletions(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 8b6d304247..843b708247 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -187,7 +187,7 @@ static void aspeed_board_init(MachineState *machine,
&error_abort);
object_property_set_int(OBJECT(&bmc->soc), cfg->num_cs, "num-cs",
&error_abort);
- object_property_set_int(OBJECT(&bmc->soc), smp_cpus, "num-cpus",
+ object_property_set_int(OBJECT(&bmc->soc), machine->smp.cpus, "num-cpus",
&error_abort);
if (machine->kernel_filename) {
/*
diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c
index 7129517378..de45833097 100644
--- a/hw/arm/fsl-imx6.c
+++ b/hw/arm/fsl-imx6.c
@@ -22,6 +22,7 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "hw/arm/fsl-imx6.h"
+#include "hw/boards.h"
#include "sysemu/sysemu.h"
#include "chardev/char.h"
#include "qemu/error-report.h"
@@ -33,11 +34,12 @@
static void fsl_imx6_init(Object *obj)
{
+ MachineState *ms = MACHINE(qdev_get_machine());
FslIMX6State *s = FSL_IMX6(obj);
char name[NAME_SIZE];
int i;
- for (i = 0; i < MIN(smp_cpus, FSL_IMX6_NUM_CPUS); i++) {
+ for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX6_NUM_CPUS); i++) {
snprintf(name, NAME_SIZE, "cpu%d", i);
object_initialize_child(obj, name, &s->cpu[i], sizeof(s->cpu[i]),
"cortex-a9-" TYPE_ARM_CPU, &error_abort, NULL);
@@ -93,9 +95,11 @@ static void fsl_imx6_init(Object *obj)
static void fsl_imx6_realize(DeviceState *dev, Error **errp)
{
+ MachineState *ms = MACHINE(qdev_get_machine());
FslIMX6State *s = FSL_IMX6(dev);
uint16_t i;
Error *err = NULL;
+ unsigned int smp_cpus = ms->smp.cpus;
if (smp_cpus > FSL_IMX6_NUM_CPUS) {
error_setg(errp, "%s: Only %d CPUs are supported (%d requested)",
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
index 05505bac56..f860165438 100644
--- a/hw/arm/fsl-imx6ul.c
+++ b/hw/arm/fsl-imx6ul.c
@@ -20,6 +20,7 @@
#include "qapi/error.h"
#include "hw/arm/fsl-imx6ul.h"
#include "hw/misc/unimp.h"
+#include "hw/boards.h"
#include "sysemu/sysemu.h"
#include "qemu/error-report.h"
#include "qemu/module.h"
@@ -28,11 +29,12 @@
static void fsl_imx6ul_init(Object *obj)
{
+ MachineState *ms = MACHINE(qdev_get_machine());
FslIMX6ULState *s = FSL_IMX6UL(obj);
char name[NAME_SIZE];
int i;
- for (i = 0; i < MIN(smp_cpus, FSL_IMX6UL_NUM_CPUS); i++) {
+ for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX6UL_NUM_CPUS); i++) {
snprintf(name, NAME_SIZE, "cpu%d", i);
object_initialize_child(obj, name, &s->cpu[i], sizeof(s->cpu[i]),
"cortex-a7-" TYPE_ARM_CPU, &error_abort, NULL);
@@ -156,10 +158,12 @@ static void fsl_imx6ul_init(Object *obj)
static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
{
+ MachineState *ms = MACHINE(qdev_get_machine());
FslIMX6ULState *s = FSL_IMX6UL(dev);
int i;
qemu_irq irq;
char name[NAME_SIZE];
+ unsigned int smp_cpus = ms->smp.cpus;
if (smp_cpus > FSL_IMX6UL_NUM_CPUS) {
error_setg(errp, "%s: Only %d CPUs are supported (%d requested)",
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
index 2eddf3f25c..119b281a50 100644
--- a/hw/arm/fsl-imx7.c
+++ b/hw/arm/fsl-imx7.c
@@ -22,6 +22,7 @@
#include "qapi/error.h"
#include "hw/arm/fsl-imx7.h"
#include "hw/misc/unimp.h"
+#include "hw/boards.h"
#include "sysemu/sysemu.h"
#include "qemu/error-report.h"
#include "qemu/module.h"
@@ -30,12 +31,12 @@
static void fsl_imx7_init(Object *obj)
{
+ MachineState *ms = MACHINE(qdev_get_machine());
FslIMX7State *s = FSL_IMX7(obj);
char name[NAME_SIZE];
int i;
-
- for (i = 0; i < MIN(smp_cpus, FSL_IMX7_NUM_CPUS); i++) {
+ for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX7_NUM_CPUS); i++) {
snprintf(name, NAME_SIZE, "cpu%d", i);
object_initialize_child(obj, name, &s->cpu[i], sizeof(s->cpu[i]),
ARM_CPU_TYPE_NAME("cortex-a7"), &error_abort,
@@ -155,11 +156,13 @@ static void fsl_imx7_init(Object *obj)
static void fsl_imx7_realize(DeviceState *dev, Error **errp)
{
+ MachineState *ms = MACHINE(qdev_get_machine());
FslIMX7State *s = FSL_IMX7(dev);
Object *o;
int i;
qemu_irq irq;
char name[NAME_SIZE];
+ unsigned int smp_cpus = ms->smp.cpus;
if (smp_cpus > FSL_IMX7_NUM_CPUS) {
error_setg(errp, "%s: Only %d CPUs are supported (%d requested)",
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index 72ca78108a..def0f1ce6a 100644
--- a/hw/arm/highbank.c
+++ b/hw/arm/highbank.c
@@ -241,6 +241,7 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
SysBusDevice *busdev;
qemu_irq pic[128];
int n;
+ unsigned int smp_cpus = machine->smp.cpus;
qemu_irq cpu_irq[4];
qemu_irq cpu_fiq[4];
qemu_irq cpu_virq[4];
diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c
index 31511059e4..bbffb11c2a 100644
--- a/hw/arm/mcimx6ul-evk.c
+++ b/hw/arm/mcimx6ul-evk.c
@@ -42,7 +42,7 @@ static void mcimx6ul_evk_init(MachineState *machine)
.kernel_filename = machine->kernel_filename,
.kernel_cmdline = machine->kernel_cmdline,
.initrd_filename = machine->initrd_filename,
- .nb_cpus = smp_cpus,
+ .nb_cpus = machine->smp.cpus,
};
object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c
index d6b190d85d..72eab03a0c 100644
--- a/hw/arm/mcimx7d-sabre.c
+++ b/hw/arm/mcimx7d-sabre.c
@@ -45,7 +45,7 @@ static void mcimx7d_sabre_init(MachineState *machine)
.kernel_filename = machine->kernel_filename,
.kernel_cmdline = machine->kernel_cmdline,
.initrd_filename = machine->initrd_filename,
- .nb_cpus = smp_cpus,
+ .nb_cpus = machine->smp.cpus,
};
object_initialize(&s->soc, sizeof(s->soc), TYPE_FSL_IMX7);
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index cb23330940..5b2620acb4 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -116,7 +116,7 @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
binfo.board_id = raspi_boardid[version];
binfo.ram_size = ram_size;
- binfo.nb_cpus = smp_cpus;
+ binfo.nb_cpus = machine->smp.cpus;
if (version <= 2) {
/* The rpi1 and 2 require some custom setup code to run in Secure
@@ -194,7 +194,7 @@ static void raspi_init(MachineState *machine, int version)
/* Setup the SOC */
object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram),
&error_abort);
- object_property_set_int(OBJECT(&s->soc), smp_cpus, "enabled-cpus",
+ object_property_set_int(OBJECT(&s->soc), machine->smp.cpus, "enabled-cpus",
&error_abort);
int board_rev = version == 3 ? 0xa02082 : 0xa21041;
object_property_set_int(OBJECT(&s->soc), board_rev, "board-rev",
diff --git a/hw/arm/realview.c b/hw/arm/realview.c
index 12d6e93a35..7c56c8d2ed 100644
--- a/hw/arm/realview.c
+++ b/hw/arm/realview.c
@@ -69,6 +69,7 @@ static void realview_init(MachineState *machine,
NICInfo *nd;
I2CBus *i2c;
int n;
+ unsigned int smp_cpus = machine->smp.cpus;
int done_nic = 0;
qemu_irq cpu_irq[4];
int is_mpcore = 0;
diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c
index 97230ac827..934f4c9261 100644
--- a/hw/arm/sabrelite.c
+++ b/hw/arm/sabrelite.c
@@ -105,7 +105,7 @@ static void sabrelite_init(MachineState *machine)
sabrelite_binfo.kernel_filename = machine->kernel_filename;
sabrelite_binfo.kernel_cmdline = machine->kernel_cmdline;
sabrelite_binfo.initrd_filename = machine->initrd_filename;
- sabrelite_binfo.nb_cpus = smp_cpus;
+ sabrelite_binfo.nb_cpus = machine->smp.cpus;
sabrelite_binfo.secure_boot = true;
sabrelite_binfo.write_secondary_boot = sabrelite_write_secondary;
sabrelite_binfo.secondary_cpu_reset_hook = sabrelite_reset_secondary;
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index ee53f0ff60..e8c65e31c7 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -328,6 +328,7 @@ static void create_secure_ram(SBSAMachineState *sms,
static void create_gic(SBSAMachineState *sms, qemu_irq *pic)
{
+ unsigned int smp_cpus = MACHINE(sms)->smp.cpus;
DeviceState *gicdev;
SysBusDevice *gicbusdev;
const char *gictype;
@@ -585,6 +586,8 @@ static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size)
static void sbsa_ref_init(MachineState *machine)
{
+ unsigned int smp_cpus = machine->smp.cpus;
+ unsigned int max_cpus = machine->smp.max_cpus;
SBSAMachineState *sms = SBSA_MACHINE(machine);
MachineClass *mc = MACHINE_GET_CLASS(machine);
MemoryRegion *sysmem = get_system_memory();
@@ -727,6 +730,7 @@ static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx)
static const CPUArchIdList *sbsa_ref_possible_cpu_arch_ids(MachineState *ms)
{
+ unsigned int max_cpus = ms->smp.max_cpus;
SBSAMachineState *sms = SBSA_MACHINE(ms);
int n;
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index 2b3b0c2334..5d932c27c0 100644
--- a/hw/arm/vexpress.c
+++ b/hw/arm/vexpress.c
@@ -203,12 +203,14 @@ struct VEDBoardInfo {
DBoardInitFn *init;
};
-static void init_cpus(const char *cpu_type, const char *privdev,
- hwaddr periphbase, qemu_irq *pic, bool secure, bool virt)
+static void init_cpus(MachineState *ms, const char *cpu_type,
+ const char *privdev, hwaddr periphbase,
+ qemu_irq *pic, bool secure, bool virt)
{
DeviceState *dev;
SysBusDevice *busdev;
int n;
+ unsigned int smp_cpus = ms->smp.cpus;
/* Create the actual CPUs */
for (n = 0; n < smp_cpus; n++) {
@@ -269,6 +271,7 @@ static void a9_daughterboard_init(const VexpressMachineState *vms,
const char *cpu_type,
qemu_irq *pic)
{
+ MachineState *machine = MACHINE(vms);
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *lowram = g_new(MemoryRegion, 1);
@@ -295,7 +298,7 @@ static void a9_daughterboard_init(const VexpressMachineState *vms,
memory_region_add_subregion(sysmem, 0x60000000, ram);
/* 0x1e000000 A9MPCore (SCU) private memory region */
- init_cpus(cpu_type, TYPE_A9MPCORE_PRIV, 0x1e000000, pic,
+ init_cpus(machine, cpu_type, TYPE_A9MPCORE_PRIV, 0x1e000000, pic,
vms->secure, vms->virt);
/* Daughterboard peripherals : 0x10020000 .. 0x20000000 */
@@ -355,6 +358,7 @@ static void a15_daughterboard_init(const VexpressMachineState *vms,
const char *cpu_type,
qemu_irq *pic)
{
+ MachineState *machine = MACHINE(vms);
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *sram = g_new(MemoryRegion, 1);
@@ -377,8 +381,8 @@ static void a15_daughterboard_init(const VexpressMachineState *vms,
memory_region_add_subregion(sysmem, 0x80000000, ram);
/* 0x2c000000 A15MPCore private memory region (GIC) */
- init_cpus(cpu_type, TYPE_A15MPCORE_PRIV, 0x2c000000, pic, vms->secure,
- vms->virt);
+ init_cpus(machine, cpu_type, TYPE_A15MPCORE_PRIV,
+ 0x2c000000, pic, vms->secure, vms->virt);
/* A15 daughterboard peripherals: */
@@ -706,7 +710,7 @@ static void vexpress_common_init(MachineState *machine)
daughterboard->bootinfo.kernel_filename = machine->kernel_filename;
daughterboard->bootinfo.kernel_cmdline = machine->kernel_cmdline;
daughterboard->bootinfo.initrd_filename = machine->initrd_filename;
- daughterboard->bootinfo.nb_cpus = smp_cpus;
+ daughterboard->bootinfo.nb_cpus = machine->smp.cpus;
daughterboard->bootinfo.board_id = VEXPRESS_BOARD_ID;
daughterboard->bootinfo.loader_start = daughterboard->loader_start;
daughterboard->bootinfo.smp_loader_start = map[VE_SRAM];
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 7b63a924a3..20f191bc93 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -559,11 +559,13 @@ static void create_v2m(VirtMachineState *vms, qemu_irq *pic)
static void create_gic(VirtMachineState *vms, qemu_irq *pic)
{
+ MachineState *ms = MACHINE(vms);
/* We create a standalone GIC */
DeviceState *gicdev;
SysBusDevice *gicbusdev;
const char *gictype;
int type = vms->gic_version, i;
+ unsigned int smp_cpus = ms->smp.cpus;
uint32_t nb_redist_regions = 0;
gictype = (type == 3) ? gicv3_class_name() : gic_class_name();
@@ -1039,13 +1041,14 @@ static bool virt_firmware_init(VirtMachineState *vms,
static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as)
{
+ MachineState *ms = MACHINE(vms);
hwaddr base = vms->memmap[VIRT_FW_CFG].base;
hwaddr size = vms->memmap[VIRT_FW_CFG].size;
FWCfgState *fw_cfg;
char *nodename;
fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as);
- fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
+ fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus);
nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
qemu_fdt_add_subnode(vms->fdt, nodename);
@@ -1478,6 +1481,8 @@ static void machvirt_init(MachineState *machine)
MemoryRegion *ram = g_new(MemoryRegion, 1);
bool firmware_loaded;
bool aarch64 = true;
+ unsigned int smp_cpus = machine->smp.cpus;
+ unsigned int max_cpus = machine->smp.max_cpus;
/*
* In accelerated mode, the memory map is computed earlier in kvm_type()
@@ -1845,6 +1850,7 @@ static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
{
int n;
+ unsigned int max_cpus = ms->smp.max_cpus;
VirtMachineState *vms = VIRT_MACHINE(ms);
if (ms->possible_cpus) {
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index a1ca9b5adf..a60830d37a 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -21,6 +21,7 @@
#include "cpu.h"
#include "hw/arm/xlnx-zynqmp.h"
#include "hw/intc/arm_gic_common.h"
+#include "hw/boards.h"
#include "exec/address-spaces.h"
#include "sysemu/kvm.h"
#include "kvm_arm.h"
@@ -171,12 +172,13 @@ static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
}
-static void xlnx_zynqmp_create_rpu(XlnxZynqMPState *s, const char *boot_cpu,
- Error **errp)
+static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s,
+ const char *boot_cpu, Error **errp)
{
Error *err = NULL;
int i;
- int num_rpus = MIN(smp_cpus - XLNX_ZYNQMP_NUM_APU_CPUS, XLNX_ZYNQMP_NUM_RPU_CPUS);
+ int num_rpus = MIN(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS,
+ XLNX_ZYNQMP_NUM_RPU_CPUS);
if (num_rpus <= 0) {
/* Don't create rpu-cluster object if there's nothing to put in it */
@@ -221,9 +223,10 @@ static void xlnx_zynqmp_create_rpu(XlnxZynqMPState *s, const char *boot_cpu,
static void xlnx_zynqmp_init(Object *obj)
{
+ MachineState *ms = MACHINE(qdev_get_machine());
XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
int i;
- int num_apus = MIN(smp_cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
+ int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
object_initialize_child(obj, "apu-cluster", &s->apu_cluster,
sizeof(s->apu_cluster), TYPE_CPU_CLUSTER,
@@ -290,11 +293,12 @@ static void xlnx_zynqmp_init(Object *obj)
static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
{
+ MachineState *ms = MACHINE(qdev_get_machine());
XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
MemoryRegion *system_memory = get_system_memory();
uint8_t i;
uint64_t ram_size;
- int num_apus = MIN(smp_cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
+ int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]";
ram_addr_t ddr_low_size, ddr_high_size;
qemu_irq gic_spi[GIC_NUM_SPI_INTR];
@@ -456,7 +460,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
"RPUs just use -smp 6.");
}
- xlnx_zynqmp_create_rpu(s, boot_cpu, &err);
+ xlnx_zynqmp_create_rpu(ms, s, boot_cpu, &err);
if (err) {
error_propagate(errp, err);
return;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index ca718fb38f..e75a64a25a 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -31,6 +31,7 @@
#include "hw/qdev-properties.h"
#if !defined(CONFIG_USER_ONLY)
#include "hw/loader.h"
+#include "hw/boards.h"
#endif
#include "sysemu/sysemu.h"
#include "sysemu/tcg.h"
@@ -1587,6 +1588,9 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
init_cpreg_list(cpu);
#ifndef CONFIG_USER_ONLY
+ MachineState *ms = MACHINE(qdev_get_machine());
+ unsigned int smp_cpus = ms->smp.cpus;
+
if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) {
cs->num_ases = 2;
@@ -2127,10 +2131,12 @@ static void cortex_a9_initfn(Object *obj)
#ifndef CONFIG_USER_ONLY
static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
+ MachineState *ms = MACHINE(qdev_get_machine());
+
/* Linux wants the number of processors from here.
* Might as well set the interrupt-controller bit too.
*/
- return ((smp_cpus - 1) << 24) | (1 << 23);
+ return ((ms->smp.cpus - 1) << 24) | (1 << 23);
}
#endif
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PULL v6 09/42] hw: Replace global smp variables with MachineState for all remaining archs
2019-07-05 22:14 [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 Eduardo Habkost
` (7 preceding siblings ...)
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 08/42] hw/arm: " Eduardo Habkost
@ 2019-07-05 22:14 ` Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 10/42] vl.c: Replace smp global variables with smp machine properties Eduardo Habkost
` (34 subsequent siblings)
43 siblings, 0 replies; 49+ messages in thread
From: Eduardo Habkost @ 2019-07-05 22:14 UTC (permalink / raw)
To: Peter Maydell, Paolo Bonzini, qemu-devel, Marcel Apfelbaum,
Richard Henderson
Cc: Like Xu
From: Like Xu <like.xu@linux.intel.com>
The global smp variables in alpha/hppa/mips/openrisc/sparc*/xtensa codes
are replaced with smp properties from MachineState.
A local variable of the same name would be introduced in the declaration
phase if it's used widely in the context OR replace it on the spot if it's
only used once. No semantic changes.
Signed-off-by: Like Xu <like.xu@linux.intel.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20190518205428.90532-10-like.xu@linux.intel.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
hw/alpha/dp264.c | 1 +
hw/hppa/machine.c | 2 ++
hw/mips/boston.c | 2 +-
hw/mips/mips_malta.c | 2 ++
hw/openrisc/openrisc_sim.c | 1 +
hw/sparc/sun4m.c | 2 ++
hw/sparc64/sun4u.c | 4 ++--
hw/xtensa/sim.c | 2 +-
hw/xtensa/xtfpga.c | 1 +
9 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/hw/alpha/dp264.c b/hw/alpha/dp264.c
index 0347eb897c..9dfb835013 100644
--- a/hw/alpha/dp264.c
+++ b/hw/alpha/dp264.c
@@ -63,6 +63,7 @@ static void clipper_init(MachineState *machine)
char *palcode_filename;
uint64_t palcode_entry, palcode_low, palcode_high;
uint64_t kernel_entry, kernel_low, kernel_high;
+ unsigned int smp_cpus = machine->smp.cpus;
/* Create up to 4 cpus. */
memset(cpus, 0, sizeof(cpus));
diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c
index 416e67bab1..662838d83b 100644
--- a/hw/hppa/machine.c
+++ b/hw/hppa/machine.c
@@ -72,6 +72,7 @@ static void machine_hppa_init(MachineState *machine)
MemoryRegion *ram_region;
MemoryRegion *cpu_region;
long i;
+ unsigned int smp_cpus = machine->smp.cpus;
ram_size = machine->ram_size;
@@ -242,6 +243,7 @@ static void machine_hppa_init(MachineState *machine)
static void hppa_machine_reset(MachineState *ms)
{
+ unsigned int smp_cpus = ms->smp.cpus;
int i;
qemu_devices_reset();
diff --git a/hw/mips/boston.c b/hw/mips/boston.c
index 749582e5aa..9eeccbea9a 100644
--- a/hw/mips/boston.c
+++ b/hw/mips/boston.c
@@ -458,7 +458,7 @@ static void boston_mach_init(MachineState *machine)
sizeof(s->cps), TYPE_MIPS_CPS);
object_property_set_str(OBJECT(&s->cps), machine->cpu_type, "cpu-type",
&err);
- object_property_set_int(OBJECT(&s->cps), smp_cpus, "num-vp", &err);
+ object_property_set_int(OBJECT(&s->cps), machine->smp.cpus, "num-vp", &err);
object_property_set_bool(OBJECT(&s->cps), true, "realized", &err);
if (err != NULL) {
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 132127882d..20e019bf66 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -1095,6 +1095,8 @@ static int64_t load_kernel (void)
static void malta_mips_config(MIPSCPU *cpu)
{
+ MachineState *ms = MACHINE(qdev_get_machine());
+ unsigned int smp_cpus = ms->smp.cpus;
CPUMIPSState *env = &cpu->env;
CPUState *cs = CPU(cpu);
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
index 87b9feaa96..b85f0df323 100644
--- a/hw/openrisc/openrisc_sim.c
+++ b/hw/openrisc/openrisc_sim.c
@@ -130,6 +130,7 @@ static void openrisc_sim_init(MachineState *machine)
qemu_irq *cpu_irqs[2];
qemu_irq serial_irq;
int n;
+ unsigned int smp_cpus = machine->smp.cpus;
for (n = 0; n < smp_cpus; n++) {
cpu = OPENRISC_CPU(cpu_create(machine->cpu_type));
diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c
index 99f53e87f7..b2342f2a89 100644
--- a/hw/sparc/sun4m.c
+++ b/hw/sparc/sun4m.c
@@ -871,6 +871,8 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
FWCfgState *fw_cfg;
DeviceState *dev;
SysBusDevice *s;
+ unsigned int smp_cpus = machine->smp.cpus;
+ unsigned int max_cpus = machine->smp.max_cpus;
/* init CPUs */
for(i = 0; i < smp_cpus; i++) {
diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c
index 4230b17b87..5d87be811d 100644
--- a/hw/sparc64/sun4u.c
+++ b/hw/sparc64/sun4u.c
@@ -697,8 +697,8 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
&FW_CFG_IO(dev)->comb_iomem);
fw_cfg = FW_CFG(dev);
- fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
- fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
+ fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)machine->smp.cpus);
+ fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus);
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry);
diff --git a/hw/xtensa/sim.c b/hw/xtensa/sim.c
index b6922c39d5..09165b6f4d 100644
--- a/hw/xtensa/sim.c
+++ b/hw/xtensa/sim.c
@@ -59,7 +59,7 @@ static void xtensa_sim_init(MachineState *machine)
const char *kernel_filename = machine->kernel_filename;
int n;
- for (n = 0; n < smp_cpus; n++) {
+ for (n = 0; n < machine->smp.cpus; n++) {
cpu = XTENSA_CPU(cpu_create(machine->cpu_type));
env = &cpu->env;
diff --git a/hw/xtensa/xtfpga.c b/hw/xtensa/xtfpga.c
index e05ef75a75..f7f3e11e93 100644
--- a/hw/xtensa/xtfpga.c
+++ b/hw/xtensa/xtfpga.c
@@ -238,6 +238,7 @@ static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine)
const unsigned system_io_size = 224 * MiB;
uint32_t freq = 10000000;
int n;
+ unsigned int smp_cpus = machine->smp.cpus;
if (smp_cpus > 1) {
mx_pic = xtensa_mx_pic_init(31);
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PULL v6 10/42] vl.c: Replace smp global variables with smp machine properties
2019-07-05 22:14 [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 Eduardo Habkost
` (8 preceding siblings ...)
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 09/42] hw: Replace global smp variables with MachineState for all remaining archs Eduardo Habkost
@ 2019-07-05 22:14 ` Eduardo Habkost
2019-07-08 14:56 ` Laurent Desnogues
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 11/42] i386: Add die-level cpu topology to x86CPU on PCMachine Eduardo Habkost
` (33 subsequent siblings)
43 siblings, 1 reply; 49+ messages in thread
From: Eduardo Habkost @ 2019-07-05 22:14 UTC (permalink / raw)
To: Peter Maydell, Paolo Bonzini, qemu-devel, Marcel Apfelbaum,
Richard Henderson
Cc: Like Xu
From: Like Xu <like.xu@linux.intel.com>
The global smp variables in vl.c are completely replaced with machine properties.
Form this commit, the smp_cpus/smp_cores/smp_threads/max_cpus are deprecated
and only machine properties within MachineState are fully applied and enabled.
Signed-off-by: Like Xu <like.xu@linux.intel.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20190518205428.90532-11-like.xu@linux.intel.com>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
vl.c | 53 ++++++++++++++++++++++++++---------------------------
1 file changed, 26 insertions(+), 27 deletions(-)
diff --git a/vl.c b/vl.c
index d657faec03..56aa221385 100644
--- a/vl.c
+++ b/vl.c
@@ -163,10 +163,6 @@ static Chardev **serial_hds;
Chardev *parallel_hds[MAX_PARALLEL_PORTS];
int win2k_install_hack = 0;
int singlestep = 0;
-int smp_cpus;
-unsigned int max_cpus;
-int smp_cores = 1;
-int smp_threads = 1;
int acpi_enabled = 1;
int no_hpet = 0;
int fd_bootchk = 1;
@@ -1265,8 +1261,9 @@ static void smp_parse(QemuOpts *opts)
sockets = sockets > 0 ? sockets : 1;
cpus = cores * threads * sockets;
} else {
- max_cpus = qemu_opt_get_number(opts, "maxcpus", cpus);
- sockets = max_cpus / (cores * threads);
+ current_machine->smp.max_cpus =
+ qemu_opt_get_number(opts, "maxcpus", cpus);
+ sockets = current_machine->smp.max_cpus / (cores * threads);
}
} else if (cores == 0) {
threads = threads > 0 ? threads : 1;
@@ -1283,34 +1280,37 @@ static void smp_parse(QemuOpts *opts)
exit(1);
}
- max_cpus = qemu_opt_get_number(opts, "maxcpus", cpus);
+ current_machine->smp.max_cpus =
+ qemu_opt_get_number(opts, "maxcpus", cpus);
- if (max_cpus < cpus) {
+ if (current_machine->smp.max_cpus < cpus) {
error_report("maxcpus must be equal to or greater than smp");
exit(1);
}
- if (sockets * cores * threads > max_cpus) {
+ if (sockets * cores * threads > current_machine->smp.max_cpus) {
error_report("cpu topology: "
"sockets (%u) * cores (%u) * threads (%u) > "
"maxcpus (%u)",
- sockets, cores, threads, max_cpus);
+ sockets, cores, threads,
+ current_machine->smp.max_cpus);
exit(1);
}
- if (sockets * cores * threads != max_cpus) {
+ if (sockets * cores * threads != current_machine->smp.max_cpus) {
warn_report("Invalid CPU topology deprecated: "
"sockets (%u) * cores (%u) * threads (%u) "
"!= maxcpus (%u)",
- sockets, cores, threads, max_cpus);
+ sockets, cores, threads,
+ current_machine->smp.max_cpus);
}
- smp_cpus = cpus;
- smp_cores = cores;
- smp_threads = threads;
+ current_machine->smp.cpus = cpus;
+ current_machine->smp.cores = cores;
+ current_machine->smp.threads = threads;
}
- if (smp_cpus > 1) {
+ if (current_machine->smp.cpus > 1) {
Error *blocker = NULL;
error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp");
replay_add_blocker(blocker);
@@ -4009,26 +4009,25 @@ int main(int argc, char **argv, char **envp)
machine_class->default_cpus = machine_class->default_cpus ?: 1;
/* default to machine_class->default_cpus */
- smp_cpus = machine_class->default_cpus;
- max_cpus = machine_class->default_cpus;
+ current_machine->smp.cpus = machine_class->default_cpus;
+ current_machine->smp.max_cpus = machine_class->default_cpus;
+ current_machine->smp.cores = 1;
+ current_machine->smp.threads = 1;
smp_parse(qemu_opts_find(qemu_find_opts("smp-opts"), NULL));
- current_machine->smp.cpus = smp_cpus;
- current_machine->smp.max_cpus = max_cpus;
- current_machine->smp.cores = smp_cores;
- current_machine->smp.threads = smp_threads;
-
/* sanity-check smp_cpus and max_cpus against machine_class */
- if (smp_cpus < machine_class->min_cpus) {
+ if (current_machine->smp.cpus < machine_class->min_cpus) {
error_report("Invalid SMP CPUs %d. The min CPUs "
- "supported by machine '%s' is %d", smp_cpus,
+ "supported by machine '%s' is %d",
+ current_machine->smp.cpus,
machine_class->name, machine_class->min_cpus);
exit(1);
}
- if (max_cpus > machine_class->max_cpus) {
+ if (current_machine->smp.max_cpus > machine_class->max_cpus) {
error_report("Invalid SMP CPUs %d. The max CPUs "
- "supported by machine '%s' is %d", max_cpus,
+ "supported by machine '%s' is %d",
+ current_machine->smp.max_cpus,
machine_class->name, machine_class->max_cpus);
exit(1);
}
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PULL v6 11/42] i386: Add die-level cpu topology to x86CPU on PCMachine
2019-07-05 22:14 [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 Eduardo Habkost
` (9 preceding siblings ...)
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 10/42] vl.c: Replace smp global variables with smp machine properties Eduardo Habkost
@ 2019-07-05 22:14 ` Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 12/42] hw/i386: Adjust nr_dies with configured smp_dies for PCMachine Eduardo Habkost
` (32 subsequent siblings)
43 siblings, 0 replies; 49+ messages in thread
From: Eduardo Habkost @ 2019-07-05 22:14 UTC (permalink / raw)
To: Peter Maydell, Paolo Bonzini, qemu-devel, Marcel Apfelbaum,
Richard Henderson
Cc: Like Xu
From: Like Xu <like.xu@linux.intel.com>
The die-level as the first PC-specific cpu topology is added to the leagcy
cpu topology model, which has one die per package implicitly and only the
numbers of sockets/cores/threads are configurable.
In the new model with die-level support, the total number of logical
processors (including offline) on board will be calculated as:
#cpus = #sockets * #dies * #cores * #threads
and considering compatibility, the default value for #dies would be
initialized to one in x86_cpu_initfn() and pc_machine_initfn().
Signed-off-by: Like Xu <like.xu@linux.intel.com>
Message-Id: <20190612084104.34984-2-like.xu@linux.intel.com>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
include/hw/i386/pc.h | 2 ++
target/i386/cpu.h | 2 ++
hw/i386/pc.c | 9 +++++++--
target/i386/cpu.c | 1 +
4 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index de3bd32f52..e56c1a39cb 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -24,6 +24,7 @@
* PCMachineState:
* @acpi_dev: link to ACPI PM device that performs ACPI hotplug handling
* @boot_cpus: number of present VCPUs
+ * @smp_dies: number of dies per one package
*/
struct PCMachineState {
/*< private >*/
@@ -59,6 +60,7 @@ struct PCMachineState {
bool apic_xrupt_override;
unsigned apic_id_limit;
uint16_t boot_cpus;
+ unsigned smp_dies;
/* NUMA information: */
uint64_t numa_nodes;
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 93345792f4..14c19e61b1 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1385,6 +1385,8 @@ typedef struct CPUX86State {
uint64_t xss;
TPRAccess tpr_access_type;
+
+ unsigned nr_dies;
} CPUX86State;
struct kvm_msrs;
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 269e44f0d0..d44b2d06db 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -2303,9 +2303,13 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
return;
}
- /* if APIC ID is not set, set it based on socket/core/thread properties */
+ /*
+ * If APIC ID is not set,
+ * set it based on socket/die/core/thread properties.
+ */
if (cpu->apic_id == UNASSIGNED_APIC_ID) {
- int max_socket = (ms->smp.max_cpus - 1) / smp_threads / smp_cores;
+ int max_socket = (ms->smp.max_cpus - 1) /
+ smp_threads / smp_cores / pcms->smp_dies;
if (cpu->socket_id < 0) {
error_setg(errp, "CPU socket-id is not set");
@@ -2684,6 +2688,7 @@ static void pc_machine_initfn(Object *obj)
pcms->smbus_enabled = true;
pcms->sata_enabled = true;
pcms->pit_enabled = true;
+ pcms->smp_dies = 1;
pc_system_flash_create(pcms);
}
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 4b5cd49338..8ef3063140 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -5639,6 +5639,7 @@ static void x86_cpu_initfn(Object *obj)
CPUX86State *env = &cpu->env;
FeatureWord w;
+ env->nr_dies = 1;
cpu_set_cpustate_pointers(cpu);
object_property_add(obj, "family", "int",
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PULL v6 12/42] hw/i386: Adjust nr_dies with configured smp_dies for PCMachine
2019-07-05 22:14 [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 Eduardo Habkost
` (10 preceding siblings ...)
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 11/42] i386: Add die-level cpu topology to x86CPU on PCMachine Eduardo Habkost
@ 2019-07-05 22:14 ` Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 13/42] i386/cpu: Consolidate die-id validity in smp context Eduardo Habkost
` (31 subsequent siblings)
43 siblings, 0 replies; 49+ messages in thread
From: Eduardo Habkost @ 2019-07-05 22:14 UTC (permalink / raw)
To: Peter Maydell, Paolo Bonzini, qemu-devel, Marcel Apfelbaum,
Richard Henderson
Cc: Like Xu
From: Like Xu <like.xu@linux.intel.com>
To support multiple dies configuration on PCMachine, the best place to
set CPUX86State->nr_dies with requested PCMachineState->smp_dies is in
pc_new_cpu() and pc_cpu_pre_plug(). Refactoring pc_new_cpu() is applied
and redundant parameter "const char *typename" would be removed.
Suggested-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Like Xu <like.xu@linux.intel.com>
Message-Id: <20190612084104.34984-3-like.xu@linux.intel.com>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
hw/i386/pc.c | 16 +++++++++++-----
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index d44b2d06db..4dac96860d 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1514,12 +1514,16 @@ void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
}
}
-static void pc_new_cpu(const char *typename, int64_t apic_id, Error **errp)
+static void pc_new_cpu(PCMachineState *pcms, int64_t apic_id, Error **errp)
{
Object *cpu = NULL;
Error *local_err = NULL;
+ CPUX86State *env = NULL;
- cpu = object_new(typename);
+ cpu = object_new(MACHINE(pcms)->cpu_type);
+
+ env = &X86_CPU(cpu)->env;
+ env->nr_dies = pcms->smp_dies;
object_property_set_uint(cpu, apic_id, "apic-id", &local_err);
object_property_set_bool(cpu, true, "realized", &local_err);
@@ -1546,7 +1550,7 @@ void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp)
return;
}
- pc_new_cpu(ms->cpu_type, apic_id, &local_err);
+ pc_new_cpu(PC_MACHINE(ms), apic_id, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
@@ -1571,8 +1575,7 @@ void pc_cpus_init(PCMachineState *pcms)
ms->smp.max_cpus - 1) + 1;
possible_cpus = mc->possible_cpu_arch_ids(ms);
for (i = 0; i < ms->smp.cpus; i++) {
- pc_new_cpu(possible_cpus->cpus[i].type, possible_cpus->cpus[i].arch_id,
- &error_fatal);
+ pc_new_cpu(pcms, possible_cpus->cpus[i].arch_id, &error_fatal);
}
}
@@ -2292,6 +2295,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
CPUArchId *cpu_slot;
X86CPUTopoInfo topo;
X86CPU *cpu = X86_CPU(dev);
+ CPUX86State *env = &cpu->env;
MachineState *ms = MACHINE(hotplug_dev);
PCMachineState *pcms = PC_MACHINE(hotplug_dev);
unsigned int smp_cores = ms->smp.cores;
@@ -2303,6 +2307,8 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
return;
}
+ env->nr_dies = pcms->smp_dies;
+
/*
* If APIC ID is not set,
* set it based on socket/die/core/thread properties.
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PULL v6 13/42] i386/cpu: Consolidate die-id validity in smp context
2019-07-05 22:14 [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 Eduardo Habkost
` (11 preceding siblings ...)
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 12/42] hw/i386: Adjust nr_dies with configured smp_dies for PCMachine Eduardo Habkost
@ 2019-07-05 22:14 ` Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 14/42] i386: Update new x86_apicid parsing rules with die_offset support Eduardo Habkost
` (30 subsequent siblings)
43 siblings, 0 replies; 49+ messages in thread
From: Eduardo Habkost @ 2019-07-05 22:14 UTC (permalink / raw)
To: Peter Maydell, Paolo Bonzini, qemu-devel, Marcel Apfelbaum,
Richard Henderson
Cc: Like Xu
From: Like Xu <like.xu@linux.intel.com>
The field die_id (default as 0) and has_die_id are introduced to X86CPU.
Following the legacy smp check rules, the die_id validity is added to
the same contexts as leagcy smp variables such as hmp_hotpluggable_cpus(),
machine_set_cpu_numa_node(), cpu_slot_to_string() and pc_cpu_pre_plug().
Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Signed-off-by: Like Xu <like.xu@linux.intel.com>
Message-Id: <20190612084104.34984-4-like.xu@linux.intel.com>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
qapi/machine.json | 7 ++++---
include/hw/i386/topology.h | 2 ++
target/i386/cpu.h | 1 +
hw/core/machine-hmp-cmds.c | 3 +++
hw/core/machine.c | 12 ++++++++++++
hw/i386/pc.c | 14 ++++++++++++++
target/i386/cpu.c | 2 ++
7 files changed, 38 insertions(+), 3 deletions(-)
diff --git a/qapi/machine.json b/qapi/machine.json
index 81849acb3a..979bc41e49 100644
--- a/qapi/machine.json
+++ b/qapi/machine.json
@@ -588,10 +588,10 @@
#
# @node-id: NUMA node ID the CPU belongs to
# @socket-id: socket number within node/board the CPU belongs to
-# @core-id: core number within socket the CPU belongs to
-# @thread-id: thread number within core the CPU belongs to
+# @die-id: die number within node/board the CPU belongs to (Since 4.1)
+# @core-id: core number within die the CPU belongs to# @thread-id: thread number within core the CPU belongs to
#
-# Note: currently there are 4 properties that could be present
+# Note: currently there are 5 properties that could be present
# but management should be prepared to pass through other
# properties with device_add command to allow for future
# interface extension. This also requires the filed names to be kept in
@@ -602,6 +602,7 @@
{ 'struct': 'CpuInstanceProperties',
'data': { '*node-id': 'int',
'*socket-id': 'int',
+ '*die-id': 'int',
'*core-id': 'int',
'*thread-id': 'int'
}
diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
index 1ebaee0f76..c9fb41588e 100644
--- a/include/hw/i386/topology.h
+++ b/include/hw/i386/topology.h
@@ -47,6 +47,7 @@ typedef uint32_t apic_id_t;
typedef struct X86CPUTopoInfo {
unsigned pkg_id;
+ unsigned die_id;
unsigned core_id;
unsigned smt_id;
} X86CPUTopoInfo;
@@ -130,6 +131,7 @@ static inline void x86_topo_ids_from_apicid(apic_id_t apicid,
topo->core_id = (apicid >> apicid_core_offset(nr_cores, nr_threads)) &
~(0xFFFFFFFFUL << apicid_core_width(nr_cores, nr_threads));
topo->pkg_id = apicid >> apicid_pkg_offset(nr_cores, nr_threads);
+ topo->die_id = 0;
}
/* Make APIC ID for the CPU 'cpu_index'
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 14c19e61b1..4d2ae2384e 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1500,6 +1500,7 @@ struct X86CPU {
int32_t node_id; /* NUMA node this CPU belongs to */
int32_t socket_id;
+ int32_t die_id;
int32_t core_id;
int32_t thread_id;
diff --git a/hw/core/machine-hmp-cmds.c b/hw/core/machine-hmp-cmds.c
index 7fa6075f1e..1f66bda346 100644
--- a/hw/core/machine-hmp-cmds.c
+++ b/hw/core/machine-hmp-cmds.c
@@ -86,6 +86,9 @@ void hmp_hotpluggable_cpus(Monitor *mon, const QDict *qdict)
if (c->has_socket_id) {
monitor_printf(mon, " socket-id: \"%" PRIu64 "\"\n", c->socket_id);
}
+ if (c->has_die_id) {
+ monitor_printf(mon, " die-id: \"%" PRIu64 "\"\n", c->die_id);
+ }
if (c->has_core_id) {
monitor_printf(mon, " core-id: \"%" PRIu64 "\"\n", c->core_id);
}
diff --git a/hw/core/machine.c b/hw/core/machine.c
index ea84bd6788..b35dea05bd 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -683,6 +683,11 @@ void machine_set_cpu_numa_node(MachineState *machine,
return;
}
+ if (props->has_die_id && !slot->props.has_die_id) {
+ error_setg(errp, "die-id is not supported");
+ return;
+ }
+
/* skip slots with explicit mismatch */
if (props->has_thread_id && props->thread_id != slot->props.thread_id) {
continue;
@@ -692,6 +697,10 @@ void machine_set_cpu_numa_node(MachineState *machine,
continue;
}
+ if (props->has_die_id && props->die_id != slot->props.die_id) {
+ continue;
+ }
+
if (props->has_socket_id && props->socket_id != slot->props.socket_id) {
continue;
}
@@ -949,6 +958,9 @@ static char *cpu_slot_to_string(const CPUArchId *cpu)
if (cpu->props.has_socket_id) {
g_string_append_printf(s, "socket-id: %"PRId64, cpu->props.socket_id);
}
+ if (cpu->props.has_die_id) {
+ g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id);
+ }
if (cpu->props.has_core_id) {
if (s->len) {
g_string_append_printf(s, ", ");
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 4dac96860d..f91ff5e06e 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -2324,6 +2324,10 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u",
cpu->socket_id, max_socket);
return;
+ } else if (cpu->die_id > pcms->smp_dies - 1) {
+ error_setg(errp, "Invalid CPU die-id: %u must be in range 0:%u",
+ cpu->die_id, max_socket);
+ return;
}
if (cpu->core_id < 0) {
error_setg(errp, "CPU core-id is not set");
@@ -2343,6 +2347,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
}
topo.pkg_id = cpu->socket_id;
+ topo.die_id = cpu->die_id;
topo.core_id = cpu->core_id;
topo.smt_id = cpu->thread_id;
cpu->apic_id = apicid_from_topo_ids(smp_cores, smp_threads, &topo);
@@ -2380,6 +2385,13 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
}
cpu->socket_id = topo.pkg_id;
+ if (cpu->die_id != -1 && cpu->die_id != topo.die_id) {
+ error_setg(errp, "property die-id: %u doesn't match set apic-id:"
+ " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo.die_id);
+ return;
+ }
+ cpu->die_id = topo.die_id;
+
if (cpu->core_id != -1 && cpu->core_id != topo.core_id) {
error_setg(errp, "property core-id: %u doesn't match set apic-id:"
" 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id);
@@ -2766,6 +2778,8 @@ static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms)
ms->smp.cores, ms->smp.threads, &topo);
ms->possible_cpus->cpus[i].props.has_socket_id = true;
ms->possible_cpus->cpus[i].props.socket_id = topo.pkg_id;
+ ms->possible_cpus->cpus[i].props.has_die_id = true;
+ ms->possible_cpus->cpus[i].props.die_id = topo.die_id;
ms->possible_cpus->cpus[i].props.has_core_id = true;
ms->possible_cpus->cpus[i].props.core_id = topo.core_id;
ms->possible_cpus->cpus[i].props.has_thread_id = true;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 8ef3063140..6b3d0035e0 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -5865,11 +5865,13 @@ static Property x86_cpu_properties[] = {
DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
+ DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0),
DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
#else
DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
+ DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1),
DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
#endif
DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PULL v6 14/42] i386: Update new x86_apicid parsing rules with die_offset support
2019-07-05 22:14 [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 Eduardo Habkost
` (12 preceding siblings ...)
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 13/42] i386/cpu: Consolidate die-id validity in smp context Eduardo Habkost
@ 2019-07-05 22:14 ` Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 15/42] pc: fix possible NULL pointer dereference in pc_machine_get_device_memory_region_size() Eduardo Habkost
` (29 subsequent siblings)
43 siblings, 0 replies; 49+ messages in thread
From: Eduardo Habkost @ 2019-07-05 22:14 UTC (permalink / raw)
To: Peter Maydell, Paolo Bonzini, qemu-devel, Marcel Apfelbaum,
Richard Henderson
Cc: Like Xu
From: Like Xu <like.xu@linux.intel.com>
In new sockets/dies/cores/threads model, the apicid of logical cpu could
imply die level info of guest cpu topology thus x86_apicid_from_cpu_idx()
need to be refactored with #dies value, so does apicid_*_offset().
To keep semantic compatibility, the legacy pkg_offset which helps to
generate CPUIDs such as 0x3 for L3 cache should be mapping to die_offset.
Signed-off-by: Like Xu <like.xu@linux.intel.com>
Message-Id: <20190612084104.34984-5-like.xu@linux.intel.com>
[ehabkost: squash unit test patch]
Message-Id: <20190612084104.34984-6-like.xu@linux.intel.com>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
include/hw/i386/topology.h | 76 ++++++++++++++++++++++++----------
hw/i386/pc.c | 27 +++++++-----
target/i386/cpu.c | 13 +++---
tests/test-x86-cpuid.c | 84 ++++++++++++++++++++------------------
4 files changed, 124 insertions(+), 76 deletions(-)
diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
index c9fb41588e..4ff5b2da6c 100644
--- a/include/hw/i386/topology.h
+++ b/include/hw/i386/topology.h
@@ -63,88 +63,120 @@ static unsigned apicid_bitwidth_for_count(unsigned count)
/* Bit width of the SMT_ID (thread ID) field on the APIC ID
*/
-static inline unsigned apicid_smt_width(unsigned nr_cores, unsigned nr_threads)
+static inline unsigned apicid_smt_width(unsigned nr_dies,
+ unsigned nr_cores,
+ unsigned nr_threads)
{
return apicid_bitwidth_for_count(nr_threads);
}
/* Bit width of the Core_ID field
*/
-static inline unsigned apicid_core_width(unsigned nr_cores, unsigned nr_threads)
+static inline unsigned apicid_core_width(unsigned nr_dies,
+ unsigned nr_cores,
+ unsigned nr_threads)
{
return apicid_bitwidth_for_count(nr_cores);
}
+/* Bit width of the Die_ID field */
+static inline unsigned apicid_die_width(unsigned nr_dies,
+ unsigned nr_cores,
+ unsigned nr_threads)
+{
+ return apicid_bitwidth_for_count(nr_dies);
+}
+
/* Bit offset of the Core_ID field
*/
-static inline unsigned apicid_core_offset(unsigned nr_cores,
+static inline unsigned apicid_core_offset(unsigned nr_dies,
+ unsigned nr_cores,
unsigned nr_threads)
{
- return apicid_smt_width(nr_cores, nr_threads);
+ return apicid_smt_width(nr_dies, nr_cores, nr_threads);
+}
+
+/* Bit offset of the Die_ID field */
+static inline unsigned apicid_die_offset(unsigned nr_dies,
+ unsigned nr_cores,
+ unsigned nr_threads)
+{
+ return apicid_core_offset(nr_dies, nr_cores, nr_threads) +
+ apicid_core_width(nr_dies, nr_cores, nr_threads);
}
/* Bit offset of the Pkg_ID (socket ID) field
*/
-static inline unsigned apicid_pkg_offset(unsigned nr_cores, unsigned nr_threads)
+static inline unsigned apicid_pkg_offset(unsigned nr_dies,
+ unsigned nr_cores,
+ unsigned nr_threads)
{
- return apicid_core_offset(nr_cores, nr_threads) +
- apicid_core_width(nr_cores, nr_threads);
+ return apicid_die_offset(nr_dies, nr_cores, nr_threads) +
+ apicid_die_width(nr_dies, nr_cores, nr_threads);
}
/* Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID
*
* The caller must make sure core_id < nr_cores and smt_id < nr_threads.
*/
-static inline apic_id_t apicid_from_topo_ids(unsigned nr_cores,
+static inline apic_id_t apicid_from_topo_ids(unsigned nr_dies,
+ unsigned nr_cores,
unsigned nr_threads,
const X86CPUTopoInfo *topo)
{
- return (topo->pkg_id << apicid_pkg_offset(nr_cores, nr_threads)) |
- (topo->core_id << apicid_core_offset(nr_cores, nr_threads)) |
+ return (topo->pkg_id << apicid_pkg_offset(nr_dies, nr_cores, nr_threads)) |
+ (topo->die_id << apicid_die_offset(nr_dies, nr_cores, nr_threads)) |
+ (topo->core_id << apicid_core_offset(nr_dies, nr_cores, nr_threads)) |
topo->smt_id;
}
/* Calculate thread/core/package IDs for a specific topology,
* based on (contiguous) CPU index
*/
-static inline void x86_topo_ids_from_idx(unsigned nr_cores,
+static inline void x86_topo_ids_from_idx(unsigned nr_dies,
+ unsigned nr_cores,
unsigned nr_threads,
unsigned cpu_index,
X86CPUTopoInfo *topo)
{
- unsigned core_index = cpu_index / nr_threads;
+ topo->pkg_id = cpu_index / (nr_dies * nr_cores * nr_threads);
+ topo->die_id = cpu_index / (nr_cores * nr_threads) % nr_dies;
+ topo->core_id = cpu_index / nr_threads % nr_cores;
topo->smt_id = cpu_index % nr_threads;
- topo->core_id = core_index % nr_cores;
- topo->pkg_id = core_index / nr_cores;
}
/* Calculate thread/core/package IDs for a specific topology,
* based on APIC ID
*/
static inline void x86_topo_ids_from_apicid(apic_id_t apicid,
+ unsigned nr_dies,
unsigned nr_cores,
unsigned nr_threads,
X86CPUTopoInfo *topo)
{
topo->smt_id = apicid &
- ~(0xFFFFFFFFUL << apicid_smt_width(nr_cores, nr_threads));
- topo->core_id = (apicid >> apicid_core_offset(nr_cores, nr_threads)) &
- ~(0xFFFFFFFFUL << apicid_core_width(nr_cores, nr_threads));
- topo->pkg_id = apicid >> apicid_pkg_offset(nr_cores, nr_threads);
- topo->die_id = 0;
+ ~(0xFFFFFFFFUL << apicid_smt_width(nr_dies, nr_cores, nr_threads));
+ topo->core_id =
+ (apicid >> apicid_core_offset(nr_dies, nr_cores, nr_threads)) &
+ ~(0xFFFFFFFFUL << apicid_core_width(nr_dies, nr_cores, nr_threads));
+ topo->die_id =
+ (apicid >> apicid_die_offset(nr_dies, nr_cores, nr_threads)) &
+ ~(0xFFFFFFFFUL << apicid_die_width(nr_dies, nr_cores, nr_threads));
+ topo->pkg_id = apicid >> apicid_pkg_offset(nr_dies, nr_cores, nr_threads);
}
/* Make APIC ID for the CPU 'cpu_index'
*
* 'cpu_index' is a sequential, contiguous ID for the CPU.
*/
-static inline apic_id_t x86_apicid_from_cpu_idx(unsigned nr_cores,
+static inline apic_id_t x86_apicid_from_cpu_idx(unsigned nr_dies,
+ unsigned nr_cores,
unsigned nr_threads,
unsigned cpu_index)
{
X86CPUTopoInfo topo;
- x86_topo_ids_from_idx(nr_cores, nr_threads, cpu_index, &topo);
- return apicid_from_topo_ids(nr_cores, nr_threads, &topo);
+ x86_topo_ids_from_idx(nr_dies, nr_cores, nr_threads, cpu_index, &topo);
+ return apicid_from_topo_ids(nr_dies, nr_cores, nr_threads, &topo);
}
#endif /* HW_I386_TOPOLOGY_H */
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index f91ff5e06e..e8378f6a0a 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -930,7 +930,7 @@ static uint32_t x86_cpu_apic_id_from_index(PCMachineState *pcms,
uint32_t correct_id;
static bool warned;
- correct_id = x86_apicid_from_cpu_idx(ms->smp.cores,
+ correct_id = x86_apicid_from_cpu_idx(pcms->smp_dies, ms->smp.cores,
ms->smp.threads, cpu_index);
if (pcmc->compat_apic_id_mode) {
if (cpu_index != correct_id && !warned && !qtest_enabled()) {
@@ -2350,18 +2350,21 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
topo.die_id = cpu->die_id;
topo.core_id = cpu->core_id;
topo.smt_id = cpu->thread_id;
- cpu->apic_id = apicid_from_topo_ids(smp_cores, smp_threads, &topo);
+ cpu->apic_id = apicid_from_topo_ids(pcms->smp_dies, smp_cores,
+ smp_threads, &topo);
}
cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
if (!cpu_slot) {
MachineState *ms = MACHINE(pcms);
- x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo);
- error_setg(errp, "Invalid CPU [socket: %u, core: %u, thread: %u] with"
- " APIC ID %" PRIu32 ", valid index range 0:%d",
- topo.pkg_id, topo.core_id, topo.smt_id, cpu->apic_id,
- ms->possible_cpus->len - 1);
+ x86_topo_ids_from_apicid(cpu->apic_id, pcms->smp_dies,
+ smp_cores, smp_threads, &topo);
+ error_setg(errp,
+ "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with"
+ " APIC ID %" PRIu32 ", valid index range 0:%d",
+ topo.pkg_id, topo.die_id, topo.core_id, topo.smt_id,
+ cpu->apic_id, ms->possible_cpus->len - 1);
return;
}
@@ -2377,7 +2380,8 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
/* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
* once -smp refactoring is complete and there will be CPU private
* CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
- x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo);
+ x86_topo_ids_from_apicid(cpu->apic_id, pcms->smp_dies,
+ smp_cores, smp_threads, &topo);
if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) {
error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
" 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id);
@@ -2743,10 +2747,12 @@ pc_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx)
{
X86CPUTopoInfo topo;
+ PCMachineState *pcms = PC_MACHINE(ms);
assert(idx < ms->possible_cpus->len);
x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
- ms->smp.cores, ms->smp.threads, &topo);
+ pcms->smp_dies, ms->smp.cores,
+ ms->smp.threads, &topo);
return topo.pkg_id % nb_numa_nodes;
}
@@ -2775,7 +2781,8 @@ static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms)
ms->possible_cpus->cpus[i].vcpus_count = 1;
ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(pcms, i);
x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
- ms->smp.cores, ms->smp.threads, &topo);
+ pcms->smp_dies, ms->smp.cores,
+ ms->smp.threads, &topo);
ms->possible_cpus->cpus[i].props.has_socket_id = true;
ms->possible_cpus->cpus[i].props.socket_id = topo.pkg_id;
ms->possible_cpus->cpus[i].props.has_die_id = true;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 6b3d0035e0..de1a469ae9 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -4267,7 +4267,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
{
X86CPU *cpu = env_archcpu(env);
CPUState *cs = env_cpu(env);
- uint32_t pkg_offset;
+ uint32_t die_offset;
uint32_t limit;
uint32_t signature[3];
@@ -4356,10 +4356,11 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
eax, ebx, ecx, edx);
break;
case 3: /* L3 cache info */
- pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
+ die_offset = apicid_die_offset(env->nr_dies,
+ cs->nr_cores, cs->nr_threads);
if (cpu->enable_l3_cache) {
encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache,
- (1 << pkg_offset), cs->nr_cores,
+ (1 << die_offset), cs->nr_cores,
eax, ebx, ecx, edx);
break;
}
@@ -4441,12 +4442,14 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
switch (count) {
case 0:
- *eax = apicid_core_offset(cs->nr_cores, cs->nr_threads);
+ *eax = apicid_core_offset(env->nr_dies,
+ cs->nr_cores, cs->nr_threads);
*ebx = cs->nr_threads;
*ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
break;
case 1:
- *eax = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
+ *eax = apicid_pkg_offset(env->nr_dies,
+ cs->nr_cores, cs->nr_threads);
*ebx = cs->nr_cores * cs->nr_threads;
*ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
break;
diff --git a/tests/test-x86-cpuid.c b/tests/test-x86-cpuid.c
index ff225006e4..1942287f33 100644
--- a/tests/test-x86-cpuid.c
+++ b/tests/test-x86-cpuid.c
@@ -28,74 +28,80 @@
static void test_topo_bits(void)
{
- /* simple tests for 1 thread per core, 1 core per socket */
- g_assert_cmpuint(apicid_smt_width(1, 1), ==, 0);
- g_assert_cmpuint(apicid_core_width(1, 1), ==, 0);
+ /* simple tests for 1 thread per core, 1 core per die, 1 die per package */
+ g_assert_cmpuint(apicid_smt_width(1, 1, 1), ==, 0);
+ g_assert_cmpuint(apicid_core_width(1, 1, 1), ==, 0);
+ g_assert_cmpuint(apicid_die_width(1, 1, 1), ==, 0);
- g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 0), ==, 0);
- g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 1), ==, 1);
- g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 2), ==, 2);
- g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 3), ==, 3);
+ g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 1, 0), ==, 0);
+ g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 1, 1), ==, 1);
+ g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 1, 2), ==, 2);
+ g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 1, 3), ==, 3);
/* Test field width calculation for multiple values
*/
- g_assert_cmpuint(apicid_smt_width(1, 2), ==, 1);
- g_assert_cmpuint(apicid_smt_width(1, 3), ==, 2);
- g_assert_cmpuint(apicid_smt_width(1, 4), ==, 2);
+ g_assert_cmpuint(apicid_smt_width(1, 1, 2), ==, 1);
+ g_assert_cmpuint(apicid_smt_width(1, 1, 3), ==, 2);
+ g_assert_cmpuint(apicid_smt_width(1, 1, 4), ==, 2);
- g_assert_cmpuint(apicid_smt_width(1, 14), ==, 4);
- g_assert_cmpuint(apicid_smt_width(1, 15), ==, 4);
- g_assert_cmpuint(apicid_smt_width(1, 16), ==, 4);
- g_assert_cmpuint(apicid_smt_width(1, 17), ==, 5);
+ g_assert_cmpuint(apicid_smt_width(1, 1, 14), ==, 4);
+ g_assert_cmpuint(apicid_smt_width(1, 1, 15), ==, 4);
+ g_assert_cmpuint(apicid_smt_width(1, 1, 16), ==, 4);
+ g_assert_cmpuint(apicid_smt_width(1, 1, 17), ==, 5);
- g_assert_cmpuint(apicid_core_width(30, 2), ==, 5);
- g_assert_cmpuint(apicid_core_width(31, 2), ==, 5);
- g_assert_cmpuint(apicid_core_width(32, 2), ==, 5);
- g_assert_cmpuint(apicid_core_width(33, 2), ==, 6);
+ g_assert_cmpuint(apicid_core_width(1, 30, 2), ==, 5);
+ g_assert_cmpuint(apicid_core_width(1, 31, 2), ==, 5);
+ g_assert_cmpuint(apicid_core_width(1, 32, 2), ==, 5);
+ g_assert_cmpuint(apicid_core_width(1, 33, 2), ==, 6);
+ g_assert_cmpuint(apicid_die_width(1, 30, 2), ==, 0);
+ g_assert_cmpuint(apicid_die_width(2, 30, 2), ==, 1);
+ g_assert_cmpuint(apicid_die_width(3, 30, 2), ==, 2);
+ g_assert_cmpuint(apicid_die_width(4, 30, 2), ==, 2);
/* build a weird topology and see if IDs are calculated correctly
*/
/* This will use 2 bits for thread ID and 3 bits for core ID
*/
- g_assert_cmpuint(apicid_smt_width(6, 3), ==, 2);
- g_assert_cmpuint(apicid_core_width(6, 3), ==, 3);
- g_assert_cmpuint(apicid_pkg_offset(6, 3), ==, 5);
+ g_assert_cmpuint(apicid_smt_width(1, 6, 3), ==, 2);
+ g_assert_cmpuint(apicid_core_offset(1, 6, 3), ==, 2);
+ g_assert_cmpuint(apicid_die_offset(1, 6, 3), ==, 5);
+ g_assert_cmpuint(apicid_pkg_offset(1, 6, 3), ==, 5);
- g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 0), ==, 0);
- g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 1), ==, 1);
- g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 2), ==, 2);
+ g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 0), ==, 0);
+ g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 1), ==, 1);
+ g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 2), ==, 2);
- g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 1 * 3 + 0), ==,
+ g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 1 * 3 + 0), ==,
(1 << 2) | 0);
- g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 1 * 3 + 1), ==,
+ g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 1 * 3 + 1), ==,
(1 << 2) | 1);
- g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 1 * 3 + 2), ==,
+ g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 1 * 3 + 2), ==,
(1 << 2) | 2);
- g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 2 * 3 + 0), ==,
+ g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 2 * 3 + 0), ==,
(2 << 2) | 0);
- g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 2 * 3 + 1), ==,
+ g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 2 * 3 + 1), ==,
(2 << 2) | 1);
- g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 2 * 3 + 2), ==,
+ g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 2 * 3 + 2), ==,
(2 << 2) | 2);
- g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 5 * 3 + 0), ==,
+ g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 5 * 3 + 0), ==,
(5 << 2) | 0);
- g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 5 * 3 + 1), ==,
+ g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 5 * 3 + 1), ==,
(5 << 2) | 1);
- g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 5 * 3 + 2), ==,
+ g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 5 * 3 + 2), ==,
(5 << 2) | 2);
- g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 1 * 6 * 3 + 0 * 3 + 0), ==,
- (1 << 5));
- g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 1 * 6 * 3 + 1 * 3 + 1), ==,
- (1 << 5) | (1 << 2) | 1);
- g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 3 * 6 * 3 + 5 * 3 + 2), ==,
- (3 << 5) | (5 << 2) | 2);
+ g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3,
+ 1 * 6 * 3 + 0 * 3 + 0), ==, (1 << 5));
+ g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3,
+ 1 * 6 * 3 + 1 * 3 + 1), ==, (1 << 5) | (1 << 2) | 1);
+ g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3,
+ 3 * 6 * 3 + 5 * 3 + 2), ==, (3 << 5) | (5 << 2) | 2);
}
int main(int argc, char **argv)
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PULL v6 15/42] pc: fix possible NULL pointer dereference in pc_machine_get_device_memory_region_size()
2019-07-05 22:14 [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 Eduardo Habkost
` (13 preceding siblings ...)
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 14/42] i386: Update new x86_apicid parsing rules with die_offset support Eduardo Habkost
@ 2019-07-05 22:14 ` Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 16/42] machine: show if CLI option '-numa node, mem' is supported in QAPI schema Eduardo Habkost
` (28 subsequent siblings)
43 siblings, 0 replies; 49+ messages in thread
From: Eduardo Habkost @ 2019-07-05 22:14 UTC (permalink / raw)
To: Peter Maydell, Paolo Bonzini, qemu-devel, Marcel Apfelbaum,
Richard Henderson
Cc: Igor Mammedov
From: Igor Mammedov <imammedo@redhat.com>
QEMU will crash when device-memory-region-size property is read if ms->device_memory
wasn't initialized yet.
Crash can be reproduced with:
$QEMU -preconfig -qmp unix:qmp_socket,server,nowait &
./scripts/qmp/qom-get -s qmp_socket /machine.device-memory-region-size
Instead of crashing return 0 if ms->device_memory hasn't been initialized.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20190624090200.5383-1-imammedo@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
hw/i386/pc.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index e8378f6a0a..2107532d12 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -2553,7 +2553,11 @@ pc_machine_get_device_memory_region_size(Object *obj, Visitor *v,
Error **errp)
{
MachineState *ms = MACHINE(obj);
- int64_t value = memory_region_size(&ms->device_memory->mr);
+ int64_t value = 0;
+
+ if (ms->device_memory) {
+ value = memory_region_size(&ms->device_memory->mr);
+ }
visit_type_int(v, name, &value, errp);
}
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PULL v6 16/42] machine: show if CLI option '-numa node, mem' is supported in QAPI schema
2019-07-05 22:14 [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 Eduardo Habkost
` (14 preceding siblings ...)
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 15/42] pc: fix possible NULL pointer dereference in pc_machine_get_device_memory_region_size() Eduardo Habkost
@ 2019-07-05 22:14 ` Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 17/42] numa: deprecate 'mem' parameter of '-numa node' option Eduardo Habkost
` (27 subsequent siblings)
43 siblings, 0 replies; 49+ messages in thread
From: Eduardo Habkost @ 2019-07-05 22:14 UTC (permalink / raw)
To: Peter Maydell, Paolo Bonzini, qemu-devel, Marcel Apfelbaum,
Richard Henderson
Cc: Igor Mammedov
From: Igor Mammedov <imammedo@redhat.com>
Legacy '-numa node,mem' option has a number of issues and mgmt often
defaults to it. Unfortunately it's no possible to replace it with
an alternative '-numa memdev' without breaking migration compatibility.
What's possible though is to deprecate it, keeping option working with
old machine types only.
In order to help users to find out if being deprecated CLI option
'-numa node,mem' is still supported by particular machine type, add new
"numa-mem-supported" property to output of query-machines.
"numa-mem-supported" is set to 'true' for machines that currently support
NUMA, but it will be flipped to 'false' later on, once deprecation period
expires and kept 'true' only for old machine types that used to support
the legacy option so it won't break existing configuration that are using
it.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <1560172207-378962-1-git-send-email-imammedo@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
qapi/machine.json | 5 ++++-
include/hw/boards.h | 3 +++
hw/arm/virt.c | 1 +
hw/core/machine-qmp-cmds.c | 1 +
hw/i386/pc.c | 1 +
hw/ppc/spapr.c | 1 +
6 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/qapi/machine.json b/qapi/machine.json
index 979bc41e49..78d34ef717 100644
--- a/qapi/machine.json
+++ b/qapi/machine.json
@@ -318,12 +318,15 @@
#
# @hotpluggable-cpus: cpu hotplug via -device is supported (since 2.7.0)
#
+# @numa-mem-supported: true if '-numa node,mem' option is supported by
+# the machine type and false otherwise (since 4.1)
+#
# Since: 1.2.0
##
{ 'struct': 'MachineInfo',
'data': { 'name': 'str', '*alias': 'str',
'*is-default': 'bool', 'cpu-max': 'int',
- 'hotpluggable-cpus': 'bool'} }
+ 'hotpluggable-cpus': 'bool', 'numa-mem-supported': 'bool'} }
##
# @query-machines:
diff --git a/include/hw/boards.h b/include/hw/boards.h
index d84f48c4af..ae7a542511 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -160,6 +160,8 @@ typedef struct {
* @kvm_type:
* Return the type of KVM corresponding to the kvm-type string option or
* computed based on other criteria such as the host kernel capabilities.
+ * @numa_mem_supported:
+ * true if '--numa node.mem' option is supported and false otherwise
*/
struct MachineClass {
/*< private >*/
@@ -212,6 +214,7 @@ struct MachineClass {
bool ignore_boot_device_suffixes;
bool smbus_no_migration_support;
bool nvdimm_supported;
+ bool numa_mem_supported;
HotplugHandler *(*get_hotplug_handler)(MachineState *machine,
DeviceState *dev);
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 20f191bc93..0b5138cb22 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -1952,6 +1952,7 @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
assert(!mc->get_hotplug_handler);
mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
hc->plug = virt_machine_device_plug_cb;
+ mc->numa_mem_supported = true;
}
static void virt_instance_init(Object *obj)
diff --git a/hw/core/machine-qmp-cmds.c b/hw/core/machine-qmp-cmds.c
index 14dbad1d6e..754ce77664 100644
--- a/hw/core/machine-qmp-cmds.c
+++ b/hw/core/machine-qmp-cmds.c
@@ -226,6 +226,7 @@ MachineInfoList *qmp_query_machines(Error **errp)
info->name = g_strdup(mc->name);
info->cpu_max = !mc->max_cpus ? 1 : mc->max_cpus;
info->hotpluggable_cpus = mc->has_hotpluggable_cpus;
+ info->numa_mem_supported = mc->numa_mem_supported;
entry = g_malloc0(sizeof(*entry));
entry->value = info;
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 2107532d12..14f7b4532e 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -2856,6 +2856,7 @@ static void pc_machine_class_init(ObjectClass *oc, void *data)
nc->nmi_monitor_handler = x86_nmi;
mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
mc->nvdimm_supported = true;
+ mc->numa_mem_supported = true;
object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int",
pc_machine_get_device_memory_region_size, NULL,
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 51256ac9ca..821f0d4a49 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -4367,6 +4367,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data)
* in which LMBs are represented and hot-added
*/
mc->numa_mem_align_shift = 28;
+ mc->numa_mem_supported = true;
smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF;
smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON;
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PULL v6 17/42] numa: deprecate 'mem' parameter of '-numa node' option
2019-07-05 22:14 [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 Eduardo Habkost
` (15 preceding siblings ...)
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 16/42] machine: show if CLI option '-numa node, mem' is supported in QAPI schema Eduardo Habkost
@ 2019-07-05 22:14 ` Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 18/42] numa: deprecate implict memory distribution between nodes Eduardo Habkost
` (26 subsequent siblings)
43 siblings, 0 replies; 49+ messages in thread
From: Eduardo Habkost @ 2019-07-05 22:14 UTC (permalink / raw)
To: Peter Maydell, Paolo Bonzini, qemu-devel, Marcel Apfelbaum,
Richard Henderson
Cc: Igor Mammedov
From: Igor Mammedov <imammedo@redhat.com>
The parameter allows to configure fake NUMA topology where guest
VM simulates NUMA topology but not actually getting performance
benefits from it. The same or better results could be achieved
using 'memdev' parameter.
Beside of unpredictable performance, '-numa node.mem' option has
other issues when it's used with combination of -mem-path +
+ -mem-prealloc + memdev backends (pc-dimm), breaking binding of
memdev backends since mem-path/mem-prealloc are global and affect
the most of RAM allocations.
It's possible to make memdevs and global -mem-path/mem-prealloc
to play nicely together but that will just complicate already
complicated code and add unobious ways it could break on 2
different memmory allocation pathes and their combinations.
Instead of it, consolidate all guest RAM allocation over memdev
which still allows to create fake NUMA configurations if desired
and leaves one simplifyed code path to consider when it comes
to guest RAM allocation.
To achieve desired simplification deprecate 'mem' parameter as its
ad-hoc partitioning of initial RAM MemoryRegion can't be translated
to memdev based backend transparently to users and in compatible
manner (migration wise).
Later down the road that will allow to consolidate means of how
guest RAM is allocated and would permit us to clean up quite
a bit memory allocations and numa code, leaving only 'memdev'
implementation in place.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <1559205199-233510-3-git-send-email-imammedo@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
hw/core/numa.c | 2 ++
qemu-deprecated.texi | 16 ++++++++++++++++
2 files changed, 18 insertions(+)
diff --git a/hw/core/numa.c b/hw/core/numa.c
index 4252af7100..b9e79b8c8b 100644
--- a/hw/core/numa.c
+++ b/hw/core/numa.c
@@ -118,6 +118,8 @@ static void parse_numa_node(MachineState *ms, NumaNodeOptions *node,
if (node->has_mem) {
numa_info[nodenr].node_mem = node->mem;
+ warn_report("Parameter -numa node,mem is deprecated,"
+ " use -numa node,memdev instead");
}
if (node->has_memdev) {
Object *o;
diff --git a/qemu-deprecated.texi b/qemu-deprecated.texi
index 40c017b426..ba52999f7f 100644
--- a/qemu-deprecated.texi
+++ b/qemu-deprecated.texi
@@ -88,6 +88,22 @@ The @code{-realtime mlock=on|off} argument has been replaced by the
The ``-virtfs_synth'' argument is now deprecated. Please use ``-fsdev synth''
and ``-device virtio-9p-...'' instead.
+@subsection -numa node,mem=@var{size} (since 4.1)
+
+The parameter @option{mem} of @option{-numa node} is used to assign a part of
+guest RAM to a NUMA node. But when using it, it's impossible to manage specified
+RAM chunk on the host side (like bind it to a host node, setting bind policy, ...),
+so guest end-ups with the fake NUMA configuration with suboptiomal performance.
+However since 2014 there is an alternative way to assign RAM to a NUMA node
+using parameter @option{memdev}, which does the same as @option{mem} and adds
+means to actualy manage node RAM on the host side. Use parameter @option{memdev}
+with @var{memory-backend-ram} backend as an replacement for parameter @option{mem}
+to achieve the same fake NUMA effect or a properly configured
+@var{memory-backend-file} backend to actually benefit from NUMA configuration.
+In future new machine versions will not accept the option but it will still
+work with old machine types. User can check QAPI schema to see if the legacy
+option is supported by looking at MachineInfo::numa-mem-supported property.
+
@section QEMU Machine Protocol (QMP) commands
@subsection block-dirty-bitmap-add "autoload" parameter (since 2.12.0)
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PULL v6 18/42] numa: deprecate implict memory distribution between nodes
2019-07-05 22:14 [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 Eduardo Habkost
` (16 preceding siblings ...)
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 17/42] numa: deprecate 'mem' parameter of '-numa node' option Eduardo Habkost
@ 2019-07-05 22:14 ` Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 19/42] hppa: Delete unused hppa_cpu_list() function Eduardo Habkost
` (25 subsequent siblings)
43 siblings, 0 replies; 49+ messages in thread
From: Eduardo Habkost @ 2019-07-05 22:14 UTC (permalink / raw)
To: Peter Maydell, Paolo Bonzini, qemu-devel, Marcel Apfelbaum,
Richard Henderson
Cc: Igor Mammedov
From: Igor Mammedov <imammedo@redhat.com>
Implicit RAM distribution between nodes has exactly the same issues as:
"numa: deprecate 'mem' parameter of '-numa node' option"
only with QEMU being the user that's 'adding' 'mem' parameter.
Deprecate it, to get it out of the way so that we could consolidate
guest RAM allocation using memory backends making it consistent and
possibly later on transition to using memory devices instead of
adhoc memory mapping for the initial RAM.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <1559205199-233510-4-git-send-email-imammedo@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
hw/core/numa.c | 3 +++
qemu-deprecated.texi | 8 ++++++++
2 files changed, 11 insertions(+)
diff --git a/hw/core/numa.c b/hw/core/numa.c
index b9e79b8c8b..cb5fdbcb1e 100644
--- a/hw/core/numa.c
+++ b/hw/core/numa.c
@@ -405,6 +405,9 @@ void numa_complete_configuration(MachineState *ms)
if (i == nb_numa_nodes) {
assert(mc->numa_auto_assign_ram);
mc->numa_auto_assign_ram(mc, numa_info, nb_numa_nodes, ram_size);
+ warn_report("Default splitting of RAM between nodes is deprecated,"
+ " Use '-numa node,memdev' to explictly define RAM"
+ " allocation per node");
}
numa_total = 0;
diff --git a/qemu-deprecated.texi b/qemu-deprecated.texi
index ba52999f7f..4a626f535d 100644
--- a/qemu-deprecated.texi
+++ b/qemu-deprecated.texi
@@ -104,6 +104,14 @@ In future new machine versions will not accept the option but it will still
work with old machine types. User can check QAPI schema to see if the legacy
option is supported by looking at MachineInfo::numa-mem-supported property.
+@subsection -numa node (without memory specified) (since 4.1)
+
+Splitting RAM by default between NUMA nodes has the same issues as @option{mem}
+parameter described above with the difference that the role of the user plays
+QEMU using implicit generic or board specific splitting rule.
+Use @option{memdev} with @var{memory-backend-ram} backend or @option{mem} (if
+it's supported by used machine type) to define mapping explictly instead.
+
@section QEMU Machine Protocol (QMP) commands
@subsection block-dirty-bitmap-add "autoload" parameter (since 2.12.0)
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PULL v6 19/42] hppa: Delete unused hppa_cpu_list() function
2019-07-05 22:14 [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 Eduardo Habkost
` (17 preceding siblings ...)
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 18/42] numa: deprecate implict memory distribution between nodes Eduardo Habkost
@ 2019-07-05 22:14 ` Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 20/42] deprecate -mem-path fallback to anonymous RAM Eduardo Habkost
` (24 subsequent siblings)
43 siblings, 0 replies; 49+ messages in thread
From: Eduardo Habkost @ 2019-07-05 22:14 UTC (permalink / raw)
To: Peter Maydell, Paolo Bonzini, qemu-devel, Marcel Apfelbaum,
Richard Henderson
hppa_cpu_list() is dead code and is never called. Delete it.
Cc: Richard Henderson <rth@twiddle.net>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Message-Id: <20190517191332.23400-1-ehabkost@redhat.com>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
target/hppa/cpu.h | 2 --
target/hppa/cpu.c | 17 -----------------
2 files changed, 19 deletions(-)
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 2e1f2ac67c..aab251bc4b 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -241,8 +241,6 @@ void hppa_translate_init(void);
#define CPU_RESOLVING_TYPE TYPE_HPPA_CPU
-void hppa_cpu_list(void);
-
static inline target_ulong hppa_form_gva_psw(target_ureg psw, uint64_t spc,
target_ureg off)
{
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 368cb71e6d..71b6aca45d 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -111,23 +111,6 @@ static void hppa_cpu_realizefn(DeviceState *dev, Error **errp)
#endif
}
-static void hppa_cpu_list_entry(gpointer data, gpointer user_data)
-{
- ObjectClass *oc = data;
-
- qemu_printf(" %s\n", object_class_get_name(oc));
-}
-
-void hppa_cpu_list(void)
-{
- GSList *list;
-
- list = object_class_get_list_sorted(TYPE_HPPA_CPU, false);
- qemu_printf("Available CPUs:\n");
- g_slist_foreach(list, hppa_cpu_list_entry, NULL);
- g_slist_free(list);
-}
-
static void hppa_cpu_initfn(Object *obj)
{
CPUState *cs = CPU(obj);
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PULL v6 20/42] deprecate -mem-path fallback to anonymous RAM
2019-07-05 22:14 [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 Eduardo Habkost
` (18 preceding siblings ...)
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 19/42] hppa: Delete unused hppa_cpu_list() function Eduardo Habkost
@ 2019-07-05 22:14 ` Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 21/42] i386: Don't print warning if phys-bits was set automatically Eduardo Habkost
` (23 subsequent siblings)
43 siblings, 0 replies; 49+ messages in thread
From: Eduardo Habkost @ 2019-07-05 22:14 UTC (permalink / raw)
To: Peter Maydell, Paolo Bonzini, qemu-devel, Marcel Apfelbaum,
Richard Henderson
Cc: Igor Mammedov
From: Igor Mammedov <imammedo@redhat.com>
Fallback might affect guest or worse whole host performance
or functionality if backing file were used to share guest RAM
with another process.
Patch deprecates fallback so that we could remove it in future
and ensure that QEMU will provide expected behavior and fail if
it can't use user provided backing file.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20190626074228.11558-1-imammedo@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
hw/core/numa.c | 6 ++++--
qemu-deprecated.texi | 9 +++++++++
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/hw/core/numa.c b/hw/core/numa.c
index cb5fdbcb1e..dd5c6e2334 100644
--- a/hw/core/numa.c
+++ b/hw/core/numa.c
@@ -479,8 +479,10 @@ static void allocate_system_memory_nonnuma(MemoryRegion *mr, Object *owner,
if (mem_prealloc) {
exit(1);
}
- error_report("falling back to regular RAM allocation.");
-
+ warn_report("falling back to regular RAM allocation");
+ error_printf("This is deprecated. Make sure that -mem-path "
+ " specified path has sufficient resources to allocate"
+ " -m specified RAM amount");
/* Legacy behavior: if allocation failed, fall back to
* regular RAM allocation.
*/
diff --git a/qemu-deprecated.texi b/qemu-deprecated.texi
index 4a626f535d..e6891c3a93 100644
--- a/qemu-deprecated.texi
+++ b/qemu-deprecated.texi
@@ -112,6 +112,15 @@ QEMU using implicit generic or board specific splitting rule.
Use @option{memdev} with @var{memory-backend-ram} backend or @option{mem} (if
it's supported by used machine type) to define mapping explictly instead.
+@subsection -mem-path fallback to RAM (since 4.1)
+Currently if guest RAM allocation from file pointed by @option{mem-path}
+fails, QEMU falls back to allocating from RAM, which might result
+in unpredictable behavior since the backing file specified by the user
+is ignored. In the future, users will be responsible for making sure
+the backing storage specified with @option{-mem-path} can actually provide
+the guest RAM configured with @option{-m} and QEMU will fail to start up if
+RAM allocation is unsuccessful.
+
@section QEMU Machine Protocol (QMP) commands
@subsection block-dirty-bitmap-add "autoload" parameter (since 2.12.0)
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PULL v6 21/42] i386: Don't print warning if phys-bits was set automatically
2019-07-05 22:14 [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 Eduardo Habkost
` (19 preceding siblings ...)
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 20/42] deprecate -mem-path fallback to anonymous RAM Eduardo Habkost
@ 2019-07-05 22:14 ` Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 22/42] i386: Fix signedness of hyperv_spinlock_attempts Eduardo Habkost
` (22 subsequent siblings)
43 siblings, 0 replies; 49+ messages in thread
From: Eduardo Habkost @ 2019-07-05 22:14 UTC (permalink / raw)
To: Peter Maydell, Paolo Bonzini, qemu-devel, Marcel Apfelbaum,
Richard Henderson
If cpu->host_phys_bits_limit is set, QEMU will make
cpu->phys_bits be lower than host_phys_bits on some cases. This
triggers a warning that was supposed to be printed only if
phys-bits was explicitly set in the command-line.
Reorder the code so the value of cpu->phys_bits is validated
before the cpu->host_phys_bits handling. This will avoid
unexpected warnings when cpu->host_phys_bits_limit is set.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Message-Id: <20190611205420.20286-1-ehabkost@redhat.com>
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
target/i386/cpu.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index de1a469ae9..f538b54150 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -5293,15 +5293,6 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
uint32_t host_phys_bits = x86_host_phys_bits();
static bool warned;
- if (cpu->host_phys_bits) {
- /* The user asked for us to use the host physical bits */
- cpu->phys_bits = host_phys_bits;
- if (cpu->host_phys_bits_limit &&
- cpu->phys_bits > cpu->host_phys_bits_limit) {
- cpu->phys_bits = cpu->host_phys_bits_limit;
- }
- }
-
/* Print a warning if the user set it to a value that's not the
* host value.
*/
@@ -5313,6 +5304,15 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
warned = true;
}
+ if (cpu->host_phys_bits) {
+ /* The user asked for us to use the host physical bits */
+ cpu->phys_bits = host_phys_bits;
+ if (cpu->host_phys_bits_limit &&
+ cpu->phys_bits > cpu->host_phys_bits_limit) {
+ cpu->phys_bits = cpu->host_phys_bits_limit;
+ }
+ }
+
if (cpu->phys_bits &&
(cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
cpu->phys_bits < 32)) {
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PULL v6 22/42] i386: Fix signedness of hyperv_spinlock_attempts
2019-07-05 22:14 [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 Eduardo Habkost
` (20 preceding siblings ...)
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 21/42] i386: Don't print warning if phys-bits was set automatically Eduardo Habkost
@ 2019-07-05 22:14 ` Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 23/42] i386: make 'hv-spinlocks' a regular uint32 property Eduardo Habkost
` (21 subsequent siblings)
43 siblings, 0 replies; 49+ messages in thread
From: Eduardo Habkost @ 2019-07-05 22:14 UTC (permalink / raw)
To: Peter Maydell, Paolo Bonzini, qemu-devel, Marcel Apfelbaum,
Richard Henderson
The current default value for hv-spinlocks is 0xFFFFFFFF (meaning
"never retry"). However, the value is stored as a signed
integer, making the getter of the hv-spinlocks QOM property
return -1 instead of 0xFFFFFFFF.
Fix this by changing the type of X86CPU::hyperv_spinlock_attempts
to uint32_t. This has no visible effect to guest operating
systems, affecting just the behavior of the QOM getter.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Message-Id: <20190615200505.31348-1-ehabkost@redhat.com>
Reviewed-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Reviewed-by: Roman Kagan <rkagan@virtuozzo.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
target/i386/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 4d2ae2384e..ff26351538 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1408,7 +1408,7 @@ struct X86CPU {
CPUNegativeOffsetState neg;
CPUX86State env;
- int hyperv_spinlock_attempts;
+ uint32_t hyperv_spinlock_attempts;
char *hyperv_vendor_id;
bool hyperv_synic_kvm_only;
uint64_t hyperv_features;
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PULL v6 23/42] i386: make 'hv-spinlocks' a regular uint32 property
2019-07-05 22:14 [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 Eduardo Habkost
` (21 preceding siblings ...)
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 22/42] i386: Fix signedness of hyperv_spinlock_attempts Eduardo Habkost
@ 2019-07-05 22:14 ` Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 24/42] x86/cpu: use FeatureWordArray to define filtered_features Eduardo Habkost
` (20 subsequent siblings)
43 siblings, 0 replies; 49+ messages in thread
From: Eduardo Habkost @ 2019-07-05 22:14 UTC (permalink / raw)
To: Peter Maydell, Paolo Bonzini, qemu-devel, Marcel Apfelbaum,
Richard Henderson
Cc: Roman Kagan
From: Roman Kagan <rkagan@virtuozzo.com>
X86CPU.hv-spinlocks is a uint32 property that has a special setter
validating the value to be no less than 0xFFF and no bigger than
UINT_MAX. The latter check is redundant; as for the former, there
appears to be no reason to prohibit the user from setting it to a lower
value.
So nuke the dedicated getter/setter pair and convert 'hv-spinlocks' to a
regular uint32 property.
Signed-off-by: Roman Kagan <rkagan@virtuozzo.com>
Message-Id: <20190618110659.14744-1-rkagan@virtuozzo.com>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
target/i386/cpu.c | 45 ++-------------------------------------------
1 file changed, 2 insertions(+), 43 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index f538b54150..6787da4209 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3518,46 +3518,6 @@ static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
}
-static void x86_get_hv_spinlocks(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
- X86CPU *cpu = X86_CPU(obj);
- int64_t value = cpu->hyperv_spinlock_attempts;
-
- visit_type_int(v, name, &value, errp);
-}
-
-static void x86_set_hv_spinlocks(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
- const int64_t min = 0xFFF;
- const int64_t max = UINT_MAX;
- X86CPU *cpu = X86_CPU(obj);
- Error *err = NULL;
- int64_t value;
-
- visit_type_int(v, name, &value, &err);
- if (err) {
- error_propagate(errp, err);
- return;
- }
-
- if (value < min || value > max) {
- error_setg(errp, "Property %s.%s doesn't take value %" PRId64
- " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
- object_get_typename(obj), name ? name : "null",
- value, min, max);
- return;
- }
- cpu->hyperv_spinlock_attempts = value;
-}
-
-static const PropertyInfo qdev_prop_spinlocks = {
- .name = "int",
- .get = x86_get_hv_spinlocks,
- .set = x86_set_hv_spinlocks,
-};
-
/* Convert all '_' in a feature string option name to '-', to make feature
* name conform to QOM property naming rule, which uses '-' instead of '_'.
*/
@@ -5682,8 +5642,6 @@ static void x86_cpu_initfn(Object *obj)
object_property_add(obj, "crash-information", "GuestPanicInformation",
x86_cpu_get_crash_info_qom, NULL, NULL, NULL, NULL);
- cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
-
for (w = 0; w < FEATURE_WORDS; w++) {
int bitnr;
@@ -5880,7 +5838,8 @@ static Property x86_cpu_properties[] = {
DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
- { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
+ DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts,
+ HYPERV_SPINLOCK_NEVER_RETRY),
DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features,
HYPERV_FEAT_RELAXED, 0),
DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features,
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PULL v6 24/42] x86/cpu: use FeatureWordArray to define filtered_features
2019-07-05 22:14 [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 Eduardo Habkost
` (22 preceding siblings ...)
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 23/42] i386: make 'hv-spinlocks' a regular uint32 property Eduardo Habkost
@ 2019-07-05 22:14 ` Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 25/42] i386: Remove unused host_cpudef variable Eduardo Habkost
` (19 subsequent siblings)
43 siblings, 0 replies; 49+ messages in thread
From: Eduardo Habkost @ 2019-07-05 22:14 UTC (permalink / raw)
To: Peter Maydell, Paolo Bonzini, qemu-devel, Marcel Apfelbaum,
Richard Henderson
Cc: Wei Yang
From: Wei Yang <richardw.yang@linux.intel.com>
Use the same definition as features/user_features in CPUX86State.
Signed-off-by: Wei Yang <richardw.yang@linux.intel.com>
Message-Id: <20190620023746.9869-1-richardw.yang@linux.intel.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
target/i386/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index ff26351538..85319f4ae1 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1440,7 +1440,7 @@ struct X86CPU {
} mwait;
/* Features that were filtered out because of missing host capabilities */
- uint32_t filtered_features[FEATURE_WORDS];
+ FeatureWordArray filtered_features;
/* Enable PMU CPUID bits. This can't be enabled by default yet because
* it doesn't have ABI stability guarantees, as it passes all PMU CPUID
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PULL v6 25/42] i386: Remove unused host_cpudef variable
2019-07-05 22:14 [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 Eduardo Habkost
` (23 preceding siblings ...)
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 24/42] x86/cpu: use FeatureWordArray to define filtered_features Eduardo Habkost
@ 2019-07-05 22:14 ` Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 26/42] target/i386: Add CPUID.1F generation support for multi-dies PCMachine Eduardo Habkost
` (18 subsequent siblings)
43 siblings, 0 replies; 49+ messages in thread
From: Eduardo Habkost @ 2019-07-05 22:14 UTC (permalink / raw)
To: Peter Maydell, Paolo Bonzini, qemu-devel, Marcel Apfelbaum,
Richard Henderson
The variable is completely unused, probably a leftover from
previous code clean up.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Message-Id: <20190625050008.12789-3-ehabkost@redhat.com>
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
target/i386/cpu.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 6787da4209..b9d6f32945 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3134,14 +3134,8 @@ static void max_x86_cpu_initfn(Object *obj)
char vendor[CPUID_VENDOR_SZ + 1] = { 0 };
char model_id[CPUID_MODEL_ID_SZ + 1] = { 0 };
int family, model, stepping;
- X86CPUDefinition host_cpudef = { };
- uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
-
- host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
- x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
host_vendor_fms(vendor, &family, &model, &stepping);
-
cpu_x86_fill_model_id(model_id);
object_property_set_str(OBJECT(cpu), vendor, "vendor", &error_abort);
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PULL v6 26/42] target/i386: Add CPUID.1F generation support for multi-dies PCMachine
2019-07-05 22:14 [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 Eduardo Habkost
` (24 preceding siblings ...)
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 25/42] i386: Remove unused host_cpudef variable Eduardo Habkost
@ 2019-07-05 22:14 ` Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 27/42] machine: Refactor smp_parse() in vl.c as MachineClass::smp_parse() Eduardo Habkost
` (17 subsequent siblings)
43 siblings, 0 replies; 49+ messages in thread
From: Eduardo Habkost @ 2019-07-05 22:14 UTC (permalink / raw)
To: Peter Maydell, Paolo Bonzini, qemu-devel, Marcel Apfelbaum,
Richard Henderson
Cc: Like Xu
From: Like Xu <like.xu@linux.intel.com>
The CPUID.1F as Intel V2 Extended Topology Enumeration Leaf would be
exposed if guests want to emulate multiple software-visible die within
each package. Per Intel's SDM, the 0x1f is a superset of 0xb, thus they
can be generated by almost same code as 0xb except die_offset setting.
If the number of dies per package is greater than 1, the cpuid_min_level
would be adjusted to 0x1f regardless of whether the host supports CPUID.1F.
Likewise, the CPUID.1F wouldn't be exposed if env->nr_dies < 2.
Suggested-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Like Xu <like.xu@linux.intel.com>
Message-Id: <20190620054525.37188-2-like.xu@linux.intel.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
target/i386/cpu.h | 1 +
target/i386/cpu.c | 41 +++++++++++++++++++++++++++++++++++++++++
target/i386/kvm.c | 12 ++++++++++++
3 files changed, 54 insertions(+)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 85319f4ae1..0a96c78669 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -736,6 +736,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
#define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8)
#define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8)
#define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8)
+#define CPUID_TOPOLOGY_LEVEL_DIE (5U << 8)
/* MSR Feature Bits */
#define MSR_ARCH_CAP_RDCL_NO (1U << 0)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index b9d6f32945..296ef6c918 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -4413,6 +4413,42 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
*ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
}
+ assert(!(*eax & ~0x1f));
+ *ebx &= 0xffff; /* The count doesn't need to be reliable. */
+ break;
+ case 0x1F:
+ /* V2 Extended Topology Enumeration Leaf */
+ if (env->nr_dies < 2) {
+ *eax = *ebx = *ecx = *edx = 0;
+ break;
+ }
+
+ *ecx = count & 0xff;
+ *edx = cpu->apic_id;
+ switch (count) {
+ case 0:
+ *eax = apicid_core_offset(env->nr_dies, cs->nr_cores,
+ cs->nr_threads);
+ *ebx = cs->nr_threads;
+ *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
+ break;
+ case 1:
+ *eax = apicid_die_offset(env->nr_dies, cs->nr_cores,
+ cs->nr_threads);
+ *ebx = cs->nr_cores * cs->nr_threads;
+ *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
+ break;
+ case 2:
+ *eax = apicid_pkg_offset(env->nr_dies, cs->nr_cores,
+ cs->nr_threads);
+ *ebx = env->nr_dies * cs->nr_cores * cs->nr_threads;
+ *ecx |= CPUID_TOPOLOGY_LEVEL_DIE;
+ break;
+ default:
+ *eax = 0;
+ *ebx = 0;
+ *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
+ }
assert(!(*eax & ~0x1f));
*ebx &= 0xffff; /* The count doesn't need to be reliable. */
break;
@@ -5094,6 +5130,11 @@ static void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14);
}
+ /* CPU topology with multi-dies support requires CPUID[0x1F] */
+ if (env->nr_dies > 1) {
+ x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F);
+ }
+
/* SVM requires CPUID[0x8000000A] */
if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
diff --git a/target/i386/kvm.c b/target/i386/kvm.c
index e4b4f5756a..473a17e9a5 100644
--- a/target/i386/kvm.c
+++ b/target/i386/kvm.c
@@ -1451,6 +1451,10 @@ int kvm_arch_init_vcpu(CPUState *cs)
}
break;
}
+ case 0x1f:
+ if (env->nr_dies < 2) {
+ break;
+ }
case 4:
case 0xb:
case 0xd:
@@ -1458,6 +1462,11 @@ int kvm_arch_init_vcpu(CPUState *cs)
if (i == 0xd && j == 64) {
break;
}
+
+ if (i == 0x1f && j == 64) {
+ break;
+ }
+
c->function = i;
c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
c->index = j;
@@ -1469,6 +1478,9 @@ int kvm_arch_init_vcpu(CPUState *cs)
if (i == 0xb && !(c->ecx & 0xff00)) {
break;
}
+ if (i == 0x1f && !(c->ecx & 0xff00)) {
+ break;
+ }
if (i == 0xd && c->eax == 0) {
continue;
}
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PULL v6 27/42] machine: Refactor smp_parse() in vl.c as MachineClass::smp_parse()
2019-07-05 22:14 [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 Eduardo Habkost
` (25 preceding siblings ...)
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 26/42] target/i386: Add CPUID.1F generation support for multi-dies PCMachine Eduardo Habkost
@ 2019-07-05 22:14 ` Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 28/42] vl.c: Add -smp, dies=* command line support and update doc Eduardo Habkost
` (16 subsequent siblings)
43 siblings, 0 replies; 49+ messages in thread
From: Eduardo Habkost @ 2019-07-05 22:14 UTC (permalink / raw)
To: Peter Maydell, Paolo Bonzini, qemu-devel, Marcel Apfelbaum,
Richard Henderson
Cc: Like Xu
From: Like Xu <like.xu@linux.intel.com>
To make smp_parse() more flexible and expansive, a smp_parse function
pointer is added to MachineClass that machine types could override.
The generic smp_parse() code in vl.c is moved to hw/core/machine.c, and
become the default implementation of MachineClass::smp_parse. A PC-specific
function called pc_smp_parse() has been added to hw/i386/pc.c, which in
this patch changes nothing against the default one .
Suggested-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Like Xu <like.xu@linux.intel.com>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
Message-Id: <20190620054525.37188-3-like.xu@linux.intel.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
include/hw/boards.h | 5 +++
include/hw/i386/pc.h | 1 +
hw/core/machine.c | 76 ++++++++++++++++++++++++++++++++++++++++++
hw/i386/pc.c | 79 ++++++++++++++++++++++++++++++++++++++++++++
vl.c | 75 ++---------------------------------------
5 files changed, 163 insertions(+), 73 deletions(-)
diff --git a/include/hw/boards.h b/include/hw/boards.h
index ae7a542511..a71d1a53a5 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -162,6 +162,10 @@ typedef struct {
* computed based on other criteria such as the host kernel capabilities.
* @numa_mem_supported:
* true if '--numa node.mem' option is supported and false otherwise
+ * @smp_parse:
+ * The function pointer to hook different machine specific functions for
+ * parsing "smp-opts" from QemuOpts to MachineState::CpuTopology and more
+ * machine specific topology fields, such as smp_dies for PCMachine.
*/
struct MachineClass {
/*< private >*/
@@ -178,6 +182,7 @@ struct MachineClass {
void (*reset)(MachineState *state);
void (*hot_add_cpu)(MachineState *state, const int64_t id, Error **errp);
int (*kvm_type)(MachineState *machine, const char *arg);
+ void (*smp_parse)(MachineState *ms, QemuOpts *opts);
BlockInterfaceType block_default_type;
int units_per_default_bus;
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index e56c1a39cb..0fa3e3beeb 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -192,6 +192,7 @@ void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
void pc_cpus_init(PCMachineState *pcms);
void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp);
+void pc_smp_parse(MachineState *ms, QemuOpts *opts);
void pc_guest_info_init(PCMachineState *pcms);
diff --git a/hw/core/machine.c b/hw/core/machine.c
index b35dea05bd..2be19ec0cd 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -11,6 +11,9 @@
*/
#include "qemu/osdep.h"
+#include "qemu/option.h"
+#include "qapi/qmp/qerror.h"
+#include "sysemu/replay.h"
#include "qemu/units.h"
#include "hw/boards.h"
#include "qapi/error.h"
@@ -726,6 +729,78 @@ void machine_set_cpu_numa_node(MachineState *machine,
}
}
+static void smp_parse(MachineState *ms, QemuOpts *opts)
+{
+ if (opts) {
+ unsigned cpus = qemu_opt_get_number(opts, "cpus", 0);
+ unsigned sockets = qemu_opt_get_number(opts, "sockets", 0);
+ unsigned cores = qemu_opt_get_number(opts, "cores", 0);
+ unsigned threads = qemu_opt_get_number(opts, "threads", 0);
+
+ /* compute missing values, prefer sockets over cores over threads */
+ if (cpus == 0 || sockets == 0) {
+ cores = cores > 0 ? cores : 1;
+ threads = threads > 0 ? threads : 1;
+ if (cpus == 0) {
+ sockets = sockets > 0 ? sockets : 1;
+ cpus = cores * threads * sockets;
+ } else {
+ ms->smp.max_cpus =
+ qemu_opt_get_number(opts, "maxcpus", cpus);
+ sockets = ms->smp.max_cpus / (cores * threads);
+ }
+ } else if (cores == 0) {
+ threads = threads > 0 ? threads : 1;
+ cores = cpus / (sockets * threads);
+ cores = cores > 0 ? cores : 1;
+ } else if (threads == 0) {
+ threads = cpus / (cores * sockets);
+ threads = threads > 0 ? threads : 1;
+ } else if (sockets * cores * threads < cpus) {
+ error_report("cpu topology: "
+ "sockets (%u) * cores (%u) * threads (%u) < "
+ "smp_cpus (%u)",
+ sockets, cores, threads, cpus);
+ exit(1);
+ }
+
+ ms->smp.max_cpus =
+ qemu_opt_get_number(opts, "maxcpus", cpus);
+
+ if (ms->smp.max_cpus < cpus) {
+ error_report("maxcpus must be equal to or greater than smp");
+ exit(1);
+ }
+
+ if (sockets * cores * threads > ms->smp.max_cpus) {
+ error_report("cpu topology: "
+ "sockets (%u) * cores (%u) * threads (%u) > "
+ "maxcpus (%u)",
+ sockets, cores, threads,
+ ms->smp.max_cpus);
+ exit(1);
+ }
+
+ if (sockets * cores * threads != ms->smp.max_cpus) {
+ warn_report("Invalid CPU topology deprecated: "
+ "sockets (%u) * cores (%u) * threads (%u) "
+ "!= maxcpus (%u)",
+ sockets, cores, threads,
+ ms->smp.max_cpus);
+ }
+
+ ms->smp.cpus = cpus;
+ ms->smp.cores = cores;
+ ms->smp.threads = threads;
+ }
+
+ if (ms->smp.cpus > 1) {
+ Error *blocker = NULL;
+ error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp");
+ replay_add_blocker(blocker);
+ }
+}
+
static void machine_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@@ -733,6 +808,7 @@ static void machine_class_init(ObjectClass *oc, void *data)
/* Default 128 MB as guest ram size */
mc->default_ram_size = 128 * MiB;
mc->rom_file_has_mr = true;
+ mc->smp_parse = smp_parse;
/* numa node memory size aligned on 8MB by default.
* On Linux, each node's border has to be 8MB aligned
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 14f7b4532e..894084c4e1 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -81,6 +81,8 @@
#include "standard-headers/asm-x86/bootparam.h"
#include "hw/virtio/virtio-pmem-pci.h"
#include "hw/mem/memory-device.h"
+#include "sysemu/replay.h"
+#include "qapi/qmp/qerror.h"
/* debug PC/ISA interrupts */
//#define DEBUG_IRQ
@@ -1532,6 +1534,82 @@ static void pc_new_cpu(PCMachineState *pcms, int64_t apic_id, Error **errp)
error_propagate(errp, local_err);
}
+/*
+ * This function is very similar to smp_parse()
+ * in hw/core/machine.c but includes CPU die support.
+ */
+void pc_smp_parse(MachineState *ms, QemuOpts *opts)
+{
+ if (opts) {
+ unsigned cpus = qemu_opt_get_number(opts, "cpus", 0);
+ unsigned sockets = qemu_opt_get_number(opts, "sockets", 0);
+ unsigned cores = qemu_opt_get_number(opts, "cores", 0);
+ unsigned threads = qemu_opt_get_number(opts, "threads", 0);
+
+ /* compute missing values, prefer sockets over cores over threads */
+ if (cpus == 0 || sockets == 0) {
+ cores = cores > 0 ? cores : 1;
+ threads = threads > 0 ? threads : 1;
+ if (cpus == 0) {
+ sockets = sockets > 0 ? sockets : 1;
+ cpus = cores * threads * sockets;
+ } else {
+ ms->smp.max_cpus =
+ qemu_opt_get_number(opts, "maxcpus", cpus);
+ sockets = ms->smp.max_cpus / (cores * threads);
+ }
+ } else if (cores == 0) {
+ threads = threads > 0 ? threads : 1;
+ cores = cpus / (sockets * threads);
+ cores = cores > 0 ? cores : 1;
+ } else if (threads == 0) {
+ threads = cpus / (cores * sockets);
+ threads = threads > 0 ? threads : 1;
+ } else if (sockets * cores * threads < cpus) {
+ error_report("cpu topology: "
+ "sockets (%u) * cores (%u) * threads (%u) < "
+ "smp_cpus (%u)",
+ sockets, cores, threads, cpus);
+ exit(1);
+ }
+
+ ms->smp.max_cpus =
+ qemu_opt_get_number(opts, "maxcpus", cpus);
+
+ if (ms->smp.max_cpus < cpus) {
+ error_report("maxcpus must be equal to or greater than smp");
+ exit(1);
+ }
+
+ if (sockets * cores * threads > ms->smp.max_cpus) {
+ error_report("cpu topology: "
+ "sockets (%u) * cores (%u) * threads (%u) > "
+ "maxcpus (%u)",
+ sockets, cores, threads,
+ ms->smp.max_cpus);
+ exit(1);
+ }
+
+ if (sockets * cores * threads != ms->smp.max_cpus) {
+ warn_report("Invalid CPU topology deprecated: "
+ "sockets (%u) * cores (%u) * threads (%u) "
+ "!= maxcpus (%u)",
+ sockets, cores, threads,
+ ms->smp.max_cpus);
+ }
+
+ ms->smp.cpus = cpus;
+ ms->smp.cores = cores;
+ ms->smp.threads = threads;
+ }
+
+ if (ms->smp.cpus > 1) {
+ Error *blocker = NULL;
+ error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp");
+ replay_add_blocker(blocker);
+ }
+}
+
void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp)
{
PCMachineState *pcms = PC_MACHINE(ms);
@@ -2846,6 +2924,7 @@ static void pc_machine_class_init(ObjectClass *oc, void *data)
mc->has_hotpluggable_cpus = true;
mc->default_boot_order = "cad";
mc->hot_add_cpu = pc_hot_add_cpu;
+ mc->smp_parse = pc_smp_parse;
mc->block_default_type = IF_IDE;
mc->max_cpus = 255;
mc->reset = pc_machine_reset;
diff --git a/vl.c b/vl.c
index 56aa221385..96d2456f70 100644
--- a/vl.c
+++ b/vl.c
@@ -1245,78 +1245,6 @@ static QemuOptsList qemu_smp_opts = {
},
};
-static void smp_parse(QemuOpts *opts)
-{
- if (opts) {
- unsigned cpus = qemu_opt_get_number(opts, "cpus", 0);
- unsigned sockets = qemu_opt_get_number(opts, "sockets", 0);
- unsigned cores = qemu_opt_get_number(opts, "cores", 0);
- unsigned threads = qemu_opt_get_number(opts, "threads", 0);
-
- /* compute missing values, prefer sockets over cores over threads */
- if (cpus == 0 || sockets == 0) {
- cores = cores > 0 ? cores : 1;
- threads = threads > 0 ? threads : 1;
- if (cpus == 0) {
- sockets = sockets > 0 ? sockets : 1;
- cpus = cores * threads * sockets;
- } else {
- current_machine->smp.max_cpus =
- qemu_opt_get_number(opts, "maxcpus", cpus);
- sockets = current_machine->smp.max_cpus / (cores * threads);
- }
- } else if (cores == 0) {
- threads = threads > 0 ? threads : 1;
- cores = cpus / (sockets * threads);
- cores = cores > 0 ? cores : 1;
- } else if (threads == 0) {
- threads = cpus / (cores * sockets);
- threads = threads > 0 ? threads : 1;
- } else if (sockets * cores * threads < cpus) {
- error_report("cpu topology: "
- "sockets (%u) * cores (%u) * threads (%u) < "
- "smp_cpus (%u)",
- sockets, cores, threads, cpus);
- exit(1);
- }
-
- current_machine->smp.max_cpus =
- qemu_opt_get_number(opts, "maxcpus", cpus);
-
- if (current_machine->smp.max_cpus < cpus) {
- error_report("maxcpus must be equal to or greater than smp");
- exit(1);
- }
-
- if (sockets * cores * threads > current_machine->smp.max_cpus) {
- error_report("cpu topology: "
- "sockets (%u) * cores (%u) * threads (%u) > "
- "maxcpus (%u)",
- sockets, cores, threads,
- current_machine->smp.max_cpus);
- exit(1);
- }
-
- if (sockets * cores * threads != current_machine->smp.max_cpus) {
- warn_report("Invalid CPU topology deprecated: "
- "sockets (%u) * cores (%u) * threads (%u) "
- "!= maxcpus (%u)",
- sockets, cores, threads,
- current_machine->smp.max_cpus);
- }
-
- current_machine->smp.cpus = cpus;
- current_machine->smp.cores = cores;
- current_machine->smp.threads = threads;
- }
-
- if (current_machine->smp.cpus > 1) {
- Error *blocker = NULL;
- error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp");
- replay_add_blocker(blocker);
- }
-}
-
static void realtime_init(void)
{
if (enable_mlock) {
@@ -4014,7 +3942,8 @@ int main(int argc, char **argv, char **envp)
current_machine->smp.cores = 1;
current_machine->smp.threads = 1;
- smp_parse(qemu_opts_find(qemu_find_opts("smp-opts"), NULL));
+ machine_class->smp_parse(current_machine,
+ qemu_opts_find(qemu_find_opts("smp-opts"), NULL));
/* sanity-check smp_cpus and max_cpus against machine_class */
if (current_machine->smp.cpus < machine_class->min_cpus) {
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PULL v6 28/42] vl.c: Add -smp, dies=* command line support and update doc
2019-07-05 22:14 [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 Eduardo Habkost
` (26 preceding siblings ...)
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 27/42] machine: Refactor smp_parse() in vl.c as MachineClass::smp_parse() Eduardo Habkost
@ 2019-07-05 22:14 ` Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 29/42] qmp: Add deprecation information to query-machines Eduardo Habkost
` (15 subsequent siblings)
43 siblings, 0 replies; 49+ messages in thread
From: Eduardo Habkost @ 2019-07-05 22:14 UTC (permalink / raw)
To: Peter Maydell, Paolo Bonzini, qemu-devel, Marcel Apfelbaum,
Richard Henderson
Cc: Like Xu
From: Like Xu <like.xu@linux.intel.com>
For PC target, users could configure the number of dies per one package
via command line with this patch, such as "-smp dies=2,cores=4".
The parsing rules of new cpu-topology model obey the same restrictions/logic
as the legacy socket/core/thread model especially on missing values computing.
Signed-off-by: Like Xu <like.xu@linux.intel.com>
Message-Id: <20190620054525.37188-4-like.xu@linux.intel.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
hw/i386/pc.c | 30 +++++++++++++++++-------------
vl.c | 3 +++
qemu-options.hx | 17 +++++++++--------
3 files changed, 29 insertions(+), 21 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 894084c4e1..b9c55301a2 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1540,9 +1540,12 @@ static void pc_new_cpu(PCMachineState *pcms, int64_t apic_id, Error **errp)
*/
void pc_smp_parse(MachineState *ms, QemuOpts *opts)
{
+ PCMachineState *pcms = PC_MACHINE(ms);
+
if (opts) {
unsigned cpus = qemu_opt_get_number(opts, "cpus", 0);
unsigned sockets = qemu_opt_get_number(opts, "sockets", 0);
+ unsigned dies = qemu_opt_get_number(opts, "dies", 1);
unsigned cores = qemu_opt_get_number(opts, "cores", 0);
unsigned threads = qemu_opt_get_number(opts, "threads", 0);
@@ -1552,24 +1555,24 @@ void pc_smp_parse(MachineState *ms, QemuOpts *opts)
threads = threads > 0 ? threads : 1;
if (cpus == 0) {
sockets = sockets > 0 ? sockets : 1;
- cpus = cores * threads * sockets;
+ cpus = cores * threads * dies * sockets;
} else {
ms->smp.max_cpus =
qemu_opt_get_number(opts, "maxcpus", cpus);
- sockets = ms->smp.max_cpus / (cores * threads);
+ sockets = ms->smp.max_cpus / (cores * threads * dies);
}
} else if (cores == 0) {
threads = threads > 0 ? threads : 1;
- cores = cpus / (sockets * threads);
+ cores = cpus / (sockets * dies * threads);
cores = cores > 0 ? cores : 1;
} else if (threads == 0) {
- threads = cpus / (cores * sockets);
+ threads = cpus / (cores * dies * sockets);
threads = threads > 0 ? threads : 1;
- } else if (sockets * cores * threads < cpus) {
+ } else if (sockets * dies * cores * threads < cpus) {
error_report("cpu topology: "
- "sockets (%u) * cores (%u) * threads (%u) < "
+ "sockets (%u) * dies (%u) * cores (%u) * threads (%u) < "
"smp_cpus (%u)",
- sockets, cores, threads, cpus);
+ sockets, dies, cores, threads, cpus);
exit(1);
}
@@ -1581,26 +1584,27 @@ void pc_smp_parse(MachineState *ms, QemuOpts *opts)
exit(1);
}
- if (sockets * cores * threads > ms->smp.max_cpus) {
+ if (sockets * dies * cores * threads > ms->smp.max_cpus) {
error_report("cpu topology: "
- "sockets (%u) * cores (%u) * threads (%u) > "
+ "sockets (%u) * dies (%u) * cores (%u) * threads (%u) > "
"maxcpus (%u)",
- sockets, cores, threads,
+ sockets, dies, cores, threads,
ms->smp.max_cpus);
exit(1);
}
- if (sockets * cores * threads != ms->smp.max_cpus) {
+ if (sockets * dies * cores * threads != ms->smp.max_cpus) {
warn_report("Invalid CPU topology deprecated: "
- "sockets (%u) * cores (%u) * threads (%u) "
+ "sockets (%u) * dies (%u) * cores (%u) * threads (%u) "
"!= maxcpus (%u)",
- sockets, cores, threads,
+ sockets, dies, cores, threads,
ms->smp.max_cpus);
}
ms->smp.cpus = cpus;
ms->smp.cores = cores;
ms->smp.threads = threads;
+ pcms->smp_dies = dies;
}
if (ms->smp.cpus > 1) {
diff --git a/vl.c b/vl.c
index 96d2456f70..280e709e2c 100644
--- a/vl.c
+++ b/vl.c
@@ -1231,6 +1231,9 @@ static QemuOptsList qemu_smp_opts = {
}, {
.name = "sockets",
.type = QEMU_OPT_NUMBER,
+ }, {
+ .name = "dies",
+ .type = QEMU_OPT_NUMBER,
}, {
.name = "cores",
.type = QEMU_OPT_NUMBER,
diff --git a/qemu-options.hx b/qemu-options.hx
index af850923f7..9621e934c0 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -138,25 +138,26 @@ no incompatible TCG features have been enabled (e.g. icount/replay).
ETEXI
DEF("smp", HAS_ARG, QEMU_OPTION_smp,
- "-smp [cpus=]n[,maxcpus=cpus][,cores=cores][,threads=threads][,sockets=sockets]\n"
+ "-smp [cpus=]n[,maxcpus=cpus][,cores=cores][,threads=threads][,dies=dies][,sockets=sockets]\n"
" set the number of CPUs to 'n' [default=1]\n"
" maxcpus= maximum number of total cpus, including\n"
" offline CPUs for hotplug, etc\n"
- " cores= number of CPU cores on one socket\n"
+ " cores= number of CPU cores on one socket (for PC, it's on one die)\n"
" threads= number of threads on one CPU core\n"
+ " dies= number of CPU dies on one socket (for PC only)\n"
" sockets= number of discrete sockets in the system\n",
QEMU_ARCH_ALL)
STEXI
-@item -smp [cpus=]@var{n}[,cores=@var{cores}][,threads=@var{threads}][,sockets=@var{sockets}][,maxcpus=@var{maxcpus}]
+@item -smp [cpus=]@var{n}[,cores=@var{cores}][,threads=@var{threads}][,dies=dies][,sockets=@var{sockets}][,maxcpus=@var{maxcpus}]
@findex -smp
Simulate an SMP system with @var{n} CPUs. On the PC target, up to 255
CPUs are supported. On Sparc32 target, Linux limits the number of usable CPUs
to 4.
-For the PC target, the number of @var{cores} per socket, the number
-of @var{threads} per cores and the total number of @var{sockets} can be
-specified. Missing values will be computed. If any on the three values is
-given, the total number of CPUs @var{n} can be omitted. @var{maxcpus}
-specifies the maximum number of hotpluggable CPUs.
+For the PC target, the number of @var{cores} per die, the number of @var{threads}
+per cores, the number of @var{dies} per packages and the total number of
+@var{sockets} can be specified. Missing values will be computed.
+If any on the three values is given, the total number of CPUs @var{n} can be omitted.
+@var{maxcpus} specifies the maximum number of hotpluggable CPUs.
ETEXI
DEF("numa", HAS_ARG, QEMU_OPTION_numa,
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PULL v6 29/42] qmp: Add deprecation information to query-machines
2019-07-05 22:14 [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 Eduardo Habkost
` (27 preceding siblings ...)
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 28/42] vl.c: Add -smp, dies=* command line support and update doc Eduardo Habkost
@ 2019-07-05 22:14 ` Eduardo Habkost
2019-07-08 13:29 ` Eric Blake
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 30/42] i386: Introduce SnowRidge CPU model Eduardo Habkost
` (14 subsequent siblings)
43 siblings, 1 reply; 49+ messages in thread
From: Eduardo Habkost @ 2019-07-05 22:14 UTC (permalink / raw)
To: Peter Maydell, Paolo Bonzini, qemu-devel, Marcel Apfelbaum,
Richard Henderson
Export machine type deprecation status through the query-machines
QMP command. With this, libvirt and management software will be
able to show this information to users and/or suggest changes to
VM configuration to avoid deprecated machines.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Message-Id: <20190608233447.27970-2-ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
qapi/machine.json | 7 ++++++-
hw/core/machine-qmp-cmds.c | 1 +
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/qapi/machine.json b/qapi/machine.json
index 78d34ef717..6db8a7e2ec 100644
--- a/qapi/machine.json
+++ b/qapi/machine.json
@@ -321,12 +321,17 @@
# @numa-mem-supported: true if '-numa node,mem' option is supported by
# the machine type and false otherwise (since 4.1)
#
+# @deprecated: if true, the machine type is deprecated and may be removed
+# in future versions of QEMU according to the QEMU deprecation
+# policy (since 4.1.0)
+#
# Since: 1.2.0
##
{ 'struct': 'MachineInfo',
'data': { 'name': 'str', '*alias': 'str',
'*is-default': 'bool', 'cpu-max': 'int',
- 'hotpluggable-cpus': 'bool', 'numa-mem-supported': 'bool'} }
+ 'hotpluggable-cpus': 'bool', 'numa-mem-supported': 'bool',
+ 'deprecated': 'bool' } }
##
# @query-machines:
diff --git a/hw/core/machine-qmp-cmds.c b/hw/core/machine-qmp-cmds.c
index 754ce77664..5bd95b8ab0 100644
--- a/hw/core/machine-qmp-cmds.c
+++ b/hw/core/machine-qmp-cmds.c
@@ -227,6 +227,7 @@ MachineInfoList *qmp_query_machines(Error **errp)
info->cpu_max = !mc->max_cpus ? 1 : mc->max_cpus;
info->hotpluggable_cpus = mc->has_hotpluggable_cpus;
info->numa_mem_supported = mc->numa_mem_supported;
+ info->deprecated = !!mc->deprecation_reason;
entry = g_malloc0(sizeof(*entry));
entry->value = info;
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PULL v6 30/42] i386: Introduce SnowRidge CPU model
2019-07-05 22:14 [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 Eduardo Habkost
` (28 preceding siblings ...)
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 29/42] qmp: Add deprecation information to query-machines Eduardo Habkost
@ 2019-07-05 22:14 ` Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 31/42] qmp: Add "alias-of" field to query-cpu-definitions Eduardo Habkost
` (13 subsequent siblings)
43 siblings, 0 replies; 49+ messages in thread
From: Eduardo Habkost @ 2019-07-05 22:14 UTC (permalink / raw)
To: Peter Maydell, Paolo Bonzini, qemu-devel, Marcel Apfelbaum,
Richard Henderson
Cc: Paul Lai
From: Paul Lai <paul.c.lai@intel.com>
SnowRidge CPU supports Accelerator Infrastrcture Architecture (MOVDIRI,
MOVDIR64B), CLDEMOTE and SPLIT_LOCK_DISABLE.
MOVDIRI, MOVDIR64B, and CLDEMOTE are found via CPUID.
The availability of SPLIT_LOCK_DISABLE is check via msr access
References can be found in either:
https://software.intel.com/en-us/articles/intel-sdm
https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-and-future-features-programming-reference
Signed-off-by: Paul Lai <paul.c.lai@intel.com>
Tested-by: Tao3 Xu <tao3.xu@intel.com>
Message-Id: <20190626162129.25345-1-paul.c.lai@intel.com>
[ehabkost: squashed SPLIT_LOCK_DETECT patch]
Message-Id: <20190626163232.25711-1-paul.c.lai@intel.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
target/i386/cpu.c | 71 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 71 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 296ef6c918..62043fee54 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2688,6 +2688,77 @@ static X86CPUDefinition builtin_x86_defs[] = {
.xlevel = 0x80000008,
.model_id = "Intel Xeon Processor (Icelake)",
},
+ {
+ .name = "SnowRidge-Server",
+ .level = 27,
+ .vendor = CPUID_VENDOR_INTEL,
+ .family = 6,
+ .model = 134,
+ .stepping = 1,
+ .features[FEAT_1_EDX] =
+ /* missing: CPUID_PN CPUID_IA64 */
+ /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
+ CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE |
+ CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE |
+ CPUID_CX8 | CPUID_APIC | CPUID_SEP |
+ CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
+ CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH |
+ CPUID_MMX |
+ CPUID_FXSR | CPUID_SSE | CPUID_SSE2,
+ .features[FEAT_1_ECX] =
+ CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
+ CPUID_EXT_VMX |
+ CPUID_EXT_SSSE3 |
+ CPUID_EXT_CX16 |
+ CPUID_EXT_SSE41 |
+ CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
+ CPUID_EXT_POPCNT |
+ CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE |
+ CPUID_EXT_RDRAND,
+ .features[FEAT_8000_0001_EDX] =
+ CPUID_EXT2_SYSCALL |
+ CPUID_EXT2_NX |
+ CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
+ CPUID_EXT2_LM,
+ .features[FEAT_8000_0001_ECX] =
+ CPUID_EXT3_LAHF_LM |
+ CPUID_EXT3_3DNOWPREFETCH,
+ .features[FEAT_7_0_EBX] =
+ CPUID_7_0_EBX_FSGSBASE |
+ CPUID_7_0_EBX_SMEP |
+ CPUID_7_0_EBX_ERMS |
+ CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */
+ CPUID_7_0_EBX_RDSEED |
+ CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
+ CPUID_7_0_EBX_CLWB |
+ CPUID_7_0_EBX_SHA_NI,
+ .features[FEAT_7_0_ECX] =
+ CPUID_7_0_ECX_UMIP |
+ /* missing bit 5 */
+ CPUID_7_0_ECX_GFNI |
+ CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE |
+ CPUID_7_0_ECX_MOVDIR64B,
+ .features[FEAT_7_0_EDX] =
+ CPUID_7_0_EDX_SPEC_CTRL |
+ CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD |
+ CPUID_7_0_EDX_CORE_CAPABILITY,
+ .features[FEAT_CORE_CAPABILITY] =
+ MSR_CORE_CAP_SPLIT_LOCK_DETECT,
+ /*
+ * Missing: XSAVES (not supported by some Linux versions,
+ * including v4.1 to v4.12).
+ * KVM doesn't yet expose any XSAVES state save component,
+ * and the only one defined in Skylake (processor tracing)
+ * probably will block migration anyway.
+ */
+ .features[FEAT_XSAVE] =
+ CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
+ CPUID_XSAVE_XGETBV1,
+ .features[FEAT_6_EAX] =
+ CPUID_6_EAX_ARAT,
+ .xlevel = 0x80000008,
+ .model_id = "Intel Atom Processor (SnowRidge)",
+ },
{
.name = "KnightsMill",
.level = 0xd,
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PULL v6 31/42] qmp: Add "alias-of" field to query-cpu-definitions
2019-07-05 22:14 [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 Eduardo Habkost
` (29 preceding siblings ...)
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 30/42] i386: Introduce SnowRidge CPU model Eduardo Habkost
@ 2019-07-05 22:14 ` Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 32/42] i386: Add x-force-features option for testing Eduardo Habkost
` (12 subsequent siblings)
43 siblings, 0 replies; 49+ messages in thread
From: Eduardo Habkost @ 2019-07-05 22:14 UTC (permalink / raw)
To: Peter Maydell, Paolo Bonzini, qemu-devel, Marcel Apfelbaum,
Richard Henderson
Management software will be expected to resolve CPU model name
aliases using the new field.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Message-Id: <20190628002844.24894-2-ehabkost@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
qapi/machine-target.json | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/qapi/machine-target.json b/qapi/machine-target.json
index 5d7480f6ab..55310a6aa2 100644
--- a/qapi/machine-target.json
+++ b/qapi/machine-target.json
@@ -279,6 +279,12 @@
# to introspect properties configurable using -cpu or -global.
# (since 2.9)
#
+# @alias-of: Name of CPU model this model is an alias for. The target of the
+# CPU model alias may change depending on the machine type.
+# Management software is supposed to translate CPU model aliases
+# in the VM configuration, because aliases may stop being
+# migration-safe in the future (since 4.1)
+#
# @unavailable-features is a list of QOM property names that
# represent CPU model attributes that prevent the CPU from running.
# If the QOM property is read-only, that means there's no known
@@ -302,7 +308,8 @@
'*migration-safe': 'bool',
'static': 'bool',
'*unavailable-features': [ 'str' ],
- 'typename': 'str' },
+ 'typename': 'str',
+ '*alias-of' : 'str' },
'if': 'defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_I386) || defined(TARGET_S390X) || defined(TARGET_MIPS)' }
##
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PULL v6 32/42] i386: Add x-force-features option for testing
2019-07-05 22:14 [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 Eduardo Habkost
` (30 preceding siblings ...)
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 31/42] qmp: Add "alias-of" field to query-cpu-definitions Eduardo Habkost
@ 2019-07-05 22:14 ` Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 33/42] i386: Get model-id from CPU object on "-cpu help" Eduardo Habkost
` (11 subsequent siblings)
43 siblings, 0 replies; 49+ messages in thread
From: Eduardo Habkost @ 2019-07-05 22:14 UTC (permalink / raw)
To: Peter Maydell, Paolo Bonzini, qemu-devel, Marcel Apfelbaum,
Richard Henderson
Add a new option that can be used to disable feature flag
filtering. This will allow CPU model compatibility test cases to
work without host hardware dependencies.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Message-Id: <20190628002844.24894-3-ehabkost@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
target/i386/cpu.h | 6 ++++++
target/i386/cpu.c | 8 ++++++--
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 0a96c78669..4727226a6a 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1417,6 +1417,12 @@ struct X86CPU {
bool check_cpuid;
bool enforce_cpuid;
+ /*
+ * Force features to be enabled even if the host doesn't support them.
+ * This is dangerous and should be done only for testing CPUID
+ * compatibility.
+ */
+ bool force_features;
bool expose_kvm;
bool expose_tcg;
bool migratable;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 62043fee54..8852b57c0b 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -5250,8 +5250,11 @@ static int x86_cpu_filter_features(X86CPU *cpu)
uint32_t host_feat =
x86_cpu_get_supported_feature_word(w, false);
uint32_t requested_features = env->features[w];
- env->features[w] &= host_feat;
- cpu->filtered_features[w] = requested_features & ~env->features[w];
+ uint32_t available_features = requested_features & host_feat;
+ if (!cpu->force_features) {
+ env->features[w] = available_features;
+ }
+ cpu->filtered_features[w] = requested_features & ~available_features;
if (cpu->filtered_features[w]) {
rv = 1;
}
@@ -5980,6 +5983,7 @@ static Property x86_cpu_properties[] = {
DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
+ DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false),
DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PULL v6 33/42] i386: Get model-id from CPU object on "-cpu help"
2019-07-05 22:14 [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 Eduardo Habkost
` (31 preceding siblings ...)
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 32/42] i386: Add x-force-features option for testing Eduardo Habkost
@ 2019-07-05 22:14 ` Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 34/42] i386: Register versioned CPU models Eduardo Habkost
` (10 subsequent siblings)
43 siblings, 0 replies; 49+ messages in thread
From: Eduardo Habkost @ 2019-07-05 22:14 UTC (permalink / raw)
To: Peter Maydell, Paolo Bonzini, qemu-devel, Marcel Apfelbaum,
Richard Henderson
When introducing versioned CPU models, the string at
X86CPUDefinition::model_id might not be the model-id we'll really
use. Instantiate a CPU object and check the model-id property on
"-cpu help"
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Message-Id: <20190628002844.24894-4-ehabkost@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
target/i386/cpu.c | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 8852b57c0b..a0e422adf3 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3837,18 +3837,28 @@ static GSList *get_sorted_cpu_model_list(void)
return list;
}
+static char *x86_cpu_class_get_model_id(X86CPUClass *xc)
+{
+ Object *obj = object_new(object_class_get_name(OBJECT_CLASS(xc)));
+ char *r = object_property_get_str(obj, "model-id", &error_abort);
+ object_unref(obj);
+ return r;
+}
+
static void x86_cpu_list_entry(gpointer data, gpointer user_data)
{
ObjectClass *oc = data;
X86CPUClass *cc = X86_CPU_CLASS(oc);
char *name = x86_cpu_class_get_model_name(cc);
- const char *desc = cc->model_description;
- if (!desc && cc->cpu_def) {
- desc = cc->cpu_def->model_id;
+ char *desc = g_strdup(cc->model_description);
+
+ if (!desc) {
+ desc = x86_cpu_class_get_model_id(cc);
}
qemu_printf("x86 %-20s %-48s\n", name, desc);
g_free(name);
+ g_free(desc);
}
/* list available CPU models and flags */
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PULL v6 34/42] i386: Register versioned CPU models
2019-07-05 22:14 [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 Eduardo Habkost
` (32 preceding siblings ...)
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 33/42] i386: Get model-id from CPU object on "-cpu help" Eduardo Habkost
@ 2019-07-05 22:14 ` Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 35/42] i386: Define -IBRS, -noTSX, -IBRS versions of " Eduardo Habkost
` (9 subsequent siblings)
43 siblings, 0 replies; 49+ messages in thread
From: Eduardo Habkost @ 2019-07-05 22:14 UTC (permalink / raw)
To: Peter Maydell, Paolo Bonzini, qemu-devel, Marcel Apfelbaum,
Richard Henderson
Add support for registration of multiple versions of CPU models.
The existing CPU models will be registered with a "-v1" suffix.
The -noTSX, -IBRS, and -IBPB CPU model variants will become
versions of the original models in a separate patch, so
make sure we register no versions for them.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Message-Id: <20190628002844.24894-5-ehabkost@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
target/i386/cpu-qom.h | 10 +-
target/i386/cpu.h | 10 +
target/i386/cpu.c | 223 +++++++++++++++++++--
tests/acceptance/x86_cpu_model_versions.py | 105 ++++++++++
4 files changed, 318 insertions(+), 30 deletions(-)
create mode 100644 tests/acceptance/x86_cpu_model_versions.py
diff --git a/target/i386/cpu-qom.h b/target/i386/cpu-qom.h
index 22f95eb3a4..1a52f02a4c 100644
--- a/target/i386/cpu-qom.h
+++ b/target/i386/cpu-qom.h
@@ -36,13 +36,7 @@
#define X86_CPU_GET_CLASS(obj) \
OBJECT_GET_CLASS(X86CPUClass, (obj), TYPE_X86_CPU)
-/**
- * X86CPUDefinition:
- *
- * CPU model definition data that was not converted to QOM per-subclass
- * property defaults yet.
- */
-typedef struct X86CPUDefinition X86CPUDefinition;
+typedef struct X86CPUModel X86CPUModel;
/**
* X86CPUClass:
@@ -64,7 +58,7 @@ typedef struct X86CPUClass {
/* CPU definition, automatically loaded by instance_init if not NULL.
* Should be eventually replaced by subclass-specific property defaults.
*/
- X86CPUDefinition *cpu_def;
+ X86CPUModel *model;
bool host_cpuid_required;
int ordering;
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 4727226a6a..12bc3cd4a8 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1929,6 +1929,16 @@ void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip,
*/
void x86_cpu_change_kvm_default(const char *prop, const char *value);
+/* Special values for X86CPUVersion: */
+
+/* Resolve to latest CPU version */
+#define CPU_VERSION_LATEST -1
+
+/* Don't resolve to any versioned CPU models, like old QEMU versions */
+#define CPU_VERSION_LEGACY 0
+
+typedef int X86CPUVersion;
+
/* Return name of 32-bit register, from a R_* constant */
const char *get_register_name_32(unsigned int reg);
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index a0e422adf3..87555a1c5a 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1433,7 +1433,17 @@ static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
}
-struct X86CPUDefinition {
+typedef struct PropValue {
+ const char *prop, *value;
+} PropValue;
+
+typedef struct X86CPUVersionDefinition {
+ X86CPUVersion version;
+ PropValue *props;
+} X86CPUVersionDefinition;
+
+/* Base definition for a CPU model */
+typedef struct X86CPUDefinition {
const char *name;
uint32_t level;
uint32_t xlevel;
@@ -1445,8 +1455,41 @@ struct X86CPUDefinition {
FeatureWordArray features;
const char *model_id;
CPUCaches *cache_info;
+ /*
+ * Definitions for alternative versions of CPU model.
+ * List is terminated by item with version == 0.
+ * If NULL, version 1 will be registered automatically.
+ */
+ const X86CPUVersionDefinition *versions;
+} X86CPUDefinition;
+
+/* Reference to a specific CPU model version */
+struct X86CPUModel {
+ /* Base CPU definition */
+ X86CPUDefinition *cpudef;
+ /* CPU model version */
+ X86CPUVersion version;
};
+/* Get full model name for CPU version */
+static char *x86_cpu_versioned_model_name(X86CPUDefinition *cpudef,
+ X86CPUVersion version)
+{
+ assert(version > 0);
+ return g_strdup_printf("%s-v%d", cpudef->name, (int)version);
+}
+
+static const X86CPUVersionDefinition *x86_cpu_def_get_versions(X86CPUDefinition *def)
+{
+ /* When X86CPUDefinition::versions is NULL, we register only v1 */
+ static const X86CPUVersionDefinition default_version_list[] = {
+ { 1 },
+ { /* end of list */ }
+ };
+
+ return def->versions ?: default_version_list;
+}
+
static CPUCaches epyc_cache_info = {
.l1d_cache = &(CPUCacheInfo) {
.type = DATA_CACHE,
@@ -1833,6 +1876,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_EXT3_LAHF_LM,
.xlevel = 0x80000008,
.model_id = "Intel Core i7 9xx (Nehalem Core i7, IBRS update)",
+ /*
+ * This CPU model will eventually be replaced by an alias,
+ * don't register any versions for it.
+ */
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
},
{
.name = "Westmere",
@@ -1887,6 +1935,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Westmere E56xx/L56xx/X56xx (IBRS update)",
+ /*
+ * This CPU model will eventually be replaced by an alias,
+ * don't register any versions for it.
+ */
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
},
{
.name = "SandyBridge",
@@ -1951,6 +2004,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Xeon E312xx (Sandy Bridge, IBRS update)",
+ /*
+ * This CPU model will eventually be replaced by an alias,
+ * don't register any versions for it.
+ */
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
},
{
.name = "IvyBridge",
@@ -2021,6 +2079,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)",
+ /*
+ * This CPU model will eventually be replaced by an alias,
+ * don't register any versions for it.
+ */
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
},
{
.name = "Haswell-noTSX",
@@ -2057,6 +2120,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Core Processor (Haswell, no TSX)",
+ /*
+ * This CPU model will eventually be replaced by an alias,
+ * don't register any versions for it.
+ */
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
},
{
.name = "Haswell-noTSX-IBRS",
@@ -2095,6 +2163,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Core Processor (Haswell, no TSX, IBRS)",
+ /*
+ * This CPU model will eventually be replaced by an alias,
+ * don't register any versions for it.
+ */
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
},
{
.name = "Haswell",
@@ -2171,6 +2244,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Core Processor (Haswell, IBRS)",
+ /*
+ * This CPU model will eventually be replaced by an alias,
+ * don't register any versions for it.
+ */
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
},
{
.name = "Broadwell-noTSX",
@@ -2209,6 +2287,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Core Processor (Broadwell, no TSX)",
+ /*
+ * This CPU model will eventually be replaced by an alias,
+ * don't register any versions for it.
+ */
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
},
{
.name = "Broadwell-noTSX-IBRS",
@@ -2249,6 +2332,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Core Processor (Broadwell, no TSX, IBRS)",
+ /*
+ * This CPU model will eventually be replaced by an alias,
+ * don't register any versions for it.
+ */
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
},
{
.name = "Broadwell",
@@ -2327,6 +2415,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Core Processor (Broadwell, IBRS)",
+ /*
+ * This CPU model will eventually be replaced by an alias,
+ * don't register any versions for it.
+ */
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
},
{
.name = "Skylake-Client",
@@ -2419,6 +2512,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Core Processor (Skylake, IBRS)",
+ /*
+ * This CPU model will eventually be replaced by an alias,
+ * don't register any versions for it.
+ */
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
},
{
.name = "Skylake-Server",
@@ -2521,6 +2619,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Xeon Processor (Skylake, IBRS)",
+ /*
+ * This CPU model will eventually be replaced by an alias,
+ * don't register any versions for it.
+ */
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
},
{
.name = "Cascadelake-Server",
@@ -3029,6 +3132,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
.xlevel = 0x8000001E,
.model_id = "AMD EPYC Processor (with IBPB)",
.cache_info = &epyc_cache_info,
+ /*
+ * This CPU model will eventually be replaced by an alias,
+ * don't register any versions for it.
+ */
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
},
{
.name = "Dhyana",
@@ -3082,10 +3190,6 @@ static X86CPUDefinition builtin_x86_defs[] = {
},
};
-typedef struct PropValue {
- const char *prop, *value;
-} PropValue;
-
/* KVM-specific features that are automatically added/removed
* from all CPU models when KVM is enabled.
*/
@@ -3111,6 +3215,28 @@ static PropValue tcg_default_props[] = {
};
+static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model)
+{
+ int v = 0;
+ const X86CPUVersionDefinition *vdef =
+ x86_cpu_def_get_versions(model->cpudef);
+ while (vdef->version) {
+ v = vdef->version;
+ vdef++;
+ }
+ return v;
+}
+
+/* Return the actual version being used for a specific CPU model */
+static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model)
+{
+ X86CPUVersion v = model->version;
+ if (v == CPU_VERSION_LATEST) {
+ return x86_cpu_model_last_version(model);
+ }
+ return v;
+}
+
void x86_cpu_change_kvm_default(const char *prop, const char *value)
{
PropValue *pv;
@@ -3188,8 +3314,6 @@ static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
dc->props = max_x86_cpu_properties;
}
-static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp);
-
static void max_x86_cpu_initfn(Object *obj)
{
X86CPU *cpu = X86_CPU(obj);
@@ -3980,10 +4104,40 @@ static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
}
}
+/* Apply properties for the CPU model version specified in model */
+static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model)
+{
+ const X86CPUVersionDefinition *vdef;
+ X86CPUVersion version = x86_cpu_model_resolve_version(model);
+
+ if (version == CPU_VERSION_LEGACY) {
+ return;
+ }
+
+ for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) {
+ PropValue *p;
+
+ for (p = vdef->props; p && p->prop; p++) {
+ object_property_parse(OBJECT(cpu), p->value, p->prop,
+ &error_abort);
+ }
+
+ if (vdef->version == version) {
+ break;
+ }
+ }
+
+ /*
+ * If we reached the end of the list, version number was invalid
+ */
+ assert(vdef->version == version);
+}
+
/* Load data from X86CPUDefinition into a X86CPU object
*/
-static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
+static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model, Error **errp)
{
+ X86CPUDefinition *def = model->cpudef;
CPUX86State *env = &cpu->env;
const char *vendor;
char host_vendor[CPUID_VENDOR_SZ + 1];
@@ -4040,11 +4194,12 @@ static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
+ x86_cpu_apply_version_props(cpu, model);
}
#ifndef CONFIG_USER_ONLY
/* Return a QDict containing keys for all properties that can be included
- * in static expansion of CPU models. All properties set by x86_cpu_load_def()
+ * in static expansion of CPU models. All properties set by x86_cpu_load_model()
* must be included in the dictionary.
*/
static QDict *x86_cpu_static_props(void)
@@ -4258,23 +4413,33 @@ static gchar *x86_gdb_arch_name(CPUState *cs)
static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
{
- X86CPUDefinition *cpudef = data;
+ X86CPUModel *model = data;
X86CPUClass *xcc = X86_CPU_CLASS(oc);
- xcc->cpu_def = cpudef;
+ xcc->model = model;
xcc->migration_safe = true;
}
-static void x86_register_cpudef_type(X86CPUDefinition *def)
+static void x86_register_cpu_model_type(const char *name, X86CPUModel *model)
{
- char *typename = x86_cpu_type_name(def->name);
+ char *typename = x86_cpu_type_name(name);
TypeInfo ti = {
.name = typename,
.parent = TYPE_X86_CPU,
.class_init = x86_cpu_cpudef_class_init,
- .class_data = def,
+ .class_data = model,
};
+ type_register(&ti);
+ g_free(typename);
+}
+
+static void x86_register_cpudef_types(X86CPUDefinition *def)
+{
+ X86CPUModel *m;
+ const X86CPUVersionDefinition *vdef;
+ char *name;
+
/* AMD aliases are handled at runtime based on CPUID vendor, so
* they shouldn't be set on the CPU model table.
*/
@@ -4282,9 +4447,23 @@ static void x86_register_cpudef_type(X86CPUDefinition *def)
/* catch mistakes instead of silently truncating model_id when too long */
assert(def->model_id && strlen(def->model_id) <= 48);
+ /* Unversioned model: */
+ m = g_new0(X86CPUModel, 1);
+ m->cpudef = def;
+ m->version = CPU_VERSION_LEGACY;
+ x86_register_cpu_model_type(def->name, m);
+
+ /* Versioned models: */
+
+ for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) {
+ X86CPUModel *m = g_new0(X86CPUModel, 1);
+ m->cpudef = def;
+ m->version = vdef->version;
+ name = x86_cpu_versioned_model_name(def, vdef->version);
+ x86_register_cpu_model_type(name, m);
+ g_free(name);
+ }
- type_register(&ti);
- g_free(typename);
}
#if !defined(CONFIG_USER_ONLY)
@@ -5110,7 +5289,7 @@ static void x86_cpu_enable_xsave_components(X86CPU *cpu)
* involved in setting up CPUID data are:
*
* 1) Loading CPU model definition (X86CPUDefinition). This is
- * implemented by x86_cpu_load_def() and should be completely
+ * implemented by x86_cpu_load_model() and should be completely
* transparent, as it is done automatically by instance_init.
* No code should need to look at X86CPUDefinition structs
* outside instance_init.
@@ -5432,7 +5611,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
/* Cache information initialization */
if (!cpu->legacy_cache) {
- if (!xcc->cpu_def || !xcc->cpu_def->cache_info) {
+ if (!xcc->model || !xcc->model->cpudef->cache_info) {
char *name = x86_cpu_class_get_model_name(xcc);
error_setg(errp,
"CPU model '%s' doesn't support legacy-cache=off", name);
@@ -5440,7 +5619,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
return;
}
env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd =
- *xcc->cpu_def->cache_info;
+ *xcc->model->cpudef->cache_info;
} else {
/* Build legacy cache information */
env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache;
@@ -5799,8 +5978,8 @@ static void x86_cpu_initfn(Object *obj)
object_property_add_alias(obj, "sse4_1", obj, "sse4.1", &error_abort);
object_property_add_alias(obj, "sse4_2", obj, "sse4.2", &error_abort);
- if (xcc->cpu_def) {
- x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
+ if (xcc->model) {
+ x86_cpu_load_model(cpu, xcc->model, &error_abort);
}
}
@@ -6139,7 +6318,7 @@ static void x86_cpu_register_types(void)
type_register_static(&x86_cpu_type_info);
for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
- x86_register_cpudef_type(&builtin_x86_defs[i]);
+ x86_register_cpudef_types(&builtin_x86_defs[i]);
}
type_register_static(&max_x86_cpu_type_info);
type_register_static(&x86_base_cpu_type_info);
diff --git a/tests/acceptance/x86_cpu_model_versions.py b/tests/acceptance/x86_cpu_model_versions.py
new file mode 100644
index 0000000000..b85d6f8604
--- /dev/null
+++ b/tests/acceptance/x86_cpu_model_versions.py
@@ -0,0 +1,105 @@
+#!/usr/bin/env python
+#
+# Basic validation of x86 versioned CPU models and CPU model aliases
+#
+# Copyright (c) 2019 Red Hat Inc
+#
+# Author:
+# Eduardo Habkost <ehabkost@redhat.com>
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2 of the License, or (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, see <http://www.gnu.org/licenses/>.
+#
+
+
+import avocado_qemu
+import re
+
+class X86CPUModelAliases(avocado_qemu.Test):
+ """
+ Validation of PC CPU model versions and CPU model aliases
+
+ :avocado: tags=arch:x86_64
+ """
+ def validate_aliases(self, cpus):
+ for c in cpus.values():
+ if 'alias-of' in c:
+ # all aliases must point to a valid CPU model name:
+ self.assertIn(c['alias-of'], cpus,
+ '%s.alias-of (%s) is not a valid CPU model name' % (c['name'], c['alias-of']))
+ # aliases must not point to aliases
+ self.assertNotIn('alias-of', cpus[c['alias-of']],
+ '%s.alias-of (%s) points to another alias' % (c['name'], c['alias-of']))
+
+ # aliases must not be static
+ self.assertFalse(c['static'])
+
+ def validate_variant_aliases(self, cpus):
+ # -noTSX, -IBRS and -IBPB variants of CPU models are special:
+ # they shouldn't have their own versions:
+ self.assertNotIn("Haswell-noTSX-v1", cpus,
+ "Haswell-noTSX shouldn't be versioned")
+ self.assertNotIn("Broadwell-noTSX-v1", cpus,
+ "Broadwell-noTSX shouldn't be versioned")
+ self.assertNotIn("Nehalem-IBRS-v1", cpus,
+ "Nehalem-IBRS shouldn't be versioned")
+ self.assertNotIn("Westmere-IBRS-v1", cpus,
+ "Westmere-IBRS shouldn't be versioned")
+ self.assertNotIn("SandyBridge-IBRS-v1", cpus,
+ "SandyBridge-IBRS shouldn't be versioned")
+ self.assertNotIn("IvyBridge-IBRS-v1", cpus,
+ "IvyBridge-IBRS shouldn't be versioned")
+ self.assertNotIn("Haswell-noTSX-IBRS-v1", cpus,
+ "Haswell-noTSX-IBRS shouldn't be versioned")
+ self.assertNotIn("Haswell-IBRS-v1", cpus,
+ "Haswell-IBRS shouldn't be versioned")
+ self.assertNotIn("Broadwell-noTSX-IBRS-v1", cpus,
+ "Broadwell-noTSX-IBRS shouldn't be versioned")
+ self.assertNotIn("Broadwell-IBRS-v1", cpus,
+ "Broadwell-IBRS shouldn't be versioned")
+ self.assertNotIn("Skylake-Client-IBRS-v1", cpus,
+ "Skylake-Client-IBRS shouldn't be versioned")
+ self.assertNotIn("Skylake-Server-IBRS-v1", cpus,
+ "Skylake-Server-IBRS shouldn't be versioned")
+ self.assertNotIn("EPYC-IBPB-v1", cpus,
+ "EPYC-IBPB shouldn't be versioned")
+
+ def test_4_0_alias_compatibility(self):
+ """Check if pc-*-4.0 unversioned CPU model won't be reported as aliases"""
+ # pc-*-4.0 won't expose non-versioned CPU models as aliases
+ # We do this to help management software to keep compatibility
+ # with older QEMU versions that didn't have the versioned CPU model
+ self.vm.add_args('-S')
+ self.vm.set_machine('pc-i440fx-4.0')
+ self.vm.launch()
+ cpus = dict((m['name'], m) for m in self.vm.command('query-cpu-definitions'))
+
+ self.assertFalse(cpus['Cascadelake-Server']['static'],
+ 'unversioned Cascadelake-Server CPU model must not be static')
+ self.assertNotIn('alias-of', cpus['Cascadelake-Server'],
+ 'Cascadelake-Server must not be an alias')
+ self.assertNotIn('alias-of', cpus['Cascadelake-Server-v1'],
+ 'Cascadelake-Server-v1 must not be an alias')
+
+ self.assertFalse(cpus['qemu64']['static'],
+ 'unversioned qemu64 CPU model must not be static')
+ self.assertNotIn('alias-of', cpus['qemu64'],
+ 'qemu64 must not be an alias')
+ self.assertNotIn('alias-of', cpus['qemu64-v1'],
+ 'qemu64-v1 must not be an alias')
+
+ self.validate_variant_aliases(cpus)
+
+ # On pc-*-4.0, no CPU model should be reported as an alias:
+ for name,c in cpus.items():
+ self.assertNotIn('alias-of', c, "%s shouldn't be an alias" % (name))
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PULL v6 35/42] i386: Define -IBRS, -noTSX, -IBRS versions of CPU models
2019-07-05 22:14 [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 Eduardo Habkost
` (33 preceding siblings ...)
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 34/42] i386: Register versioned CPU models Eduardo Habkost
@ 2019-07-05 22:14 ` Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 36/42] i386: Replace -noTSX, -IBRS, -IBPB CPU models with aliases Eduardo Habkost
` (8 subsequent siblings)
43 siblings, 0 replies; 49+ messages in thread
From: Eduardo Habkost @ 2019-07-05 22:14 UTC (permalink / raw)
To: Peter Maydell, Paolo Bonzini, qemu-devel, Marcel Apfelbaum,
Richard Henderson
Add versions of CPU models that are equivalent to their -IBRS,
-noTSX and -IBRS variants.
The separate variants will eventually be removed and become
aliases for these CPU versions.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Message-Id: <20190628002844.24894-6-ehabkost@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
target/i386/cpu.c | 186 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 186 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 87555a1c5a..51beebdb27 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1851,6 +1851,20 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_EXT3_LAHF_LM,
.xlevel = 0x80000008,
.model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
+ .versions = (X86CPUVersionDefinition[]) {
+ { .version = 1 },
+ {
+ .version = 2,
+ /* Equivalent to Nehalem-IBRS */
+ .props = (PropValue[]) {
+ { "spec-ctrl", "on" },
+ { "model-id",
+ "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" },
+ { /* end of list */ }
+ }
+ },
+ { /* end of list */ }
+ }
},
{
.name = "Nehalem-IBRS",
@@ -1907,6 +1921,20 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
+ .versions = (X86CPUVersionDefinition[]) {
+ { .version = 1 },
+ {
+ .version = 2,
+ /* Equivalent to Westmere-IBRS */
+ .props = (PropValue[]) {
+ { "spec-ctrl", "on" },
+ { "model-id",
+ "Westmere E56xx/L56xx/X56xx (IBRS update)" },
+ { /* end of list */ }
+ }
+ },
+ { /* end of list */ }
+ }
},
{
.name = "Westmere-IBRS",
@@ -1971,6 +1999,20 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Xeon E312xx (Sandy Bridge)",
+ .versions = (X86CPUVersionDefinition[]) {
+ { .version = 1 },
+ {
+ .version = 2,
+ /* Equivalent to SandyBridge-IBRS */
+ .props = (PropValue[]) {
+ { "spec-ctrl", "on" },
+ { "model-id",
+ "Intel Xeon E312xx (Sandy Bridge, IBRS update)" },
+ { /* end of list */ }
+ }
+ },
+ { /* end of list */ }
+ }
},
{
.name = "SandyBridge-IBRS",
@@ -2043,6 +2085,20 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
+ .versions = (X86CPUVersionDefinition[]) {
+ { .version = 1 },
+ {
+ .version = 2,
+ /* Equivalent to IvyBridge-IBRS */
+ .props = (PropValue[]) {
+ { "spec-ctrl", "on" },
+ { "model-id",
+ "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" },
+ { /* end of list */ }
+ }
+ },
+ { /* end of list */ }
+ }
},
{
.name = "IvyBridge-IBRS",
@@ -2205,6 +2261,52 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Core Processor (Haswell)",
+ .versions = (X86CPUVersionDefinition[]) {
+ { .version = 1 },
+ {
+ .version = 2,
+ /* Equivalent to Haswell-noTSX */
+ .props = (PropValue[]) {
+ { "hle", "off" },
+ { "rtm", "off" },
+ { "stepping", "1" },
+ { "model-id", "Intel Core Processor (Haswell, no TSX)", },
+ { /* end of list */ }
+ },
+ },
+ {
+ .version = 3,
+ /* Equivalent to Haswell-IBRS */
+ .props = (PropValue[]) {
+ /* Restore TSX features removed by -v2 above */
+ { "hle", "on" },
+ { "rtm", "on" },
+ /*
+ * Haswell and Haswell-IBRS had stepping=4 in
+ * QEMU 4.0 and older
+ */
+ { "stepping", "4" },
+ { "spec-ctrl", "on" },
+ { "model-id",
+ "Intel Core Processor (Haswell, IBRS)" },
+ { /* end of list */ }
+ }
+ },
+ {
+ .version = 4,
+ /* Equivalent to Haswell-noTSX-IBRS */
+ .props = (PropValue[]) {
+ { "hle", "off" },
+ { "rtm", "off" },
+ /* spec-ctrl was already enabled by -v3 above */
+ { "stepping", "1" },
+ { "model-id",
+ "Intel Core Processor (Haswell, no TSX, IBRS)" },
+ { /* end of list */ }
+ }
+ },
+ { /* end of list */ }
+ }
},
{
.name = "Haswell-IBRS",
@@ -2375,6 +2477,45 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Core Processor (Broadwell)",
+ .versions = (X86CPUVersionDefinition[]) {
+ { .version = 1 },
+ {
+ .version = 2,
+ /* Equivalent to Broadwell-noTSX */
+ .props = (PropValue[]) {
+ { "hle", "off" },
+ { "rtm", "off" },
+ { "model-id", "Intel Core Processor (Broadwell, no TSX)", },
+ { /* end of list */ }
+ },
+ },
+ {
+ .version = 3,
+ /* Equivalent to Broadwell-IBRS */
+ .props = (PropValue[]) {
+ /* Restore TSX features removed by -v2 above */
+ { "hle", "on" },
+ { "rtm", "on" },
+ { "spec-ctrl", "on" },
+ { "model-id",
+ "Intel Core Processor (Broadwell, IBRS)" },
+ { /* end of list */ }
+ }
+ },
+ {
+ .version = 4,
+ /* Equivalent to Broadwell-noTSX-IBRS */
+ .props = (PropValue[]) {
+ { "hle", "off" },
+ { "rtm", "off" },
+ /* spec-ctrl was already enabled by -v3 above */
+ { "model-id",
+ "Intel Core Processor (Broadwell, no TSX, IBRS)" },
+ { /* end of list */ }
+ }
+ },
+ { /* end of list */ }
+ }
},
{
.name = "Broadwell-IBRS",
@@ -2465,6 +2606,20 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Core Processor (Skylake)",
+ .versions = (X86CPUVersionDefinition[]) {
+ { .version = 1 },
+ {
+ .version = 2,
+ /* Equivalent to Skylake-Client-IBRS */
+ .props = (PropValue[]) {
+ { "spec-ctrl", "on" },
+ { "model-id",
+ "Intel Core Processor (Skylake, IBRS)" },
+ { /* end of list */ }
+ }
+ },
+ { /* end of list */ }
+ }
},
{
.name = "Skylake-Client-IBRS",
@@ -2567,6 +2722,23 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Xeon Processor (Skylake)",
+ .versions = (X86CPUVersionDefinition[]) {
+ { .version = 1 },
+ {
+ .version = 2,
+ /* Equivalent to Skylake-Server-IBRS */
+ .props = (PropValue[]) {
+ /* clflushopt was not added to Skylake-Server-IBRS */
+ /* TODO: add -v3 including clflushopt */
+ { "clflushopt", "off" },
+ { "spec-ctrl", "on" },
+ { "model-id",
+ "Intel Xeon Processor (Skylake, IBRS)" },
+ { /* end of list */ }
+ }
+ },
+ { /* end of list */ }
+ }
},
{
.name = "Skylake-Server-IBRS",
@@ -3082,6 +3254,20 @@ static X86CPUDefinition builtin_x86_defs[] = {
.xlevel = 0x8000001E,
.model_id = "AMD EPYC Processor",
.cache_info = &epyc_cache_info,
+ .versions = (X86CPUVersionDefinition[]) {
+ { .version = 1 },
+ {
+ .version = 2,
+ /* Equivalent to EPYC-IBPB */
+ .props = (PropValue[]) {
+ { "ibpb", "on" },
+ { "model-id",
+ "AMD EPYC Processor (with IBPB)" },
+ { /* end of list */ }
+ }
+ },
+ { /* end of list */ }
+ }
},
{
.name = "EPYC-IBPB",
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PULL v6 36/42] i386: Replace -noTSX, -IBRS, -IBPB CPU models with aliases
2019-07-05 22:14 [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 Eduardo Habkost
` (34 preceding siblings ...)
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 35/42] i386: Define -IBRS, -noTSX, -IBRS versions of " Eduardo Habkost
@ 2019-07-05 22:14 ` Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 37/42] i386: Make unversioned CPU models be aliases Eduardo Habkost
` (7 subsequent siblings)
43 siblings, 0 replies; 49+ messages in thread
From: Eduardo Habkost @ 2019-07-05 22:14 UTC (permalink / raw)
To: Peter Maydell, Paolo Bonzini, qemu-devel, Marcel Apfelbaum,
Richard Henderson
The old CPU models will be just aliases for specific versions of
the original CPU models.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Message-Id: <20190628002844.24894-7-ehabkost@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
target/i386/cpu.c | 601 ++--------------------------------------------
1 file changed, 21 insertions(+), 580 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 51beebdb27..f41917649d 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1439,6 +1439,7 @@ typedef struct PropValue {
typedef struct X86CPUVersionDefinition {
X86CPUVersion version;
+ const char *alias;
PropValue *props;
} X86CPUVersionDefinition;
@@ -1855,7 +1856,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ .version = 1 },
{
.version = 2,
- /* Equivalent to Nehalem-IBRS */
+ .alias = "Nehalem-IBRS",
.props = (PropValue[]) {
{ "spec-ctrl", "on" },
{ "model-id",
@@ -1866,36 +1867,6 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ /* end of list */ }
}
},
- {
- .name = "Nehalem-IBRS",
- .level = 11,
- .vendor = CPUID_VENDOR_INTEL,
- .family = 6,
- .model = 26,
- .stepping = 3,
- .features[FEAT_1_EDX] =
- CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
- CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
- CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
- CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
- CPUID_DE | CPUID_FP87,
- .features[FEAT_1_ECX] =
- CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
- CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
- .features[FEAT_7_0_EDX] =
- CPUID_7_0_EDX_SPEC_CTRL,
- .features[FEAT_8000_0001_EDX] =
- CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
- .features[FEAT_8000_0001_ECX] =
- CPUID_EXT3_LAHF_LM,
- .xlevel = 0x80000008,
- .model_id = "Intel Core i7 9xx (Nehalem Core i7, IBRS update)",
- /*
- * This CPU model will eventually be replaced by an alias,
- * don't register any versions for it.
- */
- .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
- },
{
.name = "Westmere",
.level = 11,
@@ -1925,7 +1896,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ .version = 1 },
{
.version = 2,
- /* Equivalent to Westmere-IBRS */
+ .alias = "Westmere-IBRS",
.props = (PropValue[]) {
{ "spec-ctrl", "on" },
{ "model-id",
@@ -1936,39 +1907,6 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ /* end of list */ }
}
},
- {
- .name = "Westmere-IBRS",
- .level = 11,
- .vendor = CPUID_VENDOR_INTEL,
- .family = 6,
- .model = 44,
- .stepping = 1,
- .features[FEAT_1_EDX] =
- CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
- CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
- CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
- CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
- CPUID_DE | CPUID_FP87,
- .features[FEAT_1_ECX] =
- CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
- CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
- CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
- .features[FEAT_8000_0001_EDX] =
- CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
- .features[FEAT_8000_0001_ECX] =
- CPUID_EXT3_LAHF_LM,
- .features[FEAT_7_0_EDX] =
- CPUID_7_0_EDX_SPEC_CTRL,
- .features[FEAT_6_EAX] =
- CPUID_6_EAX_ARAT,
- .xlevel = 0x80000008,
- .model_id = "Westmere E56xx/L56xx/X56xx (IBRS update)",
- /*
- * This CPU model will eventually be replaced by an alias,
- * don't register any versions for it.
- */
- .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
- },
{
.name = "SandyBridge",
.level = 0xd,
@@ -2003,7 +1941,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ .version = 1 },
{
.version = 2,
- /* Equivalent to SandyBridge-IBRS */
+ .alias = "SandyBridge-IBRS",
.props = (PropValue[]) {
{ "spec-ctrl", "on" },
{ "model-id",
@@ -2014,44 +1952,6 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ /* end of list */ }
}
},
- {
- .name = "SandyBridge-IBRS",
- .level = 0xd,
- .vendor = CPUID_VENDOR_INTEL,
- .family = 6,
- .model = 42,
- .stepping = 1,
- .features[FEAT_1_EDX] =
- CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
- CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
- CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
- CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
- CPUID_DE | CPUID_FP87,
- .features[FEAT_1_ECX] =
- CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
- CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
- CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
- CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
- CPUID_EXT_SSE3,
- .features[FEAT_8000_0001_EDX] =
- CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
- CPUID_EXT2_SYSCALL,
- .features[FEAT_8000_0001_ECX] =
- CPUID_EXT3_LAHF_LM,
- .features[FEAT_7_0_EDX] =
- CPUID_7_0_EDX_SPEC_CTRL,
- .features[FEAT_XSAVE] =
- CPUID_XSAVE_XSAVEOPT,
- .features[FEAT_6_EAX] =
- CPUID_6_EAX_ARAT,
- .xlevel = 0x80000008,
- .model_id = "Intel Xeon E312xx (Sandy Bridge, IBRS update)",
- /*
- * This CPU model will eventually be replaced by an alias,
- * don't register any versions for it.
- */
- .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
- },
{
.name = "IvyBridge",
.level = 0xd,
@@ -2089,7 +1989,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ .version = 1 },
{
.version = 2,
- /* Equivalent to IvyBridge-IBRS */
+ .alias = "IvyBridge-IBRS",
.props = (PropValue[]) {
{ "spec-ctrl", "on" },
{ "model-id",
@@ -2100,131 +2000,6 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ /* end of list */ }
}
},
- {
- .name = "IvyBridge-IBRS",
- .level = 0xd,
- .vendor = CPUID_VENDOR_INTEL,
- .family = 6,
- .model = 58,
- .stepping = 9,
- .features[FEAT_1_EDX] =
- CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
- CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
- CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
- CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
- CPUID_DE | CPUID_FP87,
- .features[FEAT_1_ECX] =
- CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
- CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
- CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
- CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
- CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
- .features[FEAT_7_0_EBX] =
- CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
- CPUID_7_0_EBX_ERMS,
- .features[FEAT_8000_0001_EDX] =
- CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
- CPUID_EXT2_SYSCALL,
- .features[FEAT_8000_0001_ECX] =
- CPUID_EXT3_LAHF_LM,
- .features[FEAT_7_0_EDX] =
- CPUID_7_0_EDX_SPEC_CTRL,
- .features[FEAT_XSAVE] =
- CPUID_XSAVE_XSAVEOPT,
- .features[FEAT_6_EAX] =
- CPUID_6_EAX_ARAT,
- .xlevel = 0x80000008,
- .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)",
- /*
- * This CPU model will eventually be replaced by an alias,
- * don't register any versions for it.
- */
- .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
- },
- {
- .name = "Haswell-noTSX",
- .level = 0xd,
- .vendor = CPUID_VENDOR_INTEL,
- .family = 6,
- .model = 60,
- .stepping = 1,
- .features[FEAT_1_EDX] =
- CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
- CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
- CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
- CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
- CPUID_DE | CPUID_FP87,
- .features[FEAT_1_ECX] =
- CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
- CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
- CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
- CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
- CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
- CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
- .features[FEAT_8000_0001_EDX] =
- CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
- CPUID_EXT2_SYSCALL,
- .features[FEAT_8000_0001_ECX] =
- CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
- .features[FEAT_7_0_EBX] =
- CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
- CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
- CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
- .features[FEAT_XSAVE] =
- CPUID_XSAVE_XSAVEOPT,
- .features[FEAT_6_EAX] =
- CPUID_6_EAX_ARAT,
- .xlevel = 0x80000008,
- .model_id = "Intel Core Processor (Haswell, no TSX)",
- /*
- * This CPU model will eventually be replaced by an alias,
- * don't register any versions for it.
- */
- .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
- },
- {
- .name = "Haswell-noTSX-IBRS",
- .level = 0xd,
- .vendor = CPUID_VENDOR_INTEL,
- .family = 6,
- .model = 60,
- .stepping = 1,
- .features[FEAT_1_EDX] =
- CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
- CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
- CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
- CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
- CPUID_DE | CPUID_FP87,
- .features[FEAT_1_ECX] =
- CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
- CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
- CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
- CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
- CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
- CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
- .features[FEAT_8000_0001_EDX] =
- CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
- CPUID_EXT2_SYSCALL,
- .features[FEAT_8000_0001_ECX] =
- CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
- .features[FEAT_7_0_EDX] =
- CPUID_7_0_EDX_SPEC_CTRL,
- .features[FEAT_7_0_EBX] =
- CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
- CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
- CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
- .features[FEAT_XSAVE] =
- CPUID_XSAVE_XSAVEOPT,
- .features[FEAT_6_EAX] =
- CPUID_6_EAX_ARAT,
- .xlevel = 0x80000008,
- .model_id = "Intel Core Processor (Haswell, no TSX, IBRS)",
- /*
- * This CPU model will eventually be replaced by an alias,
- * don't register any versions for it.
- */
- .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
- },
{
.name = "Haswell",
.level = 0xd,
@@ -2265,7 +2040,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ .version = 1 },
{
.version = 2,
- /* Equivalent to Haswell-noTSX */
+ .alias = "Haswell-noTSX",
.props = (PropValue[]) {
{ "hle", "off" },
{ "rtm", "off" },
@@ -2276,7 +2051,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
},
{
.version = 3,
- /* Equivalent to Haswell-IBRS */
+ .alias = "Haswell-IBRS",
.props = (PropValue[]) {
/* Restore TSX features removed by -v2 above */
{ "hle", "on" },
@@ -2294,7 +2069,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
},
{
.version = 4,
- /* Equivalent to Haswell-noTSX-IBRS */
+ .alias = "Haswell-noTSX-IBRS",
.props = (PropValue[]) {
{ "hle", "off" },
{ "rtm", "off" },
@@ -2308,138 +2083,6 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ /* end of list */ }
}
},
- {
- .name = "Haswell-IBRS",
- .level = 0xd,
- .vendor = CPUID_VENDOR_INTEL,
- .family = 6,
- .model = 60,
- .stepping = 4,
- .features[FEAT_1_EDX] =
- CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
- CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
- CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
- CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
- CPUID_DE | CPUID_FP87,
- .features[FEAT_1_ECX] =
- CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
- CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
- CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
- CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
- CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
- CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
- .features[FEAT_8000_0001_EDX] =
- CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
- CPUID_EXT2_SYSCALL,
- .features[FEAT_8000_0001_ECX] =
- CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
- .features[FEAT_7_0_EDX] =
- CPUID_7_0_EDX_SPEC_CTRL,
- .features[FEAT_7_0_EBX] =
- CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
- CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
- CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
- CPUID_7_0_EBX_RTM,
- .features[FEAT_XSAVE] =
- CPUID_XSAVE_XSAVEOPT,
- .features[FEAT_6_EAX] =
- CPUID_6_EAX_ARAT,
- .xlevel = 0x80000008,
- .model_id = "Intel Core Processor (Haswell, IBRS)",
- /*
- * This CPU model will eventually be replaced by an alias,
- * don't register any versions for it.
- */
- .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
- },
- {
- .name = "Broadwell-noTSX",
- .level = 0xd,
- .vendor = CPUID_VENDOR_INTEL,
- .family = 6,
- .model = 61,
- .stepping = 2,
- .features[FEAT_1_EDX] =
- CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
- CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
- CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
- CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
- CPUID_DE | CPUID_FP87,
- .features[FEAT_1_ECX] =
- CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
- CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
- CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
- CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
- CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
- CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
- .features[FEAT_8000_0001_EDX] =
- CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
- CPUID_EXT2_SYSCALL,
- .features[FEAT_8000_0001_ECX] =
- CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
- .features[FEAT_7_0_EBX] =
- CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
- CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
- CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
- CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
- CPUID_7_0_EBX_SMAP,
- .features[FEAT_XSAVE] =
- CPUID_XSAVE_XSAVEOPT,
- .features[FEAT_6_EAX] =
- CPUID_6_EAX_ARAT,
- .xlevel = 0x80000008,
- .model_id = "Intel Core Processor (Broadwell, no TSX)",
- /*
- * This CPU model will eventually be replaced by an alias,
- * don't register any versions for it.
- */
- .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
- },
- {
- .name = "Broadwell-noTSX-IBRS",
- .level = 0xd,
- .vendor = CPUID_VENDOR_INTEL,
- .family = 6,
- .model = 61,
- .stepping = 2,
- .features[FEAT_1_EDX] =
- CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
- CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
- CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
- CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
- CPUID_DE | CPUID_FP87,
- .features[FEAT_1_ECX] =
- CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
- CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
- CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
- CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
- CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
- CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
- .features[FEAT_8000_0001_EDX] =
- CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
- CPUID_EXT2_SYSCALL,
- .features[FEAT_8000_0001_ECX] =
- CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
- .features[FEAT_7_0_EDX] =
- CPUID_7_0_EDX_SPEC_CTRL,
- .features[FEAT_7_0_EBX] =
- CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
- CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
- CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
- CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
- CPUID_7_0_EBX_SMAP,
- .features[FEAT_XSAVE] =
- CPUID_XSAVE_XSAVEOPT,
- .features[FEAT_6_EAX] =
- CPUID_6_EAX_ARAT,
- .xlevel = 0x80000008,
- .model_id = "Intel Core Processor (Broadwell, no TSX, IBRS)",
- /*
- * This CPU model will eventually be replaced by an alias,
- * don't register any versions for it.
- */
- .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
- },
{
.name = "Broadwell",
.level = 0xd,
@@ -2481,7 +2124,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ .version = 1 },
{
.version = 2,
- /* Equivalent to Broadwell-noTSX */
+ .alias = "Broadwell-noTSX",
.props = (PropValue[]) {
{ "hle", "off" },
{ "rtm", "off" },
@@ -2491,7 +2134,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
},
{
.version = 3,
- /* Equivalent to Broadwell-IBRS */
+ .alias = "Broadwell-IBRS",
.props = (PropValue[]) {
/* Restore TSX features removed by -v2 above */
{ "hle", "on" },
@@ -2504,7 +2147,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
},
{
.version = 4,
- /* Equivalent to Broadwell-noTSX-IBRS */
+ .alias = "Broadwell-noTSX-IBRS",
.props = (PropValue[]) {
{ "hle", "off" },
{ "rtm", "off" },
@@ -2517,51 +2160,6 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ /* end of list */ }
}
},
- {
- .name = "Broadwell-IBRS",
- .level = 0xd,
- .vendor = CPUID_VENDOR_INTEL,
- .family = 6,
- .model = 61,
- .stepping = 2,
- .features[FEAT_1_EDX] =
- CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
- CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
- CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
- CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
- CPUID_DE | CPUID_FP87,
- .features[FEAT_1_ECX] =
- CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
- CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
- CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
- CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
- CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
- CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
- .features[FEAT_8000_0001_EDX] =
- CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
- CPUID_EXT2_SYSCALL,
- .features[FEAT_8000_0001_ECX] =
- CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
- .features[FEAT_7_0_EDX] =
- CPUID_7_0_EDX_SPEC_CTRL,
- .features[FEAT_7_0_EBX] =
- CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
- CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
- CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
- CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
- CPUID_7_0_EBX_SMAP,
- .features[FEAT_XSAVE] =
- CPUID_XSAVE_XSAVEOPT,
- .features[FEAT_6_EAX] =
- CPUID_6_EAX_ARAT,
- .xlevel = 0x80000008,
- .model_id = "Intel Core Processor (Broadwell, IBRS)",
- /*
- * This CPU model will eventually be replaced by an alias,
- * don't register any versions for it.
- */
- .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
- },
{
.name = "Skylake-Client",
.level = 0xd,
@@ -2610,7 +2208,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ .version = 1 },
{
.version = 2,
- /* Equivalent to Skylake-Client-IBRS */
+ .alias = "Skylake-Client-IBRS",
.props = (PropValue[]) {
{ "spec-ctrl", "on" },
{ "model-id",
@@ -2621,58 +2219,6 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ /* end of list */ }
}
},
- {
- .name = "Skylake-Client-IBRS",
- .level = 0xd,
- .vendor = CPUID_VENDOR_INTEL,
- .family = 6,
- .model = 94,
- .stepping = 3,
- .features[FEAT_1_EDX] =
- CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
- CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
- CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
- CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
- CPUID_DE | CPUID_FP87,
- .features[FEAT_1_ECX] =
- CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
- CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
- CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
- CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
- CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
- CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
- .features[FEAT_8000_0001_EDX] =
- CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
- CPUID_EXT2_SYSCALL,
- .features[FEAT_8000_0001_ECX] =
- CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
- .features[FEAT_7_0_EDX] =
- CPUID_7_0_EDX_SPEC_CTRL,
- .features[FEAT_7_0_EBX] =
- CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
- CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
- CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
- CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
- CPUID_7_0_EBX_SMAP,
- /* Missing: XSAVES (not supported by some Linux versions,
- * including v4.1 to v4.12).
- * KVM doesn't yet expose any XSAVES state save component,
- * and the only one defined in Skylake (processor tracing)
- * probably will block migration anyway.
- */
- .features[FEAT_XSAVE] =
- CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
- CPUID_XSAVE_XGETBV1,
- .features[FEAT_6_EAX] =
- CPUID_6_EAX_ARAT,
- .xlevel = 0x80000008,
- .model_id = "Intel Core Processor (Skylake, IBRS)",
- /*
- * This CPU model will eventually be replaced by an alias,
- * don't register any versions for it.
- */
- .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
- },
{
.name = "Skylake-Server",
.level = 0xd,
@@ -2726,7 +2272,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ .version = 1 },
{
.version = 2,
- /* Equivalent to Skylake-Server-IBRS */
+ .alias = "Skylake-Server-IBRS",
.props = (PropValue[]) {
/* clflushopt was not added to Skylake-Server-IBRS */
/* TODO: add -v3 including clflushopt */
@@ -2740,63 +2286,6 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ /* end of list */ }
}
},
- {
- .name = "Skylake-Server-IBRS",
- .level = 0xd,
- .vendor = CPUID_VENDOR_INTEL,
- .family = 6,
- .model = 85,
- .stepping = 4,
- .features[FEAT_1_EDX] =
- CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
- CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
- CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
- CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
- CPUID_DE | CPUID_FP87,
- .features[FEAT_1_ECX] =
- CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
- CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
- CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
- CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
- CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
- CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
- .features[FEAT_8000_0001_EDX] =
- CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
- CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
- .features[FEAT_8000_0001_ECX] =
- CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
- .features[FEAT_7_0_EDX] =
- CPUID_7_0_EDX_SPEC_CTRL,
- .features[FEAT_7_0_EBX] =
- CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
- CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
- CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
- CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
- CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
- CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
- CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
- CPUID_7_0_EBX_AVX512VL,
- .features[FEAT_7_0_ECX] =
- CPUID_7_0_ECX_PKU,
- /* Missing: XSAVES (not supported by some Linux versions,
- * including v4.1 to v4.12).
- * KVM doesn't yet expose any XSAVES state save component,
- * and the only one defined in Skylake (processor tracing)
- * probably will block migration anyway.
- */
- .features[FEAT_XSAVE] =
- CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
- CPUID_XSAVE_XGETBV1,
- .features[FEAT_6_EAX] =
- CPUID_6_EAX_ARAT,
- .xlevel = 0x80000008,
- .model_id = "Intel Xeon Processor (Skylake, IBRS)",
- /*
- * This CPU model will eventually be replaced by an alias,
- * don't register any versions for it.
- */
- .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
- },
{
.name = "Cascadelake-Server",
.level = 0xd,
@@ -3258,7 +2747,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ .version = 1 },
{
.version = 2,
- /* Equivalent to EPYC-IBPB */
+ .alias = "EPYC-IBPB",
.props = (PropValue[]) {
{ "ibpb", "on" },
{ "model-id",
@@ -3269,61 +2758,6 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ /* end of list */ }
}
},
- {
- .name = "EPYC-IBPB",
- .level = 0xd,
- .vendor = CPUID_VENDOR_AMD,
- .family = 23,
- .model = 1,
- .stepping = 2,
- .features[FEAT_1_EDX] =
- CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
- CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
- CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
- CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
- CPUID_VME | CPUID_FP87,
- .features[FEAT_1_ECX] =
- CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
- CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
- CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
- CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
- CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
- .features[FEAT_8000_0001_EDX] =
- CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
- CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
- CPUID_EXT2_SYSCALL,
- .features[FEAT_8000_0001_ECX] =
- CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
- CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
- CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
- CPUID_EXT3_TOPOEXT,
- .features[FEAT_8000_0008_EBX] =
- CPUID_8000_0008_EBX_IBPB,
- .features[FEAT_7_0_EBX] =
- CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
- CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
- CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
- CPUID_7_0_EBX_SHA_NI,
- /* Missing: XSAVES (not supported by some Linux versions,
- * including v4.1 to v4.12).
- * KVM doesn't yet expose any XSAVES state save component.
- */
- .features[FEAT_XSAVE] =
- CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
- CPUID_XSAVE_XGETBV1,
- .features[FEAT_6_EAX] =
- CPUID_6_EAX_ARAT,
- .features[FEAT_SVM] =
- CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
- .xlevel = 0x8000001E,
- .model_id = "AMD EPYC Processor (with IBPB)",
- .cache_info = &epyc_cache_info,
- /*
- * This CPU model will eventually be replaced by an alias,
- * don't register any versions for it.
- */
- .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
- },
{
.name = "Dhyana",
.level = 0xd,
@@ -4648,6 +4082,13 @@ static void x86_register_cpudef_types(X86CPUDefinition *def)
name = x86_cpu_versioned_model_name(def, vdef->version);
x86_register_cpu_model_type(name, m);
g_free(name);
+
+ if (vdef->alias) {
+ X86CPUModel *am = g_new0(X86CPUModel, 1);
+ am->cpudef = def;
+ am->version = vdef->version;
+ x86_register_cpu_model_type(vdef->alias, am);
+ }
}
}
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PULL v6 37/42] i386: Make unversioned CPU models be aliases
2019-07-05 22:14 [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 Eduardo Habkost
` (35 preceding siblings ...)
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 36/42] i386: Replace -noTSX, -IBRS, -IBPB CPU models with aliases Eduardo Habkost
@ 2019-07-05 22:14 ` Eduardo Habkost
2019-07-05 22:15 ` [Qemu-devel] [PULL v6 38/42] docs: Deprecate CPU model runnability guarantees Eduardo Habkost
` (6 subsequent siblings)
43 siblings, 0 replies; 49+ messages in thread
From: Eduardo Habkost @ 2019-07-05 22:14 UTC (permalink / raw)
To: Peter Maydell, Paolo Bonzini, qemu-devel, Marcel Apfelbaum,
Richard Henderson
This will make unversioned CPU models behavior depend on the
machine type:
* "pc-*-4.0" and older will not report them as aliases.
This is done to keep compatibility with older QEMU versions
after management software starts translating aliases.
* "pc-*-4.1" will translate unversioned CPU models to -v1.
This is done to keep compatibility with existing management
software, that still relies on CPU model runnability promises.
* "none" will translate unversioned CPU models to their latest
version. This is planned become the default in future machine
types (probably in pc-*-4.3).
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Message-Id: <20190628002844.24894-8-ehabkost@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
include/hw/i386/pc.h | 3 +
target/i386/cpu.h | 12 ++
hw/i386/pc.c | 3 +
hw/i386/pc_piix.c | 4 +
hw/i386/pc_q35.c | 4 +
target/i386/cpu.c | 52 ++++++++-
tests/acceptance/x86_cpu_model_versions.py | 126 +++++++++++++++++++++
7 files changed, 203 insertions(+), 1 deletion(-)
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 0fa3e3beeb..859b64c51d 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -109,6 +109,9 @@ typedef struct PCMachineClass {
/* Compat options: */
+ /* Default CPU model version. See x86_cpu_set_default_version(). */
+ int default_cpu_version;
+
/* ACPI compat: */
bool has_acpi_build;
bool rsdp_in_ram;
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 12bc3cd4a8..05393cf9d1 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1934,11 +1934,23 @@ void x86_cpu_change_kvm_default(const char *prop, const char *value);
/* Resolve to latest CPU version */
#define CPU_VERSION_LATEST -1
+/*
+ * Resolve to version defined by current machine type.
+ * See x86_cpu_set_default_version()
+ */
+#define CPU_VERSION_AUTO -2
+
/* Don't resolve to any versioned CPU models, like old QEMU versions */
#define CPU_VERSION_LEGACY 0
typedef int X86CPUVersion;
+/*
+ * Set default CPU model version for CPU models having
+ * version == CPU_VERSION_AUTO.
+ */
+void x86_cpu_set_default_version(X86CPUVersion version);
+
/* Return name of 32-bit register, from a R_* constant */
const char *get_register_name_32(unsigned int reg);
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index b9c55301a2..c33ce47578 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1645,6 +1645,9 @@ void pc_cpus_init(PCMachineState *pcms)
const CPUArchIdList *possible_cpus;
MachineState *ms = MACHINE(pcms);
MachineClass *mc = MACHINE_GET_CLASS(pcms);
+ PCMachineClass *pcmc = PC_MACHINE_CLASS(mc);
+
+ x86_cpu_set_default_version(pcmc->default_cpu_version);
/* Calculates the limit to CPU APIC ID values
*
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index f29de58636..581b3c2baa 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -429,9 +429,11 @@ static void pc_i440fx_machine_options(MachineClass *m)
static void pc_i440fx_4_1_machine_options(MachineClass *m)
{
+ PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
pc_i440fx_machine_options(m);
m->alias = "pc";
m->is_default = 1;
+ pcmc->default_cpu_version = 1;
}
DEFINE_I440FX_MACHINE(v4_1, "pc-i440fx-4.1", NULL,
@@ -439,9 +441,11 @@ DEFINE_I440FX_MACHINE(v4_1, "pc-i440fx-4.1", NULL,
static void pc_i440fx_4_0_machine_options(MachineClass *m)
{
+ PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
pc_i440fx_4_1_machine_options(m);
m->alias = NULL;
m->is_default = 0;
+ pcmc->default_cpu_version = CPU_VERSION_LEGACY;
compat_props_add(m->compat_props, hw_compat_4_0, hw_compat_4_0_len);
compat_props_add(m->compat_props, pc_compat_4_0, pc_compat_4_0_len);
}
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 57232aed6b..397e1fdd2f 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -367,8 +367,10 @@ static void pc_q35_machine_options(MachineClass *m)
static void pc_q35_4_1_machine_options(MachineClass *m)
{
+ PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
pc_q35_machine_options(m);
m->alias = "q35";
+ pcmc->default_cpu_version = 1;
}
DEFINE_Q35_MACHINE(v4_1, "pc-q35-4.1", NULL,
@@ -376,8 +378,10 @@ DEFINE_Q35_MACHINE(v4_1, "pc-q35-4.1", NULL,
static void pc_q35_4_0_1_machine_options(MachineClass *m)
{
+ PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
pc_q35_4_1_machine_options(m);
m->alias = NULL;
+ pcmc->default_cpu_version = CPU_VERSION_LEGACY;
/*
* This is the default machine for the 4.0-stable branch. It is basically
* a 4.0 that doesn't use split irqchip by default. It MUST hence apply the
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index f41917649d..0cf8e545c6 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1470,6 +1470,11 @@ struct X86CPUModel {
X86CPUDefinition *cpudef;
/* CPU model version */
X86CPUVersion version;
+ /*
+ * If true, this is an alias CPU model.
+ * This matters only for "-cpu help" and query-cpu-definitions
+ */
+ bool is_alias;
};
/* Get full model name for CPU version */
@@ -2835,6 +2840,15 @@ static PropValue tcg_default_props[] = {
};
+X86CPUVersion default_cpu_version = CPU_VERSION_LATEST;
+
+void x86_cpu_set_default_version(X86CPUVersion version)
+{
+ /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */
+ assert(version != CPU_VERSION_AUTO);
+ default_cpu_version = version;
+}
+
static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model)
{
int v = 0;
@@ -2851,6 +2865,9 @@ static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model)
static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model)
{
X86CPUVersion v = model->version;
+ if (v == CPU_VERSION_AUTO) {
+ v = default_cpu_version;
+ }
if (v == CPU_VERSION_LATEST) {
return x86_cpu_model_last_version(model);
}
@@ -3589,13 +3606,35 @@ static char *x86_cpu_class_get_model_id(X86CPUClass *xc)
return r;
}
+static char *x86_cpu_class_get_alias_of(X86CPUClass *cc)
+{
+ X86CPUVersion version;
+
+ if (!cc->model || !cc->model->is_alias) {
+ return NULL;
+ }
+ version = x86_cpu_model_resolve_version(cc->model);
+ if (version <= 0) {
+ return NULL;
+ }
+ return x86_cpu_versioned_model_name(cc->model->cpudef, version);
+}
+
static void x86_cpu_list_entry(gpointer data, gpointer user_data)
{
ObjectClass *oc = data;
X86CPUClass *cc = X86_CPU_CLASS(oc);
char *name = x86_cpu_class_get_model_name(cc);
char *desc = g_strdup(cc->model_description);
+ char *alias_of = x86_cpu_class_get_alias_of(cc);
+ if (!desc && alias_of) {
+ if (cc->model && cc->model->version == CPU_VERSION_AUTO) {
+ desc = g_strdup("(alias configured by machine type)");
+ } else {
+ desc = g_strdup_printf("(alias of %s)", alias_of);
+ }
+ }
if (!desc) {
desc = x86_cpu_class_get_model_id(cc);
}
@@ -3603,6 +3642,7 @@ static void x86_cpu_list_entry(gpointer data, gpointer user_data)
qemu_printf("x86 %-20s %-48s\n", name, desc);
g_free(name);
g_free(desc);
+ g_free(alias_of);
}
/* list available CPU models and flags */
@@ -3651,6 +3691,14 @@ static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
info->migration_safe = cc->migration_safe;
info->has_migration_safe = true;
info->q_static = cc->static_model;
+ /*
+ * Old machine types won't report aliases, so that alias translation
+ * doesn't break compatibility with previous QEMU versions.
+ */
+ if (default_cpu_version != CPU_VERSION_LEGACY) {
+ info->alias_of = x86_cpu_class_get_alias_of(cc);
+ info->has_alias_of = !!info->alias_of;
+ }
entry = g_malloc0(sizeof(*entry));
entry->value = info;
@@ -4070,7 +4118,8 @@ static void x86_register_cpudef_types(X86CPUDefinition *def)
/* Unversioned model: */
m = g_new0(X86CPUModel, 1);
m->cpudef = def;
- m->version = CPU_VERSION_LEGACY;
+ m->version = CPU_VERSION_AUTO;
+ m->is_alias = true;
x86_register_cpu_model_type(def->name, m);
/* Versioned models: */
@@ -4087,6 +4136,7 @@ static void x86_register_cpudef_types(X86CPUDefinition *def)
X86CPUModel *am = g_new0(X86CPUModel, 1);
am->cpudef = def;
am->version = vdef->version;
+ am->is_alias = true;
x86_register_cpu_model_type(vdef->alias, am);
}
}
diff --git a/tests/acceptance/x86_cpu_model_versions.py b/tests/acceptance/x86_cpu_model_versions.py
index b85d6f8604..165c0c7601 100644
--- a/tests/acceptance/x86_cpu_model_versions.py
+++ b/tests/acceptance/x86_cpu_model_versions.py
@@ -103,3 +103,129 @@ class X86CPUModelAliases(avocado_qemu.Test):
# On pc-*-4.0, no CPU model should be reported as an alias:
for name,c in cpus.items():
self.assertNotIn('alias-of', c, "%s shouldn't be an alias" % (name))
+
+ def test_4_1_alias(self):
+ """Check if unversioned CPU model is an alias pointing to right version"""
+ self.vm.add_args('-S')
+ self.vm.set_machine('pc-i440fx-4.1')
+ self.vm.launch()
+
+ cpus = dict((m['name'], m) for m in self.vm.command('query-cpu-definitions'))
+
+ self.assertFalse(cpus['Cascadelake-Server']['static'],
+ 'unversioned Cascadelake-Server CPU model must not be static')
+ self.assertEquals(cpus['Cascadelake-Server'].get('alias-of'), 'Cascadelake-Server-v1',
+ 'Cascadelake-Server must be an alias of Cascadelake-Server-v1')
+ self.assertNotIn('alias-of', cpus['Cascadelake-Server-v1'],
+ 'Cascadelake-Server-v1 must not be an alias')
+
+ self.assertFalse(cpus['qemu64']['static'],
+ 'unversioned qemu64 CPU model must not be static')
+ self.assertEquals(cpus['qemu64'].get('alias-of'), 'qemu64-v1',
+ 'qemu64 must be an alias of qemu64-v1')
+ self.assertNotIn('alias-of', cpus['qemu64-v1'],
+ 'qemu64-v1 must not be an alias')
+
+ self.validate_variant_aliases(cpus)
+
+ # On pc-*-4.1, -noTSX and -IBRS models should be aliases:
+ self.assertEquals(cpus["Haswell"].get('alias-of'),
+ "Haswell-v1",
+ "Haswell must be an alias")
+ self.assertEquals(cpus["Haswell-noTSX"].get('alias-of'),
+ "Haswell-v2",
+ "Haswell-noTSX must be an alias")
+ self.assertEquals(cpus["Haswell-IBRS"].get('alias-of'),
+ "Haswell-v3",
+ "Haswell-IBRS must be an alias")
+ self.assertEquals(cpus["Haswell-noTSX-IBRS"].get('alias-of'),
+ "Haswell-v4",
+ "Haswell-noTSX-IBRS must be an alias")
+
+ self.assertEquals(cpus["Broadwell"].get('alias-of'),
+ "Broadwell-v1",
+ "Broadwell must be an alias")
+ self.assertEquals(cpus["Broadwell-noTSX"].get('alias-of'),
+ "Broadwell-v2",
+ "Broadwell-noTSX must be an alias")
+ self.assertEquals(cpus["Broadwell-IBRS"].get('alias-of'),
+ "Broadwell-v3",
+ "Broadwell-IBRS must be an alias")
+ self.assertEquals(cpus["Broadwell-noTSX-IBRS"].get('alias-of'),
+ "Broadwell-v4",
+ "Broadwell-noTSX-IBRS must be an alias")
+
+ self.assertEquals(cpus["Nehalem"].get('alias-of'),
+ "Nehalem-v1",
+ "Nehalem must be an alias")
+ self.assertEquals(cpus["Nehalem-IBRS"].get('alias-of'),
+ "Nehalem-v2",
+ "Nehalem-IBRS must be an alias")
+
+ self.assertEquals(cpus["Westmere"].get('alias-of'),
+ "Westmere-v1",
+ "Westmere must be an alias")
+ self.assertEquals(cpus["Westmere-IBRS"].get('alias-of'),
+ "Westmere-v2",
+ "Westmere-IBRS must be an alias")
+
+ self.assertEquals(cpus["SandyBridge"].get('alias-of'),
+ "SandyBridge-v1",
+ "SandyBridge must be an alias")
+ self.assertEquals(cpus["SandyBridge-IBRS"].get('alias-of'),
+ "SandyBridge-v2",
+ "SandyBridge-IBRS must be an alias")
+
+ self.assertEquals(cpus["IvyBridge"].get('alias-of'),
+ "IvyBridge-v1",
+ "IvyBridge must be an alias")
+ self.assertEquals(cpus["IvyBridge-IBRS"].get('alias-of'),
+ "IvyBridge-v2",
+ "IvyBridge-IBRS must be an alias")
+
+ self.assertEquals(cpus["Skylake-Client"].get('alias-of'),
+ "Skylake-Client-v1",
+ "Skylake-Client must be an alias")
+ self.assertEquals(cpus["Skylake-Client-IBRS"].get('alias-of'),
+ "Skylake-Client-v2",
+ "Skylake-Client-IBRS must be an alias")
+
+ self.assertEquals(cpus["Skylake-Server"].get('alias-of'),
+ "Skylake-Server-v1",
+ "Skylake-Server must be an alias")
+ self.assertEquals(cpus["Skylake-Server-IBRS"].get('alias-of'),
+ "Skylake-Server-v2",
+ "Skylake-Server-IBRS must be an alias")
+
+ self.assertEquals(cpus["EPYC"].get('alias-of'),
+ "EPYC-v1",
+ "EPYC must be an alias")
+ self.assertEquals(cpus["EPYC-IBPB"].get('alias-of'),
+ "EPYC-v2",
+ "EPYC-IBPB must be an alias")
+
+ self.validate_aliases(cpus)
+
+ def test_none_alias(self):
+ """Check if unversioned CPU model is an alias pointing to some version"""
+ self.vm.add_args('-S')
+ self.vm.set_machine('none')
+ self.vm.launch()
+
+ cpus = dict((m['name'], m) for m in self.vm.command('query-cpu-definitions'))
+
+ self.assertFalse(cpus['Cascadelake-Server']['static'],
+ 'unversioned Cascadelake-Server CPU model must not be static')
+ self.assertTrue(re.match('Cascadelake-Server-v[0-9]+', cpus['Cascadelake-Server']['alias-of']),
+ 'Cascadelake-Server must be an alias of versioned CPU model')
+ self.assertNotIn('alias-of', cpus['Cascadelake-Server-v1'],
+ 'Cascadelake-Server-v1 must not be an alias')
+
+ self.assertFalse(cpus['qemu64']['static'],
+ 'unversioned qemu64 CPU model must not be static')
+ self.assertTrue(re.match('qemu64-v[0-9]+', cpus['qemu64']['alias-of']),
+ 'qemu64 must be an alias of versioned CPU model')
+ self.assertNotIn('alias-of', cpus['qemu64-v1'],
+ 'qemu64-v1 must not be an alias')
+
+ self.validate_aliases(cpus)
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PULL v6 38/42] docs: Deprecate CPU model runnability guarantees
2019-07-05 22:14 [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 Eduardo Habkost
` (36 preceding siblings ...)
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 37/42] i386: Make unversioned CPU models be aliases Eduardo Habkost
@ 2019-07-05 22:15 ` Eduardo Habkost
2019-07-05 22:15 ` [Qemu-devel] [PULL v6 39/42] i386: Add Cascadelake-Server-v2 CPU model Eduardo Habkost
` (5 subsequent siblings)
43 siblings, 0 replies; 49+ messages in thread
From: Eduardo Habkost @ 2019-07-05 22:15 UTC (permalink / raw)
To: Peter Maydell, Paolo Bonzini, qemu-devel, Marcel Apfelbaum,
Richard Henderson
Document that CPU model runnability guarantees won't apply to
unversioned CPU models anymore.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Message-Id: <20190628002844.24894-9-ehabkost@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
qemu-deprecated.texi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/qemu-deprecated.texi b/qemu-deprecated.texi
index e6891c3a93..c90b08d553 100644
--- a/qemu-deprecated.texi
+++ b/qemu-deprecated.texi
@@ -292,3 +292,22 @@ subset of the image.
In the future, QEMU will require Python 3 to be available at
build time. Support for Python 2 in scripts shipped with QEMU
is deprecated.
+
+@section Backwards compatibility
+
+@subsection Runnability guarantee of CPU models (since 4.1.0)
+
+Previous versions of QEMU never changed existing CPU models in
+ways that introduced additional host software or hardware
+requirements to the VM. This allowed management software to
+safely change the machine type of an existing VM without
+introducing new requirements ("runnability guarantee"). This
+prevented CPU models from being updated to include CPU
+vulnerability mitigations, leaving guests vulnerable in the
+default configuration.
+
+The CPU model runnability guarantee won't apply anymore to
+existing CPU models. Management software that needs runnability
+guarantees must resolve the CPU model aliases using te
+``alias-of'' field returned by the ``query-cpu-definitions'' QMP
+command.
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PULL v6 39/42] i386: Add Cascadelake-Server-v2 CPU model
2019-07-05 22:14 [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 Eduardo Habkost
` (37 preceding siblings ...)
2019-07-05 22:15 ` [Qemu-devel] [PULL v6 38/42] docs: Deprecate CPU model runnability guarantees Eduardo Habkost
@ 2019-07-05 22:15 ` Eduardo Habkost
2019-07-05 22:15 ` [Qemu-devel] [PULL v6 40/42] numa: Make deprecation warnings conditional on !qtest_enabled() Eduardo Habkost
` (4 subsequent siblings)
43 siblings, 0 replies; 49+ messages in thread
From: Eduardo Habkost @ 2019-07-05 22:15 UTC (permalink / raw)
To: Peter Maydell, Paolo Bonzini, qemu-devel, Marcel Apfelbaum,
Richard Henderson
Add new version of Cascadelake-Server CPU model, setting
stepping=5 and enabling the IA32_ARCH_CAPABILITIES MSR
with some flags.
The new feature will introduce a new host software requirement,
breaking our CPU model runnability promises. This means we can't
enable the new CPU model version by default in QEMU 4.1, because
management software isn't ready yet to resolve CPU model aliases.
This is why "pc-*-4.1" will keep returning Cascadelake-Server-v1
if "-cpu Cascadelake-Server" is specified.
Includes a test case to ensure the right combinations of
machine-type + CPU model + command-line feature flags will work
as expected.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Message-Id: <20190628002844.24894-10-ehabkost@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20190703221723.8161-1-ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
target/i386/cpu.c | 14 +++++
tests/acceptance/x86_cpu_model_versions.py | 73 ++++++++++++++++++++++
2 files changed, 87 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 0cf8e545c6..805ce95247 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2343,6 +2343,20 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Xeon Processor (Cascadelake)",
+ .versions = (X86CPUVersionDefinition[]) {
+ { .version = 1 },
+ { .version = 2,
+ .props = (PropValue[]) {
+ { "arch-capabilities", "on" },
+ { "rdctl-no", "on" },
+ { "ibrs-all", "on" },
+ { "skip-l1dfl-vmentry", "on" },
+ { "mds-no", "on" },
+ { /* end of list */ }
+ },
+ },
+ { /* end of list */ }
+ }
},
{
.name = "Icelake-Client",
diff --git a/tests/acceptance/x86_cpu_model_versions.py b/tests/acceptance/x86_cpu_model_versions.py
index 165c0c7601..1c9fd6a56e 100644
--- a/tests/acceptance/x86_cpu_model_versions.py
+++ b/tests/acceptance/x86_cpu_model_versions.py
@@ -25,6 +25,10 @@
import avocado_qemu
import re
+def get_cpu_prop(vm, prop):
+ cpu_path = vm.command('query-cpus')[0].get('qom_path')
+ return vm.command('qom-get', path=cpu_path, property=prop)
+
class X86CPUModelAliases(avocado_qemu.Test):
"""
Validation of PC CPU model versions and CPU model aliases
@@ -229,3 +233,72 @@ class X86CPUModelAliases(avocado_qemu.Test):
'qemu64-v1 must not be an alias')
self.validate_aliases(cpus)
+
+ def test_Cascadelake_arch_capabilities_result(self):
+ # machine-type only:
+ vm = self.get_vm()
+ vm.add_args('-S')
+ vm.set_machine('pc-i440fx-4.1')
+ vm.add_args('-cpu', 'Cascadelake-Server,x-force-features=on,check=off,enforce=off')
+ vm.launch()
+ self.assertFalse(get_cpu_prop(vm, 'arch-capabilities'),
+ 'pc-i440fx-4.1 + Cascadelake-Server should not have arch-capabilities')
+
+ vm = self.get_vm()
+ vm.add_args('-S')
+ vm.set_machine('pc-i440fx-4.0')
+ vm.add_args('-cpu', 'Cascadelake-Server,x-force-features=on,check=off,enforce=off')
+ vm.launch()
+ self.assertFalse(get_cpu_prop(vm, 'arch-capabilities'),
+ 'pc-i440fx-4.0 + Cascadelake-Server should not have arch-capabilities')
+
+ # command line must override machine-type if CPU model is not versioned:
+ vm = self.get_vm()
+ vm.add_args('-S')
+ vm.set_machine('pc-i440fx-4.0')
+ vm.add_args('-cpu', 'Cascadelake-Server,x-force-features=on,check=off,enforce=off,+arch-capabilities')
+ vm.launch()
+ self.assertTrue(get_cpu_prop(vm, 'arch-capabilities'),
+ 'pc-i440fx-4.0 + Cascadelake-Server,+arch-capabilities should have arch-capabilities')
+
+ vm = self.get_vm()
+ vm.add_args('-S')
+ vm.set_machine('pc-i440fx-4.1')
+ vm.add_args('-cpu', 'Cascadelake-Server,x-force-features=on,check=off,enforce=off,-arch-capabilities')
+ vm.launch()
+ self.assertFalse(get_cpu_prop(vm, 'arch-capabilities'),
+ 'pc-i440fx-4.1 + Cascadelake-Server,-arch-capabilities should not have arch-capabilities')
+
+ # versioned CPU model overrides machine-type:
+ vm = self.get_vm()
+ vm.add_args('-S')
+ vm.set_machine('pc-i440fx-4.0')
+ vm.add_args('-cpu', 'Cascadelake-Server-v1,x-force-features=on,check=off,enforce=off')
+ vm.launch()
+ self.assertFalse(get_cpu_prop(vm, 'arch-capabilities'),
+ 'pc-i440fx-4.1 + Cascadelake-Server-v1 should not have arch-capabilities')
+
+ vm = self.get_vm()
+ vm.add_args('-S')
+ vm.set_machine('pc-i440fx-4.0')
+ vm.add_args('-cpu', 'Cascadelake-Server-v2,x-force-features=on,check=off,enforce=off')
+ vm.launch()
+ self.assertTrue(get_cpu_prop(vm, 'arch-capabilities'),
+ 'pc-i440fx-4.1 + Cascadelake-Server-v1 should have arch-capabilities')
+
+ # command line must override machine-type and versioned CPU model:
+ vm = self.get_vm()
+ vm.add_args('-S')
+ vm.set_machine('pc-i440fx-4.0')
+ vm.add_args('-cpu', 'Cascadelake-Server,x-force-features=on,check=off,enforce=off,+arch-capabilities')
+ vm.launch()
+ self.assertTrue(get_cpu_prop(vm, 'arch-capabilities'),
+ 'pc-i440fx-4.0 + Cascadelake-Server-v1,+arch-capabilities should have arch-capabilities')
+
+ vm = self.get_vm()
+ vm.add_args('-S')
+ vm.set_machine('pc-i440fx-4.1')
+ vm.add_args('-cpu', 'Cascadelake-Server-v2,x-force-features=on,check=off,enforce=off,-arch-capabilities')
+ vm.launch()
+ self.assertFalse(get_cpu_prop(vm, 'arch-capabilities'),
+ 'pc-i440fx-4.1 + Cascadelake-Server-v2,-arch-capabilities should not have arch-capabilities')
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PULL v6 40/42] numa: Make deprecation warnings conditional on !qtest_enabled()
2019-07-05 22:14 [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 Eduardo Habkost
` (38 preceding siblings ...)
2019-07-05 22:15 ` [Qemu-devel] [PULL v6 39/42] i386: Add Cascadelake-Server-v2 CPU model Eduardo Habkost
@ 2019-07-05 22:15 ` Eduardo Habkost
2019-07-05 22:15 ` [Qemu-devel] [PULL v6 41/42] numa: allow memory-less nodes when using memdev as backend Eduardo Habkost
` (3 subsequent siblings)
43 siblings, 0 replies; 49+ messages in thread
From: Eduardo Habkost @ 2019-07-05 22:15 UTC (permalink / raw)
To: Peter Maydell, Paolo Bonzini, qemu-devel, Marcel Apfelbaum,
Richard Henderson
This will help us avoid spurious warnings during "make check".
Note that this will silence the warnings generated by
tests/numa-test, but not the ones generated by
tests/bios-tables-test. We still need to change
tests/bios-tables-test to use "-numa ...,memdev=" to silence
these warnings.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Message-Id: <20190702215726.23661-1-ehabkost@redhat.com>
---
hw/core/numa.c | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/hw/core/numa.c b/hw/core/numa.c
index dd5c6e2334..2d984b025b 100644
--- a/hw/core/numa.c
+++ b/hw/core/numa.c
@@ -31,6 +31,7 @@
#include "qapi/error.h"
#include "qapi/opts-visitor.h"
#include "qapi/qapi-visit-machine.h"
+#include "sysemu/qtest.h"
#include "hw/mem/pc-dimm.h"
#include "hw/mem/memory-device.h"
#include "qemu/option.h"
@@ -118,8 +119,10 @@ static void parse_numa_node(MachineState *ms, NumaNodeOptions *node,
if (node->has_mem) {
numa_info[nodenr].node_mem = node->mem;
- warn_report("Parameter -numa node,mem is deprecated,"
- " use -numa node,memdev instead");
+ if (!qtest_enabled()) {
+ warn_report("Parameter -numa node,mem is deprecated,"
+ " use -numa node,memdev instead");
+ }
}
if (node->has_memdev) {
Object *o;
@@ -405,9 +408,11 @@ void numa_complete_configuration(MachineState *ms)
if (i == nb_numa_nodes) {
assert(mc->numa_auto_assign_ram);
mc->numa_auto_assign_ram(mc, numa_info, nb_numa_nodes, ram_size);
- warn_report("Default splitting of RAM between nodes is deprecated,"
- " Use '-numa node,memdev' to explictly define RAM"
- " allocation per node");
+ if (!qtest_enabled()) {
+ warn_report("Default splitting of RAM between nodes is deprecated,"
+ " Use '-numa node,memdev' to explictly define RAM"
+ " allocation per node");
+ }
}
numa_total = 0;
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PULL v6 41/42] numa: allow memory-less nodes when using memdev as backend
2019-07-05 22:14 [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 Eduardo Habkost
` (39 preceding siblings ...)
2019-07-05 22:15 ` [Qemu-devel] [PULL v6 40/42] numa: Make deprecation warnings conditional on !qtest_enabled() Eduardo Habkost
@ 2019-07-05 22:15 ` Eduardo Habkost
2019-07-05 22:15 ` [Qemu-devel] [PULL v6 42/42] tests: use -numa memdev option in tests instead of legacy 'mem' option Eduardo Habkost
` (2 subsequent siblings)
43 siblings, 0 replies; 49+ messages in thread
From: Eduardo Habkost @ 2019-07-05 22:15 UTC (permalink / raw)
To: Peter Maydell, Paolo Bonzini, qemu-devel, Marcel Apfelbaum,
Richard Henderson
Cc: Igor Mammedov
From: Igor Mammedov <imammedo@redhat.com>
QEMU fails to start if memory-less node is present when memdev
is used
qemu-system-x86_64 -object memory-backend-ram,id=ram0,size=128M \
-numa node -numa node,memdev=ram0
with error:
"memdev option must be specified for either all or no nodes"
which works as expected if legacy 'mem' is used.
Fix check to make memory-less nodes valid when memdev option is used
but still disallow mix of mem and memdev options.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20190702140745.27767-2-imammedo@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
hw/core/numa.c | 19 +++++++------------
1 file changed, 7 insertions(+), 12 deletions(-)
diff --git a/hw/core/numa.c b/hw/core/numa.c
index 2d984b025b..a11431483c 100644
--- a/hw/core/numa.c
+++ b/hw/core/numa.c
@@ -45,7 +45,8 @@ QemuOptsList qemu_numa_opts = {
.desc = { { 0 } } /* validated with OptsVisitor */
};
-static int have_memdevs = -1;
+static int have_memdevs;
+static int have_mem;
static int max_numa_nodeid; /* Highest specified NUMA node ID, plus one.
* For all nodes, nodeid < max_numa_nodeid
*/
@@ -103,17 +104,11 @@ static void parse_numa_node(MachineState *ms, NumaNodeOptions *node,
}
}
- if (node->has_mem && node->has_memdev) {
- error_setg(errp, "cannot specify both mem= and memdev=");
- return;
- }
-
- if (have_memdevs == -1) {
- have_memdevs = node->has_memdev;
- }
- if (node->has_memdev != have_memdevs) {
- error_setg(errp, "memdev option must be specified for either "
- "all or no nodes");
+ have_memdevs = have_memdevs ? : node->has_memdev;
+ have_mem = have_mem ? : node->has_mem;
+ if ((node->has_mem && have_memdevs) || (node->has_memdev && have_mem)) {
+ error_setg(errp, "numa configuration should use either mem= or memdev=,"
+ "mixing both is not allowed");
return;
}
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [Qemu-devel] [PULL v6 42/42] tests: use -numa memdev option in tests instead of legacy 'mem' option
2019-07-05 22:14 [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 Eduardo Habkost
` (40 preceding siblings ...)
2019-07-05 22:15 ` [Qemu-devel] [PULL v6 41/42] numa: allow memory-less nodes when using memdev as backend Eduardo Habkost
@ 2019-07-05 22:15 ` Eduardo Habkost
2019-07-06 6:46 ` [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 no-reply
2019-07-08 9:26 ` Peter Maydell
43 siblings, 0 replies; 49+ messages in thread
From: Eduardo Habkost @ 2019-07-05 22:15 UTC (permalink / raw)
To: Peter Maydell, Paolo Bonzini, qemu-devel, Marcel Apfelbaum,
Richard Henderson
Cc: Igor Mammedov
From: Igor Mammedov <imammedo@redhat.com>
it will test preferred memdev option more extensively and remove
undesired deprecation warnings during 'make check'
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20190702140745.27767-3-imammedo@redhat.com>
[ehabkost: remove numa-test.c changes]
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
tests/bios-tables-test.c | 40 ++++++++++++++++++++++++++++------------
1 file changed, 28 insertions(+), 12 deletions(-)
diff --git a/tests/bios-tables-test.c b/tests/bios-tables-test.c
index 0ce55182f2..d863233fe9 100644
--- a/tests/bios-tables-test.c
+++ b/tests/bios-tables-test.c
@@ -688,6 +688,8 @@ static void test_acpi_q35_tcg_mmio64(void)
};
test_acpi_one("-m 128M,slots=1,maxmem=2G "
+ "-object memory-backend-ram,id=ram0,size=128M "
+ "-numa node,memdev=ram0 "
"-device pci-testdev,membar=2G",
&data);
free_test_data(&data);
@@ -701,7 +703,9 @@ static void test_acpi_piix4_tcg_cphp(void)
data.machine = MACHINE_PC;
data.variant = ".cphp";
test_acpi_one("-smp 2,cores=3,sockets=2,maxcpus=6"
- " -numa node -numa node"
+ " -object memory-backend-ram,id=ram0,size=64M"
+ " -object memory-backend-ram,id=ram1,size=64M"
+ " -numa node,memdev=ram0 -numa node,memdev=ram1"
" -numa dist,src=0,dst=1,val=21",
&data);
free_test_data(&data);
@@ -715,7 +719,9 @@ static void test_acpi_q35_tcg_cphp(void)
data.machine = MACHINE_Q35;
data.variant = ".cphp";
test_acpi_one(" -smp 2,cores=3,sockets=2,maxcpus=6"
- " -numa node -numa node"
+ " -object memory-backend-ram,id=ram0,size=64M"
+ " -object memory-backend-ram,id=ram1,size=64M"
+ " -numa node,memdev=ram0 -numa node,memdev=ram1"
" -numa dist,src=0,dst=1,val=21",
&data);
free_test_data(&data);
@@ -766,7 +772,9 @@ static void test_acpi_q35_tcg_memhp(void)
data.machine = MACHINE_Q35;
data.variant = ".memhp";
test_acpi_one(" -m 128,slots=3,maxmem=1G"
- " -numa node -numa node"
+ " -object memory-backend-ram,id=ram0,size=64M"
+ " -object memory-backend-ram,id=ram1,size=64M"
+ " -numa node,memdev=ram0 -numa node,memdev=ram1"
" -numa dist,src=0,dst=1,val=21",
&data);
free_test_data(&data);
@@ -780,7 +788,9 @@ static void test_acpi_piix4_tcg_memhp(void)
data.machine = MACHINE_PC;
data.variant = ".memhp";
test_acpi_one(" -m 128,slots=3,maxmem=1G"
- " -numa node -numa node"
+ " -object memory-backend-ram,id=ram0,size=64M"
+ " -object memory-backend-ram,id=ram1,size=64M"
+ " -numa node,memdev=ram0 -numa node,memdev=ram1"
" -numa dist,src=0,dst=1,val=21",
&data);
free_test_data(&data);
@@ -793,7 +803,8 @@ static void test_acpi_q35_tcg_numamem(void)
memset(&data, 0, sizeof(data));
data.machine = MACHINE_Q35;
data.variant = ".numamem";
- test_acpi_one(" -numa node -numa node,mem=128", &data);
+ test_acpi_one(" -object memory-backend-ram,id=ram0,size=128M"
+ " -numa node -numa node,memdev=ram0", &data);
free_test_data(&data);
}
@@ -804,7 +815,8 @@ static void test_acpi_piix4_tcg_numamem(void)
memset(&data, 0, sizeof(data));
data.machine = MACHINE_PC;
data.variant = ".numamem";
- test_acpi_one(" -numa node -numa node,mem=128", &data);
+ test_acpi_one(" -object memory-backend-ram,id=ram0,size=128M"
+ " -numa node -numa node,memdev=ram0", &data);
free_test_data(&data);
}
@@ -818,17 +830,21 @@ static void test_acpi_tcg_dimm_pxm(const char *machine)
test_acpi_one(" -machine nvdimm=on,nvdimm-persistence=cpu"
" -smp 4,sockets=4"
" -m 128M,slots=3,maxmem=1G"
- " -numa node,mem=32M,nodeid=0"
- " -numa node,mem=32M,nodeid=1"
- " -numa node,mem=32M,nodeid=2"
- " -numa node,mem=32M,nodeid=3"
+ " -object memory-backend-ram,id=ram0,size=32M"
+ " -object memory-backend-ram,id=ram1,size=32M"
+ " -object memory-backend-ram,id=ram2,size=32M"
+ " -object memory-backend-ram,id=ram3,size=32M"
+ " -numa node,memdev=ram0,nodeid=0"
+ " -numa node,memdev=ram1,nodeid=1"
+ " -numa node,memdev=ram2,nodeid=2"
+ " -numa node,memdev=ram3,nodeid=3"
" -numa cpu,node-id=0,socket-id=0"
" -numa cpu,node-id=1,socket-id=1"
" -numa cpu,node-id=2,socket-id=2"
" -numa cpu,node-id=3,socket-id=3"
- " -object memory-backend-ram,id=ram0,size=128M"
+ " -object memory-backend-ram,id=ram4,size=128M"
" -object memory-backend-ram,id=nvm0,size=128M"
- " -device pc-dimm,id=dimm0,memdev=ram0,node=1"
+ " -device pc-dimm,id=dimm0,memdev=ram4,node=1"
" -device nvdimm,id=dimm1,memdev=nvm0,node=2",
&data);
free_test_data(&data);
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 49+ messages in thread
* Re: [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05
2019-07-05 22:14 [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 Eduardo Habkost
` (41 preceding siblings ...)
2019-07-05 22:15 ` [Qemu-devel] [PULL v6 42/42] tests: use -numa memdev option in tests instead of legacy 'mem' option Eduardo Habkost
@ 2019-07-06 6:46 ` no-reply
2019-07-08 9:26 ` Peter Maydell
43 siblings, 0 replies; 49+ messages in thread
From: no-reply @ 2019-07-06 6:46 UTC (permalink / raw)
To: ehabkost; +Cc: peter.maydell, rth, qemu-devel, pbonzini
Patchew URL: https://patchew.org/QEMU/20190705221504.25166-1-ehabkost@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20190705221504.25166-1-ehabkost@redhat.com
Subject: [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
8222dd1 tests: use -numa memdev option in tests instead of legacy 'mem' option
17f968f numa: allow memory-less nodes when using memdev as backend
ba5a8f5 numa: Make deprecation warnings conditional on !qtest_enabled()
e7eed65 i386: Add Cascadelake-Server-v2 CPU model
c270e11 docs: Deprecate CPU model runnability guarantees
d148782 i386: Make unversioned CPU models be aliases
212584e i386: Replace -noTSX, -IBRS, -IBPB CPU models with aliases
14bea5f i386: Define -IBRS, -noTSX, -IBRS versions of CPU models
abe39dc i386: Register versioned CPU models
43e890f i386: Get model-id from CPU object on "-cpu help"
86bad9a i386: Add x-force-features option for testing
3764570 qmp: Add "alias-of" field to query-cpu-definitions
2136259 i386: Introduce SnowRidge CPU model
5c64e25 qmp: Add deprecation information to query-machines
d9fca16 vl.c: Add -smp, dies=* command line support and update doc
58066f7 machine: Refactor smp_parse() in vl.c as MachineClass::smp_parse()
e5521eb target/i386: Add CPUID.1F generation support for multi-dies PCMachine
efe9c60 i386: Remove unused host_cpudef variable
c786127 x86/cpu: use FeatureWordArray to define filtered_features
599f2d2 i386: make 'hv-spinlocks' a regular uint32 property
12b504f i386: Fix signedness of hyperv_spinlock_attempts
51b09c1 i386: Don't print warning if phys-bits was set automatically
940f005 deprecate -mem-path fallback to anonymous RAM
b60560d hppa: Delete unused hppa_cpu_list() function
79ffefd numa: deprecate implict memory distribution between nodes
f7fc9c7 numa: deprecate 'mem' parameter of '-numa node' option
4760053 machine: show if CLI option '-numa node, mem' is supported in QAPI schema
c445aeb pc: fix possible NULL pointer dereference in pc_machine_get_device_memory_region_size()
08979e7 i386: Update new x86_apicid parsing rules with die_offset support
877b166 i386/cpu: Consolidate die-id validity in smp context
6ed8e31 hw/i386: Adjust nr_dies with configured smp_dies for PCMachine
5a48895 i386: Add die-level cpu topology to x86CPU on PCMachine
a468b59 vl.c: Replace smp global variables with smp machine properties
0f5c31d hw: Replace global smp variables with MachineState for all remaining archs
f5605f8 hw/arm: Replace global smp variables with machine smp properties
b6ed3fc hw/i386: Replace global smp variables with machine smp properties
90c875c hw/s390x: Replace global smp variables with machine smp properties
ed06b18 hw/riscv: Replace global smp variables with machine smp properties
e180e9c hw/ppc: Replace global smp variables with machine smp properties
99fae98 general: Replace global smp variables with smp machine properties
442604b machine: Refactor smp-related call chains to pass MachineState
b9ea53f hw/boards: Add struct CpuTopology to MachineState
=== OUTPUT BEGIN ===
1/42 Checking commit b9ea53f93d3b (hw/boards: Add struct CpuTopology to MachineState)
2/42 Checking commit 442604b2a8f7 (machine: Refactor smp-related call chains to pass MachineState)
3/42 Checking commit 99fae98b339d (general: Replace global smp variables with smp machine properties)
4/42 Checking commit e180e9c58736 (hw/ppc: Replace global smp variables with machine smp properties)
5/42 Checking commit ed06b18ac991 (hw/riscv: Replace global smp variables with machine smp properties)
6/42 Checking commit 90c875c003ca (hw/s390x: Replace global smp variables with machine smp properties)
7/42 Checking commit b6ed3fcd0057 (hw/i386: Replace global smp variables with machine smp properties)
8/42 Checking commit f5605f812d27 (hw/arm: Replace global smp variables with machine smp properties)
9/42 Checking commit 0f5c31d7d679 (hw: Replace global smp variables with MachineState for all remaining archs)
10/42 Checking commit a468b5935abe (vl.c: Replace smp global variables with smp machine properties)
11/42 Checking commit 5a48895d51e5 (i386: Add die-level cpu topology to x86CPU on PCMachine)
12/42 Checking commit 6ed8e31874e1 (hw/i386: Adjust nr_dies with configured smp_dies for PCMachine)
13/42 Checking commit 877b1661e86d (i386/cpu: Consolidate die-id validity in smp context)
14/42 Checking commit 08979e7e3e98 (i386: Update new x86_apicid parsing rules with die_offset support)
15/42 Checking commit c445aebbc23b (pc: fix possible NULL pointer dereference in pc_machine_get_device_memory_region_size())
16/42 Checking commit 4760053c2d35 (machine: show if CLI option '-numa node, mem' is supported in QAPI schema)
17/42 Checking commit f7fc9c769452 (numa: deprecate 'mem' parameter of '-numa node' option)
18/42 Checking commit 79ffefdf89eb (numa: deprecate implict memory distribution between nodes)
19/42 Checking commit b60560d9a1d6 (hppa: Delete unused hppa_cpu_list() function)
20/42 Checking commit 940f005a14e4 (deprecate -mem-path fallback to anonymous RAM)
21/42 Checking commit 51b09c151c24 (i386: Don't print warning if phys-bits was set automatically)
22/42 Checking commit 12b504ff090c (i386: Fix signedness of hyperv_spinlock_attempts)
23/42 Checking commit 599f2d213701 (i386: make 'hv-spinlocks' a regular uint32 property)
24/42 Checking commit c78612762a38 (x86/cpu: use FeatureWordArray to define filtered_features)
25/42 Checking commit efe9c60dcf40 (i386: Remove unused host_cpudef variable)
26/42 Checking commit e5521ebe5c06 (target/i386: Add CPUID.1F generation support for multi-dies PCMachine)
27/42 Checking commit 58066f711480 (machine: Refactor smp_parse() in vl.c as MachineClass::smp_parse())
28/42 Checking commit d9fca162e23f (vl.c: Add -smp, dies=* command line support and update doc)
29/42 Checking commit 5c64e254f4eb (qmp: Add deprecation information to query-machines)
30/42 Checking commit 21362596beb9 (i386: Introduce SnowRidge CPU model)
31/42 Checking commit 376457065ee8 (qmp: Add "alias-of" field to query-cpu-definitions)
32/42 Checking commit 86bad9a396fc (i386: Add x-force-features option for testing)
33/42 Checking commit 43e890fc16cb (i386: Get model-id from CPU object on "-cpu help")
34/42 Checking commit abe39dcbb8da (i386: Register versioned CPU models)
WARNING: line over 80 characters
#100: FILE: target/i386/cpu.c:1482:
+static const X86CPUVersionDefinition *x86_cpu_def_get_versions(X86CPUDefinition *def)
WARNING: Block comments use a leading /* on a separate line
#105: FILE: target/i386/cpu.c:1487:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#122: FILE: target/i386/cpu.c:1883:
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
WARNING: Block comments use a leading /* on a separate line
#134: FILE: target/i386/cpu.c:1942:
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
WARNING: Block comments use a leading /* on a separate line
#146: FILE: target/i386/cpu.c:2011:
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
WARNING: Block comments use a leading /* on a separate line
#158: FILE: target/i386/cpu.c:2086:
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
WARNING: Block comments use a leading /* on a separate line
#170: FILE: target/i386/cpu.c:2127:
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
WARNING: Block comments use a leading /* on a separate line
#182: FILE: target/i386/cpu.c:2170:
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
WARNING: Block comments use a leading /* on a separate line
#194: FILE: target/i386/cpu.c:2251:
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
WARNING: Block comments use a leading /* on a separate line
#206: FILE: target/i386/cpu.c:2294:
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
WARNING: Block comments use a leading /* on a separate line
#218: FILE: target/i386/cpu.c:2339:
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
WARNING: Block comments use a leading /* on a separate line
#230: FILE: target/i386/cpu.c:2422:
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
WARNING: Block comments use a leading /* on a separate line
#242: FILE: target/i386/cpu.c:2519:
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
WARNING: Block comments use a leading /* on a separate line
#254: FILE: target/i386/cpu.c:2626:
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
WARNING: Block comments use a leading /* on a separate line
#266: FILE: target/i386/cpu.c:3139:
+ .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
WARNING: line over 80 characters
#333: FILE: target/i386/cpu.c:4117:
+ for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) {
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#509:
new file mode 100644
ERROR: line over 90 characters
#552: FILE: tests/acceptance/x86_cpu_model_versions.py:39:
+ '%s.alias-of (%s) is not a valid CPU model name' % (c['name'], c['alias-of']))
ERROR: line over 90 characters
#555: FILE: tests/acceptance/x86_cpu_model_versions.py:42:
+ '%s.alias-of (%s) points to another alias' % (c['name'], c['alias-of']))
WARNING: line over 80 characters
#591: FILE: tests/acceptance/x86_cpu_model_versions.py:78:
+ """Check if pc-*-4.0 unversioned CPU model won't be reported as aliases"""
WARNING: line over 80 characters
#598: FILE: tests/acceptance/x86_cpu_model_versions.py:85:
+ cpus = dict((m['name'], m) for m in self.vm.command('query-cpu-definitions'))
WARNING: line over 80 characters
#601: FILE: tests/acceptance/x86_cpu_model_versions.py:88:
+ 'unversioned Cascadelake-Server CPU model must not be static')
total: 2 errors, 20 warnings, 550 lines checked
Patch 34/42 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
35/42 Checking commit 14bea5fba448 (i386: Define -IBRS, -noTSX, -IBRS versions of CPU models)
WARNING: Block comments use a leading /* on a separate line
#36: FILE: target/i386/cpu.c:1863:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#39: FILE: target/i386/cpu.c:1866:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#57: FILE: target/i386/cpu.c:1933:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#60: FILE: target/i386/cpu.c:1936:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#78: FILE: target/i386/cpu.c:2011:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#81: FILE: target/i386/cpu.c:2014:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#99: FILE: target/i386/cpu.c:2097:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#102: FILE: target/i386/cpu.c:2100:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#121: FILE: target/i386/cpu.c:2274:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#139: FILE: target/i386/cpu.c:2292:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#152: FILE: target/i386/cpu.c:2305:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#155: FILE: target/i386/cpu.c:2308:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#173: FILE: target/i386/cpu.c:2489:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#186: FILE: target/i386/cpu.c:2502:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#198: FILE: target/i386/cpu.c:2514:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#201: FILE: target/i386/cpu.c:2517:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#219: FILE: target/i386/cpu.c:2618:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#222: FILE: target/i386/cpu.c:2621:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#243: FILE: target/i386/cpu.c:2737:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#246: FILE: target/i386/cpu.c:2740:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#264: FILE: target/i386/cpu.c:3266:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#267: FILE: target/i386/cpu.c:3269:
+ { /* end of list */ }
total: 0 errors, 22 warnings, 240 lines checked
Patch 35/42 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
36/42 Checking commit 212584e2a174 (i386: Replace -noTSX, -IBRS, -IBPB CPU models with aliases)
37/42 Checking commit d14878267940 (i386: Make unversioned CPU models be aliases)
WARNING: line over 80 characters
#267: FILE: tests/acceptance/x86_cpu_model_versions.py:108:
+ """Check if unversioned CPU model is an alias pointing to right version"""
WARNING: line over 80 characters
#272: FILE: tests/acceptance/x86_cpu_model_versions.py:113:
+ cpus = dict((m['name'], m) for m in self.vm.command('query-cpu-definitions'))
WARNING: line over 80 characters
#275: FILE: tests/acceptance/x86_cpu_model_versions.py:116:
+ 'unversioned Cascadelake-Server CPU model must not be static')
ERROR: line over 90 characters
#276: FILE: tests/acceptance/x86_cpu_model_versions.py:117:
+ self.assertEquals(cpus['Cascadelake-Server'].get('alias-of'), 'Cascadelake-Server-v1',
WARNING: line over 80 characters
#277: FILE: tests/acceptance/x86_cpu_model_versions.py:118:
+ 'Cascadelake-Server must be an alias of Cascadelake-Server-v1')
WARNING: line over 80 characters
#369: FILE: tests/acceptance/x86_cpu_model_versions.py:210:
+ """Check if unversioned CPU model is an alias pointing to some version"""
WARNING: line over 80 characters
#374: FILE: tests/acceptance/x86_cpu_model_versions.py:215:
+ cpus = dict((m['name'], m) for m in self.vm.command('query-cpu-definitions'))
WARNING: line over 80 characters
#377: FILE: tests/acceptance/x86_cpu_model_versions.py:218:
+ 'unversioned Cascadelake-Server CPU model must not be static')
ERROR: line over 90 characters
#378: FILE: tests/acceptance/x86_cpu_model_versions.py:219:
+ self.assertTrue(re.match('Cascadelake-Server-v[0-9]+', cpus['Cascadelake-Server']['alias-of']),
WARNING: line over 80 characters
#379: FILE: tests/acceptance/x86_cpu_model_versions.py:220:
+ 'Cascadelake-Server must be an alias of versioned CPU model')
total: 2 errors, 8 warnings, 319 lines checked
Patch 37/42 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
38/42 Checking commit c270e116f3d0 (docs: Deprecate CPU model runnability guarantees)
39/42 Checking commit e7eed65410f0 (i386: Add Cascadelake-Server-v2 CPU model)
WARNING: Block comments use a leading /* on a separate line
#46: FILE: target/i386/cpu.c:2355:
+ { /* end of list */ }
WARNING: Block comments use a leading /* on a separate line
#49: FILE: target/i386/cpu.c:2358:
+ { /* end of list */ }
ERROR: line over 90 characters
#79: FILE: tests/acceptance/x86_cpu_model_versions.py:242:
+ vm.add_args('-cpu', 'Cascadelake-Server,x-force-features=on,check=off,enforce=off')
ERROR: line over 90 characters
#82: FILE: tests/acceptance/x86_cpu_model_versions.py:245:
+ 'pc-i440fx-4.1 + Cascadelake-Server should not have arch-capabilities')
ERROR: line over 90 characters
#87: FILE: tests/acceptance/x86_cpu_model_versions.py:250:
+ vm.add_args('-cpu', 'Cascadelake-Server,x-force-features=on,check=off,enforce=off')
ERROR: line over 90 characters
#90: FILE: tests/acceptance/x86_cpu_model_versions.py:253:
+ 'pc-i440fx-4.0 + Cascadelake-Server should not have arch-capabilities')
ERROR: line over 90 characters
#96: FILE: tests/acceptance/x86_cpu_model_versions.py:259:
+ vm.add_args('-cpu', 'Cascadelake-Server,x-force-features=on,check=off,enforce=off,+arch-capabilities')
ERROR: line over 90 characters
#99: FILE: tests/acceptance/x86_cpu_model_versions.py:262:
+ 'pc-i440fx-4.0 + Cascadelake-Server,+arch-capabilities should have arch-capabilities')
ERROR: line over 90 characters
#104: FILE: tests/acceptance/x86_cpu_model_versions.py:267:
+ vm.add_args('-cpu', 'Cascadelake-Server,x-force-features=on,check=off,enforce=off,-arch-capabilities')
ERROR: line over 90 characters
#107: FILE: tests/acceptance/x86_cpu_model_versions.py:270:
+ 'pc-i440fx-4.1 + Cascadelake-Server,-arch-capabilities should not have arch-capabilities')
ERROR: line over 90 characters
#113: FILE: tests/acceptance/x86_cpu_model_versions.py:276:
+ vm.add_args('-cpu', 'Cascadelake-Server-v1,x-force-features=on,check=off,enforce=off')
ERROR: line over 90 characters
#116: FILE: tests/acceptance/x86_cpu_model_versions.py:279:
+ 'pc-i440fx-4.1 + Cascadelake-Server-v1 should not have arch-capabilities')
ERROR: line over 90 characters
#121: FILE: tests/acceptance/x86_cpu_model_versions.py:284:
+ vm.add_args('-cpu', 'Cascadelake-Server-v2,x-force-features=on,check=off,enforce=off')
ERROR: line over 90 characters
#124: FILE: tests/acceptance/x86_cpu_model_versions.py:287:
+ 'pc-i440fx-4.1 + Cascadelake-Server-v1 should have arch-capabilities')
ERROR: line over 90 characters
#130: FILE: tests/acceptance/x86_cpu_model_versions.py:293:
+ vm.add_args('-cpu', 'Cascadelake-Server,x-force-features=on,check=off,enforce=off,+arch-capabilities')
ERROR: line over 90 characters
#133: FILE: tests/acceptance/x86_cpu_model_versions.py:296:
+ 'pc-i440fx-4.0 + Cascadelake-Server-v1,+arch-capabilities should have arch-capabilities')
ERROR: line over 90 characters
#138: FILE: tests/acceptance/x86_cpu_model_versions.py:301:
+ vm.add_args('-cpu', 'Cascadelake-Server-v2,x-force-features=on,check=off,enforce=off,-arch-capabilities')
ERROR: line over 90 characters
#141: FILE: tests/acceptance/x86_cpu_model_versions.py:304:
+ 'pc-i440fx-4.1 + Cascadelake-Server-v2,-arch-capabilities should not have arch-capabilities')
total: 16 errors, 2 warnings, 102 lines checked
Patch 39/42 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
40/42 Checking commit ba5a8f5a94ae (numa: Make deprecation warnings conditional on !qtest_enabled())
WARNING: line over 80 characters
#52: FILE: hw/core/numa.c:412:
+ warn_report("Default splitting of RAM between nodes is deprecated,"
total: 0 errors, 1 warnings, 33 lines checked
Patch 40/42 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
41/42 Checking commit 17f968fb74da (numa: allow memory-less nodes when using memdev as backend)
42/42 Checking commit 8222dd14a69f (tests: use -numa memdev option in tests instead of legacy 'mem' option)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190705221504.25166-1-ehabkost@redhat.com/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05
2019-07-05 22:14 [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 Eduardo Habkost
` (42 preceding siblings ...)
2019-07-06 6:46 ` [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 no-reply
@ 2019-07-08 9:26 ` Peter Maydell
2019-07-08 12:44 ` Igor Mammedov
43 siblings, 1 reply; 49+ messages in thread
From: Peter Maydell @ 2019-07-08 9:26 UTC (permalink / raw)
To: Eduardo Habkost; +Cc: Paolo Bonzini, QEMU Developers, Richard Henderson
On Fri, 5 Jul 2019 at 23:15, Eduardo Habkost <ehabkost@redhat.com> wrote:
>
> Changes v5 -> v6:
> * Rebase and solve conflicts with other pull requests
> (for the 4th time)
> * Included Cascadelake-Server-v2 update
>
> Changes v4 -> v5:
> * Rebase and solve conflicts with commit 374f63f6810a ("Merge remote-tracking
> branch 'remotes/armbru/tags/pull-monitor-2019-07-02-v2' into staging")
>
> Changes v3 -> v4:
> * Fix ppc64 "make check" failure
>
> Changes v2 -> v3:
> * Fix "make check" warnings (Igor Mammedov)
> * Fix conflicts of "hw/arm: Replace global smp variables with
> machine smp properties" with recent arm changes (Eduardo Habkost)
> * x86 versioned CPU models (Eduardo Habkost)
> * SnowRidge CPU model (Paul Lai)
> * Add deprecation information to query-machines (Eduardo Habkost)
>
> Changes v1 -> v2:
> * Fix s390x build failure
>
> The following changes since commit d2c5f91ca944aaade642624397e1853801bbc744:
>
> Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-pull-request' into staging (2019-07-05 16:16:15 +0100)
>
> are available in the Git repository at:
>
> git://github.com/ehabkost/qemu.git tags/machine-next-pull-request
>
> for you to fetch changes up to af135030e3405af5ce234a9f92cf8cc4e55fec96:
>
> tests: use -numa memdev option in tests instead of legacy 'mem' option (2019-07-05 17:12:45 -0300)
>
> ----------------------------------------------------------------
> Machine and x86 queue, 2019-07-05
>
> * CPU die topology support (Like Xu)
> * Deprecation of features (Igor Mammedov):
> * 'mem' parameter of '-numa node' option
> * implict memory distribution between NUMA nodes
> * deprecate -mem-path fallback to anonymous RAM
> * x86 versioned CPU models (Eduardo Habkost)
> * SnowRidge CPU model (Paul Lai)
> * Add deprecation information to query-machines (Eduardo Habkost)
> * Other i386 fixes
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/4.1
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05
2019-07-08 9:26 ` Peter Maydell
@ 2019-07-08 12:44 ` Igor Mammedov
0 siblings, 0 replies; 49+ messages in thread
From: Igor Mammedov @ 2019-07-08 12:44 UTC (permalink / raw)
To: Peter Maydell
Cc: Paolo Bonzini, Richard Henderson, Eduardo Habkost, QEMU Developers
On Mon, 8 Jul 2019 10:26:05 +0100
Peter Maydell <peter.maydell@linaro.org> wrote:
> On Fri, 5 Jul 2019 at 23:15, Eduardo Habkost <ehabkost@redhat.com> wrote:
> >
> > Changes v5 -> v6:
> > * Rebase and solve conflicts with other pull requests
> > (for the 4th time)
> > * Included Cascadelake-Server-v2 update
> >
> > Changes v4 -> v5:
> > * Rebase and solve conflicts with commit 374f63f6810a ("Merge remote-tracking
> > branch 'remotes/armbru/tags/pull-monitor-2019-07-02-v2' into staging")
> >
> > Changes v3 -> v4:
> > * Fix ppc64 "make check" failure
> >
> > Changes v2 -> v3:
> > * Fix "make check" warnings (Igor Mammedov)
> > * Fix conflicts of "hw/arm: Replace global smp variables with
> > machine smp properties" with recent arm changes (Eduardo Habkost)
> > * x86 versioned CPU models (Eduardo Habkost)
> > * SnowRidge CPU model (Paul Lai)
> > * Add deprecation information to query-machines (Eduardo Habkost)
> >
> > Changes v1 -> v2:
> > * Fix s390x build failure
> >
> > The following changes since commit d2c5f91ca944aaade642624397e1853801bbc744:
> >
> > Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-pull-request' into staging (2019-07-05 16:16:15 +0100)
> >
> > are available in the Git repository at:
> >
> > git://github.com/ehabkost/qemu.git tags/machine-next-pull-request
> >
> > for you to fetch changes up to af135030e3405af5ce234a9f92cf8cc4e55fec96:
> >
> > tests: use -numa memdev option in tests instead of legacy 'mem' option (2019-07-05 17:12:45 -0300)
> >
> > ----------------------------------------------------------------
> > Machine and x86 queue, 2019-07-05
> >
> > * CPU die topology support (Like Xu)
> > * Deprecation of features (Igor Mammedov):
> > * 'mem' parameter of '-numa node' option
> > * implict memory distribution between NUMA nodes
> > * deprecate -mem-path fallback to anonymous RAM
> > * x86 versioned CPU models (Eduardo Habkost)
> > * SnowRidge CPU model (Paul Lai)
> > * Add deprecation information to query-machines (Eduardo Habkost)
> > * Other i386 fixes
> >
>
>
> Applied, thanks.
>
> Please update the changelog at https://wiki.qemu.org/ChangeLog/4.1
> for any user-visible changes.
Updated "Miscellaneous" + "New deprecated options and features"
with NUMA related changes.
>
> -- PMM
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [Qemu-devel] [PULL v6 29/42] qmp: Add deprecation information to query-machines
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 29/42] qmp: Add deprecation information to query-machines Eduardo Habkost
@ 2019-07-08 13:29 ` Eric Blake
0 siblings, 0 replies; 49+ messages in thread
From: Eric Blake @ 2019-07-08 13:29 UTC (permalink / raw)
To: Eduardo Habkost, Peter Maydell, Paolo Bonzini, qemu-devel,
Marcel Apfelbaum, Richard Henderson, Markus Armbruster
[-- Attachment #1.1: Type: text/plain, Size: 1561 bytes --]
On 7/5/19 5:14 PM, Eduardo Habkost wrote:
> Export machine type deprecation status through the query-machines
> QMP command. With this, libvirt and management software will be
> able to show this information to users and/or suggest changes to
> VM configuration to avoid deprecated machines.
>
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> Message-Id: <20190608233447.27970-2-ehabkost@redhat.com>
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> ---
> qapi/machine.json | 7 ++++++-
> hw/core/machine-qmp-cmds.c | 1 +
> 2 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/qapi/machine.json b/qapi/machine.json
> index 78d34ef717..6db8a7e2ec 100644
> --- a/qapi/machine.json
> +++ b/qapi/machine.json
> @@ -321,12 +321,17 @@
> # @numa-mem-supported: true if '-numa node,mem' option is supported by
> # the machine type and false otherwise (since 4.1)
> #
> +# @deprecated: if true, the machine type is deprecated and may be removed
> +# in future versions of QEMU according to the QEMU deprecation
> +# policy (since 4.1.0)
Here, you used 'since 4.1.0'; in patch 31, you used merely 'since 4.1'.
It's not the first time we are inconsistent, but if someone wants a
trivial cleanup job, scrubbing the docs for all 3-element versions and
converting them to 2-element may be an interesting beginner's task.
--
Eric Blake, Principal Software Engineer
Red Hat, Inc. +1-919-301-3226
Virtualization: qemu.org | libvirt.org
[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [Qemu-devel] [PULL v6 10/42] vl.c: Replace smp global variables with smp machine properties
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 10/42] vl.c: Replace smp global variables with smp machine properties Eduardo Habkost
@ 2019-07-08 14:56 ` Laurent Desnogues
2019-07-08 20:40 ` Eduardo Habkost
0 siblings, 1 reply; 49+ messages in thread
From: Laurent Desnogues @ 2019-07-08 14:56 UTC (permalink / raw)
To: Eduardo Habkost, Like Xu
Cc: Peter Maydell, Richard Henderson, qemu-devel, Paolo Bonzini
Hi,
On Sat, Jul 6, 2019 at 12:40 AM Eduardo Habkost <ehabkost@redhat.com> wrote:
>
> From: Like Xu <like.xu@linux.intel.com>
>
> The global smp variables in vl.c are completely replaced with machine properties.
>
> Form this commit, the smp_cpus/smp_cores/smp_threads/max_cpus are deprecated
> and only machine properties within MachineState are fully applied and enabled.
Wouldn't it make sense to now remove the declarations in
include/sysemu/cpus.h and include/sysemu/sysemu.h?
Thanks,
Laurent
> Signed-off-by: Like Xu <like.xu@linux.intel.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> Message-Id: <20190518205428.90532-11-like.xu@linux.intel.com>
> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> ---
> vl.c | 53 ++++++++++++++++++++++++++---------------------------
> 1 file changed, 26 insertions(+), 27 deletions(-)
>
> diff --git a/vl.c b/vl.c
> index d657faec03..56aa221385 100644
> --- a/vl.c
> +++ b/vl.c
> @@ -163,10 +163,6 @@ static Chardev **serial_hds;
> Chardev *parallel_hds[MAX_PARALLEL_PORTS];
> int win2k_install_hack = 0;
> int singlestep = 0;
> -int smp_cpus;
> -unsigned int max_cpus;
> -int smp_cores = 1;
> -int smp_threads = 1;
> int acpi_enabled = 1;
> int no_hpet = 0;
> int fd_bootchk = 1;
> @@ -1265,8 +1261,9 @@ static void smp_parse(QemuOpts *opts)
> sockets = sockets > 0 ? sockets : 1;
> cpus = cores * threads * sockets;
> } else {
> - max_cpus = qemu_opt_get_number(opts, "maxcpus", cpus);
> - sockets = max_cpus / (cores * threads);
> + current_machine->smp.max_cpus =
> + qemu_opt_get_number(opts, "maxcpus", cpus);
> + sockets = current_machine->smp.max_cpus / (cores * threads);
> }
> } else if (cores == 0) {
> threads = threads > 0 ? threads : 1;
> @@ -1283,34 +1280,37 @@ static void smp_parse(QemuOpts *opts)
> exit(1);
> }
>
> - max_cpus = qemu_opt_get_number(opts, "maxcpus", cpus);
> + current_machine->smp.max_cpus =
> + qemu_opt_get_number(opts, "maxcpus", cpus);
>
> - if (max_cpus < cpus) {
> + if (current_machine->smp.max_cpus < cpus) {
> error_report("maxcpus must be equal to or greater than smp");
> exit(1);
> }
>
> - if (sockets * cores * threads > max_cpus) {
> + if (sockets * cores * threads > current_machine->smp.max_cpus) {
> error_report("cpu topology: "
> "sockets (%u) * cores (%u) * threads (%u) > "
> "maxcpus (%u)",
> - sockets, cores, threads, max_cpus);
> + sockets, cores, threads,
> + current_machine->smp.max_cpus);
> exit(1);
> }
>
> - if (sockets * cores * threads != max_cpus) {
> + if (sockets * cores * threads != current_machine->smp.max_cpus) {
> warn_report("Invalid CPU topology deprecated: "
> "sockets (%u) * cores (%u) * threads (%u) "
> "!= maxcpus (%u)",
> - sockets, cores, threads, max_cpus);
> + sockets, cores, threads,
> + current_machine->smp.max_cpus);
> }
>
> - smp_cpus = cpus;
> - smp_cores = cores;
> - smp_threads = threads;
> + current_machine->smp.cpus = cpus;
> + current_machine->smp.cores = cores;
> + current_machine->smp.threads = threads;
> }
>
> - if (smp_cpus > 1) {
> + if (current_machine->smp.cpus > 1) {
> Error *blocker = NULL;
> error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp");
> replay_add_blocker(blocker);
> @@ -4009,26 +4009,25 @@ int main(int argc, char **argv, char **envp)
> machine_class->default_cpus = machine_class->default_cpus ?: 1;
>
> /* default to machine_class->default_cpus */
> - smp_cpus = machine_class->default_cpus;
> - max_cpus = machine_class->default_cpus;
> + current_machine->smp.cpus = machine_class->default_cpus;
> + current_machine->smp.max_cpus = machine_class->default_cpus;
> + current_machine->smp.cores = 1;
> + current_machine->smp.threads = 1;
>
> smp_parse(qemu_opts_find(qemu_find_opts("smp-opts"), NULL));
>
> - current_machine->smp.cpus = smp_cpus;
> - current_machine->smp.max_cpus = max_cpus;
> - current_machine->smp.cores = smp_cores;
> - current_machine->smp.threads = smp_threads;
> -
> /* sanity-check smp_cpus and max_cpus against machine_class */
> - if (smp_cpus < machine_class->min_cpus) {
> + if (current_machine->smp.cpus < machine_class->min_cpus) {
> error_report("Invalid SMP CPUs %d. The min CPUs "
> - "supported by machine '%s' is %d", smp_cpus,
> + "supported by machine '%s' is %d",
> + current_machine->smp.cpus,
> machine_class->name, machine_class->min_cpus);
> exit(1);
> }
> - if (max_cpus > machine_class->max_cpus) {
> + if (current_machine->smp.max_cpus > machine_class->max_cpus) {
> error_report("Invalid SMP CPUs %d. The max CPUs "
> - "supported by machine '%s' is %d", max_cpus,
> + "supported by machine '%s' is %d",
> + current_machine->smp.max_cpus,
> machine_class->name, machine_class->max_cpus);
> exit(1);
> }
> --
> 2.18.0.rc1.1.g3f1ff2140
>
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [Qemu-devel] [PULL v6 10/42] vl.c: Replace smp global variables with smp machine properties
2019-07-08 14:56 ` Laurent Desnogues
@ 2019-07-08 20:40 ` Eduardo Habkost
0 siblings, 0 replies; 49+ messages in thread
From: Eduardo Habkost @ 2019-07-08 20:40 UTC (permalink / raw)
To: Laurent Desnogues
Cc: Peter Maydell, Like Xu, qemu-devel, Paolo Bonzini, Richard Henderson
On Mon, Jul 08, 2019 at 04:56:56PM +0200, Laurent Desnogues wrote:
> Hi,
>
> On Sat, Jul 6, 2019 at 12:40 AM Eduardo Habkost <ehabkost@redhat.com> wrote:
> >
> > From: Like Xu <like.xu@linux.intel.com>
> >
> > The global smp variables in vl.c are completely replaced with machine properties.
> >
> > Form this commit, the smp_cpus/smp_cores/smp_threads/max_cpus are deprecated
> > and only machine properties within MachineState are fully applied and enabled.
>
> Wouldn't it make sense to now remove the declarations in
> include/sysemu/cpus.h and include/sysemu/sysemu.h?
You're right. This will be done in a follow up patch.
--
Eduardo
^ permalink raw reply [flat|nested] 49+ messages in thread
end of thread, other threads:[~2019-07-08 20:42 UTC | newest]
Thread overview: 49+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-07-05 22:14 [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 01/42] hw/boards: Add struct CpuTopology to MachineState Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 02/42] machine: Refactor smp-related call chains to pass MachineState Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 03/42] general: Replace global smp variables with smp machine properties Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 04/42] hw/ppc: Replace global smp variables with machine smp properties Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 05/42] hw/riscv: " Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 06/42] hw/s390x: " Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 07/42] hw/i386: " Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 08/42] hw/arm: " Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 09/42] hw: Replace global smp variables with MachineState for all remaining archs Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 10/42] vl.c: Replace smp global variables with smp machine properties Eduardo Habkost
2019-07-08 14:56 ` Laurent Desnogues
2019-07-08 20:40 ` Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 11/42] i386: Add die-level cpu topology to x86CPU on PCMachine Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 12/42] hw/i386: Adjust nr_dies with configured smp_dies for PCMachine Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 13/42] i386/cpu: Consolidate die-id validity in smp context Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 14/42] i386: Update new x86_apicid parsing rules with die_offset support Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 15/42] pc: fix possible NULL pointer dereference in pc_machine_get_device_memory_region_size() Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 16/42] machine: show if CLI option '-numa node, mem' is supported in QAPI schema Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 17/42] numa: deprecate 'mem' parameter of '-numa node' option Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 18/42] numa: deprecate implict memory distribution between nodes Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 19/42] hppa: Delete unused hppa_cpu_list() function Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 20/42] deprecate -mem-path fallback to anonymous RAM Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 21/42] i386: Don't print warning if phys-bits was set automatically Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 22/42] i386: Fix signedness of hyperv_spinlock_attempts Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 23/42] i386: make 'hv-spinlocks' a regular uint32 property Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 24/42] x86/cpu: use FeatureWordArray to define filtered_features Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 25/42] i386: Remove unused host_cpudef variable Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 26/42] target/i386: Add CPUID.1F generation support for multi-dies PCMachine Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 27/42] machine: Refactor smp_parse() in vl.c as MachineClass::smp_parse() Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 28/42] vl.c: Add -smp, dies=* command line support and update doc Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 29/42] qmp: Add deprecation information to query-machines Eduardo Habkost
2019-07-08 13:29 ` Eric Blake
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 30/42] i386: Introduce SnowRidge CPU model Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 31/42] qmp: Add "alias-of" field to query-cpu-definitions Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 32/42] i386: Add x-force-features option for testing Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 33/42] i386: Get model-id from CPU object on "-cpu help" Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 34/42] i386: Register versioned CPU models Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 35/42] i386: Define -IBRS, -noTSX, -IBRS versions of " Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 36/42] i386: Replace -noTSX, -IBRS, -IBPB CPU models with aliases Eduardo Habkost
2019-07-05 22:14 ` [Qemu-devel] [PULL v6 37/42] i386: Make unversioned CPU models be aliases Eduardo Habkost
2019-07-05 22:15 ` [Qemu-devel] [PULL v6 38/42] docs: Deprecate CPU model runnability guarantees Eduardo Habkost
2019-07-05 22:15 ` [Qemu-devel] [PULL v6 39/42] i386: Add Cascadelake-Server-v2 CPU model Eduardo Habkost
2019-07-05 22:15 ` [Qemu-devel] [PULL v6 40/42] numa: Make deprecation warnings conditional on !qtest_enabled() Eduardo Habkost
2019-07-05 22:15 ` [Qemu-devel] [PULL v6 41/42] numa: allow memory-less nodes when using memdev as backend Eduardo Habkost
2019-07-05 22:15 ` [Qemu-devel] [PULL v6 42/42] tests: use -numa memdev option in tests instead of legacy 'mem' option Eduardo Habkost
2019-07-06 6:46 ` [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05 no-reply
2019-07-08 9:26 ` Peter Maydell
2019-07-08 12:44 ` Igor Mammedov
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