* [PATCH v2 0/4] Modular FIA
@ 2019-07-08 17:28 Lucas De Marchi
2019-07-08 17:28 ` [PATCH v2 1/4] drm/i915: make new intel_tc.c use uncore accessors Lucas De Marchi
` (6 more replies)
0 siblings, 7 replies; 15+ messages in thread
From: Lucas De Marchi @ 2019-07-08 17:28 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
v2:
- Fix sparse warning
- Do not try to make header self-contained
- Fix coding style while moving code
Anusha Srivatsa (1):
drm/i915: Add modular FIA
Lucas De Marchi (3):
drm/i915: make new intel_tc.c use uncore accessors
drm/i915: fix include order in intel_tc.*
drm/i915: move intel_ddi_set_fia_lane_count to intel_tc.c
drivers/gpu/drm/i915/display/intel_ddi.c | 49 ++-------
drivers/gpu/drm/i915/display/intel_tc.c | 125 ++++++++++++++++++-----
drivers/gpu/drm/i915/display/intel_tc.h | 7 +-
drivers/gpu/drm/i915/i915_reg.h | 13 ++-
drivers/gpu/drm/i915/intel_device_info.h | 1 +
drivers/gpu/drm/i915/intel_drv.h | 1 +
6 files changed, 121 insertions(+), 75 deletions(-)
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v2 1/4] drm/i915: make new intel_tc.c use uncore accessors
2019-07-08 17:28 [PATCH v2 0/4] Modular FIA Lucas De Marchi
@ 2019-07-08 17:28 ` Lucas De Marchi
2019-07-09 10:31 ` Imre Deak
2019-07-08 17:28 ` [PATCH v2 2/4] drm/i915: fix include order in intel_tc.* Lucas De Marchi
` (5 subsequent siblings)
6 siblings, 1 reply; 15+ messages in thread
From: Lucas De Marchi @ 2019-07-08 17:28 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
Let's make the just created intel_tc.c already follow the trend of using
i915 instead of dev_priv and calling the intel_uncore_*() functions.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_tc.c | 57 ++++++++++++++-----------
1 file changed, 31 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 53103a9aa8a7..1a9dd32fb0a5 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -24,11 +24,12 @@ static const char *tc_port_mode_name(enum tc_port_mode mode)
u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
{
- struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
- enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
+ struct intel_uncore *uncore = &i915->uncore;
u32 lane_mask;
- lane_mask = I915_READ(PORT_TX_DFLEXDPSP);
+ lane_mask = intel_uncore_read(uncore, PORT_TX_DFLEXDPSP);
WARN_ON(lane_mask == 0xffffffff);
@@ -38,7 +39,7 @@ u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
{
- struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
intel_wakeref_t wakeref;
u32 lane_mask;
@@ -46,7 +47,7 @@ int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
return 4;
lane_mask = 0;
- with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
+ with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
lane_mask = intel_tc_port_get_lane_mask(dig_port);
switch (lane_mask) {
@@ -89,12 +90,13 @@ static void tc_port_fixup_legacy_flag(struct intel_digital_port *dig_port,
static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port)
{
- struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
- enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
+ struct intel_uncore *uncore = &i915->uncore;
u32 mask = 0;
u32 val;
- val = I915_READ(PORT_TX_DFLEXDPSP);
+ val = intel_uncore_read(uncore, PORT_TX_DFLEXDPSP);
if (val == 0xffffffff) {
DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, nothing connected\n",
@@ -107,7 +109,7 @@ static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port)
if (val & TC_LIVE_STATE_TC(tc_port))
mask |= BIT(TC_PORT_DP_ALT);
- if (I915_READ(SDEISR) & SDE_TC_HOTPLUG_ICP(tc_port))
+ if (intel_uncore_read(uncore, SDEISR) & SDE_TC_HOTPLUG_ICP(tc_port))
mask |= BIT(TC_PORT_LEGACY);
/* The sink can be connected only in a single mode. */
@@ -119,11 +121,12 @@ static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port)
static bool icl_tc_phy_status_complete(struct intel_digital_port *dig_port)
{
- struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
- enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
+ struct intel_uncore *uncore = &i915->uncore;
u32 val;
- val = I915_READ(PORT_TX_DFLEXDPPMS);
+ val = intel_uncore_read(uncore, PORT_TX_DFLEXDPPMS);
if (val == 0xffffffff) {
DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, assuming not complete\n",
dig_port->tc_port_name);
@@ -136,11 +139,12 @@ static bool icl_tc_phy_status_complete(struct intel_digital_port *dig_port)
static bool icl_tc_phy_set_safe_mode(struct intel_digital_port *dig_port,
bool enable)
{
- struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
- enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
+ struct intel_uncore *uncore = &i915->uncore;
u32 val;
- val = I915_READ(PORT_TX_DFLEXDPCSSS);
+ val = intel_uncore_read(uncore, PORT_TX_DFLEXDPCSSS);
if (val == 0xffffffff) {
DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, can't set safe-mode to %s\n",
dig_port->tc_port_name,
@@ -153,7 +157,7 @@ static bool icl_tc_phy_set_safe_mode(struct intel_digital_port *dig_port,
if (!enable)
val |= DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
- I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
+ intel_uncore_write(uncore, PORT_TX_DFLEXDPCSSS, val);
if (enable && wait_for(!icl_tc_phy_status_complete(dig_port), 10))
DRM_DEBUG_KMS("Port %s: PHY complete clear timed out\n",
@@ -164,11 +168,12 @@ static bool icl_tc_phy_set_safe_mode(struct intel_digital_port *dig_port,
static bool icl_tc_phy_is_in_safe_mode(struct intel_digital_port *dig_port)
{
- struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
- enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
+ struct intel_uncore *uncore = &i915->uncore;
u32 val;
- val = I915_READ(PORT_TX_DFLEXDPCSSS);
+ val = intel_uncore_read(uncore, PORT_TX_DFLEXDPCSSS);
if (val == 0xffffffff) {
DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, assume safe mode\n",
dig_port->tc_port_name);
@@ -317,11 +322,11 @@ intel_tc_port_get_target_mode(struct intel_digital_port *dig_port)
static void intel_tc_port_reset_mode(struct intel_digital_port *dig_port,
int required_lanes)
{
- struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
enum tc_port_mode old_tc_mode = dig_port->tc_mode;
- intel_display_power_flush_work(dev_priv);
- WARN_ON(intel_display_power_is_enabled(dev_priv,
+ intel_display_power_flush_work(i915);
+ WARN_ON(intel_display_power_is_enabled(i915,
intel_aux_power_domain(dig_port)));
icl_tc_phy_disconnect(dig_port);
@@ -404,10 +409,10 @@ bool intel_tc_port_connected(struct intel_digital_port *dig_port)
static void __intel_tc_port_lock(struct intel_digital_port *dig_port,
int required_lanes)
{
- struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
intel_wakeref_t wakeref;
- wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
+ wakeref = intel_display_power_get(i915, POWER_DOMAIN_DISPLAY_CORE);
mutex_lock(&dig_port->tc_lock);
@@ -426,12 +431,12 @@ void intel_tc_port_lock(struct intel_digital_port *dig_port)
void intel_tc_port_unlock(struct intel_digital_port *dig_port)
{
- struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
intel_wakeref_t wakeref = fetch_and_zero(&dig_port->tc_lock_wakeref);
mutex_unlock(&dig_port->tc_lock);
- intel_display_power_put_async(dev_priv, POWER_DOMAIN_DISPLAY_CORE,
+ intel_display_power_put_async(i915, POWER_DOMAIN_DISPLAY_CORE,
wakeref);
}
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v2 2/4] drm/i915: fix include order in intel_tc.*
2019-07-08 17:28 [PATCH v2 0/4] Modular FIA Lucas De Marchi
2019-07-08 17:28 ` [PATCH v2 1/4] drm/i915: make new intel_tc.c use uncore accessors Lucas De Marchi
@ 2019-07-08 17:28 ` Lucas De Marchi
2019-07-09 10:49 ` Imre Deak
2019-07-08 17:28 ` [PATCH v2 3/4] drm/i915: move intel_ddi_set_fia_lane_count to intel_tc.c Lucas De Marchi
` (4 subsequent siblings)
6 siblings, 1 reply; 15+ messages in thread
From: Lucas De Marchi @ 2019-07-08 17:28 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
Make intel_tc.h the first include so we guarantee it's self-contained.
Sort the rest. Same principle applies for includes in the header.
v2: don't make intel_tc.h be the first include
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_tc.c | 2 +-
drivers/gpu/drm/i915/display/intel_tc.h | 5 +++--
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 1a9dd32fb0a5..0c969f6fd714 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -3,9 +3,9 @@
* Copyright © 2019 Intel Corporation
*/
+#include "i915_drv.h"
#include "intel_display.h"
#include "intel_dp_mst.h"
-#include "i915_drv.h"
#include "intel_tc.h"
static const char *tc_port_mode_name(enum tc_port_mode mode)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.h b/drivers/gpu/drm/i915/display/intel_tc.h
index 0d8411d4a91d..45ae30537b78 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.h
+++ b/drivers/gpu/drm/i915/display/intel_tc.h
@@ -6,10 +6,11 @@
#ifndef __INTEL_TC_H__
#define __INTEL_TC_H__
-#include <linux/types.h>
-#include <linux/mutex.h>
#include "intel_drv.h"
+#include <linux/mutex.h>
+#include <linux/types.h>
+
bool intel_tc_port_connected(struct intel_digital_port *dig_port);
u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port);
int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port);
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v2 3/4] drm/i915: move intel_ddi_set_fia_lane_count to intel_tc.c
2019-07-08 17:28 [PATCH v2 0/4] Modular FIA Lucas De Marchi
2019-07-08 17:28 ` [PATCH v2 1/4] drm/i915: make new intel_tc.c use uncore accessors Lucas De Marchi
2019-07-08 17:28 ` [PATCH v2 2/4] drm/i915: fix include order in intel_tc.* Lucas De Marchi
@ 2019-07-08 17:28 ` Lucas De Marchi
2019-07-08 17:28 ` [PATCH v2 4/4] drm/i915: Add modular FIA Lucas De Marchi
` (3 subsequent siblings)
6 siblings, 0 replies; 15+ messages in thread
From: Lucas De Marchi @ 2019-07-08 17:28 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
PORT_TX_DFLEXDPMLE1 is a FIA register so move it to intel_tc.c where we
access other FIA registers. In Tiger Lake we have multiple/modular FIAs
so it makes sense to start moving all access to their registers to a
common place.
While at it, make it clear that we will only ever call this function
for ports with TC phy. Previously we were relying on tc_mode being
TC_PORT_TBT_ALT for combo phy ports. However it's confusing since in
this same function we have checks for is_tc_port. Also, if we manage to
make each phy access only their own field, we may in future add them as
a union inside intel_digital_port.
v2: Fix coding style while moving the code
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 49 ++++--------------------
drivers/gpu/drm/i915/display/intel_tc.c | 33 ++++++++++++++++
drivers/gpu/drm/i915/display/intel_tc.h | 2 +
3 files changed, 42 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 30e48609db1d..ad638e7f27bb 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3594,37 +3594,6 @@ static void intel_ddi_update_pipe(struct intel_encoder *encoder,
intel_hdcp_disable(to_intel_connector(conn_state->connector));
}
-static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
- const struct intel_crtc_state *pipe_config,
- enum port port)
-{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
- enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
- u32 val = I915_READ(PORT_TX_DFLEXDPMLE1);
- bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
-
- WARN_ON(lane_reversal && dig_port->tc_mode != TC_PORT_LEGACY);
-
- val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
- switch (pipe_config->lane_count) {
- case 1:
- val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3(tc_port) :
- DFLEXDPMLE1_DPMLETC_ML0(tc_port);
- break;
- case 2:
- val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) :
- DFLEXDPMLE1_DPMLETC_ML1_0(tc_port);
- break;
- case 4:
- val |= DFLEXDPMLE1_DPMLETC_ML3_0(tc_port);
- break;
- default:
- MISSING_CASE(pipe_config->lane_count);
- }
- I915_WRITE(PORT_TX_DFLEXDPMLE1, val);
-}
-
static void
intel_ddi_update_prepare(struct intel_atomic_state *state,
struct intel_encoder *encoder,
@@ -3657,7 +3626,6 @@ intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
bool is_tc_port = intel_port_is_tc(dev_priv, encoder->port);
- enum port port = encoder->port;
if (is_tc_port)
intel_tc_port_get_link(dig_port, crtc_state->lane_count);
@@ -3666,18 +3634,15 @@ intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
intel_display_power_get(dev_priv,
intel_ddi_main_link_aux_domain(dig_port));
- if (IS_GEN9_LP(dev_priv))
+ if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT)
+ /*
+ * Program the lane count for static/dynamic connections on
+ * Type-C ports. Skip this step for TBT.
+ */
+ intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count);
+ else if (IS_GEN9_LP(dev_priv))
bxt_ddi_phy_set_lane_optim_mask(encoder,
crtc_state->lane_lat_optim_mask);
-
- /*
- * Program the lane count for static/dynamic connections on Type-C ports.
- * Skip this step for TBT.
- */
- if (dig_port->tc_mode == TC_PORT_TBT_ALT)
- return;
-
- intel_ddi_set_fia_lane_count(encoder, crtc_state, port);
}
static void
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 0c969f6fd714..f44ee4bfe7c8 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -67,6 +67,39 @@ int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
}
}
+void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
+ int required_lanes)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
+ bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
+ struct intel_uncore *uncore = &i915->uncore;
+ u32 val;
+
+ WARN_ON(lane_reversal && dig_port->tc_mode != TC_PORT_LEGACY);
+
+ val = intel_uncore_read(uncore, PORT_TX_DFLEXDPMLE1);
+ val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
+
+ switch (required_lanes) {
+ case 1:
+ val |= lane_reversal ? DFLEXDPMLE1_DPMLETC_ML3(tc_port) :
+ DFLEXDPMLE1_DPMLETC_ML0(tc_port);
+ break;
+ case 2:
+ val |= lane_reversal ? DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) :
+ DFLEXDPMLE1_DPMLETC_ML1_0(tc_port);
+ break;
+ case 4:
+ val |= DFLEXDPMLE1_DPMLETC_ML3_0(tc_port);
+ break;
+ default:
+ MISSING_CASE(required_lanes);
+ }
+
+ intel_uncore_write(uncore, PORT_TX_DFLEXDPMLE1, val);
+}
+
static void tc_port_fixup_legacy_flag(struct intel_digital_port *dig_port,
u32 live_status_mask)
{
diff --git a/drivers/gpu/drm/i915/display/intel_tc.h b/drivers/gpu/drm/i915/display/intel_tc.h
index 45ae30537b78..df4d97971354 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.h
+++ b/drivers/gpu/drm/i915/display/intel_tc.h
@@ -14,6 +14,8 @@
bool intel_tc_port_connected(struct intel_digital_port *dig_port);
u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port);
int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port);
+void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
+ int required_lanes);
void intel_tc_port_sanitize(struct intel_digital_port *dig_port);
void intel_tc_port_lock(struct intel_digital_port *dig_port);
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v2 4/4] drm/i915: Add modular FIA
2019-07-08 17:28 [PATCH v2 0/4] Modular FIA Lucas De Marchi
` (2 preceding siblings ...)
2019-07-08 17:28 ` [PATCH v2 3/4] drm/i915: move intel_ddi_set_fia_lane_count to intel_tc.c Lucas De Marchi
@ 2019-07-08 17:28 ` Lucas De Marchi
2019-07-10 18:33 ` Ville Syrjälä
2019-07-08 18:06 ` ✓ Fi.CI.BAT: success for Modular FIA (rev2) Patchwork
` (2 subsequent siblings)
6 siblings, 1 reply; 15+ messages in thread
From: Lucas De Marchi @ 2019-07-08 17:28 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Anusha Srivatsa <anusha.srivatsa@intel.com>
Some platforms may have Modular FIA. If Modular FIA is used in the SOC,
then Display Driver will access the additional instances of
FIA based on pre-assigned offset in GTTMADDR space.
Each Modular FIA instance has its own IOSF Sideband Port ID
and it houses only 2 Type-C Port. In SOC that has more than
two Type-C Ports, there are multiple instances of Modular FIA.
Gunit will need to use different destination ID when it access
different pair of Type-C Port.
The DFLEXDPSP register has Modular FIA bit starting on Tiger Lake. If
Modular FIA is used in the SOC, this register bit exists in all the
instances of Modular FIA. IOM FW is required to program only the MF bit
in first FIA instance that houses the Type-C Port 0 and Port 1, for
Display Driver to read from.
v2 (Lucas):
- Move all accesses to FIA to be contained in intel_tc.c, along with
display_fia that is now called tc_phy_fia
- Save the fia instance number on intel_digital_port, so we don't have
to query if modular FIA is used on every access
v3 (Lucas):
- Make function static
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_tc.c | 49 ++++++++++++++++++++----
drivers/gpu/drm/i915/i915_reg.h | 13 +++++--
drivers/gpu/drm/i915/intel_device_info.h | 1 +
drivers/gpu/drm/i915/intel_drv.h | 1 +
4 files changed, 52 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index f44ee4bfe7c8..671261b55d11 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -8,6 +8,12 @@
#include "intel_dp_mst.h"
#include "intel_tc.h"
+enum phy_fia {
+ FIA1,
+ FIA2,
+ FIA3,
+};
+
static const char *tc_port_mode_name(enum tc_port_mode mode)
{
static const char * const names[] = {
@@ -22,6 +28,24 @@ static const char *tc_port_mode_name(enum tc_port_mode mode)
return names[mode];
}
+static bool has_modular_fia(struct drm_i915_private *i915)
+{
+ if (!INTEL_INFO(i915)->display.has_modular_fia)
+ return false;
+
+ return intel_uncore_read(&i915->uncore,
+ PORT_TX_DFLEXDPSP(FIA1)) & MODULAR_FIA_MASK;
+}
+
+static enum phy_fia tc_port_to_fia(struct drm_i915_private *i915,
+ enum tc_port tc_port)
+{
+ if (!has_modular_fia(i915))
+ return FIA1;
+
+ return tc_port / 2;
+}
+
u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
@@ -29,7 +53,8 @@ u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
struct intel_uncore *uncore = &i915->uncore;
u32 lane_mask;
- lane_mask = intel_uncore_read(uncore, PORT_TX_DFLEXDPSP);
+ lane_mask = intel_uncore_read(uncore,
+ PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
WARN_ON(lane_mask == 0xffffffff);
@@ -78,7 +103,8 @@ void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
WARN_ON(lane_reversal && dig_port->tc_mode != TC_PORT_LEGACY);
- val = intel_uncore_read(uncore, PORT_TX_DFLEXDPMLE1);
+ val = intel_uncore_read(uncore,
+ PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia));
val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
switch (required_lanes) {
@@ -97,7 +123,8 @@ void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
MISSING_CASE(required_lanes);
}
- intel_uncore_write(uncore, PORT_TX_DFLEXDPMLE1, val);
+ intel_uncore_write(uncore,
+ PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia), val);
}
static void tc_port_fixup_legacy_flag(struct intel_digital_port *dig_port,
@@ -129,7 +156,8 @@ static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port)
u32 mask = 0;
u32 val;
- val = intel_uncore_read(uncore, PORT_TX_DFLEXDPSP);
+ val = intel_uncore_read(uncore,
+ PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
if (val == 0xffffffff) {
DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, nothing connected\n",
@@ -159,7 +187,8 @@ static bool icl_tc_phy_status_complete(struct intel_digital_port *dig_port)
struct intel_uncore *uncore = &i915->uncore;
u32 val;
- val = intel_uncore_read(uncore, PORT_TX_DFLEXDPPMS);
+ val = intel_uncore_read(uncore,
+ PORT_TX_DFLEXDPPMS(dig_port->tc_phy_fia));
if (val == 0xffffffff) {
DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, assuming not complete\n",
dig_port->tc_port_name);
@@ -177,7 +206,8 @@ static bool icl_tc_phy_set_safe_mode(struct intel_digital_port *dig_port,
struct intel_uncore *uncore = &i915->uncore;
u32 val;
- val = intel_uncore_read(uncore, PORT_TX_DFLEXDPCSSS);
+ val = intel_uncore_read(uncore,
+ PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia));
if (val == 0xffffffff) {
DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, can't set safe-mode to %s\n",
dig_port->tc_port_name,
@@ -190,7 +220,8 @@ static bool icl_tc_phy_set_safe_mode(struct intel_digital_port *dig_port,
if (!enable)
val |= DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
- intel_uncore_write(uncore, PORT_TX_DFLEXDPCSSS, val);
+ intel_uncore_write(uncore,
+ PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia), val);
if (enable && wait_for(!icl_tc_phy_status_complete(dig_port), 10))
DRM_DEBUG_KMS("Port %s: PHY complete clear timed out\n",
@@ -206,7 +237,8 @@ static bool icl_tc_phy_is_in_safe_mode(struct intel_digital_port *dig_port)
struct intel_uncore *uncore = &i915->uncore;
u32 val;
- val = intel_uncore_read(uncore, PORT_TX_DFLEXDPCSSS);
+ val = intel_uncore_read(uncore,
+ PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia));
if (val == 0xffffffff) {
DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, assume safe mode\n",
dig_port->tc_port_name);
@@ -503,4 +535,5 @@ void intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy)
mutex_init(&dig_port->tc_lock);
dig_port->tc_legacy_port = is_legacy;
dig_port->tc_link_refcount = 0;
+ dig_port->tc_phy_fia = tc_port_to_fia(i915, tc_port);
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5898f59e3dd7..74f2b31443fb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2203,9 +2203,13 @@ enum i915_power_well_id {
#define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
#define FIA1_BASE 0x163000
+#define FIA2_BASE 0x16E000
+#define FIA3_BASE 0x16F000
+#define _FIA(fia) _PICK((fia), FIA1_BASE, FIA2_BASE, FIA3_BASE)
+#define _MMIO_FIA(fia, off) _MMIO(_FIA(fia) + (off))
/* ICL PHY DFLEX registers */
-#define PORT_TX_DFLEXDPMLE1 _MMIO(FIA1_BASE + 0x008C0)
+#define PORT_TX_DFLEXDPMLE1(fia) _MMIO_FIA((fia), 0x008C0)
#define DFLEXDPMLE1_DPMLETC_MASK(tc_port) (0xf << (4 * (tc_port)))
#define DFLEXDPMLE1_DPMLETC_ML0(tc_port) (1 << (4 * (tc_port)))
#define DFLEXDPMLE1_DPMLETC_ML1_0(tc_port) (3 << (4 * (tc_port)))
@@ -11480,17 +11484,18 @@ enum skl_power_gate {
_ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
_ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
-#define PORT_TX_DFLEXDPSP _MMIO(FIA1_BASE + 0x008A0)
+#define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia), 0x008A0)
+#define MODULAR_FIA_MASK (1 << 4)
#define TC_LIVE_STATE_TBT(tc_port) (1 << ((tc_port) * 8 + 6))
#define TC_LIVE_STATE_TC(tc_port) (1 << ((tc_port) * 8 + 5))
#define DP_LANE_ASSIGNMENT_SHIFT(tc_port) ((tc_port) * 8)
#define DP_LANE_ASSIGNMENT_MASK(tc_port) (0xf << ((tc_port) * 8))
#define DP_LANE_ASSIGNMENT(tc_port, x) ((x) << ((tc_port) * 8))
-#define PORT_TX_DFLEXDPPMS _MMIO(FIA1_BASE + 0x00890)
+#define PORT_TX_DFLEXDPPMS(fia) _MMIO_FIA((fia), 0x00890)
#define DP_PHY_MODE_STATUS_COMPLETED(tc_port) (1 << (tc_port))
-#define PORT_TX_DFLEXDPCSSS _MMIO(FIA1_BASE + 0x00894)
+#define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894)
#define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port))
#endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index ddafc819bf30..e9dc86ed517b 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -136,6 +136,7 @@ enum intel_ppgtt_type {
func(has_gmch); \
func(has_hotplug); \
func(has_ipc); \
+ func(has_modular_fia); \
func(has_overlay); \
func(has_psr); \
func(overlay_needs_physical); \
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 24c63ed45c6f..7ea979c8c5f7 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1245,6 +1245,7 @@ struct intel_digital_port {
bool tc_legacy_port:1;
char tc_port_name[8];
enum tc_port_mode tc_mode;
+ u8 tc_phy_fia;
void (*write_infoframe)(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread
* ✓ Fi.CI.BAT: success for Modular FIA (rev2)
2019-07-08 17:28 [PATCH v2 0/4] Modular FIA Lucas De Marchi
` (3 preceding siblings ...)
2019-07-08 17:28 ` [PATCH v2 4/4] drm/i915: Add modular FIA Lucas De Marchi
@ 2019-07-08 18:06 ` Patchwork
2019-07-09 17:15 ` ✓ Fi.CI.BAT: success for Modular FIA (rev3) Patchwork
2019-07-10 7:11 ` ✓ Fi.CI.IGT: " Patchwork
6 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2019-07-08 18:06 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: Modular FIA (rev2)
URL : https://patchwork.freedesktop.org/series/63175/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6431 -> Patchwork_13569
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13569/
Known issues
------------
Here are the changes found in Patchwork_13569 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live_contexts:
- fi-skl-iommu: [PASS][1] -> [INCOMPLETE][2] ([fdo#111050])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/fi-skl-iommu/igt@i915_selftest@live_contexts.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13569/fi-skl-iommu/igt@i915_selftest@live_contexts.html
#### Possible fixes ####
* igt@gem_close_race@basic-process:
- fi-icl-u3: [DMESG-WARN][3] ([fdo#107724]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/fi-icl-u3/igt@gem_close_race@basic-process.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13569/fi-icl-u3/igt@gem_close_race@basic-process.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u3: [INCOMPLETE][5] ([fdo#107713] / [fdo#108569]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6431/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13569/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#111046 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111046
[fdo#111050]: https://bugs.freedesktop.org/show_bug.cgi?id=111050
Participating hosts (53 -> 47)
------------------------------
Additional (1): fi-pnv-d510
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_6431 -> Patchwork_13569
CI_DRM_6431: 9a40fb28e45261f2fc44a9b271c19faf1f071138 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5090: c6c75e11175baeb6b984e0cc13c6fbe2863a0794 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13569: 4d0275413be523094414d03d7f2f7026955b0bfe @ git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13569/build_32bit.log
CALL scripts/checksyscalls.sh
CALL scripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1287: recipe for target 'modules' failed
make: *** [modules] Error 2
== Linux commits ==
4d0275413be5 drm/i915: Add modular FIA
9718e39adc29 drm/i915: move intel_ddi_set_fia_lane_count to intel_tc.c
16541e8db1fc drm/i915: fix include order in intel_tc.*
29a4bcb3052b drm/i915: make new intel_tc.c use uncore accessors
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13569/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 1/4] drm/i915: make new intel_tc.c use uncore accessors
2019-07-08 17:28 ` [PATCH v2 1/4] drm/i915: make new intel_tc.c use uncore accessors Lucas De Marchi
@ 2019-07-09 10:31 ` Imre Deak
0 siblings, 0 replies; 15+ messages in thread
From: Imre Deak @ 2019-07-09 10:31 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Mon, Jul 08, 2019 at 10:28:12AM -0700, Lucas De Marchi wrote:
> Let's make the just created intel_tc.c already follow the trend of using
> i915 instead of dev_priv and calling the intel_uncore_*() functions.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
No changes since v1, so still r-b.
> ---
> drivers/gpu/drm/i915/display/intel_tc.c | 57 ++++++++++++++-----------
> 1 file changed, 31 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
> index 53103a9aa8a7..1a9dd32fb0a5 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -24,11 +24,12 @@ static const char *tc_port_mode_name(enum tc_port_mode mode)
>
> u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
> {
> - struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> - enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
> + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> + enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
> + struct intel_uncore *uncore = &i915->uncore;
> u32 lane_mask;
>
> - lane_mask = I915_READ(PORT_TX_DFLEXDPSP);
> + lane_mask = intel_uncore_read(uncore, PORT_TX_DFLEXDPSP);
>
> WARN_ON(lane_mask == 0xffffffff);
>
> @@ -38,7 +39,7 @@ u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
>
> int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
> {
> - struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> intel_wakeref_t wakeref;
> u32 lane_mask;
>
> @@ -46,7 +47,7 @@ int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
> return 4;
>
> lane_mask = 0;
> - with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
> + with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
> lane_mask = intel_tc_port_get_lane_mask(dig_port);
>
> switch (lane_mask) {
> @@ -89,12 +90,13 @@ static void tc_port_fixup_legacy_flag(struct intel_digital_port *dig_port,
>
> static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port)
> {
> - struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> - enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
> + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> + enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
> + struct intel_uncore *uncore = &i915->uncore;
> u32 mask = 0;
> u32 val;
>
> - val = I915_READ(PORT_TX_DFLEXDPSP);
> + val = intel_uncore_read(uncore, PORT_TX_DFLEXDPSP);
>
> if (val == 0xffffffff) {
> DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, nothing connected\n",
> @@ -107,7 +109,7 @@ static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port)
> if (val & TC_LIVE_STATE_TC(tc_port))
> mask |= BIT(TC_PORT_DP_ALT);
>
> - if (I915_READ(SDEISR) & SDE_TC_HOTPLUG_ICP(tc_port))
> + if (intel_uncore_read(uncore, SDEISR) & SDE_TC_HOTPLUG_ICP(tc_port))
> mask |= BIT(TC_PORT_LEGACY);
>
> /* The sink can be connected only in a single mode. */
> @@ -119,11 +121,12 @@ static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port)
>
> static bool icl_tc_phy_status_complete(struct intel_digital_port *dig_port)
> {
> - struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> - enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
> + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> + enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
> + struct intel_uncore *uncore = &i915->uncore;
> u32 val;
>
> - val = I915_READ(PORT_TX_DFLEXDPPMS);
> + val = intel_uncore_read(uncore, PORT_TX_DFLEXDPPMS);
> if (val == 0xffffffff) {
> DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, assuming not complete\n",
> dig_port->tc_port_name);
> @@ -136,11 +139,12 @@ static bool icl_tc_phy_status_complete(struct intel_digital_port *dig_port)
> static bool icl_tc_phy_set_safe_mode(struct intel_digital_port *dig_port,
> bool enable)
> {
> - struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> - enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
> + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> + enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
> + struct intel_uncore *uncore = &i915->uncore;
> u32 val;
>
> - val = I915_READ(PORT_TX_DFLEXDPCSSS);
> + val = intel_uncore_read(uncore, PORT_TX_DFLEXDPCSSS);
> if (val == 0xffffffff) {
> DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, can't set safe-mode to %s\n",
> dig_port->tc_port_name,
> @@ -153,7 +157,7 @@ static bool icl_tc_phy_set_safe_mode(struct intel_digital_port *dig_port,
> if (!enable)
> val |= DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
>
> - I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
> + intel_uncore_write(uncore, PORT_TX_DFLEXDPCSSS, val);
>
> if (enable && wait_for(!icl_tc_phy_status_complete(dig_port), 10))
> DRM_DEBUG_KMS("Port %s: PHY complete clear timed out\n",
> @@ -164,11 +168,12 @@ static bool icl_tc_phy_set_safe_mode(struct intel_digital_port *dig_port,
>
> static bool icl_tc_phy_is_in_safe_mode(struct intel_digital_port *dig_port)
> {
> - struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> - enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
> + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> + enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
> + struct intel_uncore *uncore = &i915->uncore;
> u32 val;
>
> - val = I915_READ(PORT_TX_DFLEXDPCSSS);
> + val = intel_uncore_read(uncore, PORT_TX_DFLEXDPCSSS);
> if (val == 0xffffffff) {
> DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, assume safe mode\n",
> dig_port->tc_port_name);
> @@ -317,11 +322,11 @@ intel_tc_port_get_target_mode(struct intel_digital_port *dig_port)
> static void intel_tc_port_reset_mode(struct intel_digital_port *dig_port,
> int required_lanes)
> {
> - struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> enum tc_port_mode old_tc_mode = dig_port->tc_mode;
>
> - intel_display_power_flush_work(dev_priv);
> - WARN_ON(intel_display_power_is_enabled(dev_priv,
> + intel_display_power_flush_work(i915);
> + WARN_ON(intel_display_power_is_enabled(i915,
> intel_aux_power_domain(dig_port)));
>
> icl_tc_phy_disconnect(dig_port);
> @@ -404,10 +409,10 @@ bool intel_tc_port_connected(struct intel_digital_port *dig_port)
> static void __intel_tc_port_lock(struct intel_digital_port *dig_port,
> int required_lanes)
> {
> - struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> intel_wakeref_t wakeref;
>
> - wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
> + wakeref = intel_display_power_get(i915, POWER_DOMAIN_DISPLAY_CORE);
>
> mutex_lock(&dig_port->tc_lock);
>
> @@ -426,12 +431,12 @@ void intel_tc_port_lock(struct intel_digital_port *dig_port)
>
> void intel_tc_port_unlock(struct intel_digital_port *dig_port)
> {
> - struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> intel_wakeref_t wakeref = fetch_and_zero(&dig_port->tc_lock_wakeref);
>
> mutex_unlock(&dig_port->tc_lock);
>
> - intel_display_power_put_async(dev_priv, POWER_DOMAIN_DISPLAY_CORE,
> + intel_display_power_put_async(i915, POWER_DOMAIN_DISPLAY_CORE,
> wakeref);
> }
>
> --
> 2.21.0
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 2/4] drm/i915: fix include order in intel_tc.*
2019-07-08 17:28 ` [PATCH v2 2/4] drm/i915: fix include order in intel_tc.* Lucas De Marchi
@ 2019-07-09 10:49 ` Imre Deak
2019-07-09 15:54 ` [PATCH v3 " Lucas De Marchi
0 siblings, 1 reply; 15+ messages in thread
From: Imre Deak @ 2019-07-09 10:49 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Mon, Jul 08, 2019 at 10:28:13AM -0700, Lucas De Marchi wrote:
> Make intel_tc.h the first include so we guarantee it's self-contained.
> Sort the rest. Same principle applies for includes in the header.
>
> v2: don't make intel_tc.h be the first include
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_tc.c | 2 +-
> drivers/gpu/drm/i915/display/intel_tc.h | 5 +++--
> 2 files changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
> index 1a9dd32fb0a5..0c969f6fd714 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -3,9 +3,9 @@
> * Copyright © 2019 Intel Corporation
> */
>
> +#include "i915_drv.h"
> #include "intel_display.h"
> #include "intel_dp_mst.h"
> -#include "i915_drv.h"
> #include "intel_tc.h"
>
> static const char *tc_port_mode_name(enum tc_port_mode mode)
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.h b/drivers/gpu/drm/i915/display/intel_tc.h
> index 0d8411d4a91d..45ae30537b78 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.h
> +++ b/drivers/gpu/drm/i915/display/intel_tc.h
> @@ -6,10 +6,11 @@
> #ifndef __INTEL_TC_H__
> #define __INTEL_TC_H__
>
> -#include <linux/types.h>
> -#include <linux/mutex.h>
> #include "intel_drv.h"
>
> +#include <linux/mutex.h>
> +#include <linux/types.h>
Sorry, I missed this in my v1 review: could you explain why you reorder
intel_drv.h wrt. linux/* includes? Everywhere else in i915 I see a more
generic->more specific order of includes, that is for instance:
#include <linux/*>
#include <drm/*>
#include "*"
Is that also to get a better guarantee that local includes are
self-contained? If so, that could also be done in a more uniform way
everywhere imo.
> +
> bool intel_tc_port_connected(struct intel_digital_port *dig_port);
> u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port);
> int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port);
> --
> 2.21.0
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 2/4] drm/i915: fix include order in intel_tc.*
2019-07-09 10:49 ` Imre Deak
@ 2019-07-09 15:54 ` Lucas De Marchi
2019-07-10 13:15 ` Imre Deak
0 siblings, 1 reply; 15+ messages in thread
From: Lucas De Marchi @ 2019-07-09 15:54 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
Separate local includes with a blank line and sort the groups
alphabetically.
v2: don't make intel_tc.h be the first include
v3: don't make local includes be included first
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_tc.c | 2 +-
drivers/gpu/drm/i915/display/intel_tc.h | 3 ++-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 1a9dd32fb0a5..0c969f6fd714 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -3,9 +3,9 @@
* Copyright © 2019 Intel Corporation
*/
+#include "i915_drv.h"
#include "intel_display.h"
#include "intel_dp_mst.h"
-#include "i915_drv.h"
#include "intel_tc.h"
static const char *tc_port_mode_name(enum tc_port_mode mode)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.h b/drivers/gpu/drm/i915/display/intel_tc.h
index 0d8411d4a91d..706c5bc050a5 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.h
+++ b/drivers/gpu/drm/i915/display/intel_tc.h
@@ -6,8 +6,9 @@
#ifndef __INTEL_TC_H__
#define __INTEL_TC_H__
-#include <linux/types.h>
#include <linux/mutex.h>
+#include <linux/types.h>
+
#include "intel_drv.h"
bool intel_tc_port_connected(struct intel_digital_port *dig_port);
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread
* ✓ Fi.CI.BAT: success for Modular FIA (rev3)
2019-07-08 17:28 [PATCH v2 0/4] Modular FIA Lucas De Marchi
` (4 preceding siblings ...)
2019-07-08 18:06 ` ✓ Fi.CI.BAT: success for Modular FIA (rev2) Patchwork
@ 2019-07-09 17:15 ` Patchwork
2019-07-10 7:11 ` ✓ Fi.CI.IGT: " Patchwork
6 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2019-07-09 17:15 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: Modular FIA (rev3)
URL : https://patchwork.freedesktop.org/series/63175/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6443 -> Patchwork_13585
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/
Known issues
------------
Here are the changes found in Patchwork_13585 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_create@basic-files:
- fi-icl-guc: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] / [fdo#109100])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/fi-icl-guc/igt@gem_ctx_create@basic-files.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/fi-icl-guc/igt@gem_ctx_create@basic-files.html
* igt@i915_selftest@live_blt:
- fi-icl-dsi: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/fi-icl-dsi/igt@i915_selftest@live_blt.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/fi-icl-dsi/igt@i915_selftest@live_blt.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][5] -> [FAIL][6] ([fdo#109485])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: [PASS][7] -> [FAIL][8] ([fdo#103167])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
#### Possible fixes ####
* igt@gem_mmap_gtt@basic-small-bo:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/fi-icl-u3/igt@gem_mmap_gtt@basic-small-bo.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/fi-icl-u3/igt@gem_mmap_gtt@basic-small-bo.html
* igt@i915_selftest@live_contexts:
- fi-skl-iommu: [INCOMPLETE][11] ([fdo#111050]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/fi-skl-iommu/igt@i915_selftest@live_contexts.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/fi-skl-iommu/igt@i915_selftest@live_contexts.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [FAIL][13] ([fdo#109635 ]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111050]: https://bugs.freedesktop.org/show_bug.cgi?id=111050
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
Participating hosts (51 -> 47)
------------------------------
Additional (1): fi-gdg-551
Missing (5): fi-kbl-soraka fi-byt-squawks fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_6443 -> Patchwork_13585
CI_DRM_6443: 0a6f3e30283594af78f45c777d28c4d55ace9e35 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5092: 2a66ae6626d5583240509f84117d1345a799b75a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13585: 6c698f3ecfafe1bdaf2926b97309135b7683923a @ git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/build_32bit.log
CALL scripts/checksyscalls.sh
CALL scripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1287: recipe for target 'modules' failed
make: *** [modules] Error 2
== Linux commits ==
6c698f3ecfaf drm/i915: Add modular FIA
63de0b2617be drm/i915: move intel_ddi_set_fia_lane_count to intel_tc.c
212ea21bb881 drm/i915: fix include order in intel_tc.*
20e9b516e3eb drm/i915: make new intel_tc.c use uncore accessors
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* ✓ Fi.CI.IGT: success for Modular FIA (rev3)
2019-07-08 17:28 [PATCH v2 0/4] Modular FIA Lucas De Marchi
` (5 preceding siblings ...)
2019-07-09 17:15 ` ✓ Fi.CI.BAT: success for Modular FIA (rev3) Patchwork
@ 2019-07-10 7:11 ` Patchwork
6 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2019-07-10 7:11 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: Modular FIA (rev3)
URL : https://patchwork.freedesktop.org/series/63175/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6443_full -> Patchwork_13585_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_13585_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_eio@unwedge-stress:
- shard-snb: [PASS][1] -> [FAIL][2] ([fdo#109661])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/shard-snb6/igt@gem_eio@unwedge-stress.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/shard-snb7/igt@gem_eio@unwedge-stress.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-kbl: [PASS][3] -> [INCOMPLETE][4] ([fdo#103665])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/shard-kbl6/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/shard-kbl6/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: [PASS][5] -> [FAIL][6] ([fdo#105363])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/shard-skl8/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render:
- shard-skl: [PASS][7] -> [FAIL][8] ([fdo#108040])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/shard-skl8/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/shard-skl3/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite:
- shard-iclb: [PASS][9] -> [FAIL][10] ([fdo#103167]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-apl: [PASS][11] -> [DMESG-WARN][12] ([fdo#108566]) +2 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/shard-apl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/shard-apl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [PASS][13] -> [FAIL][14] ([fdo#108145])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/shard-skl8/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/shard-skl3/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109642] / [fdo#111068])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/shard-iclb5/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_cursor_plane_move:
- shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109441])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/shard-iclb5/igt@kms_psr@psr2_cursor_plane_move.html
* igt@kms_setmode@basic:
- shard-kbl: [PASS][19] -> [FAIL][20] ([fdo#99912])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/shard-kbl1/igt@kms_setmode@basic.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/shard-kbl2/igt@kms_setmode@basic.html
* igt@perf@blocking:
- shard-skl: [PASS][21] -> [FAIL][22] ([fdo#110728])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/shard-skl9/igt@perf@blocking.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/shard-skl7/igt@perf@blocking.html
#### Possible fixes ####
* igt@i915_suspend@forcewake:
- shard-snb: [DMESG-WARN][23] ([fdo#102365]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/shard-snb5/igt@i915_suspend@forcewake.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/shard-snb6/igt@i915_suspend@forcewake.html
* igt@kms_color@pipe-c-ctm-green-to-red:
- shard-skl: [FAIL][25] ([fdo#107201]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/shard-skl2/igt@kms_color@pipe-c-ctm-green-to-red.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/shard-skl5/igt@kms_color@pipe-c-ctm-green-to-red.html
* igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled:
- shard-skl: [FAIL][27] ([fdo#103184] / [fdo#103232]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/shard-skl4/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/shard-skl4/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled.html
* igt@kms_flip@flip-vs-suspend:
- shard-snb: [INCOMPLETE][29] ([fdo#105411]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/shard-snb1/igt@kms_flip@flip-vs-suspend.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/shard-snb5/igt@kms_flip@flip-vs-suspend.html
- shard-glk: [INCOMPLETE][31] ([fdo#103359] / [k.org#198133]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/shard-glk4/igt@kms_flip@flip-vs-suspend.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/shard-glk1/igt@kms_flip@flip-vs-suspend.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-apl: [DMESG-WARN][33] ([fdo#108566]) -> [PASS][34] +2 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/shard-apl5/igt@kms_flip@flip-vs-suspend-interruptible.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_flip_tiling@flip-changes-tiling-yf:
- shard-skl: [FAIL][35] ([fdo#108228] / [fdo#108303]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/shard-skl4/igt@kms_flip_tiling@flip-changes-tiling-yf.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/shard-skl4/igt@kms_flip_tiling@flip-changes-tiling-yf.html
* igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack:
- shard-skl: [FAIL][37] ([fdo#108040]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/shard-skl10/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/shard-skl4/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html
* igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
- shard-iclb: [FAIL][39] ([fdo#103167]) -> [PASS][40] +6 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
- shard-hsw: [INCOMPLETE][41] ([fdo#103540]) -> [PASS][42] +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/shard-hsw5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/shard-hsw2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
- shard-snb: [SKIP][43] ([fdo#109271]) -> [PASS][44] +1 similar issue
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/shard-snb1/igt@kms_pipe_crc_basic@hang-read-crc-pipe-a.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/shard-snb5/igt@kms_pipe_crc_basic@hang-read-crc-pipe-a.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [FAIL][45] ([fdo#108145]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/shard-skl4/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [FAIL][47] ([fdo#108145] / [fdo#110403]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: [FAIL][49] ([fdo#103166]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/shard-iclb8/igt@kms_plane_lowres@pipe-a-tiling-x.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/shard-iclb8/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_psr@psr2_primary_page_flip:
- shard-iclb: [SKIP][51] ([fdo#109441]) -> [PASS][52] +1 similar issue
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6443/shard-iclb6/igt@kms_psr@psr2_primary_page_flip.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
[fdo#102365]: https://bugs.freedesktop.org/show_bug.cgi?id=102365
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#107201]: https://bugs.freedesktop.org/show_bug.cgi?id=107201
[fdo#108040]: https://bugs.freedesktop.org/show_bug.cgi?id=108040
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108228]: https://bugs.freedesktop.org/show_bug.cgi?id=108228
[fdo#108303]: https://bugs.freedesktop.org/show_bug.cgi?id=108303
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#109661]: https://bugs.freedesktop.org/show_bug.cgi?id=109661
[fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
[fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_6443 -> Patchwork_13585
CI_DRM_6443: 0a6f3e30283594af78f45c777d28c4d55ace9e35 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5092: 2a66ae6626d5583240509f84117d1345a799b75a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13585: 6c698f3ecfafe1bdaf2926b97309135b7683923a @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13585/
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 2/4] drm/i915: fix include order in intel_tc.*
2019-07-09 15:54 ` [PATCH v3 " Lucas De Marchi
@ 2019-07-10 13:15 ` Imre Deak
0 siblings, 0 replies; 15+ messages in thread
From: Imre Deak @ 2019-07-10 13:15 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Tue, Jul 09, 2019 at 08:54:03AM -0700, Lucas De Marchi wrote:
> Separate local includes with a blank line and sort the groups
> alphabetically.
>
> v2: don't make intel_tc.h be the first include
> v3: don't make local includes be included first
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_tc.c | 2 +-
> drivers/gpu/drm/i915/display/intel_tc.h | 3 ++-
> 2 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
> index 1a9dd32fb0a5..0c969f6fd714 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -3,9 +3,9 @@
> * Copyright © 2019 Intel Corporation
> */
>
> +#include "i915_drv.h"
> #include "intel_display.h"
> #include "intel_dp_mst.h"
> -#include "i915_drv.h"
> #include "intel_tc.h"
>
> static const char *tc_port_mode_name(enum tc_port_mode mode)
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.h b/drivers/gpu/drm/i915/display/intel_tc.h
> index 0d8411d4a91d..706c5bc050a5 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.h
> +++ b/drivers/gpu/drm/i915/display/intel_tc.h
> @@ -6,8 +6,9 @@
> #ifndef __INTEL_TC_H__
> #define __INTEL_TC_H__
>
> -#include <linux/types.h>
> #include <linux/mutex.h>
> +#include <linux/types.h>
> +
> #include "intel_drv.h"
>
> bool intel_tc_port_connected(struct intel_digital_port *dig_port);
> --
> 2.21.0
>
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 4/4] drm/i915: Add modular FIA
2019-07-08 17:28 ` [PATCH v2 4/4] drm/i915: Add modular FIA Lucas De Marchi
@ 2019-07-10 18:33 ` Ville Syrjälä
2019-07-10 19:22 ` Lucas De Marchi
0 siblings, 1 reply; 15+ messages in thread
From: Ville Syrjälä @ 2019-07-10 18:33 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Mon, Jul 08, 2019 at 10:28:15AM -0700, Lucas De Marchi wrote:
> From: Anusha Srivatsa <anusha.srivatsa@intel.com>
>
> Some platforms may have Modular FIA. If Modular FIA is used in the SOC,
> then Display Driver will access the additional instances of
> FIA based on pre-assigned offset in GTTMADDR space.
>
> Each Modular FIA instance has its own IOSF Sideband Port ID
> and it houses only 2 Type-C Port. In SOC that has more than
> two Type-C Ports, there are multiple instances of Modular FIA.
> Gunit will need to use different destination ID when it access
> different pair of Type-C Port.
>
> The DFLEXDPSP register has Modular FIA bit starting on Tiger Lake. If
> Modular FIA is used in the SOC, this register bit exists in all the
> instances of Modular FIA. IOM FW is required to program only the MF bit
> in first FIA instance that houses the Type-C Port 0 and Port 1, for
> Display Driver to read from.
>
> v2 (Lucas):
> - Move all accesses to FIA to be contained in intel_tc.c, along with
> display_fia that is now called tc_phy_fia
> - Save the fia instance number on intel_digital_port, so we don't have
> to query if modular FIA is used on every access
> v3 (Lucas):
> - Make function static
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_tc.c | 49 ++++++++++++++++++++----
> drivers/gpu/drm/i915/i915_reg.h | 13 +++++--
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> 4 files changed, 52 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
> index f44ee4bfe7c8..671261b55d11 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -8,6 +8,12 @@
> #include "intel_dp_mst.h"
> #include "intel_tc.h"
>
> +enum phy_fia {
> + FIA1,
> + FIA2,
> + FIA3,
> +};
> +
> static const char *tc_port_mode_name(enum tc_port_mode mode)
> {
> static const char * const names[] = {
> @@ -22,6 +28,24 @@ static const char *tc_port_mode_name(enum tc_port_mode mode)
> return names[mode];
> }
>
> +static bool has_modular_fia(struct drm_i915_private *i915)
> +{
> + if (!INTEL_INFO(i915)->display.has_modular_fia)
> + return false;
> +
> + return intel_uncore_read(&i915->uncore,
> + PORT_TX_DFLEXDPSP(FIA1)) & MODULAR_FIA_MASK;
> +}
> +
> +static enum phy_fia tc_port_to_fia(struct drm_i915_private *i915,
> + enum tc_port tc_port)
> +{
> + if (!has_modular_fia(i915))
> + return FIA1;
> +
> + return tc_port / 2;
> +}
> +
> u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
> {
> struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> @@ -29,7 +53,8 @@ u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
> struct intel_uncore *uncore = &i915->uncore;
> u32 lane_mask;
>
> - lane_mask = intel_uncore_read(uncore, PORT_TX_DFLEXDPSP);
> + lane_mask = intel_uncore_read(uncore,
> + PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
>
> WARN_ON(lane_mask == 0xffffffff);
>
> @@ -78,7 +103,8 @@ void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
>
> WARN_ON(lane_reversal && dig_port->tc_mode != TC_PORT_LEGACY);
>
> - val = intel_uncore_read(uncore, PORT_TX_DFLEXDPMLE1);
> + val = intel_uncore_read(uncore,
> + PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia));
> val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
>
> switch (required_lanes) {
> @@ -97,7 +123,8 @@ void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
> MISSING_CASE(required_lanes);
> }
>
> - intel_uncore_write(uncore, PORT_TX_DFLEXDPMLE1, val);
> + intel_uncore_write(uncore,
> + PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia), val);
> }
>
> static void tc_port_fixup_legacy_flag(struct intel_digital_port *dig_port,
> @@ -129,7 +156,8 @@ static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port)
> u32 mask = 0;
> u32 val;
>
> - val = intel_uncore_read(uncore, PORT_TX_DFLEXDPSP);
> + val = intel_uncore_read(uncore,
> + PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
>
> if (val == 0xffffffff) {
> DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, nothing connected\n",
> @@ -159,7 +187,8 @@ static bool icl_tc_phy_status_complete(struct intel_digital_port *dig_port)
> struct intel_uncore *uncore = &i915->uncore;
> u32 val;
>
> - val = intel_uncore_read(uncore, PORT_TX_DFLEXDPPMS);
> + val = intel_uncore_read(uncore,
> + PORT_TX_DFLEXDPPMS(dig_port->tc_phy_fia));
> if (val == 0xffffffff) {
> DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, assuming not complete\n",
> dig_port->tc_port_name);
> @@ -177,7 +206,8 @@ static bool icl_tc_phy_set_safe_mode(struct intel_digital_port *dig_port,
> struct intel_uncore *uncore = &i915->uncore;
> u32 val;
>
> - val = intel_uncore_read(uncore, PORT_TX_DFLEXDPCSSS);
> + val = intel_uncore_read(uncore,
> + PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia));
> if (val == 0xffffffff) {
> DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, can't set safe-mode to %s\n",
> dig_port->tc_port_name,
> @@ -190,7 +220,8 @@ static bool icl_tc_phy_set_safe_mode(struct intel_digital_port *dig_port,
> if (!enable)
> val |= DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
>
> - intel_uncore_write(uncore, PORT_TX_DFLEXDPCSSS, val);
> + intel_uncore_write(uncore,
> + PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia), val);
>
> if (enable && wait_for(!icl_tc_phy_status_complete(dig_port), 10))
> DRM_DEBUG_KMS("Port %s: PHY complete clear timed out\n",
> @@ -206,7 +237,8 @@ static bool icl_tc_phy_is_in_safe_mode(struct intel_digital_port *dig_port)
> struct intel_uncore *uncore = &i915->uncore;
> u32 val;
>
> - val = intel_uncore_read(uncore, PORT_TX_DFLEXDPCSSS);
> + val = intel_uncore_read(uncore,
> + PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia));
> if (val == 0xffffffff) {
> DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, assume safe mode\n",
> dig_port->tc_port_name);
> @@ -503,4 +535,5 @@ void intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy)
> mutex_init(&dig_port->tc_lock);
> dig_port->tc_legacy_port = is_legacy;
> dig_port->tc_link_refcount = 0;
> + dig_port->tc_phy_fia = tc_port_to_fia(i915, tc_port);
> }
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5898f59e3dd7..74f2b31443fb 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2203,9 +2203,13 @@ enum i915_power_well_id {
> #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
>
> #define FIA1_BASE 0x163000
> +#define FIA2_BASE 0x16E000
> +#define FIA3_BASE 0x16F000
> +#define _FIA(fia) _PICK((fia), FIA1_BASE, FIA2_BASE, FIA3_BASE)
> +#define _MMIO_FIA(fia, off) _MMIO(_FIA(fia) + (off))
>
> /* ICL PHY DFLEX registers */
> -#define PORT_TX_DFLEXDPMLE1 _MMIO(FIA1_BASE + 0x008C0)
> +#define PORT_TX_DFLEXDPMLE1(fia) _MMIO_FIA((fia), 0x008C0)
> #define DFLEXDPMLE1_DPMLETC_MASK(tc_port) (0xf << (4 * (tc_port)))
> #define DFLEXDPMLE1_DPMLETC_ML0(tc_port) (1 << (4 * (tc_port)))
> #define DFLEXDPMLE1_DPMLETC_ML1_0(tc_port) (3 << (4 * (tc_port)))
> @@ -11480,17 +11484,18 @@ enum skl_power_gate {
> _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
> _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
>
> -#define PORT_TX_DFLEXDPSP _MMIO(FIA1_BASE + 0x008A0)
> +#define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia), 0x008A0)
> +#define MODULAR_FIA_MASK (1 << 4)
> #define TC_LIVE_STATE_TBT(tc_port) (1 << ((tc_port) * 8 + 6))
> #define TC_LIVE_STATE_TC(tc_port) (1 << ((tc_port) * 8 + 5))
> #define DP_LANE_ASSIGNMENT_SHIFT(tc_port) ((tc_port) * 8)
> #define DP_LANE_ASSIGNMENT_MASK(tc_port) (0xf << ((tc_port) * 8))
> #define DP_LANE_ASSIGNMENT(tc_port, x) ((x) << ((tc_port) * 8))
>
> -#define PORT_TX_DFLEXDPPMS _MMIO(FIA1_BASE + 0x00890)
> +#define PORT_TX_DFLEXDPPMS(fia) _MMIO_FIA((fia), 0x00890)
> #define DP_PHY_MODE_STATUS_COMPLETED(tc_port) (1 << (tc_port))
>
> -#define PORT_TX_DFLEXDPCSSS _MMIO(FIA1_BASE + 0x00894)
> +#define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894)
> #define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port))
>
> #endif /* _I915_REG_H_ */
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index ddafc819bf30..e9dc86ed517b 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -136,6 +136,7 @@ enum intel_ppgtt_type {
> func(has_gmch); \
> func(has_hotplug); \
> func(has_ipc); \
> + func(has_modular_fia); \
> func(has_overlay); \
> func(has_psr); \
> func(overlay_needs_physical); \
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 24c63ed45c6f..7ea979c8c5f7 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1245,6 +1245,7 @@ struct intel_digital_port {
> bool tc_legacy_port:1;
> char tc_port_name[8];
> enum tc_port_mode tc_mode;
> + u8 tc_phy_fia;
enum phy_fia ?
I didn't read theough the nuts and bolts of the register offsets but the
approach seems OK to me.
Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> void (*write_infoframe)(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state,
> --
> 2.21.0
--
Ville Syrjälä
Intel
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* Re: [PATCH v2 4/4] drm/i915: Add modular FIA
2019-07-10 18:33 ` Ville Syrjälä
@ 2019-07-10 19:22 ` Lucas De Marchi
2019-07-10 19:31 ` Ville Syrjälä
0 siblings, 1 reply; 15+ messages in thread
From: Lucas De Marchi @ 2019-07-10 19:22 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Wed, Jul 10, 2019 at 09:33:39PM +0300, Ville Syrjälä wrote:
>On Mon, Jul 08, 2019 at 10:28:15AM -0700, Lucas De Marchi wrote:
>> From: Anusha Srivatsa <anusha.srivatsa@intel.com>
>>
>> Some platforms may have Modular FIA. If Modular FIA is used in the SOC,
>> then Display Driver will access the additional instances of
>> FIA based on pre-assigned offset in GTTMADDR space.
>>
>> Each Modular FIA instance has its own IOSF Sideband Port ID
>> and it houses only 2 Type-C Port. In SOC that has more than
>> two Type-C Ports, there are multiple instances of Modular FIA.
>> Gunit will need to use different destination ID when it access
>> different pair of Type-C Port.
>>
>> The DFLEXDPSP register has Modular FIA bit starting on Tiger Lake. If
>> Modular FIA is used in the SOC, this register bit exists in all the
>> instances of Modular FIA. IOM FW is required to program only the MF bit
>> in first FIA instance that houses the Type-C Port 0 and Port 1, for
>> Display Driver to read from.
>>
>> v2 (Lucas):
>> - Move all accesses to FIA to be contained in intel_tc.c, along with
>> display_fia that is now called tc_phy_fia
>> - Save the fia instance number on intel_digital_port, so we don't have
>> to query if modular FIA is used on every access
>> v3 (Lucas):
>> - Make function static
>>
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_tc.c | 49 ++++++++++++++++++++----
>> drivers/gpu/drm/i915/i915_reg.h | 13 +++++--
>> drivers/gpu/drm/i915/intel_device_info.h | 1 +
>> drivers/gpu/drm/i915/intel_drv.h | 1 +
>> 4 files changed, 52 insertions(+), 12 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
>> index f44ee4bfe7c8..671261b55d11 100644
>> --- a/drivers/gpu/drm/i915/display/intel_tc.c
>> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
>> @@ -8,6 +8,12 @@
>> #include "intel_dp_mst.h"
>> #include "intel_tc.h"
>>
>> +enum phy_fia {
>> + FIA1,
>> + FIA2,
>> + FIA3,
>> +};
>> +
>> static const char *tc_port_mode_name(enum tc_port_mode mode)
>> {
>> static const char * const names[] = {
>> @@ -22,6 +28,24 @@ static const char *tc_port_mode_name(enum tc_port_mode mode)
>> return names[mode];
>> }
>>
>> +static bool has_modular_fia(struct drm_i915_private *i915)
>> +{
>> + if (!INTEL_INFO(i915)->display.has_modular_fia)
>> + return false;
>> +
>> + return intel_uncore_read(&i915->uncore,
>> + PORT_TX_DFLEXDPSP(FIA1)) & MODULAR_FIA_MASK;
>> +}
>> +
>> +static enum phy_fia tc_port_to_fia(struct drm_i915_private *i915,
>> + enum tc_port tc_port)
>> +{
>> + if (!has_modular_fia(i915))
>> + return FIA1;
>> +
>> + return tc_port / 2;
>> +}
>> +
>> u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
>> {
>> struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
>> @@ -29,7 +53,8 @@ u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
>> struct intel_uncore *uncore = &i915->uncore;
>> u32 lane_mask;
>>
>> - lane_mask = intel_uncore_read(uncore, PORT_TX_DFLEXDPSP);
>> + lane_mask = intel_uncore_read(uncore,
>> + PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
>>
>> WARN_ON(lane_mask == 0xffffffff);
>>
>> @@ -78,7 +103,8 @@ void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
>>
>> WARN_ON(lane_reversal && dig_port->tc_mode != TC_PORT_LEGACY);
>>
>> - val = intel_uncore_read(uncore, PORT_TX_DFLEXDPMLE1);
>> + val = intel_uncore_read(uncore,
>> + PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia));
>> val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
>>
>> switch (required_lanes) {
>> @@ -97,7 +123,8 @@ void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
>> MISSING_CASE(required_lanes);
>> }
>>
>> - intel_uncore_write(uncore, PORT_TX_DFLEXDPMLE1, val);
>> + intel_uncore_write(uncore,
>> + PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia), val);
>> }
>>
>> static void tc_port_fixup_legacy_flag(struct intel_digital_port *dig_port,
>> @@ -129,7 +156,8 @@ static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port)
>> u32 mask = 0;
>> u32 val;
>>
>> - val = intel_uncore_read(uncore, PORT_TX_DFLEXDPSP);
>> + val = intel_uncore_read(uncore,
>> + PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
>>
>> if (val == 0xffffffff) {
>> DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, nothing connected\n",
>> @@ -159,7 +187,8 @@ static bool icl_tc_phy_status_complete(struct intel_digital_port *dig_port)
>> struct intel_uncore *uncore = &i915->uncore;
>> u32 val;
>>
>> - val = intel_uncore_read(uncore, PORT_TX_DFLEXDPPMS);
>> + val = intel_uncore_read(uncore,
>> + PORT_TX_DFLEXDPPMS(dig_port->tc_phy_fia));
>> if (val == 0xffffffff) {
>> DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, assuming not complete\n",
>> dig_port->tc_port_name);
>> @@ -177,7 +206,8 @@ static bool icl_tc_phy_set_safe_mode(struct intel_digital_port *dig_port,
>> struct intel_uncore *uncore = &i915->uncore;
>> u32 val;
>>
>> - val = intel_uncore_read(uncore, PORT_TX_DFLEXDPCSSS);
>> + val = intel_uncore_read(uncore,
>> + PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia));
>> if (val == 0xffffffff) {
>> DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, can't set safe-mode to %s\n",
>> dig_port->tc_port_name,
>> @@ -190,7 +220,8 @@ static bool icl_tc_phy_set_safe_mode(struct intel_digital_port *dig_port,
>> if (!enable)
>> val |= DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
>>
>> - intel_uncore_write(uncore, PORT_TX_DFLEXDPCSSS, val);
>> + intel_uncore_write(uncore,
>> + PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia), val);
>>
>> if (enable && wait_for(!icl_tc_phy_status_complete(dig_port), 10))
>> DRM_DEBUG_KMS("Port %s: PHY complete clear timed out\n",
>> @@ -206,7 +237,8 @@ static bool icl_tc_phy_is_in_safe_mode(struct intel_digital_port *dig_port)
>> struct intel_uncore *uncore = &i915->uncore;
>> u32 val;
>>
>> - val = intel_uncore_read(uncore, PORT_TX_DFLEXDPCSSS);
>> + val = intel_uncore_read(uncore,
>> + PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia));
>> if (val == 0xffffffff) {
>> DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, assume safe mode\n",
>> dig_port->tc_port_name);
>> @@ -503,4 +535,5 @@ void intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy)
>> mutex_init(&dig_port->tc_lock);
>> dig_port->tc_legacy_port = is_legacy;
>> dig_port->tc_link_refcount = 0;
>> + dig_port->tc_phy_fia = tc_port_to_fia(i915, tc_port);
>> }
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 5898f59e3dd7..74f2b31443fb 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -2203,9 +2203,13 @@ enum i915_power_well_id {
>> #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
>>
>> #define FIA1_BASE 0x163000
>> +#define FIA2_BASE 0x16E000
>> +#define FIA3_BASE 0x16F000
>> +#define _FIA(fia) _PICK((fia), FIA1_BASE, FIA2_BASE, FIA3_BASE)
>> +#define _MMIO_FIA(fia, off) _MMIO(_FIA(fia) + (off))
>>
>> /* ICL PHY DFLEX registers */
>> -#define PORT_TX_DFLEXDPMLE1 _MMIO(FIA1_BASE + 0x008C0)
>> +#define PORT_TX_DFLEXDPMLE1(fia) _MMIO_FIA((fia), 0x008C0)
>> #define DFLEXDPMLE1_DPMLETC_MASK(tc_port) (0xf << (4 * (tc_port)))
>> #define DFLEXDPMLE1_DPMLETC_ML0(tc_port) (1 << (4 * (tc_port)))
>> #define DFLEXDPMLE1_DPMLETC_ML1_0(tc_port) (3 << (4 * (tc_port)))
>> @@ -11480,17 +11484,18 @@ enum skl_power_gate {
>> _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
>> _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
>>
>> -#define PORT_TX_DFLEXDPSP _MMIO(FIA1_BASE + 0x008A0)
>> +#define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia), 0x008A0)
>> +#define MODULAR_FIA_MASK (1 << 4)
>> #define TC_LIVE_STATE_TBT(tc_port) (1 << ((tc_port) * 8 + 6))
>> #define TC_LIVE_STATE_TC(tc_port) (1 << ((tc_port) * 8 + 5))
>> #define DP_LANE_ASSIGNMENT_SHIFT(tc_port) ((tc_port) * 8)
>> #define DP_LANE_ASSIGNMENT_MASK(tc_port) (0xf << ((tc_port) * 8))
>> #define DP_LANE_ASSIGNMENT(tc_port, x) ((x) << ((tc_port) * 8))
>>
>> -#define PORT_TX_DFLEXDPPMS _MMIO(FIA1_BASE + 0x00890)
>> +#define PORT_TX_DFLEXDPPMS(fia) _MMIO_FIA((fia), 0x00890)
>> #define DP_PHY_MODE_STATUS_COMPLETED(tc_port) (1 << (tc_port))
>>
>> -#define PORT_TX_DFLEXDPCSSS _MMIO(FIA1_BASE + 0x00894)
>> +#define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894)
>> #define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port))
>>
>> #endif /* _I915_REG_H_ */
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
>> index ddafc819bf30..e9dc86ed517b 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.h
>> +++ b/drivers/gpu/drm/i915/intel_device_info.h
>> @@ -136,6 +136,7 @@ enum intel_ppgtt_type {
>> func(has_gmch); \
>> func(has_hotplug); \
>> func(has_ipc); \
>> + func(has_modular_fia); \
>> func(has_overlay); \
>> func(has_psr); \
>> func(overlay_needs_physical); \
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>> index 24c63ed45c6f..7ea979c8c5f7 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -1245,6 +1245,7 @@ struct intel_digital_port {
>> bool tc_legacy_port:1;
>> char tc_port_name[8];
>> enum tc_port_mode tc_mode;
>> + u8 tc_phy_fia;
>
>enum phy_fia ?
but then we need to move its definition to the header.
Is it really needed? The only place that should care about it is
intel_tc.c
Lucas De Marchi
>
>I didn't read theough the nuts and bolts of the register offsets but the
>approach seems OK to me.
>
>Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>>
>> void (*write_infoframe)(struct intel_encoder *encoder,
>> const struct intel_crtc_state *crtc_state,
>> --
>> 2.21.0
>
>--
>Ville Syrjälä
>Intel
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^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 4/4] drm/i915: Add modular FIA
2019-07-10 19:22 ` Lucas De Marchi
@ 2019-07-10 19:31 ` Ville Syrjälä
0 siblings, 0 replies; 15+ messages in thread
From: Ville Syrjälä @ 2019-07-10 19:31 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Wed, Jul 10, 2019 at 12:22:51PM -0700, Lucas De Marchi wrote:
> On Wed, Jul 10, 2019 at 09:33:39PM +0300, Ville Syrjälä wrote:
> >On Mon, Jul 08, 2019 at 10:28:15AM -0700, Lucas De Marchi wrote:
> >> From: Anusha Srivatsa <anusha.srivatsa@intel.com>
> >>
> >> Some platforms may have Modular FIA. If Modular FIA is used in the SOC,
> >> then Display Driver will access the additional instances of
> >> FIA based on pre-assigned offset in GTTMADDR space.
> >>
> >> Each Modular FIA instance has its own IOSF Sideband Port ID
> >> and it houses only 2 Type-C Port. In SOC that has more than
> >> two Type-C Ports, there are multiple instances of Modular FIA.
> >> Gunit will need to use different destination ID when it access
> >> different pair of Type-C Port.
> >>
> >> The DFLEXDPSP register has Modular FIA bit starting on Tiger Lake. If
> >> Modular FIA is used in the SOC, this register bit exists in all the
> >> instances of Modular FIA. IOM FW is required to program only the MF bit
> >> in first FIA instance that houses the Type-C Port 0 and Port 1, for
> >> Display Driver to read from.
> >>
> >> v2 (Lucas):
> >> - Move all accesses to FIA to be contained in intel_tc.c, along with
> >> display_fia that is now called tc_phy_fia
> >> - Save the fia instance number on intel_digital_port, so we don't have
> >> to query if modular FIA is used on every access
> >> v3 (Lucas):
> >> - Make function static
> >>
> >> Cc: Jani Nikula <jani.nikula@intel.com>
> >> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> >> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/display/intel_tc.c | 49 ++++++++++++++++++++----
> >> drivers/gpu/drm/i915/i915_reg.h | 13 +++++--
> >> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> >> drivers/gpu/drm/i915/intel_drv.h | 1 +
> >> 4 files changed, 52 insertions(+), 12 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
> >> index f44ee4bfe7c8..671261b55d11 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> >> @@ -8,6 +8,12 @@
> >> #include "intel_dp_mst.h"
> >> #include "intel_tc.h"
> >>
> >> +enum phy_fia {
> >> + FIA1,
> >> + FIA2,
> >> + FIA3,
> >> +};
> >> +
> >> static const char *tc_port_mode_name(enum tc_port_mode mode)
> >> {
> >> static const char * const names[] = {
> >> @@ -22,6 +28,24 @@ static const char *tc_port_mode_name(enum tc_port_mode mode)
> >> return names[mode];
> >> }
> >>
> >> +static bool has_modular_fia(struct drm_i915_private *i915)
> >> +{
> >> + if (!INTEL_INFO(i915)->display.has_modular_fia)
> >> + return false;
> >> +
> >> + return intel_uncore_read(&i915->uncore,
> >> + PORT_TX_DFLEXDPSP(FIA1)) & MODULAR_FIA_MASK;
> >> +}
> >> +
> >> +static enum phy_fia tc_port_to_fia(struct drm_i915_private *i915,
> >> + enum tc_port tc_port)
> >> +{
> >> + if (!has_modular_fia(i915))
> >> + return FIA1;
> >> +
> >> + return tc_port / 2;
> >> +}
> >> +
> >> u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
> >> {
> >> struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> >> @@ -29,7 +53,8 @@ u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
> >> struct intel_uncore *uncore = &i915->uncore;
> >> u32 lane_mask;
> >>
> >> - lane_mask = intel_uncore_read(uncore, PORT_TX_DFLEXDPSP);
> >> + lane_mask = intel_uncore_read(uncore,
> >> + PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
> >>
> >> WARN_ON(lane_mask == 0xffffffff);
> >>
> >> @@ -78,7 +103,8 @@ void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
> >>
> >> WARN_ON(lane_reversal && dig_port->tc_mode != TC_PORT_LEGACY);
> >>
> >> - val = intel_uncore_read(uncore, PORT_TX_DFLEXDPMLE1);
> >> + val = intel_uncore_read(uncore,
> >> + PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia));
> >> val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
> >>
> >> switch (required_lanes) {
> >> @@ -97,7 +123,8 @@ void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
> >> MISSING_CASE(required_lanes);
> >> }
> >>
> >> - intel_uncore_write(uncore, PORT_TX_DFLEXDPMLE1, val);
> >> + intel_uncore_write(uncore,
> >> + PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia), val);
> >> }
> >>
> >> static void tc_port_fixup_legacy_flag(struct intel_digital_port *dig_port,
> >> @@ -129,7 +156,8 @@ static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port)
> >> u32 mask = 0;
> >> u32 val;
> >>
> >> - val = intel_uncore_read(uncore, PORT_TX_DFLEXDPSP);
> >> + val = intel_uncore_read(uncore,
> >> + PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
> >>
> >> if (val == 0xffffffff) {
> >> DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, nothing connected\n",
> >> @@ -159,7 +187,8 @@ static bool icl_tc_phy_status_complete(struct intel_digital_port *dig_port)
> >> struct intel_uncore *uncore = &i915->uncore;
> >> u32 val;
> >>
> >> - val = intel_uncore_read(uncore, PORT_TX_DFLEXDPPMS);
> >> + val = intel_uncore_read(uncore,
> >> + PORT_TX_DFLEXDPPMS(dig_port->tc_phy_fia));
> >> if (val == 0xffffffff) {
> >> DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, assuming not complete\n",
> >> dig_port->tc_port_name);
> >> @@ -177,7 +206,8 @@ static bool icl_tc_phy_set_safe_mode(struct intel_digital_port *dig_port,
> >> struct intel_uncore *uncore = &i915->uncore;
> >> u32 val;
> >>
> >> - val = intel_uncore_read(uncore, PORT_TX_DFLEXDPCSSS);
> >> + val = intel_uncore_read(uncore,
> >> + PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia));
> >> if (val == 0xffffffff) {
> >> DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, can't set safe-mode to %s\n",
> >> dig_port->tc_port_name,
> >> @@ -190,7 +220,8 @@ static bool icl_tc_phy_set_safe_mode(struct intel_digital_port *dig_port,
> >> if (!enable)
> >> val |= DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
> >>
> >> - intel_uncore_write(uncore, PORT_TX_DFLEXDPCSSS, val);
> >> + intel_uncore_write(uncore,
> >> + PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia), val);
> >>
> >> if (enable && wait_for(!icl_tc_phy_status_complete(dig_port), 10))
> >> DRM_DEBUG_KMS("Port %s: PHY complete clear timed out\n",
> >> @@ -206,7 +237,8 @@ static bool icl_tc_phy_is_in_safe_mode(struct intel_digital_port *dig_port)
> >> struct intel_uncore *uncore = &i915->uncore;
> >> u32 val;
> >>
> >> - val = intel_uncore_read(uncore, PORT_TX_DFLEXDPCSSS);
> >> + val = intel_uncore_read(uncore,
> >> + PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia));
> >> if (val == 0xffffffff) {
> >> DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, assume safe mode\n",
> >> dig_port->tc_port_name);
> >> @@ -503,4 +535,5 @@ void intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy)
> >> mutex_init(&dig_port->tc_lock);
> >> dig_port->tc_legacy_port = is_legacy;
> >> dig_port->tc_link_refcount = 0;
> >> + dig_port->tc_phy_fia = tc_port_to_fia(i915, tc_port);
> >> }
> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> >> index 5898f59e3dd7..74f2b31443fb 100644
> >> --- a/drivers/gpu/drm/i915/i915_reg.h
> >> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> @@ -2203,9 +2203,13 @@ enum i915_power_well_id {
> >> #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
> >>
> >> #define FIA1_BASE 0x163000
> >> +#define FIA2_BASE 0x16E000
> >> +#define FIA3_BASE 0x16F000
> >> +#define _FIA(fia) _PICK((fia), FIA1_BASE, FIA2_BASE, FIA3_BASE)
> >> +#define _MMIO_FIA(fia, off) _MMIO(_FIA(fia) + (off))
> >>
> >> /* ICL PHY DFLEX registers */
> >> -#define PORT_TX_DFLEXDPMLE1 _MMIO(FIA1_BASE + 0x008C0)
> >> +#define PORT_TX_DFLEXDPMLE1(fia) _MMIO_FIA((fia), 0x008C0)
> >> #define DFLEXDPMLE1_DPMLETC_MASK(tc_port) (0xf << (4 * (tc_port)))
> >> #define DFLEXDPMLE1_DPMLETC_ML0(tc_port) (1 << (4 * (tc_port)))
> >> #define DFLEXDPMLE1_DPMLETC_ML1_0(tc_port) (3 << (4 * (tc_port)))
> >> @@ -11480,17 +11484,18 @@ enum skl_power_gate {
> >> _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
> >> _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
> >>
> >> -#define PORT_TX_DFLEXDPSP _MMIO(FIA1_BASE + 0x008A0)
> >> +#define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia), 0x008A0)
> >> +#define MODULAR_FIA_MASK (1 << 4)
> >> #define TC_LIVE_STATE_TBT(tc_port) (1 << ((tc_port) * 8 + 6))
> >> #define TC_LIVE_STATE_TC(tc_port) (1 << ((tc_port) * 8 + 5))
> >> #define DP_LANE_ASSIGNMENT_SHIFT(tc_port) ((tc_port) * 8)
> >> #define DP_LANE_ASSIGNMENT_MASK(tc_port) (0xf << ((tc_port) * 8))
> >> #define DP_LANE_ASSIGNMENT(tc_port, x) ((x) << ((tc_port) * 8))
> >>
> >> -#define PORT_TX_DFLEXDPPMS _MMIO(FIA1_BASE + 0x00890)
> >> +#define PORT_TX_DFLEXDPPMS(fia) _MMIO_FIA((fia), 0x00890)
> >> #define DP_PHY_MODE_STATUS_COMPLETED(tc_port) (1 << (tc_port))
> >>
> >> -#define PORT_TX_DFLEXDPCSSS _MMIO(FIA1_BASE + 0x00894)
> >> +#define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894)
> >> #define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port))
> >>
> >> #endif /* _I915_REG_H_ */
> >> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> >> index ddafc819bf30..e9dc86ed517b 100644
> >> --- a/drivers/gpu/drm/i915/intel_device_info.h
> >> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> >> @@ -136,6 +136,7 @@ enum intel_ppgtt_type {
> >> func(has_gmch); \
> >> func(has_hotplug); \
> >> func(has_ipc); \
> >> + func(has_modular_fia); \
> >> func(has_overlay); \
> >> func(has_psr); \
> >> func(overlay_needs_physical); \
> >> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> >> index 24c63ed45c6f..7ea979c8c5f7 100644
> >> --- a/drivers/gpu/drm/i915/intel_drv.h
> >> +++ b/drivers/gpu/drm/i915/intel_drv.h
> >> @@ -1245,6 +1245,7 @@ struct intel_digital_port {
> >> bool tc_legacy_port:1;
> >> char tc_port_name[8];
> >> enum tc_port_mode tc_mode;
> >> + u8 tc_phy_fia;
> >
> >enum phy_fia ?
>
> but then we need to move its definition to the header.
>
> Is it really needed? The only place that should care about it is
> intel_tc.c
I think if we have a name for it we should use it. Otherwise it's just
confusing, and someone is going to clean it up accidentally anyway.
>
> Lucas De Marchi
>
> >
> >I didn't read theough the nuts and bolts of the register offsets but the
> >approach seems OK to me.
> >
> >Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> >>
> >> void (*write_infoframe)(struct intel_encoder *encoder,
> >> const struct intel_crtc_state *crtc_state,
> >> --
> >> 2.21.0
> >
> >--
> >Ville Syrjälä
> >Intel
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2019-07-10 19:31 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-07-08 17:28 [PATCH v2 0/4] Modular FIA Lucas De Marchi
2019-07-08 17:28 ` [PATCH v2 1/4] drm/i915: make new intel_tc.c use uncore accessors Lucas De Marchi
2019-07-09 10:31 ` Imre Deak
2019-07-08 17:28 ` [PATCH v2 2/4] drm/i915: fix include order in intel_tc.* Lucas De Marchi
2019-07-09 10:49 ` Imre Deak
2019-07-09 15:54 ` [PATCH v3 " Lucas De Marchi
2019-07-10 13:15 ` Imre Deak
2019-07-08 17:28 ` [PATCH v2 3/4] drm/i915: move intel_ddi_set_fia_lane_count to intel_tc.c Lucas De Marchi
2019-07-08 17:28 ` [PATCH v2 4/4] drm/i915: Add modular FIA Lucas De Marchi
2019-07-10 18:33 ` Ville Syrjälä
2019-07-10 19:22 ` Lucas De Marchi
2019-07-10 19:31 ` Ville Syrjälä
2019-07-08 18:06 ` ✓ Fi.CI.BAT: success for Modular FIA (rev2) Patchwork
2019-07-09 17:15 ` ✓ Fi.CI.BAT: success for Modular FIA (rev3) Patchwork
2019-07-10 7:11 ` ✓ Fi.CI.IGT: " Patchwork
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