[PATCH v2 00/25] Initial support for Tiger Lake

[PATCH v2 00/25] Initial support for Tiger Lake

[Lucas De Marchi]

v2 of https://patchwork.freedesktop.org/series/62726/

  - Remove patches already reviewed
  - Remove modular FIA - it's handled in a separate series now
  - Add r-b on some patches
  - Handle comments on power well definitions

Patches are from their original authors, modified as per review on
upstream.

Daniele Ceraolo Spurio (1):
  drm/i915/tgl: add initial Tiger Lake definitions

Imre Deak (1):
  drm/i915/tgl: Add power well support

José Roberto de Souza (3):
  drm/i915/tgl: Check if pipe D is fused
  drm/i915/tgl: use TRANSCODER_EDP_VDSC on transcoder A
  drm/i915/tgl: Update DPLL clock reference register

Lucas De Marchi (5):
  drm/i915: Add 4th pipe and transcoder
  drm/i915/tgl: Add TGL PCI IDs
  drm/i915/tgl: apply Display WA #1178 to fix type C dongles
  drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization
  drm/i915/tgl: Add DPLL registers

Mahesh Kumar (8):
  drm/i915/tgl: Add TGL PCH detection in virtualized environment
  drm/i915/tgl: update ddi/tc clock_off bits
  drm/i915/tgl: Add gmbus gpio pin to port mapping
  drm/i915/tgl: port to ddc pin mapping
  drm/i915/tgl: select correct bit for port select
  drm/i915/tgl: extend intel_port_is_combophy/tc
  drm/i915/tgl: init ddi port A-C for Tiger Lake
  drm/i915/tgl: Add vbt value mapping for DDC Bus pin

Michel Thierry (1):
  x86/gpu: add TGL stolen memory support

Mika Kahola (1):
  drm/i915/tgl: Add power well to support 4th pipe

Radhakrishna Sripada (1):
  drm/i915/tgl: Introduce Tiger Lake PCH

Rodrigo Vivi (1):
  drm/i915/gen12: MBUS B credit change

Vandita Kulkarni (3):
  drm/i915/tgl: Add new pll ids
  drm/i915/tgl: Add pll manager
  drm/i915/tgl: Add additional ports for Tiger Lake

 arch/x86/kernel/early-quirks.c                |   1 +
 drivers/gpu/drm/i915/display/intel_bios.c     |  17 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      |  60 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  34 +-
 drivers/gpu/drm/i915/display/intel_display.h  |   8 +
 .../drm/i915/display/intel_display_power.c    | 525 +++++++++++++++++-
 .../drm/i915/display/intel_display_power.h    |  29 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  51 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h |  23 +-
 drivers/gpu/drm/i915/display/intel_gmbus.c    |  20 +-
 drivers/gpu/drm/i915/display/intel_hdmi.c     |  16 +-
 drivers/gpu/drm/i915/display/intel_vbt_defs.h |   3 +
 drivers/gpu/drm/i915/display/intel_vdsc.c     |   9 +-
 drivers/gpu/drm/i915/i915_debugfs.c           |   3 +-
 drivers/gpu/drm/i915/i915_drv.c               |   8 +-
 drivers/gpu/drm/i915/i915_drv.h               |   4 +
 drivers/gpu/drm/i915/i915_pci.c               |  30 +
 drivers/gpu/drm/i915/i915_reg.h               |  62 ++-
 drivers/gpu/drm/i915/intel_device_info.c      |   4 +
 drivers/gpu/drm/i915/intel_device_info.h      |   2 +
 include/drm/i915_component.h                  |   2 +-
 include/drm/i915_drm.h                        |   3 +
 include/drm/i915_pciids.h                     |  10 +
 23 files changed, 852 insertions(+), 72 deletions(-)

-- 
2.21.0

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[PATCH v2 01/25] drm/i915: Add 4th pipe and transcoder

[Lucas De Marchi]

Add pipe D and transcoder D to prepare for platforms having them.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
 drivers/gpu/drm/i915/display/intel_display.h | 4 ++++
 drivers/gpu/drm/i915/i915_reg.h              | 3 +++
 3 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f09eda75711a..d1148786920e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -17178,7 +17178,7 @@ struct intel_display_error_state {
 		u32 vtotal;
 		u32 vblank;
 		u32 vsync;
-	} transcoder[4];
+	} transcoder[5];
 };
 
 struct intel_display_error_state *
@@ -17189,6 +17189,7 @@ intel_display_capture_error_state(struct drm_i915_private *dev_priv)
 		TRANSCODER_A,
 		TRANSCODER_B,
 		TRANSCODER_C,
+		TRANSCODER_D,
 		TRANSCODER_EDP,
 	};
 	int i;
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index d296556ed82e..e781df463ffa 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -58,6 +58,7 @@ enum pipe {
 	PIPE_A = 0,
 	PIPE_B,
 	PIPE_C,
+	PIPE_D,
 	_PIPE_EDP,
 
 	I915_MAX_PIPES = _PIPE_EDP
@@ -75,6 +76,7 @@ enum transcoder {
 	TRANSCODER_A = PIPE_A,
 	TRANSCODER_B = PIPE_B,
 	TRANSCODER_C = PIPE_C,
+	TRANSCODER_D = PIPE_D,
 
 	/*
 	 * The following transcoders can map to any pipe, their enum value
@@ -98,6 +100,8 @@ static inline const char *transcoder_name(enum transcoder transcoder)
 		return "B";
 	case TRANSCODER_C:
 		return "C";
+	case TRANSCODER_D:
+		return "D";
 	case TRANSCODER_EDP:
 		return "EDP";
 	case TRANSCODER_DSI_A:
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5898f59e3dd7..31c6c168dde2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4217,6 +4217,7 @@ enum {
 #define TRANSCODER_B_OFFSET 0x61000
 #define TRANSCODER_C_OFFSET 0x62000
 #define CHV_TRANSCODER_C_OFFSET 0x63000
+#define TRANSCODER_D_OFFSET 0x63000
 #define TRANSCODER_EDP_OFFSET 0x6f000
 #define TRANSCODER_DSI0_OFFSET	0x6b000
 #define TRANSCODER_DSI1_OFFSET	0x6b800
@@ -5763,6 +5764,7 @@ enum {
 #define PIPE_A_OFFSET		0x70000
 #define PIPE_B_OFFSET		0x71000
 #define PIPE_C_OFFSET		0x72000
+#define PIPE_D_OFFSET		0x73000
 #define CHV_PIPE_C_OFFSET	0x74000
 /*
  * There's actually no pipe EDP. Some pipe registers have
@@ -9346,6 +9348,7 @@ enum skl_power_gate {
 #define _TRANS_DDI_FUNC_CTL_A		0x60400
 #define _TRANS_DDI_FUNC_CTL_B		0x61400
 #define _TRANS_DDI_FUNC_CTL_C		0x62400
+#define _TRANS_DDI_FUNC_CTL_D		0x63400
 #define _TRANS_DDI_FUNC_CTL_EDP		0x6F400
 #define _TRANS_DDI_FUNC_CTL_DSI0	0x6b400
 #define _TRANS_DDI_FUNC_CTL_DSI1	0x6bc00
-- 
2.21.0

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[PATCH v2 02/25] drm/i915/tgl: add initial Tiger Lake definitions

[Lucas De Marchi]

From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

Tiger Lake is a Intel® Processor containing Intel® HD Graphics.

This is just an initial Tiger Lake definition. PCI IDs, generic support
and new features coming in following patches.

v2 (Lucas):
  - Remove modular FIA - feature will be re-introduced in future

Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h          |  1 +
 drivers/gpu/drm/i915/i915_pci.c          | 29 ++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_device_info.c |  1 +
 drivers/gpu/drm/i915/intel_device_info.h |  2 ++
 4 files changed, 33 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e05bc3e1014d..2508b1222d2c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2088,6 +2088,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_CANNONLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
 #define IS_ICELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ICELAKE)
 #define IS_ELKHARTLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
+#define IS_TIGERLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
 				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
 #define IS_BDW_ULT(dev_priv) \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 94b588e0a1dd..da926485845d 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -765,6 +765,35 @@ static const struct intel_device_info intel_elkhartlake_info = {
 	.ppgtt_size = 36,
 };
 
+#define GEN12_FEATURES \
+	GEN11_FEATURES, \
+	GEN(12), \
+	.pipe_offsets = { \
+		[TRANSCODER_A] = PIPE_A_OFFSET, \
+		[TRANSCODER_B] = PIPE_B_OFFSET, \
+		[TRANSCODER_C] = PIPE_C_OFFSET, \
+		[TRANSCODER_D] = PIPE_D_OFFSET, \
+		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
+		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
+	}, \
+	.trans_offsets = { \
+		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
+		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
+		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
+		[TRANSCODER_D] = TRANSCODER_D_OFFSET, \
+		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
+		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
+	}
+
+static const struct intel_device_info intel_tigerlake_12_info = {
+	GEN12_FEATURES,
+	PLATFORM(INTEL_TIGERLAKE),
+	.num_pipes = 4,
+	.require_force_probe = 1,
+	.engine_mask =
+		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
+};
+
 #undef GEN
 #undef PLATFORM
 
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index e64536e1fd1b..e0d9a7a37994 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -58,6 +58,7 @@ static const char * const platform_names[] = {
 	PLATFORM_NAME(CANNONLAKE),
 	PLATFORM_NAME(ICELAKE),
 	PLATFORM_NAME(ELKHARTLAKE),
+	PLATFORM_NAME(TIGERLAKE),
 };
 #undef PLATFORM_NAME
 
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index ddafc819bf30..468582484758 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -78,6 +78,8 @@ enum intel_platform {
 	/* gen11 */
 	INTEL_ICELAKE,
 	INTEL_ELKHARTLAKE,
+	/* gen12 */
+	INTEL_TIGERLAKE,
 	INTEL_MAX_PLATFORMS
 };
 
-- 
2.21.0

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[PATCH v2 03/25] drm/i915/tgl: Introduce Tiger Lake PCH

[Lucas De Marchi]

From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>

Add the enum additions to TGP.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: David Weinehall <david.weinehall@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 4 ++++
 drivers/gpu/drm/i915/i915_drv.h | 3 +++
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 794c6814a6d0..bcedd2d8e267 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -224,6 +224,10 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
 		DRM_DEBUG_KMS("Found Mule Creek Canyon PCH\n");
 		WARN_ON(!IS_ELKHARTLAKE(dev_priv));
 		return PCH_MCC;
+	case INTEL_PCH_TGP_DEVICE_ID_TYPE:
+		DRM_DEBUG_KMS("Found Tiger Lake LP PCH\n");
+		WARN_ON(!IS_TIGERLAKE(dev_priv));
+		return PCH_TGP;
 	default:
 		return PCH_NONE;
 	}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2508b1222d2c..3248f9959227 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -536,6 +536,7 @@ enum intel_pch {
 	PCH_CNP,        /* Cannon/Comet Lake PCH */
 	PCH_ICP,	/* Ice Lake PCH */
 	PCH_MCC,        /* Mule Creek Canyon PCH */
+	PCH_TGP,	/* Tiger Lake PCH */
 };
 
 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
@@ -2322,6 +2323,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define INTEL_PCH_ICP_DEVICE_ID_TYPE		0x3480
 #define INTEL_PCH_MCC_DEVICE_ID_TYPE		0x4B00
 #define INTEL_PCH_MCC2_DEVICE_ID_TYPE		0x3880
+#define INTEL_PCH_TGP_DEVICE_ID_TYPE		0xA080
 #define INTEL_PCH_P2X_DEVICE_ID_TYPE		0x7100
 #define INTEL_PCH_P3X_DEVICE_ID_TYPE		0x7000
 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE		0x2900 /* qemu q35 has 2918 */
@@ -2329,6 +2331,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
 #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
 #define HAS_PCH_MCC(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MCC)
+#define HAS_PCH_TGP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_TGP)
 #define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
 #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
-- 
2.21.0

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[PATCH v2 04/25] drm/i915/tgl: Add TGL PCH detection in virtualized environment

[Lucas De Marchi]

From: Mahesh Kumar <mahesh1.kumar@intel.com>

Assume PCH_TGP when platform is TGL.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index bcedd2d8e267..926bbf2d169b 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -255,7 +255,9 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv)
 	 * make an educated guess as to which PCH is really there.
 	 */
 
-	if (IS_ELKHARTLAKE(dev_priv))
+	if (IS_TIGERLAKE(dev_priv))
+		id = INTEL_PCH_TGP_DEVICE_ID_TYPE;
+	else if (IS_ELKHARTLAKE(dev_priv))
 		id = INTEL_PCH_MCC_DEVICE_ID_TYPE;
 	else if (IS_ICELAKE(dev_priv))
 		id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
-- 
2.21.0

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[PATCH v2 05/25] drm/i915/tgl: Add TGL PCI IDs

[Lucas De Marchi]

Current list of PCI IDs for Tiger Lake.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c |  1 +
 include/drm/i915_pciids.h       | 10 ++++++++++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index da926485845d..e83c94cf2744 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -865,6 +865,7 @@ static const struct pci_device_id pciidlist[] = {
 	INTEL_CNL_IDS(&intel_cannonlake_info),
 	INTEL_ICL_11_IDS(&intel_icelake_11_info),
 	INTEL_EHL_IDS(&intel_elkhartlake_info),
+	INTEL_TGL_12_IDS(&intel_tigerlake_12_info),
 	{0, 0, 0}
 };
 MODULE_DEVICE_TABLE(pci, pciidlist);
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 6c342ac470c8..a70c982ddff9 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -583,4 +583,14 @@
 	INTEL_VGA_DEVICE(0x4551, info), \
 	INTEL_VGA_DEVICE(0x4541, info)
 
+/* TGL */
+#define INTEL_TGL_12_IDS(info) \
+	INTEL_VGA_DEVICE(0x9A49, info), \
+	INTEL_VGA_DEVICE(0x9A40, info), \
+	INTEL_VGA_DEVICE(0x9A59, info), \
+	INTEL_VGA_DEVICE(0x9A60, info), \
+	INTEL_VGA_DEVICE(0x9A68, info), \
+	INTEL_VGA_DEVICE(0x9A70, info), \
+	INTEL_VGA_DEVICE(0x9A78, info)
+
 #endif /* _I915_PCIIDS_H */
-- 
2.21.0

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[PATCH v2 06/25] x86/gpu: add TGL stolen memory support

[Lucas De Marchi]

From: Michel Thierry <michel.thierry@intel.com>

Reuse Gen11 stolen memory changes since Tiger Lake uses the same BSM
register (and format).

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 arch/x86/kernel/early-quirks.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 6c4f01540833..6f6b1d04dadf 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -549,6 +549,7 @@ static const struct pci_device_id intel_early_ids[] __initconst = {
 	INTEL_CNL_IDS(&gen9_early_ops),
 	INTEL_ICL_11_IDS(&gen11_early_ops),
 	INTEL_EHL_IDS(&gen11_early_ops),
+	INTEL_TGL_12_IDS(&gen11_early_ops),
 };
 
 struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0);
-- 
2.21.0

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[PATCH v2 07/25] drm/i915/tgl: Check if pipe D is fused

[Lucas De Marchi]

From: José Roberto de Souza <jose.souza@intel.com>

On Tiger Lake there is one more pipe - check if it's fused.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 1 +
 drivers/gpu/drm/i915/intel_device_info.c | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 31c6c168dde2..08dc71e4b818 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7633,6 +7633,7 @@ enum {
 #define SKL_DFSM_PIPE_A_DISABLE		(1 << 30)
 #define SKL_DFSM_PIPE_B_DISABLE		(1 << 21)
 #define SKL_DFSM_PIPE_C_DISABLE		(1 << 28)
+#define TGL_DFSM_PIPE_D_DISABLE		(1 << 22)
 
 #define SKL_DSSM				_MMIO(0x51004)
 #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz		(1 << 31)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index e0d9a7a37994..f99c9fd497b2 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -938,6 +938,9 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 			enabled_mask &= ~BIT(PIPE_B);
 		if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
 			enabled_mask &= ~BIT(PIPE_C);
+		if (INTEL_GEN(dev_priv) >= 12 &&
+		    (dfsm & TGL_DFSM_PIPE_D_DISABLE))
+			enabled_mask &= ~BIT(PIPE_D);
 
 		/*
 		 * At least one pipe should be enabled and if there are
-- 
2.21.0

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[PATCH v2 08/25] drm/i915/tgl: use TRANSCODER_EDP_VDSC on transcoder A

[Lucas De Marchi]

From: José Roberto de Souza <jose.souza@intel.com>

On TGL the special EDP transcoder is gone and it should be handled by
transcoder A.

v2 (Lucas):
  - Reuse POWER_DOMAIN_TRANSCODER_EDP_VDSC (suggested by Ville)
  - Use crtc->dev since new_crtc_state->state may be NULL on atomic
    commit (suggested by Maarten)

Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vdsc.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index ffec807b8960..c27912f552f0 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -459,16 +459,19 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
 enum intel_display_power_domain
 intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
 {
+	struct drm_i915_private *i915 = to_i915(crtc_state->base.crtc->dev);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 
 	/*
-	 * On ICL VDSC/joining for eDP transcoder uses a separate power well PW2
-	 * This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
+	 * On ICL+ VDSC/joining for eDP/A transcoder uses a separate power well
+	 * PW2. This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
 	 * For any other transcoder, VDSC/joining uses the power well associated
 	 * with the pipe/transcoder in use. Hence another reference on the
 	 * transcoder power domain will suffice.
 	 */
-	if (cpu_transcoder == TRANSCODER_EDP)
+	if (INTEL_GEN(i915) >= 12 && cpu_transcoder == TRANSCODER_A)
+		return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
+	else if (cpu_transcoder == TRANSCODER_EDP)
 		return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
 	else
 		return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
-- 
2.21.0

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[PATCH v2 09/25] drm/i915/tgl: Add power well support

[Lucas De Marchi]

From: Imre Deak <imre.deak@intel.com>

The patch adds the new power wells introduced by TGL (GEN 12) and
maps these to existing/new power domains. The changes for GEN 12 wrt
to GEN 11 are the following:

- Transcoder#EDP removed from power well#1 (Transcoder#A used in
  low-power mode instead)
- Transcoder#A is now backed by power well#1 instead of power well#3
- The DDI#B/C combo PHY ports are now backed by power well#1 instead of
  power well#3
- New power well#5 added for pipe#D functionality (TODO)
- 2 additional TC ports (TC#5-6) backed by power well#3, 2 port
  specific IO power wells (only for the non-TBT modes) and 4 port
  specific AUX power wells (2-2 for TBT vs. non-TBT modes)
- Power well#2 backs now VDSC/joining for pipe#A instead of VDSC for
  eDP and MIPI DSI (TODO)

On TGL Port DDI#C changed to be a combo PHY (native DP/HDMI) and
BSpec has renamed ports DDI#D-F to TC#4-6 respectively. Thus on ICL we
have the following naming for ports:

- Combo PHYs (native DP/HDMI):
  DDI#A-B
- TBT/non-TBT (TC altmode, native DP/HDMI) PHYs:
  DDI#C-F

Starting from GEN 12 we have the following naming for ports:
- Combo PHYs (native DP/HDMI):
  DDI#A-C
- TBT/non-TBT (TC altmode, native DP/HDMI) PHYs:
  DDI TC#1-6

To save some space in the power domain enum the power domain naming in
the driver reflects the above change, that is power domains TC#1-3 are
added as aliases for DDI#D-F and new power domains are reserved for
TC#4-6.

v2 (Lucas):
  - Separate out the bits and definitions for TGL from the ICL ones.
    Fix use of TRANSCODER_EDP_VDSC, that is now the correct define since
    we don't define TRANSCODER_A_VDSC power domain to spare a one bit in
    the bitmask (suggested by Ville)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 .../drm/i915/display/intel_display_power.c    | 480 +++++++++++++++++-
 .../drm/i915/display/intel_display_power.h    |  26 +-
 drivers/gpu/drm/i915/i915_debugfs.c           |   3 +-
 drivers/gpu/drm/i915/i915_reg.h               |  18 +
 4 files changed, 508 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 7437fc71d289..c3f42169831f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -23,8 +23,11 @@ bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
 					 enum i915_power_well_id power_well_id);
 
 const char *
-intel_display_power_domain_str(enum intel_display_power_domain domain)
+intel_display_power_domain_str(struct drm_i915_private *i915,
+			       enum intel_display_power_domain domain)
 {
+	bool ddi_tc_ports = IS_GEN(i915, 12);
+
 	switch (domain) {
 	case POWER_DOMAIN_DISPLAY_CORE:
 		return "DISPLAY_CORE";
@@ -61,11 +64,23 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
 	case POWER_DOMAIN_PORT_DDI_C_LANES:
 		return "PORT_DDI_C_LANES";
 	case POWER_DOMAIN_PORT_DDI_D_LANES:
-		return "PORT_DDI_D_LANES";
+		BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_D_LANES !=
+			     POWER_DOMAIN_PORT_DDI_TC1_LANES);
+		return ddi_tc_ports ? "PORT_DDI_TC1_LANES" : "PORT_DDI_D_LANES";
 	case POWER_DOMAIN_PORT_DDI_E_LANES:
-		return "PORT_DDI_E_LANES";
+		BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_E_LANES !=
+			     POWER_DOMAIN_PORT_DDI_TC2_LANES);
+		return ddi_tc_ports ? "PORT_DDI_TC2_LANES" : "PORT_DDI_E_LANES";
 	case POWER_DOMAIN_PORT_DDI_F_LANES:
-		return "PORT_DDI_F_LANES";
+		BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_F_LANES !=
+			     POWER_DOMAIN_PORT_DDI_TC3_LANES);
+		return ddi_tc_ports ? "PORT_DDI_TC3_LANES" : "PORT_DDI_F_LANES";
+	case POWER_DOMAIN_PORT_DDI_TC4_LANES:
+		return "PORT_DDI_TC4_LANES";
+	case POWER_DOMAIN_PORT_DDI_TC5_LANES:
+		return "PORT_DDI_TC5_LANES";
+	case POWER_DOMAIN_PORT_DDI_TC6_LANES:
+		return "PORT_DDI_TC6_LANES";
 	case POWER_DOMAIN_PORT_DDI_A_IO:
 		return "PORT_DDI_A_IO";
 	case POWER_DOMAIN_PORT_DDI_B_IO:
@@ -73,11 +88,23 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
 	case POWER_DOMAIN_PORT_DDI_C_IO:
 		return "PORT_DDI_C_IO";
 	case POWER_DOMAIN_PORT_DDI_D_IO:
-		return "PORT_DDI_D_IO";
+		BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_D_IO !=
+			     POWER_DOMAIN_PORT_DDI_TC1_IO);
+		return ddi_tc_ports ? "PORT_DDI_TC1_IO" : "PORT_DDI_D_IO";
 	case POWER_DOMAIN_PORT_DDI_E_IO:
-		return "PORT_DDI_E_IO";
+		BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_E_IO !=
+			     POWER_DOMAIN_PORT_DDI_TC2_IO);
+		return ddi_tc_ports ? "PORT_DDI_TC2_IO" : "PORT_DDI_E_IO";
 	case POWER_DOMAIN_PORT_DDI_F_IO:
-		return "PORT_DDI_F_IO";
+		BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_F_IO !=
+			     POWER_DOMAIN_PORT_DDI_TC3_IO);
+		return ddi_tc_ports ? "PORT_DDI_TC3_IO" : "PORT_DDI_F_IO";
+	case POWER_DOMAIN_PORT_DDI_TC4_IO:
+		return "PORT_DDI_TC4_IO";
+	case POWER_DOMAIN_PORT_DDI_TC5_IO:
+		return "PORT_DDI_TC5_IO";
+	case POWER_DOMAIN_PORT_DDI_TC6_IO:
+		return "PORT_DDI_TC6_IO";
 	case POWER_DOMAIN_PORT_DSI:
 		return "PORT_DSI";
 	case POWER_DOMAIN_PORT_CRT:
@@ -95,11 +122,20 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
 	case POWER_DOMAIN_AUX_C:
 		return "AUX_C";
 	case POWER_DOMAIN_AUX_D:
-		return "AUX_D";
+		BUILD_BUG_ON(POWER_DOMAIN_AUX_D != POWER_DOMAIN_AUX_TC1);
+		return ddi_tc_ports ? "AUX_TC1" : "AUX_D";
 	case POWER_DOMAIN_AUX_E:
-		return "AUX_E";
+		BUILD_BUG_ON(POWER_DOMAIN_AUX_E != POWER_DOMAIN_AUX_TC2);
+		return ddi_tc_ports ? "AUX_TC2" : "AUX_E";
 	case POWER_DOMAIN_AUX_F:
-		return "AUX_F";
+		BUILD_BUG_ON(POWER_DOMAIN_AUX_F != POWER_DOMAIN_AUX_TC3);
+		return ddi_tc_ports ? "AUX_TC3" : "AUX_F";
+	case POWER_DOMAIN_AUX_TC4:
+		return "AUX_TC4";
+	case POWER_DOMAIN_AUX_TC5:
+		return "AUX_TC5";
+	case POWER_DOMAIN_AUX_TC6:
+		return "AUX_TC6";
 	case POWER_DOMAIN_AUX_IO_A:
 		return "AUX_IO_A";
 	case POWER_DOMAIN_AUX_TBT1:
@@ -110,6 +146,10 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
 		return "AUX_TBT3";
 	case POWER_DOMAIN_AUX_TBT4:
 		return "AUX_TBT4";
+	case POWER_DOMAIN_AUX_TBT5:
+		return "AUX_TBT5";
+	case POWER_DOMAIN_AUX_TBT6:
+		return "AUX_TBT6";
 	case POWER_DOMAIN_GMBUS:
 		return "GMBUS";
 	case POWER_DOMAIN_INIT:
@@ -1664,12 +1704,15 @@ __async_put_domains_state_ok(struct i915_power_domains *power_domains)
 static void print_power_domains(struct i915_power_domains *power_domains,
 				const char *prefix, u64 mask)
 {
+	struct drm_i915_private *i915 =
+		container_of(power_domains, struct drm_i915_private,
+			     power_domains);
 	enum intel_display_power_domain domain;
 
 	DRM_DEBUG_DRIVER("%s (%lu):\n", prefix, hweight64(mask));
 	for_each_power_domain(domain, mask)
 		DRM_DEBUG_DRIVER("%s use_count %d\n",
-				 intel_display_power_domain_str(domain),
+				 intel_display_power_domain_str(i915, domain),
 				 power_domains->domain_use_count[domain]);
 }
 
@@ -1839,7 +1882,7 @@ __intel_display_power_put_domain(struct drm_i915_private *dev_priv,
 {
 	struct i915_power_domains *power_domains;
 	struct i915_power_well *power_well;
-	const char *name = intel_display_power_domain_str(domain);
+	const char *name = intel_display_power_domain_str(dev_priv, domain);
 
 	power_domains = &dev_priv->power_domains;
 
@@ -2408,11 +2451,11 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
  * - DDI_A
  * - FBC
  */
+/* TODO: TGL_PW_5_POWER_DOMAINS: PIPE_D */
 #define ICL_PW_4_POWER_DOMAINS (			\
 	BIT_ULL(POWER_DOMAIN_PIPE_C) |			\
 	BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |	\
 	BIT_ULL(POWER_DOMAIN_INIT))
-	/* VDSC/joining */
 #define ICL_PW_3_POWER_DOMAINS (			\
 	ICL_PW_4_POWER_DOMAINS |			\
 	BIT_ULL(POWER_DOMAIN_PIPE_B) |			\
@@ -2448,16 +2491,17 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
 	 */
 #define ICL_PW_2_POWER_DOMAINS (			\
 	ICL_PW_3_POWER_DOMAINS |			\
-	BIT_ULL(POWER_DOMAIN_TRANSCODER_EDP_VDSC) |		\
+	BIT_ULL(POWER_DOMAIN_TRANSCODER_EDP_VDSC) |	\
 	BIT_ULL(POWER_DOMAIN_INIT))
 	/*
 	 * - KVMR (HW control)
+	 * - GEN 11: eDP/DSI VDSC
 	 */
 #define ICL_DISPLAY_DC_OFF_POWER_DOMAINS (		\
 	ICL_PW_2_POWER_DOMAINS |			\
 	BIT_ULL(POWER_DOMAIN_MODESET) |			\
 	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
-	BIT_ULL(POWER_DOMAIN_DPLL_DC_OFF) |			\
+	BIT_ULL(POWER_DOMAIN_DPLL_DC_OFF) |		\
 	BIT_ULL(POWER_DOMAIN_INIT))
 
 #define ICL_DDI_IO_A_POWER_DOMAINS (			\
@@ -2495,6 +2539,87 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
 #define ICL_AUX_TBT4_IO_POWER_DOMAINS (			\
 	BIT_ULL(POWER_DOMAIN_AUX_TBT4))
 
+#define TGL_PW_4_POWER_DOMAINS (			\
+	BIT_ULL(POWER_DOMAIN_PIPE_C) |			\
+	BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |	\
+	BIT_ULL(POWER_DOMAIN_INIT))
+
+#define TGL_PW_3_POWER_DOMAINS (			\
+	TGL_PW_4_POWER_DOMAINS |			\
+	BIT_ULL(POWER_DOMAIN_PIPE_B) |			\
+	BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |		\
+	BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |		\
+	/* TODO: TRANSCODER_D */			\
+	BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |	\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_LANES) |	\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_IO) |		\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC2_LANES) |	\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC2_IO) |		\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC3_LANES) |	\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC3_IO) |		\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC4_LANES) |	\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC4_IO) |		\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC5_LANES) |	\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC5_IO) |		\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC6_LANES) |	\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC6_IO) |		\
+	BIT_ULL(POWER_DOMAIN_AUX_TC1) |		\
+	BIT_ULL(POWER_DOMAIN_AUX_TC2) |		\
+	BIT_ULL(POWER_DOMAIN_AUX_TC3) |		\
+	BIT_ULL(POWER_DOMAIN_AUX_TC4) |		\
+	BIT_ULL(POWER_DOMAIN_AUX_TC5) |		\
+	BIT_ULL(POWER_DOMAIN_AUX_TC6) |		\
+	BIT_ULL(POWER_DOMAIN_AUX_TBT1) |		\
+	BIT_ULL(POWER_DOMAIN_AUX_TBT2) |		\
+	BIT_ULL(POWER_DOMAIN_AUX_TBT3) |		\
+	BIT_ULL(POWER_DOMAIN_AUX_TBT4) |		\
+	BIT_ULL(POWER_DOMAIN_AUX_TBT5) |		\
+	BIT_ULL(POWER_DOMAIN_AUX_TBT6) |		\
+	BIT_ULL(POWER_DOMAIN_VGA) |			\
+	BIT_ULL(POWER_DOMAIN_AUDIO) |			\
+	BIT_ULL(POWER_DOMAIN_INIT))
+
+#define TGL_PW_2_POWER_DOMAINS (			\
+	TGL_PW_3_POWER_DOMAINS |			\
+	BIT_ULL(POWER_DOMAIN_TRANSCODER_EDP_VDSC) |	\
+	BIT_ULL(POWER_DOMAIN_INIT))
+
+#define TGL_DISPLAY_DC_OFF_POWER_DOMAINS (		\
+	TGL_PW_2_POWER_DOMAINS |			\
+	BIT_ULL(POWER_DOMAIN_MODESET) |			\
+	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
+	BIT_ULL(POWER_DOMAIN_INIT))
+
+#define TGL_DDI_IO_TC1_POWER_DOMAINS (		\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_IO))
+#define TGL_DDI_IO_TC2_POWER_DOMAINS (		\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC2_IO))
+#define TGL_DDI_IO_TC3_POWER_DOMAINS (		\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC3_IO))
+#define TGL_DDI_IO_TC4_POWER_DOMAINS (		\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC4_IO))
+#define TGL_DDI_IO_TC5_POWER_DOMAINS (		\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC5_IO))
+#define TGL_DDI_IO_TC6_POWER_DOMAINS (		\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC6_IO))
+
+#define TGL_AUX_TC1_IO_POWER_DOMAINS (		\
+	BIT_ULL(POWER_DOMAIN_AUX_TC1))
+#define TGL_AUX_TC2_IO_POWER_DOMAINS (		\
+	BIT_ULL(POWER_DOMAIN_AUX_TC2))
+#define TGL_AUX_TC3_IO_POWER_DOMAINS (		\
+	BIT_ULL(POWER_DOMAIN_AUX_TC3))
+#define TGL_AUX_TC4_IO_POWER_DOMAINS (		\
+	BIT_ULL(POWER_DOMAIN_AUX_TC4))
+#define TGL_AUX_TC5_IO_POWER_DOMAINS (		\
+	BIT_ULL(POWER_DOMAIN_AUX_TC5))
+#define TGL_AUX_TC6_IO_POWER_DOMAINS (		\
+	BIT_ULL(POWER_DOMAIN_AUX_TC6))
+#define TGL_AUX_TBT5_IO_POWER_DOMAINS (		\
+	BIT_ULL(POWER_DOMAIN_AUX_TBT5))
+#define TGL_AUX_TBT6_IO_POWER_DOMAINS (		\
+	BIT_ULL(POWER_DOMAIN_AUX_TBT6))
+
 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
 	.sync_hw = i9xx_power_well_sync_hw_noop,
 	.enable = i9xx_always_on_power_well_noop,
@@ -3452,6 +3577,324 @@ static const struct i915_power_well_desc icl_power_wells[] = {
 	},
 };
 
+static const struct i915_power_well_desc tgl_power_wells[] = {
+	{
+		.name = "always-on",
+		.always_on = true,
+		.domains = POWER_DOMAIN_MASK,
+		.ops = &i9xx_always_on_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+	},
+	{
+		.name = "power well 1",
+		/* Handled by the DMC firmware */
+		.always_on = true,
+		.domains = 0,
+		.ops = &hsw_power_well_ops,
+		.id = SKL_DISP_PW_1,
+		{
+			.hsw.regs = &hsw_power_well_regs,
+			.hsw.idx = ICL_PW_CTL_IDX_PW_1,
+			.hsw.has_fuses = true,
+		},
+	},
+	{
+		.name = "DC off",
+		.domains = TGL_DISPLAY_DC_OFF_POWER_DOMAINS,
+		.ops = &gen9_dc_off_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+	},
+	{
+		.name = "power well 2",
+		.domains = TGL_PW_2_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = SKL_DISP_PW_2,
+		{
+			.hsw.regs = &hsw_power_well_regs,
+			.hsw.idx = ICL_PW_CTL_IDX_PW_2,
+			.hsw.has_fuses = true,
+		},
+	},
+	{
+		.name = "power well 3",
+		.domains = TGL_PW_3_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &hsw_power_well_regs,
+			.hsw.idx = ICL_PW_CTL_IDX_PW_3,
+			.hsw.irq_pipe_mask = BIT(PIPE_B),
+			.hsw.has_vga = true,
+			.hsw.has_fuses = true,
+		},
+	},
+	{
+		.name = "DDI A IO",
+		.domains = ICL_DDI_IO_A_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_ddi_power_well_regs,
+			.hsw.idx = ICL_PW_CTL_IDX_DDI_A,
+		}
+	},
+	{
+		.name = "DDI B IO",
+		.domains = ICL_DDI_IO_B_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_ddi_power_well_regs,
+			.hsw.idx = ICL_PW_CTL_IDX_DDI_B,
+		}
+	},
+	{
+		.name = "DDI C IO",
+		.domains = ICL_DDI_IO_C_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_ddi_power_well_regs,
+			.hsw.idx = ICL_PW_CTL_IDX_DDI_C,
+		}
+	},
+	{
+		.name = "DDI TC1 IO",
+		.domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_ddi_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
+		},
+	},
+	{
+		.name = "DDI TC2 IO",
+		.domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_ddi_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
+		},
+	},
+	{
+		.name = "DDI TC3 IO",
+		.domains = TGL_DDI_IO_TC3_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_ddi_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC3,
+		},
+	},
+	{
+		.name = "DDI TC4 IO",
+		.domains = TGL_DDI_IO_TC4_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_ddi_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC4,
+		},
+	},
+	{
+		.name = "DDI TC5 IO",
+		.domains = TGL_DDI_IO_TC5_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_ddi_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC5,
+		},
+	},
+	{
+		.name = "DDI TC6 IO",
+		.domains = TGL_DDI_IO_TC6_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_ddi_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC6,
+		},
+	},
+	{
+		.name = "AUX A",
+		.domains = ICL_AUX_A_IO_POWER_DOMAINS,
+		.ops = &icl_combo_phy_aux_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_aux_power_well_regs,
+			.hsw.idx = ICL_PW_CTL_IDX_AUX_A,
+		},
+	},
+	{
+		.name = "AUX B",
+		.domains = ICL_AUX_B_IO_POWER_DOMAINS,
+		.ops = &icl_combo_phy_aux_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_aux_power_well_regs,
+			.hsw.idx = ICL_PW_CTL_IDX_AUX_B,
+		},
+	},
+	{
+		.name = "AUX C",
+		.domains = ICL_AUX_C_IO_POWER_DOMAINS,
+		.ops = &icl_combo_phy_aux_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_aux_power_well_regs,
+			.hsw.idx = ICL_PW_CTL_IDX_AUX_C,
+		},
+	},
+	{
+		.name = "AUX TC1",
+		.domains = TGL_AUX_TC1_IO_POWER_DOMAINS,
+		.ops = &icl_tc_phy_aux_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_aux_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
+			.hsw.is_tc_tbt = false,
+		},
+	},
+	{
+		.name = "AUX TC2",
+		.domains = TGL_AUX_TC2_IO_POWER_DOMAINS,
+		.ops = &icl_tc_phy_aux_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_aux_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
+			.hsw.is_tc_tbt = false,
+		},
+	},
+	{
+		.name = "AUX TC3",
+		.domains = TGL_AUX_TC3_IO_POWER_DOMAINS,
+		.ops = &icl_tc_phy_aux_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_aux_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC3,
+			.hsw.is_tc_tbt = false,
+		},
+	},
+	{
+		.name = "AUX TC4",
+		.domains = TGL_AUX_TC4_IO_POWER_DOMAINS,
+		.ops = &icl_tc_phy_aux_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_aux_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC4,
+			.hsw.is_tc_tbt = false,
+		},
+	},
+	{
+		.name = "AUX TC5",
+		.domains = TGL_AUX_TC5_IO_POWER_DOMAINS,
+		.ops = &icl_tc_phy_aux_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_aux_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC5,
+			.hsw.is_tc_tbt = false,
+		},
+	},
+	{
+		.name = "AUX TC6",
+		.domains = TGL_AUX_TC6_IO_POWER_DOMAINS,
+		.ops = &icl_tc_phy_aux_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_aux_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC6,
+			.hsw.is_tc_tbt = false,
+		},
+	},
+	{
+		.name = "AUX TBT1",
+		.domains = ICL_AUX_TBT1_IO_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_aux_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1,
+			.hsw.is_tc_tbt = true,
+		},
+	},
+	{
+		.name = "AUX TBT2",
+		.domains = ICL_AUX_TBT2_IO_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_aux_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2,
+			.hsw.is_tc_tbt = true,
+		},
+	},
+	{
+		.name = "AUX TBT3",
+		.domains = ICL_AUX_TBT3_IO_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_aux_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3,
+			.hsw.is_tc_tbt = true,
+		},
+	},
+	{
+		.name = "AUX TBT4",
+		.domains = ICL_AUX_TBT4_IO_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_aux_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4,
+			.hsw.is_tc_tbt = true,
+		},
+	},
+	{
+		.name = "AUX TBT5",
+		.domains = TGL_AUX_TBT5_IO_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_aux_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT5,
+			.hsw.is_tc_tbt = true,
+		},
+	},
+	{
+		.name = "AUX TBT6",
+		.domains = TGL_AUX_TBT6_IO_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_aux_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT6,
+			.hsw.is_tc_tbt = true,
+		},
+	},
+	{
+		.name = "power well 4",
+		.domains = ICL_PW_4_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &hsw_power_well_regs,
+			.hsw.idx = ICL_PW_CTL_IDX_PW_4,
+			.hsw.has_fuses = true,
+			.hsw.irq_pipe_mask = BIT(PIPE_C),
+		}
+	},
+	/* TODO: power well 5 for pipe D */
+};
+
 static int
 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
 				   int disable_power_well)
@@ -3579,7 +4022,9 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
 	 * The enabling order will be from lower to higher indexed wells,
 	 * the disabling order is reversed.
 	 */
-	if (IS_GEN(dev_priv, 11)) {
+	if (IS_GEN(dev_priv, 12)) {
+		err = set_power_wells(power_domains, tgl_power_wells);
+	} else if (IS_GEN(dev_priv, 11)) {
 		err = set_power_wells(power_domains, icl_power_wells);
 	} else if (IS_CANNONLAKE(dev_priv)) {
 		err = set_power_wells(power_domains, cnl_power_wells);
@@ -4643,7 +5088,8 @@ static void intel_power_domains_dump_info(struct drm_i915_private *i915)
 
 		for_each_power_domain(domain, power_well->desc->domains)
 			DRM_DEBUG_DRIVER("  %-23s %d\n",
-					 intel_display_power_domain_str(domain),
+					 intel_display_power_domain_str(i915,
+									domain),
 					 power_domains->domain_use_count[domain]);
 	}
 }
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 8f43f7051a16..86afd70c1fb2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -32,14 +32,29 @@ enum intel_display_power_domain {
 	POWER_DOMAIN_PORT_DDI_B_LANES,
 	POWER_DOMAIN_PORT_DDI_C_LANES,
 	POWER_DOMAIN_PORT_DDI_D_LANES,
+	POWER_DOMAIN_PORT_DDI_TC1_LANES = POWER_DOMAIN_PORT_DDI_D_LANES,
 	POWER_DOMAIN_PORT_DDI_E_LANES,
+	POWER_DOMAIN_PORT_DDI_TC2_LANES = POWER_DOMAIN_PORT_DDI_E_LANES,
 	POWER_DOMAIN_PORT_DDI_F_LANES,
+	POWER_DOMAIN_PORT_DDI_TC3_LANES = POWER_DOMAIN_PORT_DDI_F_LANES,
+	POWER_DOMAIN_PORT_DDI_TC4_LANES,
+	POWER_DOMAIN_PORT_DDI_TC5_LANES,
+	POWER_DOMAIN_PORT_DDI_TC6_LANES,
 	POWER_DOMAIN_PORT_DDI_A_IO,
 	POWER_DOMAIN_PORT_DDI_B_IO,
 	POWER_DOMAIN_PORT_DDI_C_IO,
 	POWER_DOMAIN_PORT_DDI_D_IO,
+	POWER_DOMAIN_PORT_DDI_TC1_IO = POWER_DOMAIN_PORT_DDI_D_IO,
 	POWER_DOMAIN_PORT_DDI_E_IO,
+	POWER_DOMAIN_PORT_DDI_TC2_IO = POWER_DOMAIN_PORT_DDI_E_IO,
 	POWER_DOMAIN_PORT_DDI_F_IO,
+	POWER_DOMAIN_PORT_DDI_TC3_IO = POWER_DOMAIN_PORT_DDI_F_IO,
+	POWER_DOMAIN_PORT_DDI_G_IO,
+	POWER_DOMAIN_PORT_DDI_TC4_IO = POWER_DOMAIN_PORT_DDI_G_IO,
+	POWER_DOMAIN_PORT_DDI_H_IO,
+	POWER_DOMAIN_PORT_DDI_TC5_IO = POWER_DOMAIN_PORT_DDI_H_IO,
+	POWER_DOMAIN_PORT_DDI_I_IO,
+	POWER_DOMAIN_PORT_DDI_TC6_IO = POWER_DOMAIN_PORT_DDI_I_IO,
 	POWER_DOMAIN_PORT_DSI,
 	POWER_DOMAIN_PORT_CRT,
 	POWER_DOMAIN_PORT_OTHER,
@@ -49,13 +64,21 @@ enum intel_display_power_domain {
 	POWER_DOMAIN_AUX_B,
 	POWER_DOMAIN_AUX_C,
 	POWER_DOMAIN_AUX_D,
+	POWER_DOMAIN_AUX_TC1 = POWER_DOMAIN_AUX_D,
 	POWER_DOMAIN_AUX_E,
+	POWER_DOMAIN_AUX_TC2 = POWER_DOMAIN_AUX_E,
 	POWER_DOMAIN_AUX_F,
+	POWER_DOMAIN_AUX_TC3 = POWER_DOMAIN_AUX_F,
+	POWER_DOMAIN_AUX_TC4,
+	POWER_DOMAIN_AUX_TC5,
+	POWER_DOMAIN_AUX_TC6,
 	POWER_DOMAIN_AUX_IO_A,
 	POWER_DOMAIN_AUX_TBT1,
 	POWER_DOMAIN_AUX_TBT2,
 	POWER_DOMAIN_AUX_TBT3,
 	POWER_DOMAIN_AUX_TBT4,
+	POWER_DOMAIN_AUX_TBT5,
+	POWER_DOMAIN_AUX_TBT6,
 	POWER_DOMAIN_GMBUS,
 	POWER_DOMAIN_MODESET,
 	POWER_DOMAIN_GT_IRQ,
@@ -228,7 +251,8 @@ void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
 
 const char *
-intel_display_power_domain_str(enum intel_display_power_domain domain);
+intel_display_power_domain_str(struct drm_i915_private *i915,
+			       enum intel_display_power_domain domain);
 
 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 				    enum intel_display_power_domain domain);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 3e4f58f19362..4d59972e9689 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2472,7 +2472,8 @@ static int i915_power_domain_info(struct seq_file *m, void *unused)
 
 		for_each_power_domain(power_domain, power_well->desc->domains)
 			seq_printf(m, "  %-23s %d\n",
-				 intel_display_power_domain_str(power_domain),
+				 intel_display_power_domain_str(dev_priv,
+								power_domain),
 				 power_domains->domain_use_count[power_domain]);
 	}
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 08dc71e4b818..f59cb5c45c34 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9156,13 +9156,25 @@ enum {
 #define ICL_PWR_WELL_CTL_AUX1			_MMIO(0x45440)
 #define ICL_PWR_WELL_CTL_AUX2			_MMIO(0x45444)
 #define ICL_PWR_WELL_CTL_AUX4			_MMIO(0x4544C)
+#define   TGL_PW_CTL_IDX_AUX_TBT6		14
+#define   TGL_PW_CTL_IDX_AUX_TBT5		13
+#define   TGL_PW_CTL_IDX_AUX_TBT4		12
 #define   ICL_PW_CTL_IDX_AUX_TBT4		11
+#define   TGL_PW_CTL_IDX_AUX_TBT3		11
 #define   ICL_PW_CTL_IDX_AUX_TBT3		10
+#define   TGL_PW_CTL_IDX_AUX_TBT2		10
 #define   ICL_PW_CTL_IDX_AUX_TBT2		9
+#define   TGL_PW_CTL_IDX_AUX_TBT1		9
 #define   ICL_PW_CTL_IDX_AUX_TBT1		8
+#define   TGL_PW_CTL_IDX_AUX_TC6		8
+#define   TGL_PW_CTL_IDX_AUX_TC5		7
+#define   TGL_PW_CTL_IDX_AUX_TC4		6
 #define   ICL_PW_CTL_IDX_AUX_F			5
+#define   TGL_PW_CTL_IDX_AUX_TC3		5
 #define   ICL_PW_CTL_IDX_AUX_E			4
+#define   TGL_PW_CTL_IDX_AUX_TC2		4
 #define   ICL_PW_CTL_IDX_AUX_D			3
+#define   TGL_PW_CTL_IDX_AUX_TC1		3
 #define   ICL_PW_CTL_IDX_AUX_C			2
 #define   ICL_PW_CTL_IDX_AUX_B			1
 #define   ICL_PW_CTL_IDX_AUX_A			0
@@ -9170,9 +9182,15 @@ enum {
 #define ICL_PWR_WELL_CTL_DDI1			_MMIO(0x45450)
 #define ICL_PWR_WELL_CTL_DDI2			_MMIO(0x45454)
 #define ICL_PWR_WELL_CTL_DDI4			_MMIO(0x4545C)
+#define   TGL_PW_CTL_IDX_DDI_TC6		8
+#define   TGL_PW_CTL_IDX_DDI_TC5		7
+#define   TGL_PW_CTL_IDX_DDI_TC4		6
 #define   ICL_PW_CTL_IDX_DDI_F			5
+#define   TGL_PW_CTL_IDX_DDI_TC3		5
 #define   ICL_PW_CTL_IDX_DDI_E			4
+#define   TGL_PW_CTL_IDX_DDI_TC2		4
 #define   ICL_PW_CTL_IDX_DDI_D			3
+#define   TGL_PW_CTL_IDX_DDI_TC1		3
 #define   ICL_PW_CTL_IDX_DDI_C			2
 #define   ICL_PW_CTL_IDX_DDI_B			1
 #define   ICL_PW_CTL_IDX_DDI_A			0
-- 
2.21.0

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[PATCH v2 10/25] drm/i915/tgl: Add power well to support 4th pipe

[Lucas De Marchi]

From: Mika Kahola <mika.kahola@intel.com>

Add power well 5 to support 4th pipe and transcoder on TGL.

Cc: James Ausmus <james.ausmus@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 .../drm/i915/display/intel_display_power.c    | 30 ++++++++++++++++---
 .../drm/i915/display/intel_display_power.h    |  3 ++
 drivers/gpu/drm/i915/i915_reg.h               |  3 +-
 3 files changed, 31 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index c3f42169831f..455f9aab188d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -37,18 +37,24 @@ intel_display_power_domain_str(struct drm_i915_private *i915,
 		return "PIPE_B";
 	case POWER_DOMAIN_PIPE_C:
 		return "PIPE_C";
+	case POWER_DOMAIN_PIPE_D:
+		return "PIPE_D";
 	case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
 		return "PIPE_A_PANEL_FITTER";
 	case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
 		return "PIPE_B_PANEL_FITTER";
 	case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
 		return "PIPE_C_PANEL_FITTER";
+	case POWER_DOMAIN_PIPE_D_PANEL_FITTER:
+		return "PIPE_D_PANEL_FITTER";
 	case POWER_DOMAIN_TRANSCODER_A:
 		return "TRANSCODER_A";
 	case POWER_DOMAIN_TRANSCODER_B:
 		return "TRANSCODER_B";
 	case POWER_DOMAIN_TRANSCODER_C:
 		return "TRANSCODER_C";
+	case POWER_DOMAIN_TRANSCODER_D:
+		return "TRANSCODER_D";
 	case POWER_DOMAIN_TRANSCODER_EDP:
 		return "TRANSCODER_EDP";
 	case POWER_DOMAIN_TRANSCODER_EDP_VDSC:
@@ -2451,7 +2457,6 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
  * - DDI_A
  * - FBC
  */
-/* TODO: TGL_PW_5_POWER_DOMAINS: PIPE_D */
 #define ICL_PW_4_POWER_DOMAINS (			\
 	BIT_ULL(POWER_DOMAIN_PIPE_C) |			\
 	BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |	\
@@ -2539,7 +2544,13 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
 #define ICL_AUX_TBT4_IO_POWER_DOMAINS (			\
 	BIT_ULL(POWER_DOMAIN_AUX_TBT4))
 
+#define TGL_PW_5_POWER_DOMAINS (			\
+	BIT_ULL(POWER_DOMAIN_PIPE_D) |			\
+	BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) |     \
+	BIT_ULL(POWER_DOMAIN_INIT))
+
 #define TGL_PW_4_POWER_DOMAINS (			\
+	TGL_PW_5_POWER_DOMAINS |			\
 	BIT_ULL(POWER_DOMAIN_PIPE_C) |			\
 	BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |	\
 	BIT_ULL(POWER_DOMAIN_INIT))
@@ -2549,7 +2560,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
 	BIT_ULL(POWER_DOMAIN_PIPE_B) |			\
 	BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |		\
 	BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |		\
-	/* TODO: TRANSCODER_D */			\
+	BIT_ULL(POWER_DOMAIN_TRANSCODER_D) |		\
 	BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |	\
 	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_LANES) |	\
 	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_IO) |		\
@@ -3882,7 +3893,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
 	},
 	{
 		.name = "power well 4",
-		.domains = ICL_PW_4_POWER_DOMAINS,
+		.domains = TGL_PW_4_POWER_DOMAINS,
 		.ops = &hsw_power_well_ops,
 		.id = DISP_PW_ID_NONE,
 		{
@@ -3892,7 +3903,18 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
 			.hsw.irq_pipe_mask = BIT(PIPE_C),
 		}
 	},
-	/* TODO: power well 5 for pipe D */
+	{
+		.name = "power well 5",
+		.domains = TGL_PW_5_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &hsw_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_PW_5,
+			.hsw.has_fuses = true,
+			.hsw.irq_pipe_mask = BIT(PIPE_D),
+		},
+	},
 };
 
 static int
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 86afd70c1fb2..ebb397e330ea 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -18,12 +18,15 @@ enum intel_display_power_domain {
 	POWER_DOMAIN_PIPE_A,
 	POWER_DOMAIN_PIPE_B,
 	POWER_DOMAIN_PIPE_C,
+	POWER_DOMAIN_PIPE_D,
 	POWER_DOMAIN_PIPE_A_PANEL_FITTER,
 	POWER_DOMAIN_PIPE_B_PANEL_FITTER,
 	POWER_DOMAIN_PIPE_C_PANEL_FITTER,
+	POWER_DOMAIN_PIPE_D_PANEL_FITTER,
 	POWER_DOMAIN_TRANSCODER_A,
 	POWER_DOMAIN_TRANSCODER_B,
 	POWER_DOMAIN_TRANSCODER_C,
+	POWER_DOMAIN_TRANSCODER_D,
 	POWER_DOMAIN_TRANSCODER_EDP,
 	POWER_DOMAIN_TRANSCODER_EDP_VDSC,
 	POWER_DOMAIN_TRANSCODER_DSI_A,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f59cb5c45c34..5ca74eca05a4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9147,7 +9147,8 @@ enum {
 #define   GLK_PW_CTL_IDX_DDI_A			1
 #define   SKL_PW_CTL_IDX_MISC_IO		0
 
-/* ICL - power wells */
+/* ICL/TGL - power wells */
+#define   TGL_PW_CTL_IDX_PW_5			4
 #define   ICL_PW_CTL_IDX_PW_4			3
 #define   ICL_PW_CTL_IDX_PW_3			2
 #define   ICL_PW_CTL_IDX_PW_2			1
-- 
2.21.0

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[PATCH v2 11/25] drm/i915/tgl: Add new pll ids

[Lucas De Marchi]

From: Vandita Kulkarni <vandita.kulkarni@intel.com>

Add 2 new PLLs for additional TC ports. The names for the PLLs on TGL
changed, but most registers remained the same, like MGPLL5_ENABLE,
MGPLL6_ENABLE. So continue to use the name from ICL.

Cc: Madhav Chauhan <madhav.chauhan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 23 +++++++++++++++----
 1 file changed, 18 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 4c2c5e93aff3..d0e14ed6e5f8 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -112,11 +112,11 @@ enum intel_dpll_id {
 
 
 	/**
-	 * @DPLL_ID_ICL_DPLL0: ICL combo PHY DPLL0
+	 * @DPLL_ID_ICL_DPLL0: ICL/TGL combo PHY DPLL0
 	 */
 	DPLL_ID_ICL_DPLL0 = 0,
 	/**
-	 * @DPLL_ID_ICL_DPLL1: ICL combo PHY DPLL1
+	 * @DPLL_ID_ICL_DPLL1: ICL/TGL combo PHY DPLL1
 	 */
 	DPLL_ID_ICL_DPLL1 = 1,
 	/**
@@ -124,27 +124,40 @@ enum intel_dpll_id {
 	 */
 	DPLL_ID_EHL_DPLL4 = 2,
 	/**
-	 * @DPLL_ID_ICL_TBTPLL: ICL TBT PLL
+	 * @DPLL_ID_ICL_TBTPLL: ICL/TGL TBT PLL
 	 */
 	DPLL_ID_ICL_TBTPLL = 2,
 	/**
-	 * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C)
+	 * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C),
+	 *                      TGL TC PLL 1 port 1 (TC1)
 	 */
 	DPLL_ID_ICL_MGPLL1 = 3,
 	/**
 	 * @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D)
+	 *                      TGL TC PLL 1 port 2 (TC2)
 	 */
 	DPLL_ID_ICL_MGPLL2 = 4,
 	/**
 	 * @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E)
+	 *                      TGL TC PLL 1 port 3 (TC3)
 	 */
 	DPLL_ID_ICL_MGPLL3 = 5,
 	/**
 	 * @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F)
+	 *                      TGL TC PLL 1 port 4 (TC4)
 	 */
 	DPLL_ID_ICL_MGPLL4 = 6,
+	/**
+	 * @DPLL_ID_TGL_TCPLL5: TGL TC PLL port 5 (TC5)
+	 */
+	DPLL_ID_TGL_MGPLL5 = 7,
+	/**
+	 * @DPLL_ID_TGL_TCPLL6: TGL TC PLL port 6 (TC6)
+	 */
+	DPLL_ID_TGL_MGPLL6 = 8,
 };
-#define I915_NUM_PLLS 7
+
+#define I915_NUM_PLLS 9
 
 enum icl_port_dpll_id {
 	ICL_PORT_DPLL_DEFAULT,
-- 
2.21.0

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[PATCH v2 12/25] drm/i915/tgl: Add pll manager

[Lucas De Marchi]

From: Vandita Kulkarni <vandita.kulkarni@intel.com>

Add a new pll array for Tiger Lake. The TC pll functions for type C will
be covered in later patches after its phy is implemented.

Cc: Madhav Chauhan <madhav.chauhan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 67cfe836286e..ae1c552d7afb 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3455,6 +3455,21 @@ static const struct intel_dpll_mgr ehl_pll_mgr = {
 	.dump_hw_state = icl_dump_hw_state,
 };
 
+static const struct dpll_info tgl_plls[] = {
+	{ "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0,  0 },
+	{ "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1,  0 },
+	{ "TBT PLL",  &tbt_pll_funcs, DPLL_ID_ICL_TBTPLL, 0 },
+	/* TODO: Add typeC plls */
+	{ },
+};
+
+static const struct intel_dpll_mgr tgl_pll_mgr = {
+	.dpll_info = tgl_plls,
+	.get_dplls = icl_get_dplls,
+	.put_dplls = icl_put_dplls,
+	.dump_hw_state = icl_dump_hw_state,
+};
+
 /**
  * intel_shared_dpll_init - Initialize shared DPLLs
  * @dev: drm device
@@ -3468,7 +3483,9 @@ void intel_shared_dpll_init(struct drm_device *dev)
 	const struct dpll_info *dpll_info;
 	int i;
 
-	if (IS_ELKHARTLAKE(dev_priv))
+	if (INTEL_GEN(dev_priv) >= 12)
+		dpll_mgr = &tgl_pll_mgr;
+	else if (IS_ELKHARTLAKE(dev_priv))
 		dpll_mgr = &ehl_pll_mgr;
 	else if (INTEL_GEN(dev_priv) >= 11)
 		dpll_mgr = &icl_pll_mgr;
-- 
2.21.0

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[PATCH v2 13/25] drm/i915/tgl: Add additional ports for Tiger Lake

[Lucas De Marchi]

From: Vandita Kulkarni <vandita.kulkarni@intel.com>

There are 2 new additional typeC ports in Tiger Lake and PORT-C is now a
combophy port. This results in 6 typeC ports and 3 combophy ports.
These 6 TC ports can be DP alternate mode, DP over thunderbolt, native
DP on legacy DP connector or native HDMI on legacy connector.

v2: Rebase on new modular FIA code (Lucas)

Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c     | 12 ++++++++++++
 drivers/gpu/drm/i915/display/intel_display.h |  2 ++
 include/drm/i915_component.h                 |  2 +-
 include/drm/i915_drm.h                       |  3 +++
 4 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 30e48609db1d..e72cf0bb48a7 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4297,6 +4297,18 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 		intel_dig_port->ddi_io_power_domain =
 			POWER_DOMAIN_PORT_DDI_F_IO;
 		break;
+	case PORT_G:
+		intel_dig_port->ddi_io_power_domain =
+			POWER_DOMAIN_PORT_DDI_G_IO;
+		break;
+	case PORT_H:
+		intel_dig_port->ddi_io_power_domain =
+			POWER_DOMAIN_PORT_DDI_H_IO;
+		break;
+	case PORT_I:
+		intel_dig_port->ddi_io_power_domain =
+			POWER_DOMAIN_PORT_DDI_I_IO;
+		break;
 	default:
 		MISSING_CASE(port);
 	}
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index e781df463ffa..270b1f18dedd 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -189,6 +189,8 @@ enum tc_port {
 	PORT_TC2,
 	PORT_TC3,
 	PORT_TC4,
+	PORT_TC5,
+	PORT_TC6,
 
 	I915_MAX_TC_PORTS
 };
diff --git a/include/drm/i915_component.h b/include/drm/i915_component.h
index dcb95bd9dee6..55c3b123581b 100644
--- a/include/drm/i915_component.h
+++ b/include/drm/i915_component.h
@@ -34,7 +34,7 @@ enum i915_component_type {
 /* MAX_PORT is the number of port
  * It must be sync with I915_MAX_PORTS defined i915_drv.h
  */
-#define MAX_PORTS 6
+#define MAX_PORTS 9
 
 /**
  * struct i915_audio_component - Used for direct communication between i915 and hda drivers
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index 7523e9a7b6e2..eb30062359d1 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -109,6 +109,9 @@ enum port {
 	PORT_D,
 	PORT_E,
 	PORT_F,
+	PORT_G,
+	PORT_H,
+	PORT_I,
 
 	I915_MAX_PORTS
 };
-- 
2.21.0

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[PATCH v2 14/25] drm/i915/tgl: update ddi/tc clock_off bits

[Lucas De Marchi]

From: Mahesh Kumar <mahesh1.kumar@intel.com>

In GEN 12 PORT_C DDI clk_off bit is not equally distanced to A/B,
it's at offset 24. Similarly TC port (5/6) clk off bits are at
offset 22/23. Extend the macros to cover the additional ports.

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5ca74eca05a4..4588df9e11de 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9723,9 +9723,11 @@ enum skl_power_gate {
 #define DPCLKA_CFGCR0_ICL			_MMIO(0x164280)
 #define  DPCLKA_CFGCR0_DDI_CLK_OFF(port)	(1 << ((port) ==  PORT_F ? 23 : \
 						      (port) + 10))
-#define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port)   (1 << ((port) + 10))
-#define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \
-						      21 : (tc_port) + 12))
+#define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port)	(1 << ((port) == PORT_C ? 24 : \
+						       (port) + 10))
+#define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)	(1 << ((tc_port) < PORT_TC4 ? \
+						       (tc_port) + 12 : \
+						       (tc_port) - PORT_TC4 + 21))
 #define  DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)	((port) == PORT_F ? 21 : \
 						(port) * 2)
 #define  DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port)	(3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
-- 
2.21.0

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[PATCH v2 15/25] drm/i915/tgl: Add gmbus gpio pin to port mapping

[Lucas De Marchi]

From: Mahesh Kumar <mahesh1.kumar@intel.com>

Add default GPIO pin mapping for all ports. Tiger Lake has 3 combophy
ports and 6 TC ports, gpio pin1-3 are mapped to combophy & pin9-14 are
mapped to TC ports.

Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.h |  2 ++
 drivers/gpu/drm/i915/display/intel_gmbus.c   | 20 ++++++++++++++++++--
 drivers/gpu/drm/i915/i915_reg.h              |  4 +++-
 3 files changed, 23 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 270b1f18dedd..231d8595845a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -45,6 +45,8 @@ enum i915_gpio {
 	GPIOK,
 	GPIOL,
 	GPIOM,
+	GPION,
+	GPIOO,
 };
 
 /*
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
index 4f6a9bd5af47..b42c79aea61a 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -94,11 +94,25 @@ static const struct gmbus_pin gmbus_pins_mcc[] = {
 	[GMBUS_PIN_9_TC1_ICP] = { "dpc", GPIOJ },
 };
 
+static const struct gmbus_pin gmbus_pins_tgp[] = {
+	[GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
+	[GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
+	[GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
+	[GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
+	[GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
+	[GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
+	[GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
+	[GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION },
+	[GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO },
+};
+
 /* pin is expected to be valid */
 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
 					     unsigned int pin)
 {
-	if (HAS_PCH_MCC(dev_priv))
+	if (HAS_PCH_TGP(dev_priv))
+		return &gmbus_pins_tgp[pin];
+	else if (HAS_PCH_MCC(dev_priv))
 		return &gmbus_pins_mcc[pin];
 	else if (HAS_PCH_ICP(dev_priv))
 		return &gmbus_pins_icp[pin];
@@ -119,7 +133,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
 {
 	unsigned int size;
 
-	if (HAS_PCH_MCC(dev_priv))
+	if (HAS_PCH_TGP(dev_priv))
+		size = ARRAY_SIZE(gmbus_pins_tgp);
+	else if (HAS_PCH_MCC(dev_priv))
 		size = ARRAY_SIZE(gmbus_pins_mcc);
 	else if (HAS_PCH_ICP(dev_priv))
 		size = ARRAY_SIZE(gmbus_pins_icp);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4588df9e11de..c554df69f289 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3254,8 +3254,10 @@ enum i915_power_well_id {
 #define   GMBUS_PIN_10_TC2_ICP	10
 #define   GMBUS_PIN_11_TC3_ICP	11
 #define   GMBUS_PIN_12_TC4_ICP	12
+#define   GMBUS_PIN_13_TC5_TGP	13
+#define   GMBUS_PIN_14_TC6_TGP	14
 
-#define   GMBUS_NUM_PINS	13 /* including 0 */
+#define   GMBUS_NUM_PINS	15 /* including 0 */
 #define GMBUS1			_MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
 #define   GMBUS_SW_CLR_INT	(1 << 31)
 #define   GMBUS_SW_RDY		(1 << 30)
-- 
2.21.0

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[PATCH v2 16/25] drm/i915/tgl: port to ddc pin mapping

[Lucas De Marchi]

From: Mahesh Kumar <mahesh1.kumar@intel.com>

Create a helper function to get ddc pin according to port number.

Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdmi.c | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 0ebec69bbbfc..3b33e7626d7c 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2981,6 +2981,18 @@ static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
 	return ddc_pin;
 }
 
+static u8 tgp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
+			      enum port port)
+{
+	if (intel_port_is_combophy(dev_priv, port))
+		return GMBUS_PIN_1_BXT + port;
+	else if (intel_port_is_tc(dev_priv, port))
+		return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port);
+
+	WARN(1, "Unknown port:%c\n", port_name(port));
+	return GMBUS_PIN_2_BXT;
+}
+
 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
 			      enum port port)
 {
@@ -3017,7 +3029,9 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
 		return info->alternate_ddc_pin;
 	}
 
-	if (HAS_PCH_MCC(dev_priv))
+	if (HAS_PCH_TGP(dev_priv))
+		ddc_pin = tgp_port_to_ddc_pin(dev_priv, port);
+	else if (HAS_PCH_MCC(dev_priv))
 		ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
 	else if (HAS_PCH_ICP(dev_priv))
 		ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
-- 
2.21.0

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[PATCH v2 17/25] drm/i915/tgl: select correct bit for port select

[Lucas De Marchi]

From: Mahesh Kumar <mahesh1.kumar@intel.com>

Bit definitions for port-select got changed for TRANS_CLK_SEL &
TRANS_DDI_FUNC_CTL registers in TGL.

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 48 +++++++++++++++++++-----
 drivers/gpu/drm/i915/i915_reg.h          |  5 +++
 2 files changed, 43 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index e72cf0bb48a7..5125c31af6aa 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1771,7 +1771,10 @@ void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
 
 	/* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
 	temp = TRANS_DDI_FUNC_ENABLE;
-	temp |= TRANS_DDI_SELECT_PORT(port);
+	if (INTEL_GEN(dev_priv) >= 12)
+		temp |= TGL_TRANS_DDI_SELECT_PORT(port);
+	else
+		temp |= TRANS_DDI_SELECT_PORT(port);
 
 	switch (crtc_state->pipe_bpp) {
 	case 18:
@@ -1851,8 +1854,14 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state
 	i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 	u32 val = I915_READ(reg);
 
-	val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
-	val |= TRANS_DDI_PORT_NONE;
+	if (INTEL_GEN(dev_priv) >= 12) {
+		val &= ~(TRANS_DDI_FUNC_ENABLE | TGL_TRANS_DDI_PORT_MASK |
+			 TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
+	} else {
+		val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK |
+			 TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
+		val |= TRANS_DDI_PORT_NONE;
+	}
 	I915_WRITE(reg, val);
 
 	if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
@@ -2004,10 +2013,19 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
 	mst_pipe_mask = 0;
 	for_each_pipe(dev_priv, p) {
 		enum transcoder cpu_transcoder = (enum transcoder)p;
+		unsigned int port_mask, ddi_select;
+
+		if (INTEL_GEN(dev_priv) >= 12) {
+			port_mask = TGL_TRANS_DDI_PORT_MASK;
+			ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
+		} else {
+			port_mask = TRANS_DDI_PORT_MASK;
+			ddi_select = TRANS_DDI_SELECT_PORT(port);
+		}
 
 		tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
 
-		if ((tmp & TRANS_DDI_PORT_MASK) != TRANS_DDI_SELECT_PORT(port))
+		if ((tmp & port_mask) != ddi_select)
 			continue;
 
 		if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
@@ -2123,9 +2141,14 @@ void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
 	enum port port = encoder->port;
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 
-	if (cpu_transcoder != TRANSCODER_EDP)
-		I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
-			   TRANS_CLK_SEL_PORT(port));
+	if (cpu_transcoder != TRANSCODER_EDP) {
+		if (INTEL_GEN(dev_priv) >= 12)
+			I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
+				   TGL_TRANS_CLK_SEL_PORT(port));
+		else
+			I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
+				   TRANS_CLK_SEL_PORT(port));
+	}
 }
 
 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
@@ -2133,9 +2156,14 @@ void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
 	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 
-	if (cpu_transcoder != TRANSCODER_EDP)
-		I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
-			   TRANS_CLK_SEL_DISABLED);
+	if (cpu_transcoder != TRANSCODER_EDP) {
+		if (INTEL_GEN(dev_priv) >= 12)
+			I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
+				   TGL_TRANS_CLK_SEL_DISABLED);
+		else
+			I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
+				   TRANS_CLK_SEL_DISABLED);
+	}
 }
 
 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c554df69f289..ccfb95e2aa03 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9379,8 +9379,10 @@ enum skl_power_gate {
 #define  TRANS_DDI_FUNC_ENABLE		(1 << 31)
 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
 #define  TRANS_DDI_PORT_MASK		(7 << 28)
+#define  TGL_TRANS_DDI_PORT_MASK	(0xf << 27)
 #define  TRANS_DDI_PORT_SHIFT		28
 #define  TRANS_DDI_SELECT_PORT(x)	((x) << 28)
+#define  TGL_TRANS_DDI_SELECT_PORT(x)	(((x) + 1) << 27)
 #define  TRANS_DDI_PORT_NONE		(0 << 28)
 #define  TRANS_DDI_MODE_SELECT_MASK	(7 << 24)
 #define  TRANS_DDI_MODE_SELECT_HDMI	(0 << 24)
@@ -9591,6 +9593,9 @@ enum skl_power_gate {
 /* For each transcoder, we need to select the corresponding port clock */
 #define  TRANS_CLK_SEL_DISABLED		(0x0 << 29)
 #define  TRANS_CLK_SEL_PORT(x)		(((x) + 1) << 29)
+#define  TGL_TRANS_CLK_SEL_DISABLED	(0x0 << 28)
+#define  TGL_TRANS_CLK_SEL_PORT(x)	(((x) + 1) << 28)
+
 
 #define CDCLK_FREQ			_MMIO(0x46200)
 
-- 
2.21.0

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[PATCH v2 18/25] drm/i915/tgl: extend intel_port_is_combophy/tc

[Lucas De Marchi]

From: Mahesh Kumar <mahesh1.kumar@intel.com>

TGL has 3 combophy ports, so extend check for tigerlake in
intel_port_is_combophy/tc function.

Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d1148786920e..e224dcf60e31 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6676,10 +6676,10 @@ bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
 	if (port == PORT_NONE)
 		return false;
 
-	if (IS_ELKHARTLAKE(dev_priv))
+	if (IS_ELKHARTLAKE(dev_priv) || INTEL_GEN(dev_priv) >= 12)
 		return port <= PORT_C;
 
-	if (INTEL_GEN(dev_priv) >= 11)
+	if (IS_GEN(dev_priv, 11))
 		return port <= PORT_B;
 
 	return false;
@@ -6687,7 +6687,10 @@ bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
 
 bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
 {
-	if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
+	if (INTEL_GEN(dev_priv) >= 12)
+		return port >= PORT_D && port <= PORT_I;
+
+	if (IS_GEN(dev_priv, 11) && !IS_ELKHARTLAKE(dev_priv))
 		return port >= PORT_C && port <= PORT_F;
 
 	return false;
@@ -6698,6 +6701,9 @@ enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
 	if (!intel_port_is_tc(dev_priv, port))
 		return PORT_TC_NONE;
 
+	if (INTEL_GEN(dev_priv) >= 12)
+		return port - PORT_D;
+
 	return port - PORT_C;
 }
 
-- 
2.21.0

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[PATCH v2 19/25] drm/i915/tgl: init ddi port A-C for Tiger Lake

[Lucas De Marchi]

From: Mahesh Kumar <mahesh1.kumar@intel.com>

This patch initializes DDI PORT A, B & C for Tiger lake. Other
TC ports need to be initialized later once corresponding code is there.

Cc: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e224dcf60e31..9ccf58ff4dba 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15302,12 +15302,17 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
 	if (!HAS_DISPLAY(dev_priv))
 		return;
 
-	if (IS_ELKHARTLAKE(dev_priv)) {
+	if (INTEL_GEN(dev_priv) >= 12) {
+		/* TODO: initialize TC ports as well */
+		intel_ddi_init(dev_priv, PORT_A);
+		intel_ddi_init(dev_priv, PORT_B);
+		intel_ddi_init(dev_priv, PORT_C);
+	} else if (IS_ELKHARTLAKE(dev_priv)) {
 		intel_ddi_init(dev_priv, PORT_A);
 		intel_ddi_init(dev_priv, PORT_B);
 		intel_ddi_init(dev_priv, PORT_C);
 		icl_dsi_init(dev_priv);
-	} else if (INTEL_GEN(dev_priv) >= 11) {
+	} else if (IS_GEN(dev_priv, 11)) {
 		intel_ddi_init(dev_priv, PORT_A);
 		intel_ddi_init(dev_priv, PORT_B);
 		intel_ddi_init(dev_priv, PORT_C);
-- 
2.21.0

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[PATCH v2 20/25] drm/i915/tgl: Add vbt value mapping for DDC Bus pin

[Lucas De Marchi]

From: Mahesh Kumar <mahesh1.kumar@intel.com>

Add VBT-value to DDC bus pin mapping for the same.

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c     | 17 ++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_vbt_defs.h |  3 +++
 2 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 0c9808132d67..a08bc4f617c8 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1354,12 +1354,27 @@ static const u8 mcc_ddc_pin_map[] = {
 	[MCC_DDC_BUS_DDI_C] = GMBUS_PIN_9_TC1_ICP,
 };
 
+static const u8 tgp_ddc_pin_map[] = {
+	[ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
+	[ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT,
+	[TGL_DDC_BUS_DDI_C] = GMBUS_PIN_3_BXT,
+	[ICL_DDC_BUS_PORT_1] = GMBUS_PIN_9_TC1_ICP,
+	[ICL_DDC_BUS_PORT_2] = GMBUS_PIN_10_TC2_ICP,
+	[ICL_DDC_BUS_PORT_3] = GMBUS_PIN_11_TC3_ICP,
+	[ICL_DDC_BUS_PORT_4] = GMBUS_PIN_12_TC4_ICP,
+	[TGL_DDC_BUS_PORT_5] = GMBUS_PIN_13_TC5_TGP,
+	[TGL_DDC_BUS_PORT_6] = GMBUS_PIN_14_TC6_TGP,
+};
+
 static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
 {
 	const u8 *ddc_pin_map;
 	int n_entries;
 
-	if (HAS_PCH_MCC(dev_priv)) {
+	if (HAS_PCH_TGP(dev_priv)) {
+		ddc_pin_map = tgp_ddc_pin_map;
+		n_entries = ARRAY_SIZE(tgp_ddc_pin_map);
+	} else if (HAS_PCH_MCC(dev_priv)) {
 		ddc_pin_map = mcc_ddc_pin_map;
 		n_entries = ARRAY_SIZE(mcc_ddc_pin_map);
 	} else if (HAS_PCH_ICP(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 2f4894e9a03d..93f5c9d204d6 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -310,10 +310,13 @@ enum vbt_gmbus_ddi {
 	DDC_BUS_DDI_F,
 	ICL_DDC_BUS_DDI_A = 0x1,
 	ICL_DDC_BUS_DDI_B,
+	TGL_DDC_BUS_DDI_C,
 	ICL_DDC_BUS_PORT_1 = 0x4,
 	ICL_DDC_BUS_PORT_2,
 	ICL_DDC_BUS_PORT_3,
 	ICL_DDC_BUS_PORT_4,
+	TGL_DDC_BUS_PORT_5,
+	TGL_DDC_BUS_PORT_6,
 	MCC_DDC_BUS_DDI_A = 0x1,
 	MCC_DDC_BUS_DDI_B,
 	MCC_DDC_BUS_DDI_C = 0x4,
-- 
2.21.0

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[PATCH v2 21/25] drm/i915/tgl: apply Display WA #1178 to fix type C dongles

[Lucas De Marchi]

Add port C to workaround to cover Tiger Lake.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 11 ++++++++---
 drivers/gpu/drm/i915/i915_reg.h                    |  4 +++-
 2 files changed, 11 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 455f9aab188d..be3d4d1eece2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -453,6 +453,7 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
 	int pw_idx = power_well->desc->hsw.idx;
 	enum port port = ICL_AUX_PW_TO_PORT(pw_idx);
 	u32 val;
+	int wa_idx_max;
 
 	val = I915_READ(regs->driver);
 	I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
@@ -462,9 +463,13 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
 
 	hsw_wait_for_power_well_enable(dev_priv, power_well);
 
-	/* Display WA #1178: icl */
-	if (IS_ICELAKE(dev_priv) &&
-	    pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B &&
+	/* Display WA #1178: icl, tgl */
+	if (IS_TIGERLAKE(dev_priv))
+		wa_idx_max = ICL_PW_CTL_IDX_AUX_C;
+	else
+		wa_idx_max = ICL_PW_CTL_IDX_AUX_B;
+
+	if (pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= wa_idx_max &&
 	    !intel_bios_is_port_edp(dev_priv, port)) {
 		val = I915_READ(ICL_AUX_ANAOVRD1(pw_idx));
 		val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ccfb95e2aa03..fbcc7981c8c4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9246,9 +9246,11 @@ enum skl_power_gate {
 #define _ICL_AUX_REG_IDX(pw_idx)	((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
 #define _ICL_AUX_ANAOVRD1_A		0x162398
 #define _ICL_AUX_ANAOVRD1_B		0x6C398
+#define _TGL_AUX_ANAOVRD1_C		0x160398
 #define ICL_AUX_ANAOVRD1(pw_idx)	_MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \
 						    _ICL_AUX_ANAOVRD1_A, \
-						    _ICL_AUX_ANAOVRD1_B))
+						    _ICL_AUX_ANAOVRD1_B, \
+						    _TGL_AUX_ANAOVRD1_C))
 #define   ICL_AUX_ANAOVRD1_LDO_BYPASS	(1 << 7)
 #define   ICL_AUX_ANAOVRD1_ENABLE	(1 << 0)
 
-- 
2.21.0

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[PATCH v2 22/25] drm/i915/gen12: MBUS B credit change

[Lucas De Marchi]

From: Rodrigo Vivi <rodrigo.vivi@intel.com>

Previously, the recommended B credit for all platforms was 24 / number
of pipes, which would give 6 for newer platforms with 4 pipes. However 6
is not enough and we need 12 on these cases.

We also need a different BW credit for these platforms.

Cc: Arthur J Runyan <arthur.j.runyan@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 9ccf58ff4dba..9a5d04a2ab3e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6423,8 +6423,14 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
 	u32 val;
 
 	val = MBUS_DBOX_A_CREDIT(2);
-	val |= MBUS_DBOX_BW_CREDIT(1);
-	val |= MBUS_DBOX_B_CREDIT(8);
+
+	if (INTEL_GEN(dev_priv) >= 12) {
+		val |= MBUS_DBOX_BW_CREDIT(2);
+		val |= MBUS_DBOX_B_CREDIT(12);
+	} else {
+		val |= MBUS_DBOX_BW_CREDIT(1);
+		val |= MBUS_DBOX_B_CREDIT(8);
+	}
 
 	I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
 }
-- 
2.21.0

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[PATCH v2 23/25] drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization

[Lucas De Marchi]

According to the spec when initializing the display in TGL we should not
set PORT_CL_DW12 for the Aux channel of the combo PHYs. We will re-use the
power well hooks from ICL so just check for IS_TIGERLAKE() inside it.

Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index be3d4d1eece2..f040a74349df 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -458,8 +458,10 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
 	val = I915_READ(regs->driver);
 	I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
 
-	val = I915_READ(ICL_PORT_CL_DW12(port));
-	I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX);
+	if (!IS_TIGERLAKE(dev_priv)) {
+		val = I915_READ(ICL_PORT_CL_DW12(port));
+		I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX);
+	}
 
 	hsw_wait_for_power_well_enable(dev_priv, power_well);
 
@@ -486,8 +488,10 @@ icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
 	enum port port = ICL_AUX_PW_TO_PORT(pw_idx);
 	u32 val;
 
-	val = I915_READ(ICL_PORT_CL_DW12(port));
-	I915_WRITE(ICL_PORT_CL_DW12(port), val & ~ICL_LANE_ENABLE_AUX);
+	if (!IS_TIGERLAKE(dev_priv)) {
+		val = I915_READ(ICL_PORT_CL_DW12(port));
+		I915_WRITE(ICL_PORT_CL_DW12(port), val & ~ICL_LANE_ENABLE_AUX);
+	}
 
 	val = I915_READ(regs->driver);
 	I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
-- 
2.21.0

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[PATCH v2 24/25] drm/i915/tgl: Add DPLL registers

[Lucas De Marchi]

On TGL the port programming for combophy is very similar to ICL, so
adapt the callers to possibly use the different register values.

Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 24 +++++++++++++++----
 drivers/gpu/drm/i915/i915_reg.h               | 15 ++++++++++++
 2 files changed, 34 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index ae1c552d7afb..330b42a1f54e 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3113,8 +3113,13 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
 	if (!(val & PLL_ENABLE))
 		goto out;
 
-	hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
-	hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
+	if (INTEL_GEN(dev_priv) >= 12) {
+		hw_state->cfgcr0 = I915_READ(TGL_DPLL_CFGCR0(id));
+		hw_state->cfgcr1 = I915_READ(TGL_DPLL_CFGCR1(id));
+	} else {
+		hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
+		hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
+	}
 
 	ret = true;
 out:
@@ -3148,10 +3153,19 @@ static void icl_dpll_write(struct drm_i915_private *dev_priv,
 {
 	struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
 	const enum intel_dpll_id id = pll->info->id;
+	i915_reg_t cfgcr0_reg, cfgcr1_reg;
+
+	if (INTEL_GEN(dev_priv) >= 12) {
+		cfgcr0_reg = TGL_DPLL_CFGCR0(id);
+		cfgcr1_reg = TGL_DPLL_CFGCR1(id);
+	} else {
+		cfgcr0_reg = ICL_DPLL_CFGCR0(id);
+		cfgcr1_reg = ICL_DPLL_CFGCR1(id);
+	}
 
-	I915_WRITE(ICL_DPLL_CFGCR0(id), hw_state->cfgcr0);
-	I915_WRITE(ICL_DPLL_CFGCR1(id), hw_state->cfgcr1);
-	POSTING_READ(ICL_DPLL_CFGCR1(id));
+	I915_WRITE(cfgcr0_reg, hw_state->cfgcr0);
+	I915_WRITE(cfgcr1_reg, hw_state->cfgcr1);
+	POSTING_READ(cfgcr1_reg);
 }
 
 static void icl_mg_pll_write(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fbcc7981c8c4..84c04ea67ec8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -242,6 +242,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define _MMIO_PIPE3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
 #define _MMIO_PORT3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
 #define _MMIO_PHY3(phy, a, b, c)	_MMIO(_PHY3(phy, a, b, c))
+#define _MMIO_PLL3(pll, a, b, c)	_MMIO(_PICK(pll, a, b, c))
 
 /*
  * Device info offset array based helpers for groups of registers with unevenly
@@ -9958,6 +9959,20 @@ enum skl_power_gate {
 #define ICL_DPLL_CFGCR1(pll)		_MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \
 						  _ICL_DPLL1_CFGCR1)
 
+#define _TGL_DPLL0_CFGCR0		0x164284
+#define _TGL_DPLL1_CFGCR0		0x16428C
+#define _TGL_TBTPLL_CFGCR0		0x16429C
+#define TGL_DPLL_CFGCR0(pll)		_MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
+						  _TGL_DPLL1_CFGCR0, \
+						  _TGL_TBTPLL_CFGCR0)
+
+#define _TGL_DPLL0_CFGCR1		0x164288
+#define _TGL_DPLL1_CFGCR1		0x164290
+#define _TGL_TBTPLL_CFGCR1		0x1642A0
+#define TGL_DPLL_CFGCR1(pll)		_MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
+						   _TGL_DPLL1_CFGCR1, \
+						   _TGL_TBTPLL_CFGCR1)
+
 /* BXT display engine PLL */
 #define BXT_DE_PLL_CTL			_MMIO(0x6d000)
 #define   BXT_DE_PLL_RATIO(x)		(x)	/* {60,65,100} * 19.2MHz */
-- 
2.21.0

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[PATCH v2 25/25] drm/i915/tgl: Update DPLL clock reference register

[Lucas De Marchi]

From: José Roberto de Souza <jose.souza@intel.com>

This register definition changed from ICL and has now another meaning.
Use the right bits on TGL.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 8 ++++++--
 drivers/gpu/drm/i915/i915_reg.h               | 1 +
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 330b42a1f54e..9793039485e5 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2597,8 +2597,12 @@ static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
 	cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params.qdiv_ratio) |
 		 DPLL_CFGCR1_QDIV_MODE(pll_params.qdiv_mode) |
 		 DPLL_CFGCR1_KDIV(pll_params.kdiv) |
-		 DPLL_CFGCR1_PDIV(pll_params.pdiv) |
-		 DPLL_CFGCR1_CENTRAL_FREQ_8400;
+		 DPLL_CFGCR1_PDIV(pll_params.pdiv);
+
+	if (INTEL_GEN(dev_priv) >= 12)
+		cfgcr1 |= TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL;
+	else
+		cfgcr1 |= DPLL_CFGCR1_CENTRAL_FREQ_8400;
 
 	memset(pll_state, 0, sizeof(*pll_state));
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 84c04ea67ec8..a244e8158aee 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9947,6 +9947,7 @@ enum skl_power_gate {
 #define  DPLL_CFGCR1_PDIV_7		(8 << 2)
 #define  DPLL_CFGCR1_CENTRAL_FREQ	(3 << 0)
 #define  DPLL_CFGCR1_CENTRAL_FREQ_8400	(3 << 0)
+#define  TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL	(0 << 0)
 #define CNL_DPLL_CFGCR1(pll)		_MMIO_PLL(pll, _CNL_DPLL0_CFGCR1, _CNL_DPLL1_CFGCR1)
 
 #define _ICL_DPLL0_CFGCR0		0x164000
-- 
2.21.0

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✗ Fi.CI.CHECKPATCH: warning for Initial support for Tiger Lake (rev2)

[Patchwork]

== Series Details ==

Series: Initial support for Tiger Lake (rev2)
URL   : https://patchwork.freedesktop.org/series/62726/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
00d88902cdbe drm/i915: Add 4th pipe and transcoder
1957212e1a06 drm/i915/tgl: add initial Tiger Lake definitions
f090ff212c09 drm/i915/tgl: Introduce Tiger Lake PCH
5bae69ddf724 drm/i915/tgl: Add TGL PCH detection in virtualized environment
2357168b2a25 drm/i915/tgl: Add TGL PCI IDs
-:32: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#32: FILE: include/drm/i915_pciids.h:587:
+#define INTEL_TGL_12_IDS(info) \
+	INTEL_VGA_DEVICE(0x9A49, info), \
+	INTEL_VGA_DEVICE(0x9A40, info), \
+	INTEL_VGA_DEVICE(0x9A59, info), \
+	INTEL_VGA_DEVICE(0x9A60, info), \
+	INTEL_VGA_DEVICE(0x9A68, info), \
+	INTEL_VGA_DEVICE(0x9A70, info), \
+	INTEL_VGA_DEVICE(0x9A78, info)

-:32: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#32: FILE: include/drm/i915_pciids.h:587:
+#define INTEL_TGL_12_IDS(info) \
+	INTEL_VGA_DEVICE(0x9A49, info), \
+	INTEL_VGA_DEVICE(0x9A40, info), \
+	INTEL_VGA_DEVICE(0x9A59, info), \
+	INTEL_VGA_DEVICE(0x9A60, info), \
+	INTEL_VGA_DEVICE(0x9A68, info), \
+	INTEL_VGA_DEVICE(0x9A70, info), \
+	INTEL_VGA_DEVICE(0x9A78, info)

total: 1 errors, 0 warnings, 1 checks, 21 lines checked
ff15c4352fcc x86/gpu: add TGL stolen memory support
2e99be826cae drm/i915/tgl: Check if pipe D is fused
c66cb70352e9 drm/i915/tgl: use TRANSCODER_EDP_VDSC on transcoder A
48e70eb0a8fd drm/i915/tgl: Add power well support
ce8d3b70dd79 drm/i915/tgl: Add power well to support 4th pipe
d93d40c8620e drm/i915/tgl: Add new pll ids
6f0b3408f127 drm/i915/tgl: Add pll manager
0c85ba787405 drm/i915/tgl: Add additional ports for Tiger Lake
9c0c1f90cc5b drm/i915/tgl: update ddi/tc clock_off bits
-:24: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'port' - possible side-effects?
#24: FILE: drivers/gpu/drm/i915/i915_reg.h:9726:
+#define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port)	(1 << ((port) == PORT_C ? 24 : \
+						       (port) + 10))

-:26: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'tc_port' - possible side-effects?
#26: FILE: drivers/gpu/drm/i915/i915_reg.h:9728:
+#define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)	(1 << ((tc_port) < PORT_TC4 ? \
+						       (tc_port) + 12 : \
+						       (tc_port) - PORT_TC4 + 21))

total: 0 errors, 0 warnings, 2 checks, 14 lines checked
480ad7f760d3 drm/i915/tgl: Add gmbus gpio pin to port mapping
02eb68e95124 drm/i915/tgl: port to ddc pin mapping
515bc804c4ae drm/i915/tgl: select correct bit for port select
8ccbd571ebbe drm/i915/tgl: extend intel_port_is_combophy/tc
dc4c3dc34108 drm/i915/tgl: init ddi port A-C for Tiger Lake
6c6c34e25091 drm/i915/tgl: Add vbt value mapping for DDC Bus pin
2a4b9d250782 drm/i915/tgl: apply Display WA #1178 to fix type C dongles
ce6203f8c68e drm/i915/gen12: MBUS B credit change
281046dee43c drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization
47bbfafa8cfc drm/i915/tgl: Add DPLL registers
0482935d29fe drm/i915/tgl: Update DPLL clock reference register

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✓ Fi.CI.BAT: success for Initial support for Tiger Lake (rev2)

[Patchwork]

== Series Details ==

Series: Initial support for Tiger Lake (rev2)
URL   : https://patchwork.freedesktop.org/series/62726/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6433 -> Patchwork_13574
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13574/

Known issues
------------

  Here are the changes found in Patchwork_13574 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_mmap_gtt@basic-small-bo-tiledx:
    - fi-icl-u3:          [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6433/fi-icl-u3/igt@gem_mmap_gtt@basic-small-bo-tiledx.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13574/fi-icl-u3/igt@gem_mmap_gtt@basic-small-bo-tiledx.html

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s4-devices:
    - fi-blb-e6850:       [INCOMPLETE][3] ([fdo#107718]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6433/fi-blb-e6850/igt@gem_exec_suspend@basic-s4-devices.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13574/fi-blb-e6850/igt@gem_exec_suspend@basic-s4-devices.html

  
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724


Participating hosts (53 -> 47)
------------------------------

  Additional (1): fi-icl-guc 
  Missing    (7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper 


Build changes
-------------

  * Linux: CI_DRM_6433 -> Patchwork_13574

  CI_DRM_6433: 6da10e343bc0d479ab208c4c291bab18ee11d1ea @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5092: 2a66ae6626d5583240509f84117d1345a799b75a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13574: 0482935d29fee26860b43eab8e6c6efcb40632b5 @ git://anongit.freedesktop.org/gfx-ci/linux


== Kernel 32bit build ==

Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13574/build_32bit.log

  CALL    scripts/checksyscalls.sh
  CALL    scripts/atomic/check-atomics.sh
  CHK     include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready  (#1)
  Building modules, stage 2.
  MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1287: recipe for target 'modules' failed
make: *** [modules] Error 2


== Linux commits ==

0482935d29fe drm/i915/tgl: Update DPLL clock reference register
47bbfafa8cfc drm/i915/tgl: Add DPLL registers
281046dee43c drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization
ce6203f8c68e drm/i915/gen12: MBUS B credit change
2a4b9d250782 drm/i915/tgl: apply Display WA #1178 to fix type C dongles
6c6c34e25091 drm/i915/tgl: Add vbt value mapping for DDC Bus pin
dc4c3dc34108 drm/i915/tgl: init ddi port A-C for Tiger Lake
8ccbd571ebbe drm/i915/tgl: extend intel_port_is_combophy/tc
515bc804c4ae drm/i915/tgl: select correct bit for port select
02eb68e95124 drm/i915/tgl: port to ddc pin mapping
480ad7f760d3 drm/i915/tgl: Add gmbus gpio pin to port mapping
9c0c1f90cc5b drm/i915/tgl: update ddi/tc clock_off bits
0c85ba787405 drm/i915/tgl: Add additional ports for Tiger Lake
6f0b3408f127 drm/i915/tgl: Add pll manager
d93d40c8620e drm/i915/tgl: Add new pll ids
ce8d3b70dd79 drm/i915/tgl: Add power well to support 4th pipe
48e70eb0a8fd drm/i915/tgl: Add power well support
c66cb70352e9 drm/i915/tgl: use TRANSCODER_EDP_VDSC on transcoder A
2e99be826cae drm/i915/tgl: Check if pipe D is fused
ff15c4352fcc x86/gpu: add TGL stolen memory support
2357168b2a25 drm/i915/tgl: Add TGL PCI IDs
5bae69ddf724 drm/i915/tgl: Add TGL PCH detection in virtualized environment
f090ff212c09 drm/i915/tgl: Introduce Tiger Lake PCH
1957212e1a06 drm/i915/tgl: add initial Tiger Lake definitions
00d88902cdbe drm/i915: Add 4th pipe and transcoder

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13574/
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Re: [PATCH v2 08/25] drm/i915/tgl: use TRANSCODER_EDP_VDSC on transcoder A

[Souza, Jose]

On Mon, 2019-07-08 at 16:16 -0700, Lucas De Marchi wrote:
> From: José Roberto de Souza <jose.souza@intel.com>
> 
> On TGL the special EDP transcoder is gone and it should be handled by
> transcoder A.
> 
> v2 (Lucas):
>   - Reuse POWER_DOMAIN_TRANSCODER_EDP_VDSC (suggested by Ville)
>   - Use crtc->dev since new_crtc_state->state may be NULL on atomic
>     commit (suggested by Maarten)

As we are reusing would be nice also rename it to something like:
POWER_DOMAIN_TRANSCODER_VDSC_PW2
POWER_DOMAIN_LOW_POWER_TRANSCODER_VDSC /
POWER_DOMAIN_LP_TRANSCODER_VDSC

> 
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_vdsc.c | 9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index ffec807b8960..c27912f552f0 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -459,16 +459,19 @@ int intel_dp_compute_dsc_params(struct intel_dp
> *intel_dp,
>  enum intel_display_power_domain
>  intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
>  {
> +	struct drm_i915_private *i915 = to_i915(crtc_state->base.crtc-
> >dev);
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>  
>  	/*
> -	 * On ICL VDSC/joining for eDP transcoder uses a separate power
> well PW2
> -	 * This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
> +	 * On ICL+ VDSC/joining for eDP/A transcoder uses a separate
> power well
> +	 * PW2. This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power
> domain.
>  	 * For any other transcoder, VDSC/joining uses the power well
> associated
>  	 * with the pipe/transcoder in use. Hence another reference on
> the
>  	 * transcoder power domain will suffice.
>  	 */
> -	if (cpu_transcoder == TRANSCODER_EDP)
> +	if (INTEL_GEN(i915) >= 12 && cpu_transcoder == TRANSCODER_A)
> +		return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
> +	else if (cpu_transcoder == TRANSCODER_EDP)
>  		return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
>  	else
>  		return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
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Re: [PATCH v2 05/25] drm/i915/tgl: Add TGL PCI IDs

[Rodrigo Vivi]

On Mon, Jul 08, 2019 at 04:16:09PM -0700, Lucas De Marchi wrote:
> Current list of PCI IDs for Tiger Lake.
> 
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_pci.c |  1 +
>  include/drm/i915_pciids.h       | 10 ++++++++++
>  2 files changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index da926485845d..e83c94cf2744 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -865,6 +865,7 @@ static const struct pci_device_id pciidlist[] = {
>  	INTEL_CNL_IDS(&intel_cannonlake_info),
>  	INTEL_ICL_11_IDS(&intel_icelake_11_info),
>  	INTEL_EHL_IDS(&intel_elkhartlake_info),
> +	INTEL_TGL_12_IDS(&intel_tigerlake_12_info),
>  	{0, 0, 0}
>  };
>  MODULE_DEVICE_TABLE(pci, pciidlist);
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 6c342ac470c8..a70c982ddff9 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -583,4 +583,14 @@
>  	INTEL_VGA_DEVICE(0x4551, info), \
>  	INTEL_VGA_DEVICE(0x4541, info)
>  
> +/* TGL */
> +#define INTEL_TGL_12_IDS(info) \
> +	INTEL_VGA_DEVICE(0x9A49, info), \
> +	INTEL_VGA_DEVICE(0x9A40, info), \
> +	INTEL_VGA_DEVICE(0x9A59, info), \
> +	INTEL_VGA_DEVICE(0x9A60, info), \
> +	INTEL_VGA_DEVICE(0x9A68, info), \
> +	INTEL_VGA_DEVICE(0x9A70, info), \
> +	INTEL_VGA_DEVICE(0x9A78, info)
> +
>  #endif /* _I915_PCIIDS_H */
> -- 
> 2.21.0
> 
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Re: [PATCH v2 10/25] drm/i915/tgl: Add power well to support 4th pipe

[Rodrigo Vivi]

On Mon, Jul 08, 2019 at 04:16:14PM -0700, Lucas De Marchi wrote:
> From: Mika Kahola <mika.kahola@intel.com>
> 
> Add power well 5 to support 4th pipe and transcoder on TGL.
> 
> Cc: James Ausmus <james.ausmus@intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  .../drm/i915/display/intel_display_power.c    | 30 ++++++++++++++++---
>  .../drm/i915/display/intel_display_power.h    |  3 ++
>  drivers/gpu/drm/i915/i915_reg.h               |  3 +-
>  3 files changed, 31 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index c3f42169831f..455f9aab188d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -37,18 +37,24 @@ intel_display_power_domain_str(struct drm_i915_private *i915,
>  		return "PIPE_B";
>  	case POWER_DOMAIN_PIPE_C:
>  		return "PIPE_C";
> +	case POWER_DOMAIN_PIPE_D:
> +		return "PIPE_D";
>  	case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
>  		return "PIPE_A_PANEL_FITTER";
>  	case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
>  		return "PIPE_B_PANEL_FITTER";
>  	case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
>  		return "PIPE_C_PANEL_FITTER";
> +	case POWER_DOMAIN_PIPE_D_PANEL_FITTER:
> +		return "PIPE_D_PANEL_FITTER";
>  	case POWER_DOMAIN_TRANSCODER_A:
>  		return "TRANSCODER_A";
>  	case POWER_DOMAIN_TRANSCODER_B:
>  		return "TRANSCODER_B";
>  	case POWER_DOMAIN_TRANSCODER_C:
>  		return "TRANSCODER_C";
> +	case POWER_DOMAIN_TRANSCODER_D:
> +		return "TRANSCODER_D";
>  	case POWER_DOMAIN_TRANSCODER_EDP:
>  		return "TRANSCODER_EDP";
>  	case POWER_DOMAIN_TRANSCODER_EDP_VDSC:
> @@ -2451,7 +2457,6 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
>   * - DDI_A
>   * - FBC
>   */
> -/* TODO: TGL_PW_5_POWER_DOMAINS: PIPE_D */
>  #define ICL_PW_4_POWER_DOMAINS (			\
>  	BIT_ULL(POWER_DOMAIN_PIPE_C) |			\
>  	BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |	\
> @@ -2539,7 +2544,13 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
>  #define ICL_AUX_TBT4_IO_POWER_DOMAINS (			\
>  	BIT_ULL(POWER_DOMAIN_AUX_TBT4))
>  
> +#define TGL_PW_5_POWER_DOMAINS (			\
> +	BIT_ULL(POWER_DOMAIN_PIPE_D) |			\
> +	BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) |     \
> +	BIT_ULL(POWER_DOMAIN_INIT))
> +
>  #define TGL_PW_4_POWER_DOMAINS (			\
> +	TGL_PW_5_POWER_DOMAINS |			\

why?

>  	BIT_ULL(POWER_DOMAIN_PIPE_C) |			\
>  	BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |	\
>  	BIT_ULL(POWER_DOMAIN_INIT))
> @@ -2549,7 +2560,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
>  	BIT_ULL(POWER_DOMAIN_PIPE_B) |			\
>  	BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |		\
>  	BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |		\
> -	/* TODO: TRANSCODER_D */			\
> +	BIT_ULL(POWER_DOMAIN_TRANSCODER_D) |		\
>  	BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |	\
>  	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_LANES) |	\
>  	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_IO) |		\
> @@ -3882,7 +3893,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
>  	},
>  	{
>  		.name = "power well 4",
> -		.domains = ICL_PW_4_POWER_DOMAINS,
> +		.domains = TGL_PW_4_POWER_DOMAINS,

why?

>  		.ops = &hsw_power_well_ops,
>  		.id = DISP_PW_ID_NONE,
>  		{
> @@ -3892,7 +3903,18 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
>  			.hsw.irq_pipe_mask = BIT(PIPE_C),
>  		}
>  	},
> -	/* TODO: power well 5 for pipe D */
> +	{
> +		.name = "power well 5",
> +		.domains = TGL_PW_5_POWER_DOMAINS,
> +		.ops = &hsw_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &hsw_power_well_regs,
> +			.hsw.idx = TGL_PW_CTL_IDX_PW_5,
> +			.hsw.has_fuses = true,
> +			.hsw.irq_pipe_mask = BIT(PIPE_D),
> +		},
> +	},
>  };
>  
>  static int
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
> index 86afd70c1fb2..ebb397e330ea 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -18,12 +18,15 @@ enum intel_display_power_domain {
>  	POWER_DOMAIN_PIPE_A,
>  	POWER_DOMAIN_PIPE_B,
>  	POWER_DOMAIN_PIPE_C,
> +	POWER_DOMAIN_PIPE_D,
>  	POWER_DOMAIN_PIPE_A_PANEL_FITTER,
>  	POWER_DOMAIN_PIPE_B_PANEL_FITTER,
>  	POWER_DOMAIN_PIPE_C_PANEL_FITTER,
> +	POWER_DOMAIN_PIPE_D_PANEL_FITTER,
>  	POWER_DOMAIN_TRANSCODER_A,
>  	POWER_DOMAIN_TRANSCODER_B,
>  	POWER_DOMAIN_TRANSCODER_C,
> +	POWER_DOMAIN_TRANSCODER_D,
>  	POWER_DOMAIN_TRANSCODER_EDP,
>  	POWER_DOMAIN_TRANSCODER_EDP_VDSC,
>  	POWER_DOMAIN_TRANSCODER_DSI_A,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f59cb5c45c34..5ca74eca05a4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9147,7 +9147,8 @@ enum {
>  #define   GLK_PW_CTL_IDX_DDI_A			1
>  #define   SKL_PW_CTL_IDX_MISC_IO		0
>  
> -/* ICL - power wells */
> +/* ICL/TGL - power wells */
> +#define   TGL_PW_CTL_IDX_PW_5			4
>  #define   ICL_PW_CTL_IDX_PW_4			3
>  #define   ICL_PW_CTL_IDX_PW_3			2
>  #define   ICL_PW_CTL_IDX_PW_2			1
> -- 
> 2.21.0
> 
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Re: [PATCH v2 03/25] drm/i915/tgl: Introduce Tiger Lake PCH

[Rodrigo Vivi]

On Mon, Jul 08, 2019 at 04:16:07PM -0700, Lucas De Marchi wrote:
> From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> 
> Add the enum additions to TGP.
> 
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: David Weinehall <david.weinehall@intel.com>
> Cc: James Ausmus <james.ausmus@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.c | 4 ++++
>  drivers/gpu/drm/i915/i915_drv.h | 3 +++
>  2 files changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 794c6814a6d0..bcedd2d8e267 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -224,6 +224,10 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
>  		DRM_DEBUG_KMS("Found Mule Creek Canyon PCH\n");
>  		WARN_ON(!IS_ELKHARTLAKE(dev_priv));
>  		return PCH_MCC;
> +	case INTEL_PCH_TGP_DEVICE_ID_TYPE:
> +		DRM_DEBUG_KMS("Found Tiger Lake LP PCH\n");
> +		WARN_ON(!IS_TIGERLAKE(dev_priv));
> +		return PCH_TGP;
>  	default:
>  		return PCH_NONE;
>  	}
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 2508b1222d2c..3248f9959227 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -536,6 +536,7 @@ enum intel_pch {
>  	PCH_CNP,        /* Cannon/Comet Lake PCH */
>  	PCH_ICP,	/* Ice Lake PCH */
>  	PCH_MCC,        /* Mule Creek Canyon PCH */
> +	PCH_TGP,	/* Tiger Lake PCH */
>  };
>  
>  #define QUIRK_LVDS_SSC_DISABLE (1<<1)
> @@ -2322,6 +2323,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  #define INTEL_PCH_ICP_DEVICE_ID_TYPE		0x3480
>  #define INTEL_PCH_MCC_DEVICE_ID_TYPE		0x4B00
>  #define INTEL_PCH_MCC2_DEVICE_ID_TYPE		0x3880
> +#define INTEL_PCH_TGP_DEVICE_ID_TYPE		0xA080
>  #define INTEL_PCH_P2X_DEVICE_ID_TYPE		0x7100
>  #define INTEL_PCH_P3X_DEVICE_ID_TYPE		0x7000
>  #define INTEL_PCH_QEMU_DEVICE_ID_TYPE		0x2900 /* qemu q35 has 2918 */
> @@ -2329,6 +2331,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
>  #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
>  #define HAS_PCH_MCC(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MCC)
> +#define HAS_PCH_TGP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_TGP)
>  #define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
>  #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
>  #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
> -- 
> 2.21.0
> 
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Re: [PATCH v2 16/25] drm/i915/tgl: port to ddc pin mapping

[Rodrigo Vivi]

On Mon, Jul 08, 2019 at 04:16:20PM -0700, Lucas De Marchi wrote:
> From: Mahesh Kumar <mahesh1.kumar@intel.com>
> 
> Create a helper function to get ddc pin according to port number.

Could you please explain why we can't simply reuse the icl one?

I couldn't find a new table for tgl on bspec...

> 
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_hdmi.c | 16 +++++++++++++++-
>  1 file changed, 15 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 0ebec69bbbfc..3b33e7626d7c 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -2981,6 +2981,18 @@ static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
>  	return ddc_pin;
>  }
>  
> +static u8 tgp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
> +			      enum port port)
> +{
> +	if (intel_port_is_combophy(dev_priv, port))
> +		return GMBUS_PIN_1_BXT + port;
> +	else if (intel_port_is_tc(dev_priv, port))
> +		return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port);

okay, this seems better than the table we have on icl func,
but couldn't we just change the icl one?

> +
> +	WARN(1, "Unknown port:%c\n", port_name(port));
> +	return GMBUS_PIN_2_BXT;
> +}
> +
>  static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
>  			      enum port port)
>  {
> @@ -3017,7 +3029,9 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
>  		return info->alternate_ddc_pin;
>  	}
>  
> -	if (HAS_PCH_MCC(dev_priv))
> +	if (HAS_PCH_TGP(dev_priv))
> +		ddc_pin = tgp_port_to_ddc_pin(dev_priv, port);
> +	else if (HAS_PCH_MCC(dev_priv))
>  		ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
>  	else if (HAS_PCH_ICP(dev_priv))
>  		ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
> -- 
> 2.21.0
> 
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Re: [PATCH v2 21/25] drm/i915/tgl: apply Display WA #1178 to fix type C dongles

[Rodrigo Vivi]

On Mon, Jul 08, 2019 at 04:16:25PM -0700, Lucas De Marchi wrote:
> Add port C to workaround to cover Tiger Lake.
> 
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_power.c | 11 ++++++++---
>  drivers/gpu/drm/i915/i915_reg.h                    |  4 +++-
>  2 files changed, 11 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 455f9aab188d..be3d4d1eece2 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -453,6 +453,7 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
>  	int pw_idx = power_well->desc->hsw.idx;
>  	enum port port = ICL_AUX_PW_TO_PORT(pw_idx);
>  	u32 val;
> +	int wa_idx_max;
>  
>  	val = I915_READ(regs->driver);
>  	I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
> @@ -462,9 +463,13 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
>  
>  	hsw_wait_for_power_well_enable(dev_priv, power_well);
>  
> -	/* Display WA #1178: icl */
> -	if (IS_ICELAKE(dev_priv) &&
> -	    pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B &&
> +	/* Display WA #1178: icl, tgl */
> +	if (IS_TIGERLAKE(dev_priv))
> +		wa_idx_max = ICL_PW_CTL_IDX_AUX_C;
> +	else
> +		wa_idx_max = ICL_PW_CTL_IDX_AUX_B;
> +
> +	if (pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= wa_idx_max &&
>  	    !intel_bios_is_port_edp(dev_priv, port)) {
>  		val = I915_READ(ICL_AUX_ANAOVRD1(pw_idx));
>  		val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ccfb95e2aa03..fbcc7981c8c4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9246,9 +9246,11 @@ enum skl_power_gate {
>  #define _ICL_AUX_REG_IDX(pw_idx)	((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
>  #define _ICL_AUX_ANAOVRD1_A		0x162398
>  #define _ICL_AUX_ANAOVRD1_B		0x6C398
> +#define _TGL_AUX_ANAOVRD1_C		0x160398
>  #define ICL_AUX_ANAOVRD1(pw_idx)	_MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \
>  						    _ICL_AUX_ANAOVRD1_A, \
> -						    _ICL_AUX_ANAOVRD1_B))
> +						    _ICL_AUX_ANAOVRD1_B, \
> +						    _TGL_AUX_ANAOVRD1_C))
>  #define   ICL_AUX_ANAOVRD1_LDO_BYPASS	(1 << 7)
>  #define   ICL_AUX_ANAOVRD1_ENABLE	(1 << 0)
>  
> -- 
> 2.21.0
> 
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Re: [PATCH v2 12/25] drm/i915/tgl: Add pll manager

[Rodrigo Vivi]

On Mon, Jul 08, 2019 at 04:16:16PM -0700, Lucas De Marchi wrote:
> From: Vandita Kulkarni <vandita.kulkarni@intel.com>
> 
> Add a new pll array for Tiger Lake. The TC pll functions for type C will
> be covered in later patches after its phy is implemented.
> 
> Cc: Madhav Chauhan <madhav.chauhan@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 19 ++++++++++++++++++-
>  1 file changed, 18 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 67cfe836286e..ae1c552d7afb 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -3455,6 +3455,21 @@ static const struct intel_dpll_mgr ehl_pll_mgr = {
>  	.dump_hw_state = icl_dump_hw_state,
>  };
>  
> +static const struct dpll_info tgl_plls[] = {
> +	{ "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0,  0 },
> +	{ "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1,  0 },
> +	{ "TBT PLL",  &tbt_pll_funcs, DPLL_ID_ICL_TBTPLL, 0 },
> +	/* TODO: Add typeC plls */
> +	{ },
> +};
> +
> +static const struct intel_dpll_mgr tgl_pll_mgr = {
> +	.dpll_info = tgl_plls,
> +	.get_dplls = icl_get_dplls,
> +	.put_dplls = icl_put_dplls,
> +	.dump_hw_state = icl_dump_hw_state,
> +};
> +
>  /**
>   * intel_shared_dpll_init - Initialize shared DPLLs
>   * @dev: drm device
> @@ -3468,7 +3483,9 @@ void intel_shared_dpll_init(struct drm_device *dev)
>  	const struct dpll_info *dpll_info;
>  	int i;
>  
> -	if (IS_ELKHARTLAKE(dev_priv))
> +	if (INTEL_GEN(dev_priv) >= 12)
> +		dpll_mgr = &tgl_pll_mgr;
> +	else if (IS_ELKHARTLAKE(dev_priv))
>  		dpll_mgr = &ehl_pll_mgr;
>  	else if (INTEL_GEN(dev_priv) >= 11)
>  		dpll_mgr = &icl_pll_mgr;
> -- 
> 2.21.0
> 
> _______________________________________________
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH v2 05/25] drm/i915/tgl: Add TGL PCI IDs

[Kahola, Mika]

On Mon, 2019-07-08 at 16:16 -0700, Lucas De Marchi wrote:
> Current list of PCI IDs for Tiger Lake.
> 
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

As per BSPec #44455 the IDs seems correct.

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_pci.c |  1 +
>  include/drm/i915_pciids.h       | 10 ++++++++++
>  2 files changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_pci.c
> b/drivers/gpu/drm/i915/i915_pci.c
> index da926485845d..e83c94cf2744 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -865,6 +865,7 @@ static const struct pci_device_id pciidlist[] = {
>  	INTEL_CNL_IDS(&intel_cannonlake_info),
>  	INTEL_ICL_11_IDS(&intel_icelake_11_info),
>  	INTEL_EHL_IDS(&intel_elkhartlake_info),
> +	INTEL_TGL_12_IDS(&intel_tigerlake_12_info),
>  	{0, 0, 0}
>  };
>  MODULE_DEVICE_TABLE(pci, pciidlist);
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 6c342ac470c8..a70c982ddff9 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -583,4 +583,14 @@
>  	INTEL_VGA_DEVICE(0x4551, info), \
>  	INTEL_VGA_DEVICE(0x4541, info)
>  
> +/* TGL */
> +#define INTEL_TGL_12_IDS(info) \
> +	INTEL_VGA_DEVICE(0x9A49, info), \
> +	INTEL_VGA_DEVICE(0x9A40, info), \
> +	INTEL_VGA_DEVICE(0x9A59, info), \
> +	INTEL_VGA_DEVICE(0x9A60, info), \
> +	INTEL_VGA_DEVICE(0x9A68, info), \
> +	INTEL_VGA_DEVICE(0x9A70, info), \
> +	INTEL_VGA_DEVICE(0x9A78, info)
> +
>  #endif /* _I915_PCIIDS_H */
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Re: [PATCH v2 07/25] drm/i915/tgl: Check if pipe D is fused

[Kahola, Mika]

On Mon, 2019-07-08 at 16:16 -0700, Lucas De Marchi wrote:
> From: José Roberto de Souza <jose.souza@intel.com>
> 
> On Tiger Lake there is one more pipe - check if it's fused.
> 
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h          | 1 +
>  drivers/gpu/drm/i915/intel_device_info.c | 3 +++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 31c6c168dde2..08dc71e4b818 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7633,6 +7633,7 @@ enum {
>  #define SKL_DFSM_PIPE_A_DISABLE		(1 << 30)
>  #define SKL_DFSM_PIPE_B_DISABLE		(1 << 21)
>  #define SKL_DFSM_PIPE_C_DISABLE		(1 << 28)
> +#define TGL_DFSM_PIPE_D_DISABLE		(1 << 22)
>  
>  #define SKL_DSSM				_MMIO(0x51004)
>  #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz		(1 << 31)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> b/drivers/gpu/drm/i915/intel_device_info.c
> index e0d9a7a37994..f99c9fd497b2 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -938,6 +938,9 @@ void intel_device_info_runtime_init(struct
> drm_i915_private *dev_priv)
>  			enabled_mask &= ~BIT(PIPE_B);
>  		if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
>  			enabled_mask &= ~BIT(PIPE_C);
> +		if (INTEL_GEN(dev_priv) >= 12 &&
> +		    (dfsm & TGL_DFSM_PIPE_D_DISABLE))
> +			enabled_mask &= ~BIT(PIPE_D);
>  
>  		/*
>  		 * At least one pipe should be enabled and if there are
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Re: [PATCH v2 25/25] drm/i915/tgl: Update DPLL clock reference register

[Ville Syrjälä]

On Mon, Jul 08, 2019 at 04:16:29PM -0700, Lucas De Marchi wrote:
> From: José Roberto de Souza <jose.souza@intel.com>
> 
> This register definition changed from ICL and has now another meaning.
> Use the right bits on TGL.
> 
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 8 ++++++--
>  drivers/gpu/drm/i915/i915_reg.h               | 1 +
>  2 files changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 330b42a1f54e..9793039485e5 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -2597,8 +2597,12 @@ static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
>  	cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params.qdiv_ratio) |
>  		 DPLL_CFGCR1_QDIV_MODE(pll_params.qdiv_mode) |
>  		 DPLL_CFGCR1_KDIV(pll_params.kdiv) |
> -		 DPLL_CFGCR1_PDIV(pll_params.pdiv) |
> -		 DPLL_CFGCR1_CENTRAL_FREQ_8400;
> +		 DPLL_CFGCR1_PDIV(pll_params.pdiv);
> +
> +	if (INTEL_GEN(dev_priv) >= 12)
> +		cfgcr1 |= TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL;
> +	else
> +		cfgcr1 |= DPLL_CFGCR1_CENTRAL_FREQ_8400;
>  
>  	memset(pll_state, 0, sizeof(*pll_state));
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 84c04ea67ec8..a244e8158aee 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9947,6 +9947,7 @@ enum skl_power_gate {
>  #define  DPLL_CFGCR1_PDIV_7		(8 << 2)
>  #define  DPLL_CFGCR1_CENTRAL_FREQ	(3 << 0)
>  #define  DPLL_CFGCR1_CENTRAL_FREQ_8400	(3 << 0)
> +#define  TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL	(0 << 0)

I'd probably leave this out entirely if we're not going to define the
other values of thess bits.

Either way
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

>  #define CNL_DPLL_CFGCR1(pll)		_MMIO_PLL(pll, _CNL_DPLL0_CFGCR1, _CNL_DPLL1_CFGCR1)
>  
>  #define _ICL_DPLL0_CFGCR0		0x164000
> -- 
> 2.21.0

-- 
Ville Syrjälä
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Re: [PATCH v2 24/25] drm/i915/tgl: Add DPLL registers

[Ville Syrjälä]

On Mon, Jul 08, 2019 at 04:16:28PM -0700, Lucas De Marchi wrote:
> On TGL the port programming for combophy is very similar to ICL, so
> adapt the callers to possibly use the different register values.
> 
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 24 +++++++++++++++----
>  drivers/gpu/drm/i915/i915_reg.h               | 15 ++++++++++++
>  2 files changed, 34 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index ae1c552d7afb..330b42a1f54e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -3113,8 +3113,13 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
>  	if (!(val & PLL_ENABLE))
>  		goto out;
>  
> -	hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
> -	hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
> +	if (INTEL_GEN(dev_priv) >= 12) {
> +		hw_state->cfgcr0 = I915_READ(TGL_DPLL_CFGCR0(id));
> +		hw_state->cfgcr1 = I915_READ(TGL_DPLL_CFGCR1(id));
> +	} else {
> +		hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
> +		hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
> +	}
>  
>  	ret = true;
>  out:
> @@ -3148,10 +3153,19 @@ static void icl_dpll_write(struct drm_i915_private *dev_priv,
>  {
>  	struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
>  	const enum intel_dpll_id id = pll->info->id;
> +	i915_reg_t cfgcr0_reg, cfgcr1_reg;
> +
> +	if (INTEL_GEN(dev_priv) >= 12) {
> +		cfgcr0_reg = TGL_DPLL_CFGCR0(id);
> +		cfgcr1_reg = TGL_DPLL_CFGCR1(id);
> +	} else {
> +		cfgcr0_reg = ICL_DPLL_CFGCR0(id);
> +		cfgcr1_reg = ICL_DPLL_CFGCR1(id);
> +	}
>  
> -	I915_WRITE(ICL_DPLL_CFGCR0(id), hw_state->cfgcr0);
> -	I915_WRITE(ICL_DPLL_CFGCR1(id), hw_state->cfgcr1);
> -	POSTING_READ(ICL_DPLL_CFGCR1(id));
> +	I915_WRITE(cfgcr0_reg, hw_state->cfgcr0);
> +	I915_WRITE(cfgcr1_reg, hw_state->cfgcr1);
> +	POSTING_READ(cfgcr1_reg);
>  }
>  
>  static void icl_mg_pll_write(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fbcc7981c8c4..84c04ea67ec8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -242,6 +242,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define _MMIO_PIPE3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
>  #define _MMIO_PORT3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
>  #define _MMIO_PHY3(phy, a, b, c)	_MMIO(_PHY3(phy, a, b, c))
> +#define _MMIO_PLL3(pll, a, b, c)	_MMIO(_PICK(pll, a, b, c))
>  
>  /*
>   * Device info offset array based helpers for groups of registers with unevenly
> @@ -9958,6 +9959,20 @@ enum skl_power_gate {
>  #define ICL_DPLL_CFGCR1(pll)		_MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \
>  						  _ICL_DPLL1_CFGCR1)
>  
> +#define _TGL_DPLL0_CFGCR0		0x164284
> +#define _TGL_DPLL1_CFGCR0		0x16428C
> +#define _TGL_TBTPLL_CFGCR0		0x16429C

What about DPLL4?

In fact looks like the ICL counterparts are borked even for ehl DPLL4.

> +#define TGL_DPLL_CFGCR0(pll)		_MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
> +						  _TGL_DPLL1_CFGCR0, \
> +						  _TGL_TBTPLL_CFGCR0)
> +
> +#define _TGL_DPLL0_CFGCR1		0x164288
> +#define _TGL_DPLL1_CFGCR1		0x164290
> +#define _TGL_TBTPLL_CFGCR1		0x1642A0
> +#define TGL_DPLL_CFGCR1(pll)		_MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
> +						   _TGL_DPLL1_CFGCR1, \
> +						   _TGL_TBTPLL_CFGCR1)
> +
>  /* BXT display engine PLL */
>  #define BXT_DE_PLL_CTL			_MMIO(0x6d000)
>  #define   BXT_DE_PLL_RATIO(x)		(x)	/* {60,65,100} * 19.2MHz */
> -- 
> 2.21.0

-- 
Ville Syrjälä
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✓ Fi.CI.IGT: success for Initial support for Tiger Lake (rev2)

[Patchwork]

== Series Details ==

Series: Initial support for Tiger Lake (rev2)
URL   : https://patchwork.freedesktop.org/series/62726/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6433_full -> Patchwork_13574_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_13574_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_softpin@noreloc-s3:
    - shard-apl:          [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +2 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6433/shard-apl2/igt@gem_softpin@noreloc-s3.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13574/shard-apl7/igt@gem_softpin@noreloc-s3.html
    - shard-skl:          [PASS][3] -> [INCOMPLETE][4] ([fdo#104108])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6433/shard-skl3/igt@gem_softpin@noreloc-s3.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13574/shard-skl6/igt@gem_softpin@noreloc-s3.html

  * igt@gem_workarounds@suspend-resume-fd:
    - shard-iclb:         [PASS][5] -> [INCOMPLETE][6] ([fdo#107713])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6433/shard-iclb3/igt@gem_workarounds@suspend-resume-fd.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13574/shard-iclb3/igt@gem_workarounds@suspend-resume-fd.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-skl:          [PASS][7] -> [FAIL][8] ([fdo#105363])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6433/shard-skl8/igt@kms_flip@flip-vs-expired-vblank.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13574/shard-skl4/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack:
    - shard-skl:          [PASS][9] -> [FAIL][10] ([fdo#103167])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6433/shard-skl9/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13574/shard-skl8/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-iclb:         [PASS][11] -> [FAIL][12] ([fdo#103167]) +6 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6433/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13574/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-kbl:          [PASS][13] -> [DMESG-WARN][14] ([fdo#108566]) +4 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6433/shard-kbl2/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13574/shard-kbl2/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
    - shard-skl:          [PASS][15] -> [FAIL][16] ([fdo#108145])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6433/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13574/shard-skl8/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [PASS][17] -> [FAIL][18] ([fdo#108145] / [fdo#110403]) +1 similar issue
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6433/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13574/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_psr@psr2_cursor_mmap_gtt:
    - shard-iclb:         [PASS][19] -> [SKIP][20] ([fdo#109441])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6433/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_gtt.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13574/shard-iclb8/igt@kms_psr@psr2_cursor_mmap_gtt.html

  * igt@kms_setmode@basic:
    - shard-apl:          [PASS][21] -> [FAIL][22] ([fdo#99912])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6433/shard-apl4/igt@kms_setmode@basic.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13574/shard-apl2/igt@kms_setmode@basic.html

  * igt@perf@polling:
    - shard-skl:          [PASS][23] -> [FAIL][24] ([fdo#110728])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6433/shard-skl5/igt@perf@polling.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13574/shard-skl3/igt@perf@polling.html

  
#### Possible fixes ####

  * igt@gem_tiled_swapping@non-threaded:
    - shard-apl:          [DMESG-WARN][25] ([fdo#108686]) -> [PASS][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6433/shard-apl1/igt@gem_tiled_swapping@non-threaded.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13574/shard-apl2/igt@gem_tiled_swapping@non-threaded.html

  * igt@i915_pm_rps@min-max-config-loaded:
    - shard-iclb:         [FAIL][27] ([fdo#108059]) -> [PASS][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6433/shard-iclb2/igt@i915_pm_rps@min-max-config-loaded.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13574/shard-iclb8/igt@i915_pm_rps@min-max-config-loaded.html

  * igt@i915_suspend@debugfs-reader:
    - shard-kbl:          [DMESG-WARN][29] ([fdo#108566]) -> [PASS][30] +2 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6433/shard-kbl6/igt@i915_suspend@debugfs-reader.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13574/shard-kbl1/igt@i915_suspend@debugfs-reader.html

  * igt@i915_suspend@forcewake:
    - shard-apl:          [DMESG-WARN][31] ([fdo#108566]) -> [PASS][32] +1 similar issue
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6433/shard-apl2/igt@i915_suspend@forcewake.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13574/shard-apl6/igt@i915_suspend@forcewake.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
    - shard-glk:          [FAIL][33] ([fdo#104873]) -> [PASS][34] +1 similar issue
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6433/shard-glk5/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13574/shard-glk5/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html

  * igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled:
    - shard-skl:          [FAIL][35] ([fdo#103184] / [fdo#103232]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6433/shard-skl9/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13574/shard-skl8/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-skl:          [FAIL][37] ([fdo#105363]) -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6433/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13574/shard-skl5/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-skl:          [INCOMPLETE][39] ([fdo#109507]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6433/shard-skl8/igt@kms_flip@flip-vs-suspend-interruptible.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13574/shard-skl4/igt@kms_flip@flip-vs-suspend-interruptible.html
    - shard-hsw:          [INCOMPLETE][41] ([fdo#103540]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6433/shard-hsw2/igt@kms_flip@flip-vs-suspend-interruptible.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13574/shard-hsw2/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt:
    - shard-snb:          [SKIP][43] ([fdo#109271]) -> [PASS][44] +1 similar issue
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6433/shard-snb6/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13574/shard-snb5/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite:
    - shard-iclb:         [FAIL][45] ([fdo#103167]) -> [PASS][46] +5 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6433/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13574/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu:
    - shard-iclb:         [INCOMPLETE][47] ([fdo#106978] / [fdo#107713]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6433/shard-iclb1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13574/shard-iclb2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html

  * igt@kms_psr2_su@page_flip:
    - shard-iclb:         [SKIP][49] ([fdo#109642] / [fdo#111068]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6433/shard-iclb3/igt@kms_psr2_su@page_flip.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13574/shard-iclb2/igt@kms_psr2_su@page_flip.html

  * igt@kms_psr@psr2_sprite_plane_onoff:
    - shard-iclb:         [SKIP][51] ([fdo#109441]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6433/shard-iclb8/igt@kms_psr@psr2_sprite_plane_onoff.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13574/shard-iclb2/igt@kms_psr@psr2_sprite_plane_onoff.html

  * igt@perf@oa-exponents:
    - shard-glk:          [FAIL][53] ([fdo#105483]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6433/shard-glk4/igt@perf@oa-exponents.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13574/shard-glk2/igt@perf@oa-exponents.html

  
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#104873]: https://bugs.freedesktop.org/show_bug.cgi?id=104873
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#105483]: https://bugs.freedesktop.org/show_bug.cgi?id=105483
  [fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#108059]: https://bugs.freedesktop.org/show_bug.cgi?id=108059
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
  [fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_6433 -> Patchwork_13574

  CI_DRM_6433: 6da10e343bc0d479ab208c4c291bab18ee11d1ea @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5092: 2a66ae6626d5583240509f84117d1345a799b75a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13574: 0482935d29fee26860b43eab8e6c6efcb40632b5 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13574/
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Re: [PATCH v2 09/25] drm/i915/tgl: Add power well support

[Ville Syrjälä]

On Mon, Jul 08, 2019 at 04:16:13PM -0700, Lucas De Marchi wrote:
> From: Imre Deak <imre.deak@intel.com>
> 
> The patch adds the new power wells introduced by TGL (GEN 12) and
> maps these to existing/new power domains. The changes for GEN 12 wrt
> to GEN 11 are the following:
> 
> - Transcoder#EDP removed from power well#1 (Transcoder#A used in
>   low-power mode instead)
> - Transcoder#A is now backed by power well#1 instead of power well#3
> - The DDI#B/C combo PHY ports are now backed by power well#1 instead of
>   power well#3
> - New power well#5 added for pipe#D functionality (TODO)
> - 2 additional TC ports (TC#5-6) backed by power well#3, 2 port
>   specific IO power wells (only for the non-TBT modes) and 4 port
>   specific AUX power wells (2-2 for TBT vs. non-TBT modes)
> - Power well#2 backs now VDSC/joining for pipe#A instead of VDSC for
>   eDP and MIPI DSI (TODO)
> 
> On TGL Port DDI#C changed to be a combo PHY (native DP/HDMI) and
> BSpec has renamed ports DDI#D-F to TC#4-6 respectively. Thus on ICL we
> have the following naming for ports:
> 
> - Combo PHYs (native DP/HDMI):
>   DDI#A-B
> - TBT/non-TBT (TC altmode, native DP/HDMI) PHYs:
>   DDI#C-F
> 
> Starting from GEN 12 we have the following naming for ports:
> - Combo PHYs (native DP/HDMI):
>   DDI#A-C
> - TBT/non-TBT (TC altmode, native DP/HDMI) PHYs:
>   DDI TC#1-6
> 
> To save some space in the power domain enum the power domain naming in
> the driver reflects the above change, that is power domains TC#1-3 are
> added as aliases for DDI#D-F and new power domains are reserved for
> TC#4-6.
> 
> v2 (Lucas):
>   - Separate out the bits and definitions for TGL from the ICL ones.
>     Fix use of TRANSCODER_EDP_VDSC, that is now the correct define since
>     we don't define TRANSCODER_A_VDSC power domain to spare a one bit in
>     the bitmask (suggested by Ville)
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  .../drm/i915/display/intel_display_power.c    | 480 +++++++++++++++++-
>  .../drm/i915/display/intel_display_power.h    |  26 +-
>  drivers/gpu/drm/i915/i915_debugfs.c           |   3 +-
>  drivers/gpu/drm/i915/i915_reg.h               |  18 +
>  4 files changed, 508 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 7437fc71d289..c3f42169831f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -23,8 +23,11 @@ bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
>  					 enum i915_power_well_id power_well_id);
>  
>  const char *
> -intel_display_power_domain_str(enum intel_display_power_domain domain)
> +intel_display_power_domain_str(struct drm_i915_private *i915,
> +			       enum intel_display_power_domain domain)
>  {
> +	bool ddi_tc_ports = IS_GEN(i915, 12);
> +
>  	switch (domain) {
>  	case POWER_DOMAIN_DISPLAY_CORE:
>  		return "DISPLAY_CORE";
> @@ -61,11 +64,23 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
>  	case POWER_DOMAIN_PORT_DDI_C_LANES:
>  		return "PORT_DDI_C_LANES";
>  	case POWER_DOMAIN_PORT_DDI_D_LANES:
> -		return "PORT_DDI_D_LANES";
> +		BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_D_LANES !=
> +			     POWER_DOMAIN_PORT_DDI_TC1_LANES);
> +		return ddi_tc_ports ? "PORT_DDI_TC1_LANES" : "PORT_DDI_D_LANES";
>  	case POWER_DOMAIN_PORT_DDI_E_LANES:
> -		return "PORT_DDI_E_LANES";
> +		BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_E_LANES !=
> +			     POWER_DOMAIN_PORT_DDI_TC2_LANES);
> +		return ddi_tc_ports ? "PORT_DDI_TC2_LANES" : "PORT_DDI_E_LANES";
>  	case POWER_DOMAIN_PORT_DDI_F_LANES:
> -		return "PORT_DDI_F_LANES";
> +		BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_F_LANES !=
> +			     POWER_DOMAIN_PORT_DDI_TC3_LANES);
> +		return ddi_tc_ports ? "PORT_DDI_TC3_LANES" : "PORT_DDI_F_LANES";
> +	case POWER_DOMAIN_PORT_DDI_TC4_LANES:
> +		return "PORT_DDI_TC4_LANES";
> +	case POWER_DOMAIN_PORT_DDI_TC5_LANES:
> +		return "PORT_DDI_TC5_LANES";
> +	case POWER_DOMAIN_PORT_DDI_TC6_LANES:
> +		return "PORT_DDI_TC6_LANES";
>  	case POWER_DOMAIN_PORT_DDI_A_IO:
>  		return "PORT_DDI_A_IO";
>  	case POWER_DOMAIN_PORT_DDI_B_IO:
> @@ -73,11 +88,23 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
>  	case POWER_DOMAIN_PORT_DDI_C_IO:
>  		return "PORT_DDI_C_IO";
>  	case POWER_DOMAIN_PORT_DDI_D_IO:
> -		return "PORT_DDI_D_IO";
> +		BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_D_IO !=
> +			     POWER_DOMAIN_PORT_DDI_TC1_IO);
> +		return ddi_tc_ports ? "PORT_DDI_TC1_IO" : "PORT_DDI_D_IO";
>  	case POWER_DOMAIN_PORT_DDI_E_IO:
> -		return "PORT_DDI_E_IO";
> +		BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_E_IO !=
> +			     POWER_DOMAIN_PORT_DDI_TC2_IO);
> +		return ddi_tc_ports ? "PORT_DDI_TC2_IO" : "PORT_DDI_E_IO";
>  	case POWER_DOMAIN_PORT_DDI_F_IO:
> -		return "PORT_DDI_F_IO";
> +		BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_F_IO !=
> +			     POWER_DOMAIN_PORT_DDI_TC3_IO);
> +		return ddi_tc_ports ? "PORT_DDI_TC3_IO" : "PORT_DDI_F_IO";
> +	case POWER_DOMAIN_PORT_DDI_TC4_IO:
> +		return "PORT_DDI_TC4_IO";
> +	case POWER_DOMAIN_PORT_DDI_TC5_IO:
> +		return "PORT_DDI_TC5_IO";
> +	case POWER_DOMAIN_PORT_DDI_TC6_IO:
> +		return "PORT_DDI_TC6_IO";
>  	case POWER_DOMAIN_PORT_DSI:
>  		return "PORT_DSI";
>  	case POWER_DOMAIN_PORT_CRT:
> @@ -95,11 +122,20 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
>  	case POWER_DOMAIN_AUX_C:
>  		return "AUX_C";
>  	case POWER_DOMAIN_AUX_D:
> -		return "AUX_D";
> +		BUILD_BUG_ON(POWER_DOMAIN_AUX_D != POWER_DOMAIN_AUX_TC1);
> +		return ddi_tc_ports ? "AUX_TC1" : "AUX_D";
>  	case POWER_DOMAIN_AUX_E:
> -		return "AUX_E";
> +		BUILD_BUG_ON(POWER_DOMAIN_AUX_E != POWER_DOMAIN_AUX_TC2);
> +		return ddi_tc_ports ? "AUX_TC2" : "AUX_E";
>  	case POWER_DOMAIN_AUX_F:
> -		return "AUX_F";
> +		BUILD_BUG_ON(POWER_DOMAIN_AUX_F != POWER_DOMAIN_AUX_TC3);
> +		return ddi_tc_ports ? "AUX_TC3" : "AUX_F";
> +	case POWER_DOMAIN_AUX_TC4:
> +		return "AUX_TC4";
> +	case POWER_DOMAIN_AUX_TC5:
> +		return "AUX_TC5";
> +	case POWER_DOMAIN_AUX_TC6:
> +		return "AUX_TC6";
>  	case POWER_DOMAIN_AUX_IO_A:
>  		return "AUX_IO_A";
>  	case POWER_DOMAIN_AUX_TBT1:
> @@ -110,6 +146,10 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
>  		return "AUX_TBT3";
>  	case POWER_DOMAIN_AUX_TBT4:
>  		return "AUX_TBT4";
> +	case POWER_DOMAIN_AUX_TBT5:
> +		return "AUX_TBT5";
> +	case POWER_DOMAIN_AUX_TBT6:
> +		return "AUX_TBT6";
>  	case POWER_DOMAIN_GMBUS:
>  		return "GMBUS";
>  	case POWER_DOMAIN_INIT:
> @@ -1664,12 +1704,15 @@ __async_put_domains_state_ok(struct i915_power_domains *power_domains)
>  static void print_power_domains(struct i915_power_domains *power_domains,
>  				const char *prefix, u64 mask)
>  {
> +	struct drm_i915_private *i915 =
> +		container_of(power_domains, struct drm_i915_private,
> +			     power_domains);
>  	enum intel_display_power_domain domain;
>  
>  	DRM_DEBUG_DRIVER("%s (%lu):\n", prefix, hweight64(mask));
>  	for_each_power_domain(domain, mask)
>  		DRM_DEBUG_DRIVER("%s use_count %d\n",
> -				 intel_display_power_domain_str(domain),
> +				 intel_display_power_domain_str(i915, domain),
>  				 power_domains->domain_use_count[domain]);
>  }
>  
> @@ -1839,7 +1882,7 @@ __intel_display_power_put_domain(struct drm_i915_private *dev_priv,
>  {
>  	struct i915_power_domains *power_domains;
>  	struct i915_power_well *power_well;
> -	const char *name = intel_display_power_domain_str(domain);
> +	const char *name = intel_display_power_domain_str(dev_priv, domain);
>  
>  	power_domains = &dev_priv->power_domains;
>  
> @@ -2408,11 +2451,11 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
>   * - DDI_A
>   * - FBC
>   */
> +/* TODO: TGL_PW_5_POWER_DOMAINS: PIPE_D */
>  #define ICL_PW_4_POWER_DOMAINS (			\
>  	BIT_ULL(POWER_DOMAIN_PIPE_C) |			\
>  	BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |	\
>  	BIT_ULL(POWER_DOMAIN_INIT))
> -	/* VDSC/joining */
>  #define ICL_PW_3_POWER_DOMAINS (			\
>  	ICL_PW_4_POWER_DOMAINS |			\
>  	BIT_ULL(POWER_DOMAIN_PIPE_B) |			\
> @@ -2448,16 +2491,17 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
>  	 */
>  #define ICL_PW_2_POWER_DOMAINS (			\
>  	ICL_PW_3_POWER_DOMAINS |			\
> -	BIT_ULL(POWER_DOMAIN_TRANSCODER_EDP_VDSC) |		\
> +	BIT_ULL(POWER_DOMAIN_TRANSCODER_EDP_VDSC) |	\
>  	BIT_ULL(POWER_DOMAIN_INIT))
>  	/*
>  	 * - KVMR (HW control)
> +	 * - GEN 11: eDP/DSI VDSC
>  	 */
>  #define ICL_DISPLAY_DC_OFF_POWER_DOMAINS (		\
>  	ICL_PW_2_POWER_DOMAINS |			\
>  	BIT_ULL(POWER_DOMAIN_MODESET) |			\
>  	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
> -	BIT_ULL(POWER_DOMAIN_DPLL_DC_OFF) |			\
> +	BIT_ULL(POWER_DOMAIN_DPLL_DC_OFF) |		\
>  	BIT_ULL(POWER_DOMAIN_INIT))
>  
>  #define ICL_DDI_IO_A_POWER_DOMAINS (			\
> @@ -2495,6 +2539,87 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
>  #define ICL_AUX_TBT4_IO_POWER_DOMAINS (			\
>  	BIT_ULL(POWER_DOMAIN_AUX_TBT4))
>  
> +#define TGL_PW_4_POWER_DOMAINS (			\
> +	BIT_ULL(POWER_DOMAIN_PIPE_C) |			\
> +	BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |	\
> +	BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define TGL_PW_3_POWER_DOMAINS (			\
> +	TGL_PW_4_POWER_DOMAINS |			\
> +	BIT_ULL(POWER_DOMAIN_PIPE_B) |			\
> +	BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |		\
> +	BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |		\
> +	/* TODO: TRANSCODER_D */			\
> +	BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |	\
> +	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_LANES) |	\
> +	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_IO) |		\
> +	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC2_LANES) |	\
> +	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC2_IO) |		\
> +	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC3_LANES) |	\
> +	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC3_IO) |		\
> +	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC4_LANES) |	\
> +	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC4_IO) |		\
> +	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC5_LANES) |	\
> +	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC5_IO) |		\
> +	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC6_LANES) |	\
> +	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC6_IO) |		\

The IO power stuff shouln't be here I guess. But I already discussed
that with Imre, and I believe we have the same issue on icl. So I
guess we can sort it out later for both platforms.

Patch lgtm
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> +	BIT_ULL(POWER_DOMAIN_AUX_TC1) |		\
> +	BIT_ULL(POWER_DOMAIN_AUX_TC2) |		\
> +	BIT_ULL(POWER_DOMAIN_AUX_TC3) |		\
> +	BIT_ULL(POWER_DOMAIN_AUX_TC4) |		\
> +	BIT_ULL(POWER_DOMAIN_AUX_TC5) |		\
> +	BIT_ULL(POWER_DOMAIN_AUX_TC6) |		\
> +	BIT_ULL(POWER_DOMAIN_AUX_TBT1) |		\
> +	BIT_ULL(POWER_DOMAIN_AUX_TBT2) |		\
> +	BIT_ULL(POWER_DOMAIN_AUX_TBT3) |		\
> +	BIT_ULL(POWER_DOMAIN_AUX_TBT4) |		\
> +	BIT_ULL(POWER_DOMAIN_AUX_TBT5) |		\
> +	BIT_ULL(POWER_DOMAIN_AUX_TBT6) |		\
> +	BIT_ULL(POWER_DOMAIN_VGA) |			\
> +	BIT_ULL(POWER_DOMAIN_AUDIO) |			\
> +	BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define TGL_PW_2_POWER_DOMAINS (			\
> +	TGL_PW_3_POWER_DOMAINS |			\
> +	BIT_ULL(POWER_DOMAIN_TRANSCODER_EDP_VDSC) |	\
> +	BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define TGL_DISPLAY_DC_OFF_POWER_DOMAINS (		\
> +	TGL_PW_2_POWER_DOMAINS |			\
> +	BIT_ULL(POWER_DOMAIN_MODESET) |			\
> +	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
> +	BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define TGL_DDI_IO_TC1_POWER_DOMAINS (		\
> +	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_IO))
> +#define TGL_DDI_IO_TC2_POWER_DOMAINS (		\
> +	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC2_IO))
> +#define TGL_DDI_IO_TC3_POWER_DOMAINS (		\
> +	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC3_IO))
> +#define TGL_DDI_IO_TC4_POWER_DOMAINS (		\
> +	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC4_IO))
> +#define TGL_DDI_IO_TC5_POWER_DOMAINS (		\
> +	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC5_IO))
> +#define TGL_DDI_IO_TC6_POWER_DOMAINS (		\
> +	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC6_IO))
> +
> +#define TGL_AUX_TC1_IO_POWER_DOMAINS (		\
> +	BIT_ULL(POWER_DOMAIN_AUX_TC1))
> +#define TGL_AUX_TC2_IO_POWER_DOMAINS (		\
> +	BIT_ULL(POWER_DOMAIN_AUX_TC2))
> +#define TGL_AUX_TC3_IO_POWER_DOMAINS (		\
> +	BIT_ULL(POWER_DOMAIN_AUX_TC3))
> +#define TGL_AUX_TC4_IO_POWER_DOMAINS (		\
> +	BIT_ULL(POWER_DOMAIN_AUX_TC4))
> +#define TGL_AUX_TC5_IO_POWER_DOMAINS (		\
> +	BIT_ULL(POWER_DOMAIN_AUX_TC5))
> +#define TGL_AUX_TC6_IO_POWER_DOMAINS (		\
> +	BIT_ULL(POWER_DOMAIN_AUX_TC6))
> +#define TGL_AUX_TBT5_IO_POWER_DOMAINS (		\
> +	BIT_ULL(POWER_DOMAIN_AUX_TBT5))
> +#define TGL_AUX_TBT6_IO_POWER_DOMAINS (		\
> +	BIT_ULL(POWER_DOMAIN_AUX_TBT6))
> +
>  static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
>  	.sync_hw = i9xx_power_well_sync_hw_noop,
>  	.enable = i9xx_always_on_power_well_noop,
> @@ -3452,6 +3577,324 @@ static const struct i915_power_well_desc icl_power_wells[] = {
>  	},
>  };
>  
> +static const struct i915_power_well_desc tgl_power_wells[] = {
> +	{
> +		.name = "always-on",
> +		.always_on = true,
> +		.domains = POWER_DOMAIN_MASK,
> +		.ops = &i9xx_always_on_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +	},
> +	{
> +		.name = "power well 1",
> +		/* Handled by the DMC firmware */
> +		.always_on = true,
> +		.domains = 0,
> +		.ops = &hsw_power_well_ops,
> +		.id = SKL_DISP_PW_1,
> +		{
> +			.hsw.regs = &hsw_power_well_regs,
> +			.hsw.idx = ICL_PW_CTL_IDX_PW_1,
> +			.hsw.has_fuses = true,
> +		},
> +	},
> +	{
> +		.name = "DC off",
> +		.domains = TGL_DISPLAY_DC_OFF_POWER_DOMAINS,
> +		.ops = &gen9_dc_off_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +	},
> +	{
> +		.name = "power well 2",
> +		.domains = TGL_PW_2_POWER_DOMAINS,
> +		.ops = &hsw_power_well_ops,
> +		.id = SKL_DISP_PW_2,
> +		{
> +			.hsw.regs = &hsw_power_well_regs,
> +			.hsw.idx = ICL_PW_CTL_IDX_PW_2,
> +			.hsw.has_fuses = true,
> +		},
> +	},
> +	{
> +		.name = "power well 3",
> +		.domains = TGL_PW_3_POWER_DOMAINS,
> +		.ops = &hsw_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &hsw_power_well_regs,
> +			.hsw.idx = ICL_PW_CTL_IDX_PW_3,
> +			.hsw.irq_pipe_mask = BIT(PIPE_B),
> +			.hsw.has_vga = true,
> +			.hsw.has_fuses = true,
> +		},
> +	},
> +	{
> +		.name = "DDI A IO",
> +		.domains = ICL_DDI_IO_A_POWER_DOMAINS,
> +		.ops = &hsw_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &icl_ddi_power_well_regs,
> +			.hsw.idx = ICL_PW_CTL_IDX_DDI_A,
> +		}
> +	},
> +	{
> +		.name = "DDI B IO",
> +		.domains = ICL_DDI_IO_B_POWER_DOMAINS,
> +		.ops = &hsw_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &icl_ddi_power_well_regs,
> +			.hsw.idx = ICL_PW_CTL_IDX_DDI_B,
> +		}
> +	},
> +	{
> +		.name = "DDI C IO",
> +		.domains = ICL_DDI_IO_C_POWER_DOMAINS,
> +		.ops = &hsw_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &icl_ddi_power_well_regs,
> +			.hsw.idx = ICL_PW_CTL_IDX_DDI_C,
> +		}
> +	},
> +	{
> +		.name = "DDI TC1 IO",
> +		.domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
> +		.ops = &hsw_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &icl_ddi_power_well_regs,
> +			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
> +		},
> +	},
> +	{
> +		.name = "DDI TC2 IO",
> +		.domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
> +		.ops = &hsw_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &icl_ddi_power_well_regs,
> +			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
> +		},
> +	},
> +	{
> +		.name = "DDI TC3 IO",
> +		.domains = TGL_DDI_IO_TC3_POWER_DOMAINS,
> +		.ops = &hsw_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &icl_ddi_power_well_regs,
> +			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC3,
> +		},
> +	},
> +	{
> +		.name = "DDI TC4 IO",
> +		.domains = TGL_DDI_IO_TC4_POWER_DOMAINS,
> +		.ops = &hsw_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &icl_ddi_power_well_regs,
> +			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC4,
> +		},
> +	},
> +	{
> +		.name = "DDI TC5 IO",
> +		.domains = TGL_DDI_IO_TC5_POWER_DOMAINS,
> +		.ops = &hsw_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &icl_ddi_power_well_regs,
> +			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC5,
> +		},
> +	},
> +	{
> +		.name = "DDI TC6 IO",
> +		.domains = TGL_DDI_IO_TC6_POWER_DOMAINS,
> +		.ops = &hsw_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &icl_ddi_power_well_regs,
> +			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC6,
> +		},
> +	},
> +	{
> +		.name = "AUX A",
> +		.domains = ICL_AUX_A_IO_POWER_DOMAINS,
> +		.ops = &icl_combo_phy_aux_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &icl_aux_power_well_regs,
> +			.hsw.idx = ICL_PW_CTL_IDX_AUX_A,
> +		},
> +	},
> +	{
> +		.name = "AUX B",
> +		.domains = ICL_AUX_B_IO_POWER_DOMAINS,
> +		.ops = &icl_combo_phy_aux_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &icl_aux_power_well_regs,
> +			.hsw.idx = ICL_PW_CTL_IDX_AUX_B,
> +		},
> +	},
> +	{
> +		.name = "AUX C",
> +		.domains = ICL_AUX_C_IO_POWER_DOMAINS,
> +		.ops = &icl_combo_phy_aux_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &icl_aux_power_well_regs,
> +			.hsw.idx = ICL_PW_CTL_IDX_AUX_C,
> +		},
> +	},
> +	{
> +		.name = "AUX TC1",
> +		.domains = TGL_AUX_TC1_IO_POWER_DOMAINS,
> +		.ops = &icl_tc_phy_aux_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &icl_aux_power_well_regs,
> +			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
> +			.hsw.is_tc_tbt = false,
> +		},
> +	},
> +	{
> +		.name = "AUX TC2",
> +		.domains = TGL_AUX_TC2_IO_POWER_DOMAINS,
> +		.ops = &icl_tc_phy_aux_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &icl_aux_power_well_regs,
> +			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
> +			.hsw.is_tc_tbt = false,
> +		},
> +	},
> +	{
> +		.name = "AUX TC3",
> +		.domains = TGL_AUX_TC3_IO_POWER_DOMAINS,
> +		.ops = &icl_tc_phy_aux_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &icl_aux_power_well_regs,
> +			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC3,
> +			.hsw.is_tc_tbt = false,
> +		},
> +	},
> +	{
> +		.name = "AUX TC4",
> +		.domains = TGL_AUX_TC4_IO_POWER_DOMAINS,
> +		.ops = &icl_tc_phy_aux_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &icl_aux_power_well_regs,
> +			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC4,
> +			.hsw.is_tc_tbt = false,
> +		},
> +	},
> +	{
> +		.name = "AUX TC5",
> +		.domains = TGL_AUX_TC5_IO_POWER_DOMAINS,
> +		.ops = &icl_tc_phy_aux_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &icl_aux_power_well_regs,
> +			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC5,
> +			.hsw.is_tc_tbt = false,
> +		},
> +	},
> +	{
> +		.name = "AUX TC6",
> +		.domains = TGL_AUX_TC6_IO_POWER_DOMAINS,
> +		.ops = &icl_tc_phy_aux_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &icl_aux_power_well_regs,
> +			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC6,
> +			.hsw.is_tc_tbt = false,
> +		},
> +	},
> +	{
> +		.name = "AUX TBT1",
> +		.domains = ICL_AUX_TBT1_IO_POWER_DOMAINS,
> +		.ops = &hsw_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &icl_aux_power_well_regs,
> +			.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1,
> +			.hsw.is_tc_tbt = true,
> +		},
> +	},
> +	{
> +		.name = "AUX TBT2",
> +		.domains = ICL_AUX_TBT2_IO_POWER_DOMAINS,
> +		.ops = &hsw_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &icl_aux_power_well_regs,
> +			.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2,
> +			.hsw.is_tc_tbt = true,
> +		},
> +	},
> +	{
> +		.name = "AUX TBT3",
> +		.domains = ICL_AUX_TBT3_IO_POWER_DOMAINS,
> +		.ops = &hsw_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &icl_aux_power_well_regs,
> +			.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3,
> +			.hsw.is_tc_tbt = true,
> +		},
> +	},
> +	{
> +		.name = "AUX TBT4",
> +		.domains = ICL_AUX_TBT4_IO_POWER_DOMAINS,
> +		.ops = &hsw_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &icl_aux_power_well_regs,
> +			.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4,
> +			.hsw.is_tc_tbt = true,
> +		},
> +	},
> +	{
> +		.name = "AUX TBT5",
> +		.domains = TGL_AUX_TBT5_IO_POWER_DOMAINS,
> +		.ops = &hsw_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &icl_aux_power_well_regs,
> +			.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT5,
> +			.hsw.is_tc_tbt = true,
> +		},
> +	},
> +	{
> +		.name = "AUX TBT6",
> +		.domains = TGL_AUX_TBT6_IO_POWER_DOMAINS,
> +		.ops = &hsw_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &icl_aux_power_well_regs,
> +			.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT6,
> +			.hsw.is_tc_tbt = true,
> +		},
> +	},
> +	{
> +		.name = "power well 4",
> +		.domains = ICL_PW_4_POWER_DOMAINS,
> +		.ops = &hsw_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &hsw_power_well_regs,
> +			.hsw.idx = ICL_PW_CTL_IDX_PW_4,
> +			.hsw.has_fuses = true,
> +			.hsw.irq_pipe_mask = BIT(PIPE_C),
> +		}
> +	},
> +	/* TODO: power well 5 for pipe D */
> +};
> +
>  static int
>  sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
>  				   int disable_power_well)
> @@ -3579,7 +4022,9 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
>  	 * The enabling order will be from lower to higher indexed wells,
>  	 * the disabling order is reversed.
>  	 */
> -	if (IS_GEN(dev_priv, 11)) {
> +	if (IS_GEN(dev_priv, 12)) {
> +		err = set_power_wells(power_domains, tgl_power_wells);
> +	} else if (IS_GEN(dev_priv, 11)) {
>  		err = set_power_wells(power_domains, icl_power_wells);
>  	} else if (IS_CANNONLAKE(dev_priv)) {
>  		err = set_power_wells(power_domains, cnl_power_wells);
> @@ -4643,7 +5088,8 @@ static void intel_power_domains_dump_info(struct drm_i915_private *i915)
>  
>  		for_each_power_domain(domain, power_well->desc->domains)
>  			DRM_DEBUG_DRIVER("  %-23s %d\n",
> -					 intel_display_power_domain_str(domain),
> +					 intel_display_power_domain_str(i915,
> +									domain),
>  					 power_domains->domain_use_count[domain]);
>  	}
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
> index 8f43f7051a16..86afd70c1fb2 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -32,14 +32,29 @@ enum intel_display_power_domain {
>  	POWER_DOMAIN_PORT_DDI_B_LANES,
>  	POWER_DOMAIN_PORT_DDI_C_LANES,
>  	POWER_DOMAIN_PORT_DDI_D_LANES,
> +	POWER_DOMAIN_PORT_DDI_TC1_LANES = POWER_DOMAIN_PORT_DDI_D_LANES,
>  	POWER_DOMAIN_PORT_DDI_E_LANES,
> +	POWER_DOMAIN_PORT_DDI_TC2_LANES = POWER_DOMAIN_PORT_DDI_E_LANES,
>  	POWER_DOMAIN_PORT_DDI_F_LANES,
> +	POWER_DOMAIN_PORT_DDI_TC3_LANES = POWER_DOMAIN_PORT_DDI_F_LANES,
> +	POWER_DOMAIN_PORT_DDI_TC4_LANES,
> +	POWER_DOMAIN_PORT_DDI_TC5_LANES,
> +	POWER_DOMAIN_PORT_DDI_TC6_LANES,
>  	POWER_DOMAIN_PORT_DDI_A_IO,
>  	POWER_DOMAIN_PORT_DDI_B_IO,
>  	POWER_DOMAIN_PORT_DDI_C_IO,
>  	POWER_DOMAIN_PORT_DDI_D_IO,
> +	POWER_DOMAIN_PORT_DDI_TC1_IO = POWER_DOMAIN_PORT_DDI_D_IO,
>  	POWER_DOMAIN_PORT_DDI_E_IO,
> +	POWER_DOMAIN_PORT_DDI_TC2_IO = POWER_DOMAIN_PORT_DDI_E_IO,
>  	POWER_DOMAIN_PORT_DDI_F_IO,
> +	POWER_DOMAIN_PORT_DDI_TC3_IO = POWER_DOMAIN_PORT_DDI_F_IO,
> +	POWER_DOMAIN_PORT_DDI_G_IO,
> +	POWER_DOMAIN_PORT_DDI_TC4_IO = POWER_DOMAIN_PORT_DDI_G_IO,
> +	POWER_DOMAIN_PORT_DDI_H_IO,
> +	POWER_DOMAIN_PORT_DDI_TC5_IO = POWER_DOMAIN_PORT_DDI_H_IO,
> +	POWER_DOMAIN_PORT_DDI_I_IO,
> +	POWER_DOMAIN_PORT_DDI_TC6_IO = POWER_DOMAIN_PORT_DDI_I_IO,
>  	POWER_DOMAIN_PORT_DSI,
>  	POWER_DOMAIN_PORT_CRT,
>  	POWER_DOMAIN_PORT_OTHER,
> @@ -49,13 +64,21 @@ enum intel_display_power_domain {
>  	POWER_DOMAIN_AUX_B,
>  	POWER_DOMAIN_AUX_C,
>  	POWER_DOMAIN_AUX_D,
> +	POWER_DOMAIN_AUX_TC1 = POWER_DOMAIN_AUX_D,
>  	POWER_DOMAIN_AUX_E,
> +	POWER_DOMAIN_AUX_TC2 = POWER_DOMAIN_AUX_E,
>  	POWER_DOMAIN_AUX_F,
> +	POWER_DOMAIN_AUX_TC3 = POWER_DOMAIN_AUX_F,
> +	POWER_DOMAIN_AUX_TC4,
> +	POWER_DOMAIN_AUX_TC5,
> +	POWER_DOMAIN_AUX_TC6,
>  	POWER_DOMAIN_AUX_IO_A,
>  	POWER_DOMAIN_AUX_TBT1,
>  	POWER_DOMAIN_AUX_TBT2,
>  	POWER_DOMAIN_AUX_TBT3,
>  	POWER_DOMAIN_AUX_TBT4,
> +	POWER_DOMAIN_AUX_TBT5,
> +	POWER_DOMAIN_AUX_TBT6,
>  	POWER_DOMAIN_GMBUS,
>  	POWER_DOMAIN_MODESET,
>  	POWER_DOMAIN_GT_IRQ,
> @@ -228,7 +251,8 @@ void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
>  void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
>  
>  const char *
> -intel_display_power_domain_str(enum intel_display_power_domain domain);
> +intel_display_power_domain_str(struct drm_i915_private *i915,
> +			       enum intel_display_power_domain domain);
>  
>  bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
>  				    enum intel_display_power_domain domain);
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 3e4f58f19362..4d59972e9689 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2472,7 +2472,8 @@ static int i915_power_domain_info(struct seq_file *m, void *unused)
>  
>  		for_each_power_domain(power_domain, power_well->desc->domains)
>  			seq_printf(m, "  %-23s %d\n",
> -				 intel_display_power_domain_str(power_domain),
> +				 intel_display_power_domain_str(dev_priv,
> +								power_domain),
>  				 power_domains->domain_use_count[power_domain]);
>  	}
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 08dc71e4b818..f59cb5c45c34 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9156,13 +9156,25 @@ enum {
>  #define ICL_PWR_WELL_CTL_AUX1			_MMIO(0x45440)
>  #define ICL_PWR_WELL_CTL_AUX2			_MMIO(0x45444)
>  #define ICL_PWR_WELL_CTL_AUX4			_MMIO(0x4544C)
> +#define   TGL_PW_CTL_IDX_AUX_TBT6		14
> +#define   TGL_PW_CTL_IDX_AUX_TBT5		13
> +#define   TGL_PW_CTL_IDX_AUX_TBT4		12
>  #define   ICL_PW_CTL_IDX_AUX_TBT4		11
> +#define   TGL_PW_CTL_IDX_AUX_TBT3		11
>  #define   ICL_PW_CTL_IDX_AUX_TBT3		10
> +#define   TGL_PW_CTL_IDX_AUX_TBT2		10
>  #define   ICL_PW_CTL_IDX_AUX_TBT2		9
> +#define   TGL_PW_CTL_IDX_AUX_TBT1		9
>  #define   ICL_PW_CTL_IDX_AUX_TBT1		8
> +#define   TGL_PW_CTL_IDX_AUX_TC6		8
> +#define   TGL_PW_CTL_IDX_AUX_TC5		7
> +#define   TGL_PW_CTL_IDX_AUX_TC4		6
>  #define   ICL_PW_CTL_IDX_AUX_F			5
> +#define   TGL_PW_CTL_IDX_AUX_TC3		5
>  #define   ICL_PW_CTL_IDX_AUX_E			4
> +#define   TGL_PW_CTL_IDX_AUX_TC2		4
>  #define   ICL_PW_CTL_IDX_AUX_D			3
> +#define   TGL_PW_CTL_IDX_AUX_TC1		3
>  #define   ICL_PW_CTL_IDX_AUX_C			2
>  #define   ICL_PW_CTL_IDX_AUX_B			1
>  #define   ICL_PW_CTL_IDX_AUX_A			0
> @@ -9170,9 +9182,15 @@ enum {
>  #define ICL_PWR_WELL_CTL_DDI1			_MMIO(0x45450)
>  #define ICL_PWR_WELL_CTL_DDI2			_MMIO(0x45454)
>  #define ICL_PWR_WELL_CTL_DDI4			_MMIO(0x4545C)
> +#define   TGL_PW_CTL_IDX_DDI_TC6		8
> +#define   TGL_PW_CTL_IDX_DDI_TC5		7
> +#define   TGL_PW_CTL_IDX_DDI_TC4		6
>  #define   ICL_PW_CTL_IDX_DDI_F			5
> +#define   TGL_PW_CTL_IDX_DDI_TC3		5
>  #define   ICL_PW_CTL_IDX_DDI_E			4
> +#define   TGL_PW_CTL_IDX_DDI_TC2		4
>  #define   ICL_PW_CTL_IDX_DDI_D			3
> +#define   TGL_PW_CTL_IDX_DDI_TC1		3
>  #define   ICL_PW_CTL_IDX_DDI_C			2
>  #define   ICL_PW_CTL_IDX_DDI_B			1
>  #define   ICL_PW_CTL_IDX_DDI_A			0
> -- 
> 2.21.0

-- 
Ville Syrjälä
Intel
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Re: [PATCH v2 22/25] drm/i915/gen12: MBUS B credit change

[Ville Syrjälä]

On Mon, Jul 08, 2019 at 04:16:26PM -0700, Lucas De Marchi wrote:
> From: Rodrigo Vivi <rodrigo.vivi@intel.com>
> 
> Previously, the recommended B credit for all platforms was 24 / number
> of pipes, which would give 6 for newer platforms with 4 pipes. However 6
> is not enough and we need 12 on these cases.
> 
> We also need a different BW credit for these platforms.
> 
> Cc: Arthur J Runyan <arthur.j.runyan@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 10 ++++++++--
>  1 file changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 9ccf58ff4dba..9a5d04a2ab3e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6423,8 +6423,14 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
>  	u32 val;
>  
>  	val = MBUS_DBOX_A_CREDIT(2);
> -	val |= MBUS_DBOX_BW_CREDIT(1);
> -	val |= MBUS_DBOX_B_CREDIT(8);
> +
> +	if (INTEL_GEN(dev_priv) >= 12) {
> +		val |= MBUS_DBOX_BW_CREDIT(2);
> +		val |= MBUS_DBOX_B_CREDIT(12);
> +	} else {
> +		val |= MBUS_DBOX_BW_CREDIT(1);
> +		val |= MBUS_DBOX_B_CREDIT(8);
> +	}
>  
>  	I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
>  }
> -- 
> 2.21.0

-- 
Ville Syrjälä
Intel
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Re: [PATCH v2 24/25] drm/i915/tgl: Add DPLL registers

[Lucas De Marchi]

On Tue, Jul 09, 2019 at 03:56:51PM +0300, Ville Syrjälä wrote:
>On Mon, Jul 08, 2019 at 04:16:28PM -0700, Lucas De Marchi wrote:
>> On TGL the port programming for combophy is very similar to ICL, so
>> adapt the callers to possibly use the different register values.
>>
>> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 24 +++++++++++++++----
>>  drivers/gpu/drm/i915/i915_reg.h               | 15 ++++++++++++
>>  2 files changed, 34 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
>> index ae1c552d7afb..330b42a1f54e 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
>> @@ -3113,8 +3113,13 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
>>  	if (!(val & PLL_ENABLE))
>>  		goto out;
>>
>> -	hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
>> -	hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
>> +	if (INTEL_GEN(dev_priv) >= 12) {
>> +		hw_state->cfgcr0 = I915_READ(TGL_DPLL_CFGCR0(id));
>> +		hw_state->cfgcr1 = I915_READ(TGL_DPLL_CFGCR1(id));
>> +	} else {
>> +		hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
>> +		hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
>> +	}
>>
>>  	ret = true;
>>  out:
>> @@ -3148,10 +3153,19 @@ static void icl_dpll_write(struct drm_i915_private *dev_priv,
>>  {
>>  	struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
>>  	const enum intel_dpll_id id = pll->info->id;
>> +	i915_reg_t cfgcr0_reg, cfgcr1_reg;
>> +
>> +	if (INTEL_GEN(dev_priv) >= 12) {
>> +		cfgcr0_reg = TGL_DPLL_CFGCR0(id);
>> +		cfgcr1_reg = TGL_DPLL_CFGCR1(id);
>> +	} else {
>> +		cfgcr0_reg = ICL_DPLL_CFGCR0(id);
>> +		cfgcr1_reg = ICL_DPLL_CFGCR1(id);
>> +	}
>>
>> -	I915_WRITE(ICL_DPLL_CFGCR0(id), hw_state->cfgcr0);
>> -	I915_WRITE(ICL_DPLL_CFGCR1(id), hw_state->cfgcr1);
>> -	POSTING_READ(ICL_DPLL_CFGCR1(id));
>> +	I915_WRITE(cfgcr0_reg, hw_state->cfgcr0);
>> +	I915_WRITE(cfgcr1_reg, hw_state->cfgcr1);
>> +	POSTING_READ(cfgcr1_reg);
>>  }
>>
>>  static void icl_mg_pll_write(struct drm_i915_private *dev_priv,
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index fbcc7981c8c4..84c04ea67ec8 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -242,6 +242,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>>  #define _MMIO_PIPE3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
>>  #define _MMIO_PORT3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
>>  #define _MMIO_PHY3(phy, a, b, c)	_MMIO(_PHY3(phy, a, b, c))
>> +#define _MMIO_PLL3(pll, a, b, c)	_MMIO(_PICK(pll, a, b, c))
>>
>>  /*
>>   * Device info offset array based helpers for groups of registers with unevenly
>> @@ -9958,6 +9959,20 @@ enum skl_power_gate {
>>  #define ICL_DPLL_CFGCR1(pll)		_MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \
>>  						  _ICL_DPLL1_CFGCR1)
>>
>> +#define _TGL_DPLL0_CFGCR0		0x164284
>> +#define _TGL_DPLL1_CFGCR0		0x16428C
>> +#define _TGL_TBTPLL_CFGCR0		0x16429C
>
>What about DPLL4?

not all TGL skus have DPLL4. The ones that do (and were not tested
here), are very different from what is done for EHL so we can't reuse
the implementation. I will leave the DPLL4 on TGL for later, when it
makes sense to add it.

Lucas De Marchi

>
>In fact looks like the ICL counterparts are borked even for ehl DPLL4.
>
>> +#define TGL_DPLL_CFGCR0(pll)		_MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
>> +						  _TGL_DPLL1_CFGCR0, \
>> +						  _TGL_TBTPLL_CFGCR0)
>> +
>> +#define _TGL_DPLL0_CFGCR1		0x164288
>> +#define _TGL_DPLL1_CFGCR1		0x164290
>> +#define _TGL_TBTPLL_CFGCR1		0x1642A0
>> +#define TGL_DPLL_CFGCR1(pll)		_MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
>> +						   _TGL_DPLL1_CFGCR1, \
>> +						   _TGL_TBTPLL_CFGCR1)
>> +
>>  /* BXT display engine PLL */
>>  #define BXT_DE_PLL_CTL			_MMIO(0x6d000)
>>  #define   BXT_DE_PLL_RATIO(x)		(x)	/* {60,65,100} * 19.2MHz */
>> --
>> 2.21.0
>
>-- 
>Ville Syrjälä
>Intel
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Re: [PATCH v2 08/25] drm/i915/tgl: use TRANSCODER_EDP_VDSC on transcoder A

[Lucas De Marchi]

On Mon, Jul 08, 2019 at 06:07:17PM -0700, Jose Souza wrote:
>On Mon, 2019-07-08 at 16:16 -0700, Lucas De Marchi wrote:
>> From: José Roberto de Souza <jose.souza@intel.com>
>>
>> On TGL the special EDP transcoder is gone and it should be handled by
>> transcoder A.
>>
>> v2 (Lucas):
>>   - Reuse POWER_DOMAIN_TRANSCODER_EDP_VDSC (suggested by Ville)
>>   - Use crtc->dev since new_crtc_state->state may be NULL on atomic
>>     commit (suggested by Maarten)
>
>As we are reusing would be nice also rename it to something like:
>POWER_DOMAIN_TRANSCODER_VDSC_PW2
>POWER_DOMAIN_LOW_POWER_TRANSCODER_VDSC /
>POWER_DOMAIN_LP_TRANSCODER_VDSC

as it is still being used for EDP, I didn't think the rename was worth.

Lucas De Marchi

>
>>
>> Cc: Imre Deak <imre.deak@intel.com>
>> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_vdsc.c | 9 ++++++---
>>  1 file changed, 6 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
>> b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> index ffec807b8960..c27912f552f0 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> @@ -459,16 +459,19 @@ int intel_dp_compute_dsc_params(struct intel_dp
>> *intel_dp,
>>  enum intel_display_power_domain
>>  intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
>>  {
>> +	struct drm_i915_private *i915 = to_i915(crtc_state->base.crtc-
>> >dev);
>>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>>
>>  	/*
>> -	 * On ICL VDSC/joining for eDP transcoder uses a separate power
>> well PW2
>> -	 * This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
>> +	 * On ICL+ VDSC/joining for eDP/A transcoder uses a separate
>> power well
>> +	 * PW2. This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power
>> domain.
>>  	 * For any other transcoder, VDSC/joining uses the power well
>> associated
>>  	 * with the pipe/transcoder in use. Hence another reference on
>> the
>>  	 * transcoder power domain will suffice.
>>  	 */
>> -	if (cpu_transcoder == TRANSCODER_EDP)
>> +	if (INTEL_GEN(i915) >= 12 && cpu_transcoder == TRANSCODER_A)
>> +		return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
>> +	else if (cpu_transcoder == TRANSCODER_EDP)
>>  		return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
>>  	else
>>  		return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
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Re: [PATCH v2 10/25] drm/i915/tgl: Add power well to support 4th pipe

[Lucas De Marchi]

On Tue, Jul 09, 2019 at 04:57:32AM -0700, Rodrigo Vivi wrote:
>On Mon, Jul 08, 2019 at 04:16:14PM -0700, Lucas De Marchi wrote:
>> From: Mika Kahola <mika.kahola@intel.com>
>>
>> Add power well 5 to support 4th pipe and transcoder on TGL.
>>
>> Cc: James Ausmus <james.ausmus@intel.com>
>> Cc: Imre Deak <imre.deak@intel.com>
>> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  .../drm/i915/display/intel_display_power.c    | 30 ++++++++++++++++---
>>  .../drm/i915/display/intel_display_power.h    |  3 ++
>>  drivers/gpu/drm/i915/i915_reg.h               |  3 +-
>>  3 files changed, 31 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>> index c3f42169831f..455f9aab188d 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>> @@ -37,18 +37,24 @@ intel_display_power_domain_str(struct drm_i915_private *i915,
>>  		return "PIPE_B";
>>  	case POWER_DOMAIN_PIPE_C:
>>  		return "PIPE_C";
>> +	case POWER_DOMAIN_PIPE_D:
>> +		return "PIPE_D";
>>  	case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
>>  		return "PIPE_A_PANEL_FITTER";
>>  	case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
>>  		return "PIPE_B_PANEL_FITTER";
>>  	case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
>>  		return "PIPE_C_PANEL_FITTER";
>> +	case POWER_DOMAIN_PIPE_D_PANEL_FITTER:
>> +		return "PIPE_D_PANEL_FITTER";
>>  	case POWER_DOMAIN_TRANSCODER_A:
>>  		return "TRANSCODER_A";
>>  	case POWER_DOMAIN_TRANSCODER_B:
>>  		return "TRANSCODER_B";
>>  	case POWER_DOMAIN_TRANSCODER_C:
>>  		return "TRANSCODER_C";
>> +	case POWER_DOMAIN_TRANSCODER_D:
>> +		return "TRANSCODER_D";
>>  	case POWER_DOMAIN_TRANSCODER_EDP:
>>  		return "TRANSCODER_EDP";
>>  	case POWER_DOMAIN_TRANSCODER_EDP_VDSC:
>> @@ -2451,7 +2457,6 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
>>   * - DDI_A
>>   * - FBC
>>   */
>> -/* TODO: TGL_PW_5_POWER_DOMAINS: PIPE_D */
>>  #define ICL_PW_4_POWER_DOMAINS (			\
>>  	BIT_ULL(POWER_DOMAIN_PIPE_C) |			\
>>  	BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |	\
>> @@ -2539,7 +2544,13 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
>>  #define ICL_AUX_TBT4_IO_POWER_DOMAINS (			\
>>  	BIT_ULL(POWER_DOMAIN_AUX_TBT4))
>>
>> +#define TGL_PW_5_POWER_DOMAINS (			\
>> +	BIT_ULL(POWER_DOMAIN_PIPE_D) |			\
>> +	BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) |     \
>> +	BIT_ULL(POWER_DOMAIN_INIT))
>> +
>>  #define TGL_PW_4_POWER_DOMAINS (			\
>> +	TGL_PW_5_POWER_DOMAINS |			\
>
>why?

not sure I understand this one. Are you saying we shouldn't have a new
power well for pipe d? How would we handle the different ctl?

>
>>  	BIT_ULL(POWER_DOMAIN_PIPE_C) |			\
>>  	BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |	\
>>  	BIT_ULL(POWER_DOMAIN_INIT))
>> @@ -2549,7 +2560,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
>>  	BIT_ULL(POWER_DOMAIN_PIPE_B) |			\
>>  	BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |		\
>>  	BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |		\
>> -	/* TODO: TRANSCODER_D */			\
>> +	BIT_ULL(POWER_DOMAIN_TRANSCODER_D) |		\
>>  	BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |	\
>>  	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_LANES) |	\
>>  	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_IO) |		\
>> @@ -3882,7 +3893,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
>>  	},
>>  	{
>>  		.name = "power well 4",
>> -		.domains = ICL_PW_4_POWER_DOMAINS,
>> +		.domains = TGL_PW_4_POWER_DOMAINS,
>
>why?

this is a leftover from v1 and should be squashed on previous patch, my
bad. In v1 we were reusing the ICL definitions. I changed in this
revision and forgot to squash this change there. I will send a new
version

thanks

Lucas De Marchi

>
>>  		.ops = &hsw_power_well_ops,
>>  		.id = DISP_PW_ID_NONE,
>>  		{
>> @@ -3892,7 +3903,18 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
>>  			.hsw.irq_pipe_mask = BIT(PIPE_C),
>>  		}
>>  	},
>> -	/* TODO: power well 5 for pipe D */
>> +	{
>> +		.name = "power well 5",
>> +		.domains = TGL_PW_5_POWER_DOMAINS,
>> +		.ops = &hsw_power_well_ops,
>> +		.id = DISP_PW_ID_NONE,
>> +		{
>> +			.hsw.regs = &hsw_power_well_regs,
>> +			.hsw.idx = TGL_PW_CTL_IDX_PW_5,
>> +			.hsw.has_fuses = true,
>> +			.hsw.irq_pipe_mask = BIT(PIPE_D),
>> +		},
>> +	},
>>  };
>>
>>  static int
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
>> index 86afd70c1fb2..ebb397e330ea 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
>> @@ -18,12 +18,15 @@ enum intel_display_power_domain {
>>  	POWER_DOMAIN_PIPE_A,
>>  	POWER_DOMAIN_PIPE_B,
>>  	POWER_DOMAIN_PIPE_C,
>> +	POWER_DOMAIN_PIPE_D,
>>  	POWER_DOMAIN_PIPE_A_PANEL_FITTER,
>>  	POWER_DOMAIN_PIPE_B_PANEL_FITTER,
>>  	POWER_DOMAIN_PIPE_C_PANEL_FITTER,
>> +	POWER_DOMAIN_PIPE_D_PANEL_FITTER,
>>  	POWER_DOMAIN_TRANSCODER_A,
>>  	POWER_DOMAIN_TRANSCODER_B,
>>  	POWER_DOMAIN_TRANSCODER_C,
>> +	POWER_DOMAIN_TRANSCODER_D,
>>  	POWER_DOMAIN_TRANSCODER_EDP,
>>  	POWER_DOMAIN_TRANSCODER_EDP_VDSC,
>>  	POWER_DOMAIN_TRANSCODER_DSI_A,
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index f59cb5c45c34..5ca74eca05a4 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -9147,7 +9147,8 @@ enum {
>>  #define   GLK_PW_CTL_IDX_DDI_A			1
>>  #define   SKL_PW_CTL_IDX_MISC_IO		0
>>
>> -/* ICL - power wells */
>> +/* ICL/TGL - power wells */
>> +#define   TGL_PW_CTL_IDX_PW_5			4
>>  #define   ICL_PW_CTL_IDX_PW_4			3
>>  #define   ICL_PW_CTL_IDX_PW_3			2
>>  #define   ICL_PW_CTL_IDX_PW_2			1
>> --
>> 2.21.0
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH v2 16/25] drm/i915/tgl: port to ddc pin mapping

[Lucas De Marchi]

On Tue, Jul 09, 2019 at 05:11:08AM -0700, Rodrigo Vivi wrote:
>On Mon, Jul 08, 2019 at 04:16:20PM -0700, Lucas De Marchi wrote:
>> From: Mahesh Kumar <mahesh1.kumar@intel.com>
>>
>> Create a helper function to get ddc pin according to port number.
>
>Could you please explain why we can't simply reuse the icl one?
>
>I couldn't find a new table for tgl on bspec...
>
>>
>> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_hdmi.c | 16 +++++++++++++++-
>>  1 file changed, 15 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
>> index 0ebec69bbbfc..3b33e7626d7c 100644
>> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
>> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
>> @@ -2981,6 +2981,18 @@ static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
>>  	return ddc_pin;
>>  }
>>
>> +static u8 tgp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
>> +			      enum port port)
>> +{
>> +	if (intel_port_is_combophy(dev_priv, port))
>> +		return GMBUS_PIN_1_BXT + port;
>> +	else if (intel_port_is_tc(dev_priv, port))
>> +		return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port);
>
>okay, this seems better than the table we have on icl func,
>but couldn't we just change the icl one?

I think initially we had it implemented like in the icl function, and on
tgl we have the additional combo port. With the reworks to use
intel_port_to_tc() I didn't realize this now applies to icl as well.

I will change it in next version.

Thanks
Lucas De Marchi

>
>> +
>> +	WARN(1, "Unknown port:%c\n", port_name(port));
>> +	return GMBUS_PIN_2_BXT;
>> +}
>> +
>>  static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
>>  			      enum port port)
>>  {
>> @@ -3017,7 +3029,9 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
>>  		return info->alternate_ddc_pin;
>>  	}
>>
>> -	if (HAS_PCH_MCC(dev_priv))
>> +	if (HAS_PCH_TGP(dev_priv))
>> +		ddc_pin = tgp_port_to_ddc_pin(dev_priv, port);
>> +	else if (HAS_PCH_MCC(dev_priv))
>>  		ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
>>  	else if (HAS_PCH_ICP(dev_priv))
>>  		ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
>> --
>> 2.21.0
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[PATCH v3 16/25] drm/i915/tgl: port to ddc pin mapping

[Lucas De Marchi]

Make the icl function generic so it is based on phy type and can be
applied to tgl as well.

I checked if this could not apply to EHL as well, but unfortunately
there the HPD and DDC/GMBUS pins for DDI C are mapped to TypeC Port 1
even though it doesn't have TC phy.

v2: don't add a separate function for TGL, but rather reuse the ICL one
    (suggested by Rodrigo)

Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdmi.c | 34 +++++------------------
 1 file changed, 7 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 0ebec69bbbfc..dfdcd25eda02 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2930,33 +2930,13 @@ static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
 
 static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
 {
-	u8 ddc_pin;
+	if (intel_port_is_combophy(dev_priv, port))
+		return GMBUS_PIN_1_BXT + port;
+	else if (intel_port_is_tc(dev_priv, port))
+		return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port);
 
-	switch (port) {
-	case PORT_A:
-		ddc_pin = GMBUS_PIN_1_BXT;
-		break;
-	case PORT_B:
-		ddc_pin = GMBUS_PIN_2_BXT;
-		break;
-	case PORT_C:
-		ddc_pin = GMBUS_PIN_9_TC1_ICP;
-		break;
-	case PORT_D:
-		ddc_pin = GMBUS_PIN_10_TC2_ICP;
-		break;
-	case PORT_E:
-		ddc_pin = GMBUS_PIN_11_TC3_ICP;
-		break;
-	case PORT_F:
-		ddc_pin = GMBUS_PIN_12_TC4_ICP;
-		break;
-	default:
-		MISSING_CASE(port);
-		ddc_pin = GMBUS_PIN_2_BXT;
-		break;
-	}
-	return ddc_pin;
+	WARN(1, "Unknown port:%c\n", port_name(port));
+	return GMBUS_PIN_2_BXT;
 }
 
 static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
@@ -3019,7 +2999,7 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
 
 	if (HAS_PCH_MCC(dev_priv))
 		ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
-	else if (HAS_PCH_ICP(dev_priv))
+	else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_ICP(dev_priv))
 		ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
 	else if (HAS_PCH_CNP(dev_priv))
 		ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
-- 
2.21.0

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✗ Fi.CI.CHECKPATCH: warning for Initial support for Tiger Lake (rev3)

[Patchwork]

== Series Details ==

Series: Initial support for Tiger Lake (rev3)
URL   : https://patchwork.freedesktop.org/series/62726/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
5c5e5e6008d1 drm/i915: Add 4th pipe and transcoder
0cd4b6f0f2d1 drm/i915/tgl: add initial Tiger Lake definitions
777a2d8d8266 drm/i915/tgl: Introduce Tiger Lake PCH
cb543d474e7a drm/i915/tgl: Add TGL PCH detection in virtualized environment
9b52a5d4d480 drm/i915/tgl: Add TGL PCI IDs
-:34: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#34: FILE: include/drm/i915_pciids.h:587:
+#define INTEL_TGL_12_IDS(info) \
+	INTEL_VGA_DEVICE(0x9A49, info), \
+	INTEL_VGA_DEVICE(0x9A40, info), \
+	INTEL_VGA_DEVICE(0x9A59, info), \
+	INTEL_VGA_DEVICE(0x9A60, info), \
+	INTEL_VGA_DEVICE(0x9A68, info), \
+	INTEL_VGA_DEVICE(0x9A70, info), \
+	INTEL_VGA_DEVICE(0x9A78, info)

-:34: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#34: FILE: include/drm/i915_pciids.h:587:
+#define INTEL_TGL_12_IDS(info) \
+	INTEL_VGA_DEVICE(0x9A49, info), \
+	INTEL_VGA_DEVICE(0x9A40, info), \
+	INTEL_VGA_DEVICE(0x9A59, info), \
+	INTEL_VGA_DEVICE(0x9A60, info), \
+	INTEL_VGA_DEVICE(0x9A68, info), \
+	INTEL_VGA_DEVICE(0x9A70, info), \
+	INTEL_VGA_DEVICE(0x9A78, info)

total: 1 errors, 0 warnings, 1 checks, 21 lines checked
8e56a0e4bf92 x86/gpu: add TGL stolen memory support
7ad31e8ccdb5 drm/i915/tgl: Check if pipe D is fused
52cd60dca858 drm/i915/tgl: use TRANSCODER_EDP_VDSC on transcoder A
228a055462e0 drm/i915/tgl: Add power well support
f5175d7ae1c3 drm/i915/tgl: Add power well to support 4th pipe
45b62a9eac96 drm/i915/tgl: Add new pll ids
91b16ba0eb18 drm/i915/tgl: Add pll manager
5e768170eebe drm/i915/tgl: Add additional ports for Tiger Lake
7787733b30b1 drm/i915/tgl: update ddi/tc clock_off bits
-:24: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'port' - possible side-effects?
#24: FILE: drivers/gpu/drm/i915/i915_reg.h:9726:
+#define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port)	(1 << ((port) == PORT_C ? 24 : \
+						       (port) + 10))

-:26: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'tc_port' - possible side-effects?
#26: FILE: drivers/gpu/drm/i915/i915_reg.h:9728:
+#define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)	(1 << ((tc_port) < PORT_TC4 ? \
+						       (tc_port) + 12 : \
+						       (tc_port) - PORT_TC4 + 21))

total: 0 errors, 0 warnings, 2 checks, 14 lines checked
5ff6a19fe86f drm/i915/tgl: Add gmbus gpio pin to port mapping
93b16ee61a60 drm/i915/tgl: port to ddc pin mapping
e7d46091155c drm/i915/tgl: select correct bit for port select
17b3e3c96fb6 drm/i915/tgl: extend intel_port_is_combophy/tc
33cbf7793050 drm/i915/tgl: init ddi port A-C for Tiger Lake
414c3ae9ddfd drm/i915/tgl: Add vbt value mapping for DDC Bus pin
9bb0ad3b4017 drm/i915/tgl: apply Display WA #1178 to fix type C dongles
cd3414367161 drm/i915/gen12: MBUS B credit change
a840d06f8c92 drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization
cf688295aed2 drm/i915/tgl: Add DPLL registers
281d1bcfc226 drm/i915/tgl: Update DPLL clock reference register

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✓ Fi.CI.BAT: success for Initial support for Tiger Lake (rev3)

[Patchwork]

== Series Details ==

Series: Initial support for Tiger Lake (rev3)
URL   : https://patchwork.freedesktop.org/series/62726/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6444 -> Patchwork_13588
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13588/

Known issues
------------

  Here are the changes found in Patchwork_13588 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live_sanitycheck:
    - fi-icl-u3:          [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/fi-icl-u3/igt@i915_selftest@live_sanitycheck.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13588/fi-icl-u3/igt@i915_selftest@live_sanitycheck.html

  
#### Possible fixes ####

  * {igt@gem_ctx_switch@legacy-render}:
    - fi-icl-guc:         [INCOMPLETE][3] ([fdo#107713]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/fi-icl-guc/igt@gem_ctx_switch@legacy-render.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13588/fi-icl-guc/igt@gem_ctx_switch@legacy-render.html

  * igt@gem_mmap_gtt@basic-read-no-prefault:
    - fi-icl-u3:          [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/fi-icl-u3/igt@gem_mmap_gtt@basic-read-no-prefault.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13588/fi-icl-u3/igt@gem_mmap_gtt@basic-read-no-prefault.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-icl-u2:          [FAIL][7] ([fdo#103167]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13588/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724


Participating hosts (53 -> 46)
------------------------------

  Missing    (7): fi-kbl-soraka fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-icl-y fi-icl-dsi fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_6444 -> Patchwork_13588

  CI_DRM_6444: 6e842ef98f5278c942ddd9bbe83b19697deef7b0 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5092: 2a66ae6626d5583240509f84117d1345a799b75a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13588: 281d1bcfc2261eb88918b65d844d7bb9f638ab9a @ git://anongit.freedesktop.org/gfx-ci/linux


== Kernel 32bit build ==

Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13588/build_32bit.log

  CALL    scripts/checksyscalls.sh
  CALL    scripts/atomic/check-atomics.sh
  CHK     include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready  (#1)
  Building modules, stage 2.
  MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1287: recipe for target 'modules' failed
make: *** [modules] Error 2


== Linux commits ==

281d1bcfc226 drm/i915/tgl: Update DPLL clock reference register
cf688295aed2 drm/i915/tgl: Add DPLL registers
a840d06f8c92 drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization
cd3414367161 drm/i915/gen12: MBUS B credit change
9bb0ad3b4017 drm/i915/tgl: apply Display WA #1178 to fix type C dongles
414c3ae9ddfd drm/i915/tgl: Add vbt value mapping for DDC Bus pin
33cbf7793050 drm/i915/tgl: init ddi port A-C for Tiger Lake
17b3e3c96fb6 drm/i915/tgl: extend intel_port_is_combophy/tc
e7d46091155c drm/i915/tgl: select correct bit for port select
93b16ee61a60 drm/i915/tgl: port to ddc pin mapping
5ff6a19fe86f drm/i915/tgl: Add gmbus gpio pin to port mapping
7787733b30b1 drm/i915/tgl: update ddi/tc clock_off bits
5e768170eebe drm/i915/tgl: Add additional ports for Tiger Lake
91b16ba0eb18 drm/i915/tgl: Add pll manager
45b62a9eac96 drm/i915/tgl: Add new pll ids
f5175d7ae1c3 drm/i915/tgl: Add power well to support 4th pipe
228a055462e0 drm/i915/tgl: Add power well support
52cd60dca858 drm/i915/tgl: use TRANSCODER_EDP_VDSC on transcoder A
7ad31e8ccdb5 drm/i915/tgl: Check if pipe D is fused
8e56a0e4bf92 x86/gpu: add TGL stolen memory support
9b52a5d4d480 drm/i915/tgl: Add TGL PCI IDs
cb543d474e7a drm/i915/tgl: Add TGL PCH detection in virtualized environment
777a2d8d8266 drm/i915/tgl: Introduce Tiger Lake PCH
0cd4b6f0f2d1 drm/i915/tgl: add initial Tiger Lake definitions
5c5e5e6008d1 drm/i915: Add 4th pipe and transcoder

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13588/
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Re: [PATCH v2 13/25] drm/i915/tgl: Add additional ports for Tiger Lake

[Souza, Jose]

On Mon, 2019-07-08 at 16:16 -0700, Lucas De Marchi wrote:
> From: Vandita Kulkarni <vandita.kulkarni@intel.com>
> 
> There are 2 new additional typeC ports in Tiger Lake and PORT-C is
> now a
> combophy port. This results in 6 typeC ports and 3 combophy ports.
> These 6 TC ports can be DP alternate mode, DP over thunderbolt,
> native
> DP on legacy DP connector or native HDMI on legacy connector.
> 
> v2: Rebase on new modular FIA code (Lucas)
> 
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c     | 12 ++++++++++++
>  drivers/gpu/drm/i915/display/intel_display.h |  2 ++
>  include/drm/i915_component.h                 |  2 +-
>  include/drm/i915_drm.h                       |  3 +++
>  4 files changed, 18 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 30e48609db1d..e72cf0bb48a7 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4297,6 +4297,18 @@ void intel_ddi_init(struct drm_i915_private
> *dev_priv, enum port port)
>  		intel_dig_port->ddi_io_power_domain =
>  			POWER_DOMAIN_PORT_DDI_F_IO;
>  		break;
> +	case PORT_G:
> +		intel_dig_port->ddi_io_power_domain =
> +			POWER_DOMAIN_PORT_DDI_G_IO;
> +		break;
> +	case PORT_H:
> +		intel_dig_port->ddi_io_power_domain =
> +			POWER_DOMAIN_PORT_DDI_H_IO;
> +		break;
> +	case PORT_I:
> +		intel_dig_port->ddi_io_power_domain =
> +			POWER_DOMAIN_PORT_DDI_I_IO;
> +		break;
>  	default:
>  		MISSING_CASE(port);
>  	}
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> b/drivers/gpu/drm/i915/display/intel_display.h
> index e781df463ffa..270b1f18dedd 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h

Nit: Missing add new ports to port_identifier() on this file but they
can't be HDMI so it should not cause any bugs, even better would be
make use of port_name()

Other than that:

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> @@ -189,6 +189,8 @@ enum tc_port {
>  	PORT_TC2,
>  	PORT_TC3,
>  	PORT_TC4,
> +	PORT_TC5,
> +	PORT_TC6,
>  
>  	I915_MAX_TC_PORTS
>  };
> diff --git a/include/drm/i915_component.h
> b/include/drm/i915_component.h
> index dcb95bd9dee6..55c3b123581b 100644
> --- a/include/drm/i915_component.h
> +++ b/include/drm/i915_component.h
> @@ -34,7 +34,7 @@ enum i915_component_type {
>  /* MAX_PORT is the number of port
>   * It must be sync with I915_MAX_PORTS defined i915_drv.h
>   */
> -#define MAX_PORTS 6
> +#define MAX_PORTS 9
>  
>  /**
>   * struct i915_audio_component - Used for direct communication
> between i915 and hda drivers
> diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
> index 7523e9a7b6e2..eb30062359d1 100644
> --- a/include/drm/i915_drm.h
> +++ b/include/drm/i915_drm.h
> @@ -109,6 +109,9 @@ enum port {
>  	PORT_D,
>  	PORT_E,
>  	PORT_F,
> +	PORT_G,
> +	PORT_H,
> +	PORT_I,
>  
>  	I915_MAX_PORTS
>  };
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Re: [PATCH v2 14/25] drm/i915/tgl: update ddi/tc clock_off bits

[Souza, Jose]

FYI

https://patchwork.freedesktop.org/patch/316805/?series=62492&rev=7

Is just waiting CI feedback to get merged and it is doing the same job
as this patch.

On Mon, 2019-07-08 at 16:16 -0700, Lucas De Marchi wrote:
> From: Mahesh Kumar <mahesh1.kumar@intel.com>
> 
> In GEN 12 PORT_C DDI clk_off bit is not equally distanced to A/B,
> it's at offset 24. Similarly TC port (5/6) clk off bits are at
> offset 22/23. Extend the macros to cover the additional ports.
> 
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 8 +++++---
>  1 file changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 5ca74eca05a4..4588df9e11de 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9723,9 +9723,11 @@ enum skl_power_gate {
>  #define DPCLKA_CFGCR0_ICL			_MMIO(0x164280)
>  #define  DPCLKA_CFGCR0_DDI_CLK_OFF(port)	(1 << ((port)
> ==  PORT_F ? 23 : \
>  						      (port) + 10))
> -#define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port)   (1 << ((port) + 10))
> -#define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) ==
> PORT_TC4 ? \
> -						      21 : (tc_port) +
> 12))
> +#define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port)	(1 << ((port) == PORT_C
> ? 24 : \
> +						       (port) + 10))
> +#define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)	(1 <<
> ((tc_port) < PORT_TC4 ? \
> +						       (tc_port) + 12 :
> \
> +						       (tc_port) -
> PORT_TC4 + 21))
>  #define  DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)	((port) ==
> PORT_F ? 21 : \
>  						(port) * 2)
>  #define  DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port)	(3 <<
> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
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Re: [PATCH v2 18/25] drm/i915/tgl: extend intel_port_is_combophy/tc

[Souza, Jose]

On Mon, 2019-07-08 at 16:16 -0700, Lucas De Marchi wrote:
> From: Mahesh Kumar <mahesh1.kumar@intel.com>
> 
> TGL has 3 combophy ports, so extend check for tigerlake in
> intel_port_is_combophy/tc function.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> 
> Cc: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 12 +++++++++---
>  1 file changed, 9 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index d1148786920e..e224dcf60e31 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6676,10 +6676,10 @@ bool intel_port_is_combophy(struct
> drm_i915_private *dev_priv, enum port port)
>  	if (port == PORT_NONE)
>  		return false;
>  
> -	if (IS_ELKHARTLAKE(dev_priv))
> +	if (IS_ELKHARTLAKE(dev_priv) || INTEL_GEN(dev_priv) >= 12)
>  		return port <= PORT_C;
>  
> -	if (INTEL_GEN(dev_priv) >= 11)
> +	if (IS_GEN(dev_priv, 11))
>  		return port <= PORT_B;
>  
>  	return false;
> @@ -6687,7 +6687,10 @@ bool intel_port_is_combophy(struct
> drm_i915_private *dev_priv, enum port port)
>  
>  bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port
> port)
>  {
> -	if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
> +	if (INTEL_GEN(dev_priv) >= 12)
> +		return port >= PORT_D && port <= PORT_I;
> +
> +	if (IS_GEN(dev_priv, 11) && !IS_ELKHARTLAKE(dev_priv))
>  		return port >= PORT_C && port <= PORT_F;
>  
>  	return false;
> @@ -6698,6 +6701,9 @@ enum tc_port intel_port_to_tc(struct
> drm_i915_private *dev_priv, enum port port)
>  	if (!intel_port_is_tc(dev_priv, port))
>  		return PORT_TC_NONE;
>  
> +	if (INTEL_GEN(dev_priv) >= 12)
> +		return port - PORT_D;
> +
>  	return port - PORT_C;
>  }
>  
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Re: [PATCH v2 19/25] drm/i915/tgl: init ddi port A-C for Tiger Lake

[Souza, Jose]

On Mon, 2019-07-08 at 16:16 -0700, Lucas De Marchi wrote:
> From: Mahesh Kumar <mahesh1.kumar@intel.com>
> 
> This patch initializes DDI PORT A, B & C for Tiger lake. Other
> TC ports need to be initialized later once corresponding code is
> there.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> 
> Cc: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index e224dcf60e31..9ccf58ff4dba 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -15302,12 +15302,17 @@ static void intel_setup_outputs(struct
> drm_i915_private *dev_priv)
>  	if (!HAS_DISPLAY(dev_priv))
>  		return;
>  
> -	if (IS_ELKHARTLAKE(dev_priv)) {
> +	if (INTEL_GEN(dev_priv) >= 12) {
> +		/* TODO: initialize TC ports as well */
> +		intel_ddi_init(dev_priv, PORT_A);
> +		intel_ddi_init(dev_priv, PORT_B);
> +		intel_ddi_init(dev_priv, PORT_C);
> +	} else if (IS_ELKHARTLAKE(dev_priv)) {
>  		intel_ddi_init(dev_priv, PORT_A);
>  		intel_ddi_init(dev_priv, PORT_B);
>  		intel_ddi_init(dev_priv, PORT_C);
>  		icl_dsi_init(dev_priv);
> -	} else if (INTEL_GEN(dev_priv) >= 11) {
> +	} else if (IS_GEN(dev_priv, 11)) {
>  		intel_ddi_init(dev_priv, PORT_A);
>  		intel_ddi_init(dev_priv, PORT_B);
>  		intel_ddi_init(dev_priv, PORT_C);
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Re: [PATCH v2 14/25] drm/i915/tgl: update ddi/tc clock_off bits

[Lucas De Marchi]

On Tue, Jul 09, 2019 at 12:49:21PM -0700, Jose Souza wrote:
>FYI
>
>https://patchwork.freedesktop.org/patch/316805/?series=62492&rev=7
>
>Is just waiting CI feedback to get merged and it is doing the same job
>as this patch.

But that depends on the enum phy infra. Is that entering now?? This
would means reworking the patches on this series as they are going to
conflict badly.

Lucas De Marchi

>
>On Mon, 2019-07-08 at 16:16 -0700, Lucas De Marchi wrote:
>> From: Mahesh Kumar <mahesh1.kumar@intel.com>
>>
>> In GEN 12 PORT_C DDI clk_off bit is not equally distanced to A/B,
>> it's at offset 24. Similarly TC port (5/6) clk off bits are at
>> offset 22/23. Extend the macros to cover the additional ports.
>>
>> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_reg.h | 8 +++++---
>>  1 file changed, 5 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h
>> index 5ca74eca05a4..4588df9e11de 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -9723,9 +9723,11 @@ enum skl_power_gate {
>>  #define DPCLKA_CFGCR0_ICL			_MMIO(0x164280)
>>  #define  DPCLKA_CFGCR0_DDI_CLK_OFF(port)	(1 << ((port)
>> ==  PORT_F ? 23 : \
>>  						      (port) + 10))
>> -#define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port)   (1 << ((port) + 10))
>> -#define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) ==
>> PORT_TC4 ? \
>> -						      21 : (tc_port) +
>> 12))
>> +#define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port)	(1 << ((port) == PORT_C
>> ? 24 : \
>> +						       (port) + 10))
>> +#define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)	(1 <<
>> ((tc_port) < PORT_TC4 ? \
>> +						       (tc_port) + 12 :
>> \
>> +						       (tc_port) -
>> PORT_TC4 + 21))
>>  #define  DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)	((port) ==
>> PORT_F ? 21 : \
>>  						(port) * 2)
>>  #define  DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port)	(3 <<
>> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
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Re: [PATCH v2 08/25] drm/i915/tgl: use TRANSCODER_EDP_VDSC on transcoder A

[Manasi Navare]

On Tue, Jul 09, 2019 at 01:07:17AM +0000, Souza, Jose wrote:
> On Mon, 2019-07-08 at 16:16 -0700, Lucas De Marchi wrote:
> > From: José Roberto de Souza <jose.souza@intel.com>
> > 
> > On TGL the special EDP transcoder is gone and it should be handled by
> > transcoder A.
> > 
> > v2 (Lucas):
> >   - Reuse POWER_DOMAIN_TRANSCODER_EDP_VDSC (suggested by Ville)
> >   - Use crtc->dev since new_crtc_state->state may be NULL on atomic
> >     commit (suggested by Maarten)
> 
> As we are reusing would be nice also rename it to something like:
> POWER_DOMAIN_TRANSCODER_VDSC_PW2
> POWER_DOMAIN_LOW_POWER_TRANSCODER_VDSC /
> POWER_DOMAIN_LP_TRANSCODER_VDSC

We did struggle initially as well to find an appropriate name and settled for
POWER_DOMAIN_TRANSCODER_EDP_VDSC but I agree that now since it is not just for EDP
but for Transcoder A which could be any connector, its better to rename the power well

POWER_DOMAIN_TRANSCODER_VDSC_PW2 or 
POWER_DOMAIN_TRANSCODER_EDP_A_VDSC and then in the comment clearly mention that
for Gen 11 it is for Transcoder EDP VDSC and then Gen 12 + it is for Transcoder A VDSC

Manasi

> 
> > 
> > Cc: Imre Deak <imre.deak@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_vdsc.c | 9 ++++++---
> >  1 file changed, 6 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > index ffec807b8960..c27912f552f0 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > @@ -459,16 +459,19 @@ int intel_dp_compute_dsc_params(struct intel_dp
> > *intel_dp,
> >  enum intel_display_power_domain
> >  intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
> >  {
> > +	struct drm_i915_private *i915 = to_i915(crtc_state->base.crtc-
> > >dev);
> >  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> >  
> >  	/*
> > -	 * On ICL VDSC/joining for eDP transcoder uses a separate power
> > well PW2
> > -	 * This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
> > +	 * On ICL+ VDSC/joining for eDP/A transcoder uses a separate
> > power well
> > +	 * PW2. This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power
> > domain.
> >  	 * For any other transcoder, VDSC/joining uses the power well
> > associated
> >  	 * with the pipe/transcoder in use. Hence another reference on
> > the
> >  	 * transcoder power domain will suffice.
> >  	 */
> > -	if (cpu_transcoder == TRANSCODER_EDP)
> > +	if (INTEL_GEN(i915) >= 12 && cpu_transcoder == TRANSCODER_A)
> > +		return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
> > +	else if (cpu_transcoder == TRANSCODER_EDP)
> >  		return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
> >  	else
> >  		return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
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Re: [PATCH v2 23/25] drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization

[Souza, Jose]

On Mon, 2019-07-08 at 16:16 -0700, Lucas De Marchi wrote:
> According to the spec when initializing the display in TGL we should
> not
> set PORT_CL_DW12 for the Aux channel of the combo PHYs. We will re-
> use the
> power well hooks from ICL so just check for IS_TIGERLAKE() inside it.


BSpec: 4301
It took me a while to find it :P


> 
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_power.c | 12 ++++++++----
>  1 file changed, 8 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index be3d4d1eece2..f040a74349df 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -458,8 +458,10 @@ icl_combo_phy_aux_power_well_enable(struct
> drm_i915_private *dev_priv,
>  	val = I915_READ(regs->driver);
>  	I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
>  
> -	val = I915_READ(ICL_PORT_CL_DW12(port));
> -	I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX);
> +	if (!IS_TIGERLAKE(dev_priv)) {

You probably want to change this to if (INTEL_GEN(dev_priv) < 12) or
something like to carry this change to future platforms.

With that:

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> +		val = I915_READ(ICL_PORT_CL_DW12(port));
> +		I915_WRITE(ICL_PORT_CL_DW12(port), val |
> ICL_LANE_ENABLE_AUX);
> +	}
>  
>  	hsw_wait_for_power_well_enable(dev_priv, power_well);
>  
> @@ -486,8 +488,10 @@ icl_combo_phy_aux_power_well_disable(struct
> drm_i915_private *dev_priv,
>  	enum port port = ICL_AUX_PW_TO_PORT(pw_idx);
>  	u32 val;
>  
> -	val = I915_READ(ICL_PORT_CL_DW12(port));
> -	I915_WRITE(ICL_PORT_CL_DW12(port), val & ~ICL_LANE_ENABLE_AUX);
> +	if (!IS_TIGERLAKE(dev_priv)) {
> +		val = I915_READ(ICL_PORT_CL_DW12(port));
> +		I915_WRITE(ICL_PORT_CL_DW12(port), val &
> ~ICL_LANE_ENABLE_AUX);
> +	}
>  
>  	val = I915_READ(regs->driver);
>  	I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
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✓ Fi.CI.IGT: success for Initial support for Tiger Lake (rev3)

[Patchwork]

== Series Details ==

Series: Initial support for Tiger Lake (rev3)
URL   : https://patchwork.freedesktop.org/series/62726/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6444_full -> Patchwork_13588_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_13588_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_isolation@rcs0-s3:
    - shard-apl:          [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +5 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-apl5/igt@gem_ctx_isolation@rcs0-s3.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13588/shard-apl5/igt@gem_ctx_isolation@rcs0-s3.html

  * igt@gem_eio@unwedge-stress:
    - shard-snb:          [PASS][3] -> [FAIL][4] ([fdo#109661])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-snb2/igt@gem_eio@unwedge-stress.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13588/shard-snb7/igt@gem_eio@unwedge-stress.html

  * igt@kms_color@pipe-c-ctm-green-to-red:
    - shard-skl:          [PASS][5] -> [FAIL][6] ([fdo#107201])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-skl10/igt@kms_color@pipe-c-ctm-green-to-red.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13588/shard-skl7/igt@kms_color@pipe-c-ctm-green-to-red.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-skl:          [PASS][7] -> [FAIL][8] ([fdo#105363])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-skl2/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13588/shard-skl8/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-snb:          [PASS][9] -> [INCOMPLETE][10] ([fdo#105411])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-snb5/igt@kms_flip@flip-vs-suspend.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13588/shard-snb1/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_frontbuffer_tracking@fbc-indfb-scaledprimary:
    - shard-iclb:         [PASS][11] -> [FAIL][12] ([fdo#103167]) +4 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-indfb-scaledprimary.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13588/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-indfb-scaledprimary.html

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          [PASS][13] -> [FAIL][14] ([fdo#108145] / [fdo#110403])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13588/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-glk:          [PASS][15] -> [INCOMPLETE][16] ([fdo#103359] / [k.org#198133])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-glk7/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13588/shard-glk2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_psr@psr2_cursor_mmap_cpu:
    - shard-iclb:         [PASS][17] -> [SKIP][18] ([fdo#109441])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13588/shard-iclb4/igt@kms_psr@psr2_cursor_mmap_cpu.html

  * igt@kms_vblank@pipe-b-query-forked-busy-hang:
    - shard-hsw:          [PASS][19] -> [INCOMPLETE][20] ([fdo#103540])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-hsw6/igt@kms_vblank@pipe-b-query-forked-busy-hang.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13588/shard-hsw7/igt@kms_vblank@pipe-b-query-forked-busy-hang.html

  * igt@perf@blocking:
    - shard-skl:          [PASS][21] -> [FAIL][22] ([fdo#110728])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-skl5/igt@perf@blocking.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13588/shard-skl1/igt@perf@blocking.html

  
#### Possible fixes ####

  * igt@gem_eio@in-flight-suspend:
    - shard-apl:          [DMESG-WARN][23] ([fdo#108566]) -> [PASS][24] +1 similar issue
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-apl7/igt@gem_eio@in-flight-suspend.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13588/shard-apl8/igt@gem_eio@in-flight-suspend.html

  * igt@gem_exec_balancer@smoke:
    - shard-iclb:         [SKIP][25] ([fdo#110854]) -> [PASS][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-iclb6/igt@gem_exec_balancer@smoke.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13588/shard-iclb4/igt@gem_exec_balancer@smoke.html

  * igt@kms_atomic_transition@1x-modeset-transitions-fencing:
    - shard-iclb:         [INCOMPLETE][27] ([fdo#107713]) -> [PASS][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-iclb4/igt@kms_atomic_transition@1x-modeset-transitions-fencing.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13588/shard-iclb5/igt@kms_atomic_transition@1x-modeset-transitions-fencing.html

  * igt@kms_color@pipe-b-ctm-red-to-blue:
    - shard-skl:          [FAIL][29] ([fdo#107201]) -> [PASS][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-skl4/igt@kms_color@pipe-b-ctm-red-to-blue.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13588/shard-skl7/igt@kms_color@pipe-b-ctm-red-to-blue.html

  * igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled:
    - shard-skl:          [FAIL][31] ([fdo#103184] / [fdo#103232]) -> [PASS][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-skl9/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13588/shard-skl2/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled.html

  * igt@kms_flip@modeset-vs-vblank-race:
    - shard-glk:          [FAIL][33] ([fdo#103060]) -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-glk8/igt@kms_flip@modeset-vs-vblank-race.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13588/shard-glk4/igt@kms_flip@modeset-vs-vblank-race.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack:
    - shard-iclb:         [FAIL][35] ([fdo#103167]) -> [PASS][36] +6 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13588/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack.html

  * igt@kms_psr@psr2_suspend:
    - shard-iclb:         [SKIP][37] ([fdo#109441]) -> [PASS][38] +1 similar issue
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-iclb7/igt@kms_psr@psr2_suspend.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13588/shard-iclb2/igt@kms_psr@psr2_suspend.html

  * igt@kms_setmode@basic:
    - shard-apl:          [FAIL][39] ([fdo#99912]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-apl8/igt@kms_setmode@basic.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13588/shard-apl1/igt@kms_setmode@basic.html
    - shard-skl:          [FAIL][41] ([fdo#99912]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-skl7/igt@kms_setmode@basic.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13588/shard-skl4/igt@kms_setmode@basic.html
    - shard-kbl:          [FAIL][43] ([fdo#99912]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-kbl7/igt@kms_setmode@basic.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13588/shard-kbl3/igt@kms_setmode@basic.html

  * igt@tools_test@tools_test:
    - shard-hsw:          [SKIP][45] ([fdo#109271]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-hsw6/igt@tools_test@tools_test.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13588/shard-hsw1/igt@tools_test@tools_test.html

  
  [fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
  [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
  [fdo#107201]: https://bugs.freedesktop.org/show_bug.cgi?id=107201
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109661]: https://bugs.freedesktop.org/show_bug.cgi?id=109661
  [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
  [fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
  [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
  [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_6444 -> Patchwork_13588

  CI_DRM_6444: 6e842ef98f5278c942ddd9bbe83b19697deef7b0 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5092: 2a66ae6626d5583240509f84117d1345a799b75a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13588: 281d1bcfc2261eb88918b65d844d7bb9f638ab9a @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13588/
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Re: [PATCH v3 16/25] drm/i915/tgl: port to ddc pin mapping

[Rodrigo Vivi]

On Tue, Jul 09, 2019 at 10:00:44AM -0700, Lucas De Marchi wrote:
> Make the icl function generic so it is based on phy type and can be
> applied to tgl as well.
> 
> I checked if this could not apply to EHL as well, but unfortunately
> there the HPD and DDC/GMBUS pins for DDI C are mapped to TypeC Port 1
> even though it doesn't have TC phy.
> 
> v2: don't add a separate function for TGL, but rather reuse the ICL one
>     (suggested by Rodrigo)
> 
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Thanks

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>


> ---
>  drivers/gpu/drm/i915/display/intel_hdmi.c | 34 +++++------------------
>  1 file changed, 7 insertions(+), 27 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 0ebec69bbbfc..dfdcd25eda02 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -2930,33 +2930,13 @@ static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
>  
>  static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
>  {
> -	u8 ddc_pin;
> +	if (intel_port_is_combophy(dev_priv, port))
> +		return GMBUS_PIN_1_BXT + port;
> +	else if (intel_port_is_tc(dev_priv, port))
> +		return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port);
>  
> -	switch (port) {
> -	case PORT_A:
> -		ddc_pin = GMBUS_PIN_1_BXT;
> -		break;
> -	case PORT_B:
> -		ddc_pin = GMBUS_PIN_2_BXT;
> -		break;
> -	case PORT_C:
> -		ddc_pin = GMBUS_PIN_9_TC1_ICP;
> -		break;
> -	case PORT_D:
> -		ddc_pin = GMBUS_PIN_10_TC2_ICP;
> -		break;
> -	case PORT_E:
> -		ddc_pin = GMBUS_PIN_11_TC3_ICP;
> -		break;
> -	case PORT_F:
> -		ddc_pin = GMBUS_PIN_12_TC4_ICP;
> -		break;
> -	default:
> -		MISSING_CASE(port);
> -		ddc_pin = GMBUS_PIN_2_BXT;
> -		break;
> -	}
> -	return ddc_pin;
> +	WARN(1, "Unknown port:%c\n", port_name(port));
> +	return GMBUS_PIN_2_BXT;
>  }
>  
>  static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
> @@ -3019,7 +2999,7 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
>  
>  	if (HAS_PCH_MCC(dev_priv))
>  		ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
> -	else if (HAS_PCH_ICP(dev_priv))
> +	else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_ICP(dev_priv))
>  		ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
>  	else if (HAS_PCH_CNP(dev_priv))
>  		ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
> -- 
> 2.21.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH v2 10/25] drm/i915/tgl: Add power well to support 4th pipe

[Rodrigo Vivi]

On Tue, Jul 09, 2019 at 09:20:42AM -0700, Lucas De Marchi wrote:
> On Tue, Jul 09, 2019 at 04:57:32AM -0700, Rodrigo Vivi wrote:
> > On Mon, Jul 08, 2019 at 04:16:14PM -0700, Lucas De Marchi wrote:
> > > From: Mika Kahola <mika.kahola@intel.com>
> > > 
> > > Add power well 5 to support 4th pipe and transcoder on TGL.
> > > 
> > > Cc: James Ausmus <james.ausmus@intel.com>
> > > Cc: Imre Deak <imre.deak@intel.com>
> > > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > ---
> > >  .../drm/i915/display/intel_display_power.c    | 30 ++++++++++++++++---
> > >  .../drm/i915/display/intel_display_power.h    |  3 ++
> > >  drivers/gpu/drm/i915/i915_reg.h               |  3 +-
> > >  3 files changed, 31 insertions(+), 5 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > index c3f42169831f..455f9aab188d 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > @@ -37,18 +37,24 @@ intel_display_power_domain_str(struct drm_i915_private *i915,
> > >  		return "PIPE_B";
> > >  	case POWER_DOMAIN_PIPE_C:
> > >  		return "PIPE_C";
> > > +	case POWER_DOMAIN_PIPE_D:
> > > +		return "PIPE_D";
> > >  	case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
> > >  		return "PIPE_A_PANEL_FITTER";
> > >  	case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
> > >  		return "PIPE_B_PANEL_FITTER";
> > >  	case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
> > >  		return "PIPE_C_PANEL_FITTER";
> > > +	case POWER_DOMAIN_PIPE_D_PANEL_FITTER:
> > > +		return "PIPE_D_PANEL_FITTER";
> > >  	case POWER_DOMAIN_TRANSCODER_A:
> > >  		return "TRANSCODER_A";
> > >  	case POWER_DOMAIN_TRANSCODER_B:
> > >  		return "TRANSCODER_B";
> > >  	case POWER_DOMAIN_TRANSCODER_C:
> > >  		return "TRANSCODER_C";
> > > +	case POWER_DOMAIN_TRANSCODER_D:
> > > +		return "TRANSCODER_D";
> > >  	case POWER_DOMAIN_TRANSCODER_EDP:
> > >  		return "TRANSCODER_EDP";
> > >  	case POWER_DOMAIN_TRANSCODER_EDP_VDSC:
> > > @@ -2451,7 +2457,6 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> > >   * - DDI_A
> > >   * - FBC
> > >   */
> > > -/* TODO: TGL_PW_5_POWER_DOMAINS: PIPE_D */
> > >  #define ICL_PW_4_POWER_DOMAINS (			\
> > >  	BIT_ULL(POWER_DOMAIN_PIPE_C) |			\
> > >  	BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |	\
> > > @@ -2539,7 +2544,13 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> > >  #define ICL_AUX_TBT4_IO_POWER_DOMAINS (			\
> > >  	BIT_ULL(POWER_DOMAIN_AUX_TBT4))
> > > 
> > > +#define TGL_PW_5_POWER_DOMAINS (			\
> > > +	BIT_ULL(POWER_DOMAIN_PIPE_D) |			\
> > > +	BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) |     \
> > > +	BIT_ULL(POWER_DOMAIN_INIT))
> > > +
> > >  #define TGL_PW_4_POWER_DOMAINS (			\
> > > +	TGL_PW_5_POWER_DOMAINS |			\
> > 
> > why?
> 
> not sure I understand this one. Are you saying we shouldn't have a new
> power well for pipe d? How would we handle the different ctl?

We should have a new one. The above block who adds PW5 domains is okay.
What I didn't understand is why to add pipe D also on PW4

> 
> > 
> > >  	BIT_ULL(POWER_DOMAIN_PIPE_C) |			\
> > >  	BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |	\
> > >  	BIT_ULL(POWER_DOMAIN_INIT))
> > > @@ -2549,7 +2560,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> > >  	BIT_ULL(POWER_DOMAIN_PIPE_B) |			\
> > >  	BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |		\
> > >  	BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |		\
> > > -	/* TODO: TRANSCODER_D */			\
> > > +	BIT_ULL(POWER_DOMAIN_TRANSCODER_D) |		\
> > >  	BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |	\
> > >  	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_LANES) |	\
> > >  	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_IO) |		\
> > > @@ -3882,7 +3893,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> > >  	},
> > >  	{
> > >  		.name = "power well 4",
> > > -		.domains = ICL_PW_4_POWER_DOMAINS,
> > > +		.domains = TGL_PW_4_POWER_DOMAINS,
> > 
> > why?
> 
> this is a leftover from v1 and should be squashed on previous patch, my
> bad. In v1 we were reusing the ICL definitions. I changed in this
> revision and forgot to squash this change there. I will send a new
> version
> 
> thanks
> 
> Lucas De Marchi
> 
> > 
> > >  		.ops = &hsw_power_well_ops,
> > >  		.id = DISP_PW_ID_NONE,
> > >  		{
> > > @@ -3892,7 +3903,18 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> > >  			.hsw.irq_pipe_mask = BIT(PIPE_C),
> > >  		}
> > >  	},
> > > -	/* TODO: power well 5 for pipe D */
> > > +	{
> > > +		.name = "power well 5",
> > > +		.domains = TGL_PW_5_POWER_DOMAINS,
> > > +		.ops = &hsw_power_well_ops,
> > > +		.id = DISP_PW_ID_NONE,
> > > +		{
> > > +			.hsw.regs = &hsw_power_well_regs,
> > > +			.hsw.idx = TGL_PW_CTL_IDX_PW_5,
> > > +			.hsw.has_fuses = true,
> > > +			.hsw.irq_pipe_mask = BIT(PIPE_D),
> > > +		},
> > > +	},
> > >  };
> > > 
> > >  static int
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
> > > index 86afd70c1fb2..ebb397e330ea 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> > > @@ -18,12 +18,15 @@ enum intel_display_power_domain {
> > >  	POWER_DOMAIN_PIPE_A,
> > >  	POWER_DOMAIN_PIPE_B,
> > >  	POWER_DOMAIN_PIPE_C,
> > > +	POWER_DOMAIN_PIPE_D,
> > >  	POWER_DOMAIN_PIPE_A_PANEL_FITTER,
> > >  	POWER_DOMAIN_PIPE_B_PANEL_FITTER,
> > >  	POWER_DOMAIN_PIPE_C_PANEL_FITTER,
> > > +	POWER_DOMAIN_PIPE_D_PANEL_FITTER,
> > >  	POWER_DOMAIN_TRANSCODER_A,
> > >  	POWER_DOMAIN_TRANSCODER_B,
> > >  	POWER_DOMAIN_TRANSCODER_C,
> > > +	POWER_DOMAIN_TRANSCODER_D,
> > >  	POWER_DOMAIN_TRANSCODER_EDP,
> > >  	POWER_DOMAIN_TRANSCODER_EDP_VDSC,
> > >  	POWER_DOMAIN_TRANSCODER_DSI_A,
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index f59cb5c45c34..5ca74eca05a4 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -9147,7 +9147,8 @@ enum {
> > >  #define   GLK_PW_CTL_IDX_DDI_A			1
> > >  #define   SKL_PW_CTL_IDX_MISC_IO		0
> > > 
> > > -/* ICL - power wells */
> > > +/* ICL/TGL - power wells */
> > > +#define   TGL_PW_CTL_IDX_PW_5			4
> > >  #define   ICL_PW_CTL_IDX_PW_4			3
> > >  #define   ICL_PW_CTL_IDX_PW_3			2
> > >  #define   ICL_PW_CTL_IDX_PW_2			1
> > > --
> > > 2.21.0
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
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Re: [PATCH v2 10/25] drm/i915/tgl: Add power well to support 4th pipe

[Lucas De Marchi]

On Wed, Jul 10, 2019 at 04:04:29AM -0700, Rodrigo Vivi wrote:
>On Tue, Jul 09, 2019 at 09:20:42AM -0700, Lucas De Marchi wrote:
>> On Tue, Jul 09, 2019 at 04:57:32AM -0700, Rodrigo Vivi wrote:
>> > On Mon, Jul 08, 2019 at 04:16:14PM -0700, Lucas De Marchi wrote:
>> > > From: Mika Kahola <mika.kahola@intel.com>
>> > >
>> > > Add power well 5 to support 4th pipe and transcoder on TGL.
>> > >
>> > > Cc: James Ausmus <james.ausmus@intel.com>
>> > > Cc: Imre Deak <imre.deak@intel.com>
>> > > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
>> > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> > > ---
>> > >  .../drm/i915/display/intel_display_power.c    | 30 ++++++++++++++++---
>> > >  .../drm/i915/display/intel_display_power.h    |  3 ++
>> > >  drivers/gpu/drm/i915/i915_reg.h               |  3 +-
>> > >  3 files changed, 31 insertions(+), 5 deletions(-)
>> > >
>> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>> > > index c3f42169831f..455f9aab188d 100644
>> > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>> > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>> > > @@ -37,18 +37,24 @@ intel_display_power_domain_str(struct drm_i915_private *i915,
>> > >  		return "PIPE_B";
>> > >  	case POWER_DOMAIN_PIPE_C:
>> > >  		return "PIPE_C";
>> > > +	case POWER_DOMAIN_PIPE_D:
>> > > +		return "PIPE_D";
>> > >  	case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
>> > >  		return "PIPE_A_PANEL_FITTER";
>> > >  	case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
>> > >  		return "PIPE_B_PANEL_FITTER";
>> > >  	case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
>> > >  		return "PIPE_C_PANEL_FITTER";
>> > > +	case POWER_DOMAIN_PIPE_D_PANEL_FITTER:
>> > > +		return "PIPE_D_PANEL_FITTER";
>> > >  	case POWER_DOMAIN_TRANSCODER_A:
>> > >  		return "TRANSCODER_A";
>> > >  	case POWER_DOMAIN_TRANSCODER_B:
>> > >  		return "TRANSCODER_B";
>> > >  	case POWER_DOMAIN_TRANSCODER_C:
>> > >  		return "TRANSCODER_C";
>> > > +	case POWER_DOMAIN_TRANSCODER_D:
>> > > +		return "TRANSCODER_D";
>> > >  	case POWER_DOMAIN_TRANSCODER_EDP:
>> > >  		return "TRANSCODER_EDP";
>> > >  	case POWER_DOMAIN_TRANSCODER_EDP_VDSC:
>> > > @@ -2451,7 +2457,6 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
>> > >   * - DDI_A
>> > >   * - FBC
>> > >   */
>> > > -/* TODO: TGL_PW_5_POWER_DOMAINS: PIPE_D */
>> > >  #define ICL_PW_4_POWER_DOMAINS (			\
>> > >  	BIT_ULL(POWER_DOMAIN_PIPE_C) |			\
>> > >  	BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |	\
>> > > @@ -2539,7 +2544,13 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
>> > >  #define ICL_AUX_TBT4_IO_POWER_DOMAINS (			\
>> > >  	BIT_ULL(POWER_DOMAIN_AUX_TBT4))
>> > >
>> > > +#define TGL_PW_5_POWER_DOMAINS (			\
>> > > +	BIT_ULL(POWER_DOMAIN_PIPE_D) |			\
>> > > +	BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) |     \
>> > > +	BIT_ULL(POWER_DOMAIN_INIT))
>> > > +
>> > >  #define TGL_PW_4_POWER_DOMAINS (			\
>> > > +	TGL_PW_5_POWER_DOMAINS |			\
>> >
>> > why?
>>
>> not sure I understand this one. Are you saying we shouldn't have a new
>> power well for pipe d? How would we handle the different ctl?
>
>We should have a new one. The above block who adds PW5 domains is okay.
>What I didn't understand is why to add pipe D also on PW4

as we chated on IRC, because there's this dependency on the enabling
sequence:

PG0 -> PG1 -> PG2 -> PG3 -> PG4 -> PG5

So to enable PG5 I need to enable all the previous power wells. When we
lookup, say, POWER_DOMAIN_PIPE_D, the bit will be set on all the
power wells, which makes this happen.

Lucas De Marchi

>
>>
>> >
>> > >  	BIT_ULL(POWER_DOMAIN_PIPE_C) |			\
>> > >  	BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |	\
>> > >  	BIT_ULL(POWER_DOMAIN_INIT))
>> > > @@ -2549,7 +2560,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
>> > >  	BIT_ULL(POWER_DOMAIN_PIPE_B) |			\
>> > >  	BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |		\
>> > >  	BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |		\
>> > > -	/* TODO: TRANSCODER_D */			\
>> > > +	BIT_ULL(POWER_DOMAIN_TRANSCODER_D) |		\
>> > >  	BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |	\
>> > >  	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_LANES) |	\
>> > >  	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_IO) |		\
>> > > @@ -3882,7 +3893,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
>> > >  	},
>> > >  	{
>> > >  		.name = "power well 4",
>> > > -		.domains = ICL_PW_4_POWER_DOMAINS,
>> > > +		.domains = TGL_PW_4_POWER_DOMAINS,
>> >
>> > why?
>>
>> this is a leftover from v1 and should be squashed on previous patch, my
>> bad. In v1 we were reusing the ICL definitions. I changed in this
>> revision and forgot to squash this change there. I will send a new
>> version
>>
>> thanks
>>
>> Lucas De Marchi
>>
>> >
>> > >  		.ops = &hsw_power_well_ops,
>> > >  		.id = DISP_PW_ID_NONE,
>> > >  		{
>> > > @@ -3892,7 +3903,18 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
>> > >  			.hsw.irq_pipe_mask = BIT(PIPE_C),
>> > >  		}
>> > >  	},
>> > > -	/* TODO: power well 5 for pipe D */
>> > > +	{
>> > > +		.name = "power well 5",
>> > > +		.domains = TGL_PW_5_POWER_DOMAINS,
>> > > +		.ops = &hsw_power_well_ops,
>> > > +		.id = DISP_PW_ID_NONE,
>> > > +		{
>> > > +			.hsw.regs = &hsw_power_well_regs,
>> > > +			.hsw.idx = TGL_PW_CTL_IDX_PW_5,
>> > > +			.hsw.has_fuses = true,
>> > > +			.hsw.irq_pipe_mask = BIT(PIPE_D),
>> > > +		},
>> > > +	},
>> > >  };
>> > >
>> > >  static int
>> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
>> > > index 86afd70c1fb2..ebb397e330ea 100644
>> > > --- a/drivers/gpu/drm/i915/display/intel_display_power.h
>> > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
>> > > @@ -18,12 +18,15 @@ enum intel_display_power_domain {
>> > >  	POWER_DOMAIN_PIPE_A,
>> > >  	POWER_DOMAIN_PIPE_B,
>> > >  	POWER_DOMAIN_PIPE_C,
>> > > +	POWER_DOMAIN_PIPE_D,
>> > >  	POWER_DOMAIN_PIPE_A_PANEL_FITTER,
>> > >  	POWER_DOMAIN_PIPE_B_PANEL_FITTER,
>> > >  	POWER_DOMAIN_PIPE_C_PANEL_FITTER,
>> > > +	POWER_DOMAIN_PIPE_D_PANEL_FITTER,
>> > >  	POWER_DOMAIN_TRANSCODER_A,
>> > >  	POWER_DOMAIN_TRANSCODER_B,
>> > >  	POWER_DOMAIN_TRANSCODER_C,
>> > > +	POWER_DOMAIN_TRANSCODER_D,
>> > >  	POWER_DOMAIN_TRANSCODER_EDP,
>> > >  	POWER_DOMAIN_TRANSCODER_EDP_VDSC,
>> > >  	POWER_DOMAIN_TRANSCODER_DSI_A,
>> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> > > index f59cb5c45c34..5ca74eca05a4 100644
>> > > --- a/drivers/gpu/drm/i915/i915_reg.h
>> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
>> > > @@ -9147,7 +9147,8 @@ enum {
>> > >  #define   GLK_PW_CTL_IDX_DDI_A			1
>> > >  #define   SKL_PW_CTL_IDX_MISC_IO		0
>> > >
>> > > -/* ICL - power wells */
>> > > +/* ICL/TGL - power wells */
>> > > +#define   TGL_PW_CTL_IDX_PW_5			4
>> > >  #define   ICL_PW_CTL_IDX_PW_4			3
>> > >  #define   ICL_PW_CTL_IDX_PW_3			2
>> > >  #define   ICL_PW_CTL_IDX_PW_2			1
>> > > --
>> > > 2.21.0
>> > >
>> > > _______________________________________________
>> > > Intel-gfx mailing list
>> > > Intel-gfx@lists.freedesktop.org
>> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>> _______________________________________________
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>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH v2 10/25] drm/i915/tgl: Add power well to support 4th pipe

[Rodrigo Vivi]

On Wed, Jul 10, 2019 at 09:02:22AM -0700, Lucas De Marchi wrote:
> On Wed, Jul 10, 2019 at 04:04:29AM -0700, Rodrigo Vivi wrote:
> > On Tue, Jul 09, 2019 at 09:20:42AM -0700, Lucas De Marchi wrote:
> > > On Tue, Jul 09, 2019 at 04:57:32AM -0700, Rodrigo Vivi wrote:
> > > > On Mon, Jul 08, 2019 at 04:16:14PM -0700, Lucas De Marchi wrote:
> > > > > From: Mika Kahola <mika.kahola@intel.com>
> > > > >
> > > > > Add power well 5 to support 4th pipe and transcoder on TGL.
> > > > >
> > > > > Cc: James Ausmus <james.ausmus@intel.com>
> > > > > Cc: Imre Deak <imre.deak@intel.com>
> > > > > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > > > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > > > ---
> > > > >  .../drm/i915/display/intel_display_power.c    | 30 ++++++++++++++++---
> > > > >  .../drm/i915/display/intel_display_power.h    |  3 ++
> > > > >  drivers/gpu/drm/i915/i915_reg.h               |  3 +-
> > > > >  3 files changed, 31 insertions(+), 5 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > > index c3f42169831f..455f9aab188d 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > > @@ -37,18 +37,24 @@ intel_display_power_domain_str(struct drm_i915_private *i915,
> > > > >  		return "PIPE_B";
> > > > >  	case POWER_DOMAIN_PIPE_C:
> > > > >  		return "PIPE_C";
> > > > > +	case POWER_DOMAIN_PIPE_D:
> > > > > +		return "PIPE_D";
> > > > >  	case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
> > > > >  		return "PIPE_A_PANEL_FITTER";
> > > > >  	case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
> > > > >  		return "PIPE_B_PANEL_FITTER";
> > > > >  	case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
> > > > >  		return "PIPE_C_PANEL_FITTER";
> > > > > +	case POWER_DOMAIN_PIPE_D_PANEL_FITTER:
> > > > > +		return "PIPE_D_PANEL_FITTER";
> > > > >  	case POWER_DOMAIN_TRANSCODER_A:
> > > > >  		return "TRANSCODER_A";
> > > > >  	case POWER_DOMAIN_TRANSCODER_B:
> > > > >  		return "TRANSCODER_B";
> > > > >  	case POWER_DOMAIN_TRANSCODER_C:
> > > > >  		return "TRANSCODER_C";
> > > > > +	case POWER_DOMAIN_TRANSCODER_D:
> > > > > +		return "TRANSCODER_D";
> > > > >  	case POWER_DOMAIN_TRANSCODER_EDP:
> > > > >  		return "TRANSCODER_EDP";
> > > > >  	case POWER_DOMAIN_TRANSCODER_EDP_VDSC:
> > > > > @@ -2451,7 +2457,6 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> > > > >   * - DDI_A
> > > > >   * - FBC
> > > > >   */
> > > > > -/* TODO: TGL_PW_5_POWER_DOMAINS: PIPE_D */
> > > > >  #define ICL_PW_4_POWER_DOMAINS (			\
> > > > >  	BIT_ULL(POWER_DOMAIN_PIPE_C) |			\
> > > > >  	BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |	\
> > > > > @@ -2539,7 +2544,13 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> > > > >  #define ICL_AUX_TBT4_IO_POWER_DOMAINS (			\
> > > > >  	BIT_ULL(POWER_DOMAIN_AUX_TBT4))
> > > > >
> > > > > +#define TGL_PW_5_POWER_DOMAINS (			\
> > > > > +	BIT_ULL(POWER_DOMAIN_PIPE_D) |			\
> > > > > +	BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) |     \
> > > > > +	BIT_ULL(POWER_DOMAIN_INIT))
> > > > > +
> > > > >  #define TGL_PW_4_POWER_DOMAINS (			\
> > > > > +	TGL_PW_5_POWER_DOMAINS |			\
> > > >
> > > > why?
> > > 
> > > not sure I understand this one. Are you saying we shouldn't have a new
> > > power well for pipe d? How would we handle the different ctl?
> > 
> > We should have a new one. The above block who adds PW5 domains is okay.
> > What I didn't understand is why to add pipe D also on PW4
> 
> as we chated on IRC, because there's this dependency on the enabling
> sequence:
> 
> PG0 -> PG1 -> PG2 -> PG3 -> PG4 -> PG5
> 
> So to enable PG5 I need to enable all the previous power wells. When we
> lookup, say, POWER_DOMAIN_PIPE_D, the bit will be set on all the
> power wells, which makes this happen.

Thanks for the info here and on irc and sorry for my inverted confusion there ;)

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Lucas De Marchi
> 
> > 
> > > 
> > > >
> > > > >  	BIT_ULL(POWER_DOMAIN_PIPE_C) |			\
> > > > >  	BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |	\
> > > > >  	BIT_ULL(POWER_DOMAIN_INIT))
> > > > > @@ -2549,7 +2560,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> > > > >  	BIT_ULL(POWER_DOMAIN_PIPE_B) |			\
> > > > >  	BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |		\
> > > > >  	BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |		\
> > > > > -	/* TODO: TRANSCODER_D */			\
> > > > > +	BIT_ULL(POWER_DOMAIN_TRANSCODER_D) |		\
> > > > >  	BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |	\
> > > > >  	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_LANES) |	\
> > > > >  	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_IO) |		\
> > > > > @@ -3882,7 +3893,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> > > > >  	},
> > > > >  	{
> > > > >  		.name = "power well 4",
> > > > > -		.domains = ICL_PW_4_POWER_DOMAINS,
> > > > > +		.domains = TGL_PW_4_POWER_DOMAINS,
> > > >
> > > > why?
> > > 
> > > this is a leftover from v1 and should be squashed on previous patch, my
> > > bad. In v1 we were reusing the ICL definitions. I changed in this
> > > revision and forgot to squash this change there. I will send a new
> > > version
> > > 
> > > thanks
> > > 
> > > Lucas De Marchi
> > > 
> > > >
> > > > >  		.ops = &hsw_power_well_ops,
> > > > >  		.id = DISP_PW_ID_NONE,
> > > > >  		{
> > > > > @@ -3892,7 +3903,18 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> > > > >  			.hsw.irq_pipe_mask = BIT(PIPE_C),
> > > > >  		}
> > > > >  	},
> > > > > -	/* TODO: power well 5 for pipe D */
> > > > > +	{
> > > > > +		.name = "power well 5",
> > > > > +		.domains = TGL_PW_5_POWER_DOMAINS,
> > > > > +		.ops = &hsw_power_well_ops,
> > > > > +		.id = DISP_PW_ID_NONE,
> > > > > +		{
> > > > > +			.hsw.regs = &hsw_power_well_regs,
> > > > > +			.hsw.idx = TGL_PW_CTL_IDX_PW_5,
> > > > > +			.hsw.has_fuses = true,
> > > > > +			.hsw.irq_pipe_mask = BIT(PIPE_D),
> > > > > +		},
> > > > > +	},
> > > > >  };
> > > > >
> > > > >  static int
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
> > > > > index 86afd70c1fb2..ebb397e330ea 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> > > > > @@ -18,12 +18,15 @@ enum intel_display_power_domain {
> > > > >  	POWER_DOMAIN_PIPE_A,
> > > > >  	POWER_DOMAIN_PIPE_B,
> > > > >  	POWER_DOMAIN_PIPE_C,
> > > > > +	POWER_DOMAIN_PIPE_D,
> > > > >  	POWER_DOMAIN_PIPE_A_PANEL_FITTER,
> > > > >  	POWER_DOMAIN_PIPE_B_PANEL_FITTER,
> > > > >  	POWER_DOMAIN_PIPE_C_PANEL_FITTER,
> > > > > +	POWER_DOMAIN_PIPE_D_PANEL_FITTER,
> > > > >  	POWER_DOMAIN_TRANSCODER_A,
> > > > >  	POWER_DOMAIN_TRANSCODER_B,
> > > > >  	POWER_DOMAIN_TRANSCODER_C,
> > > > > +	POWER_DOMAIN_TRANSCODER_D,
> > > > >  	POWER_DOMAIN_TRANSCODER_EDP,
> > > > >  	POWER_DOMAIN_TRANSCODER_EDP_VDSC,
> > > > >  	POWER_DOMAIN_TRANSCODER_DSI_A,
> > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > > > index f59cb5c45c34..5ca74eca05a4 100644
> > > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > > @@ -9147,7 +9147,8 @@ enum {
> > > > >  #define   GLK_PW_CTL_IDX_DDI_A			1
> > > > >  #define   SKL_PW_CTL_IDX_MISC_IO		0
> > > > >
> > > > > -/* ICL - power wells */
> > > > > +/* ICL/TGL - power wells */
> > > > > +#define   TGL_PW_CTL_IDX_PW_5			4
> > > > >  #define   ICL_PW_CTL_IDX_PW_4			3
> > > > >  #define   ICL_PW_CTL_IDX_PW_3			2
> > > > >  #define   ICL_PW_CTL_IDX_PW_2			1
> > > > > --
> > > > > 2.21.0
> > > > >
> > > > > _______________________________________________
> > > > > Intel-gfx mailing list
> > > > > Intel-gfx@lists.freedesktop.org
> > > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH v2 17/25] drm/i915/tgl: select correct bit for port select

[Ville Syrjälä]

On Mon, Jul 08, 2019 at 04:16:21PM -0700, Lucas De Marchi wrote:
> From: Mahesh Kumar <mahesh1.kumar@intel.com>
> 
> Bit definitions for port-select got changed for TRANS_CLK_SEL &
> TRANS_DDI_FUNC_CTL registers in TGL.
> 
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 48 +++++++++++++++++++-----
>  drivers/gpu/drm/i915/i915_reg.h          |  5 +++
>  2 files changed, 43 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index e72cf0bb48a7..5125c31af6aa 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1771,7 +1771,10 @@ void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
>  
>  	/* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
>  	temp = TRANS_DDI_FUNC_ENABLE;
> -	temp |= TRANS_DDI_SELECT_PORT(port);
> +	if (INTEL_GEN(dev_priv) >= 12)
> +		temp |= TGL_TRANS_DDI_SELECT_PORT(port);
> +	else
> +		temp |= TRANS_DDI_SELECT_PORT(port);
>  
>  	switch (crtc_state->pipe_bpp) {
>  	case 18:
> @@ -1851,8 +1854,14 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state
>  	i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
>  	u32 val = I915_READ(reg);
>  
> -	val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
> -	val |= TRANS_DDI_PORT_NONE;
> +	if (INTEL_GEN(dev_priv) >= 12) {
> +		val &= ~(TRANS_DDI_FUNC_ENABLE | TGL_TRANS_DDI_PORT_MASK |
> +			 TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
> +	} else {
> +		val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK |
> +			 TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
> +		val |= TRANS_DDI_PORT_NONE;

A bit incosistent leaving the NONE thing here. Maybe just nuke that
entirely?

Patch is
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> +	}
>  	I915_WRITE(reg, val);
>  
>  	if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
> @@ -2004,10 +2013,19 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
>  	mst_pipe_mask = 0;
>  	for_each_pipe(dev_priv, p) {
>  		enum transcoder cpu_transcoder = (enum transcoder)p;
> +		unsigned int port_mask, ddi_select;
> +
> +		if (INTEL_GEN(dev_priv) >= 12) {
> +			port_mask = TGL_TRANS_DDI_PORT_MASK;
> +			ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
> +		} else {
> +			port_mask = TRANS_DDI_PORT_MASK;
> +			ddi_select = TRANS_DDI_SELECT_PORT(port);
> +		}
>  
>  		tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
>  
> -		if ((tmp & TRANS_DDI_PORT_MASK) != TRANS_DDI_SELECT_PORT(port))
> +		if ((tmp & port_mask) != ddi_select)
>  			continue;
>  
>  		if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
> @@ -2123,9 +2141,14 @@ void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
>  	enum port port = encoder->port;
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>  
> -	if (cpu_transcoder != TRANSCODER_EDP)
> -		I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
> -			   TRANS_CLK_SEL_PORT(port));
> +	if (cpu_transcoder != TRANSCODER_EDP) {
> +		if (INTEL_GEN(dev_priv) >= 12)
> +			I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
> +				   TGL_TRANS_CLK_SEL_PORT(port));
> +		else
> +			I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
> +				   TRANS_CLK_SEL_PORT(port));
> +	}
>  }
>  
>  void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
> @@ -2133,9 +2156,14 @@ void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
>  	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>  
> -	if (cpu_transcoder != TRANSCODER_EDP)
> -		I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
> -			   TRANS_CLK_SEL_DISABLED);
> +	if (cpu_transcoder != TRANSCODER_EDP) {
> +		if (INTEL_GEN(dev_priv) >= 12)
> +			I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
> +				   TGL_TRANS_CLK_SEL_DISABLED);
> +		else
> +			I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
> +				   TRANS_CLK_SEL_DISABLED);
> +	}
>  }
>  
>  static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c554df69f289..ccfb95e2aa03 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9379,8 +9379,10 @@ enum skl_power_gate {
>  #define  TRANS_DDI_FUNC_ENABLE		(1 << 31)
>  /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
>  #define  TRANS_DDI_PORT_MASK		(7 << 28)
> +#define  TGL_TRANS_DDI_PORT_MASK	(0xf << 27)
>  #define  TRANS_DDI_PORT_SHIFT		28
>  #define  TRANS_DDI_SELECT_PORT(x)	((x) << 28)
> +#define  TGL_TRANS_DDI_SELECT_PORT(x)	(((x) + 1) << 27)
>  #define  TRANS_DDI_PORT_NONE		(0 << 28)
>  #define  TRANS_DDI_MODE_SELECT_MASK	(7 << 24)
>  #define  TRANS_DDI_MODE_SELECT_HDMI	(0 << 24)
> @@ -9591,6 +9593,9 @@ enum skl_power_gate {
>  /* For each transcoder, we need to select the corresponding port clock */
>  #define  TRANS_CLK_SEL_DISABLED		(0x0 << 29)
>  #define  TRANS_CLK_SEL_PORT(x)		(((x) + 1) << 29)
> +#define  TGL_TRANS_CLK_SEL_DISABLED	(0x0 << 28)
> +#define  TGL_TRANS_CLK_SEL_PORT(x)	(((x) + 1) << 28)
> +
>  
>  #define CDCLK_FREQ			_MMIO(0x46200)
>  
> -- 
> 2.21.0

-- 
Ville Syrjälä
Intel
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Re: [PATCH v2 24/25] drm/i915/tgl: Add DPLL registers

[Ville Syrjälä]

On Tue, Jul 09, 2019 at 08:58:32AM -0700, Lucas De Marchi wrote:
> On Tue, Jul 09, 2019 at 03:56:51PM +0300, Ville Syrjälä wrote:
> >On Mon, Jul 08, 2019 at 04:16:28PM -0700, Lucas De Marchi wrote:
> >> On TGL the port programming for combophy is very similar to ICL, so
> >> adapt the callers to possibly use the different register values.
> >>
> >> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> >> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> >> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> >> ---
> >>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 24 +++++++++++++++----
> >>  drivers/gpu/drm/i915/i915_reg.h               | 15 ++++++++++++
> >>  2 files changed, 34 insertions(+), 5 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> >> index ae1c552d7afb..330b42a1f54e 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> >> @@ -3113,8 +3113,13 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
> >>  	if (!(val & PLL_ENABLE))
> >>  		goto out;
> >>
> >> -	hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
> >> -	hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
> >> +	if (INTEL_GEN(dev_priv) >= 12) {
> >> +		hw_state->cfgcr0 = I915_READ(TGL_DPLL_CFGCR0(id));
> >> +		hw_state->cfgcr1 = I915_READ(TGL_DPLL_CFGCR1(id));
> >> +	} else {
> >> +		hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
> >> +		hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
> >> +	}
> >>
> >>  	ret = true;
> >>  out:
> >> @@ -3148,10 +3153,19 @@ static void icl_dpll_write(struct drm_i915_private *dev_priv,
> >>  {
> >>  	struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
> >>  	const enum intel_dpll_id id = pll->info->id;
> >> +	i915_reg_t cfgcr0_reg, cfgcr1_reg;
> >> +
> >> +	if (INTEL_GEN(dev_priv) >= 12) {
> >> +		cfgcr0_reg = TGL_DPLL_CFGCR0(id);
> >> +		cfgcr1_reg = TGL_DPLL_CFGCR1(id);
> >> +	} else {
> >> +		cfgcr0_reg = ICL_DPLL_CFGCR0(id);
> >> +		cfgcr1_reg = ICL_DPLL_CFGCR1(id);
> >> +	}
> >>
> >> -	I915_WRITE(ICL_DPLL_CFGCR0(id), hw_state->cfgcr0);
> >> -	I915_WRITE(ICL_DPLL_CFGCR1(id), hw_state->cfgcr1);
> >> -	POSTING_READ(ICL_DPLL_CFGCR1(id));
> >> +	I915_WRITE(cfgcr0_reg, hw_state->cfgcr0);
> >> +	I915_WRITE(cfgcr1_reg, hw_state->cfgcr1);
> >> +	POSTING_READ(cfgcr1_reg);
> >>  }
> >>
> >>  static void icl_mg_pll_write(struct drm_i915_private *dev_priv,
> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> >> index fbcc7981c8c4..84c04ea67ec8 100644
> >> --- a/drivers/gpu/drm/i915/i915_reg.h
> >> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> @@ -242,6 +242,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> >>  #define _MMIO_PIPE3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
> >>  #define _MMIO_PORT3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
> >>  #define _MMIO_PHY3(phy, a, b, c)	_MMIO(_PHY3(phy, a, b, c))
> >> +#define _MMIO_PLL3(pll, a, b, c)	_MMIO(_PICK(pll, a, b, c))
> >>
> >>  /*
> >>   * Device info offset array based helpers for groups of registers with unevenly
> >> @@ -9958,6 +9959,20 @@ enum skl_power_gate {
> >>  #define ICL_DPLL_CFGCR1(pll)		_MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \
> >>  						  _ICL_DPLL1_CFGCR1)
> >>
> >> +#define _TGL_DPLL0_CFGCR0		0x164284
> >> +#define _TGL_DPLL1_CFGCR0		0x16428C
> >> +#define _TGL_TBTPLL_CFGCR0		0x16429C
> >
> >What about DPLL4?
> 
> not all TGL skus have DPLL4. The ones that do (and were not tested
> here), are very different from what is done for EHL so we can't reuse
> the implementation. I will leave the DPLL4 on TGL for later, when it
> makes sense to add it.

Fair enough. Could maybe use a FIXME/TODO somewhere maybe?

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> 
> Lucas De Marchi
> 
> >
> >In fact looks like the ICL counterparts are borked even for ehl DPLL4.
> >
> >> +#define TGL_DPLL_CFGCR0(pll)		_MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
> >> +						  _TGL_DPLL1_CFGCR0, \
> >> +						  _TGL_TBTPLL_CFGCR0)
> >> +
> >> +#define _TGL_DPLL0_CFGCR1		0x164288
> >> +#define _TGL_DPLL1_CFGCR1		0x164290
> >> +#define _TGL_TBTPLL_CFGCR1		0x1642A0
> >> +#define TGL_DPLL_CFGCR1(pll)		_MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
> >> +						   _TGL_DPLL1_CFGCR1, \
> >> +						   _TGL_TBTPLL_CFGCR1)
> >> +
> >>  /* BXT display engine PLL */
> >>  #define BXT_DE_PLL_CTL			_MMIO(0x6d000)
> >>  #define   BXT_DE_PLL_RATIO(x)		(x)	/* {60,65,100} * 19.2MHz */
> >> --
> >> 2.21.0
> >
> >-- 
> >Ville Syrjälä
> >Intel

-- 
Ville Syrjälä
Intel
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[PATCH] drm/i915/tgl: rename TRANSCODER_EDP_VDSC to use on transcoder A

[Lucas De Marchi]

From: José Roberto de Souza <jose.souza@intel.com>

On TGL the special EDP transcoder is gone and it should be handled by
transcoder A.

v2 (Lucas):
  - Reuse POWER_DOMAIN_TRANSCODER_EDP_VDSC (suggested by Ville)
  - Use crtc->dev since new_crtc_state->state may be NULL on atomic
    commit (suggested by Maarten)
v3 (Lucas):
  - Rename power domain so it's clear it can also be used for transcoder
    A in TGL (requested by José and Manasi)

Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power.c |  6 +++---
 drivers/gpu/drm/i915/display/intel_display_power.h |  3 ++-
 drivers/gpu/drm/i915/display/intel_vdsc.c          | 14 ++++++++++----
 3 files changed, 15 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 7437fc71d289..4f4c35a5ef2a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -48,8 +48,8 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
 		return "TRANSCODER_C";
 	case POWER_DOMAIN_TRANSCODER_EDP:
 		return "TRANSCODER_EDP";
-	case POWER_DOMAIN_TRANSCODER_EDP_VDSC:
-		return "TRANSCODER_EDP_VDSC";
+	case POWER_DOMAIN_TRANSCODER_VDSC_PW2:
+		return "TRANSCODER_VDSC_PW2";
 	case POWER_DOMAIN_TRANSCODER_DSI_A:
 		return "TRANSCODER_DSI_A";
 	case POWER_DOMAIN_TRANSCODER_DSI_C:
@@ -2448,7 +2448,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
 	 */
 #define ICL_PW_2_POWER_DOMAINS (			\
 	ICL_PW_3_POWER_DOMAINS |			\
-	BIT_ULL(POWER_DOMAIN_TRANSCODER_EDP_VDSC) |		\
+	BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) |		\
 	BIT_ULL(POWER_DOMAIN_INIT))
 	/*
 	 * - KVMR (HW control)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 8f43f7051a16..cc6956132ebc 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -25,7 +25,8 @@ enum intel_display_power_domain {
 	POWER_DOMAIN_TRANSCODER_B,
 	POWER_DOMAIN_TRANSCODER_C,
 	POWER_DOMAIN_TRANSCODER_EDP,
-	POWER_DOMAIN_TRANSCODER_EDP_VDSC,
+	/* VDSC/joining for TRANSCODER_EDP (ICL) or TRANSCODER_A (TGL) */
+	POWER_DOMAIN_TRANSCODER_VDSC_PW2,
 	POWER_DOMAIN_TRANSCODER_DSI_A,
 	POWER_DOMAIN_TRANSCODER_DSI_C,
 	POWER_DOMAIN_PORT_DDI_A_LANES,
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index ffec807b8960..4ab19c432ef5 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -459,17 +459,23 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
 enum intel_display_power_domain
 intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
 {
+	struct drm_i915_private *i915 = to_i915(crtc_state->base.crtc->dev);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 
 	/*
-	 * On ICL VDSC/joining for eDP transcoder uses a separate power well PW2
-	 * This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
+	 * On ICL VDSC/joining for eDP transcoder uses a separate power well,
+	 * PW2. This requires POWER_DOMAIN_TRANSCODER_VDSC_PW2 power domain.
 	 * For any other transcoder, VDSC/joining uses the power well associated
 	 * with the pipe/transcoder in use. Hence another reference on the
 	 * transcoder power domain will suffice.
+	 *
+	 * On TGL we have the same mapping, but for transcoder A (the special
+	 * TRANSCODER_EDP is gone).
 	 */
-	if (cpu_transcoder == TRANSCODER_EDP)
-		return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
+	if (INTEL_GEN(i915) >= 12 && cpu_transcoder == TRANSCODER_A)
+		return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
+	else if (cpu_transcoder == TRANSCODER_EDP)
+		return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
 	else
 		return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
 }
-- 
2.21.0

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[PATCH v3] drm/i915/tgl: Add power well support

[Lucas De Marchi]

From: Imre Deak <imre.deak@intel.com>

The patch adds the new power wells introduced by TGL (GEN 12) and
maps these to existing/new power domains. The changes for GEN 12 wrt
to GEN 11 are the following:

- Transcoder#EDP removed from power well#1 (Transcoder#A used in
  low-power mode instead)
- Transcoder#A is now backed by power well#1 instead of power well#3
- The DDI#B/C combo PHY ports are now backed by power well#1 instead of
  power well#3
- New power well#5 added for pipe#D functionality (TODO)
- 2 additional TC ports (TC#5-6) backed by power well#3, 2 port
  specific IO power wells (only for the non-TBT modes) and 4 port
  specific AUX power wells (2-2 for TBT vs. non-TBT modes)
- Power well#2 backs now VDSC/joining for pipe#A instead of VDSC for
  eDP and MIPI DSI (TODO)

On TGL Port DDI#C changed to be a combo PHY (native DP/HDMI) and
BSpec has renamed ports DDI#D-F to TC#4-6 respectively. Thus on ICL we
have the following naming for ports:

- Combo PHYs (native DP/HDMI):
  DDI#A-B
- TBT/non-TBT (TC altmode, native DP/HDMI) PHYs:
  DDI#C-F

Starting from GEN 12 we have the following naming for ports:
- Combo PHYs (native DP/HDMI):
  DDI#A-C
- TBT/non-TBT (TC altmode, native DP/HDMI) PHYs:
  DDI TC#1-6

To save some space in the power domain enum the power domain naming in
the driver reflects the above change, that is power domains TC#1-3 are
added as aliases for DDI#D-F and new power domains are reserved for
TC#4-6.

v2 (Lucas):
  - Separate out the bits and definitions for TGL from the ICL ones.
    Fix use of TRANSCODER_EDP_VDSC, that is now the correct define since
    we don't define TRANSCODER_A_VDSC power domain to spare a one bit in
    the bitmask (suggested by Ville)
v3 (Lucas):
  - Fix missing squashes on v2
  - Rebase on renamed TRANSCODER_EDP_VDSC

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 .../drm/i915/display/intel_display_power.c    | 474 +++++++++++++++++-
 .../drm/i915/display/intel_display_power.h    |  26 +-
 drivers/gpu/drm/i915/i915_debugfs.c           |   3 +-
 drivers/gpu/drm/i915/i915_reg.h               |  20 +-
 4 files changed, 506 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 89f68b05e5c0..4c8cbc16b501 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -23,8 +23,11 @@ bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
 					 enum i915_power_well_id power_well_id);
 
 const char *
-intel_display_power_domain_str(enum intel_display_power_domain domain)
+intel_display_power_domain_str(struct drm_i915_private *i915,
+			       enum intel_display_power_domain domain)
 {
+	bool ddi_tc_ports = IS_GEN(i915, 12);
+
 	switch (domain) {
 	case POWER_DOMAIN_DISPLAY_CORE:
 		return "DISPLAY_CORE";
@@ -61,11 +64,23 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
 	case POWER_DOMAIN_PORT_DDI_C_LANES:
 		return "PORT_DDI_C_LANES";
 	case POWER_DOMAIN_PORT_DDI_D_LANES:
-		return "PORT_DDI_D_LANES";
+		BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_D_LANES !=
+			     POWER_DOMAIN_PORT_DDI_TC1_LANES);
+		return ddi_tc_ports ? "PORT_DDI_TC1_LANES" : "PORT_DDI_D_LANES";
 	case POWER_DOMAIN_PORT_DDI_E_LANES:
-		return "PORT_DDI_E_LANES";
+		BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_E_LANES !=
+			     POWER_DOMAIN_PORT_DDI_TC2_LANES);
+		return ddi_tc_ports ? "PORT_DDI_TC2_LANES" : "PORT_DDI_E_LANES";
 	case POWER_DOMAIN_PORT_DDI_F_LANES:
-		return "PORT_DDI_F_LANES";
+		BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_F_LANES !=
+			     POWER_DOMAIN_PORT_DDI_TC3_LANES);
+		return ddi_tc_ports ? "PORT_DDI_TC3_LANES" : "PORT_DDI_F_LANES";
+	case POWER_DOMAIN_PORT_DDI_TC4_LANES:
+		return "PORT_DDI_TC4_LANES";
+	case POWER_DOMAIN_PORT_DDI_TC5_LANES:
+		return "PORT_DDI_TC5_LANES";
+	case POWER_DOMAIN_PORT_DDI_TC6_LANES:
+		return "PORT_DDI_TC6_LANES";
 	case POWER_DOMAIN_PORT_DDI_A_IO:
 		return "PORT_DDI_A_IO";
 	case POWER_DOMAIN_PORT_DDI_B_IO:
@@ -73,11 +88,23 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
 	case POWER_DOMAIN_PORT_DDI_C_IO:
 		return "PORT_DDI_C_IO";
 	case POWER_DOMAIN_PORT_DDI_D_IO:
-		return "PORT_DDI_D_IO";
+		BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_D_IO !=
+			     POWER_DOMAIN_PORT_DDI_TC1_IO);
+		return ddi_tc_ports ? "PORT_DDI_TC1_IO" : "PORT_DDI_D_IO";
 	case POWER_DOMAIN_PORT_DDI_E_IO:
-		return "PORT_DDI_E_IO";
+		BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_E_IO !=
+			     POWER_DOMAIN_PORT_DDI_TC2_IO);
+		return ddi_tc_ports ? "PORT_DDI_TC2_IO" : "PORT_DDI_E_IO";
 	case POWER_DOMAIN_PORT_DDI_F_IO:
-		return "PORT_DDI_F_IO";
+		BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_F_IO !=
+			     POWER_DOMAIN_PORT_DDI_TC3_IO);
+		return ddi_tc_ports ? "PORT_DDI_TC3_IO" : "PORT_DDI_F_IO";
+	case POWER_DOMAIN_PORT_DDI_TC4_IO:
+		return "PORT_DDI_TC4_IO";
+	case POWER_DOMAIN_PORT_DDI_TC5_IO:
+		return "PORT_DDI_TC5_IO";
+	case POWER_DOMAIN_PORT_DDI_TC6_IO:
+		return "PORT_DDI_TC6_IO";
 	case POWER_DOMAIN_PORT_DSI:
 		return "PORT_DSI";
 	case POWER_DOMAIN_PORT_CRT:
@@ -95,11 +122,20 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
 	case POWER_DOMAIN_AUX_C:
 		return "AUX_C";
 	case POWER_DOMAIN_AUX_D:
-		return "AUX_D";
+		BUILD_BUG_ON(POWER_DOMAIN_AUX_D != POWER_DOMAIN_AUX_TC1);
+		return ddi_tc_ports ? "AUX_TC1" : "AUX_D";
 	case POWER_DOMAIN_AUX_E:
-		return "AUX_E";
+		BUILD_BUG_ON(POWER_DOMAIN_AUX_E != POWER_DOMAIN_AUX_TC2);
+		return ddi_tc_ports ? "AUX_TC2" : "AUX_E";
 	case POWER_DOMAIN_AUX_F:
-		return "AUX_F";
+		BUILD_BUG_ON(POWER_DOMAIN_AUX_F != POWER_DOMAIN_AUX_TC3);
+		return ddi_tc_ports ? "AUX_TC3" : "AUX_F";
+	case POWER_DOMAIN_AUX_TC4:
+		return "AUX_TC4";
+	case POWER_DOMAIN_AUX_TC5:
+		return "AUX_TC5";
+	case POWER_DOMAIN_AUX_TC6:
+		return "AUX_TC6";
 	case POWER_DOMAIN_AUX_IO_A:
 		return "AUX_IO_A";
 	case POWER_DOMAIN_AUX_TBT1:
@@ -110,6 +146,10 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
 		return "AUX_TBT3";
 	case POWER_DOMAIN_AUX_TBT4:
 		return "AUX_TBT4";
+	case POWER_DOMAIN_AUX_TBT5:
+		return "AUX_TBT5";
+	case POWER_DOMAIN_AUX_TBT6:
+		return "AUX_TBT6";
 	case POWER_DOMAIN_GMBUS:
 		return "GMBUS";
 	case POWER_DOMAIN_INIT:
@@ -1668,12 +1708,15 @@ __async_put_domains_state_ok(struct i915_power_domains *power_domains)
 static void print_power_domains(struct i915_power_domains *power_domains,
 				const char *prefix, u64 mask)
 {
+	struct drm_i915_private *i915 =
+		container_of(power_domains, struct drm_i915_private,
+			     power_domains);
 	enum intel_display_power_domain domain;
 
 	DRM_DEBUG_DRIVER("%s (%lu):\n", prefix, hweight64(mask));
 	for_each_power_domain(domain, mask)
 		DRM_DEBUG_DRIVER("%s use_count %d\n",
-				 intel_display_power_domain_str(domain),
+				 intel_display_power_domain_str(i915, domain),
 				 power_domains->domain_use_count[domain]);
 }
 
@@ -1843,7 +1886,7 @@ __intel_display_power_put_domain(struct drm_i915_private *dev_priv,
 {
 	struct i915_power_domains *power_domains;
 	struct i915_power_well *power_well;
-	const char *name = intel_display_power_domain_str(domain);
+	const char *name = intel_display_power_domain_str(dev_priv, domain);
 
 	power_domains = &dev_priv->power_domains;
 
@@ -2499,6 +2542,88 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
 #define ICL_AUX_TBT4_IO_POWER_DOMAINS (			\
 	BIT_ULL(POWER_DOMAIN_AUX_TBT4))
 
+/* TODO: TGL_PW_5_POWER_DOMAINS: PIPE_D */
+#define TGL_PW_4_POWER_DOMAINS (			\
+	BIT_ULL(POWER_DOMAIN_PIPE_C) |			\
+	BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |	\
+	BIT_ULL(POWER_DOMAIN_INIT))
+
+#define TGL_PW_3_POWER_DOMAINS (			\
+	TGL_PW_4_POWER_DOMAINS |			\
+	BIT_ULL(POWER_DOMAIN_PIPE_B) |			\
+	BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |		\
+	BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |		\
+	/* TODO: TRANSCODER_D */			\
+	BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |	\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_LANES) |	\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_IO) |		\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC2_LANES) |	\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC2_IO) |		\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC3_LANES) |	\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC3_IO) |		\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC4_LANES) |	\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC4_IO) |		\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC5_LANES) |	\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC5_IO) |		\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC6_LANES) |	\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC6_IO) |		\
+	BIT_ULL(POWER_DOMAIN_AUX_TC1) |		\
+	BIT_ULL(POWER_DOMAIN_AUX_TC2) |		\
+	BIT_ULL(POWER_DOMAIN_AUX_TC3) |		\
+	BIT_ULL(POWER_DOMAIN_AUX_TC4) |		\
+	BIT_ULL(POWER_DOMAIN_AUX_TC5) |		\
+	BIT_ULL(POWER_DOMAIN_AUX_TC6) |		\
+	BIT_ULL(POWER_DOMAIN_AUX_TBT1) |		\
+	BIT_ULL(POWER_DOMAIN_AUX_TBT2) |		\
+	BIT_ULL(POWER_DOMAIN_AUX_TBT3) |		\
+	BIT_ULL(POWER_DOMAIN_AUX_TBT4) |		\
+	BIT_ULL(POWER_DOMAIN_AUX_TBT5) |		\
+	BIT_ULL(POWER_DOMAIN_AUX_TBT6) |		\
+	BIT_ULL(POWER_DOMAIN_VGA) |			\
+	BIT_ULL(POWER_DOMAIN_AUDIO) |			\
+	BIT_ULL(POWER_DOMAIN_INIT))
+
+#define TGL_PW_2_POWER_DOMAINS (			\
+	TGL_PW_3_POWER_DOMAINS |			\
+	BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) |	\
+	BIT_ULL(POWER_DOMAIN_INIT))
+
+#define TGL_DISPLAY_DC_OFF_POWER_DOMAINS (		\
+	TGL_PW_2_POWER_DOMAINS |			\
+	BIT_ULL(POWER_DOMAIN_MODESET) |			\
+	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
+	BIT_ULL(POWER_DOMAIN_INIT))
+
+#define TGL_DDI_IO_TC1_POWER_DOMAINS (		\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_IO))
+#define TGL_DDI_IO_TC2_POWER_DOMAINS (		\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC2_IO))
+#define TGL_DDI_IO_TC3_POWER_DOMAINS (		\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC3_IO))
+#define TGL_DDI_IO_TC4_POWER_DOMAINS (		\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC4_IO))
+#define TGL_DDI_IO_TC5_POWER_DOMAINS (		\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC5_IO))
+#define TGL_DDI_IO_TC6_POWER_DOMAINS (		\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC6_IO))
+
+#define TGL_AUX_TC1_IO_POWER_DOMAINS (		\
+	BIT_ULL(POWER_DOMAIN_AUX_TC1))
+#define TGL_AUX_TC2_IO_POWER_DOMAINS (		\
+	BIT_ULL(POWER_DOMAIN_AUX_TC2))
+#define TGL_AUX_TC3_IO_POWER_DOMAINS (		\
+	BIT_ULL(POWER_DOMAIN_AUX_TC3))
+#define TGL_AUX_TC4_IO_POWER_DOMAINS (		\
+	BIT_ULL(POWER_DOMAIN_AUX_TC4))
+#define TGL_AUX_TC5_IO_POWER_DOMAINS (		\
+	BIT_ULL(POWER_DOMAIN_AUX_TC5))
+#define TGL_AUX_TC6_IO_POWER_DOMAINS (		\
+	BIT_ULL(POWER_DOMAIN_AUX_TC6))
+#define TGL_AUX_TBT5_IO_POWER_DOMAINS (		\
+	BIT_ULL(POWER_DOMAIN_AUX_TBT5))
+#define TGL_AUX_TBT6_IO_POWER_DOMAINS (		\
+	BIT_ULL(POWER_DOMAIN_AUX_TBT6))
+
 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
 	.sync_hw = i9xx_power_well_sync_hw_noop,
 	.enable = i9xx_always_on_power_well_noop,
@@ -3456,6 +3581,324 @@ static const struct i915_power_well_desc icl_power_wells[] = {
 	},
 };
 
+static const struct i915_power_well_desc tgl_power_wells[] = {
+	{
+		.name = "always-on",
+		.always_on = true,
+		.domains = POWER_DOMAIN_MASK,
+		.ops = &i9xx_always_on_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+	},
+	{
+		.name = "power well 1",
+		/* Handled by the DMC firmware */
+		.always_on = true,
+		.domains = 0,
+		.ops = &hsw_power_well_ops,
+		.id = SKL_DISP_PW_1,
+		{
+			.hsw.regs = &hsw_power_well_regs,
+			.hsw.idx = ICL_PW_CTL_IDX_PW_1,
+			.hsw.has_fuses = true,
+		},
+	},
+	{
+		.name = "DC off",
+		.domains = TGL_DISPLAY_DC_OFF_POWER_DOMAINS,
+		.ops = &gen9_dc_off_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+	},
+	{
+		.name = "power well 2",
+		.domains = TGL_PW_2_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = SKL_DISP_PW_2,
+		{
+			.hsw.regs = &hsw_power_well_regs,
+			.hsw.idx = ICL_PW_CTL_IDX_PW_2,
+			.hsw.has_fuses = true,
+		},
+	},
+	{
+		.name = "power well 3",
+		.domains = TGL_PW_3_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &hsw_power_well_regs,
+			.hsw.idx = ICL_PW_CTL_IDX_PW_3,
+			.hsw.irq_pipe_mask = BIT(PIPE_B),
+			.hsw.has_vga = true,
+			.hsw.has_fuses = true,
+		},
+	},
+	{
+		.name = "DDI A IO",
+		.domains = ICL_DDI_IO_A_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_ddi_power_well_regs,
+			.hsw.idx = ICL_PW_CTL_IDX_DDI_A,
+		}
+	},
+	{
+		.name = "DDI B IO",
+		.domains = ICL_DDI_IO_B_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_ddi_power_well_regs,
+			.hsw.idx = ICL_PW_CTL_IDX_DDI_B,
+		}
+	},
+	{
+		.name = "DDI C IO",
+		.domains = ICL_DDI_IO_C_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_ddi_power_well_regs,
+			.hsw.idx = ICL_PW_CTL_IDX_DDI_C,
+		}
+	},
+	{
+		.name = "DDI TC1 IO",
+		.domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_ddi_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
+		},
+	},
+	{
+		.name = "DDI TC2 IO",
+		.domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_ddi_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
+		},
+	},
+	{
+		.name = "DDI TC3 IO",
+		.domains = TGL_DDI_IO_TC3_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_ddi_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC3,
+		},
+	},
+	{
+		.name = "DDI TC4 IO",
+		.domains = TGL_DDI_IO_TC4_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_ddi_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC4,
+		},
+	},
+	{
+		.name = "DDI TC5 IO",
+		.domains = TGL_DDI_IO_TC5_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_ddi_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC5,
+		},
+	},
+	{
+		.name = "DDI TC6 IO",
+		.domains = TGL_DDI_IO_TC6_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_ddi_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC6,
+		},
+	},
+	{
+		.name = "AUX A",
+		.domains = ICL_AUX_A_IO_POWER_DOMAINS,
+		.ops = &icl_combo_phy_aux_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_aux_power_well_regs,
+			.hsw.idx = ICL_PW_CTL_IDX_AUX_A,
+		},
+	},
+	{
+		.name = "AUX B",
+		.domains = ICL_AUX_B_IO_POWER_DOMAINS,
+		.ops = &icl_combo_phy_aux_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_aux_power_well_regs,
+			.hsw.idx = ICL_PW_CTL_IDX_AUX_B,
+		},
+	},
+	{
+		.name = "AUX C",
+		.domains = ICL_AUX_C_IO_POWER_DOMAINS,
+		.ops = &icl_combo_phy_aux_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_aux_power_well_regs,
+			.hsw.idx = ICL_PW_CTL_IDX_AUX_C,
+		},
+	},
+	{
+		.name = "AUX TC1",
+		.domains = TGL_AUX_TC1_IO_POWER_DOMAINS,
+		.ops = &icl_tc_phy_aux_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_aux_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
+			.hsw.is_tc_tbt = false,
+		},
+	},
+	{
+		.name = "AUX TC2",
+		.domains = TGL_AUX_TC2_IO_POWER_DOMAINS,
+		.ops = &icl_tc_phy_aux_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_aux_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
+			.hsw.is_tc_tbt = false,
+		},
+	},
+	{
+		.name = "AUX TC3",
+		.domains = TGL_AUX_TC3_IO_POWER_DOMAINS,
+		.ops = &icl_tc_phy_aux_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_aux_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC3,
+			.hsw.is_tc_tbt = false,
+		},
+	},
+	{
+		.name = "AUX TC4",
+		.domains = TGL_AUX_TC4_IO_POWER_DOMAINS,
+		.ops = &icl_tc_phy_aux_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_aux_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC4,
+			.hsw.is_tc_tbt = false,
+		},
+	},
+	{
+		.name = "AUX TC5",
+		.domains = TGL_AUX_TC5_IO_POWER_DOMAINS,
+		.ops = &icl_tc_phy_aux_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_aux_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC5,
+			.hsw.is_tc_tbt = false,
+		},
+	},
+	{
+		.name = "AUX TC6",
+		.domains = TGL_AUX_TC6_IO_POWER_DOMAINS,
+		.ops = &icl_tc_phy_aux_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_aux_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC6,
+			.hsw.is_tc_tbt = false,
+		},
+	},
+	{
+		.name = "AUX TBT1",
+		.domains = ICL_AUX_TBT1_IO_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_aux_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1,
+			.hsw.is_tc_tbt = true,
+		},
+	},
+	{
+		.name = "AUX TBT2",
+		.domains = ICL_AUX_TBT2_IO_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_aux_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2,
+			.hsw.is_tc_tbt = true,
+		},
+	},
+	{
+		.name = "AUX TBT3",
+		.domains = ICL_AUX_TBT3_IO_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_aux_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3,
+			.hsw.is_tc_tbt = true,
+		},
+	},
+	{
+		.name = "AUX TBT4",
+		.domains = ICL_AUX_TBT4_IO_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_aux_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4,
+			.hsw.is_tc_tbt = true,
+		},
+	},
+	{
+		.name = "AUX TBT5",
+		.domains = TGL_AUX_TBT5_IO_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_aux_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT5,
+			.hsw.is_tc_tbt = true,
+		},
+	},
+	{
+		.name = "AUX TBT6",
+		.domains = TGL_AUX_TBT6_IO_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_aux_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT6,
+			.hsw.is_tc_tbt = true,
+		},
+	},
+	{
+		.name = "power well 4",
+		.domains = TGL_PW_4_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &hsw_power_well_regs,
+			.hsw.idx = ICL_PW_CTL_IDX_PW_4,
+			.hsw.has_fuses = true,
+			.hsw.irq_pipe_mask = BIT(PIPE_C),
+		}
+	},
+	/* TODO: power well 5 for pipe D */
+};
+
 static int
 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
 				   int disable_power_well)
@@ -3583,7 +4026,9 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
 	 * The enabling order will be from lower to higher indexed wells,
 	 * the disabling order is reversed.
 	 */
-	if (IS_GEN(dev_priv, 11)) {
+	if (IS_GEN(dev_priv, 12)) {
+		err = set_power_wells(power_domains, tgl_power_wells);
+	} else if (IS_GEN(dev_priv, 11)) {
 		err = set_power_wells(power_domains, icl_power_wells);
 	} else if (IS_CANNONLAKE(dev_priv)) {
 		err = set_power_wells(power_domains, cnl_power_wells);
@@ -4647,7 +5092,8 @@ static void intel_power_domains_dump_info(struct drm_i915_private *i915)
 
 		for_each_power_domain(domain, power_well->desc->domains)
 			DRM_DEBUG_DRIVER("  %-23s %d\n",
-					 intel_display_power_domain_str(domain),
+					 intel_display_power_domain_str(i915,
+									domain),
 					 power_domains->domain_use_count[domain]);
 	}
 }
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index cc6956132ebc..54ad4f0b0886 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -33,14 +33,29 @@ enum intel_display_power_domain {
 	POWER_DOMAIN_PORT_DDI_B_LANES,
 	POWER_DOMAIN_PORT_DDI_C_LANES,
 	POWER_DOMAIN_PORT_DDI_D_LANES,
+	POWER_DOMAIN_PORT_DDI_TC1_LANES = POWER_DOMAIN_PORT_DDI_D_LANES,
 	POWER_DOMAIN_PORT_DDI_E_LANES,
+	POWER_DOMAIN_PORT_DDI_TC2_LANES = POWER_DOMAIN_PORT_DDI_E_LANES,
 	POWER_DOMAIN_PORT_DDI_F_LANES,
+	POWER_DOMAIN_PORT_DDI_TC3_LANES = POWER_DOMAIN_PORT_DDI_F_LANES,
+	POWER_DOMAIN_PORT_DDI_TC4_LANES,
+	POWER_DOMAIN_PORT_DDI_TC5_LANES,
+	POWER_DOMAIN_PORT_DDI_TC6_LANES,
 	POWER_DOMAIN_PORT_DDI_A_IO,
 	POWER_DOMAIN_PORT_DDI_B_IO,
 	POWER_DOMAIN_PORT_DDI_C_IO,
 	POWER_DOMAIN_PORT_DDI_D_IO,
+	POWER_DOMAIN_PORT_DDI_TC1_IO = POWER_DOMAIN_PORT_DDI_D_IO,
 	POWER_DOMAIN_PORT_DDI_E_IO,
+	POWER_DOMAIN_PORT_DDI_TC2_IO = POWER_DOMAIN_PORT_DDI_E_IO,
 	POWER_DOMAIN_PORT_DDI_F_IO,
+	POWER_DOMAIN_PORT_DDI_TC3_IO = POWER_DOMAIN_PORT_DDI_F_IO,
+	POWER_DOMAIN_PORT_DDI_G_IO,
+	POWER_DOMAIN_PORT_DDI_TC4_IO = POWER_DOMAIN_PORT_DDI_G_IO,
+	POWER_DOMAIN_PORT_DDI_H_IO,
+	POWER_DOMAIN_PORT_DDI_TC5_IO = POWER_DOMAIN_PORT_DDI_H_IO,
+	POWER_DOMAIN_PORT_DDI_I_IO,
+	POWER_DOMAIN_PORT_DDI_TC6_IO = POWER_DOMAIN_PORT_DDI_I_IO,
 	POWER_DOMAIN_PORT_DSI,
 	POWER_DOMAIN_PORT_CRT,
 	POWER_DOMAIN_PORT_OTHER,
@@ -50,13 +65,21 @@ enum intel_display_power_domain {
 	POWER_DOMAIN_AUX_B,
 	POWER_DOMAIN_AUX_C,
 	POWER_DOMAIN_AUX_D,
+	POWER_DOMAIN_AUX_TC1 = POWER_DOMAIN_AUX_D,
 	POWER_DOMAIN_AUX_E,
+	POWER_DOMAIN_AUX_TC2 = POWER_DOMAIN_AUX_E,
 	POWER_DOMAIN_AUX_F,
+	POWER_DOMAIN_AUX_TC3 = POWER_DOMAIN_AUX_F,
+	POWER_DOMAIN_AUX_TC4,
+	POWER_DOMAIN_AUX_TC5,
+	POWER_DOMAIN_AUX_TC6,
 	POWER_DOMAIN_AUX_IO_A,
 	POWER_DOMAIN_AUX_TBT1,
 	POWER_DOMAIN_AUX_TBT2,
 	POWER_DOMAIN_AUX_TBT3,
 	POWER_DOMAIN_AUX_TBT4,
+	POWER_DOMAIN_AUX_TBT5,
+	POWER_DOMAIN_AUX_TBT6,
 	POWER_DOMAIN_GMBUS,
 	POWER_DOMAIN_MODESET,
 	POWER_DOMAIN_GT_IRQ,
@@ -229,7 +252,8 @@ void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
 
 const char *
-intel_display_power_domain_str(enum intel_display_power_domain domain);
+intel_display_power_domain_str(struct drm_i915_private *i915,
+			       enum intel_display_power_domain domain);
 
 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 				    enum intel_display_power_domain domain);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 3e4f58f19362..4d59972e9689 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2472,7 +2472,8 @@ static int i915_power_domain_info(struct seq_file *m, void *unused)
 
 		for_each_power_domain(power_domain, power_well->desc->domains)
 			seq_printf(m, "  %-23s %d\n",
-				 intel_display_power_domain_str(power_domain),
+				 intel_display_power_domain_str(dev_priv,
+								power_domain),
 				 power_domains->domain_use_count[power_domain]);
 	}
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c69e84a779c1..15e50ea88e90 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9149,7 +9149,7 @@ enum {
 #define   GLK_PW_CTL_IDX_DDI_A			1
 #define   SKL_PW_CTL_IDX_MISC_IO		0
 
-/* ICL - power wells */
+/* ICL/TGL - power wells */
 #define   ICL_PW_CTL_IDX_PW_4			3
 #define   ICL_PW_CTL_IDX_PW_3			2
 #define   ICL_PW_CTL_IDX_PW_2			1
@@ -9158,13 +9158,25 @@ enum {
 #define ICL_PWR_WELL_CTL_AUX1			_MMIO(0x45440)
 #define ICL_PWR_WELL_CTL_AUX2			_MMIO(0x45444)
 #define ICL_PWR_WELL_CTL_AUX4			_MMIO(0x4544C)
+#define   TGL_PW_CTL_IDX_AUX_TBT6		14
+#define   TGL_PW_CTL_IDX_AUX_TBT5		13
+#define   TGL_PW_CTL_IDX_AUX_TBT4		12
 #define   ICL_PW_CTL_IDX_AUX_TBT4		11
+#define   TGL_PW_CTL_IDX_AUX_TBT3		11
 #define   ICL_PW_CTL_IDX_AUX_TBT3		10
+#define   TGL_PW_CTL_IDX_AUX_TBT2		10
 #define   ICL_PW_CTL_IDX_AUX_TBT2		9
+#define   TGL_PW_CTL_IDX_AUX_TBT1		9
 #define   ICL_PW_CTL_IDX_AUX_TBT1		8
+#define   TGL_PW_CTL_IDX_AUX_TC6		8
+#define   TGL_PW_CTL_IDX_AUX_TC5		7
+#define   TGL_PW_CTL_IDX_AUX_TC4		6
 #define   ICL_PW_CTL_IDX_AUX_F			5
+#define   TGL_PW_CTL_IDX_AUX_TC3		5
 #define   ICL_PW_CTL_IDX_AUX_E			4
+#define   TGL_PW_CTL_IDX_AUX_TC2		4
 #define   ICL_PW_CTL_IDX_AUX_D			3
+#define   TGL_PW_CTL_IDX_AUX_TC1		3
 #define   ICL_PW_CTL_IDX_AUX_C			2
 #define   ICL_PW_CTL_IDX_AUX_B			1
 #define   ICL_PW_CTL_IDX_AUX_A			0
@@ -9172,9 +9184,15 @@ enum {
 #define ICL_PWR_WELL_CTL_DDI1			_MMIO(0x45450)
 #define ICL_PWR_WELL_CTL_DDI2			_MMIO(0x45454)
 #define ICL_PWR_WELL_CTL_DDI4			_MMIO(0x4545C)
+#define   TGL_PW_CTL_IDX_DDI_TC6		8
+#define   TGL_PW_CTL_IDX_DDI_TC5		7
+#define   TGL_PW_CTL_IDX_DDI_TC4		6
 #define   ICL_PW_CTL_IDX_DDI_F			5
+#define   TGL_PW_CTL_IDX_DDI_TC3		5
 #define   ICL_PW_CTL_IDX_DDI_E			4
+#define   TGL_PW_CTL_IDX_DDI_TC2		4
 #define   ICL_PW_CTL_IDX_DDI_D			3
+#define   TGL_PW_CTL_IDX_DDI_TC1		3
 #define   ICL_PW_CTL_IDX_DDI_C			2
 #define   ICL_PW_CTL_IDX_DDI_B			1
 #define   ICL_PW_CTL_IDX_DDI_A			0
-- 
2.21.0

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[PATCH v2] drm/i915/tgl: Add power well to support 4th pipe

[Lucas De Marchi]

From: Mika Kahola <mika.kahola@intel.com>

Add power well 5 to support 4th pipe and transcoder on TGL.

v2: remove parts that should be squashed on the generic power well
    support patch

Cc: James Ausmus <james.ausmus@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 .../drm/i915/display/intel_display_power.c    | 28 +++++++++++++++++--
 .../drm/i915/display/intel_display_power.h    |  3 ++
 drivers/gpu/drm/i915/i915_reg.h               |  1 +
 3 files changed, 29 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index fead072afd96..659c0954eaf7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -37,18 +37,24 @@ intel_display_power_domain_str(struct drm_i915_private *i915,
 		return "PIPE_B";
 	case POWER_DOMAIN_PIPE_C:
 		return "PIPE_C";
+	case POWER_DOMAIN_PIPE_D:
+		return "PIPE_D";
 	case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
 		return "PIPE_A_PANEL_FITTER";
 	case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
 		return "PIPE_B_PANEL_FITTER";
 	case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
 		return "PIPE_C_PANEL_FITTER";
+	case POWER_DOMAIN_PIPE_D_PANEL_FITTER:
+		return "PIPE_D_PANEL_FITTER";
 	case POWER_DOMAIN_TRANSCODER_A:
 		return "TRANSCODER_A";
 	case POWER_DOMAIN_TRANSCODER_B:
 		return "TRANSCODER_B";
 	case POWER_DOMAIN_TRANSCODER_C:
 		return "TRANSCODER_C";
+	case POWER_DOMAIN_TRANSCODER_D:
+		return "TRANSCODER_D";
 	case POWER_DOMAIN_TRANSCODER_EDP:
 		return "TRANSCODER_EDP";
 	case POWER_DOMAIN_TRANSCODER_VDSC_PW2:
@@ -2538,8 +2544,13 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
 #define ICL_AUX_TBT4_IO_POWER_DOMAINS (			\
 	BIT_ULL(POWER_DOMAIN_AUX_TBT4))
 
-/* TODO: TGL_PW_5_POWER_DOMAINS: PIPE_D */
+#define TGL_PW_5_POWER_DOMAINS (			\
+	BIT_ULL(POWER_DOMAIN_PIPE_D) |			\
+	BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) |     \
+	BIT_ULL(POWER_DOMAIN_INIT))
+
 #define TGL_PW_4_POWER_DOMAINS (			\
+	TGL_PW_5_POWER_DOMAINS |			\
 	BIT_ULL(POWER_DOMAIN_PIPE_C) |			\
 	BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |	\
 	BIT_ULL(POWER_DOMAIN_INIT))
@@ -2549,7 +2560,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
 	BIT_ULL(POWER_DOMAIN_PIPE_B) |			\
 	BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |		\
 	BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |		\
-	/* TODO: TRANSCODER_D */			\
+	BIT_ULL(POWER_DOMAIN_TRANSCODER_D) |		\
 	BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |	\
 	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_LANES) |	\
 	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_IO) |		\
@@ -3892,7 +3903,18 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
 			.hsw.irq_pipe_mask = BIT(PIPE_C),
 		}
 	},
-	/* TODO: power well 5 for pipe D */
+	{
+		.name = "power well 5",
+		.domains = TGL_PW_5_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &hsw_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_PW_5,
+			.hsw.has_fuses = true,
+			.hsw.irq_pipe_mask = BIT(PIPE_D),
+		},
+	},
 };
 
 static int
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 54ad4f0b0886..a264f18c95f1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -18,12 +18,15 @@ enum intel_display_power_domain {
 	POWER_DOMAIN_PIPE_A,
 	POWER_DOMAIN_PIPE_B,
 	POWER_DOMAIN_PIPE_C,
+	POWER_DOMAIN_PIPE_D,
 	POWER_DOMAIN_PIPE_A_PANEL_FITTER,
 	POWER_DOMAIN_PIPE_B_PANEL_FITTER,
 	POWER_DOMAIN_PIPE_C_PANEL_FITTER,
+	POWER_DOMAIN_PIPE_D_PANEL_FITTER,
 	POWER_DOMAIN_TRANSCODER_A,
 	POWER_DOMAIN_TRANSCODER_B,
 	POWER_DOMAIN_TRANSCODER_C,
+	POWER_DOMAIN_TRANSCODER_D,
 	POWER_DOMAIN_TRANSCODER_EDP,
 	/* VDSC/joining for TRANSCODER_EDP (ICL) or TRANSCODER_A (TGL) */
 	POWER_DOMAIN_TRANSCODER_VDSC_PW2,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 63238db21b44..5ca74eca05a4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9148,6 +9148,7 @@ enum {
 #define   SKL_PW_CTL_IDX_MISC_IO		0
 
 /* ICL/TGL - power wells */
+#define   TGL_PW_CTL_IDX_PW_5			4
 #define   ICL_PW_CTL_IDX_PW_4			3
 #define   ICL_PW_CTL_IDX_PW_3			2
 #define   ICL_PW_CTL_IDX_PW_2			1
-- 
2.21.0

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✗ Fi.CI.CHECKPATCH: warning for Initial support for Tiger Lake (rev6)

[Patchwork]

== Series Details ==

Series: Initial support for Tiger Lake (rev6)
URL   : https://patchwork.freedesktop.org/series/62726/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
84393d3db7c9 drm/i915: Add 4th pipe and transcoder
a755f8c87f85 drm/i915/tgl: add initial Tiger Lake definitions
ffc0dcf5fb65 drm/i915/tgl: Introduce Tiger Lake PCH
c9e8ac767299 drm/i915/tgl: Add TGL PCH detection in virtualized environment
9dee5c2b7821 drm/i915/tgl: Add TGL PCI IDs
-:34: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#34: FILE: include/drm/i915_pciids.h:587:
+#define INTEL_TGL_12_IDS(info) \
+	INTEL_VGA_DEVICE(0x9A49, info), \
+	INTEL_VGA_DEVICE(0x9A40, info), \
+	INTEL_VGA_DEVICE(0x9A59, info), \
+	INTEL_VGA_DEVICE(0x9A60, info), \
+	INTEL_VGA_DEVICE(0x9A68, info), \
+	INTEL_VGA_DEVICE(0x9A70, info), \
+	INTEL_VGA_DEVICE(0x9A78, info)

-:34: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#34: FILE: include/drm/i915_pciids.h:587:
+#define INTEL_TGL_12_IDS(info) \
+	INTEL_VGA_DEVICE(0x9A49, info), \
+	INTEL_VGA_DEVICE(0x9A40, info), \
+	INTEL_VGA_DEVICE(0x9A59, info), \
+	INTEL_VGA_DEVICE(0x9A60, info), \
+	INTEL_VGA_DEVICE(0x9A68, info), \
+	INTEL_VGA_DEVICE(0x9A70, info), \
+	INTEL_VGA_DEVICE(0x9A78, info)

total: 1 errors, 0 warnings, 1 checks, 21 lines checked
f4bc08927341 x86/gpu: add TGL stolen memory support
83c4d1f873b5 drm/i915/tgl: Check if pipe D is fused
2ed955964046 drm/i915/tgl: rename TRANSCODER_EDP_VDSC to use on transcoder A
7da85cb1428c drm/i915/tgl: Add power well support
5389b91d4818 drm/i915/tgl: Add power well to support 4th pipe
823df8840f44 drm/i915/tgl: Add new pll ids
7c59befa3c4c drm/i915/tgl: Add pll manager
3302928f181c drm/i915/tgl: Add additional ports for Tiger Lake
3c4b2d16195c drm/i915/tgl: update ddi/tc clock_off bits
-:24: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'port' - possible side-effects?
#24: FILE: drivers/gpu/drm/i915/i915_reg.h:9726:
+#define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port)	(1 << ((port) == PORT_C ? 24 : \
+						       (port) + 10))

-:26: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'tc_port' - possible side-effects?
#26: FILE: drivers/gpu/drm/i915/i915_reg.h:9728:
+#define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)	(1 << ((tc_port) < PORT_TC4 ? \
+						       (tc_port) + 12 : \
+						       (tc_port) - PORT_TC4 + 21))

total: 0 errors, 0 warnings, 2 checks, 14 lines checked
92d6c3891dab drm/i915/tgl: Add gmbus gpio pin to port mapping
2a57fe2608ac drm/i915/tgl: port to ddc pin mapping
3d15834d9ff4 drm/i915/tgl: select correct bit for port select
9781f9a6a87e drm/i915/tgl: extend intel_port_is_combophy/tc
96761325338d drm/i915/tgl: init ddi port A-C for Tiger Lake
998ef7f0436d drm/i915/tgl: Add vbt value mapping for DDC Bus pin
d7de35fc7516 drm/i915/tgl: apply Display WA #1178 to fix type C dongles
f4a17f51c2f6 drm/i915/gen12: MBUS B credit change
605688040111 drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization
4398be057620 drm/i915/tgl: Add DPLL registers
37e84ddbab72 drm/i915/tgl: Update DPLL clock reference register

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Re: [PATCH v2 17/25] drm/i915/tgl: select correct bit for port select

[Lucas De Marchi]

On Wed, Jul 10, 2019 at 09:40:05PM +0300, Ville Syrjälä wrote:
>On Mon, Jul 08, 2019 at 04:16:21PM -0700, Lucas De Marchi wrote:
>> From: Mahesh Kumar <mahesh1.kumar@intel.com>
>>
>> Bit definitions for port-select got changed for TRANS_CLK_SEL &
>> TRANS_DDI_FUNC_CTL registers in TGL.
>>
>> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_ddi.c | 48 +++++++++++++++++++-----
>>  drivers/gpu/drm/i915/i915_reg.h          |  5 +++
>>  2 files changed, 43 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
>> index e72cf0bb48a7..5125c31af6aa 100644
>> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>> @@ -1771,7 +1771,10 @@ void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
>>
>>  	/* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
>>  	temp = TRANS_DDI_FUNC_ENABLE;
>> -	temp |= TRANS_DDI_SELECT_PORT(port);
>> +	if (INTEL_GEN(dev_priv) >= 12)
>> +		temp |= TGL_TRANS_DDI_SELECT_PORT(port);
>> +	else
>> +		temp |= TRANS_DDI_SELECT_PORT(port);
>>
>>  	switch (crtc_state->pipe_bpp) {
>>  	case 18:
>> @@ -1851,8 +1854,14 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state
>>  	i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
>>  	u32 val = I915_READ(reg);
>>
>> -	val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
>> -	val |= TRANS_DDI_PORT_NONE;
>> +	if (INTEL_GEN(dev_priv) >= 12) {
>> +		val &= ~(TRANS_DDI_FUNC_ENABLE | TGL_TRANS_DDI_PORT_MASK |
>> +			 TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
>> +	} else {
>> +		val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK |
>> +			 TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
>> +		val |= TRANS_DDI_PORT_NONE;
>
>A bit incosistent leaving the NONE thing here. Maybe just nuke that
>entirely?

I can, but the diff is actually

-TRANS_DDI_PORT_MASK
+TGL_TRANS_DDI_PORT_MASK

Lucas De Marchi

>
>Patch is
>Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>> +	}
>>  	I915_WRITE(reg, val);
>>
>>  	if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
>> @@ -2004,10 +2013,19 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
>>  	mst_pipe_mask = 0;
>>  	for_each_pipe(dev_priv, p) {
>>  		enum transcoder cpu_transcoder = (enum transcoder)p;
>> +		unsigned int port_mask, ddi_select;
>> +
>> +		if (INTEL_GEN(dev_priv) >= 12) {
>> +			port_mask = TGL_TRANS_DDI_PORT_MASK;
>> +			ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
>> +		} else {
>> +			port_mask = TRANS_DDI_PORT_MASK;
>> +			ddi_select = TRANS_DDI_SELECT_PORT(port);
>> +		}
>>
>>  		tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
>>
>> -		if ((tmp & TRANS_DDI_PORT_MASK) != TRANS_DDI_SELECT_PORT(port))
>> +		if ((tmp & port_mask) != ddi_select)
>>  			continue;
>>
>>  		if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
>> @@ -2123,9 +2141,14 @@ void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
>>  	enum port port = encoder->port;
>>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>>
>> -	if (cpu_transcoder != TRANSCODER_EDP)
>> -		I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
>> -			   TRANS_CLK_SEL_PORT(port));
>> +	if (cpu_transcoder != TRANSCODER_EDP) {
>> +		if (INTEL_GEN(dev_priv) >= 12)
>> +			I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
>> +				   TGL_TRANS_CLK_SEL_PORT(port));
>> +		else
>> +			I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
>> +				   TRANS_CLK_SEL_PORT(port));
>> +	}
>>  }
>>
>>  void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
>> @@ -2133,9 +2156,14 @@ void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
>>  	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
>>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>>
>> -	if (cpu_transcoder != TRANSCODER_EDP)
>> -		I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
>> -			   TRANS_CLK_SEL_DISABLED);
>> +	if (cpu_transcoder != TRANSCODER_EDP) {
>> +		if (INTEL_GEN(dev_priv) >= 12)
>> +			I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
>> +				   TGL_TRANS_CLK_SEL_DISABLED);
>> +		else
>> +			I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
>> +				   TRANS_CLK_SEL_DISABLED);
>> +	}
>>  }
>>
>>  static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index c554df69f289..ccfb95e2aa03 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -9379,8 +9379,10 @@ enum skl_power_gate {
>>  #define  TRANS_DDI_FUNC_ENABLE		(1 << 31)
>>  /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
>>  #define  TRANS_DDI_PORT_MASK		(7 << 28)
>> +#define  TGL_TRANS_DDI_PORT_MASK	(0xf << 27)
>>  #define  TRANS_DDI_PORT_SHIFT		28
>>  #define  TRANS_DDI_SELECT_PORT(x)	((x) << 28)
>> +#define  TGL_TRANS_DDI_SELECT_PORT(x)	(((x) + 1) << 27)
>>  #define  TRANS_DDI_PORT_NONE		(0 << 28)
>>  #define  TRANS_DDI_MODE_SELECT_MASK	(7 << 24)
>>  #define  TRANS_DDI_MODE_SELECT_HDMI	(0 << 24)
>> @@ -9591,6 +9593,9 @@ enum skl_power_gate {
>>  /* For each transcoder, we need to select the corresponding port clock */
>>  #define  TRANS_CLK_SEL_DISABLED		(0x0 << 29)
>>  #define  TRANS_CLK_SEL_PORT(x)		(((x) + 1) << 29)
>> +#define  TGL_TRANS_CLK_SEL_DISABLED	(0x0 << 28)
>> +#define  TGL_TRANS_CLK_SEL_PORT(x)	(((x) + 1) << 28)
>> +
>>
>>  #define CDCLK_FREQ			_MMIO(0x46200)
>>
>> --
>> 2.21.0
>
>-- 
>Ville Syrjälä
>Intel
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Re: [PATCH] drm/i915/tgl: rename TRANSCODER_EDP_VDSC to use on transcoder A

[Souza, Jose]

On Wed, 2019-07-10 at 12:49 -0700, Lucas De Marchi wrote:
> From: José Roberto de Souza <jose.souza@intel.com>
> 
> On TGL the special EDP transcoder is gone and it should be handled by
> transcoder A.
> 
> v2 (Lucas):
>   - Reuse POWER_DOMAIN_TRANSCODER_EDP_VDSC (suggested by Ville)
>   - Use crtc->dev since new_crtc_state->state may be NULL on atomic
>     commit (suggested by Maarten)
> v3 (Lucas):
>   - Rename power domain so it's clear it can also be used for
> transcoder
>     A in TGL (requested by José and Manasi)
> 

Acked-by: José Roberto de Souza <jose.souza@intel.com>

> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_power.c |  6 +++---
>  drivers/gpu/drm/i915/display/intel_display_power.h |  3 ++-
>  drivers/gpu/drm/i915/display/intel_vdsc.c          | 14 ++++++++++
> ----
>  3 files changed, 15 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 7437fc71d289..4f4c35a5ef2a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -48,8 +48,8 @@ intel_display_power_domain_str(enum
> intel_display_power_domain domain)
>  		return "TRANSCODER_C";
>  	case POWER_DOMAIN_TRANSCODER_EDP:
>  		return "TRANSCODER_EDP";
> -	case POWER_DOMAIN_TRANSCODER_EDP_VDSC:
> -		return "TRANSCODER_EDP_VDSC";
> +	case POWER_DOMAIN_TRANSCODER_VDSC_PW2:
> +		return "TRANSCODER_VDSC_PW2";
>  	case POWER_DOMAIN_TRANSCODER_DSI_A:
>  		return "TRANSCODER_DSI_A";
>  	case POWER_DOMAIN_TRANSCODER_DSI_C:
> @@ -2448,7 +2448,7 @@ void intel_display_power_put(struct
> drm_i915_private *dev_priv,
>  	 */
>  #define ICL_PW_2_POWER_DOMAINS (			\
>  	ICL_PW_3_POWER_DOMAINS |			\
> -	BIT_ULL(POWER_DOMAIN_TRANSCODER_EDP_VDSC) |		\
> +	BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) |		\
>  	BIT_ULL(POWER_DOMAIN_INIT))
>  	/*
>  	 * - KVMR (HW control)
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
> b/drivers/gpu/drm/i915/display/intel_display_power.h
> index 8f43f7051a16..cc6956132ebc 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -25,7 +25,8 @@ enum intel_display_power_domain {
>  	POWER_DOMAIN_TRANSCODER_B,
>  	POWER_DOMAIN_TRANSCODER_C,
>  	POWER_DOMAIN_TRANSCODER_EDP,
> -	POWER_DOMAIN_TRANSCODER_EDP_VDSC,
> +	/* VDSC/joining for TRANSCODER_EDP (ICL) or TRANSCODER_A (TGL)
> */
> +	POWER_DOMAIN_TRANSCODER_VDSC_PW2,
>  	POWER_DOMAIN_TRANSCODER_DSI_A,
>  	POWER_DOMAIN_TRANSCODER_DSI_C,
>  	POWER_DOMAIN_PORT_DDI_A_LANES,
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index ffec807b8960..4ab19c432ef5 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -459,17 +459,23 @@ int intel_dp_compute_dsc_params(struct intel_dp
> *intel_dp,
>  enum intel_display_power_domain
>  intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
>  {
> +	struct drm_i915_private *i915 = to_i915(crtc_state->base.crtc-
> >dev);
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>  
>  	/*
> -	 * On ICL VDSC/joining for eDP transcoder uses a separate power
> well PW2
> -	 * This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
> +	 * On ICL VDSC/joining for eDP transcoder uses a separate power
> well,
> +	 * PW2. This requires POWER_DOMAIN_TRANSCODER_VDSC_PW2 power
> domain.
>  	 * For any other transcoder, VDSC/joining uses the power well
> associated
>  	 * with the pipe/transcoder in use. Hence another reference on
> the
>  	 * transcoder power domain will suffice.
> +	 *
> +	 * On TGL we have the same mapping, but for transcoder A (the
> special
> +	 * TRANSCODER_EDP is gone).
>  	 */
> -	if (cpu_transcoder == TRANSCODER_EDP)
> -		return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
> +	if (INTEL_GEN(i915) >= 12 && cpu_transcoder == TRANSCODER_A)
> +		return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
> +	else if (cpu_transcoder == TRANSCODER_EDP)
> +		return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
>  	else
>  		return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
>  }
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Re: [PATCH v2 15/25] drm/i915/tgl: Add gmbus gpio pin to port mapping

[Souza, Jose]

On Mon, 2019-07-08 at 16:16 -0700, Lucas De Marchi wrote:
> From: Mahesh Kumar <mahesh1.kumar@intel.com>
> 
> Add default GPIO pin mapping for all ports. Tiger Lake has 3 combophy
> ports and 6 TC ports, gpio pin1-3 are mapped to combophy & pin9-14
> are
> mapped to TC ports.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> 
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.h |  2 ++
>  drivers/gpu/drm/i915/display/intel_gmbus.c   | 20
> ++++++++++++++++++--
>  drivers/gpu/drm/i915/i915_reg.h              |  4 +++-
>  3 files changed, 23 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> b/drivers/gpu/drm/i915/display/intel_display.h
> index 270b1f18dedd..231d8595845a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -45,6 +45,8 @@ enum i915_gpio {
>  	GPIOK,
>  	GPIOL,
>  	GPIOM,
> +	GPION,
> +	GPIOO,
>  };
>  
>  /*
> diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c
> b/drivers/gpu/drm/i915/display/intel_gmbus.c
> index 4f6a9bd5af47..b42c79aea61a 100644
> --- a/drivers/gpu/drm/i915/display/intel_gmbus.c
> +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
> @@ -94,11 +94,25 @@ static const struct gmbus_pin gmbus_pins_mcc[] =
> {
>  	[GMBUS_PIN_9_TC1_ICP] = { "dpc", GPIOJ },
>  };
>  
> +static const struct gmbus_pin gmbus_pins_tgp[] = {
> +	[GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
> +	[GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
> +	[GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
> +	[GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
> +	[GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
> +	[GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
> +	[GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
> +	[GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION },
> +	[GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO },
> +};
> +
>  /* pin is expected to be valid */
>  static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private
> *dev_priv,
>  					     unsigned int pin)
>  {
> -	if (HAS_PCH_MCC(dev_priv))
> +	if (HAS_PCH_TGP(dev_priv))
> +		return &gmbus_pins_tgp[pin];
> +	else if (HAS_PCH_MCC(dev_priv))
>  		return &gmbus_pins_mcc[pin];
>  	else if (HAS_PCH_ICP(dev_priv))
>  		return &gmbus_pins_icp[pin];
> @@ -119,7 +133,9 @@ bool intel_gmbus_is_valid_pin(struct
> drm_i915_private *dev_priv,
>  {
>  	unsigned int size;
>  
> -	if (HAS_PCH_MCC(dev_priv))
> +	if (HAS_PCH_TGP(dev_priv))
> +		size = ARRAY_SIZE(gmbus_pins_tgp);
> +	else if (HAS_PCH_MCC(dev_priv))
>  		size = ARRAY_SIZE(gmbus_pins_mcc);
>  	else if (HAS_PCH_ICP(dev_priv))
>  		size = ARRAY_SIZE(gmbus_pins_icp);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 4588df9e11de..c554df69f289 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3254,8 +3254,10 @@ enum i915_power_well_id {
>  #define   GMBUS_PIN_10_TC2_ICP	10
>  #define   GMBUS_PIN_11_TC3_ICP	11
>  #define   GMBUS_PIN_12_TC4_ICP	12
> +#define   GMBUS_PIN_13_TC5_TGP	13
> +#define   GMBUS_PIN_14_TC6_TGP	14
>  
> -#define   GMBUS_NUM_PINS	13 /* including 0 */
> +#define   GMBUS_NUM_PINS	15 /* including 0 */
>  #define GMBUS1			_MMIO(dev_priv->gpio_mmio_base
> + 0x5104) /* command/status */
>  #define   GMBUS_SW_CLR_INT	(1 << 31)
>  #define   GMBUS_SW_RDY		(1 << 30)
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Re: [PATCH v2 20/25] drm/i915/tgl: Add vbt value mapping for DDC Bus pin

[Souza, Jose]

On Mon, 2019-07-08 at 16:16 -0700, Lucas De Marchi wrote:
> From: Mahesh Kumar <mahesh1.kumar@intel.com>
> 
> Add VBT-value to DDC bus pin mapping for the same.

We have almost the same information in 3 different places as per patch
15, 16 and this one =/

Anyways lets not block TGL to do refactors:
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> 
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_bios.c     | 17 ++++++++++++++++-
>  drivers/gpu/drm/i915/display/intel_vbt_defs.h |  3 +++
>  2 files changed, 19 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index 0c9808132d67..a08bc4f617c8 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -1354,12 +1354,27 @@ static const u8 mcc_ddc_pin_map[] = {
>  	[MCC_DDC_BUS_DDI_C] = GMBUS_PIN_9_TC1_ICP,
>  };
>  
> +static const u8 tgp_ddc_pin_map[] = {
> +	[ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
> +	[ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT,
> +	[TGL_DDC_BUS_DDI_C] = GMBUS_PIN_3_BXT,
> +	[ICL_DDC_BUS_PORT_1] = GMBUS_PIN_9_TC1_ICP,
> +	[ICL_DDC_BUS_PORT_2] = GMBUS_PIN_10_TC2_ICP,
> +	[ICL_DDC_BUS_PORT_3] = GMBUS_PIN_11_TC3_ICP,
> +	[ICL_DDC_BUS_PORT_4] = GMBUS_PIN_12_TC4_ICP,
> +	[TGL_DDC_BUS_PORT_5] = GMBUS_PIN_13_TC5_TGP,
> +	[TGL_DDC_BUS_PORT_6] = GMBUS_PIN_14_TC6_TGP,
> +};
> +
>  static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
>  {
>  	const u8 *ddc_pin_map;
>  	int n_entries;
>  
> -	if (HAS_PCH_MCC(dev_priv)) {
> +	if (HAS_PCH_TGP(dev_priv)) {
> +		ddc_pin_map = tgp_ddc_pin_map;
> +		n_entries = ARRAY_SIZE(tgp_ddc_pin_map);
> +	} else if (HAS_PCH_MCC(dev_priv)) {
>  		ddc_pin_map = mcc_ddc_pin_map;
>  		n_entries = ARRAY_SIZE(mcc_ddc_pin_map);
>  	} else if (HAS_PCH_ICP(dev_priv)) {
> diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> index 2f4894e9a03d..93f5c9d204d6 100644
> --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> @@ -310,10 +310,13 @@ enum vbt_gmbus_ddi {
>  	DDC_BUS_DDI_F,
>  	ICL_DDC_BUS_DDI_A = 0x1,
>  	ICL_DDC_BUS_DDI_B,
> +	TGL_DDC_BUS_DDI_C,
>  	ICL_DDC_BUS_PORT_1 = 0x4,
>  	ICL_DDC_BUS_PORT_2,
>  	ICL_DDC_BUS_PORT_3,
>  	ICL_DDC_BUS_PORT_4,
> +	TGL_DDC_BUS_PORT_5,
> +	TGL_DDC_BUS_PORT_6,
>  	MCC_DDC_BUS_DDI_A = 0x1,
>  	MCC_DDC_BUS_DDI_B,
>  	MCC_DDC_BUS_DDI_C = 0x4,
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✓ Fi.CI.BAT: success for Initial support for Tiger Lake (rev6)

[Patchwork]

== Series Details ==

Series: Initial support for Tiger Lake (rev6)
URL   : https://patchwork.freedesktop.org/series/62726/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6453 -> Patchwork_13610
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/

Known issues
------------

  Here are the changes found in Patchwork_13610 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@debugfs_test@read_all_entries:
    - fi-icl-u3:          [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/fi-icl-u3/igt@debugfs_test@read_all_entries.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/fi-icl-u3/igt@debugfs_test@read_all_entries.html

  * igt@i915_selftest@live_contexts:
    - fi-skl-iommu:       [PASS][3] -> [INCOMPLETE][4] ([fdo#111050])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/fi-skl-iommu/igt@i915_selftest@live_contexts.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/fi-skl-iommu/igt@i915_selftest@live_contexts.html

  
#### Possible fixes ####

  * igt@gem_basic@create-fd-close:
    - fi-icl-u3:          [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/fi-icl-u3/igt@gem_basic@create-fd-close.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/fi-icl-u3/igt@gem_basic@create-fd-close.html

  * igt@i915_selftest@live_execlists:
    - fi-skl-gvtdvm:      [DMESG-FAIL][7] -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html

  * igt@kms_chamelium@hdmi-edid-read:
    - {fi-icl-u4}:        [FAIL][9] ([fdo#111045] / [fdo#111046 ]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/fi-icl-u4/igt@kms_chamelium@hdmi-edid-read.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/fi-icl-u4/igt@kms_chamelium@hdmi-edid-read.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7567u:       [FAIL][11] ([fdo#109485]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/fi-kbl-7567u/igt@kms_chamelium@hdmi-hpd-fast.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/fi-kbl-7567u/igt@kms_chamelium@hdmi-hpd-fast.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - fi-blb-e6850:       [INCOMPLETE][13] ([fdo#107718]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/fi-blb-e6850/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/fi-blb-e6850/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  * igt@prime_vgem@basic-fence-flip:
    - fi-ilk-650:         [DMESG-WARN][15] ([fdo#106387]) -> [PASS][16] +1 similar issue
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/fi-ilk-650/igt@prime_vgem@basic-fence-flip.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/fi-ilk-650/igt@prime_vgem@basic-fence-flip.html

  
#### Warnings ####

  * igt@i915_selftest@live_hangcheck:
    - fi-icl-dsi:         [INCOMPLETE][17] ([fdo#107713] / [fdo#108569]) -> [DMESG-WARN][18] ([fdo#110801])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#106387]: https://bugs.freedesktop.org/show_bug.cgi?id=106387
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
  [fdo#110801]: https://bugs.freedesktop.org/show_bug.cgi?id=110801
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111046 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111046 
  [fdo#111050]: https://bugs.freedesktop.org/show_bug.cgi?id=111050


Participating hosts (53 -> 47)
------------------------------

  Missing    (6): fi-kbl-soraka fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_6453 -> Patchwork_13610

  CI_DRM_6453: ee7ea857b5d32c7b58b5994201e0e1e194266206 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5092: 2a66ae6626d5583240509f84117d1345a799b75a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13610: 37e84ddbab72d8edd96bac9535b746d3b9b6f573 @ git://anongit.freedesktop.org/gfx-ci/linux


== Kernel 32bit build ==

Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/build_32bit.log

  CALL    scripts/checksyscalls.sh
  CALL    scripts/atomic/check-atomics.sh
  CHK     include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready  (#1)
  Building modules, stage 2.
  MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1287: recipe for target 'modules' failed
make: *** [modules] Error 2


== Linux commits ==

37e84ddbab72 drm/i915/tgl: Update DPLL clock reference register
4398be057620 drm/i915/tgl: Add DPLL registers
605688040111 drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization
f4a17f51c2f6 drm/i915/gen12: MBUS B credit change
d7de35fc7516 drm/i915/tgl: apply Display WA #1178 to fix type C dongles
998ef7f0436d drm/i915/tgl: Add vbt value mapping for DDC Bus pin
96761325338d drm/i915/tgl: init ddi port A-C for Tiger Lake
9781f9a6a87e drm/i915/tgl: extend intel_port_is_combophy/tc
3d15834d9ff4 drm/i915/tgl: select correct bit for port select
2a57fe2608ac drm/i915/tgl: port to ddc pin mapping
92d6c3891dab drm/i915/tgl: Add gmbus gpio pin to port mapping
3c4b2d16195c drm/i915/tgl: update ddi/tc clock_off bits
3302928f181c drm/i915/tgl: Add additional ports for Tiger Lake
7c59befa3c4c drm/i915/tgl: Add pll manager
823df8840f44 drm/i915/tgl: Add new pll ids
5389b91d4818 drm/i915/tgl: Add power well to support 4th pipe
7da85cb1428c drm/i915/tgl: Add power well support
2ed955964046 drm/i915/tgl: rename TRANSCODER_EDP_VDSC to use on transcoder A
83c4d1f873b5 drm/i915/tgl: Check if pipe D is fused
f4bc08927341 x86/gpu: add TGL stolen memory support
9dee5c2b7821 drm/i915/tgl: Add TGL PCI IDs
c9e8ac767299 drm/i915/tgl: Add TGL PCH detection in virtualized environment
ffc0dcf5fb65 drm/i915/tgl: Introduce Tiger Lake PCH
a755f8c87f85 drm/i915/tgl: add initial Tiger Lake definitions
84393d3db7c9 drm/i915: Add 4th pipe and transcoder

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.IGT: success for Initial support for Tiger Lake (rev6)

[Patchwork]

== Series Details ==

Series: Initial support for Tiger Lake (rev6)
URL   : https://patchwork.freedesktop.org/series/62726/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6453_full -> Patchwork_13610_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_13610_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_softpin@noreloc-s3:
    - shard-kbl:          [PASS][1] -> [DMESG-WARN][2] ([fdo#103313])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-kbl4/igt@gem_softpin@noreloc-s3.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/shard-kbl1/igt@gem_softpin@noreloc-s3.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-skl:          [PASS][3] -> [FAIL][4] ([fdo#102670])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
    - shard-glk:          [PASS][5] -> [FAIL][6] ([fdo#105363])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-glk1/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/shard-glk1/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-skl:          [PASS][7] -> [FAIL][8] ([fdo#105363])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/shard-skl8/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-kbl:          [PASS][9] -> [DMESG-WARN][10] ([fdo#108566]) +1 similar issue
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-kbl2/igt@kms_flip@flip-vs-suspend-interruptible.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt:
    - shard-iclb:         [PASS][11] -> [FAIL][12] ([fdo#103167]) +4 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [PASS][13] -> [FAIL][14] ([fdo#108145] / [fdo#110403]) +1 similar issue
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_plane_lowres@pipe-a-tiling-y:
    - shard-iclb:         [PASS][15] -> [FAIL][16] ([fdo#103166])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-y.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/shard-iclb7/igt@kms_plane_lowres@pipe-a-tiling-y.html

  * igt@kms_psr@psr2_sprite_render:
    - shard-iclb:         [PASS][17] -> [SKIP][18] ([fdo#109441])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-iclb2/igt@kms_psr@psr2_sprite_render.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/shard-iclb8/igt@kms_psr@psr2_sprite_render.html

  * igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend:
    - shard-skl:          [PASS][19] -> [INCOMPLETE][20] ([fdo#104108])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-skl2/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/shard-skl2/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
    - shard-apl:          [PASS][21] -> [DMESG-WARN][22] ([fdo#108566]) +6 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-apl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/shard-apl2/igt@kms_vblank@pipe-a-ts-continuation-suspend.html

  
#### Possible fixes ####

  * igt@gem_softpin@noreloc-s3:
    - shard-skl:          [INCOMPLETE][23] ([fdo#104108] / [fdo#107773]) -> [PASS][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-skl9/igt@gem_softpin@noreloc-s3.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/shard-skl2/igt@gem_softpin@noreloc-s3.html

  * igt@i915_pm_rpm@debugfs-read:
    - shard-iclb:         [INCOMPLETE][25] ([fdo#107713] / [fdo#108840]) -> [PASS][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-iclb7/igt@i915_pm_rpm@debugfs-read.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/shard-iclb6/igt@i915_pm_rpm@debugfs-read.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-kbl:          [DMESG-WARN][27] ([fdo#108566]) -> [PASS][28] +2 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-kbl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/shard-kbl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
    - shard-glk:          [FAIL][29] ([fdo#104873]) -> [PASS][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-glk8/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/shard-glk5/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html

  * igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled:
    - shard-skl:          [FAIL][31] ([fdo#103184] / [fdo#103232]) -> [PASS][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-skl10/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/shard-skl7/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled.html

  * igt@kms_flip@modeset-vs-vblank-race:
    - shard-apl:          [FAIL][33] ([fdo#103060]) -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-apl6/igt@kms_flip@modeset-vs-vblank-race.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/shard-apl5/igt@kms_flip@modeset-vs-vblank-race.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff:
    - shard-iclb:         [FAIL][35] ([fdo#103167]) -> [PASS][36] +1 similar issue
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
    - shard-apl:          [DMESG-WARN][37] ([fdo#108566]) -> [PASS][38] +3 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-apl5/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html

  * igt@kms_psr@psr2_no_drrs:
    - shard-iclb:         [SKIP][39] ([fdo#109441]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-iclb7/igt@kms_psr@psr2_no_drrs.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/shard-iclb2/igt@kms_psr@psr2_no_drrs.html

  * igt@kms_setmode@basic:
    - shard-kbl:          [FAIL][41] ([fdo#99912]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-kbl7/igt@kms_setmode@basic.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/shard-kbl7/igt@kms_setmode@basic.html

  * igt@kms_vblank@pipe-c-ts-continuation-suspend:
    - shard-skl:          [INCOMPLETE][43] ([fdo#104108]) -> [PASS][44] +1 similar issue
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-skl5/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/shard-skl1/igt@kms_vblank@pipe-c-ts-continuation-suspend.html

  * igt@perf@polling:
    - shard-skl:          [FAIL][45] ([fdo#110728]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-skl8/igt@perf@polling.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/shard-skl5/igt@perf@polling.html

  * igt@tools_test@tools_test:
    - shard-snb:          [SKIP][47] ([fdo#109271]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-snb2/igt@tools_test@tools_test.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/shard-snb7/igt@tools_test@tools_test.html

  
#### Warnings ####

  * igt@kms_dp_dsc@basic-dsc-enable-edp:
    - shard-iclb:         [SKIP][49] ([fdo#109349]) -> [DMESG-WARN][50] ([fdo#107724])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-iclb4/igt@kms_dp_dsc@basic-dsc-enable-edp.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html

  * igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack:
    - shard-skl:          [FAIL][51] ([fdo#103167]) -> [FAIL][52] ([fdo#108040])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-skl7/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/shard-skl6/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html

  
  [fdo#102670]: https://bugs.freedesktop.org/show_bug.cgi?id=102670
  [fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103313]: https://bugs.freedesktop.org/show_bug.cgi?id=103313
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#104873]: https://bugs.freedesktop.org/show_bug.cgi?id=104873
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
  [fdo#108040]: https://bugs.freedesktop.org/show_bug.cgi?id=108040
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
  [fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_6453 -> Patchwork_13610

  CI_DRM_6453: ee7ea857b5d32c7b58b5994201e0e1e194266206 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5092: 2a66ae6626d5583240509f84117d1345a799b75a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13610: 37e84ddbab72d8edd96bac9535b746d3b9b6f573 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13610/
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