* [Qemu-devel] [PATCH RESEND v6 00/14] Build ACPI Heterogeneous Memory Attribute Table (HMAT)
@ 2019-07-09 7:15 Tao Xu
2019-07-09 7:15 ` [Qemu-devel] [PATCH RESEND v6 01/14] hw/arm: simplify arm_load_dtb Tao Xu
` (15 more replies)
0 siblings, 16 replies; 17+ messages in thread
From: Tao Xu @ 2019-07-09 7:15 UTC (permalink / raw)
To: imammedo, eblake, ehabkost
Cc: jingqi.liu, tao3.xu, fan.du, qemu-devel, jonathan.cameron,
dan.j.williams
This series of patches will build Heterogeneous Memory Attribute Table (HMAT)
according to the command line. The ACPI HMAT describes the memory attributes,
such as memory side cache attributes and bandwidth and latency details,
related to the Memory Proximity Domain.
The software is expected to use HMAT information as hint for optimization.
In the linux kernel, the codes in drivers/acpi/hmat/hmat.c parse and report
the platform's HMAT tables.
The V5 patches link:
https://lists.gnu.org/archive/html/qemu-devel/2019-06/msg03138.html
Changelog:
v6:
- Rebase to upstream, move numa globals in arm/sbsa-ref
- When used once or twice in the function, use
ms->numa_state->num_nodes(numa_info) directly (Igor)
- Correct some mistakes
- Use once monitor_printf in hmp_info_numa (Igor)
- Add new patch to extend CLI of "-numa node" option to indicate the
initiator numa node-id (Dan)
- Update to ACPI 6.3 (Jonathan)
- Add QMP interface to update HMAT at runtime (Igor)
- Add test cases for ACPI HMAT
v5:
- spilt the 1-6/11 and 8/11 from patch v4 to build Memory Subsystem
Address Range Structure(s) and System Locality Latency and Bandwidth
Information Structure(s) firstly.
- add 1/8 of patch v5 to simplify arm_load_dtb() (Igor)
- drop the helper machine_num_numa_nodes() and use
machine->numa_state->num_nodes (and numa_state->nodes) directly (Igor)
- Add more descriptions from ACPI spec (Igor)
- Add the reason of using stub (Igor)
- Use GArray for NUMA memory ranges data (Igor)
- Separate hmat_build_lb() (Igor)
- Drop all global variables and use local variables instead (Igor)
- Add error message when base unit < 10
- Update the hmat-lb option example by using '-numa cpu'
and '-numa memdev' (Igor)
v4:
- send the patch of "move numa global variables into MachineState"
together with HMAT patches.
https://lists.gnu.org/archive/html/qemu-devel/2019-04/msg03662.html
- spilt the 1/8 of v3 patch into two patches, 4/11 introduces
build_mem_ranges() and 5/11 builds HMAT (Igor)
- use build_append_int_noprefix() to build parts of ACPI table in
all patches (Igor)
- Split 8/8 of patch v3 into two parts, 10/11 introduces NFIT
generalizations (build_acpi_aml_common), and use it in 11/11 to
simplify hmat_build_aml (Igor)
- use MachineState instead of PCMachineState to build HMAT more
generalic (Igor)
- move the 7/8 v3 patch into the former patches
- update the version tag from 4.0 to 4.1
v3:
- rebase the fixing patch into the jingqi's patches (Eric)
- update the version tag from 3.10 to 4.0 (Eric)
v2:
Per Igor and Eric's comments, fix some coding style and small issues:
- update the version number in qapi/misc.json
- including the expansion of the acronym HMAT in qapi/misc.json
- correct spell mistakes in qapi/misc.json and qemu-options.hx
- fix the comment syle in hw/i386/acpi-build.c
and hw/acpi/hmat.h
- remove some unnecessary head files in hw/acpi/hmat.c
- use hardcoded numbers from spec to generate
Memory Subsystem Address Range Structure in hw/acpi/hmat.c
- drop the struct AcpiHmat and AcpiHmatSpaRange
in hw/acpi/hmat.h
- rewrite NFIT code to build _HMA method
Liu Jingqi (6):
hmat acpi: Build Memory Proximity Domain Attributes Structure(s)
hmat acpi: Build System Locality Latency and Bandwidth Information
Structure(s)
hmat acpi: Build Memory Side Cache Information Structure(s)
numa: Extend the CLI to provide memory latency and bandwidth
information
numa: Extend the CLI to provide memory side cache information
hmat acpi: Implement _HMA method to update HMAT at runtime
Tao Xu (8):
hw/arm: simplify arm_load_dtb
numa: move numa global variable nb_numa_nodes into MachineState
numa: move numa global variable have_numa_distance into MachineState
numa: move numa global variable numa_info into MachineState
numa: Extend CLI to provide initiator information for numa nodes
acpi: introduce aml_build_runtime_buf for NFIT generalizations
QMP: Add QMP interface to update HMAT at runtime
tests/bios-tables-test: add test cases for ACPI HMAT
exec.c | 5 +-
hw/acpi/Kconfig | 5 +
hw/acpi/Makefile.objs | 1 +
hw/acpi/acpi-stub.c | 7 +
hw/acpi/aml-build.c | 9 +-
hw/acpi/hmat.c | 552 ++++++++++++++++++++++++++++
hw/acpi/hmat.h | 172 +++++++++
hw/acpi/nvdimm.c | 49 ++-
hw/arm/aspeed.c | 5 +-
hw/arm/boot.c | 20 +-
hw/arm/collie.c | 8 +-
hw/arm/cubieboard.c | 5 +-
hw/arm/exynos4_boards.c | 7 +-
hw/arm/highbank.c | 8 +-
hw/arm/imx25_pdk.c | 5 +-
hw/arm/integratorcp.c | 8 +-
hw/arm/kzm.c | 5 +-
hw/arm/mainstone.c | 5 +-
hw/arm/mcimx6ul-evk.c | 5 +-
hw/arm/mcimx7d-sabre.c | 5 +-
hw/arm/musicpal.c | 8 +-
hw/arm/nseries.c | 5 +-
hw/arm/omap_sx1.c | 5 +-
hw/arm/palm.c | 10 +-
hw/arm/raspi.c | 6 +-
hw/arm/realview.c | 5 +-
hw/arm/sabrelite.c | 5 +-
hw/arm/sbsa-ref.c | 12 +-
hw/arm/spitz.c | 5 +-
hw/arm/tosa.c | 8 +-
hw/arm/versatilepb.c | 5 +-
hw/arm/vexpress.c | 5 +-
hw/arm/virt-acpi-build.c | 19 +-
hw/arm/virt.c | 17 +-
hw/arm/xilinx_zynq.c | 8 +-
hw/arm/xlnx-versal-virt.c | 7 +-
hw/arm/xlnx-zcu102.c | 5 +-
hw/arm/z2.c | 8 +-
hw/core/machine-hmp-cmds.c | 12 +-
hw/core/machine-qmp-cmds.c | 39 ++
hw/core/machine.c | 42 ++-
hw/core/numa.c | 300 +++++++++++++--
hw/i386/acpi-build.c | 11 +-
hw/i386/pc.c | 13 +-
hw/i386/pc_piix.c | 6 +
hw/i386/pc_q35.c | 6 +
hw/mem/pc-dimm.c | 2 +
hw/pci-bridge/pci_expander_bridge.c | 3 +-
hw/ppc/spapr.c | 33 +-
hw/ppc/spapr_pci.c | 4 +-
include/hw/acpi/aml-build.h | 2 +-
include/hw/arm/boot.h | 4 +-
include/hw/boards.h | 1 +
include/hw/mem/nvdimm.h | 6 +
include/qemu/typedefs.h | 2 +
include/sysemu/numa.h | 35 +-
include/sysemu/sysemu.h | 24 ++
qapi/machine.json | 235 +++++++++++-
qemu-options.hx | 84 ++++-
tests/bios-tables-test.c | 43 +++
60 files changed, 1672 insertions(+), 264 deletions(-)
create mode 100644 hw/acpi/hmat.c
create mode 100644 hw/acpi/hmat.h
--
2.20.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH RESEND v6 01/14] hw/arm: simplify arm_load_dtb
2019-07-09 7:15 [Qemu-devel] [PATCH RESEND v6 00/14] Build ACPI Heterogeneous Memory Attribute Table (HMAT) Tao Xu
@ 2019-07-09 7:15 ` Tao Xu
2019-07-09 7:15 ` [Qemu-devel] [PATCH RESEND v6 02/14] numa: move numa global variable nb_numa_nodes into MachineState Tao Xu
` (14 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Tao Xu @ 2019-07-09 7:15 UTC (permalink / raw)
To: imammedo, eblake, ehabkost
Cc: jingqi.liu, tao3.xu, fan.du, qemu-devel, jonathan.cameron,
dan.j.williams
In struct arm_boot_info, kernel_filename, initrd_filename and
kernel_cmdline are copied from from MachineState. This patch add
MachineState as a parameter into arm_load_dtb() and move the copy chunk
of kernel_filename, initrd_filename and kernel_cmdline into
arm_load_kernel().
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Liu Jingqi <jingqi.liu@intel.com>
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Tao Xu <tao3.xu@intel.com>
---
Changes in v6:
- rebase to upstream, move the copy chunk of kernel_filename
arm_load_kernel() in arm/sbsa-ref
---
hw/arm/aspeed.c | 5 +----
hw/arm/boot.c | 14 ++++++++------
hw/arm/collie.c | 8 +-------
hw/arm/cubieboard.c | 5 +----
hw/arm/exynos4_boards.c | 7 ++-----
hw/arm/highbank.c | 8 +-------
hw/arm/imx25_pdk.c | 5 +----
hw/arm/integratorcp.c | 8 +-------
hw/arm/kzm.c | 5 +----
hw/arm/mainstone.c | 5 +----
hw/arm/mcimx6ul-evk.c | 5 +----
hw/arm/mcimx7d-sabre.c | 5 +----
hw/arm/musicpal.c | 8 +-------
hw/arm/nseries.c | 5 +----
hw/arm/omap_sx1.c | 5 +----
hw/arm/palm.c | 10 ++--------
hw/arm/raspi.c | 6 +-----
hw/arm/realview.c | 5 +----
hw/arm/sabrelite.c | 5 +----
hw/arm/sbsa-ref.c | 3 +--
hw/arm/spitz.c | 5 +----
hw/arm/tosa.c | 8 +-------
hw/arm/versatilepb.c | 5 +----
hw/arm/vexpress.c | 5 +----
hw/arm/virt.c | 8 +++-----
hw/arm/xilinx_zynq.c | 8 +-------
hw/arm/xlnx-versal-virt.c | 7 ++-----
hw/arm/xlnx-zcu102.c | 5 +----
hw/arm/z2.c | 8 +-------
include/hw/arm/boot.h | 4 ++--
30 files changed, 43 insertions(+), 147 deletions(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 843b708247..f8733b86b9 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -241,9 +241,6 @@ static void aspeed_board_init(MachineState *machine,
write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort);
}
- aspeed_board_binfo.kernel_filename = machine->kernel_filename;
- aspeed_board_binfo.initrd_filename = machine->initrd_filename;
- aspeed_board_binfo.kernel_cmdline = machine->kernel_cmdline;
aspeed_board_binfo.ram_size = ram_size;
aspeed_board_binfo.loader_start = sc->info->memmap[ASPEED_SDRAM];
aspeed_board_binfo.nb_cpus = bmc->soc.num_cpus;
@@ -252,7 +249,7 @@ static void aspeed_board_init(MachineState *machine,
cfg->i2c_init(bmc);
}
- arm_load_kernel(ARM_CPU(first_cpu), &aspeed_board_binfo);
+ arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
}
static void palmetto_bmc_i2c_init(AspeedBoardState *bmc)
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index 1fb24fbef2..a90151f465 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -524,7 +524,7 @@ static void fdt_add_psci_node(void *fdt)
}
int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo,
- hwaddr addr_limit, AddressSpace *as)
+ hwaddr addr_limit, AddressSpace *as, MachineState *ms)
{
void *fdt = NULL;
int size, rc, n = 0;
@@ -627,9 +627,9 @@ int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo,
qemu_fdt_add_subnode(fdt, "/chosen");
}
- if (binfo->kernel_cmdline && *binfo->kernel_cmdline) {
+ if (ms->kernel_cmdline && *ms->kernel_cmdline) {
rc = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
- binfo->kernel_cmdline);
+ ms->kernel_cmdline);
if (rc < 0) {
fprintf(stderr, "couldn't set /chosen/bootargs\n");
goto fail;
@@ -1244,7 +1244,7 @@ static void arm_setup_firmware_boot(ARMCPU *cpu, struct arm_boot_info *info)
*/
}
-void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
+void arm_load_kernel(ARMCPU *cpu, MachineState *ms, struct arm_boot_info *info)
{
CPUState *cs;
AddressSpace *as = arm_boot_address_space(cpu, info);
@@ -1265,7 +1265,9 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
* doesn't support secure.
*/
assert(!(info->secure_board_setup && kvm_enabled()));
-
+ info->kernel_filename = ms->kernel_filename;
+ info->kernel_cmdline = ms->kernel_cmdline;
+ info->initrd_filename = ms->initrd_filename;
info->dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb");
info->dtb_limit = 0;
@@ -1277,7 +1279,7 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
}
if (!info->skip_dtb_autoload && have_dtb(info)) {
- if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as) < 0) {
+ if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) {
exit(1);
}
}
diff --git a/hw/arm/collie.c b/hw/arm/collie.c
index 3db3c56004..72bc8f26e5 100644
--- a/hw/arm/collie.c
+++ b/hw/arm/collie.c
@@ -26,9 +26,6 @@ static struct arm_boot_info collie_binfo = {
static void collie_init(MachineState *machine)
{
- const char *kernel_filename = machine->kernel_filename;
- const char *kernel_cmdline = machine->kernel_cmdline;
- const char *initrd_filename = machine->initrd_filename;
StrongARMState *s;
DriveInfo *dinfo;
MemoryRegion *sysmem = get_system_memory();
@@ -47,11 +44,8 @@ static void collie_init(MachineState *machine)
sysbus_create_simple("scoop", 0x40800000, NULL);
- collie_binfo.kernel_filename = kernel_filename;
- collie_binfo.kernel_cmdline = kernel_cmdline;
- collie_binfo.initrd_filename = initrd_filename;
collie_binfo.board_id = 0x208;
- arm_load_kernel(s->cpu, &collie_binfo);
+ arm_load_kernel(s->cpu, machine, &collie_binfo);
}
static void collie_machine_init(MachineClass *mc)
diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
index f7c8a5985a..d992fa087a 100644
--- a/hw/arm/cubieboard.c
+++ b/hw/arm/cubieboard.c
@@ -72,10 +72,7 @@ static void cubieboard_init(MachineState *machine)
/* TODO create and connect IDE devices for ide_drive_get() */
cubieboard_binfo.ram_size = machine->ram_size;
- cubieboard_binfo.kernel_filename = machine->kernel_filename;
- cubieboard_binfo.kernel_cmdline = machine->kernel_cmdline;
- cubieboard_binfo.initrd_filename = machine->initrd_filename;
- arm_load_kernel(&s->a10->cpu, &cubieboard_binfo);
+ arm_load_kernel(&s->a10->cpu, machine, &cubieboard_binfo);
}
static void cubieboard_machine_init(MachineClass *mc)
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
index ac0b0dc2a9..da402d5216 100644
--- a/hw/arm/exynos4_boards.c
+++ b/hw/arm/exynos4_boards.c
@@ -120,9 +120,6 @@ exynos4_boards_init_common(MachineState *machine,
exynos4_board_binfo.board_id = exynos4_board_id[board_type];
exynos4_board_binfo.smp_bootreg_addr =
exynos4_board_smp_bootreg_addr[board_type];
- exynos4_board_binfo.kernel_filename = machine->kernel_filename;
- exynos4_board_binfo.initrd_filename = machine->initrd_filename;
- exynos4_board_binfo.kernel_cmdline = machine->kernel_cmdline;
exynos4_board_binfo.gic_cpu_if_addr =
EXYNOS4210_SMP_PRIVATE_BASE_ADDR + 0x100;
@@ -141,7 +138,7 @@ static void nuri_init(MachineState *machine)
{
exynos4_boards_init_common(machine, EXYNOS4_BOARD_NURI);
- arm_load_kernel(ARM_CPU(first_cpu), &exynos4_board_binfo);
+ arm_load_kernel(ARM_CPU(first_cpu), machine, &exynos4_board_binfo);
}
static void smdkc210_init(MachineState *machine)
@@ -151,7 +148,7 @@ static void smdkc210_init(MachineState *machine)
lan9215_init(SMDK_LAN9118_BASE_ADDR,
qemu_irq_invert(s->soc.irq_table[exynos4210_get_irq(37, 1)]));
- arm_load_kernel(ARM_CPU(first_cpu), &exynos4_board_binfo);
+ arm_load_kernel(ARM_CPU(first_cpu), machine, &exynos4_board_binfo);
}
static void nuri_class_init(ObjectClass *oc, void *data)
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index def0f1ce6a..1a35b6d82f 100644
--- a/hw/arm/highbank.c
+++ b/hw/arm/highbank.c
@@ -234,9 +234,6 @@ enum cxmachines {
static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
{
ram_addr_t ram_size = machine->ram_size;
- const char *kernel_filename = machine->kernel_filename;
- const char *kernel_cmdline = machine->kernel_cmdline;
- const char *initrd_filename = machine->initrd_filename;
DeviceState *dev = NULL;
SysBusDevice *busdev;
qemu_irq pic[128];
@@ -388,9 +385,6 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
/* TODO create and connect IDE devices for ide_drive_get() */
highbank_binfo.ram_size = ram_size;
- highbank_binfo.kernel_filename = kernel_filename;
- highbank_binfo.kernel_cmdline = kernel_cmdline;
- highbank_binfo.initrd_filename = initrd_filename;
/* highbank requires a dtb in order to boot, and the dtb will override
* the board ID. The following value is ignored, so set it to -1 to be
* clear that the value is meaningless.
@@ -410,7 +404,7 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
"may not boot.");
}
- arm_load_kernel(ARM_CPU(first_cpu), &highbank_binfo);
+ arm_load_kernel(ARM_CPU(first_cpu), machine, &highbank_binfo);
}
static void highbank_init(MachineState *machine)
diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c
index 5d673e47bc..c76fc2bd94 100644
--- a/hw/arm/imx25_pdk.c
+++ b/hw/arm/imx25_pdk.c
@@ -116,9 +116,6 @@ static void imx25_pdk_init(MachineState *machine)
}
imx25_pdk_binfo.ram_size = machine->ram_size;
- imx25_pdk_binfo.kernel_filename = machine->kernel_filename;
- imx25_pdk_binfo.kernel_cmdline = machine->kernel_cmdline;
- imx25_pdk_binfo.initrd_filename = machine->initrd_filename;
imx25_pdk_binfo.loader_start = FSL_IMX25_SDRAM0_ADDR;
imx25_pdk_binfo.board_id = 1771,
imx25_pdk_binfo.nb_cpus = 1;
@@ -129,7 +126,7 @@ static void imx25_pdk_init(MachineState *machine)
* fail.
*/
if (!qtest_enabled()) {
- arm_load_kernel(&s->soc.cpu, &imx25_pdk_binfo);
+ arm_load_kernel(&s->soc.cpu, machine, &imx25_pdk_binfo);
}
}
diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
index 200c0107f0..4d9e9c9e49 100644
--- a/hw/arm/integratorcp.c
+++ b/hw/arm/integratorcp.c
@@ -578,9 +578,6 @@ static struct arm_boot_info integrator_binfo = {
static void integratorcp_init(MachineState *machine)
{
ram_addr_t ram_size = machine->ram_size;
- const char *kernel_filename = machine->kernel_filename;
- const char *kernel_cmdline = machine->kernel_cmdline;
- const char *initrd_filename = machine->initrd_filename;
Object *cpuobj;
ARMCPU *cpu;
MemoryRegion *address_space_mem = get_system_memory();
@@ -650,10 +647,7 @@ static void integratorcp_init(MachineState *machine)
sysbus_create_simple("pl110", 0xc0000000, pic[22]);
integrator_binfo.ram_size = ram_size;
- integrator_binfo.kernel_filename = kernel_filename;
- integrator_binfo.kernel_cmdline = kernel_cmdline;
- integrator_binfo.initrd_filename = initrd_filename;
- arm_load_kernel(cpu, &integrator_binfo);
+ arm_load_kernel(cpu, machine, &integrator_binfo);
}
static void integratorcp_machine_init(MachineClass *mc)
diff --git a/hw/arm/kzm.c b/hw/arm/kzm.c
index 59d2102dc5..5ff419a555 100644
--- a/hw/arm/kzm.c
+++ b/hw/arm/kzm.c
@@ -126,13 +126,10 @@ static void kzm_init(MachineState *machine)
}
kzm_binfo.ram_size = machine->ram_size;
- kzm_binfo.kernel_filename = machine->kernel_filename;
- kzm_binfo.kernel_cmdline = machine->kernel_cmdline;
- kzm_binfo.initrd_filename = machine->initrd_filename;
kzm_binfo.nb_cpus = 1;
if (!qtest_enabled()) {
- arm_load_kernel(&s->soc.cpu, &kzm_binfo);
+ arm_load_kernel(&s->soc.cpu, machine, &kzm_binfo);
}
}
diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c
index cd1f904c6c..c76cfb5dd1 100644
--- a/hw/arm/mainstone.c
+++ b/hw/arm/mainstone.c
@@ -177,11 +177,8 @@ static void mainstone_common_init(MemoryRegion *address_space_mem,
smc91c111_init(&nd_table[0], MST_ETH_PHYS,
qdev_get_gpio_in(mst_irq, ETHERNET_IRQ));
- mainstone_binfo.kernel_filename = machine->kernel_filename;
- mainstone_binfo.kernel_cmdline = machine->kernel_cmdline;
- mainstone_binfo.initrd_filename = machine->initrd_filename;
mainstone_binfo.board_id = arm_id;
- arm_load_kernel(mpu->cpu, &mainstone_binfo);
+ arm_load_kernel(mpu->cpu, machine, &mainstone_binfo);
}
static void mainstone_init(MachineState *machine)
diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c
index bbffb11c2a..ff3e8ade8a 100644
--- a/hw/arm/mcimx6ul-evk.c
+++ b/hw/arm/mcimx6ul-evk.c
@@ -39,9 +39,6 @@ static void mcimx6ul_evk_init(MachineState *machine)
.loader_start = FSL_IMX6UL_MMDC_ADDR,
.board_id = -1,
.ram_size = machine->ram_size,
- .kernel_filename = machine->kernel_filename,
- .kernel_cmdline = machine->kernel_cmdline,
- .initrd_filename = machine->initrd_filename,
.nb_cpus = machine->smp.cpus,
};
@@ -71,7 +68,7 @@ static void mcimx6ul_evk_init(MachineState *machine)
}
if (!qtest_enabled()) {
- arm_load_kernel(&s->soc.cpu[0], &boot_info);
+ arm_load_kernel(&s->soc.cpu[0], machine, &boot_info);
}
}
diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c
index 72eab03a0c..3123d8767f 100644
--- a/hw/arm/mcimx7d-sabre.c
+++ b/hw/arm/mcimx7d-sabre.c
@@ -42,9 +42,6 @@ static void mcimx7d_sabre_init(MachineState *machine)
.loader_start = FSL_IMX7_MMDC_ADDR,
.board_id = -1,
.ram_size = machine->ram_size,
- .kernel_filename = machine->kernel_filename,
- .kernel_cmdline = machine->kernel_cmdline,
- .initrd_filename = machine->initrd_filename,
.nb_cpus = machine->smp.cpus,
};
@@ -74,7 +71,7 @@ static void mcimx7d_sabre_init(MachineState *machine)
}
if (!qtest_enabled()) {
- arm_load_kernel(&s->soc.cpu[0], &boot_info);
+ arm_load_kernel(&s->soc.cpu[0], machine, &boot_info);
}
}
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
index 95d56f3208..a53ee12737 100644
--- a/hw/arm/musicpal.c
+++ b/hw/arm/musicpal.c
@@ -1568,9 +1568,6 @@ static struct arm_boot_info musicpal_binfo = {
static void musicpal_init(MachineState *machine)
{
- const char *kernel_filename = machine->kernel_filename;
- const char *kernel_cmdline = machine->kernel_cmdline;
- const char *initrd_filename = machine->initrd_filename;
ARMCPU *cpu;
qemu_irq pic[32];
DeviceState *dev;
@@ -1699,10 +1696,7 @@ static void musicpal_init(MachineState *machine)
sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]);
musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE;
- musicpal_binfo.kernel_filename = kernel_filename;
- musicpal_binfo.kernel_cmdline = kernel_cmdline;
- musicpal_binfo.initrd_filename = initrd_filename;
- arm_load_kernel(cpu, &musicpal_binfo);
+ arm_load_kernel(cpu, machine, &musicpal_binfo);
}
static void musicpal_machine_init(MachineClass *mc)
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
index 4a79f5c88b..31dd2f1b51 100644
--- a/hw/arm/nseries.c
+++ b/hw/arm/nseries.c
@@ -1358,10 +1358,7 @@ static void n8x0_init(MachineState *machine,
if (machine->kernel_filename) {
/* Or at the linux loader. */
- binfo->kernel_filename = machine->kernel_filename;
- binfo->kernel_cmdline = machine->kernel_cmdline;
- binfo->initrd_filename = machine->initrd_filename;
- arm_load_kernel(s->mpu->cpu, binfo);
+ arm_load_kernel(s->mpu->cpu, machine, binfo);
qemu_register_reset(n8x0_boot_init, s);
}
diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
index cae78d0a36..3cc2817f06 100644
--- a/hw/arm/omap_sx1.c
+++ b/hw/arm/omap_sx1.c
@@ -196,10 +196,7 @@ static void sx1_init(MachineState *machine, const int version)
}
/* Load the kernel. */
- sx1_binfo.kernel_filename = machine->kernel_filename;
- sx1_binfo.kernel_cmdline = machine->kernel_cmdline;
- sx1_binfo.initrd_filename = machine->initrd_filename;
- arm_load_kernel(mpu->cpu, &sx1_binfo);
+ arm_load_kernel(mpu->cpu, machine, &sx1_binfo);
/* TODO: fix next line */
//~ qemu_console_resize(ds, 640, 480);
diff --git a/hw/arm/palm.c b/hw/arm/palm.c
index 9eb9612bce..67ab30b5bc 100644
--- a/hw/arm/palm.c
+++ b/hw/arm/palm.c
@@ -186,9 +186,6 @@ static struct arm_boot_info palmte_binfo = {
static void palmte_init(MachineState *machine)
{
- const char *kernel_filename = machine->kernel_filename;
- const char *kernel_cmdline = machine->kernel_cmdline;
- const char *initrd_filename = machine->initrd_filename;
MemoryRegion *address_space_mem = get_system_memory();
struct omap_mpu_state_s *mpu;
int flash_size = 0x00800000;
@@ -248,16 +245,13 @@ static void palmte_init(MachineState *machine)
}
}
- if (!rom_loaded && !kernel_filename && !qtest_enabled()) {
+ if (!rom_loaded && !machine->kernel_filename && !qtest_enabled()) {
fprintf(stderr, "Kernel or ROM image must be specified\n");
exit(1);
}
/* Load the kernel. */
- palmte_binfo.kernel_filename = kernel_filename;
- palmte_binfo.kernel_cmdline = kernel_cmdline;
- palmte_binfo.initrd_filename = initrd_filename;
- arm_load_kernel(mpu->cpu, &palmte_binfo);
+ arm_load_kernel(mpu->cpu, machine, &palmte_binfo);
}
static void palmte_machine_init(MachineClass *mc)
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index 5b2620acb4..74c062d05e 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -157,13 +157,9 @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
binfo.entry = firmware_addr;
binfo.firmware_loaded = true;
- } else {
- binfo.kernel_filename = machine->kernel_filename;
- binfo.kernel_cmdline = machine->kernel_cmdline;
- binfo.initrd_filename = machine->initrd_filename;
}
- arm_load_kernel(ARM_CPU(first_cpu), &binfo);
+ arm_load_kernel(ARM_CPU(first_cpu), machine, &binfo);
}
static void raspi_init(MachineState *machine, int version)
diff --git a/hw/arm/realview.c b/hw/arm/realview.c
index 7c56c8d2ed..5a3e65ddd6 100644
--- a/hw/arm/realview.c
+++ b/hw/arm/realview.c
@@ -350,13 +350,10 @@ static void realview_init(MachineState *machine,
memory_region_add_subregion(sysmem, SMP_BOOT_ADDR, ram_hack);
realview_binfo.ram_size = ram_size;
- realview_binfo.kernel_filename = machine->kernel_filename;
- realview_binfo.kernel_cmdline = machine->kernel_cmdline;
- realview_binfo.initrd_filename = machine->initrd_filename;
realview_binfo.nb_cpus = smp_cpus;
realview_binfo.board_id = realview_board_id[board_type];
realview_binfo.loader_start = (board_type == BOARD_PB_A8 ? 0x70000000 : 0);
- arm_load_kernel(ARM_CPU(first_cpu), &realview_binfo);
+ arm_load_kernel(ARM_CPU(first_cpu), machine, &realview_binfo);
}
static void realview_eb_init(MachineState *machine)
diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c
index 934f4c9261..8f4b68e14c 100644
--- a/hw/arm/sabrelite.c
+++ b/hw/arm/sabrelite.c
@@ -102,16 +102,13 @@ static void sabrelite_init(MachineState *machine)
}
sabrelite_binfo.ram_size = machine->ram_size;
- sabrelite_binfo.kernel_filename = machine->kernel_filename;
- sabrelite_binfo.kernel_cmdline = machine->kernel_cmdline;
- sabrelite_binfo.initrd_filename = machine->initrd_filename;
sabrelite_binfo.nb_cpus = machine->smp.cpus;
sabrelite_binfo.secure_boot = true;
sabrelite_binfo.write_secondary_boot = sabrelite_write_secondary;
sabrelite_binfo.secondary_cpu_reset_hook = sabrelite_reset_secondary;
if (!qtest_enabled()) {
- arm_load_kernel(&s->soc.cpu[0], &sabrelite_binfo);
+ arm_load_kernel(&s->soc.cpu[0], machine, &sabrelite_binfo);
}
}
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index 9c67d5c6f9..2aba3c58c5 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -709,13 +709,12 @@ static void sbsa_ref_init(MachineState *machine)
create_pcie(sms, pic);
sms->bootinfo.ram_size = machine->ram_size;
- sms->bootinfo.kernel_filename = machine->kernel_filename;
sms->bootinfo.nb_cpus = smp_cpus;
sms->bootinfo.board_id = -1;
sms->bootinfo.loader_start = sbsa_ref_memmap[SBSA_MEM].base;
sms->bootinfo.get_dtb = sbsa_ref_dtb;
sms->bootinfo.firmware_loaded = firmware_loaded;
- arm_load_kernel(ARM_CPU(first_cpu), &sms->bootinfo);
+ arm_load_kernel(ARM_CPU(first_cpu), machine, &sms->bootinfo);
}
static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx)
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
index 723cf5d592..42338696b3 100644
--- a/hw/arm/spitz.c
+++ b/hw/arm/spitz.c
@@ -951,11 +951,8 @@ static void spitz_common_init(MachineState *machine,
/* A 4.0 GB microdrive is permanently sitting in CF slot 0. */
spitz_microdrive_attach(mpu, 0);
- spitz_binfo.kernel_filename = machine->kernel_filename;
- spitz_binfo.kernel_cmdline = machine->kernel_cmdline;
- spitz_binfo.initrd_filename = machine->initrd_filename;
spitz_binfo.board_id = arm_id;
- arm_load_kernel(mpu->cpu, &spitz_binfo);
+ arm_load_kernel(mpu->cpu, machine, &spitz_binfo);
sl_bootparam_write(SL_PXA_PARAM_BASE);
}
diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c
index 7843d68d46..3a1de81278 100644
--- a/hw/arm/tosa.c
+++ b/hw/arm/tosa.c
@@ -218,9 +218,6 @@ static struct arm_boot_info tosa_binfo = {
static void tosa_init(MachineState *machine)
{
- const char *kernel_filename = machine->kernel_filename;
- const char *kernel_cmdline = machine->kernel_cmdline;
- const char *initrd_filename = machine->initrd_filename;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *rom = g_new(MemoryRegion, 1);
PXA2xxState *mpu;
@@ -245,11 +242,8 @@ static void tosa_init(MachineState *machine)
tosa_tg_init(mpu);
- tosa_binfo.kernel_filename = kernel_filename;
- tosa_binfo.kernel_cmdline = kernel_cmdline;
- tosa_binfo.initrd_filename = initrd_filename;
tosa_binfo.board_id = 0x208;
- arm_load_kernel(mpu->cpu, &tosa_binfo);
+ arm_load_kernel(mpu->cpu, machine, &tosa_binfo);
sl_bootparam_write(SL_PXA_PARAM_BASE);
}
diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
index e5857117ac..d3c3c00f55 100644
--- a/hw/arm/versatilepb.c
+++ b/hw/arm/versatilepb.c
@@ -373,11 +373,8 @@ static void versatile_init(MachineState *machine, int board_id)
}
versatile_binfo.ram_size = machine->ram_size;
- versatile_binfo.kernel_filename = machine->kernel_filename;
- versatile_binfo.kernel_cmdline = machine->kernel_cmdline;
- versatile_binfo.initrd_filename = machine->initrd_filename;
versatile_binfo.board_id = board_id;
- arm_load_kernel(cpu, &versatile_binfo);
+ arm_load_kernel(cpu, machine, &versatile_binfo);
}
static void vpb_init(MachineState *machine)
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index 5d932c27c0..4673a88a8d 100644
--- a/hw/arm/vexpress.c
+++ b/hw/arm/vexpress.c
@@ -707,9 +707,6 @@ static void vexpress_common_init(MachineState *machine)
}
daughterboard->bootinfo.ram_size = machine->ram_size;
- daughterboard->bootinfo.kernel_filename = machine->kernel_filename;
- daughterboard->bootinfo.kernel_cmdline = machine->kernel_cmdline;
- daughterboard->bootinfo.initrd_filename = machine->initrd_filename;
daughterboard->bootinfo.nb_cpus = machine->smp.cpus;
daughterboard->bootinfo.board_id = VEXPRESS_BOARD_ID;
daughterboard->bootinfo.loader_start = daughterboard->loader_start;
@@ -719,7 +716,7 @@ static void vexpress_common_init(MachineState *machine)
daughterboard->bootinfo.modify_dtb = vexpress_modify_dtb;
/* When booting Linux we should be in secure state if the CPU has one. */
daughterboard->bootinfo.secure_boot = vms->secure;
- arm_load_kernel(ARM_CPU(first_cpu), &daughterboard->bootinfo);
+ arm_load_kernel(ARM_CPU(first_cpu), machine, &daughterboard->bootinfo);
}
static bool vexpress_get_secure(Object *obj, Error **errp)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 0b5138cb22..9b380504b6 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -1364,6 +1364,7 @@ void virt_machine_done(Notifier *notifier, void *data)
{
VirtMachineState *vms = container_of(notifier, VirtMachineState,
machine_done);
+ MachineState *ms = MACHINE(vms);
ARMCPU *cpu = ARM_CPU(first_cpu);
struct arm_boot_info *info = &vms->bootinfo;
AddressSpace *as = arm_boot_address_space(cpu, info);
@@ -1381,7 +1382,7 @@ void virt_machine_done(Notifier *notifier, void *data)
vms->memmap[VIRT_PLATFORM_BUS].size,
vms->irqmap[VIRT_PLATFORM_BUS]);
}
- if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as) < 0) {
+ if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) {
exit(1);
}
@@ -1707,16 +1708,13 @@ static void machvirt_init(MachineState *machine)
create_platform_bus(vms, pic);
vms->bootinfo.ram_size = machine->ram_size;
- vms->bootinfo.kernel_filename = machine->kernel_filename;
- vms->bootinfo.kernel_cmdline = machine->kernel_cmdline;
- vms->bootinfo.initrd_filename = machine->initrd_filename;
vms->bootinfo.nb_cpus = smp_cpus;
vms->bootinfo.board_id = -1;
vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base;
vms->bootinfo.get_dtb = machvirt_dtb;
vms->bootinfo.skip_dtb_autoload = true;
vms->bootinfo.firmware_loaded = firmware_loaded;
- arm_load_kernel(ARM_CPU(first_cpu), &vms->bootinfo);
+ arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo);
vms->machine_done.notify = virt_machine_done;
qemu_add_machine_init_done_notifier(&vms->machine_done);
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index 89da34808b..c14774e542 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -158,9 +158,6 @@ static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,
static void zynq_init(MachineState *machine)
{
ram_addr_t ram_size = machine->ram_size;
- const char *kernel_filename = machine->kernel_filename;
- const char *kernel_cmdline = machine->kernel_cmdline;
- const char *initrd_filename = machine->initrd_filename;
ARMCPU *cpu;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
@@ -303,16 +300,13 @@ static void zynq_init(MachineState *machine)
sysbus_mmio_map(busdev, 0, 0xF8007000);
zynq_binfo.ram_size = ram_size;
- zynq_binfo.kernel_filename = kernel_filename;
- zynq_binfo.kernel_cmdline = kernel_cmdline;
- zynq_binfo.initrd_filename = initrd_filename;
zynq_binfo.nb_cpus = 1;
zynq_binfo.board_id = 0xd32;
zynq_binfo.loader_start = 0;
zynq_binfo.board_setup_addr = BOARD_SETUP_ADDR;
zynq_binfo.write_board_setup = zynq_write_board_setup;
- arm_load_kernel(ARM_CPU(first_cpu), &zynq_binfo);
+ arm_load_kernel(ARM_CPU(first_cpu), machine, &zynq_binfo);
}
static void zynq_machine_init(MachineClass *mc)
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index f95fde2309..462493c467 100644
--- a/hw/arm/xlnx-versal-virt.c
+++ b/hw/arm/xlnx-versal-virt.c
@@ -441,14 +441,11 @@ static void versal_virt_init(MachineState *machine)
0, &s->soc.fpd.apu.mr, 0);
s->binfo.ram_size = machine->ram_size;
- s->binfo.kernel_filename = machine->kernel_filename;
- s->binfo.kernel_cmdline = machine->kernel_cmdline;
- s->binfo.initrd_filename = machine->initrd_filename;
s->binfo.loader_start = 0x0;
s->binfo.get_dtb = versal_virt_get_dtb;
s->binfo.modify_dtb = versal_virt_modify_dtb;
if (machine->kernel_filename) {
- arm_load_kernel(s->soc.fpd.apu.cpu[0], &s->binfo);
+ arm_load_kernel(s->soc.fpd.apu.cpu[0], machine, &s->binfo);
} else {
AddressSpace *as = arm_boot_address_space(s->soc.fpd.apu.cpu[0],
&s->binfo);
@@ -457,7 +454,7 @@ static void versal_virt_init(MachineState *machine)
s->binfo.loader_start = 0x1000;
s->binfo.dtb_limit = 0x1000000;
if (arm_load_dtb(s->binfo.loader_start,
- &s->binfo, s->binfo.dtb_limit, as) < 0) {
+ &s->binfo, s->binfo.dtb_limit, as, machine) < 0) {
exit(EXIT_FAILURE);
}
}
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
index 044d3394c0..53cfe7c1f1 100644
--- a/hw/arm/xlnx-zcu102.c
+++ b/hw/arm/xlnx-zcu102.c
@@ -171,11 +171,8 @@ static void xlnx_zcu102_init(MachineState *machine)
/* TODO create and connect IDE devices for ide_drive_get() */
xlnx_zcu102_binfo.ram_size = ram_size;
- xlnx_zcu102_binfo.kernel_filename = machine->kernel_filename;
- xlnx_zcu102_binfo.kernel_cmdline = machine->kernel_cmdline;
- xlnx_zcu102_binfo.initrd_filename = machine->initrd_filename;
xlnx_zcu102_binfo.loader_start = 0;
- arm_load_kernel(s->soc.boot_cpu_ptr, &xlnx_zcu102_binfo);
+ arm_load_kernel(s->soc.boot_cpu_ptr, machine, &xlnx_zcu102_binfo);
}
static void xlnx_zcu102_machine_instance_init(Object *obj)
diff --git a/hw/arm/z2.c b/hw/arm/z2.c
index 44aa748d39..2f21421683 100644
--- a/hw/arm/z2.c
+++ b/hw/arm/z2.c
@@ -296,9 +296,6 @@ static const TypeInfo aer915_info = {
static void z2_init(MachineState *machine)
{
- const char *kernel_filename = machine->kernel_filename;
- const char *kernel_cmdline = machine->kernel_cmdline;
- const char *initrd_filename = machine->initrd_filename;
MemoryRegion *address_space_mem = get_system_memory();
uint32_t sector_len = 0x10000;
PXA2xxState *mpu;
@@ -352,11 +349,8 @@ static void z2_init(MachineState *machine)
qdev_connect_gpio_out(mpu->gpio, Z2_GPIO_LCD_CS,
qemu_allocate_irq(z2_lcd_cs, z2_lcd, 0));
- z2_binfo.kernel_filename = kernel_filename;
- z2_binfo.kernel_cmdline = kernel_cmdline;
- z2_binfo.initrd_filename = initrd_filename;
z2_binfo.board_id = 0x6dd;
- arm_load_kernel(mpu->cpu, &z2_binfo);
+ arm_load_kernel(mpu->cpu, machine, &z2_binfo);
}
static void z2_machine_init(MachineClass *mc)
diff --git a/include/hw/arm/boot.h b/include/hw/arm/boot.h
index c48cc4c2bc..2673abe81f 100644
--- a/include/hw/arm/boot.h
+++ b/include/hw/arm/boot.h
@@ -133,7 +133,7 @@ struct arm_boot_info {
* before sysbus-fdt arm_register_platform_bus_fdt_creator. Indeed the
* machine init done notifiers are called in registration reverse order.
*/
-void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info);
+void arm_load_kernel(ARMCPU *cpu, MachineState *ms, struct arm_boot_info *info);
AddressSpace *arm_boot_address_space(ARMCPU *cpu,
const struct arm_boot_info *info);
@@ -160,7 +160,7 @@ AddressSpace *arm_boot_address_space(ARMCPU *cpu,
* Note: Must not be called unless have_dtb(binfo) is true.
*/
int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo,
- hwaddr addr_limit, AddressSpace *as);
+ hwaddr addr_limit, AddressSpace *as, MachineState *ms);
/* Write a secure board setup routine with a dummy handler for SMCs */
void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
--
2.20.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH RESEND v6 02/14] numa: move numa global variable nb_numa_nodes into MachineState
2019-07-09 7:15 [Qemu-devel] [PATCH RESEND v6 00/14] Build ACPI Heterogeneous Memory Attribute Table (HMAT) Tao Xu
2019-07-09 7:15 ` [Qemu-devel] [PATCH RESEND v6 01/14] hw/arm: simplify arm_load_dtb Tao Xu
@ 2019-07-09 7:15 ` Tao Xu
2019-07-09 7:15 ` [Qemu-devel] [PATCH RESEND v6 03/14] numa: move numa global variable have_numa_distance " Tao Xu
` (13 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Tao Xu @ 2019-07-09 7:15 UTC (permalink / raw)
To: imammedo, eblake, ehabkost
Cc: jingqi.liu, tao3.xu, fan.du, qemu-devel, jonathan.cameron,
dan.j.williams
Add struct NumaState in MachineState and move existing numa global
nb_numa_nodes(renamed as "num_nodes") into NumaState. And add variable
numa_support into MachineClass to decide which submachines support NUMA.
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Suggested-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Tao Xu <tao3.xu@intel.com>
---
Changes in v6:
- Rebase to upstream, move globals in arm/sbsa-ref and use
numa_mem_supported
- When used once or twice in the function, use
ms->numa_state->num_nodes directly
- Correct some mistakes
- Use once monitor_printf in hmp_info_numa
---
exec.c | 5 ++-
hw/acpi/aml-build.c | 3 +-
hw/arm/boot.c | 4 +-
hw/arm/sbsa-ref.c | 4 +-
hw/arm/virt-acpi-build.c | 10 +++--
hw/arm/virt.c | 4 +-
hw/core/machine-hmp-cmds.c | 12 ++++--
hw/core/machine.c | 14 +++++--
hw/core/numa.c | 60 +++++++++++++++++------------
hw/i386/acpi-build.c | 2 +-
hw/i386/pc.c | 9 +++--
hw/mem/pc-dimm.c | 2 +
hw/pci-bridge/pci_expander_bridge.c | 3 +-
hw/ppc/spapr.c | 23 +++++------
include/hw/acpi/aml-build.h | 2 +-
include/hw/boards.h | 1 +
include/sysemu/numa.h | 10 ++++-
17 files changed, 107 insertions(+), 61 deletions(-)
diff --git a/exec.c b/exec.c
index 50ea9c5aaa..b6b75d2ad5 100644
--- a/exec.c
+++ b/exec.c
@@ -1736,6 +1736,7 @@ long qemu_minrampagesize(void)
long hpsize = LONG_MAX;
long mainrampagesize;
Object *memdev_root;
+ MachineState *ms = MACHINE(qdev_get_machine());
mainrampagesize = qemu_mempath_getpagesize(mem_path);
@@ -1763,7 +1764,9 @@ long qemu_minrampagesize(void)
* so if its page size is smaller we have got to report that size instead.
*/
if (hpsize > mainrampagesize &&
- (nb_numa_nodes == 0 || numa_info[0].node_memdev == NULL)) {
+ (ms->numa_state == NULL ||
+ ms->numa_state->num_nodes == 0 ||
+ numa_info[0].node_memdev == NULL)) {
static bool warned;
if (!warned) {
error_report("Huge page support disabled (n/a for main memory).");
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index 555c24f21d..63c1cae8c9 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -1726,10 +1726,11 @@ void build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base,
* ACPI spec 5.2.17 System Locality Distance Information Table
* (Revision 2.0 or later)
*/
-void build_slit(GArray *table_data, BIOSLinker *linker)
+void build_slit(GArray *table_data, BIOSLinker *linker, MachineState *ms)
{
int slit_start, i, j;
slit_start = table_data->len;
+ int nb_numa_nodes = ms->numa_state->num_nodes;
acpi_data_push(table_data, sizeof(AcpiTableHeader));
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index a90151f465..e28daa5278 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -598,9 +598,9 @@ int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo,
}
g_strfreev(node_path);
- if (nb_numa_nodes > 0) {
+ if (ms->numa_state != NULL && ms->numa_state->num_nodes > 0) {
mem_base = binfo->loader_start;
- for (i = 0; i < nb_numa_nodes; i++) {
+ for (i = 0; i < ms->numa_state->num_nodes; i++) {
mem_len = numa_info[i].node_mem;
rc = fdt_add_memory_node(fdt, acells, mem_base,
scells, mem_len, i);
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index 2aba3c58c5..22847909bf 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -144,6 +144,7 @@ static void create_fdt(SBSAMachineState *sms)
{
void *fdt = create_device_tree(&sms->fdt_size);
const MachineState *ms = MACHINE(sms);
+ int nb_numa_nodes = ms->numa_state->num_nodes;
int cpu;
if (!fdt) {
@@ -760,7 +761,7 @@ sbsa_ref_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
static int64_t
sbsa_ref_get_default_cpu_node_id(const MachineState *ms, int idx)
{
- return idx % nb_numa_nodes;
+ return idx % ms->numa_state->num_nodes;
}
static void sbsa_ref_instance_init(Object *obj)
@@ -787,6 +788,7 @@ static void sbsa_ref_class_init(ObjectClass *oc, void *data)
mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids;
mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props;
mc->get_default_cpu_node_id = sbsa_ref_get_default_cpu_node_id;
+ mc->numa_mem_supported = true;
}
static const TypeInfo sbsa_ref_info = {
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 0afb372769..a2cc4b84fe 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -516,7 +516,8 @@ build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
int i, srat_start;
uint64_t mem_base;
MachineClass *mc = MACHINE_GET_CLASS(vms);
- const CPUArchIdList *cpu_list = mc->possible_cpu_arch_ids(MACHINE(vms));
+ MachineState *ms = MACHINE(vms);
+ const CPUArchIdList *cpu_list = mc->possible_cpu_arch_ids(ms);
srat_start = table_data->len;
srat = acpi_data_push(table_data, sizeof(*srat));
@@ -532,7 +533,7 @@ build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
}
mem_base = vms->memmap[VIRT_MEM].base;
- for (i = 0; i < nb_numa_nodes; ++i) {
+ for (i = 0; i < ms->numa_state->num_nodes; ++i) {
if (numa_info[i].node_mem > 0) {
numamem = acpi_data_push(table_data, sizeof(*numamem));
build_srat_memory(numamem, mem_base, numa_info[i].node_mem, i,
@@ -758,6 +759,7 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
GArray *table_offsets;
unsigned dsdt, xsdt;
GArray *tables_blob = tables->table_data;
+ MachineState *ms = MACHINE(vms);
table_offsets = g_array_new(false, true /* clear */,
sizeof(uint32_t));
@@ -792,12 +794,12 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
acpi_add_table(table_offsets, tables_blob);
build_spcr(tables_blob, tables->linker, vms);
- if (nb_numa_nodes > 0) {
+ if (ms->numa_state->num_nodes > 0) {
acpi_add_table(table_offsets, tables_blob);
build_srat(tables_blob, tables->linker, vms);
if (have_numa_distance) {
acpi_add_table(table_offsets, tables_blob);
- build_slit(tables_blob, tables->linker);
+ build_slit(tables_blob, tables->linker, ms);
}
}
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 9b380504b6..01a32272b4 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -199,6 +199,8 @@ static bool cpu_type_valid(const char *cpu)
static void create_fdt(VirtMachineState *vms)
{
+ MachineState *ms = MACHINE(vms);
+ int nb_numa_nodes = ms->numa_state->num_nodes;
void *fdt = create_device_tree(&vms->fdt_size);
if (!fdt) {
@@ -1842,7 +1844,7 @@ virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
{
- return idx % nb_numa_nodes;
+ return idx % ms->numa_state->num_nodes;
}
static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
diff --git a/hw/core/machine-hmp-cmds.c b/hw/core/machine-hmp-cmds.c
index 1f66bda346..6a1a2599d8 100644
--- a/hw/core/machine-hmp-cmds.c
+++ b/hw/core/machine-hmp-cmds.c
@@ -139,15 +139,21 @@ void hmp_info_memdev(Monitor *mon, const QDict *qdict)
void hmp_info_numa(Monitor *mon, const QDict *qdict)
{
- int i;
+ int i, nb_numa_nodes;
NumaNodeMem *node_mem;
CpuInfoList *cpu_list, *cpu;
+ MachineState *ms = MACHINE(qdev_get_machine());
+
+ nb_numa_nodes = ms->numa_state ? ms->numa_state->num_nodes : 0;
+ monitor_printf(mon, "%d nodes\n", nb_numa_nodes);
+ if (!nb_numa_nodes) {
+ return;
+ }
cpu_list = qmp_query_cpus(&error_abort);
node_mem = g_new0(NumaNodeMem, nb_numa_nodes);
- query_numa_node_mem(node_mem);
- monitor_printf(mon, "%d nodes\n", nb_numa_nodes);
+ query_numa_node_mem(node_mem, ms);
for (i = 0; i < nb_numa_nodes; i++) {
monitor_printf(mon, "node %d cpus:", i);
for (cpu = cpu_list; cpu; cpu = cpu->next) {
diff --git a/hw/core/machine.c b/hw/core/machine.c
index 2be19ec0cd..4228bcd2a2 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -966,6 +966,9 @@ static void machine_initfn(Object *obj)
NULL);
}
+ if (mc->numa_mem_supported) {
+ ms->numa_state = g_new0(NumaState, 1);
+ }
/* Register notifier when init is done for sysbus sanity checks */
ms->sysbus_notifier.notify = machine_init_notify;
@@ -986,6 +989,7 @@ static void machine_finalize(Object *obj)
g_free(ms->firmware);
g_free(ms->device_memory);
g_free(ms->nvdimms_state);
+ g_free(ms->numa_state);
}
bool machine_usb(MachineState *machine)
@@ -1060,7 +1064,7 @@ static void machine_numa_finish_cpu_init(MachineState *machine)
MachineClass *mc = MACHINE_GET_CLASS(machine);
const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(machine);
- assert(nb_numa_nodes);
+ assert(machine->numa_state->num_nodes);
for (i = 0; i < possible_cpus->len; i++) {
if (possible_cpus->cpus[i].props.has_node_id) {
break;
@@ -1106,9 +1110,11 @@ void machine_run_board_init(MachineState *machine)
{
MachineClass *machine_class = MACHINE_GET_CLASS(machine);
- numa_complete_configuration(machine);
- if (nb_numa_nodes) {
- machine_numa_finish_cpu_init(machine);
+ if (machine_class->numa_mem_supported) {
+ numa_complete_configuration(machine);
+ if (machine->numa_state->num_nodes) {
+ machine_numa_finish_cpu_init(machine);
+ }
}
/* If the machine supports the valid_cpu_types check and the user
diff --git a/hw/core/numa.c b/hw/core/numa.c
index a11431483c..4d5e308bf1 100644
--- a/hw/core/numa.c
+++ b/hw/core/numa.c
@@ -50,7 +50,6 @@ static int have_mem;
static int max_numa_nodeid; /* Highest specified NUMA node ID, plus one.
* For all nodes, nodeid < max_numa_nodeid
*/
-int nb_numa_nodes;
bool have_numa_distance;
NodeInfo numa_info[MAX_NODES];
@@ -67,7 +66,7 @@ static void parse_numa_node(MachineState *ms, NumaNodeOptions *node,
if (node->has_nodeid) {
nodenr = node->nodeid;
} else {
- nodenr = nb_numa_nodes;
+ nodenr = ms->numa_state->num_nodes;
}
if (nodenr >= MAX_NODES) {
@@ -133,10 +132,11 @@ static void parse_numa_node(MachineState *ms, NumaNodeOptions *node,
}
numa_info[nodenr].present = true;
max_numa_nodeid = MAX(max_numa_nodeid, nodenr + 1);
- nb_numa_nodes++;
+ ms->numa_state->num_nodes++;
}
-static void parse_numa_distance(NumaDistOptions *dist, Error **errp)
+static
+void parse_numa_distance(MachineState *ms, NumaDistOptions *dist, Error **errp)
{
uint16_t src = dist->src;
uint16_t dst = dist->dst;
@@ -174,6 +174,12 @@ static void parse_numa_distance(NumaDistOptions *dist, Error **errp)
void set_numa_options(MachineState *ms, NumaOptions *object, Error **errp)
{
Error *err = NULL;
+ MachineClass *mc = MACHINE_GET_CLASS(ms);
+
+ if (!mc->numa_mem_supported) {
+ error_setg(errp, "NUMA is not supported by this machine-type");
+ goto end;
+ }
switch (object->type) {
case NUMA_OPTIONS_TYPE_NODE:
@@ -183,7 +189,7 @@ void set_numa_options(MachineState *ms, NumaOptions *object, Error **errp)
}
break;
case NUMA_OPTIONS_TYPE_DIST:
- parse_numa_distance(&object->u.dist, &err);
+ parse_numa_distance(ms, &object->u.dist, &err);
if (err) {
goto end;
}
@@ -248,10 +254,11 @@ end:
* distance from a node to itself is always NUMA_DISTANCE_MIN,
* so providing it is never necessary.
*/
-static void validate_numa_distance(void)
+static void validate_numa_distance(MachineState *ms)
{
int src, dst;
bool is_asymmetrical = false;
+ int nb_numa_nodes = ms->numa_state->num_nodes;
for (src = 0; src < nb_numa_nodes; src++) {
for (dst = src; dst < nb_numa_nodes; dst++) {
@@ -289,7 +296,7 @@ static void validate_numa_distance(void)
}
}
-static void complete_init_numa_distance(void)
+static void complete_init_numa_distance(MachineState *ms)
{
int src, dst;
@@ -298,8 +305,8 @@ static void complete_init_numa_distance(void)
* there would not be any missing distance except local node, which
* is verified by validate_numa_distance above.
*/
- for (src = 0; src < nb_numa_nodes; src++) {
- for (dst = 0; dst < nb_numa_nodes; dst++) {
+ for (src = 0; src < ms->numa_state->num_nodes; src++) {
+ for (dst = 0; dst < ms->numa_state->num_nodes; dst++) {
if (numa_info[src].distance[dst] == 0) {
if (src == dst) {
numa_info[src].distance[dst] = NUMA_DISTANCE_MIN;
@@ -365,7 +372,7 @@ void numa_complete_configuration(MachineState *ms)
*
* Enable NUMA implicitly by adding a new NUMA node automatically.
*/
- if (ms->ram_slots > 0 && nb_numa_nodes == 0 &&
+ if (ms->ram_slots > 0 && ms->numa_state->num_nodes == 0 &&
mc->auto_enable_numa_with_memhp) {
NumaNodeOptions node = { };
parse_numa_node(ms, &node, &error_abort);
@@ -383,26 +390,27 @@ void numa_complete_configuration(MachineState *ms)
}
/* This must be always true if all nodes are present: */
- assert(nb_numa_nodes == max_numa_nodeid);
+ assert(ms->numa_state->num_nodes == max_numa_nodeid);
- if (nb_numa_nodes > 0) {
+ if (ms->numa_state->num_nodes > 0) {
uint64_t numa_total;
- if (nb_numa_nodes > MAX_NODES) {
- nb_numa_nodes = MAX_NODES;
+ if (ms->numa_state->num_nodes > MAX_NODES) {
+ ms->numa_state->num_nodes = MAX_NODES;
}
/* If no memory size is given for any node, assume the default case
* and distribute the available memory equally across all nodes
*/
- for (i = 0; i < nb_numa_nodes; i++) {
+ for (i = 0; i < ms->numa_state->num_nodes; i++) {
if (numa_info[i].node_mem != 0) {
break;
}
}
- if (i == nb_numa_nodes) {
+ if (i == ms->numa_state->num_nodes) {
assert(mc->numa_auto_assign_ram);
- mc->numa_auto_assign_ram(mc, numa_info, nb_numa_nodes, ram_size);
+ mc->numa_auto_assign_ram(mc, numa_info,
+ ms->numa_state->num_nodes, ram_size);
if (!qtest_enabled()) {
warn_report("Default splitting of RAM between nodes is deprecated,"
" Use '-numa node,memdev' to explictly define RAM"
@@ -411,7 +419,7 @@ void numa_complete_configuration(MachineState *ms)
}
numa_total = 0;
- for (i = 0; i < nb_numa_nodes; i++) {
+ for (i = 0; i < ms->numa_state->num_nodes; i++) {
numa_total += numa_info[i].node_mem;
}
if (numa_total != ram_size) {
@@ -435,10 +443,10 @@ void numa_complete_configuration(MachineState *ms)
*/
if (have_numa_distance) {
/* Validate enough NUMA distance information was provided. */
- validate_numa_distance();
+ validate_numa_distance(ms);
/* Validation succeeded, now fill in any missing distances. */
- complete_init_numa_distance();
+ complete_init_numa_distance(ms);
}
}
}
@@ -505,14 +513,16 @@ void memory_region_allocate_system_memory(MemoryRegion *mr, Object *owner,
{
uint64_t addr = 0;
int i;
+ MachineState *ms = MACHINE(qdev_get_machine());
- if (nb_numa_nodes == 0 || !have_memdevs) {
+ if (ms->numa_state == NULL ||
+ ms->numa_state->num_nodes == 0 || !have_memdevs) {
allocate_system_memory_nonnuma(mr, owner, name, ram_size);
return;
}
memory_region_init(mr, owner, name, ram_size);
- for (i = 0; i < nb_numa_nodes; i++) {
+ for (i = 0; i < ms->numa_state->num_nodes; i++) {
uint64_t size = numa_info[i].node_mem;
HostMemoryBackend *backend = numa_info[i].node_memdev;
if (!backend) {
@@ -570,16 +580,16 @@ static void numa_stat_memory_devices(NumaNodeMem node_mem[])
qapi_free_MemoryDeviceInfoList(info_list);
}
-void query_numa_node_mem(NumaNodeMem node_mem[])
+void query_numa_node_mem(NumaNodeMem node_mem[], MachineState *ms)
{
int i;
- if (nb_numa_nodes <= 0) {
+ if (ms->numa_state == NULL || ms->numa_state->num_nodes <= 0) {
return;
}
numa_stat_memory_devices(node_mem);
- for (i = 0; i < nb_numa_nodes; i++) {
+ for (i = 0; i < ms->numa_state->num_nodes; i++) {
node_mem[i].node_mem += numa_info[i].node_mem;
}
}
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index d281ffa89e..83a8551af6 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -2685,7 +2685,7 @@ void acpi_build(AcpiBuildTables *tables, MachineState *machine)
build_srat(tables_blob, tables->linker, machine);
if (have_numa_distance) {
acpi_add_table(table_offsets, tables_blob);
- build_slit(tables_blob, tables->linker);
+ build_slit(tables_blob, tables->linker, machine);
}
}
if (acpi_get_mcfg(&mcfg)) {
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index c33ce47578..6d87fad739 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -995,6 +995,8 @@ static FWCfgState *bochs_bios_init(AddressSpace *as, PCMachineState *pcms)
int i;
const CPUArchIdList *cpus;
MachineClass *mc = MACHINE_GET_CLASS(pcms);
+ MachineState *ms = MACHINE(pcms);
+ int nb_numa_nodes = ms->numa_state->num_nodes;
fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, as);
fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
@@ -1758,12 +1760,13 @@ void pc_machine_done(Notifier *notifier, void *data)
void pc_guest_info_init(PCMachineState *pcms)
{
int i;
+ MachineState *ms = MACHINE(pcms);
pcms->apic_xrupt_override = kvm_allows_irq0_override();
- pcms->numa_nodes = nb_numa_nodes;
+ pcms->numa_nodes = ms->numa_state->num_nodes;
pcms->node_mem = g_malloc0(pcms->numa_nodes *
sizeof *pcms->node_mem);
- for (i = 0; i < nb_numa_nodes; i++) {
+ for (i = 0; i < ms->numa_state->num_nodes; i++) {
pcms->node_mem[i] = numa_info[i].node_mem;
}
@@ -2842,7 +2845,7 @@ static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx)
x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
pcms->smp_dies, ms->smp.cores,
ms->smp.threads, &topo);
- return topo.pkg_id % nb_numa_nodes;
+ return topo.pkg_id % ms->numa_state->num_nodes;
}
static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms)
diff --git a/hw/mem/pc-dimm.c b/hw/mem/pc-dimm.c
index b1239fd0d3..0a32a9fb17 100644
--- a/hw/mem/pc-dimm.c
+++ b/hw/mem/pc-dimm.c
@@ -161,6 +161,8 @@ static void pc_dimm_realize(DeviceState *dev, Error **errp)
{
PCDIMMDevice *dimm = PC_DIMM(dev);
PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
+ MachineState *ms = MACHINE(qdev_get_machine());
+ int nb_numa_nodes = ms->numa_state->num_nodes;
if (!dimm->hostmem) {
error_setg(errp, "'" PC_DIMM_MEMDEV_PROP "' property is not set");
diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expander_bridge.c
index aecf3d7ddf..0b4c5f1e71 100644
--- a/hw/pci-bridge/pci_expander_bridge.c
+++ b/hw/pci-bridge/pci_expander_bridge.c
@@ -212,9 +212,10 @@ static void pxb_dev_realize_common(PCIDevice *dev, bool pcie, Error **errp)
PCIBus *bus;
const char *dev_name = NULL;
Error *local_err = NULL;
+ MachineState *ms = MACHINE(qdev_get_machine());
if (pxb->numa_node != NUMA_NODE_UNASSIGNED &&
- pxb->numa_node >= nb_numa_nodes) {
+ pxb->numa_node >= ms->numa_state->num_nodes) {
error_setg(errp, "Illegal numa node %d", pxb->numa_node);
return;
}
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 821f0d4a49..2aec966616 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -331,7 +331,7 @@ static int spapr_fixup_cpu_dt(void *fdt, SpaprMachineState *spapr)
return ret;
}
- if (nb_numa_nodes > 1) {
+ if (ms->numa_state->num_nodes > 1) {
ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu);
if (ret < 0) {
return ret;
@@ -351,9 +351,9 @@ static int spapr_fixup_cpu_dt(void *fdt, SpaprMachineState *spapr)
static hwaddr spapr_node0_size(MachineState *machine)
{
- if (nb_numa_nodes) {
+ if (machine->numa_state->num_nodes) {
int i;
- for (i = 0; i < nb_numa_nodes; ++i) {
+ for (i = 0; i < machine->numa_state->num_nodes; ++i) {
if (numa_info[i].node_mem) {
return MIN(pow2floor(numa_info[i].node_mem),
machine->ram_size);
@@ -398,18 +398,18 @@ static int spapr_populate_memory(SpaprMachineState *spapr, void *fdt)
{
MachineState *machine = MACHINE(spapr);
hwaddr mem_start, node_size;
- int i, nb_nodes = nb_numa_nodes;
+ int i;
NodeInfo *nodes = numa_info;
NodeInfo ramnode;
/* No NUMA nodes, assume there is just one node with whole RAM */
- if (!nb_numa_nodes) {
- nb_nodes = 1;
+ if (!machine->numa_state->num_nodes) {
+ machine->numa_state->num_nodes = 1;
ramnode.node_mem = machine->ram_size;
nodes = &ramnode;
}
- for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
+ for (i = 0, mem_start = 0; i < machine->numa_state->num_nodes; ++i) {
if (!nodes[i].node_mem) {
continue;
}
@@ -554,7 +554,7 @@ static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
_FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
pft_size_prop, sizeof(pft_size_prop))));
- if (nb_numa_nodes > 1) {
+ if (ms->numa_state->num_nodes > 1) {
_FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu));
}
@@ -861,6 +861,7 @@ static int spapr_populate_drmem_v1(SpaprMachineState *spapr, void *fdt,
static int spapr_populate_drconf_memory(SpaprMachineState *spapr, void *fdt)
{
MachineState *machine = MACHINE(spapr);
+ int nb_numa_nodes = machine->numa_state->num_nodes;
int ret, i, offset;
uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
@@ -1750,7 +1751,7 @@ static void spapr_machine_reset(MachineState *machine)
* The final value of spapr->gpu_numa_id is going to be written to
* max-associativity-domains in spapr_build_fdt().
*/
- spapr->gpu_numa_id = MAX(1, nb_numa_nodes);
+ spapr->gpu_numa_id = MAX(1, machine->numa_state->num_nodes);
qemu_devices_reset();
/*
@@ -2537,7 +2538,7 @@ static void spapr_validate_node_memory(MachineState *machine, Error **errp)
return;
}
- for (i = 0; i < nb_numa_nodes; i++) {
+ for (i = 0; i < machine->numa_state->num_nodes; i++) {
if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
error_setg(errp,
"Node %d memory size 0x%" PRIx64
@@ -4139,7 +4140,7 @@ spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index)
static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx)
{
- return idx / ms->smp.cores % nb_numa_nodes;
+ return idx / ms->smp.cores % ms->numa_state->num_nodes;
}
static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine)
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index 1a563ad756..991cf05134 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -414,7 +414,7 @@ build_append_gas_from_struct(GArray *table, const struct AcpiGenericAddress *s)
void build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base,
uint64_t len, int node, MemoryAffinityFlags flags);
-void build_slit(GArray *table_data, BIOSLinker *linker);
+void build_slit(GArray *table_data, BIOSLinker *linker, MachineState *ms);
void build_fadt(GArray *tbl, BIOSLinker *linker, const AcpiFadtData *f,
const char *oem_id, const char *oem_table_id);
diff --git a/include/hw/boards.h b/include/hw/boards.h
index a71d1a53a5..2eb9a0b4e0 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -298,6 +298,7 @@ struct MachineState {
CPUArchIdList *possible_cpus;
CpuTopology smp;
struct NVDIMMState *nvdimms_state;
+ struct NumaState *numa_state;
};
#define DEFINE_MACHINE(namestr, machine_initfn) \
diff --git a/include/sysemu/numa.h b/include/sysemu/numa.h
index 01a263eba2..3e8dbf20c1 100644
--- a/include/sysemu/numa.h
+++ b/include/sysemu/numa.h
@@ -6,7 +6,6 @@
#include "sysemu/hostmem.h"
#include "hw/boards.h"
-extern int nb_numa_nodes; /* Number of NUMA nodes */
extern bool have_numa_distance;
struct NodeInfo {
@@ -23,10 +22,17 @@ struct NumaNodeMem {
extern NodeInfo numa_info[MAX_NODES];
+struct NumaState {
+ /* Number of NUMA nodes */
+ int num_nodes;
+
+};
+typedef struct NumaState NumaState;
+
void set_numa_options(MachineState *ms, NumaOptions *object, Error **errp);
void parse_numa_opts(MachineState *ms);
void numa_complete_configuration(MachineState *ms);
-void query_numa_node_mem(NumaNodeMem node_mem[]);
+void query_numa_node_mem(NumaNodeMem node_mem[], MachineState *ms);
extern QemuOptsList qemu_numa_opts;
void numa_legacy_auto_assign_ram(MachineClass *mc, NodeInfo *nodes,
int nb_nodes, ram_addr_t size);
--
2.20.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH RESEND v6 03/14] numa: move numa global variable have_numa_distance into MachineState
2019-07-09 7:15 [Qemu-devel] [PATCH RESEND v6 00/14] Build ACPI Heterogeneous Memory Attribute Table (HMAT) Tao Xu
2019-07-09 7:15 ` [Qemu-devel] [PATCH RESEND v6 01/14] hw/arm: simplify arm_load_dtb Tao Xu
2019-07-09 7:15 ` [Qemu-devel] [PATCH RESEND v6 02/14] numa: move numa global variable nb_numa_nodes into MachineState Tao Xu
@ 2019-07-09 7:15 ` Tao Xu
2019-07-09 7:15 ` [Qemu-devel] [PATCH RESEND v6 04/14] numa: move numa global variable numa_info " Tao Xu
` (12 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Tao Xu @ 2019-07-09 7:15 UTC (permalink / raw)
To: imammedo, eblake, ehabkost
Cc: jingqi.liu, tao3.xu, fan.du, qemu-devel, jonathan.cameron,
dan.j.williams
Move existing numa global have_numa_distance into NumaState.
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Liu Jingqi <jingqi.liu@intel.com>
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Suggested-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Tao Xu <tao3.xu@intel.com>
---
Changes in v6:
- rebase to upstream, move globals in arm/sbsa-ref
---
hw/arm/sbsa-ref.c | 2 +-
hw/arm/virt-acpi-build.c | 2 +-
hw/arm/virt.c | 2 +-
hw/core/numa.c | 5 ++---
hw/i386/acpi-build.c | 2 +-
include/sysemu/numa.h | 4 ++--
6 files changed, 8 insertions(+), 9 deletions(-)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index 22847909bf..7e4c471717 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -158,7 +158,7 @@ static void create_fdt(SBSAMachineState *sms)
qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
- if (have_numa_distance) {
+ if (ms->numa_state->have_numa_distance) {
int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
uint32_t *matrix = g_malloc0(size);
int idx, i, j;
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index a2cc4b84fe..461a44b5b0 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -797,7 +797,7 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
if (ms->numa_state->num_nodes > 0) {
acpi_add_table(table_offsets, tables_blob);
build_srat(tables_blob, tables->linker, vms);
- if (have_numa_distance) {
+ if (ms->numa_state->have_numa_distance) {
acpi_add_table(table_offsets, tables_blob);
build_slit(tables_blob, tables->linker, ms);
}
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 01a32272b4..984f162531 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -232,7 +232,7 @@ static void create_fdt(VirtMachineState *vms)
"clk24mhz");
qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle);
- if (have_numa_distance) {
+ if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) {
int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
uint32_t *matrix = g_malloc0(size);
int idx, i, j;
diff --git a/hw/core/numa.c b/hw/core/numa.c
index 4d5e308bf1..2142ec29e8 100644
--- a/hw/core/numa.c
+++ b/hw/core/numa.c
@@ -50,7 +50,6 @@ static int have_mem;
static int max_numa_nodeid; /* Highest specified NUMA node ID, plus one.
* For all nodes, nodeid < max_numa_nodeid
*/
-bool have_numa_distance;
NodeInfo numa_info[MAX_NODES];
@@ -168,7 +167,7 @@ void parse_numa_distance(MachineState *ms, NumaDistOptions *dist, Error **errp)
}
numa_info[src].distance[dst] = val;
- have_numa_distance = true;
+ ms->numa_state->have_numa_distance = true;
}
void set_numa_options(MachineState *ms, NumaOptions *object, Error **errp)
@@ -441,7 +440,7 @@ void numa_complete_configuration(MachineState *ms)
* asymmetric. In this case, the distances for both directions
* of all node pairs are required.
*/
- if (have_numa_distance) {
+ if (ms->numa_state->have_numa_distance) {
/* Validate enough NUMA distance information was provided. */
validate_numa_distance(ms);
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 83a8551af6..243c5b85c8 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -2683,7 +2683,7 @@ void acpi_build(AcpiBuildTables *tables, MachineState *machine)
if (pcms->numa_nodes) {
acpi_add_table(table_offsets, tables_blob);
build_srat(tables_blob, tables->linker, machine);
- if (have_numa_distance) {
+ if (machine->numa_state->have_numa_distance) {
acpi_add_table(table_offsets, tables_blob);
build_slit(tables_blob, tables->linker, machine);
}
diff --git a/include/sysemu/numa.h b/include/sysemu/numa.h
index 3e8dbf20c1..2e5e998adb 100644
--- a/include/sysemu/numa.h
+++ b/include/sysemu/numa.h
@@ -6,8 +6,6 @@
#include "sysemu/hostmem.h"
#include "hw/boards.h"
-extern bool have_numa_distance;
-
struct NodeInfo {
uint64_t node_mem;
struct HostMemoryBackend *node_memdev;
@@ -26,6 +24,8 @@ struct NumaState {
/* Number of NUMA nodes */
int num_nodes;
+ /* Allow setting NUMA distance for different NUMA nodes */
+ bool have_numa_distance;
};
typedef struct NumaState NumaState;
--
2.20.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH RESEND v6 04/14] numa: move numa global variable numa_info into MachineState
2019-07-09 7:15 [Qemu-devel] [PATCH RESEND v6 00/14] Build ACPI Heterogeneous Memory Attribute Table (HMAT) Tao Xu
` (2 preceding siblings ...)
2019-07-09 7:15 ` [Qemu-devel] [PATCH RESEND v6 03/14] numa: move numa global variable have_numa_distance " Tao Xu
@ 2019-07-09 7:15 ` Tao Xu
2019-07-09 7:15 ` [Qemu-devel] [PATCH RESEND v6 05/14] numa: Extend CLI to provide initiator information for numa nodes Tao Xu
` (11 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Tao Xu @ 2019-07-09 7:15 UTC (permalink / raw)
To: imammedo, eblake, ehabkost
Cc: jingqi.liu, tao3.xu, fan.du, qemu-devel, jonathan.cameron,
dan.j.williams
Move existing numa global numa_info (renamed as "nodes") into NumaState.
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Suggested-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Tao Xu <tao3.xu@intel.com>
---
Changes in v6:
- Rebase to upstream, move globals in arm/sbsa-ref
- Correct some mistake(Igor)
- Use ms->numa_state->nodes directly, when use it once or twice(Igor)
---
exec.c | 2 +-
hw/acpi/aml-build.c | 6 ++++--
hw/arm/boot.c | 2 +-
hw/arm/sbsa-ref.c | 3 ++-
hw/arm/virt-acpi-build.c | 7 ++++---
hw/arm/virt.c | 3 ++-
hw/core/numa.c | 15 +++++++++------
hw/i386/pc.c | 4 ++--
hw/ppc/spapr.c | 10 +++++-----
hw/ppc/spapr_pci.c | 4 +++-
include/sysemu/numa.h | 3 +++
11 files changed, 36 insertions(+), 23 deletions(-)
diff --git a/exec.c b/exec.c
index b6b75d2ad5..26dd7676c0 100644
--- a/exec.c
+++ b/exec.c
@@ -1766,7 +1766,7 @@ long qemu_minrampagesize(void)
if (hpsize > mainrampagesize &&
(ms->numa_state == NULL ||
ms->numa_state->num_nodes == 0 ||
- numa_info[0].node_memdev == NULL)) {
+ ms->numa_state->nodes[0].node_memdev == NULL)) {
static bool warned;
if (!warned) {
error_report("Huge page support disabled (n/a for main memory).");
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index 63c1cae8c9..26ccc1a3e2 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -1737,8 +1737,10 @@ void build_slit(GArray *table_data, BIOSLinker *linker, MachineState *ms)
build_append_int_noprefix(table_data, nb_numa_nodes, 8);
for (i = 0; i < nb_numa_nodes; i++) {
for (j = 0; j < nb_numa_nodes; j++) {
- assert(numa_info[i].distance[j]);
- build_append_int_noprefix(table_data, numa_info[i].distance[j], 1);
+ assert(ms->numa_state->nodes[i].distance[j]);
+ build_append_int_noprefix(table_data,
+ ms->numa_state->nodes[i].distance[j],
+ 1);
}
}
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index e28daa5278..da228919dc 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -601,7 +601,7 @@ int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo,
if (ms->numa_state != NULL && ms->numa_state->num_nodes > 0) {
mem_base = binfo->loader_start;
for (i = 0; i < ms->numa_state->num_nodes; i++) {
- mem_len = numa_info[i].node_mem;
+ mem_len = ms->numa_state->nodes[i].node_mem;
rc = fdt_add_memory_node(fdt, acells, mem_base,
scells, mem_len, i);
if (rc < 0) {
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index 7e4c471717..3a243e6a53 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -168,7 +168,8 @@ static void create_fdt(SBSAMachineState *sms)
idx = (i * nb_numa_nodes + j) * 3;
matrix[idx + 0] = cpu_to_be32(i);
matrix[idx + 1] = cpu_to_be32(j);
- matrix[idx + 2] = cpu_to_be32(numa_info[i].distance[j]);
+ matrix[idx + 2] =
+ cpu_to_be32(ms->numa_state->nodes[i].distance[j]);
}
}
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 461a44b5b0..89899ec4c1 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -534,11 +534,12 @@ build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
mem_base = vms->memmap[VIRT_MEM].base;
for (i = 0; i < ms->numa_state->num_nodes; ++i) {
- if (numa_info[i].node_mem > 0) {
+ if (ms->numa_state->nodes[i].node_mem > 0) {
numamem = acpi_data_push(table_data, sizeof(*numamem));
- build_srat_memory(numamem, mem_base, numa_info[i].node_mem, i,
+ build_srat_memory(numamem, mem_base,
+ ms->numa_state->nodes[i].node_mem, i,
MEM_AFFINITY_ENABLED);
- mem_base += numa_info[i].node_mem;
+ mem_base += ms->numa_state->nodes[i].node_mem;
}
}
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 984f162531..174e81a3de 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -242,7 +242,8 @@ static void create_fdt(VirtMachineState *vms)
idx = (i * nb_numa_nodes + j) * 3;
matrix[idx + 0] = cpu_to_be32(i);
matrix[idx + 1] = cpu_to_be32(j);
- matrix[idx + 2] = cpu_to_be32(numa_info[i].distance[j]);
+ matrix[idx + 2] =
+ cpu_to_be32(ms->numa_state->nodes[i].distance[j]);
}
}
diff --git a/hw/core/numa.c b/hw/core/numa.c
index 2142ec29e8..8fcbba05d6 100644
--- a/hw/core/numa.c
+++ b/hw/core/numa.c
@@ -50,8 +50,6 @@ static int have_mem;
static int max_numa_nodeid; /* Highest specified NUMA node ID, plus one.
* For all nodes, nodeid < max_numa_nodeid
*/
-NodeInfo numa_info[MAX_NODES];
-
static void parse_numa_node(MachineState *ms, NumaNodeOptions *node,
Error **errp)
@@ -61,6 +59,7 @@ static void parse_numa_node(MachineState *ms, NumaNodeOptions *node,
uint16List *cpus = NULL;
MachineClass *mc = MACHINE_GET_CLASS(ms);
unsigned int max_cpus = ms->smp.max_cpus;
+ NodeInfo *numa_info = ms->numa_state->nodes;
if (node->has_nodeid) {
nodenr = node->nodeid;
@@ -140,6 +139,7 @@ void parse_numa_distance(MachineState *ms, NumaDistOptions *dist, Error **errp)
uint16_t src = dist->src;
uint16_t dst = dist->dst;
uint8_t val = dist->val;
+ NodeInfo *numa_info = ms->numa_state->nodes;
if (src >= MAX_NODES || dst >= MAX_NODES) {
error_setg(errp, "Parameter '%s' expects an integer between 0 and %d",
@@ -198,7 +198,7 @@ void set_numa_options(MachineState *ms, NumaOptions *object, Error **errp)
error_setg(&err, "Missing mandatory node-id property");
goto end;
}
- if (!numa_info[object->u.cpu.node_id].present) {
+ if (!ms->numa_state->nodes[object->u.cpu.node_id].present) {
error_setg(&err, "Invalid node-id=%" PRId64 ", NUMA node must be "
"defined with -numa node,nodeid=ID before it's used with "
"-numa cpu,node-id=ID", object->u.cpu.node_id);
@@ -258,6 +258,7 @@ static void validate_numa_distance(MachineState *ms)
int src, dst;
bool is_asymmetrical = false;
int nb_numa_nodes = ms->numa_state->num_nodes;
+ NodeInfo *numa_info = ms->numa_state->nodes;
for (src = 0; src < nb_numa_nodes; src++) {
for (dst = src; dst < nb_numa_nodes; dst++) {
@@ -298,6 +299,7 @@ static void validate_numa_distance(MachineState *ms)
static void complete_init_numa_distance(MachineState *ms)
{
int src, dst;
+ NodeInfo *numa_info = ms->numa_state->nodes;
/* Fixup NUMA distance by symmetric policy because if it is an
* asymmetric distance table, it should be a complete table and
@@ -357,6 +359,7 @@ void numa_complete_configuration(MachineState *ms)
{
int i;
MachineClass *mc = MACHINE_GET_CLASS(ms);
+ NodeInfo *numa_info = ms->numa_state->nodes;
/*
* If memory hotplug is enabled (slots > 0) but without '-numa'
@@ -522,8 +525,8 @@ void memory_region_allocate_system_memory(MemoryRegion *mr, Object *owner,
memory_region_init(mr, owner, name, ram_size);
for (i = 0; i < ms->numa_state->num_nodes; i++) {
- uint64_t size = numa_info[i].node_mem;
- HostMemoryBackend *backend = numa_info[i].node_memdev;
+ uint64_t size = ms->numa_state->nodes[i].node_mem;
+ HostMemoryBackend *backend = ms->numa_state->nodes[i].node_memdev;
if (!backend) {
continue;
}
@@ -589,7 +592,7 @@ void query_numa_node_mem(NumaNodeMem node_mem[], MachineState *ms)
numa_stat_memory_devices(node_mem);
for (i = 0; i < ms->numa_state->num_nodes; i++) {
- node_mem[i].node_mem += numa_info[i].node_mem;
+ node_mem[i].node_mem += ms->numa_state->nodes[i].node_mem;
}
}
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 6d87fad739..5122f49973 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1039,7 +1039,7 @@ static FWCfgState *bochs_bios_init(AddressSpace *as, PCMachineState *pcms)
}
for (i = 0; i < nb_numa_nodes; i++) {
numa_fw_cfg[pcms->apic_id_limit + 1 + i] =
- cpu_to_le64(numa_info[i].node_mem);
+ cpu_to_le64(ms->numa_state->nodes[i].node_mem);
}
fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
(1 + pcms->apic_id_limit + nb_numa_nodes) *
@@ -1767,7 +1767,7 @@ void pc_guest_info_init(PCMachineState *pcms)
pcms->node_mem = g_malloc0(pcms->numa_nodes *
sizeof *pcms->node_mem);
for (i = 0; i < ms->numa_state->num_nodes; i++) {
- pcms->node_mem[i] = numa_info[i].node_mem;
+ pcms->node_mem[i] = ms->numa_state->nodes[i].node_mem;
}
pcms->machine_done.notify = pc_machine_done;
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 2aec966616..5a9128f07e 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -354,8 +354,8 @@ static hwaddr spapr_node0_size(MachineState *machine)
if (machine->numa_state->num_nodes) {
int i;
for (i = 0; i < machine->numa_state->num_nodes; ++i) {
- if (numa_info[i].node_mem) {
- return MIN(pow2floor(numa_info[i].node_mem),
+ if (machine->numa_state->nodes[i].node_mem) {
+ return MIN(pow2floor(machine->numa_state->nodes[i].node_mem),
machine->ram_size);
}
}
@@ -399,7 +399,7 @@ static int spapr_populate_memory(SpaprMachineState *spapr, void *fdt)
MachineState *machine = MACHINE(spapr);
hwaddr mem_start, node_size;
int i;
- NodeInfo *nodes = numa_info;
+ NodeInfo *nodes = machine->numa_state->nodes;
NodeInfo ramnode;
/* No NUMA nodes, assume there is just one node with whole RAM */
@@ -2539,11 +2539,11 @@ static void spapr_validate_node_memory(MachineState *machine, Error **errp)
}
for (i = 0; i < machine->numa_state->num_nodes; i++) {
- if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
+ if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
error_setg(errp,
"Node %d memory size 0x%" PRIx64
" is not aligned to %" PRIu64 " MiB",
- i, numa_info[i].node_mem,
+ i, machine->numa_state->nodes[i].node_mem,
SPAPR_MEMORY_BLOCK_SIZE / MiB);
return;
}
diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
index 9003fe9010..f05d82eee7 100644
--- a/hw/ppc/spapr_pci.c
+++ b/hw/ppc/spapr_pci.c
@@ -1818,6 +1818,7 @@ static void spapr_phb_realize(DeviceState *dev, Error **errp)
SysBusDevice *s = SYS_BUS_DEVICE(dev);
SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(s);
PCIHostState *phb = PCI_HOST_BRIDGE(s);
+ MachineState *ms = MACHINE(spapr);
char *namebuf;
int i;
PCIBus *bus;
@@ -1870,7 +1871,8 @@ static void spapr_phb_realize(DeviceState *dev, Error **errp)
}
if (sphb->numa_node != -1 &&
- (sphb->numa_node >= MAX_NODES || !numa_info[sphb->numa_node].present)) {
+ (sphb->numa_node >= MAX_NODES ||
+ !ms->numa_state->nodes[sphb->numa_node].present)) {
error_setg(errp, "Invalid NUMA node ID for PCI host bridge");
return;
}
diff --git a/include/sysemu/numa.h b/include/sysemu/numa.h
index 2e5e998adb..186ea0eb5e 100644
--- a/include/sysemu/numa.h
+++ b/include/sysemu/numa.h
@@ -26,6 +26,9 @@ struct NumaState {
/* Allow setting NUMA distance for different NUMA nodes */
bool have_numa_distance;
+
+ /* NUMA nodes information */
+ NodeInfo nodes[MAX_NODES];
};
typedef struct NumaState NumaState;
--
2.20.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH RESEND v6 05/14] numa: Extend CLI to provide initiator information for numa nodes
2019-07-09 7:15 [Qemu-devel] [PATCH RESEND v6 00/14] Build ACPI Heterogeneous Memory Attribute Table (HMAT) Tao Xu
` (3 preceding siblings ...)
2019-07-09 7:15 ` [Qemu-devel] [PATCH RESEND v6 04/14] numa: move numa global variable numa_info " Tao Xu
@ 2019-07-09 7:15 ` Tao Xu
2019-07-09 7:15 ` [Qemu-devel] [PATCH RESEND v6 06/14] hmat acpi: Build Memory Proximity Domain Attributes Structure(s) Tao Xu
` (10 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Tao Xu @ 2019-07-09 7:15 UTC (permalink / raw)
To: imammedo, eblake, ehabkost
Cc: jingqi.liu, tao3.xu, fan.du, qemu-devel, jonathan.cameron,
dan.j.williams
In ACPI 6.3 chapter 5.2.27 Heterogeneous Memory Attribute Table (HMAT),
The initiator represents processor which access to memory. And in 5.2.27.3
Memory Proximity Domain Attributes Structure, the attached initiator is
defined as where the memory controller responsible for a memory proximity
domain. With attached initiator information, the topology of heterogeneous
memory can be described.
Extend CLI of "-numa node" option to indicate the initiator numa node-id.
In the linux kernel, the codes in drivers/acpi/hmat/hmat.c parse and report
the platform's HMAT tables.
Suggested-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Tao Xu <tao3.xu@intel.com>
---
Changes in v6:
- Add the version designator (since 4.2) after @initiator (Eric)
---
hw/core/machine.c | 24 ++++++++++++++++++++++++
hw/core/numa.c | 13 +++++++++++++
include/sysemu/numa.h | 3 +++
qapi/machine.json | 6 +++++-
qemu-options.hx | 27 +++++++++++++++++++++++----
5 files changed, 68 insertions(+), 5 deletions(-)
diff --git a/hw/core/machine.c b/hw/core/machine.c
index 4228bcd2a2..063cb7923c 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -653,6 +653,7 @@ void machine_set_cpu_numa_node(MachineState *machine,
const CpuInstanceProperties *props, Error **errp)
{
MachineClass *mc = MACHINE_GET_CLASS(machine);
+ NodeInfo *numa_info = machine->numa_state->nodes;
bool match = false;
int i;
@@ -722,6 +723,16 @@ void machine_set_cpu_numa_node(MachineState *machine,
match = true;
slot->props.node_id = props->node_id;
slot->props.has_node_id = props->has_node_id;
+
+ if (numa_info[props->node_id].initiator_valid &&
+ (props->node_id != numa_info[props->node_id].initiator)) {
+ error_setg(errp, "The initiator of CPU NUMA node %" PRId64
+ " should be itself.", props->node_id);
+ return;
+ }
+ numa_info[props->node_id].initiator_valid = true;
+ numa_info[props->node_id].has_cpu = true;
+ numa_info[props->node_id].initiator = props->node_id;
}
if (!match) {
@@ -1063,6 +1074,7 @@ static void machine_numa_finish_cpu_init(MachineState *machine)
GString *s = g_string_new(NULL);
MachineClass *mc = MACHINE_GET_CLASS(machine);
const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(machine);
+ NodeInfo *numa_info = machine->numa_state->nodes;
assert(machine->numa_state->num_nodes);
for (i = 0; i < possible_cpus->len; i++) {
@@ -1096,6 +1108,18 @@ static void machine_numa_finish_cpu_init(MachineState *machine)
machine_set_cpu_numa_node(machine, &props, &error_fatal);
}
}
+
+ for (i = 0; i < machine->numa_state->num_nodes; i++) {
+ if (numa_info[i].initiator_valid &&
+ !numa_info[numa_info[i].initiator].has_cpu) {
+ error_report("The initiator-id %"PRIu16 " of NUMA node %d"
+ " does not exist.", numa_info[i].initiator, i);
+ error_printf("\n");
+
+ exit(1);
+ }
+ }
+
if (s->len && !qtest_enabled()) {
warn_report("CPU(s) not present in any NUMA nodes: %s",
s->str);
diff --git a/hw/core/numa.c b/hw/core/numa.c
index 8fcbba05d6..cfb6339810 100644
--- a/hw/core/numa.c
+++ b/hw/core/numa.c
@@ -128,6 +128,19 @@ static void parse_numa_node(MachineState *ms, NumaNodeOptions *node,
numa_info[nodenr].node_mem = object_property_get_uint(o, "size", NULL);
numa_info[nodenr].node_memdev = MEMORY_BACKEND(o);
}
+
+ if (node->has_initiator) {
+ if (numa_info[nodenr].initiator_valid &&
+ (node->initiator != numa_info[nodenr].initiator)) {
+ error_setg(errp, "The initiator of NUMA node %" PRIu16 " has been "
+ "set to node %" PRIu16, nodenr,
+ numa_info[nodenr].initiator);
+ return;
+ }
+
+ numa_info[nodenr].initiator_valid = true;
+ numa_info[nodenr].initiator = node->initiator;
+ }
numa_info[nodenr].present = true;
max_numa_nodeid = MAX(max_numa_nodeid, nodenr + 1);
ms->numa_state->num_nodes++;
diff --git a/include/sysemu/numa.h b/include/sysemu/numa.h
index 186ea0eb5e..21232d775e 100644
--- a/include/sysemu/numa.h
+++ b/include/sysemu/numa.h
@@ -10,6 +10,9 @@ struct NodeInfo {
uint64_t node_mem;
struct HostMemoryBackend *node_memdev;
bool present;
+ bool has_cpu;
+ bool initiator_valid;
+ uint16_t initiator;
uint8_t distance[MAX_NODES];
};
diff --git a/qapi/machine.json b/qapi/machine.json
index 6db8a7e2ec..05e367d26a 100644
--- a/qapi/machine.json
+++ b/qapi/machine.json
@@ -414,6 +414,9 @@
# @memdev: memory backend object. If specified for one node,
# it must be specified for all nodes.
#
+# @initiator: the initiator numa nodeid that is closest (as in directly
+# attached) to this numa node (since 4.2)
+#
# Since: 2.1
##
{ 'struct': 'NumaNodeOptions',
@@ -421,7 +424,8 @@
'*nodeid': 'uint16',
'*cpus': ['uint16'],
'*mem': 'size',
- '*memdev': 'str' }}
+ '*memdev': 'str',
+ '*initiator': 'uint16' }}
##
# @NumaDistOptions:
diff --git a/qemu-options.hx b/qemu-options.hx
index 9621e934c0..c480781992 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -161,14 +161,14 @@ If any on the three values is given, the total number of CPUs @var{n} can be omi
ETEXI
DEF("numa", HAS_ARG, QEMU_OPTION_numa,
- "-numa node[,mem=size][,cpus=firstcpu[-lastcpu]][,nodeid=node]\n"
- "-numa node[,memdev=id][,cpus=firstcpu[-lastcpu]][,nodeid=node]\n"
+ "-numa node[,mem=size][,cpus=firstcpu[-lastcpu]][,nodeid=node][,initiator=node]\n"
+ "-numa node[,memdev=id][,cpus=firstcpu[-lastcpu]][,nodeid=node][,initiator=node]\n"
"-numa dist,src=source,dst=destination,val=distance\n"
"-numa cpu,node-id=node[,socket-id=x][,core-id=y][,thread-id=z]\n",
QEMU_ARCH_ALL)
STEXI
-@item -numa node[,mem=@var{size}][,cpus=@var{firstcpu}[-@var{lastcpu}]][,nodeid=@var{node}]
-@itemx -numa node[,memdev=@var{id}][,cpus=@var{firstcpu}[-@var{lastcpu}]][,nodeid=@var{node}]
+@item -numa node[,mem=@var{size}][,cpus=@var{firstcpu}[-@var{lastcpu}]][,nodeid=@var{node}][,initiator=@var{initiator}]
+@itemx -numa node[,memdev=@var{id}][,cpus=@var{firstcpu}[-@var{lastcpu}]][,nodeid=@var{node}][,initiator=@var{initiator}]
@itemx -numa dist,src=@var{source},dst=@var{destination},val=@var{distance}
@itemx -numa cpu,node-id=@var{node}[,socket-id=@var{x}][,core-id=@var{y}][,thread-id=@var{z}]
@findex -numa
@@ -215,6 +215,25 @@ split equally between them.
@samp{mem} and @samp{memdev} are mutually exclusive. Furthermore,
if one node uses @samp{memdev}, all of them have to use it.
+@samp{initiator} indicate the initiator NUMA @var{initiator} that is
+closest (as in directly attached) to this NUMA @var{node}.
+
+For example, the following option assigns 2 NUMA nodes, node 0 has CPU.
+node 1 has only memory, and its' initiator is node 0. Note that because
+node 0 has CPU, by default the initiator of node 0 is itself and must be
+itself.
+@example
+-M pc \
+-m 2G,slots=2,maxmem=4G \
+-object memory-backend-ram,size=1G,id=m0 \
+-object memory-backend-ram,size=1G,id=m1 \
+-numa node,nodeid=0,memdev=m0 \
+-numa node,nodeid=1,memdev=m1,initiator=0 \
+-smp 2,sockets=2,maxcpus=2 \
+-numa cpu,node-id=0,socket-id=0 \
+-numa cpu,node-id=0,socket-id=1 \
+@end example
+
@var{source} and @var{destination} are NUMA node IDs.
@var{distance} is the NUMA distance from @var{source} to @var{destination}.
The distance from a node to itself is always 10. If any pair of nodes is
--
2.20.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH RESEND v6 06/14] hmat acpi: Build Memory Proximity Domain Attributes Structure(s)
2019-07-09 7:15 [Qemu-devel] [PATCH RESEND v6 00/14] Build ACPI Heterogeneous Memory Attribute Table (HMAT) Tao Xu
` (4 preceding siblings ...)
2019-07-09 7:15 ` [Qemu-devel] [PATCH RESEND v6 05/14] numa: Extend CLI to provide initiator information for numa nodes Tao Xu
@ 2019-07-09 7:15 ` Tao Xu
2019-07-09 7:15 ` [Qemu-devel] [PATCH RESEND v6 07/14] hmat acpi: Build System Locality Latency and Bandwidth Information Structure(s) Tao Xu
` (9 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Tao Xu @ 2019-07-09 7:15 UTC (permalink / raw)
To: imammedo, eblake, ehabkost
Cc: jingqi.liu, tao3.xu, fan.du, qemu-devel, jonathan.cameron,
dan.j.williams
From: Liu Jingqi <jingqi.liu@intel.com>
HMAT is defined in ACPI 6.3: 5.2.27 Heterogeneous Memory Attribute Table
(HMAT). The specification references below link:
http://www.uefi.org/sites/default/files/resources/ACPI_6_3_final_Jan30.pdf
It describes the memory attributes, such as memory side cache
attributes and bandwidth and latency details, related to the
Memory Proximity Domain. The software is
expected to use this information as hint for optimization.
This structure describes Memory Proximity Domain Attributes by memory
subsystem and its associativity with processor proximity domain as well as
hint for memory usage.
In the linux kernel, the codes in drivers/acpi/hmat/hmat.c parse and report
the platform's HMAT tables.
Signed-off-by: Liu Jingqi <jingqi.liu@intel.com>
Signed-off-by: Tao Xu <tao3.xu@intel.com>
---
Changes in v6:
Update to ACPI 6.3, main changes are:
- Renamed as Memory Proximity Domain Attributes, use numa nodes to
replace memory ranges
- Use "-numa initiator" to describe "the Attached Initiator", more
clear for memory topology
- Because HMAT does not use memory ranges, remove the codes to build
mem_renges for dimm device
---
hw/acpi/Kconfig | 5 +++
hw/acpi/Makefile.objs | 1 +
hw/acpi/hmat.c | 101 ++++++++++++++++++++++++++++++++++++++++++
hw/acpi/hmat.h | 45 +++++++++++++++++++
hw/i386/acpi-build.c | 3 ++
5 files changed, 155 insertions(+)
create mode 100644 hw/acpi/hmat.c
create mode 100644 hw/acpi/hmat.h
diff --git a/hw/acpi/Kconfig b/hw/acpi/Kconfig
index 7c59cf900b..039bb99efa 100644
--- a/hw/acpi/Kconfig
+++ b/hw/acpi/Kconfig
@@ -7,6 +7,7 @@ config ACPI_X86
select ACPI_NVDIMM
select ACPI_CPU_HOTPLUG
select ACPI_MEMORY_HOTPLUG
+ select ACPI_HMAT
config ACPI_X86_ICH
bool
@@ -31,3 +32,7 @@ config ACPI_VMGENID
bool
default y
depends on PC
+
+config ACPI_HMAT
+ bool
+ depends on ACPI
diff --git a/hw/acpi/Makefile.objs b/hw/acpi/Makefile.objs
index 9bb2101e3b..c05019b059 100644
--- a/hw/acpi/Makefile.objs
+++ b/hw/acpi/Makefile.objs
@@ -6,6 +6,7 @@ common-obj-$(CONFIG_ACPI_MEMORY_HOTPLUG) += memory_hotplug.o
common-obj-$(CONFIG_ACPI_CPU_HOTPLUG) += cpu.o
common-obj-$(CONFIG_ACPI_NVDIMM) += nvdimm.o
common-obj-$(CONFIG_ACPI_VMGENID) += vmgenid.o
+common-obj-$(CONFIG_ACPI_HMAT) += hmat.o
common-obj-$(call lnot,$(CONFIG_ACPI_X86)) += acpi-stub.o
common-obj-y += acpi_interface.o
diff --git a/hw/acpi/hmat.c b/hw/acpi/hmat.c
new file mode 100644
index 0000000000..abf99b1adc
--- /dev/null
+++ b/hw/acpi/hmat.c
@@ -0,0 +1,101 @@
+/*
+ * HMAT ACPI Implementation
+ *
+ * Copyright(C) 2019 Intel Corporation.
+ *
+ * Author:
+ * Liu jingqi <jingqi.liu@linux.intel.com>
+ * Tao Xu <tao3.xu@intel.com>
+ *
+ * HMAT is defined in ACPI 6.3: 5.2.27 Heterogeneous Memory Attribute Table
+ * (HMAT)
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>
+ */
+
+#include "qemu/osdep.h"
+#include "sysemu/numa.h"
+#include "hw/acpi/hmat.h"
+
+/*
+ * ACPI 6.3:
+ * 5.2.27.3 Memory Proximity Domain Attributes Structure: Table 5-141
+ */
+static void build_hmat_mpda(GArray *table_data, uint16_t flags, int initiator,
+ int mem_node)
+{
+
+ /* Memory Proximity Domain Attributes Structure */
+ /* Type */
+ build_append_int_noprefix(table_data, 0, 2);
+ /* Reserved */
+ build_append_int_noprefix(table_data, 0, 2);
+ /* Length */
+ build_append_int_noprefix(table_data, 40, 4);
+ /* Flags */
+ build_append_int_noprefix(table_data, flags, 2);
+ /* Reserved */
+ build_append_int_noprefix(table_data, 0, 2);
+ /* Proximity Domain for the Attached Initiator */
+ build_append_int_noprefix(table_data, initiator, 4);
+ /* Proximity Domain for the Memory */
+ build_append_int_noprefix(table_data, mem_node, 4);
+ /* Reserved */
+ build_append_int_noprefix(table_data, 0, 4);
+ /*
+ * Reserved:
+ * Previously defined as the Start Address of the System Physical
+ * Address Range. Deprecated since ACPI Spec 6.3.
+ */
+ build_append_int_noprefix(table_data, 0, 8);
+ /*
+ * Reserved:
+ * Previously defined as the Range Length of the region in bytes.
+ * Deprecated since ACPI Spec 6.3.
+ */
+ build_append_int_noprefix(table_data, 0, 8);
+}
+
+/* Build HMAT sub table structures */
+static void hmat_build_table_structs(GArray *table_data, NumaState *nstat)
+{
+ uint16_t flags;
+ int i;
+
+ for (i = 0; i < nstat->num_nodes; i++) {
+ flags = 0;
+
+ if (nstat->nodes[i].initiator_valid) {
+ flags |= HMAT_PROX_INIT_VALID;
+ }
+
+ build_hmat_mpda(table_data, flags, nstat->nodes[i].initiator, i);
+ }
+}
+
+void build_hmat(GArray *table_data, BIOSLinker *linker, NumaState *nstat)
+{
+ uint64_t hmat_start;
+
+ hmat_start = table_data->len;
+
+ /* reserve space for HMAT header */
+ acpi_data_push(table_data, 40);
+
+ hmat_build_table_structs(table_data, nstat);
+
+ build_header(linker, table_data,
+ (void *)(table_data->data + hmat_start),
+ "HMAT", table_data->len - hmat_start, 2, NULL, NULL);
+}
diff --git a/hw/acpi/hmat.h b/hw/acpi/hmat.h
new file mode 100644
index 0000000000..574cfba60a
--- /dev/null
+++ b/hw/acpi/hmat.h
@@ -0,0 +1,45 @@
+/*
+ * HMAT ACPI Implementation Header
+ *
+ * Copyright(C) 2019 Intel Corporation.
+ *
+ * Author:
+ * Liu jingqi <jingqi.liu@linux.intel.com>
+ * Tao Xu <tao3.xu@intel.com>
+ *
+ * HMAT is defined in ACPI 6.3: 5.2.27 Heterogeneous Memory Attribute Table
+ * (HMAT)
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>
+ */
+
+#ifndef HMAT_H
+#define HMAT_H
+
+#include "hw/acpi/acpi-defs.h"
+#include "hw/acpi/acpi.h"
+#include "hw/acpi/bios-linker-loader.h"
+#include "hw/acpi/aml-build.h"
+
+/*
+ * ACPI 6.3: 5.2.27.3 Memory Proximity Domain Attributes Structure,
+ * Table 5-141, Field "flag", Bit [0]: set to 1 to indicate that data in
+ * the Proximity Domain for the Attached Initiator field is valid.
+ * Other bits reserved.
+ */
+#define HMAT_PROX_INIT_VALID 0x1
+
+void build_hmat(GArray *table_data, BIOSLinker *linker, NumaState *nstat);
+
+#endif
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 243c5b85c8..6eee709258 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -66,6 +66,7 @@
#include "hw/i386/intel_iommu.h"
#include "hw/acpi/ipmi.h"
+#include "hw/acpi/hmat.h"
/* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
* -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
@@ -2687,6 +2688,8 @@ void acpi_build(AcpiBuildTables *tables, MachineState *machine)
acpi_add_table(table_offsets, tables_blob);
build_slit(tables_blob, tables->linker, machine);
}
+ acpi_add_table(table_offsets, tables_blob);
+ build_hmat(tables_blob, tables->linker, machine->numa_state);
}
if (acpi_get_mcfg(&mcfg)) {
acpi_add_table(table_offsets, tables_blob);
--
2.20.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH RESEND v6 07/14] hmat acpi: Build System Locality Latency and Bandwidth Information Structure(s)
2019-07-09 7:15 [Qemu-devel] [PATCH RESEND v6 00/14] Build ACPI Heterogeneous Memory Attribute Table (HMAT) Tao Xu
` (5 preceding siblings ...)
2019-07-09 7:15 ` [Qemu-devel] [PATCH RESEND v6 06/14] hmat acpi: Build Memory Proximity Domain Attributes Structure(s) Tao Xu
@ 2019-07-09 7:15 ` Tao Xu
2019-07-09 7:15 ` [Qemu-devel] [PATCH RESEND v6 08/14] hmat acpi: Build Memory Side Cache " Tao Xu
` (8 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Tao Xu @ 2019-07-09 7:15 UTC (permalink / raw)
To: imammedo, eblake, ehabkost
Cc: jingqi.liu, tao3.xu, fan.du, qemu-devel, jonathan.cameron,
dan.j.williams
From: Liu Jingqi <jingqi.liu@intel.com>
This structure describes the memory access latency and bandwidth
information from various memory access initiator proximity domains.
The latency and bandwidth numbers represented in this structure
correspond to rated latency and bandwidth for the platform.
The software could use this information as hint for optimization.
Signed-off-by: Liu Jingqi <jingqi.liu@intel.com>
Signed-off-by: Tao Xu <tao3.xu@intel.com>
---
Changes in v6:
- Update the describes in ACPI 6.3
- remove num target and target_pxm, because all numa node can be
target(no matter it can be reached or not, The Entry Base Unit for
latency 0xFFFF means the initiator and target domains are
unreachable from each other)
---
hw/acpi/hmat.c | 94 ++++++++++++++++++++++++++++++++++++++++-
hw/acpi/hmat.h | 39 +++++++++++++++++
include/qemu/typedefs.h | 1 +
include/sysemu/numa.h | 3 ++
include/sysemu/sysemu.h | 22 ++++++++++
5 files changed, 158 insertions(+), 1 deletion(-)
diff --git a/hw/acpi/hmat.c b/hw/acpi/hmat.c
index abf99b1adc..6dd39b0c85 100644
--- a/hw/acpi/hmat.c
+++ b/hw/acpi/hmat.c
@@ -67,11 +67,80 @@ static void build_hmat_mpda(GArray *table_data, uint16_t flags, int initiator,
build_append_int_noprefix(table_data, 0, 8);
}
+/*
+ * ACPI 6.3: 5.2.27.4 System Locality Latency and Bandwidth Information
+ * Structure: Table 5-142
+ */
+static void build_hmat_lb(GArray *table_data, HMAT_LB_Info *numa_hmat_lb,
+ uint32_t num_initiator, uint32_t num_target,
+ uint32_t *initiator_pxm, int type)
+{
+ uint32_t s = num_initiator;
+ uint32_t t = num_target;
+ uint8_t m, n;
+ int i;
+
+ /* Type */
+ build_append_int_noprefix(table_data, 1, 2);
+ /* Reserved */
+ build_append_int_noprefix(table_data, 0, 2);
+ /* Length */
+ build_append_int_noprefix(table_data, 32 + 4 * s + 4 * t + 2 * s * t, 4);
+ /* Flags */
+ build_append_int_noprefix(table_data, numa_hmat_lb->hierarchy, 1);
+ /* Data Type */
+ build_append_int_noprefix(table_data, numa_hmat_lb->data_type, 1);
+ /* Reserved */
+ build_append_int_noprefix(table_data, 0, 2);
+ /* Number of Initiator Proximity Domains (s) */
+ build_append_int_noprefix(table_data, s, 4);
+ /* Number of Target Proximity Domains (t) */
+ build_append_int_noprefix(table_data, t, 4);
+ /* Reserved */
+ build_append_int_noprefix(table_data, 0, 4);
+
+ /* Entry Base Unit */
+ if (type <= HMAT_LB_DATA_WRITE_LATENCY) {
+ build_append_int_noprefix(table_data, numa_hmat_lb->base_lat, 8);
+ } else {
+ build_append_int_noprefix(table_data, numa_hmat_lb->base_bw, 8);
+ }
+
+ /* Initiator Proximity Domain List */
+ for (i = 0; i < s; i++) {
+ build_append_int_noprefix(table_data, initiator_pxm[i], 4);
+ }
+
+ /* Target Proximity Domain List */
+ for (i = 0; i < t; i++) {
+ build_append_int_noprefix(table_data, i, 4);
+ }
+
+ /* Latency or Bandwidth Entries */
+ for (i = 0; i < s; i++) {
+ m = initiator_pxm[i];
+ for (n = 0; n < t; n++) {
+ uint16_t entry;
+
+ if (type <= HMAT_LB_DATA_WRITE_LATENCY) {
+ entry = numa_hmat_lb->latency[m][n];
+ } else {
+ entry = numa_hmat_lb->bandwidth[m][n];
+ }
+
+ build_append_int_noprefix(table_data, entry, 2);
+ }
+ }
+}
+
/* Build HMAT sub table structures */
static void hmat_build_table_structs(GArray *table_data, NumaState *nstat)
{
uint16_t flags;
- int i;
+ uint32_t num_initiator = 0;
+ uint32_t initiator_pxm[MAX_NODES];
+ int i, hrchy, type;
+ HMAT_LB_Info *numa_hmat_lb;
for (i = 0; i < nstat->num_nodes; i++) {
flags = 0;
@@ -82,6 +151,29 @@ static void hmat_build_table_structs(GArray *table_data, NumaState *nstat)
build_hmat_mpda(table_data, flags, nstat->nodes[i].initiator, i);
}
+
+ for (i = 0; i < nstat->num_nodes; i++) {
+ if (nstat->nodes[i].has_cpu) {
+ initiator_pxm[num_initiator++] = i;
+ }
+ }
+
+ /*
+ * ACPI 6.3: 5.2.27.4 System Locality Latency and Bandwidth Information
+ * Structure: Table 5-142
+ */
+ for (hrchy = HMAT_LB_MEM_MEMORY;
+ hrchy <= HMAT_LB_MEM_CACHE_3RD_LEVEL; hrchy++) {
+ for (type = HMAT_LB_DATA_ACCESS_LATENCY;
+ type <= HMAT_LB_DATA_WRITE_BANDWIDTH; type++) {
+ numa_hmat_lb = nstat->hmat_lb[hrchy][type];
+
+ if (numa_hmat_lb) {
+ build_hmat_lb(table_data, numa_hmat_lb, num_initiator,
+ nstat->num_nodes, initiator_pxm, type);
+ }
+ }
+ }
}
void build_hmat(GArray *table_data, BIOSLinker *linker, NumaState *nstat)
diff --git a/hw/acpi/hmat.h b/hw/acpi/hmat.h
index 574cfba60a..9d5f407b8a 100644
--- a/hw/acpi/hmat.h
+++ b/hw/acpi/hmat.h
@@ -40,6 +40,45 @@
*/
#define HMAT_PROX_INIT_VALID 0x1
+struct HMAT_LB_Info {
+ /*
+ * Indicates total number of Proximity Domains
+ * that can initiate memory access requests.
+ */
+ uint32_t num_initiator;
+ /*
+ * Indicates total number of Proximity Domains
+ * that can act as target.
+ */
+ uint32_t num_target;
+ /*
+ * Indicates it's memory or
+ * the specified level memory side cache.
+ */
+ uint8_t hierarchy;
+ /*
+ * Present the type of data,
+ * access/read/write latency or bandwidth.
+ */
+ uint8_t data_type;
+ /* The base unit for latency in nanoseconds. */
+ uint64_t base_lat;
+ /* The base unit for bandwidth in megabytes per second(MB/s). */
+ uint64_t base_bw;
+ /*
+ * latency[i][j]:
+ * Indicates the latency based on base_lat
+ * from Initiator Proximity Domain i to Target Proximity Domain j.
+ */
+ uint16_t latency[MAX_NODES][MAX_NODES];
+ /*
+ * bandwidth[i][j]:
+ * Indicates the bandwidth based on base_bw
+ * from Initiator Proximity Domain i to Target Proximity Domain j.
+ */
+ uint16_t bandwidth[MAX_NODES][MAX_NODES];
+};
+
void build_hmat(GArray *table_data, BIOSLinker *linker, NumaState *nstat);
#endif
diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
index fcdaae58c4..c0257e936b 100644
--- a/include/qemu/typedefs.h
+++ b/include/qemu/typedefs.h
@@ -33,6 +33,7 @@ typedef struct FWCfgEntry FWCfgEntry;
typedef struct FWCfgIoState FWCfgIoState;
typedef struct FWCfgMemState FWCfgMemState;
typedef struct FWCfgState FWCfgState;
+typedef struct HMAT_LB_Info HMAT_LB_Info;
typedef struct HVFX86EmulatorState HVFX86EmulatorState;
typedef struct I2CBus I2CBus;
typedef struct I2SCodec I2SCodec;
diff --git a/include/sysemu/numa.h b/include/sysemu/numa.h
index 21232d775e..6b4037d1ca 100644
--- a/include/sysemu/numa.h
+++ b/include/sysemu/numa.h
@@ -32,6 +32,9 @@ struct NumaState {
/* NUMA nodes information */
NodeInfo nodes[MAX_NODES];
+
+ /* NUMA modes HMAT Locality Latency and Bandwidth Information */
+ HMAT_LB_Info *hmat_lb[HMAT_LB_LEVELS][HMAT_LB_TYPES];
};
typedef struct NumaState NumaState;
diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h
index 984c439ac9..b6649c37ed 100644
--- a/include/sysemu/sysemu.h
+++ b/include/sysemu/sysemu.h
@@ -126,6 +126,28 @@ extern int mem_prealloc;
#define NUMA_DISTANCE_MAX 254
#define NUMA_DISTANCE_UNREACHABLE 255
+/* the value of AcpiHmatLBInfo flags */
+enum {
+ HMAT_LB_MEM_MEMORY = 0,
+ HMAT_LB_MEM_CACHE_LAST_LEVEL = 1,
+ HMAT_LB_MEM_CACHE_1ST_LEVEL = 2,
+ HMAT_LB_MEM_CACHE_2ND_LEVEL = 3,
+ HMAT_LB_MEM_CACHE_3RD_LEVEL = 4,
+};
+
+/* the value of AcpiHmatLBInfo data type */
+enum {
+ HMAT_LB_DATA_ACCESS_LATENCY = 0,
+ HMAT_LB_DATA_READ_LATENCY = 1,
+ HMAT_LB_DATA_WRITE_LATENCY = 2,
+ HMAT_LB_DATA_ACCESS_BANDWIDTH = 3,
+ HMAT_LB_DATA_READ_BANDWIDTH = 4,
+ HMAT_LB_DATA_WRITE_BANDWIDTH = 5,
+};
+
+#define HMAT_LB_LEVELS (HMAT_LB_MEM_CACHE_3RD_LEVEL + 1)
+#define HMAT_LB_TYPES (HMAT_LB_DATA_WRITE_BANDWIDTH + 1)
+
#define MAX_OPTION_ROMS 16
typedef struct QEMUOptionRom {
const char *name;
--
2.20.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH RESEND v6 08/14] hmat acpi: Build Memory Side Cache Information Structure(s)
2019-07-09 7:15 [Qemu-devel] [PATCH RESEND v6 00/14] Build ACPI Heterogeneous Memory Attribute Table (HMAT) Tao Xu
` (6 preceding siblings ...)
2019-07-09 7:15 ` [Qemu-devel] [PATCH RESEND v6 07/14] hmat acpi: Build System Locality Latency and Bandwidth Information Structure(s) Tao Xu
@ 2019-07-09 7:15 ` Tao Xu
2019-07-09 7:15 ` [Qemu-devel] [PATCH RESEND v6 09/14] numa: Extend the CLI to provide memory latency and bandwidth information Tao Xu
` (7 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Tao Xu @ 2019-07-09 7:15 UTC (permalink / raw)
To: imammedo, eblake, ehabkost
Cc: jingqi.liu, tao3.xu, fan.du, qemu-devel, jonathan.cameron,
dan.j.williams
From: Liu Jingqi <jingqi.liu@intel.com>
This structure describes memory side cache information for memory
proximity domains if the memory side cache is present and the
physical device forms the memory side cache.
The software could use this information to effectively place
the data in memory to maximize the performance of the system
memory that use the memory side cache.
Signed-off-by: Liu Jingqi <jingqi.liu@intel.com>
Signed-off-by: Tao Xu <tao3.xu@intel.com>
---
Changes in v6:
- Add descriptions from ACPI 6.3 spec
---
hw/acpi/hmat.c | 64 ++++++++++++++++++++++++++++++++++++++++-
hw/acpi/hmat.h | 20 +++++++++++++
include/qemu/typedefs.h | 1 +
include/sysemu/numa.h | 3 ++
include/sysemu/sysemu.h | 2 ++
5 files changed, 89 insertions(+), 1 deletion(-)
diff --git a/hw/acpi/hmat.c b/hw/acpi/hmat.c
index 6dd39b0c85..a207581f11 100644
--- a/hw/acpi/hmat.c
+++ b/hw/acpi/hmat.c
@@ -133,14 +133,63 @@ static void build_hmat_lb(GArray *table_data, HMAT_LB_Info *numa_hmat_lb,
}
}
+/* ACPI 6.3: 5.2.27.5 Memory Side Cache Information Structure: Table 5-143 */
+static void build_hmat_cache(GArray *table_data, HMAT_Cache_Info *hmat_cache)
+{
+ /*
+ * Cache Attributes: Bits [3:0] – Total Cache Levels
+ * for this Memory Proximity Domain
+ */
+ uint32_t cache_attr = hmat_cache->total_levels & 0xF;
+
+ /* Bits [7:4] : Cache Level described in this structure */
+ cache_attr |= (hmat_cache->level & 0xF) << 4;
+
+ /* Bits [11:8] - Cache Associativity */
+ cache_attr |= (hmat_cache->associativity & 0xF) << 8;
+
+ /* Bits [15:12] - Write Policy */
+ cache_attr |= (hmat_cache->write_policy & 0xF) << 12;
+
+ /* Bits [31:16] - Cache Line size in bytes */
+ cache_attr |= (hmat_cache->line_size & 0xFFFF) << 16;
+
+ cache_attr = cpu_to_le32(cache_attr);
+
+ /* Type */
+ build_append_int_noprefix(table_data, 2, 2);
+ /* Reserved */
+ build_append_int_noprefix(table_data, 0, 2);
+ /* Length */
+ build_append_int_noprefix(table_data, 32, 4);
+ /* Proximity Domain for the Memory */
+ build_append_int_noprefix(table_data, hmat_cache->mem_proximity, 4);
+ /* Reserved */
+ build_append_int_noprefix(table_data, 0, 4);
+ /* Memory Side Cache Size */
+ build_append_int_noprefix(table_data, hmat_cache->size, 8);
+ /* Cache Attributes */
+ build_append_int_noprefix(table_data, cache_attr, 4);
+ /* Reserved */
+ build_append_int_noprefix(table_data, 0, 2);
+ /*
+ * Number of SMBIOS handles (n)
+ * Linux kernel uses Memory Side Cache Information Structure
+ * without SMBIOS entries for now, so set Number of SMBIOS handles
+ * as 0.
+ */
+ build_append_int_noprefix(table_data, 0, 2);
+}
+
/* Build HMAT sub table structures */
static void hmat_build_table_structs(GArray *table_data, NumaState *nstat)
{
uint16_t flags;
uint32_t num_initiator = 0;
uint32_t initiator_pxm[MAX_NODES];
- int i, hrchy, type;
+ int i, hrchy, type, level;
HMAT_LB_Info *numa_hmat_lb;
+ HMAT_Cache_Info *numa_hmat_cache;
for (i = 0; i < nstat->num_nodes; i++) {
flags = 0;
@@ -174,6 +223,19 @@ static void hmat_build_table_structs(GArray *table_data, NumaState *nstat)
}
}
}
+
+ /*
+ * ACPI 6.3: 5.2.27.5 Memory Side Cache Information Structure:
+ * Table 5-143
+ */
+ for (i = 0; i < nstat->num_nodes; i++) {
+ for (level = 0; level <= MAX_HMAT_CACHE_LEVEL; level++) {
+ numa_hmat_cache = nstat->hmat_cache[i][level];
+ if (numa_hmat_cache) {
+ build_hmat_cache(table_data, numa_hmat_cache);
+ }
+ }
+ }
}
void build_hmat(GArray *table_data, BIOSLinker *linker, NumaState *nstat)
diff --git a/hw/acpi/hmat.h b/hw/acpi/hmat.h
index 9d5f407b8a..ba655281cc 100644
--- a/hw/acpi/hmat.h
+++ b/hw/acpi/hmat.h
@@ -79,6 +79,26 @@ struct HMAT_LB_Info {
uint16_t bandwidth[MAX_NODES][MAX_NODES];
};
+struct HMAT_Cache_Info {
+ /* The memory proximity domain to which the memory belongs. */
+ uint32_t mem_proximity;
+ /* Size of memory side cache in bytes. */
+ uint64_t size;
+ /*
+ * Total cache levels for this memory
+ * pr#include "hw/acpi/aml-build.h"oximity domain.
+ */
+ uint8_t total_levels;
+ /* Cache level described in this structure. */
+ uint8_t level;
+ /* Cache Associativity: None/Direct Mapped/Comple Cache Indexing */
+ uint8_t associativity;
+ /* Write Policy: None/Write Back(WB)/Write Through(WT) */
+ uint8_t write_policy;
+ /* Cache Line size in bytes. */
+ uint16_t line_size;
+};
+
void build_hmat(GArray *table_data, BIOSLinker *linker, NumaState *nstat);
#endif
diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
index c0257e936b..d971f5109e 100644
--- a/include/qemu/typedefs.h
+++ b/include/qemu/typedefs.h
@@ -33,6 +33,7 @@ typedef struct FWCfgEntry FWCfgEntry;
typedef struct FWCfgIoState FWCfgIoState;
typedef struct FWCfgMemState FWCfgMemState;
typedef struct FWCfgState FWCfgState;
+typedef struct HMAT_Cache_Info HMAT_Cache_Info;
typedef struct HMAT_LB_Info HMAT_LB_Info;
typedef struct HVFX86EmulatorState HVFX86EmulatorState;
typedef struct I2CBus I2CBus;
diff --git a/include/sysemu/numa.h b/include/sysemu/numa.h
index 6b4037d1ca..6aecbdbdc7 100644
--- a/include/sysemu/numa.h
+++ b/include/sysemu/numa.h
@@ -35,6 +35,9 @@ struct NumaState {
/* NUMA modes HMAT Locality Latency and Bandwidth Information */
HMAT_LB_Info *hmat_lb[HMAT_LB_LEVELS][HMAT_LB_TYPES];
+
+ /* Memory Side Cache Information Structure */
+ HMAT_Cache_Info *hmat_cache[MAX_NODES][MAX_HMAT_CACHE_LEVEL + 1];
};
typedef struct NumaState NumaState;
diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h
index b6649c37ed..08925abeb8 100644
--- a/include/sysemu/sysemu.h
+++ b/include/sysemu/sysemu.h
@@ -145,6 +145,8 @@ enum {
HMAT_LB_DATA_WRITE_BANDWIDTH = 5,
};
+#define MAX_HMAT_CACHE_LEVEL 3
+
#define HMAT_LB_LEVELS (HMAT_LB_MEM_CACHE_3RD_LEVEL + 1)
#define HMAT_LB_TYPES (HMAT_LB_DATA_WRITE_BANDWIDTH + 1)
--
2.20.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH RESEND v6 09/14] numa: Extend the CLI to provide memory latency and bandwidth information
2019-07-09 7:15 [Qemu-devel] [PATCH RESEND v6 00/14] Build ACPI Heterogeneous Memory Attribute Table (HMAT) Tao Xu
` (7 preceding siblings ...)
2019-07-09 7:15 ` [Qemu-devel] [PATCH RESEND v6 08/14] hmat acpi: Build Memory Side Cache " Tao Xu
@ 2019-07-09 7:15 ` Tao Xu
2019-07-09 7:15 ` [Qemu-devel] [PATCH RESEND v6 10/14] numa: Extend the CLI to provide memory side cache information Tao Xu
` (6 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Tao Xu @ 2019-07-09 7:15 UTC (permalink / raw)
To: imammedo, eblake, ehabkost
Cc: jingqi.liu, tao3.xu, fan.du, qemu-devel, jonathan.cameron,
dan.j.williams
From: Liu Jingqi <jingqi.liu@intel.com>
Add -numa hmat-lb option to provide System Locality Latency and
Bandwidth Information. These memory attributes help to build
System Locality Latency and Bandwidth Information Structure(s)
in ACPI Heterogeneous Memory Attribute Table (HMAT).
Signed-off-by: Liu Jingqi <jingqi.liu@intel.com>
Signed-off-by: Tao Xu <tao3.xu@intel.com>
---
Changes in v6:
- Update the describes in ACPI 6.3(The entry base unit for latency is
in picoseconds)
- Update the designator to 4.2 (Eric)
---
hw/core/numa.c | 127 ++++++++++++++++++++++++++++++++++++++++++
include/sysemu/numa.h | 2 +
qapi/machine.json | 103 +++++++++++++++++++++++++++++++++-
qemu-options.hx | 45 ++++++++++++++-
4 files changed, 274 insertions(+), 3 deletions(-)
diff --git a/hw/core/numa.c b/hw/core/numa.c
index cfb6339810..83ead77191 100644
--- a/hw/core/numa.c
+++ b/hw/core/numa.c
@@ -37,6 +37,7 @@
#include "qemu/option.h"
#include "qemu/config-file.h"
#include "qemu/cutils.h"
+#include "hw/acpi/hmat.h"
QemuOptsList qemu_numa_opts = {
.name = "numa",
@@ -183,6 +184,126 @@ void parse_numa_distance(MachineState *ms, NumaDistOptions *dist, Error **errp)
ms->numa_state->have_numa_distance = true;
}
+void parse_numa_hmat_lb(MachineState *ms, NumaHmatLBOptions *node,
+ Error **errp)
+{
+ int nb_numa_nodes = ms->numa_state->num_nodes;
+ NodeInfo *numa_info = ms->numa_state->nodes;
+ HMAT_LB_Info *hmat_lb = NULL;
+
+ if (node->data_type <= HMATLB_DATA_TYPE_WRITE_LATENCY) {
+ if (!node->has_latency) {
+ error_setg(errp, "Missing 'latency' option.");
+ return;
+ }
+ if (node->has_bandwidth) {
+ error_setg(errp, "Invalid option 'bandwidth' since "
+ "the data type is latency.");
+ return;
+ }
+ if (node->has_base_bw) {
+ error_setg(errp, "Invalid option 'base_bw' since "
+ "the data type is latency.");
+ return;
+ }
+ }
+
+ if (node->data_type >= HMATLB_DATA_TYPE_ACCESS_BANDWIDTH) {
+ if (!node->has_bandwidth) {
+ error_setg(errp, "Missing 'bandwidth' option.");
+ return;
+ }
+ if (node->has_latency) {
+ error_setg(errp, "Invalid option 'latency' since "
+ "the data type is bandwidth.");
+ return;
+ }
+ if (node->has_base_lat) {
+ error_setg(errp, "Invalid option 'base_lat' since "
+ "the data type is bandwidth.");
+ return;
+ }
+ }
+
+ if (node->initiator >= nb_numa_nodes) {
+ error_setg(errp, "Invalid initiator=%"
+ PRIu16 ", it should be less than %d.",
+ node->initiator, nb_numa_nodes);
+ return;
+ }
+ if (!numa_info[node->initiator].has_cpu) {
+ error_setg(errp, "Invalid initiator=%"
+ PRIu16 ", it isn't an initiator proximity domain.",
+ node->initiator);
+ return;
+ }
+
+ if (node->target >= nb_numa_nodes) {
+ error_setg(errp, "Invalid target=%"
+ PRIu16 ", it should be less than %d.",
+ node->target, nb_numa_nodes);
+ return;
+ }
+ if (!numa_info[node->target].initiator_valid) {
+ error_setg(errp, "Invalid target=%"
+ PRIu16 ", it hasn't a valid initiator proximity domain.",
+ node->target);
+ return;
+ }
+
+ if (node->has_latency) {
+ hmat_lb = ms->numa_state->hmat_lb[node->hierarchy][node->data_type];
+
+ if (!hmat_lb) {
+ hmat_lb = g_malloc0(sizeof(*hmat_lb));
+ ms->numa_state->hmat_lb[node->hierarchy][node->data_type] = hmat_lb;
+ } else if (hmat_lb->latency[node->initiator][node->target]) {
+ error_setg(errp, "Duplicate configuration of the latency for "
+ "initiator=%" PRIu16 " and target=%" PRIu16 ".",
+ node->initiator, node->target);
+ return;
+ }
+
+ /* Only the first time of setting the base unit is valid. */
+ if ((hmat_lb->base_lat == 0) && (node->has_base_lat)) {
+ hmat_lb->base_lat = node->base_lat;
+ }
+
+ hmat_lb->latency[node->initiator][node->target] = node->latency;
+ }
+
+ if (node->has_bandwidth) {
+ hmat_lb = ms->numa_state->hmat_lb[node->hierarchy][node->data_type];
+
+ if (!hmat_lb) {
+ hmat_lb = g_malloc0(sizeof(*hmat_lb));
+ ms->numa_state->hmat_lb[node->hierarchy][node->data_type] = hmat_lb;
+ } else if (hmat_lb->bandwidth[node->initiator][node->target]) {
+ error_setg(errp, "Duplicate configuration of the bandwidth for "
+ "initiator=%" PRIu16 " and target=%" PRIu16 ".",
+ node->initiator, node->target);
+ return;
+ }
+
+ /* Only the first time of setting the base unit is valid. */
+ if (hmat_lb->base_bw == 0) {
+ if (!node->has_base_bw) {
+ error_setg(errp, "Missing 'base-bw' option");
+ return;
+ } else {
+ hmat_lb->base_bw = node->base_bw;
+ }
+ }
+
+ hmat_lb->bandwidth[node->initiator][node->target] = node->bandwidth;
+ }
+
+ if (hmat_lb) {
+ hmat_lb->hierarchy = node->hierarchy;
+ hmat_lb->data_type = node->data_type;
+ }
+}
+
void set_numa_options(MachineState *ms, NumaOptions *object, Error **errp)
{
Error *err = NULL;
@@ -221,6 +342,12 @@ void set_numa_options(MachineState *ms, NumaOptions *object, Error **errp)
machine_set_cpu_numa_node(ms, qapi_NumaCpuOptions_base(&object->u.cpu),
&err);
break;
+ case NUMA_OPTIONS_TYPE_HMAT_LB:
+ parse_numa_hmat_lb(ms, &object->u.hmat_lb, &err);
+ if (err) {
+ goto end;
+ }
+ break;
default:
abort();
}
diff --git a/include/sysemu/numa.h b/include/sysemu/numa.h
index 6aecbdbdc7..9aa5ea9add 100644
--- a/include/sysemu/numa.h
+++ b/include/sysemu/numa.h
@@ -43,6 +43,8 @@ typedef struct NumaState NumaState;
void set_numa_options(MachineState *ms, NumaOptions *object, Error **errp);
void parse_numa_opts(MachineState *ms);
+void parse_numa_hmat_lb(MachineState *ms, NumaHmatLBOptions *node,
+ Error **errp);
void numa_complete_configuration(MachineState *ms);
void query_numa_node_mem(NumaNodeMem node_mem[], MachineState *ms);
extern QemuOptsList qemu_numa_opts;
diff --git a/qapi/machine.json b/qapi/machine.json
index 05e367d26a..541834f358 100644
--- a/qapi/machine.json
+++ b/qapi/machine.json
@@ -377,10 +377,12 @@
#
# @cpu: property based CPU(s) to node mapping (Since: 2.10)
#
+# @hmat-lb: memory latency and bandwidth information (Since: 4.2)
+#
# Since: 2.1
##
{ 'enum': 'NumaOptionsType',
- 'data': [ 'node', 'dist', 'cpu' ] }
+ 'data': [ 'node', 'dist', 'cpu', 'hmat-lb' ] }
##
# @NumaOptions:
@@ -395,7 +397,8 @@
'data': {
'node': 'NumaNodeOptions',
'dist': 'NumaDistOptions',
- 'cpu': 'NumaCpuOptions' }}
+ 'cpu': 'NumaCpuOptions',
+ 'hmat-lb': 'NumaHmatLBOptions' }}
##
# @NumaNodeOptions:
@@ -504,6 +507,102 @@
'base': 'CpuInstanceProperties',
'data' : {} }
+##
+# @HmatLBMemoryHierarchy:
+#
+# The memory hierarchy in the System Locality Latency
+# and Bandwidth Information Structure of HMAT (Heterogeneous
+# Memory Attribute Table)
+#
+# For more information of @HmatLBMemoryHierarchy see
+# the chapter 5.2.27.4: Table 5-142: Field "Flags" of ACPI 6.3 spec.
+#
+# @memory: the structure represents the memory performance
+#
+# @last-level: last level memory of memory side cached memory
+#
+# @first-level: first level memory of memory side cached memory
+#
+# @second-level: second level memory of memory side cached memory
+#
+# @third-level: third level memory of memory side cached memory
+#
+# Since: 4.2
+##
+{ 'enum': 'HmatLBMemoryHierarchy',
+ 'data': [ 'memory', 'last-level', 'first-level',
+ 'second-level', 'third-level' ] }
+
+##
+# @HmatLBDataType:
+#
+# Data type in the System Locality Latency
+# and Bandwidth Information Structure of HMAT (Heterogeneous
+# Memory Attribute Table)
+#
+# For more information of @HmatLBDataType see
+# the chapter 5.2.27.4: Table 5-142: Field "Data Type" of ACPI 6.3 spec.
+#
+# @access-latency: access latency (picoseconds)
+#
+# @read-latency: read latency (picoseconds)
+#
+# @write-latency: write latency (picoseconds)
+#
+# @access-bandwidth: access bandwidth (MB/s)
+#
+# @read-bandwidth: read bandwidth (MB/s)
+#
+# @write-bandwidth: write bandwidth (MB/s)
+#
+# Since: 4.2
+##
+{ 'enum': 'HmatLBDataType',
+ 'data': [ 'access-latency', 'read-latency', 'write-latency',
+ 'access-bandwidth', 'read-bandwidth', 'write-bandwidth' ] }
+
+##
+# @NumaHmatLBOptions:
+#
+# Set the system locality latency and bandwidth information
+# between Initiator and Target proximity Domains.
+#
+# For more information of @NumaHmatLBOptions see
+# the chapter 5.2.27.4: Table 5-142 of ACPI 6.3 spec.
+#
+# @initiator: the Initiator Proximity Domain.
+#
+# @target: the Target Proximity Domain.
+#
+# @hierarchy: the Memory Hierarchy. Indicates the performance
+# of memory or side cache.
+#
+# @data-type: presents the type of data, access/read/write
+# latency or hit latency.
+#
+# @base-lat: the base unit for latency in picoseconds.
+#
+# @base-bw: the base unit for bandwidth in megabytes per second(MB/s).
+#
+# @latency: the value of latency based on Base Unit from @initiator
+# to @target proximity domain.
+#
+# @bandwidth: the value of bandwidth based on Base Unit between
+# @initiator and @target proximity domain.
+#
+# Since: 4.2
+##
+{ 'struct': 'NumaHmatLBOptions',
+ 'data': {
+ 'initiator': 'uint16',
+ 'target': 'uint16',
+ 'hierarchy': 'HmatLBMemoryHierarchy',
+ 'data-type': 'HmatLBDataType',
+ '*base-lat': 'uint64',
+ '*base-bw': 'uint64',
+ '*latency': 'uint16',
+ '*bandwidth': 'uint16' }}
+
##
# @HostMemPolicy:
#
diff --git a/qemu-options.hx b/qemu-options.hx
index c480781992..ae8d4c5c0e 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -164,16 +164,19 @@ DEF("numa", HAS_ARG, QEMU_OPTION_numa,
"-numa node[,mem=size][,cpus=firstcpu[-lastcpu]][,nodeid=node][,initiator=node]\n"
"-numa node[,memdev=id][,cpus=firstcpu[-lastcpu]][,nodeid=node][,initiator=node]\n"
"-numa dist,src=source,dst=destination,val=distance\n"
- "-numa cpu,node-id=node[,socket-id=x][,core-id=y][,thread-id=z]\n",
+ "-numa cpu,node-id=node[,socket-id=x][,core-id=y][,thread-id=z]\n"
+ "-numa hmat-lb,initiator=node,target=node,hierarchy=memory|last-level|first-level|second-level|third-level,data-type=access-latency|read-latency|write-latency[,base-lat=blat][,base-bw=bbw][,latency=lat][,bandwidth=bw]\n",
QEMU_ARCH_ALL)
STEXI
@item -numa node[,mem=@var{size}][,cpus=@var{firstcpu}[-@var{lastcpu}]][,nodeid=@var{node}][,initiator=@var{initiator}]
@itemx -numa node[,memdev=@var{id}][,cpus=@var{firstcpu}[-@var{lastcpu}]][,nodeid=@var{node}][,initiator=@var{initiator}]
@itemx -numa dist,src=@var{source},dst=@var{destination},val=@var{distance}
@itemx -numa cpu,node-id=@var{node}[,socket-id=@var{x}][,core-id=@var{y}][,thread-id=@var{z}]
+@itemx -numa hmat-lb,initiator=@var{node},target=@var{node},hierarchy=@var{str},data-type=@var{str}[,base-lat=@var{blat}][,base-bw=@var{bbw}][,latency=@var{lat}][,bandwidth=@var{bw}]
@findex -numa
Define a NUMA node and assign RAM and VCPUs to it.
Set the NUMA distance from a source node to a destination node.
+Set the ACPI Heterogeneous Memory Attributes for the given nodes.
Legacy VCPU assignment uses @samp{cpus} option where
@var{firstcpu} and @var{lastcpu} are CPU indexes. Each
@@ -250,6 +253,46 @@ specified resources, it just assigns existing resources to NUMA
nodes. This means that one still has to use the @option{-m},
@option{-smp} options to allocate RAM and VCPUs respectively.
+Use @samp{hmat-lb} to set System Locality Latency and Bandwidth Information
+between initiator and target NUMA nodes in ACPI Heterogeneous Attribute Memory Table (HMAT).
+Initiator NUMA node can create memory requests, usually including one or more processors.
+Target NUMA node contains addressable memory.
+[,base-lat=@var{blat}][,base-bw=@var{bbw}][,latency=@var{lat}][,bandwidth=@var{bw}]
+
+In @samp{hmat-lb} option, @var{node} are NUMA node IDs. @var{str} of 'hierarchy'
+is the memory hierarchy of the target NUMA node: if @var{str} is 'memory', the structure
+represents the memory performance; if @var{str} is 'last-level|first-level|second-level|third-level',
+this structure represents aggregated performance of memory side caches for each domain.
+@var{str} of 'data-type' is type of data represented by this structure instance:
+if 'hierarchy' is 'memory', 'data-type' is 'access|read|write' latency(picoseconds)
+or 'access|read|write' bandwidth(MB/s) of the target memory; if 'hierarchy' is
+'last-level|first-level|second-level|third-level', 'data-type' is 'access|read|write' hit latency(picoseconds)
+or 'access|read|write' hit bandwidth of the target memory side cache. @var{blat}
+or @var{bbw} is Matrix Entry Values(latency or bandwidth) base unit used for normalizing
+the matrix entry values(which store the latency or bandwidth values). Base unit
+for latency in picoseconds. Base unit for bandwidth in megabytes per second(MB/s).
+Note: Due to the minimum matrix value entry value being 10, the base unit corresponds
+to a value of 10. And @var{blat} or @var{bbw} should be an integer. @var{lat} or
+@var{bw} is the latency/bandwidth value.
+
+For example, the following option assigns NUMA node 0 and 1. Node 0 has 2 cpus and
+a ram, node 1 has only a ram. The processors in node 0 access memory in node
+0 with access-latency 5 picoseconds(base latency is 10), access-bandwidth 5 MB/s(base latency is 20);
+The processors in NUMA node 0 access memory in NUMA node 1 with access-latency 10
+picoseconds(base latency is 10), access-bandwidth 10 MB/s(base latency is 20):
+@example
+-m 2G \
+-object memory-backend-ram,size=1024M,policy=bind,host-nodes=0,id=ram-node0 -numa node,nodeid=0,memdev=ram-node0 \
+-object memory-backend-ram,size=1024M,policy=bind,host-nodes=1,id=ram-node1 -numa node,nodeid=1,memdev=ram-node1 \
+-smp 2 \
+-numa cpu,node-id=0,socket-id=0 \
+-numa cpu,node-id=0,socket-id=1 \
+-numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-latency,base-lat=10,latency=5 \
+-numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=5 \
+-numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-latency,base-lat=10,latency=10 \
+-numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=10 \
+@end example
+
ETEXI
DEF("add-fd", HAS_ARG, QEMU_OPTION_add_fd,
--
2.20.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH RESEND v6 10/14] numa: Extend the CLI to provide memory side cache information
2019-07-09 7:15 [Qemu-devel] [PATCH RESEND v6 00/14] Build ACPI Heterogeneous Memory Attribute Table (HMAT) Tao Xu
` (8 preceding siblings ...)
2019-07-09 7:15 ` [Qemu-devel] [PATCH RESEND v6 09/14] numa: Extend the CLI to provide memory latency and bandwidth information Tao Xu
@ 2019-07-09 7:15 ` Tao Xu
2019-07-09 7:15 ` [Qemu-devel] [PATCH RESEND v6 11/14] acpi: introduce aml_build_runtime_buf for NFIT generalizations Tao Xu
` (5 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Tao Xu @ 2019-07-09 7:15 UTC (permalink / raw)
To: imammedo, eblake, ehabkost
Cc: jingqi.liu, tao3.xu, fan.du, qemu-devel, jonathan.cameron,
dan.j.williams
From: Liu Jingqi <jingqi.liu@intel.com>
Add -numa hmat-cache option to provide Memory Side Cache Information.
These memory attributes help to build Memory Side Cache Information
Structure(s) in ACPI Heterogeneous Memory Attribute Table (HMAT).
Signed-off-by: Liu Jingqi <jingqi.liu@intel.com>
Signed-off-by: Tao Xu <tao3.xu@intel.com>
---
Changes in v6:
- Add add reference to ACPI 6.3 spec (Igor)
- Update the designator to 4.2 (Eric)
---
hw/core/numa.c | 67 +++++++++++++++++++++++++++++++++++
include/sysemu/numa.h | 2 ++
qapi/machine.json | 81 +++++++++++++++++++++++++++++++++++++++++--
qemu-options.hx | 16 +++++++--
4 files changed, 162 insertions(+), 4 deletions(-)
diff --git a/hw/core/numa.c b/hw/core/numa.c
index 83ead77191..75db35ac19 100644
--- a/hw/core/numa.c
+++ b/hw/core/numa.c
@@ -304,6 +304,67 @@ void parse_numa_hmat_lb(MachineState *ms, NumaHmatLBOptions *node,
}
}
+void parse_numa_hmat_cache(MachineState *ms, NumaHmatCacheOptions *node,
+ Error **errp)
+{
+ int nb_numa_nodes = ms->numa_state->num_nodes;
+ HMAT_Cache_Info *hmat_cache = NULL;
+
+ if (node->node_id >= nb_numa_nodes) {
+ error_setg(errp, "Invalid node-id=%" PRIu32
+ ", it should be less than %d.",
+ node->node_id, nb_numa_nodes);
+ return;
+ }
+
+ if (node->total > MAX_HMAT_CACHE_LEVEL) {
+ error_setg(errp, "Invalid total=%" PRIu8
+ ", it should be less than or equal to %d.",
+ node->total, MAX_HMAT_CACHE_LEVEL);
+ return;
+ }
+ if (node->level > node->total) {
+ error_setg(errp, "Invalid level=%" PRIu8
+ ", it should be less than or equal to"
+ " total=%" PRIu8 ".",
+ node->level, node->total);
+ return;
+ }
+ if (ms->numa_state->hmat_cache[node->node_id][node->level]) {
+ error_setg(errp, "Duplicate configuration of the side cache for "
+ "node-id=%" PRIu32 " and level=%" PRIu8 ".",
+ node->node_id, node->level);
+ return;
+ }
+
+ if ((node->level > 1) &&
+ ms->numa_state->hmat_cache[node->node_id][node->level - 1] &&
+ (node->size >=
+ ms->numa_state->hmat_cache[node->node_id][node->level - 1]->size)) {
+ error_setg(errp, "Invalid size=0x%" PRIx64
+ ", the size of level=%" PRIu8
+ " should be less than the size(0x%" PRIx64
+ ") of level=%" PRIu8 ".",
+ node->size, node->level,
+ ms->numa_state->hmat_cache[node->node_id]
+ [node->level - 1]->size,
+ node->level - 1);
+ return;
+ }
+
+ hmat_cache = g_malloc0(sizeof(*hmat_cache));
+
+ hmat_cache->mem_proximity = node->node_id;
+ hmat_cache->size = node->size;
+ hmat_cache->total_levels = node->total;
+ hmat_cache->level = node->level;
+ hmat_cache->associativity = node->assoc;
+ hmat_cache->write_policy = node->policy;
+ hmat_cache->line_size = node->line;
+
+ ms->numa_state->hmat_cache[node->node_id][node->level] = hmat_cache;
+}
+
void set_numa_options(MachineState *ms, NumaOptions *object, Error **errp)
{
Error *err = NULL;
@@ -348,6 +409,12 @@ void set_numa_options(MachineState *ms, NumaOptions *object, Error **errp)
goto end;
}
break;
+ case NUMA_OPTIONS_TYPE_HMAT_CACHE:
+ parse_numa_hmat_cache(ms, &object->u.hmat_cache, &err);
+ if (err) {
+ goto end;
+ }
+ break;
default:
abort();
}
diff --git a/include/sysemu/numa.h b/include/sysemu/numa.h
index 9aa5ea9add..3649262918 100644
--- a/include/sysemu/numa.h
+++ b/include/sysemu/numa.h
@@ -45,6 +45,8 @@ void set_numa_options(MachineState *ms, NumaOptions *object, Error **errp);
void parse_numa_opts(MachineState *ms);
void parse_numa_hmat_lb(MachineState *ms, NumaHmatLBOptions *node,
Error **errp);
+void parse_numa_hmat_cache(MachineState *ms, NumaHmatCacheOptions *node,
+ Error **errp);
void numa_complete_configuration(MachineState *ms);
void query_numa_node_mem(NumaNodeMem node_mem[], MachineState *ms);
extern QemuOptsList qemu_numa_opts;
diff --git a/qapi/machine.json b/qapi/machine.json
index 541834f358..b0d42cff21 100644
--- a/qapi/machine.json
+++ b/qapi/machine.json
@@ -379,10 +379,12 @@
#
# @hmat-lb: memory latency and bandwidth information (Since: 4.2)
#
+# @hmat-cache: memory side cache information (Since: 4.2)
+#
# Since: 2.1
##
{ 'enum': 'NumaOptionsType',
- 'data': [ 'node', 'dist', 'cpu', 'hmat-lb' ] }
+ 'data': [ 'node', 'dist', 'cpu', 'hmat-lb', 'hmat-cache' ] }
##
# @NumaOptions:
@@ -398,7 +400,8 @@
'node': 'NumaNodeOptions',
'dist': 'NumaDistOptions',
'cpu': 'NumaCpuOptions',
- 'hmat-lb': 'NumaHmatLBOptions' }}
+ 'hmat-lb': 'NumaHmatLBOptions',
+ 'hmat-cache': 'NumaHmatCacheOptions' }}
##
# @NumaNodeOptions:
@@ -603,6 +606,80 @@
'*latency': 'uint16',
'*bandwidth': 'uint16' }}
+##
+# @HmatCacheAssociativity:
+#
+# Cache associativity in the Memory Side Cache
+# Information Structure of HMAT
+#
+# For more information of @HmatCacheAssociativity see
+# the chapter 5.2.27.5: Table 5-143 of ACPI 6.3 spec.
+#
+# @none: None
+#
+# @direct: Direct Mapped
+#
+# @complex: Complex Cache Indexing (implementation specific)
+#
+# Since: 4.2
+##
+{ 'enum': 'HmatCacheAssociativity',
+ 'data': [ 'none', 'direct', 'complex' ] }
+
+##
+# @HmatCacheWritePolicy:
+#
+# Cache write policy in the Memory Side Cache
+# Information Structure of HMAT
+#
+# For more information of @HmatCacheWritePolicy see
+# the chapter 5.2.27.5: Table 5-143: Field "Cache Attributes" of ACPI 6.3 spec.
+#
+# @none: None
+#
+# @write-back: Write Back (WB)
+#
+# @write-through: Write Through (WT)
+#
+# Since: 4.2
+##
+{ 'enum': 'HmatCacheWritePolicy',
+ 'data': [ 'none', 'write-back', 'write-through' ] }
+
+##
+# @NumaHmatCacheOptions:
+#
+# Set the memory side cache information for a given memory domain.
+#
+# For more information of @NumaHmatCacheOptions see
+# the chapter 5.2.27.5: Table 5-143: Field "Cache Attributes" of ACPI 6.3 spec.
+#
+# @node-id: the memory proximity domain to which the memory belongs.
+#
+# @size: the size of memory side cache in bytes.
+#
+# @total: the total cache levels for this memory proximity domain.
+#
+# @level: the cache level described in this structure.
+#
+# @assoc: the cache associativity, none/direct-mapped/complex(complex cache indexing).
+#
+# @policy: the write policy, none/write-back/write-through.
+#
+# @line: the cache Line size in bytes.
+#
+# Since: 4.2
+##
+{ 'struct': 'NumaHmatCacheOptions',
+ 'data': {
+ 'node-id': 'uint32',
+ 'size': 'size',
+ 'total': 'uint8',
+ 'level': 'uint8',
+ 'assoc': 'HmatCacheAssociativity',
+ 'policy': 'HmatCacheWritePolicy',
+ 'line': 'uint16' }}
+
##
# @HostMemPolicy:
#
diff --git a/qemu-options.hx b/qemu-options.hx
index ae8d4c5c0e..09be7e3708 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -165,7 +165,8 @@ DEF("numa", HAS_ARG, QEMU_OPTION_numa,
"-numa node[,memdev=id][,cpus=firstcpu[-lastcpu]][,nodeid=node][,initiator=node]\n"
"-numa dist,src=source,dst=destination,val=distance\n"
"-numa cpu,node-id=node[,socket-id=x][,core-id=y][,thread-id=z]\n"
- "-numa hmat-lb,initiator=node,target=node,hierarchy=memory|last-level|first-level|second-level|third-level,data-type=access-latency|read-latency|write-latency[,base-lat=blat][,base-bw=bbw][,latency=lat][,bandwidth=bw]\n",
+ "-numa hmat-lb,initiator=node,target=node,hierarchy=memory|last-level|first-level|second-level|third-level,data-type=access-latency|read-latency|write-latency[,base-lat=blat][,base-bw=bbw][,latency=lat][,bandwidth=bw]\n"
+ "-numa hmat-cache,node-id=node,size=size,total=total,level=level[,assoc=none|direct|complex][,policy=none|write-back|write-through][,line=size]\n",
QEMU_ARCH_ALL)
STEXI
@item -numa node[,mem=@var{size}][,cpus=@var{firstcpu}[-@var{lastcpu}]][,nodeid=@var{node}][,initiator=@var{initiator}]
@@ -173,6 +174,7 @@ STEXI
@itemx -numa dist,src=@var{source},dst=@var{destination},val=@var{distance}
@itemx -numa cpu,node-id=@var{node}[,socket-id=@var{x}][,core-id=@var{y}][,thread-id=@var{z}]
@itemx -numa hmat-lb,initiator=@var{node},target=@var{node},hierarchy=@var{str},data-type=@var{str}[,base-lat=@var{blat}][,base-bw=@var{bbw}][,latency=@var{lat}][,bandwidth=@var{bw}]
+@itemx -numa hmat-cache,node-id=@var{node},size=@var{size},total=@var{total},level=@var{level}[,assoc=@var{str}][,policy=@var{str}][,line=@var{size}]
@findex -numa
Define a NUMA node and assign RAM and VCPUs to it.
Set the NUMA distance from a source node to a destination node.
@@ -275,11 +277,19 @@ Note: Due to the minimum matrix value entry value being 10, the base unit corres
to a value of 10. And @var{blat} or @var{bbw} should be an integer. @var{lat} or
@var{bw} is the latency/bandwidth value.
+In @samp{hmat-cache} option, @var{node-id} is the NUMA-id of the memory belongs.
+@var{size} is the size of memory side cache in bytes. @var{total} is the total cache levels.
+@var{level} is the cache level described in this structure. @var{assoc} is the cache associativity.
+"none/direct-mapped/complex(complex cache indexing). @var{policy} is the write policy.
+@var{line} is the cache Line size in bytes.
+
For example, the following option assigns NUMA node 0 and 1. Node 0 has 2 cpus and
a ram, node 1 has only a ram. The processors in node 0 access memory in node
0 with access-latency 5 picoseconds(base latency is 10), access-bandwidth 5 MB/s(base latency is 20);
The processors in NUMA node 0 access memory in NUMA node 1 with access-latency 10
-picoseconds(base latency is 10), access-bandwidth 10 MB/s(base latency is 20):
+picoseconds(base latency is 10), access-bandwidth 10 MB/s(base latency is 20).
+And for memory side cache information, NUMA node 0 and 1 both have 1 level memory
+cache, size is 0x20000 bytes, policy is write-back, the cache Line size is 8 bytes:
@example
-m 2G \
-object memory-backend-ram,size=1024M,policy=bind,host-nodes=0,id=ram-node0 -numa node,nodeid=0,memdev=ram-node0 \
@@ -291,6 +301,8 @@ picoseconds(base latency is 10), access-bandwidth 10 MB/s(base latency is 20):
-numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=5 \
-numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-latency,base-lat=10,latency=10 \
-numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=10 \
+-numa hmat-cache,node-id=0,size=0x20000,total=1,level=1,assoc=direct,policy=write-back,line=8 \
+-numa hmat-cache,node-id=1,size=0x20000,total=1,level=1,assoc=direct,policy=write-back,line=8 \
@end example
ETEXI
--
2.20.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH RESEND v6 11/14] acpi: introduce aml_build_runtime_buf for NFIT generalizations
2019-07-09 7:15 [Qemu-devel] [PATCH RESEND v6 00/14] Build ACPI Heterogeneous Memory Attribute Table (HMAT) Tao Xu
` (9 preceding siblings ...)
2019-07-09 7:15 ` [Qemu-devel] [PATCH RESEND v6 10/14] numa: Extend the CLI to provide memory side cache information Tao Xu
@ 2019-07-09 7:15 ` Tao Xu
2019-07-09 7:15 ` [Qemu-devel] [PATCH RESEND v6 12/14] hmat acpi: Implement _HMA method to update HMAT at runtime Tao Xu
` (4 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Tao Xu @ 2019-07-09 7:15 UTC (permalink / raw)
To: imammedo, eblake, ehabkost
Cc: jingqi.liu, tao3.xu, fan.du, qemu-devel, jonathan.cameron,
dan.j.williams
Move the _FIT method buff Aml-build codes into
aml_build_runtime_buf(), and then NFIT and HMAT can both use it.
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Tao Xu <tao3.xu@intel.com>
---
Changes in v6:
- Add more commit message and change the function name
---
hw/acpi/nvdimm.c | 49 +++++++++++++++++++++++++++--------------
include/hw/mem/nvdimm.h | 6 +++++
2 files changed, 38 insertions(+), 17 deletions(-)
diff --git a/hw/acpi/nvdimm.c b/hw/acpi/nvdimm.c
index 9fdad6dc3f..0eb57245d3 100644
--- a/hw/acpi/nvdimm.c
+++ b/hw/acpi/nvdimm.c
@@ -1140,12 +1140,11 @@ static void nvdimm_build_device_dsm(Aml *dev, uint32_t handle)
static void nvdimm_build_fit(Aml *dev)
{
- Aml *method, *pkg, *buf, *buf_size, *offset, *call_result;
- Aml *whilectx, *ifcond, *ifctx, *elsectx, *fit;
+ Aml *method, *pkg, *buf, *buf_name, *buf_size, *call_result;
buf = aml_local(0);
buf_size = aml_local(1);
- fit = aml_local(2);
+ buf_name = aml_local(2);
aml_append(dev, aml_name_decl(NVDIMM_DSM_RFIT_STATUS, aml_int(0)));
@@ -1164,6 +1163,22 @@ static void nvdimm_build_fit(Aml *dev)
aml_int(1) /* Revision 1 */,
aml_int(0x1) /* Read FIT */,
pkg, aml_int(NVDIMM_QEMU_RSVD_HANDLE_ROOT));
+
+ aml_build_runtime_buf(method, buf, buf_size,
+ call_result, buf_name, dev,
+ "RFIT", "_FIT",
+ NVDIMM_DSM_RET_STATUS_SUCCESS,
+ NVDIMM_DSM_RET_STATUS_FIT_CHANGED);
+}
+
+void aml_build_runtime_buf(Aml *method, Aml *buf, Aml *buf_size,
+ Aml *call_result, Aml *buf_name, Aml *dev,
+ const char *help_function, const char *method_name,
+ int ret_status_success,
+ int ret_status_changed)
+{
+ Aml *offset, *whilectx, *ifcond, *ifctx, *elsectx;
+
aml_append(method, aml_store(call_result, buf));
/* handle _DSM result. */
@@ -1174,7 +1189,7 @@ static void nvdimm_build_fit(Aml *dev)
aml_name(NVDIMM_DSM_RFIT_STATUS)));
/* if something is wrong during _DSM. */
- ifcond = aml_equal(aml_int(NVDIMM_DSM_RET_STATUS_SUCCESS),
+ ifcond = aml_equal(aml_int(ret_status_success),
aml_name("STAU"));
ifctx = aml_if(aml_lnot(ifcond));
aml_append(ifctx, aml_return(aml_buffer(0, NULL)));
@@ -1185,7 +1200,7 @@ static void nvdimm_build_fit(Aml *dev)
aml_int(4) /* the size of "STAU" */,
buf_size));
- /* if we read the end of fit. */
+ /* if we read the end of buff method. */
ifctx = aml_if(aml_equal(buf_size, aml_int(0)));
aml_append(ifctx, aml_return(aml_buffer(0, NULL)));
aml_append(method, ifctx);
@@ -1196,38 +1211,38 @@ static void nvdimm_build_fit(Aml *dev)
aml_append(method, aml_return(aml_name("BUFF")));
aml_append(dev, method);
- /* build _FIT. */
- method = aml_method("_FIT", 0, AML_SERIALIZED);
+ /* build buff method. */
+ method = aml_method(method_name, 0, AML_SERIALIZED);
offset = aml_local(3);
- aml_append(method, aml_store(aml_buffer(0, NULL), fit));
+ aml_append(method, aml_store(aml_buffer(0, NULL), buf_name));
aml_append(method, aml_store(aml_int(0), offset));
whilectx = aml_while(aml_int(1));
- aml_append(whilectx, aml_store(aml_call1("RFIT", offset), buf));
+ aml_append(whilectx, aml_store(aml_call1(help_function, offset), buf));
aml_append(whilectx, aml_store(aml_sizeof(buf), buf_size));
/*
- * if fit buffer was changed during RFIT, read from the beginning
- * again.
+ * if buffer was changed during runtime,
+ * read from the beginning again.
*/
ifctx = aml_if(aml_equal(aml_name(NVDIMM_DSM_RFIT_STATUS),
- aml_int(NVDIMM_DSM_RET_STATUS_FIT_CHANGED)));
- aml_append(ifctx, aml_store(aml_buffer(0, NULL), fit));
+ aml_int(ret_status_changed)));
+ aml_append(ifctx, aml_store(aml_buffer(0, NULL), buf_name));
aml_append(ifctx, aml_store(aml_int(0), offset));
aml_append(whilectx, ifctx);
elsectx = aml_else();
- /* finish fit read if no data is read out. */
+ /* finish buff read if no data is read out. */
ifctx = aml_if(aml_equal(buf_size, aml_int(0)));
- aml_append(ifctx, aml_return(fit));
+ aml_append(ifctx, aml_return(buf_name));
aml_append(elsectx, ifctx);
/* update the offset. */
aml_append(elsectx, aml_add(offset, buf_size, offset));
- /* append the data we read out to the fit buffer. */
- aml_append(elsectx, aml_concatenate(fit, buf, fit));
+ /* append the data we read out to the buffer. */
+ aml_append(elsectx, aml_concatenate(buf_name, buf, buf_name));
aml_append(whilectx, elsectx);
aml_append(method, whilectx);
diff --git a/include/hw/mem/nvdimm.h b/include/hw/mem/nvdimm.h
index 523a9b3d4a..95bbe044cb 100644
--- a/include/hw/mem/nvdimm.h
+++ b/include/hw/mem/nvdimm.h
@@ -25,6 +25,7 @@
#include "hw/mem/pc-dimm.h"
#include "hw/acpi/bios-linker-loader.h"
+#include "hw/acpi/aml-build.h"
#define NVDIMM_DEBUG 0
#define nvdimm_debug(fmt, ...) \
@@ -150,4 +151,9 @@ void nvdimm_build_acpi(GArray *table_offsets, GArray *table_data,
uint32_t ram_slots);
void nvdimm_plug(NVDIMMState *state);
void nvdimm_acpi_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev);
+void aml_build_runtime_buf(Aml *method, Aml *buf, Aml *buf_size,
+ Aml *call_result, Aml *buf_name, Aml *dev,
+ const char *help_function, const char *method_name,
+ int ret_status_success,
+ int ret_status_changed);
#endif
--
2.20.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH RESEND v6 12/14] hmat acpi: Implement _HMA method to update HMAT at runtime
2019-07-09 7:15 [Qemu-devel] [PATCH RESEND v6 00/14] Build ACPI Heterogeneous Memory Attribute Table (HMAT) Tao Xu
` (10 preceding siblings ...)
2019-07-09 7:15 ` [Qemu-devel] [PATCH RESEND v6 11/14] acpi: introduce aml_build_runtime_buf for NFIT generalizations Tao Xu
@ 2019-07-09 7:15 ` Tao Xu
2019-07-09 7:15 ` [Qemu-devel] [PATCH RESEND v6 13/14] QMP: Add QMP interface " Tao Xu
` (3 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Tao Xu @ 2019-07-09 7:15 UTC (permalink / raw)
To: imammedo, eblake, ehabkost
Cc: jingqi.liu, tao3.xu, fan.du, qemu-devel, jonathan.cameron,
dan.j.williams
From: Liu Jingqi <jingqi.liu@intel.com>
OSPM evaluates HMAT only during system initialization.
Any changes to the HMAT state at runtime or information
regarding HMAT for hot plug are communicated using _HMA method.
_HMA is an optional object that enables the platform to provide
the OS with updated Heterogeneous Memory Attributes information
at runtime. _HMA provides OSPM with the latest HMAT in entirety
overriding existing HMAT.
Signed-off-by: Liu Jingqi <jingqi.liu@intel.com>
Signed-off-by: Tao Xu <tao3.xu@intel.com>
---
Changes in v6:
- move AcpiHmaState from PCMachineState to MachineState
to make HMAT more generalic (Igor)
- use build_acpi_aml_common() introduced in patch 10/11 to
simplify hmat_build_aml (Igor)
- Add _HMA only qemu use hmat-lb or hmat-cache
---
hw/acpi/hmat.c | 297 ++++++++++++++++++++++++++++++++++++++++++
hw/acpi/hmat.h | 68 ++++++++++
hw/core/machine.c | 4 +
hw/core/numa.c | 10 ++
hw/i386/acpi-build.c | 4 +
hw/i386/pc_piix.c | 6 +
hw/i386/pc_q35.c | 6 +
include/sysemu/numa.h | 5 +
8 files changed, 400 insertions(+)
diff --git a/hw/acpi/hmat.c b/hw/acpi/hmat.c
index a207581f11..33b9dd2e04 100644
--- a/hw/acpi/hmat.c
+++ b/hw/acpi/hmat.c
@@ -27,6 +27,8 @@
#include "qemu/osdep.h"
#include "sysemu/numa.h"
#include "hw/acpi/hmat.h"
+#include "hw/mem/nvdimm.h"
+#include "hw/nvram/fw_cfg.h"
/*
* ACPI 6.3:
@@ -238,6 +240,270 @@ static void hmat_build_table_structs(GArray *table_data, NumaState *nstat)
}
}
+static uint64_t
+hmat_hma_method_read(void *opaque, hwaddr addr, unsigned size)
+{
+ printf("BUG: we never read _HMA IO Port.\n");
+ return 0;
+}
+
+/* _HMA Method: read HMA data. */
+static void hmat_handle_hma_method(AcpiHmaState *state,
+ HmatHmamIn *in, hwaddr hmam_mem_addr)
+{
+ HmatHmaBuffer *hma_buf = &state->hma_buf;
+ HmatHmamOut *read_hma_out;
+ GArray *hma;
+ uint32_t read_len = 0, ret_status;
+ int size;
+
+ if (in != NULL) {
+ le32_to_cpus(&in->offset);
+ }
+
+ hma = hma_buf->hma;
+ if (in->offset > hma->len) {
+ ret_status = HMAM_RET_STATUS_INVALID;
+ goto exit;
+ }
+
+ /* It is the first time to read HMA. */
+ if (!in->offset) {
+ hma_buf->dirty = false;
+ } else if (hma_buf->dirty) {
+ /* HMA has been changed during Reading HMA. */
+ ret_status = HMAM_RET_STATUS_HMA_CHANGED;
+ goto exit;
+ }
+
+ ret_status = HMAM_RET_STATUS_SUCCESS;
+ read_len = MIN(hma->len - in->offset,
+ HMAM_MEMORY_SIZE - 2 * sizeof(uint32_t));
+exit:
+ size = sizeof(HmatHmamOut) + read_len;
+ read_hma_out = g_malloc(size);
+
+ read_hma_out->len = cpu_to_le32(size);
+ read_hma_out->ret_status = cpu_to_le32(ret_status);
+ memcpy(read_hma_out->data, hma->data + in->offset, read_len);
+
+ cpu_physical_memory_write(hmam_mem_addr, read_hma_out, size);
+
+ g_free(read_hma_out);
+}
+
+static void
+hmat_hma_method_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
+{
+ AcpiHmaState *state = opaque;
+ hwaddr hmam_mem_addr = val;
+ HmatHmamIn *in;
+
+ in = g_new(HmatHmamIn, 1);
+ cpu_physical_memory_read(hmam_mem_addr, in, sizeof(*in));
+
+ hmat_handle_hma_method(state, in, hmam_mem_addr);
+}
+
+static const MemoryRegionOps hmat_hma_method_ops = {
+ .read = hmat_hma_method_read,
+ .write = hmat_hma_method_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+};
+
+static void hmat_init_hma_buffer(HmatHmaBuffer *hma_buf)
+{
+ hma_buf->hma = g_array_new(false, true /* clear */, 1);
+}
+
+static uint8_t hmat_acpi_table_checksum(uint8_t *buffer, uint32_t length)
+{
+ uint8_t sum = 0;
+ uint8_t *end = buffer + length;
+
+ while (buffer < end) {
+ sum = (uint8_t) (sum + *(buffer++));
+ }
+ return (uint8_t)(0 - sum);
+}
+
+static void hmat_build_header(AcpiTableHeader *h,
+ const char *sig, int len, uint8_t rev,
+ const char *oem_id, const char *oem_table_id)
+{
+ memcpy(&h->signature, sig, 4);
+ h->length = cpu_to_le32(len);
+ h->revision = rev;
+
+ if (oem_id) {
+ strncpy((char *)h->oem_id, oem_id, sizeof h->oem_id);
+ } else {
+ memcpy(h->oem_id, ACPI_BUILD_APPNAME6, 6);
+ }
+
+ if (oem_table_id) {
+ strncpy((char *)h->oem_table_id, oem_table_id, sizeof(h->oem_table_id));
+ } else {
+ memcpy(h->oem_table_id, ACPI_BUILD_APPNAME4, 4);
+ memcpy(h->oem_table_id + 4, sig, 4);
+ }
+
+ h->oem_revision = cpu_to_le32(1);
+ memcpy(h->asl_compiler_id, ACPI_BUILD_APPNAME4, 4);
+ h->asl_compiler_revision = cpu_to_le32(1);
+
+ /* Caculate the checksum of acpi table. */
+ h->checksum = 0;
+ h->checksum = hmat_acpi_table_checksum((uint8_t *)h, len);
+}
+
+static void hmat_build_hma_buffer(NumaState *nstat)
+{
+ HmatHmaBuffer *hma_buf = &(nstat->acpi_hma_state->hma_buf);
+
+ /* Free the old hma buffer before new allocation. */
+ g_array_free(hma_buf->hma, true);
+
+ hma_buf->hma = g_array_new(false, true /* clear */, 1);
+ acpi_data_push(hma_buf->hma, 40);
+
+ /* build HMAT in a given buffer. */
+ hmat_build_table_structs(hma_buf->hma, nstat);
+ hmat_build_header((void *)hma_buf->hma->data,
+ "HMAT", hma_buf->hma->len, 2, NULL, NULL);
+ hma_buf->dirty = true;
+}
+
+static void hmat_build_common_aml(Aml *dev)
+{
+ Aml *method, *ifctx, *hmam_mem;
+ Aml *unsupport;
+ Aml *pckg, *pckg_index, *pckg_buf, *field;
+ Aml *hmam_out_buf, *hmam_out_buf_size;
+ uint8_t byte_list[1];
+
+ method = aml_method(HMA_COMMON_METHOD, 1, AML_SERIALIZED);
+ hmam_mem = aml_local(6);
+ hmam_out_buf = aml_local(7);
+
+ aml_append(method, aml_store(aml_name(HMAM_ACPI_MEM_ADDR), hmam_mem));
+
+ /* map _HMA memory and IO into ACPI namespace. */
+ aml_append(method, aml_operation_region(HMAM_IOPORT, AML_SYSTEM_IO,
+ aml_int(HMAM_ACPI_IO_BASE), HMAM_ACPI_IO_LEN));
+ aml_append(method, aml_operation_region(HMAM_MEMORY,
+ AML_SYSTEM_MEMORY, hmam_mem, HMAM_MEMORY_SIZE));
+
+ /*
+ * _HMAC notifier:
+ * HMAM_NOTIFY: write the address of DSM memory and notify QEMU to
+ * emulate the access.
+ *
+ * It is the IO port so that accessing them will cause VM-exit, the
+ * control will be transferred to QEMU.
+ */
+ field = aml_field(HMAM_IOPORT, AML_DWORD_ACC, AML_NOLOCK,
+ AML_PRESERVE);
+ aml_append(field, aml_named_field(HMAM_NOTIFY,
+ sizeof(uint32_t) * BITS_PER_BYTE));
+ aml_append(method, field);
+
+ /*
+ * _HMAC input:
+ * HMAM_OFFSET: store the current offset of _HMA buffer.
+ *
+ * They are RAM mapping on host so that these accesses never cause VMExit.
+ */
+ field = aml_field(HMAM_MEMORY, AML_DWORD_ACC, AML_NOLOCK,
+ AML_PRESERVE);
+ aml_append(field, aml_named_field(HMAM_OFFSET,
+ sizeof(typeof_field(HmatHmamIn, offset)) * BITS_PER_BYTE));
+ aml_append(method, field);
+
+ /*
+ * _HMAC output:
+ * HMAM_OUT_BUF_SIZE: the size of the buffer filled by QEMU.
+ * HMAM_OUT_BUF: the buffer QEMU uses to store the result.
+ *
+ * Since the page is reused by both input and out, the input data
+ * will be lost after storing new result into ODAT so we should fetch
+ * all the input data before writing the result.
+ */
+ field = aml_field(HMAM_MEMORY, AML_DWORD_ACC, AML_NOLOCK,
+ AML_PRESERVE);
+ aml_append(field, aml_named_field(HMAM_OUT_BUF_SIZE,
+ sizeof(typeof_field(HmatHmamOut, len)) * BITS_PER_BYTE));
+ aml_append(field, aml_named_field(HMAM_OUT_BUF,
+ (sizeof(HmatHmamOut) - sizeof(uint32_t)) * BITS_PER_BYTE));
+ aml_append(method, field);
+
+ /*
+ * do not support any method if HMA memory address has not been
+ * patched.
+ */
+ unsupport = aml_if(aml_equal(hmam_mem, aml_int(0x0)));
+ byte_list[0] = HMAM_RET_STATUS_UNSUPPORT;
+ aml_append(unsupport, aml_return(aml_buffer(1, byte_list)));
+ aml_append(method, unsupport);
+
+ /* The parameter (Arg0) of _HMAC is a package which contains a buffer. */
+ pckg = aml_arg(0);
+ ifctx = aml_if(aml_and(aml_equal(aml_object_type(pckg),
+ aml_int(4 /* Package */)) /* It is a Package? */,
+ aml_equal(aml_sizeof(pckg), aml_int(1)) /* 1 element */,
+ NULL));
+
+ pckg_index = aml_local(2);
+ pckg_buf = aml_local(3);
+ aml_append(ifctx, aml_store(aml_index(pckg, aml_int(0)), pckg_index));
+ aml_append(ifctx, aml_store(aml_derefof(pckg_index), pckg_buf));
+ aml_append(ifctx, aml_store(pckg_buf, aml_name(HMAM_OFFSET)));
+ aml_append(method, ifctx);
+
+ /*
+ * tell QEMU about the real address of HMA memory, then QEMU
+ * gets the control and fills the result in _HMAC memory.
+ */
+ aml_append(method, aml_store(hmam_mem, aml_name(HMAM_NOTIFY)));
+
+ hmam_out_buf_size = aml_local(1);
+ /* RLEN is not included in the payload returned to guest. */
+ aml_append(method, aml_subtract(aml_name(HMAM_OUT_BUF_SIZE),
+ aml_int(4), hmam_out_buf_size));
+ aml_append(method, aml_store(aml_shiftleft(hmam_out_buf_size, aml_int(3)),
+ hmam_out_buf_size));
+ aml_append(method, aml_create_field(aml_name(HMAM_OUT_BUF),
+ aml_int(0), hmam_out_buf_size, "OBUF"));
+ aml_append(method, aml_concatenate(aml_buffer(0, NULL), aml_name("OBUF"),
+ hmam_out_buf));
+ aml_append(method, aml_return(hmam_out_buf));
+ aml_append(dev, method);
+}
+
+void hmat_init_acpi_state(AcpiHmaState *state, MemoryRegion *io,
+ FWCfgState *fw_cfg, Object *owner)
+{
+ memory_region_init_io(&state->io_mr, owner, &hmat_hma_method_ops, state,
+ "hma-acpi-io", HMAM_ACPI_IO_LEN);
+ memory_region_add_subregion(io, HMAM_ACPI_IO_BASE, &state->io_mr);
+
+ state->hmam_mem = g_array_new(false, true /* clear */, 1);
+ fw_cfg_add_file(fw_cfg, HMAM_MEM_FILE, state->hmam_mem->data,
+ state->hmam_mem->len);
+
+ hmat_init_hma_buffer(&state->hma_buf);
+}
+
+void hmat_update(NumaState *nstat)
+{
+ /* build HMAT in a given buffer. */
+ hmat_build_hma_buffer(nstat);
+}
+
void build_hmat(GArray *table_data, BIOSLinker *linker, NumaState *nstat)
{
uint64_t hmat_start;
@@ -253,3 +519,34 @@ void build_hmat(GArray *table_data, BIOSLinker *linker, NumaState *nstat)
(void *)(table_data->data + hmat_start),
"HMAT", table_data->len - hmat_start, 2, NULL, NULL);
}
+
+void hmat_build_aml(Aml *dev)
+{
+ Aml *method, *pkg, *buf, *buf_name, *buf_size, *call_result;
+
+ hmat_build_common_aml(dev);
+
+ buf = aml_local(0);
+ buf_size = aml_local(1);
+ buf_name = aml_local(2);
+
+ aml_append(dev, aml_name_decl(HMAM_RHMA_STATUS, aml_int(0)));
+
+ /* build helper function, RHMA. */
+ method = aml_method("RHMA", 1, AML_SERIALIZED);
+ aml_append(method, aml_name_decl("OFST", aml_int(0)));
+
+ /* prepare input package. */
+ pkg = aml_package(1);
+ aml_append(method, aml_store(aml_arg(0), aml_name("OFST")));
+ aml_append(pkg, aml_name("OFST"));
+
+ /* call Read HMA function. */
+ call_result = aml_call1(HMA_COMMON_METHOD, pkg);
+
+ aml_build_runtime_buf(method, buf, buf_size,
+ call_result, buf_name, dev,
+ "RHMA", "_HMA",
+ HMAM_RET_STATUS_SUCCESS,
+ HMAM_RET_STATUS_HMA_CHANGED);
+}
diff --git a/hw/acpi/hmat.h b/hw/acpi/hmat.h
index ba655281cc..937d5ee6dc 100644
--- a/hw/acpi/hmat.h
+++ b/hw/acpi/hmat.h
@@ -99,6 +99,74 @@ struct HMAT_Cache_Info {
uint16_t line_size;
};
+#define HMAM_MEMORY_SIZE 4096
+#define HMAM_MEM_FILE "etc/acpi/hma-mem"
+
+/*
+ * 32 bits IO port starting from 0x0a19 in guest is reserved for
+ * HMA ACPI emulation.
+ */
+#define HMAM_ACPI_IO_BASE 0x0a19
+#define HMAM_ACPI_IO_LEN 4
+
+#define HMAM_ACPI_MEM_ADDR "HMTA"
+#define HMAM_MEMORY "HRAM"
+#define HMAM_IOPORT "HPIO"
+
+#define HMAM_NOTIFY "NTFI"
+#define HMAM_OUT_BUF_SIZE "RLEN"
+#define HMAM_OUT_BUF "ODAT"
+
+#define HMAM_RHMA_STATUS "RSTA"
+#define HMA_COMMON_METHOD "HMAC"
+#define HMAM_OFFSET "OFFT"
+
+#define HMAM_RET_STATUS_SUCCESS 0 /* Success */
+#define HMAM_RET_STATUS_UNSUPPORT 1 /* Not Supported */
+#define HMAM_RET_STATUS_INVALID 2 /* Invalid Input Parameters */
+#define HMAM_RET_STATUS_HMA_CHANGED 0x100 /* HMA Changed */
+
+/*
+ * HmatHmaBuffer:
+ * @hma: HMA buffer with the updated HMAT. It is updated when
+ * the memory device is plugged or unplugged.
+ * @dirty: It allows OSPM to detect changes and restart read if there is any.
+ */
+struct HmatHmaBuffer {
+ GArray *hma;
+ bool dirty;
+};
+typedef struct HmatHmaBuffer HmatHmaBuffer;
+
+struct AcpiHmaState {
+ /* the data of the fw_cfg file HMAM_MEM_FILE. */
+ GArray *hmam_mem;
+
+ HmatHmaBuffer hma_buf;
+
+ /* the IO region used by OSPM to transfer control to QEMU. */
+ MemoryRegion io_mr;
+};
+typedef struct AcpiHmaState AcpiHmaState;
+
+struct HmatHmamIn {
+ /* the offset in the _HMA buffer */
+ uint32_t offset;
+} QEMU_PACKED;
+typedef struct HmatHmamIn HmatHmamIn;
+
+struct HmatHmamOut {
+ /* the size of buffer filled by QEMU. */
+ uint32_t len;
+ uint32_t ret_status; /* return status code. */
+ uint8_t data[4088];
+} QEMU_PACKED;
+typedef struct HmatHmamOut HmatHmamOut;
+
void build_hmat(GArray *table_data, BIOSLinker *linker, NumaState *nstat);
+void hmat_build_aml(Aml *dsdt);
+void hmat_init_acpi_state(AcpiHmaState *state, MemoryRegion *io,
+ FWCfgState *fw_cfg, Object *owner);
+void hmat_update(NumaState *nstat);
#endif
diff --git a/hw/core/machine.c b/hw/core/machine.c
index 063cb7923c..234cf63aad 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -26,6 +26,7 @@
#include "sysemu/qtest.h"
#include "hw/pci/pci.h"
#include "hw/mem/nvdimm.h"
+#include "hw/acpi/hmat.h"
GlobalProperty hw_compat_4_0[] = {
{ "VGA", "edid", "false" },
@@ -1000,6 +1001,9 @@ static void machine_finalize(Object *obj)
g_free(ms->firmware);
g_free(ms->device_memory);
g_free(ms->nvdimms_state);
+ if (ms->numa_state->hma_enabled) {
+ g_free(ms->numa_state->acpi_hma_state);
+ }
g_free(ms->numa_state);
}
diff --git a/hw/core/numa.c b/hw/core/numa.c
index 75db35ac19..5ed53ef05e 100644
--- a/hw/core/numa.c
+++ b/hw/core/numa.c
@@ -251,6 +251,11 @@ void parse_numa_hmat_lb(MachineState *ms, NumaHmatLBOptions *node,
return;
}
+ if (!ms->numa_state->hma_enabled && !ms->numa_state->acpi_hma_state) {
+ ms->numa_state->hma_enabled = true;
+ ms->numa_state->acpi_hma_state = g_new0(AcpiHmaState, 1);
+ }
+
if (node->has_latency) {
hmat_lb = ms->numa_state->hmat_lb[node->hierarchy][node->data_type];
@@ -352,6 +357,11 @@ void parse_numa_hmat_cache(MachineState *ms, NumaHmatCacheOptions *node,
return;
}
+ if (!ms->numa_state->hma_enabled && !ms->numa_state->acpi_hma_state) {
+ ms->numa_state->hma_enabled = true;
+ ms->numa_state->acpi_hma_state = g_new0(AcpiHmaState, 1);
+ }
+
hmat_cache = g_malloc0(sizeof(*hmat_cache));
hmat_cache->mem_proximity = node->node_id;
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 6eee709258..e38fbbcc37 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1857,6 +1857,10 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
build_q35_pci0_int(dsdt);
}
+ if (machine->numa_state->hma_enabled) {
+ hmat_build_aml(dsdt);
+ }
+
if (pcmc->legacy_cpu_hotplug) {
build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base);
} else {
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index c2280c72ef..9ef92ba4cb 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -59,6 +59,7 @@
#include "migration/misc.h"
#include "kvm_i386.h"
#include "sysemu/numa.h"
+#include "hw/acpi/hmat.h"
#define MAX_IDE_BUS 2
@@ -307,6 +308,11 @@ else {
nvdimm_init_acpi_state(machine->nvdimms_state, system_io,
pcms->fw_cfg, OBJECT(pcms));
}
+
+ if (machine->numa_state->hma_enabled) {
+ hmat_init_acpi_state(machine->numa_state->acpi_hma_state, system_io,
+ pcms->fw_cfg, OBJECT(pcms));
+ }
}
/* Looking for a pc_compat_2_4() function? It doesn't exist.
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 397e1fdd2f..0e42698b8e 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -54,6 +54,7 @@
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "sysemu/numa.h"
+#include "hw/acpi/hmat.h"
/* ICH9 AHCI has 6 ports */
#define MAX_SATA_PORTS 6
@@ -333,6 +334,11 @@ static void pc_q35_init(MachineState *machine)
nvdimm_init_acpi_state(machine->nvdimms_state, system_io,
pcms->fw_cfg, OBJECT(pcms));
}
+
+ if (machine->numa_state->hma_enabled) {
+ hmat_init_acpi_state(machine->numa_state->acpi_hma_state, system_io,
+ pcms->fw_cfg, OBJECT(pcms));
+ }
}
#define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \
diff --git a/include/sysemu/numa.h b/include/sysemu/numa.h
index 3649262918..ba040b8b76 100644
--- a/include/sysemu/numa.h
+++ b/include/sysemu/numa.h
@@ -38,6 +38,11 @@ struct NumaState {
/* Memory Side Cache Information Structure */
HMAT_Cache_Info *hmat_cache[MAX_NODES][MAX_HMAT_CACHE_LEVEL + 1];
+
+ /* Detect if HMA support is enabled. */
+ bool hma_enabled;
+
+ struct AcpiHmaState *acpi_hma_state;
};
typedef struct NumaState NumaState;
--
2.20.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH RESEND v6 13/14] QMP: Add QMP interface to update HMAT at runtime
2019-07-09 7:15 [Qemu-devel] [PATCH RESEND v6 00/14] Build ACPI Heterogeneous Memory Attribute Table (HMAT) Tao Xu
` (11 preceding siblings ...)
2019-07-09 7:15 ` [Qemu-devel] [PATCH RESEND v6 12/14] hmat acpi: Implement _HMA method to update HMAT at runtime Tao Xu
@ 2019-07-09 7:15 ` Tao Xu
2019-07-09 7:15 ` [Qemu-devel] [PATCH RESEND v6 14/14] tests/bios-tables-test: add test cases for ACPI HMAT Tao Xu
` (2 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Tao Xu @ 2019-07-09 7:15 UTC (permalink / raw)
To: imammedo, eblake, ehabkost
Cc: jingqi.liu, tao3.xu, fan.du, qemu-devel, jonathan.cameron,
dan.j.williams
Add QMP interface to introduce new HMAT data (including System Locality
Latency and Bandwidth Information Structure, Memory Side Cache
Information Structure) at runtime. The interface can
also replace existing HMAT data.
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Tao Xu <tao3.xu@intel.com>
---
hw/acpi/acpi-stub.c | 7 ++++++
hw/core/machine-qmp-cmds.c | 39 ++++++++++++++++++++++++++++++
hw/core/numa.c | 17 +++++++------
include/sysemu/numa.h | 4 ++--
qapi/machine.json | 49 ++++++++++++++++++++++++++++++++++++++
5 files changed, 107 insertions(+), 9 deletions(-)
diff --git a/hw/acpi/acpi-stub.c b/hw/acpi/acpi-stub.c
index 4c9d081ed4..757570ee7f 100644
--- a/hw/acpi/acpi-stub.c
+++ b/hw/acpi/acpi-stub.c
@@ -22,8 +22,15 @@
#include "qapi/error.h"
#include "qapi/qmp/qerror.h"
#include "hw/acpi/acpi.h"
+#include "sysemu/numa.h"
+#include "hw/acpi/hmat.h"
void acpi_table_add(const QemuOpts *opts, Error **errp)
{
error_setg(errp, QERR_UNSUPPORTED);
}
+
+void hmat_update(NumaState *nstat)
+{
+ /* For qmp_set_hmat_lb and qmp_set_hmat_cache in numa.c can compile */
+}
diff --git a/hw/core/machine-qmp-cmds.c b/hw/core/machine-qmp-cmds.c
index 5bd95b8ab0..fe6ed418b1 100644
--- a/hw/core/machine-qmp-cmds.c
+++ b/hw/core/machine-qmp-cmds.c
@@ -17,6 +17,7 @@
#include "sysemu/hw_accel.h"
#include "sysemu/numa.h"
#include "sysemu/sysemu.h"
+#include "hw/acpi/hmat.h"
CpuInfoList *qmp_query_cpus(Error **errp)
{
@@ -283,6 +284,44 @@ void qmp_set_numa_node(NumaOptions *cmd, Error **errp)
set_numa_options(MACHINE(qdev_get_machine()), cmd, errp);
}
+void qmp_set_hmat_lb(NumaHmatLBOptions *node, Error **errp)
+{
+ MachineState *ms = MACHINE(qdev_get_machine());
+
+ if (ms->numa_state == NULL || ms->numa_state->num_nodes <= 0) {
+ error_setg(errp, "NUMA is not supported");
+ return;
+ }
+
+ if (ms->numa_state->hma_enabled) {
+ parse_numa_hmat_lb(ms, node, 1, errp);
+ hmat_update(ms->numa_state);
+ } else {
+ error_setg(errp, "HMAT can't be changed at runtime when QEMU boot"
+ " without setting HMAT latency, bandwidth or memory cache"
+ " information");
+ }
+}
+
+void qmp_set_hmat_cache(NumaHmatCacheOptions *node, Error **errp)
+{
+ MachineState *ms = MACHINE(qdev_get_machine());
+
+ if (ms->numa_state == NULL || ms->numa_state->num_nodes <= 0) {
+ error_setg(errp, "NUMA is not supported");
+ return;
+ }
+
+ if (ms->numa_state->hma_enabled) {
+ parse_numa_hmat_cache(ms, node, 1, errp);
+ hmat_update(ms->numa_state);
+ } else {
+ error_setg(errp, "HMAT can't be changed at runtime when QEMU boot"
+ " without setting HMAT latency, bandwidth or memory cache"
+ " information");
+ }
+}
+
static int query_memdev(Object *obj, void *opaque)
{
MemdevList **list = opaque;
diff --git a/hw/core/numa.c b/hw/core/numa.c
index 5ed53ef05e..e8ee4edd67 100644
--- a/hw/core/numa.c
+++ b/hw/core/numa.c
@@ -185,7 +185,7 @@ void parse_numa_distance(MachineState *ms, NumaDistOptions *dist, Error **errp)
}
void parse_numa_hmat_lb(MachineState *ms, NumaHmatLBOptions *node,
- Error **errp)
+ bool runtime_flag, Error **errp)
{
int nb_numa_nodes = ms->numa_state->num_nodes;
NodeInfo *numa_info = ms->numa_state->nodes;
@@ -262,7 +262,8 @@ void parse_numa_hmat_lb(MachineState *ms, NumaHmatLBOptions *node,
if (!hmat_lb) {
hmat_lb = g_malloc0(sizeof(*hmat_lb));
ms->numa_state->hmat_lb[node->hierarchy][node->data_type] = hmat_lb;
- } else if (hmat_lb->latency[node->initiator][node->target]) {
+ } else if (!runtime_flag &&
+ hmat_lb->latency[node->initiator][node->target]) {
error_setg(errp, "Duplicate configuration of the latency for "
"initiator=%" PRIu16 " and target=%" PRIu16 ".",
node->initiator, node->target);
@@ -283,7 +284,8 @@ void parse_numa_hmat_lb(MachineState *ms, NumaHmatLBOptions *node,
if (!hmat_lb) {
hmat_lb = g_malloc0(sizeof(*hmat_lb));
ms->numa_state->hmat_lb[node->hierarchy][node->data_type] = hmat_lb;
- } else if (hmat_lb->bandwidth[node->initiator][node->target]) {
+ } else if (!runtime_flag &&
+ hmat_lb->bandwidth[node->initiator][node->target]) {
error_setg(errp, "Duplicate configuration of the bandwidth for "
"initiator=%" PRIu16 " and target=%" PRIu16 ".",
node->initiator, node->target);
@@ -310,7 +312,7 @@ void parse_numa_hmat_lb(MachineState *ms, NumaHmatLBOptions *node,
}
void parse_numa_hmat_cache(MachineState *ms, NumaHmatCacheOptions *node,
- Error **errp)
+ bool runtime_flag, Error **errp)
{
int nb_numa_nodes = ms->numa_state->num_nodes;
HMAT_Cache_Info *hmat_cache = NULL;
@@ -335,7 +337,8 @@ void parse_numa_hmat_cache(MachineState *ms, NumaHmatCacheOptions *node,
node->level, node->total);
return;
}
- if (ms->numa_state->hmat_cache[node->node_id][node->level]) {
+ if (!runtime_flag &&
+ ms->numa_state->hmat_cache[node->node_id][node->level]) {
error_setg(errp, "Duplicate configuration of the side cache for "
"node-id=%" PRIu32 " and level=%" PRIu8 ".",
node->node_id, node->level);
@@ -414,13 +417,13 @@ void set_numa_options(MachineState *ms, NumaOptions *object, Error **errp)
&err);
break;
case NUMA_OPTIONS_TYPE_HMAT_LB:
- parse_numa_hmat_lb(ms, &object->u.hmat_lb, &err);
+ parse_numa_hmat_lb(ms, &object->u.hmat_lb, 0, &err);
if (err) {
goto end;
}
break;
case NUMA_OPTIONS_TYPE_HMAT_CACHE:
- parse_numa_hmat_cache(ms, &object->u.hmat_cache, &err);
+ parse_numa_hmat_cache(ms, &object->u.hmat_cache, 0, &err);
if (err) {
goto end;
}
diff --git a/include/sysemu/numa.h b/include/sysemu/numa.h
index ba040b8b76..e5899f0764 100644
--- a/include/sysemu/numa.h
+++ b/include/sysemu/numa.h
@@ -49,9 +49,9 @@ typedef struct NumaState NumaState;
void set_numa_options(MachineState *ms, NumaOptions *object, Error **errp);
void parse_numa_opts(MachineState *ms);
void parse_numa_hmat_lb(MachineState *ms, NumaHmatLBOptions *node,
- Error **errp);
+ bool runtime_flag, Error **errp);
void parse_numa_hmat_cache(MachineState *ms, NumaHmatCacheOptions *node,
- Error **errp);
+ bool runtime_flag, Error **errp);
void numa_complete_configuration(MachineState *ms);
void query_numa_node_mem(NumaNodeMem node_mem[], MachineState *ms);
extern QemuOptsList qemu_numa_opts;
diff --git a/qapi/machine.json b/qapi/machine.json
index b0d42cff21..3cb69d2c6e 100644
--- a/qapi/machine.json
+++ b/qapi/machine.json
@@ -606,6 +606,31 @@
'*latency': 'uint16',
'*bandwidth': 'uint16' }}
+##
+# @set-hmat-lb:
+#
+# Set @NumaHmatLBOptions at runtime.
+#
+# Since: 4.1
+#
+# Example:
+# Set the processors in node 0 access memory in node with access-latency 5
+# nanoseconds(base latency is 10):
+#
+# -> { "execute": "set-hmat-lb",
+# "arguments": { "initiator": 0,
+# "target": 1,
+# "hierarchy": "memory",
+# "data-type": "access-latency",
+# "base-lat": 10,
+# "latency": 5 } }
+# <- { "return": {} }
+##
+{ 'command': 'set-hmat-lb', 'boxed': true,
+ 'data': 'NumaHmatLBOptions',
+ 'allow-preconfig': true
+}
+
##
# @HmatCacheAssociativity:
#
@@ -680,6 +705,30 @@
'policy': 'HmatCacheWritePolicy',
'line': 'uint16' }}
+##
+# @set-hmat-cache:
+#
+# Set @NumaHmatCacheOptions at runtime.
+#
+# Since: 4.1
+#
+# Example:
+# Set Memory Side Cache Information in node 1:
+#
+# -> { "execute": "set-hmat-cache",
+# "arguments": { "node-id": 1,
+# "size": 0x20000,
+# "total": 3,
+# "level": "direct",
+# "policy": "write-back",
+# "line": 8 } }
+# <- { "return": {} }
+##
+{ 'command': 'set-hmat-cache', 'boxed': true,
+ 'data': 'NumaHmatCacheOptions',
+ 'allow-preconfig': true
+}
+
##
# @HostMemPolicy:
#
--
2.20.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH RESEND v6 14/14] tests/bios-tables-test: add test cases for ACPI HMAT
2019-07-09 7:15 [Qemu-devel] [PATCH RESEND v6 00/14] Build ACPI Heterogeneous Memory Attribute Table (HMAT) Tao Xu
` (12 preceding siblings ...)
2019-07-09 7:15 ` [Qemu-devel] [PATCH RESEND v6 13/14] QMP: Add QMP interface " Tao Xu
@ 2019-07-09 7:15 ` Tao Xu
2019-07-09 7:41 ` [Qemu-devel] [PATCH RESEND v6 00/14] Build ACPI Heterogeneous Memory Attribute Table (HMAT) no-reply
2019-07-09 7:46 ` no-reply
15 siblings, 0 replies; 17+ messages in thread
From: Tao Xu @ 2019-07-09 7:15 UTC (permalink / raw)
To: imammedo, eblake, ehabkost
Cc: jingqi.liu, tao3.xu, fan.du, qemu-devel, jonathan.cameron,
dan.j.williams
ACPI table HMAT has been introduced, QEMU now builds HMAT tables for
Heterogeneous Memory with boot option '-numa node'.
Add test cases on PC and Q35 machines with 2 numa nodes.
Because HMAT is generated when system enable numa, the
following tables need to be added for this test:
tests/acpi-test-data/pc/*.acpihmat
tests/acpi-test-data/pc/HMAT.*
tests/acpi-test-data/q35/*.acpihmat
tests/acpi-test-data/q35/HMAT.*
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Tao Xu <tao3.xu@intel.com>
---
tests/bios-tables-test.c | 43 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/tests/bios-tables-test.c b/tests/bios-tables-test.c
index d863233fe9..27a17921f2 100644
--- a/tests/bios-tables-test.c
+++ b/tests/bios-tables-test.c
@@ -860,6 +860,47 @@ static void test_acpi_piix4_tcg_dimm_pxm(void)
test_acpi_tcg_dimm_pxm(MACHINE_PC);
}
+static void test_acpi_tcg_acpi_hmat(const char *machine)
+{
+ test_data data;
+
+ memset(&data, 0, sizeof(data));
+ data.machine = machine;
+ data.variant = ".acpihmat";
+ test_acpi_one(" -smp 2,sockets=2"
+ " -m 128M,slots=2,maxmem=1G"
+ " -object memory-backend-ram,size=64M,id=m0"
+ " -object memory-backend-ram,size=64M,id=m1"
+ " -numa node,nodeid=0,memdev=m0"
+ " -numa node,nodeid=1,memdev=m1,initiator=0"
+ " -numa cpu,node-id=0,socket-id=0"
+ " -numa cpu,node-id=0,socket-id=1"
+ " -numa hmat-lb,initiator=0,target=0,hierarchy=memory,"
+ "data-type=access-latency,base-lat=10,latency=5"
+ " -numa hmat-lb,initiator=0,target=0,hierarchy=memory,"
+ "data-type=access-bandwidth,base-bw=20,bandwidth=5"
+ " -numa hmat-lb,initiator=0,target=1,hierarchy=memory,"
+ "data-type=access-latency,base-lat=10,latency=10"
+ " -numa hmat-lb,initiator=0,target=1,hierarchy=memory,"
+ "data-type=access-bandwidth,base-bw=20,bandwidth=10"
+ " -numa hmat-cache,node-id=0,size=0x20000,total=1,level=1"
+ ",assoc=direct,policy=write-back,line=8"
+ " -numa hmat-cache,node-id=1,size=0x20000,total=1,level=1"
+ ",assoc=direct,policy=write-back,line=8",
+ &data);
+ free_test_data(&data);
+}
+
+static void test_acpi_q35_tcg_acpi_hmat(void)
+{
+ test_acpi_tcg_acpi_hmat(MACHINE_Q35);
+}
+
+static void test_acpi_piix4_tcg_acpi_hmat(void)
+{
+ test_acpi_tcg_acpi_hmat(MACHINE_PC);
+}
+
static void test_acpi_virt_tcg(void)
{
test_data data = {
@@ -904,6 +945,8 @@ int main(int argc, char *argv[])
qtest_add_func("acpi/q35/numamem", test_acpi_q35_tcg_numamem);
qtest_add_func("acpi/piix4/dimmpxm", test_acpi_piix4_tcg_dimm_pxm);
qtest_add_func("acpi/q35/dimmpxm", test_acpi_q35_tcg_dimm_pxm);
+ qtest_add_func("acpi/piix4/acpihmat", test_acpi_piix4_tcg_acpi_hmat);
+ qtest_add_func("acpi/q35/acpihmat", test_acpi_q35_tcg_acpi_hmat);
} else if (strcmp(arch, "aarch64") == 0) {
qtest_add_func("acpi/virt", test_acpi_virt_tcg);
}
--
2.20.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [Qemu-devel] [PATCH RESEND v6 00/14] Build ACPI Heterogeneous Memory Attribute Table (HMAT)
2019-07-09 7:15 [Qemu-devel] [PATCH RESEND v6 00/14] Build ACPI Heterogeneous Memory Attribute Table (HMAT) Tao Xu
` (13 preceding siblings ...)
2019-07-09 7:15 ` [Qemu-devel] [PATCH RESEND v6 14/14] tests/bios-tables-test: add test cases for ACPI HMAT Tao Xu
@ 2019-07-09 7:41 ` no-reply
2019-07-09 7:46 ` no-reply
15 siblings, 0 replies; 17+ messages in thread
From: no-reply @ 2019-07-09 7:41 UTC (permalink / raw)
To: tao3.xu
Cc: ehabkost, jingqi.liu, tao3.xu, fan.du, qemu-devel,
jonathan.cameron, imammedo, dan.j.williams
Patchew URL: https://patchew.org/QEMU/20190709071520.8745-1-tao3.xu@intel.com/
Hi,
This series failed build test on s390x host. Please find the details below.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
# Testing script will be invoked under the git checkout with
# HEAD pointing to a commit that has the patches applied on top of "base"
# branch
set -e
echo
echo "=== ENV ==="
env
echo
echo "=== PACKAGES ==="
rpm -qa
echo
echo "=== UNAME ==="
uname -a
CC=$HOME/bin/cc
INSTALL=$PWD/install
BUILD=$PWD/build
mkdir -p $BUILD $INSTALL
SRC=$PWD
cd $BUILD
$SRC/configure --cc=$CC --prefix=$INSTALL
make -j4
# XXX: we need reliable clean up
# make check -j4 V=1
make install
=== TEST SCRIPT END ===
GEN util/trace.c
GEN config-all-devices.mak
Cloning into '/var/tmp/patchew-tester-tmp-ehkqzjm7/src/dtc'...
error: RPC failed; curl 18 transfer closed with outstanding read data remaining
fatal: the remote end hung up unexpectedly
fatal: protocol error: bad pack header
fatal: clone of 'https://git.qemu.org/git/dtc.git' into submodule path '/var/tmp/patchew-tester-tmp-ehkqzjm7/src/dtc' failed
Failed to clone 'dtc'. Retry scheduled
Cloning into '/var/tmp/patchew-tester-tmp-ehkqzjm7/src/slirp'...
---
Cloning into '/var/tmp/patchew-tester-tmp-ehkqzjm7/src/tests/fp/berkeley-testfloat-3'...
Cloning into '/var/tmp/patchew-tester-tmp-ehkqzjm7/src/ui/keycodemapdb'...
Cloning into '/var/tmp/patchew-tester-tmp-ehkqzjm7/src/dtc'...
error: RPC failed; curl 18 transfer closed with outstanding read data remaining
fatal: the remote end hung up unexpectedly
fatal: protocol error: bad pack header
fatal: clone of 'https://git.qemu.org/git/dtc.git' into submodule path '/var/tmp/patchew-tester-tmp-ehkqzjm7/src/dtc' failed
Failed to clone 'dtc' a second time, aborting
./scripts/git-submodule.sh: failed to update modules
The full log is available at
http://patchew.org/logs/20190709071520.8745-1-tao3.xu@intel.com/testing.s390x/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Qemu-devel] [PATCH RESEND v6 00/14] Build ACPI Heterogeneous Memory Attribute Table (HMAT)
2019-07-09 7:15 [Qemu-devel] [PATCH RESEND v6 00/14] Build ACPI Heterogeneous Memory Attribute Table (HMAT) Tao Xu
` (14 preceding siblings ...)
2019-07-09 7:41 ` [Qemu-devel] [PATCH RESEND v6 00/14] Build ACPI Heterogeneous Memory Attribute Table (HMAT) no-reply
@ 2019-07-09 7:46 ` no-reply
15 siblings, 0 replies; 17+ messages in thread
From: no-reply @ 2019-07-09 7:46 UTC (permalink / raw)
To: tao3.xu
Cc: ehabkost, jingqi.liu, tao3.xu, fan.du, qemu-devel,
jonathan.cameron, imammedo, dan.j.williams
Patchew URL: https://patchew.org/QEMU/20190709071520.8745-1-tao3.xu@intel.com/
Hi,
This series failed the asan build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
make docker-image-fedora V=1 NETWORK=1
time make docker-test-debug@fedora TARGET_LIST=x86_64-softmmu J=14 NETWORK=1
=== TEST SCRIPT END ===
CC hw/audio/ac97.o
CC hw/audio/fmopl.o
CC hw/audio/adlib.o
/tmp/qemu-test/src/hw/acpi/hmat.c:261:23: error: taking address of packed member 'offset' of class or structure 'HmatHmamIn' may result in an unaligned pointer value [-Werror,-Waddress-of-packed-member]
le32_to_cpus(&in->offset);
^~~~~~~~~~
1 error generated.
The full log is available at
http://patchew.org/logs/20190709071520.8745-1-tao3.xu@intel.com/testing.asan/?type=message.
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^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2019-07-09 7:48 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-07-09 7:15 [Qemu-devel] [PATCH RESEND v6 00/14] Build ACPI Heterogeneous Memory Attribute Table (HMAT) Tao Xu
2019-07-09 7:15 ` [Qemu-devel] [PATCH RESEND v6 01/14] hw/arm: simplify arm_load_dtb Tao Xu
2019-07-09 7:15 ` [Qemu-devel] [PATCH RESEND v6 02/14] numa: move numa global variable nb_numa_nodes into MachineState Tao Xu
2019-07-09 7:15 ` [Qemu-devel] [PATCH RESEND v6 03/14] numa: move numa global variable have_numa_distance " Tao Xu
2019-07-09 7:15 ` [Qemu-devel] [PATCH RESEND v6 04/14] numa: move numa global variable numa_info " Tao Xu
2019-07-09 7:15 ` [Qemu-devel] [PATCH RESEND v6 05/14] numa: Extend CLI to provide initiator information for numa nodes Tao Xu
2019-07-09 7:15 ` [Qemu-devel] [PATCH RESEND v6 06/14] hmat acpi: Build Memory Proximity Domain Attributes Structure(s) Tao Xu
2019-07-09 7:15 ` [Qemu-devel] [PATCH RESEND v6 07/14] hmat acpi: Build System Locality Latency and Bandwidth Information Structure(s) Tao Xu
2019-07-09 7:15 ` [Qemu-devel] [PATCH RESEND v6 08/14] hmat acpi: Build Memory Side Cache " Tao Xu
2019-07-09 7:15 ` [Qemu-devel] [PATCH RESEND v6 09/14] numa: Extend the CLI to provide memory latency and bandwidth information Tao Xu
2019-07-09 7:15 ` [Qemu-devel] [PATCH RESEND v6 10/14] numa: Extend the CLI to provide memory side cache information Tao Xu
2019-07-09 7:15 ` [Qemu-devel] [PATCH RESEND v6 11/14] acpi: introduce aml_build_runtime_buf for NFIT generalizations Tao Xu
2019-07-09 7:15 ` [Qemu-devel] [PATCH RESEND v6 12/14] hmat acpi: Implement _HMA method to update HMAT at runtime Tao Xu
2019-07-09 7:15 ` [Qemu-devel] [PATCH RESEND v6 13/14] QMP: Add QMP interface " Tao Xu
2019-07-09 7:15 ` [Qemu-devel] [PATCH RESEND v6 14/14] tests/bios-tables-test: add test cases for ACPI HMAT Tao Xu
2019-07-09 7:41 ` [Qemu-devel] [PATCH RESEND v6 00/14] Build ACPI Heterogeneous Memory Attribute Table (HMAT) no-reply
2019-07-09 7:46 ` no-reply
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