* [PATCH v6 0/5] EHL port programming
@ 2019-07-09 18:39 Matt Roper
2019-07-09 18:39 ` [PATCH v6 1/5] drm/i915/gen11: Start distinguishing 'phy' from 'port' Matt Roper
` (7 more replies)
0 siblings, 8 replies; 13+ messages in thread
From: Matt Roper @ 2019-07-09 18:39 UTC (permalink / raw)
To: intel-gfx
Final revision which incorporates Jose's minor suggestions (renaming a
register and dropping one #include) and triggers a final CI run. All
patches are reviewed so this should be ready to apply once CI finishes.
Previous series revisions were here:
v4/5: https://lists.freedesktop.org/archives/intel-gfx/2019-July/204257.html
v3: https://lists.freedesktop.org/archives/intel-gfx/2019-June/203287.html
v1/2: https://lists.freedesktop.org/archives/intel-gfx/2019-June/202776.html
Matt Roper (5):
drm/i915/gen11: Start distinguishing 'phy' from 'port'
drm/i915/gen11: Program ICL_DPCLKA_CFGCR0 according to PHY
drm/i915/gen11: Convert combo PHY logic to use new 'enum phy'
namespace
drm/i915: Transition port type checks to phy checks
drm/i915/ehl: Enable DDI-D
drivers/gpu/drm/i915/display/icl_dsi.c | 152 +++++++++---------
drivers/gpu/drm/i915/display/intel_bios.c | 4 +-
.../gpu/drm/i915/display/intel_combo_phy.c | 143 ++++++++--------
.../gpu/drm/i915/display/intel_combo_phy.h | 4 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 146 ++++++++++-------
drivers/gpu/drm/i915/display/intel_display.c | 41 +++--
drivers/gpu/drm/i915/display/intel_display.h | 20 +++
.../drm/i915/display/intel_display_power.c | 20 +--
drivers/gpu/drm/i915/display/intel_dp.c | 15 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 11 +-
drivers/gpu/drm/i915/display/intel_dsi.h | 12 +-
drivers/gpu/drm/i915/i915_reg.h | 86 +++++-----
drivers/gpu/drm/i915/intel_drv.h | 4 +-
13 files changed, 365 insertions(+), 293 deletions(-)
--
2.20.1
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^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCH v6 1/5] drm/i915/gen11: Start distinguishing 'phy' from 'port' 2019-07-09 18:39 [PATCH v6 0/5] EHL port programming Matt Roper @ 2019-07-09 18:39 ` Matt Roper 2019-07-09 18:39 ` [PATCH v6 2/5] drm/i915/gen11: Program ICL_DPCLKA_CFGCR0 according to PHY Matt Roper ` (6 subsequent siblings) 7 siblings, 0 replies; 13+ messages in thread From: Matt Roper @ 2019-07-09 18:39 UTC (permalink / raw) To: intel-gfx; +Cc: Jani Nikula, Lucas De Marchi Our past DDI-based Intel platforms have had a fixed DDI<->PHY mapping. Because of this, both the bspec documentation and our i915 code has used the term "port" when talking about either DDI's or PHY's; it was always easy to tell what terms like "Port A" were referring to from the context. Unfortunately this is starting to break down now that EHL allows PHY-A to be driven by either DDI-A or DDI-D. Is a setup with DDI-D driving PHY-A considered "Port A" or "Port D?" The answer depends on which register we're working with, and even the bspec doesn't do a great job of clarifying this. Let's try to be more explicit about whether we're talking about the DDI or the PHY on gen11+ by using 'port' to refer to the DDI and creating a new 'enum phy' namespace to refer to the PHY in use. This patch just adds the new PHY namespace, new phy-based versions of intel_port_is_*(), and a helper to convert a port to a PHY. Transitioning various areas of the code over to using the PHY namespace will be done in subsequent patches to make review easier. We'll remove the intel_port_is_*() functions at the end of the series when we transition all callers over to using the PHY-based versions. v2: - Convert a few more 'port' uses to 'phy.' (Sparse) v3: - Switch DDI_CLK_SEL() back to 'port.' (Jose) - Add a code comment clarifying why DPCLKA_CFGCR0_ICL needs to use PHY for its bit definitions, even though the register description is given in terms of DDI. - To avoid confusion, switch CNL's DPCLKA_CFGCR0 defines back to using port and create separate ICL+ definitions that work in terms of PHY. v4: - Rebase and resolve conflicts with Imre's TC series. - This patch now just adds the namespace and a few convenience functions; the important changes are now split out into separate patches to make review easier. Suggested-by: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 32 +++++++++++++++++++- drivers/gpu/drm/i915/display/intel_display.h | 16 ++++++++++ drivers/gpu/drm/i915/intel_drv.h | 2 ++ 3 files changed, 49 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index f07081815b80..43caee6d3c2f 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -6685,6 +6685,20 @@ bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port) return false; } +bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) +{ + if (phy == PHY_NONE) + return false; + + if (IS_ELKHARTLAKE(dev_priv)) + return phy <= PHY_C; + + if (INTEL_GEN(dev_priv) >= 11) + return phy <= PHY_B; + + return false; +} + bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port) { if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv)) @@ -6693,9 +6707,25 @@ bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port) return false; } +bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy) +{ + if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv)) + return phy >= PHY_C && phy <= PHY_F; + + return false; +} + +enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port) +{ + if (IS_ELKHARTLAKE(i915) && port == PORT_D) + return PHY_A; + + return (enum phy)port; +} + enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port) { - if (!intel_port_is_tc(dev_priv, port)) + if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port))) return PORT_TC_NONE; return port - PORT_C; diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index d296556ed82e..d53285fb883f 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -228,6 +228,21 @@ struct intel_link_m_n { u32 link_n; }; +enum phy { + PHY_NONE = -1, + + PHY_A = 0, + PHY_B, + PHY_C, + PHY_D, + PHY_E, + PHY_F, + + I915_MAX_PHYS +}; + +#define phy_name(a) ((a) + 'A') + #define for_each_pipe(__dev_priv, __p) \ for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) @@ -356,5 +371,6 @@ void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv); u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, u32 pixel_format, u64 modifier); bool intel_plane_can_remap(const struct intel_plane_state *plane_state); +enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port); #endif diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 24c63ed45c6f..815c26c0b98c 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1493,7 +1493,9 @@ void intel_encoder_destroy(struct drm_encoder *encoder); struct drm_display_mode * intel_encoder_current_mode(struct intel_encoder *encoder); bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port); +bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy); bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port); +bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy); enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port); int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v6 2/5] drm/i915/gen11: Program ICL_DPCLKA_CFGCR0 according to PHY 2019-07-09 18:39 [PATCH v6 0/5] EHL port programming Matt Roper 2019-07-09 18:39 ` [PATCH v6 1/5] drm/i915/gen11: Start distinguishing 'phy' from 'port' Matt Roper @ 2019-07-09 18:39 ` Matt Roper 2019-07-09 18:39 ` [PATCH v6 3/5] drm/i915/gen11: Convert combo PHY logic to use new 'enum phy' namespace Matt Roper ` (5 subsequent siblings) 7 siblings, 0 replies; 13+ messages in thread From: Matt Roper @ 2019-07-09 18:39 UTC (permalink / raw) To: intel-gfx Although the register name implies that it operates on DDI's, DPCLKA_CFGCR0_ICL actually needs to be programmed according to the PHY that's in use. I.e., when using EHL's DDI-D on combo PHY A, the bits described as "port A" in the bspec are what we need to set. The bspec clarifies: "[For EHL] DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA Clock Select chooses the PLL for both DDIA and DDID and drives port A in all cases." Also, since the CNL DPCLKA_CFGCR0 bit defines are still port-based, we create separate ICL-specific defines that accept the PHY rather than trying to share the same bit definitions between CNL and ICL. v5: Make icl_dpclka_cfgcr0_clk_off() take phy rather than port. When splitting the original patch the hunk to handle this wound up too late in the series. (Sparse) v6: Since we're already changing this code, s/DPCLKA_CFGCR0_ICL/ICL_DPCLKA_CFGCR0/ for consistency. (Jose) Bspec: 33148 Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> --- drivers/gpu/drm/i915/display/icl_dsi.c | 33 ++++++---- drivers/gpu/drm/i915/display/intel_ddi.c | 63 ++++++++++++-------- drivers/gpu/drm/i915/display/intel_display.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 12 ++-- 4 files changed, 67 insertions(+), 43 deletions(-) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index 3cf95c34143c..8f1324c2f539 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -560,14 +560,16 @@ static void gen11_dsi_gate_clocks(struct intel_encoder *encoder) struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); u32 tmp; enum port port; + enum phy phy; mutex_lock(&dev_priv->dpll_lock); - tmp = I915_READ(DPCLKA_CFGCR0_ICL); + tmp = I915_READ(ICL_DPCLKA_CFGCR0); for_each_dsi_port(port, intel_dsi->ports) { - tmp |= DPCLKA_CFGCR0_DDI_CLK_OFF(port); + phy = intel_port_to_phy(dev_priv, port); + tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); } - I915_WRITE(DPCLKA_CFGCR0_ICL, tmp); + I915_WRITE(ICL_DPCLKA_CFGCR0, tmp); mutex_unlock(&dev_priv->dpll_lock); } @@ -577,14 +579,16 @@ static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder) struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); u32 tmp; enum port port; + enum phy phy; mutex_lock(&dev_priv->dpll_lock); - tmp = I915_READ(DPCLKA_CFGCR0_ICL); + tmp = I915_READ(ICL_DPCLKA_CFGCR0); for_each_dsi_port(port, intel_dsi->ports) { - tmp &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port); + phy = intel_port_to_phy(dev_priv, port); + tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); } - I915_WRITE(DPCLKA_CFGCR0_ICL, tmp); + I915_WRITE(ICL_DPCLKA_CFGCR0, tmp); mutex_unlock(&dev_priv->dpll_lock); } @@ -595,23 +599,26 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder, struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); struct intel_shared_dpll *pll = crtc_state->shared_dpll; enum port port; + enum phy phy; u32 val; mutex_lock(&dev_priv->dpll_lock); - val = I915_READ(DPCLKA_CFGCR0_ICL); + val = I915_READ(ICL_DPCLKA_CFGCR0); for_each_dsi_port(port, intel_dsi->ports) { - val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); - val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port); + phy = intel_port_to_phy(dev_priv, port); + val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); + val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); } - I915_WRITE(DPCLKA_CFGCR0_ICL, val); + I915_WRITE(ICL_DPCLKA_CFGCR0, val); for_each_dsi_port(port, intel_dsi->ports) { - val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port); + phy = intel_port_to_phy(dev_priv, port); + val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); } - I915_WRITE(DPCLKA_CFGCR0_ICL, val); + I915_WRITE(ICL_DPCLKA_CFGCR0, val); - POSTING_READ(DPCLKA_CFGCR0_ICL); + POSTING_READ(ICL_DPCLKA_CFGCR0); mutex_unlock(&dev_priv->dpll_lock); } diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 30e48609db1d..b5bc00c4e3fe 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -2729,12 +2729,13 @@ u32 ddi_signal_levels(struct intel_dp *intel_dp) static inline u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv, - enum port port) + enum phy phy) { - if (intel_port_is_combophy(dev_priv, port)) { - return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port); - } else if (intel_port_is_tc(dev_priv, port)) { - enum tc_port tc_port = intel_port_to_tc(dev_priv, port); + if (intel_phy_is_combo(dev_priv, phy)) { + return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); + } else if (intel_phy_is_tc(dev_priv, phy)) { + enum tc_port tc_port = intel_port_to_tc(dev_priv, + (enum port)phy); return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port); } @@ -2747,23 +2748,33 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_shared_dpll *pll = crtc_state->shared_dpll; - enum port port = encoder->port; + enum phy phy = intel_port_to_phy(dev_priv, encoder->port); u32 val; mutex_lock(&dev_priv->dpll_lock); - val = I915_READ(DPCLKA_CFGCR0_ICL); - WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0); + val = I915_READ(ICL_DPCLKA_CFGCR0); + WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0); - if (intel_port_is_combophy(dev_priv, port)) { - val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); - val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port); - I915_WRITE(DPCLKA_CFGCR0_ICL, val); - POSTING_READ(DPCLKA_CFGCR0_ICL); + if (intel_phy_is_combo(dev_priv, phy)) { + /* + * Even though this register references DDIs, note that we + * want to pass the PHY rather than the port (DDI). For + * ICL, port=phy in all cases so it doesn't matter, but for + * EHL the bspec notes the following: + * + * "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA + * Clock Select chooses the PLL for both DDIA and DDID and + * drives port A in all cases." + */ + val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); + val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); + I915_WRITE(ICL_DPCLKA_CFGCR0, val); + POSTING_READ(ICL_DPCLKA_CFGCR0); } - val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port); - I915_WRITE(DPCLKA_CFGCR0_ICL, val); + val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy); + I915_WRITE(ICL_DPCLKA_CFGCR0, val); mutex_unlock(&dev_priv->dpll_lock); } @@ -2771,14 +2782,14 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder, static void icl_unmap_plls_to_ports(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - enum port port = encoder->port; + enum phy phy = intel_port_to_phy(dev_priv, encoder->port); u32 val; mutex_lock(&dev_priv->dpll_lock); - val = I915_READ(DPCLKA_CFGCR0_ICL); - val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port); - I915_WRITE(DPCLKA_CFGCR0_ICL, val); + val = I915_READ(ICL_DPCLKA_CFGCR0); + val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy); + I915_WRITE(ICL_DPCLKA_CFGCR0, val); mutex_unlock(&dev_priv->dpll_lock); } @@ -2836,11 +2847,13 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) ddi_clk_needed = false; } - val = I915_READ(DPCLKA_CFGCR0_ICL); + val = I915_READ(ICL_DPCLKA_CFGCR0); for_each_port_masked(port, port_mask) { + enum phy phy = intel_port_to_phy(dev_priv, port); + bool ddi_clk_ungated = !(val & icl_dpclka_cfgcr0_clk_off(dev_priv, - port)); + phy)); if (ddi_clk_needed == ddi_clk_ungated) continue; @@ -2852,10 +2865,10 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) if (WARN_ON(ddi_clk_needed)) continue; - DRM_NOTE("Port %c is disabled/in DSI mode with an ungated DDI clock, gate it\n", - port_name(port)); - val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port); - I915_WRITE(DPCLKA_CFGCR0_ICL, val); + DRM_NOTE("PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n", + phy_name(port)); + val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy); + I915_WRITE(ICL_DPCLKA_CFGCR0, val); } } diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 43caee6d3c2f..44c79f8bd028 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -10096,7 +10096,7 @@ static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv, u32 temp; if (intel_port_is_combophy(dev_priv, port)) { - temp = I915_READ(DPCLKA_CFGCR0_ICL) & + temp = I915_READ(ICL_DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port); port_dpll_id = ICL_PORT_DPLL_DEFAULT; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5898f59e3dd7..d3fc575a94db 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -9697,17 +9697,21 @@ enum skl_power_gate { * CNL Clocks */ #define DPCLKA_CFGCR0 _MMIO(0x6C200) -#define DPCLKA_CFGCR0_ICL _MMIO(0x164280) #define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_F ? 23 : \ (port) + 10)) -#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) + 10)) -#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \ - 21 : (tc_port) + 12)) #define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) == PORT_F ? 21 : \ (port) * 2) #define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)) #define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)) +#define ICL_DPCLKA_CFGCR0 _MMIO(0x164280) +#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24)) +#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \ + 21 : (tc_port) + 12)) +#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2) +#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) +#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) + /* CNL PLL */ #define DPLL0_ENABLE 0x46010 #define DPLL1_ENABLE 0x46014 -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v6 3/5] drm/i915/gen11: Convert combo PHY logic to use new 'enum phy' namespace 2019-07-09 18:39 [PATCH v6 0/5] EHL port programming Matt Roper 2019-07-09 18:39 ` [PATCH v6 1/5] drm/i915/gen11: Start distinguishing 'phy' from 'port' Matt Roper 2019-07-09 18:39 ` [PATCH v6 2/5] drm/i915/gen11: Program ICL_DPCLKA_CFGCR0 according to PHY Matt Roper @ 2019-07-09 18:39 ` Matt Roper 2019-09-04 13:42 ` Jani Nikula 2019-07-09 18:39 ` [PATCH v6 4/5] drm/i915: Transition port type checks to phy checks Matt Roper ` (4 subsequent siblings) 7 siblings, 1 reply; 13+ messages in thread From: Matt Roper @ 2019-07-09 18:39 UTC (permalink / raw) To: intel-gfx Convert the code that operates directly on gen11 combo PHY's to use the new namespace. Combo PHY registers are those named "ICL_PORT_*" plus ICL_DPHY_CHKN. Note that a lot of the PHY programming happens in the MIPI DSI code. For clarity I've added a for_each_dsi_phy() to loop over the phys used by DSI. Since DSI always uses A & B on gen11, port=phy in all cases so it doesn't actually matter which form we use in the DSI code. I've used the phy iterator in code that's explicitly working with the combo PHY, but left the rest of the DSI code using the port iterator and namespace to minimize patch deltas. We can switch the rest of the DSI code over to use phy terminology later if this winds up being too confusing. v6: Drop an include of drm/i915_drm.h; that was previously included just for the definition of 'enum port' which this patch removes the need for. (Jose) Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> --- drivers/gpu/drm/i915/display/icl_dsi.c | 127 ++++++++-------- .../gpu/drm/i915/display/intel_combo_phy.c | 143 +++++++++--------- .../gpu/drm/i915/display/intel_combo_phy.h | 4 +- drivers/gpu/drm/i915/display/intel_ddi.c | 45 +++--- drivers/gpu/drm/i915/display/intel_display.h | 4 + .../drm/i915/display/intel_display_power.c | 16 +- drivers/gpu/drm/i915/display/intel_dsi.h | 12 +- drivers/gpu/drm/i915/i915_reg.h | 74 ++++----- 8 files changed, 213 insertions(+), 212 deletions(-) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index 8f1324c2f539..4d952accfaaa 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -202,63 +202,62 @@ static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); - enum port port; + enum phy phy; u32 tmp; int lane; - for_each_dsi_port(port, intel_dsi->ports) { - + for_each_dsi_phy(phy, intel_dsi->phys) { /* * Program voltage swing and pre-emphasis level values as per * table in BSPEC under DDI buffer programing */ - tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port)); + tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK); tmp |= SCALING_MODE_SEL(0x2); tmp |= TAP2_DISABLE | TAP3_DISABLE; tmp |= RTERM_SELECT(0x6); - I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp); + I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), tmp); - tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port)); + tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy)); tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK); tmp |= SCALING_MODE_SEL(0x2); tmp |= TAP2_DISABLE | TAP3_DISABLE; tmp |= RTERM_SELECT(0x6); - I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp); + I915_WRITE(ICL_PORT_TX_DW5_AUX(phy), tmp); - tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port)); + tmp = I915_READ(ICL_PORT_TX_DW2_LN0(phy)); tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | RCOMP_SCALAR_MASK); tmp |= SWING_SEL_UPPER(0x2); tmp |= SWING_SEL_LOWER(0x2); tmp |= RCOMP_SCALAR(0x98); - I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp); + I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), tmp); - tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port)); + tmp = I915_READ(ICL_PORT_TX_DW2_AUX(phy)); tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | RCOMP_SCALAR_MASK); tmp |= SWING_SEL_UPPER(0x2); tmp |= SWING_SEL_LOWER(0x2); tmp |= RCOMP_SCALAR(0x98); - I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp); + I915_WRITE(ICL_PORT_TX_DW2_AUX(phy), tmp); - tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port)); + tmp = I915_READ(ICL_PORT_TX_DW4_AUX(phy)); tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK); tmp |= POST_CURSOR_1(0x0); tmp |= POST_CURSOR_2(0x0); tmp |= CURSOR_COEFF(0x3f); - I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp); + I915_WRITE(ICL_PORT_TX_DW4_AUX(phy), tmp); for (lane = 0; lane <= 3; lane++) { /* Bspec: must not use GRP register for write */ - tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, port)); + tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, phy)); tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK); tmp |= POST_CURSOR_1(0x0); tmp |= POST_CURSOR_2(0x0); tmp |= CURSOR_COEFF(0x3f); - I915_WRITE(ICL_PORT_TX_DW4_LN(lane, port), tmp); + I915_WRITE(ICL_PORT_TX_DW4_LN(lane, phy), tmp); } } } @@ -364,10 +363,10 @@ static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); - enum port port; + enum phy phy; - for_each_dsi_port(port, intel_dsi->ports) - intel_combo_phy_power_up_lanes(dev_priv, port, true, + for_each_dsi_phy(phy, intel_dsi->phys) + intel_combo_phy_power_up_lanes(dev_priv, phy, true, intel_dsi->lane_count, false); } @@ -375,46 +374,46 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); - enum port port; + enum phy phy; u32 tmp; int lane; /* Step 4b(i) set loadgen select for transmit and aux lanes */ - for_each_dsi_port(port, intel_dsi->ports) { - tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port)); + for_each_dsi_phy(phy, intel_dsi->phys) { + tmp = I915_READ(ICL_PORT_TX_DW4_AUX(phy)); tmp &= ~LOADGEN_SELECT; - I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp); + I915_WRITE(ICL_PORT_TX_DW4_AUX(phy), tmp); for (lane = 0; lane <= 3; lane++) { - tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, port)); + tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, phy)); tmp &= ~LOADGEN_SELECT; if (lane != 2) tmp |= LOADGEN_SELECT; - I915_WRITE(ICL_PORT_TX_DW4_LN(lane, port), tmp); + I915_WRITE(ICL_PORT_TX_DW4_LN(lane, phy), tmp); } } /* Step 4b(ii) set latency optimization for transmit and aux lanes */ - for_each_dsi_port(port, intel_dsi->ports) { - tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port)); + for_each_dsi_phy(phy, intel_dsi->phys) { + tmp = I915_READ(ICL_PORT_TX_DW2_AUX(phy)); tmp &= ~FRC_LATENCY_OPTIM_MASK; tmp |= FRC_LATENCY_OPTIM_VAL(0x5); - I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp); - tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port)); + I915_WRITE(ICL_PORT_TX_DW2_AUX(phy), tmp); + tmp = I915_READ(ICL_PORT_TX_DW2_LN0(phy)); tmp &= ~FRC_LATENCY_OPTIM_MASK; tmp |= FRC_LATENCY_OPTIM_VAL(0x5); - I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp); + I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), tmp); /* For EHL set latency optimization for PCS_DW1 lanes */ if (IS_ELKHARTLAKE(dev_priv)) { - tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(port)); + tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(phy)); tmp &= ~LATENCY_OPTIM_MASK; tmp |= LATENCY_OPTIM_VAL(0); - I915_WRITE(ICL_PORT_PCS_DW1_AUX(port), tmp); + I915_WRITE(ICL_PORT_PCS_DW1_AUX(phy), tmp); - tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(port)); + tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(phy)); tmp &= ~LATENCY_OPTIM_MASK; tmp |= LATENCY_OPTIM_VAL(0x1); - I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), tmp); + I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), tmp); } } @@ -425,16 +424,16 @@ static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder) struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); u32 tmp; - enum port port; + enum phy phy; /* clear common keeper enable bit */ - for_each_dsi_port(port, intel_dsi->ports) { - tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(port)); + for_each_dsi_phy(phy, intel_dsi->phys) { + tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(phy)); tmp &= ~COMMON_KEEPER_EN; - I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), tmp); - tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(port)); + I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), tmp); + tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(phy)); tmp &= ~COMMON_KEEPER_EN; - I915_WRITE(ICL_PORT_PCS_DW1_AUX(port), tmp); + I915_WRITE(ICL_PORT_PCS_DW1_AUX(phy), tmp); } /* @@ -442,33 +441,33 @@ static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder) * Note: loadgen select program is done * as part of lane phy sequence configuration */ - for_each_dsi_port(port, intel_dsi->ports) { - tmp = I915_READ(ICL_PORT_CL_DW5(port)); + for_each_dsi_phy(phy, intel_dsi->phys) { + tmp = I915_READ(ICL_PORT_CL_DW5(phy)); tmp |= SUS_CLOCK_CONFIG; - I915_WRITE(ICL_PORT_CL_DW5(port), tmp); + I915_WRITE(ICL_PORT_CL_DW5(phy), tmp); } /* Clear training enable to change swing values */ - for_each_dsi_port(port, intel_dsi->ports) { - tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port)); + for_each_dsi_phy(phy, intel_dsi->phys) { + tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); tmp &= ~TX_TRAINING_EN; - I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp); - tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port)); + I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), tmp); + tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy)); tmp &= ~TX_TRAINING_EN; - I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp); + I915_WRITE(ICL_PORT_TX_DW5_AUX(phy), tmp); } /* Program swing and de-emphasis */ dsi_program_swing_and_deemphasis(encoder); /* Set training enable to trigger update */ - for_each_dsi_port(port, intel_dsi->ports) { - tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port)); + for_each_dsi_phy(phy, intel_dsi->phys) { + tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); tmp |= TX_TRAINING_EN; - I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp); - tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port)); + I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), tmp); + tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy)); tmp |= TX_TRAINING_EN; - I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp); + I915_WRITE(ICL_PORT_TX_DW5_AUX(phy), tmp); } } @@ -497,6 +496,7 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder) struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); u32 tmp; enum port port; + enum phy phy; /* Program T-INIT master registers */ for_each_dsi_port(port, intel_dsi->ports) { @@ -546,10 +546,10 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder) } if (IS_ELKHARTLAKE(dev_priv)) { - for_each_dsi_port(port, intel_dsi->ports) { - tmp = I915_READ(ICL_DPHY_CHKN(port)); + for_each_dsi_phy(phy, intel_dsi->phys) { + tmp = I915_READ(ICL_DPHY_CHKN(phy)); tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP; - I915_WRITE(ICL_DPHY_CHKN(port), tmp); + I915_WRITE(ICL_DPHY_CHKN(phy), tmp); } } } @@ -559,15 +559,12 @@ static void gen11_dsi_gate_clocks(struct intel_encoder *encoder) struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); u32 tmp; - enum port port; enum phy phy; mutex_lock(&dev_priv->dpll_lock); tmp = I915_READ(ICL_DPCLKA_CFGCR0); - for_each_dsi_port(port, intel_dsi->ports) { - phy = intel_port_to_phy(dev_priv, port); + for_each_dsi_phy(phy, intel_dsi->phys) tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); - } I915_WRITE(ICL_DPCLKA_CFGCR0, tmp); mutex_unlock(&dev_priv->dpll_lock); @@ -578,15 +575,12 @@ static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder) struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); u32 tmp; - enum port port; enum phy phy; mutex_lock(&dev_priv->dpll_lock); tmp = I915_READ(ICL_DPCLKA_CFGCR0); - for_each_dsi_port(port, intel_dsi->ports) { - phy = intel_port_to_phy(dev_priv, port); + for_each_dsi_phy(phy, intel_dsi->phys) tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); - } I915_WRITE(ICL_DPCLKA_CFGCR0, tmp); mutex_unlock(&dev_priv->dpll_lock); @@ -598,22 +592,19 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); struct intel_shared_dpll *pll = crtc_state->shared_dpll; - enum port port; enum phy phy; u32 val; mutex_lock(&dev_priv->dpll_lock); val = I915_READ(ICL_DPCLKA_CFGCR0); - for_each_dsi_port(port, intel_dsi->ports) { - phy = intel_port_to_phy(dev_priv, port); + for_each_dsi_phy(phy, intel_dsi->phys) { val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); } I915_WRITE(ICL_DPCLKA_CFGCR0, val); - for_each_dsi_port(port, intel_dsi->ports) { - phy = intel_port_to_phy(dev_priv, port); + for_each_dsi_phy(phy, intel_dsi->phys) { val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); } I915_WRITE(ICL_DPCLKA_CFGCR0, val); diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c index d3d5244765e6..ac8218a040ab 100644 --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c @@ -6,13 +6,13 @@ #include "intel_combo_phy.h" #include "intel_drv.h" -#define for_each_combo_port(__dev_priv, __port) \ - for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \ - for_each_if(intel_port_is_combophy(__dev_priv, __port)) +#define for_each_combo_phy(__dev_priv, __phy) \ + for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \ + for_each_if(intel_phy_is_combo(__dev_priv, __phy)) -#define for_each_combo_port_reverse(__dev_priv, __port) \ - for ((__port) = I915_MAX_PORTS; (__port)-- > PORT_A;) \ - for_each_if(intel_port_is_combophy(__dev_priv, __port)) +#define for_each_combo_phy_reverse(__dev_priv, __phy) \ + for ((__phy) = I915_MAX_PHYS; (__phy)-- > PHY_A;) \ + for_each_if(intel_phy_is_combo(__dev_priv, __phy)) enum { PROCMON_0_85V_DOT_0, @@ -38,18 +38,17 @@ static const struct cnl_procmon { }; /* - * CNL has just one set of registers, while ICL has two sets: one for port A and - * the other for port B. The CNL registers are equivalent to the ICL port A - * registers, that's why we call the ICL macros even though the function has CNL - * on its name. + * CNL has just one set of registers, while gen11 has a set for each combo PHY. + * The CNL registers are equivalent to the gen11 PHY A registers, that's why we + * call the ICL macros even though the function has CNL on its name. */ static const struct cnl_procmon * -cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum port port) +cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy) { const struct cnl_procmon *procmon; u32 val; - val = I915_READ(ICL_PORT_COMP_DW3(port)); + val = I915_READ(ICL_PORT_COMP_DW3(phy)); switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) { default: MISSING_CASE(val); @@ -75,32 +74,32 @@ cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum port port) } static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv, - enum port port) + enum phy phy) { const struct cnl_procmon *procmon; u32 val; - procmon = cnl_get_procmon_ref_values(dev_priv, port); + procmon = cnl_get_procmon_ref_values(dev_priv, phy); - val = I915_READ(ICL_PORT_COMP_DW1(port)); + val = I915_READ(ICL_PORT_COMP_DW1(phy)); val &= ~((0xff << 16) | 0xff); val |= procmon->dw1; - I915_WRITE(ICL_PORT_COMP_DW1(port), val); + I915_WRITE(ICL_PORT_COMP_DW1(phy), val); - I915_WRITE(ICL_PORT_COMP_DW9(port), procmon->dw9); - I915_WRITE(ICL_PORT_COMP_DW10(port), procmon->dw10); + I915_WRITE(ICL_PORT_COMP_DW9(phy), procmon->dw9); + I915_WRITE(ICL_PORT_COMP_DW10(phy), procmon->dw10); } static bool check_phy_reg(struct drm_i915_private *dev_priv, - enum port port, i915_reg_t reg, u32 mask, + enum phy phy, i915_reg_t reg, u32 mask, u32 expected_val) { u32 val = I915_READ(reg); if ((val & mask) != expected_val) { - DRM_DEBUG_DRIVER("Port %c combo PHY reg %08x state mismatch: " + DRM_DEBUG_DRIVER("Combo PHY %c reg %08x state mismatch: " "current %08x mask %08x expected %08x\n", - port_name(port), + phy_name(phy), reg.reg, val, mask, expected_val); return false; } @@ -109,18 +108,18 @@ static bool check_phy_reg(struct drm_i915_private *dev_priv, } static bool cnl_verify_procmon_ref_values(struct drm_i915_private *dev_priv, - enum port port) + enum phy phy) { const struct cnl_procmon *procmon; bool ret; - procmon = cnl_get_procmon_ref_values(dev_priv, port); + procmon = cnl_get_procmon_ref_values(dev_priv, phy); - ret = check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW1(port), + ret = check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW1(phy), (0xff << 16) | 0xff, procmon->dw1); - ret &= check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW9(port), + ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW9(phy), -1U, procmon->dw9); - ret &= check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW10(port), + ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW10(phy), -1U, procmon->dw10); return ret; @@ -134,15 +133,15 @@ static bool cnl_combo_phy_enabled(struct drm_i915_private *dev_priv) static bool cnl_combo_phy_verify_state(struct drm_i915_private *dev_priv) { - enum port port = PORT_A; + enum phy phy = PHY_A; bool ret; if (!cnl_combo_phy_enabled(dev_priv)) return false; - ret = cnl_verify_procmon_ref_values(dev_priv, port); + ret = cnl_verify_procmon_ref_values(dev_priv, phy); - ret &= check_phy_reg(dev_priv, port, CNL_PORT_CL1CM_DW5, + ret &= check_phy_reg(dev_priv, phy, CNL_PORT_CL1CM_DW5, CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE); return ret; @@ -157,7 +156,7 @@ static void cnl_combo_phys_init(struct drm_i915_private *dev_priv) I915_WRITE(CHICKEN_MISC_2, val); /* Dummy PORT_A to get the correct CNL register from the ICL macro */ - cnl_set_procmon_ref_values(dev_priv, PORT_A); + cnl_set_procmon_ref_values(dev_priv, PHY_A); val = I915_READ(CNL_PORT_COMP_DW0); val |= COMP_INIT; @@ -181,39 +180,39 @@ static void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv) } static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv, - enum port port) + enum phy phy) { /* The PHY C added by EHL has no PHY_MISC register */ - if (IS_ELKHARTLAKE(dev_priv) && port == PORT_C) - return I915_READ(ICL_PORT_COMP_DW0(port)) & COMP_INIT; + if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C) + return I915_READ(ICL_PORT_COMP_DW0(phy)) & COMP_INIT; else - return !(I915_READ(ICL_PHY_MISC(port)) & + return !(I915_READ(ICL_PHY_MISC(phy)) & ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) && - (I915_READ(ICL_PORT_COMP_DW0(port)) & COMP_INIT); + (I915_READ(ICL_PORT_COMP_DW0(phy)) & COMP_INIT); } static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv, - enum port port) + enum phy phy) { bool ret; - if (!icl_combo_phy_enabled(dev_priv, port)) + if (!icl_combo_phy_enabled(dev_priv, phy)) return false; - ret = cnl_verify_procmon_ref_values(dev_priv, port); + ret = cnl_verify_procmon_ref_values(dev_priv, phy); - if (port == PORT_A) - ret &= check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW8(port), + if (phy == PHY_A) + ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy), IREFGEN, IREFGEN); - ret &= check_phy_reg(dev_priv, port, ICL_PORT_CL_DW5(port), + ret &= check_phy_reg(dev_priv, phy, ICL_PORT_CL_DW5(phy), CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE); return ret; } void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv, - enum port port, bool is_dsi, + enum phy phy, bool is_dsi, int lane_count, bool lane_reversal) { u8 lane_mask; @@ -258,10 +257,10 @@ void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv, } } - val = I915_READ(ICL_PORT_CL_DW10(port)); + val = I915_READ(ICL_PORT_CL_DW10(phy)); val &= ~PWR_DOWN_LN_MASK; val |= lane_mask << PWR_DOWN_LN_SHIFT; - I915_WRITE(ICL_PORT_CL_DW10(port), val); + I915_WRITE(ICL_PORT_CL_DW10(phy), val); } static u32 ehl_combo_phy_a_mux(struct drm_i915_private *i915, u32 val) @@ -292,14 +291,14 @@ static u32 ehl_combo_phy_a_mux(struct drm_i915_private *i915, u32 val) static void icl_combo_phys_init(struct drm_i915_private *dev_priv) { - enum port port; + enum phy phy; - for_each_combo_port(dev_priv, port) { + for_each_combo_phy(dev_priv, phy) { u32 val; - if (icl_combo_phy_verify_state(dev_priv, port)) { - DRM_DEBUG_DRIVER("Port %c combo PHY already enabled, won't reprogram it.\n", - port_name(port)); + if (icl_combo_phy_verify_state(dev_priv, phy)) { + DRM_DEBUG_DRIVER("Combo PHY %c already enabled, won't reprogram it.\n", + phy_name(phy)); continue; } @@ -308,7 +307,7 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv) * register for it and no need to program the * DE_IO_COMP_PWR_DOWN setting on PHY C. */ - if (IS_ELKHARTLAKE(dev_priv) && port == PORT_C) + if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C) goto skip_phy_misc; /* @@ -319,59 +318,59 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv) * based on whether our VBT indicates the presence of any * "internal" child devices. */ - val = I915_READ(ICL_PHY_MISC(port)); - if (IS_ELKHARTLAKE(dev_priv) && port == PORT_A) + val = I915_READ(ICL_PHY_MISC(phy)); + if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_A) val = ehl_combo_phy_a_mux(dev_priv, val); val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN; - I915_WRITE(ICL_PHY_MISC(port), val); + I915_WRITE(ICL_PHY_MISC(phy), val); skip_phy_misc: - cnl_set_procmon_ref_values(dev_priv, port); + cnl_set_procmon_ref_values(dev_priv, phy); - if (port == PORT_A) { - val = I915_READ(ICL_PORT_COMP_DW8(port)); + if (phy == PHY_A) { + val = I915_READ(ICL_PORT_COMP_DW8(phy)); val |= IREFGEN; - I915_WRITE(ICL_PORT_COMP_DW8(port), val); + I915_WRITE(ICL_PORT_COMP_DW8(phy), val); } - val = I915_READ(ICL_PORT_COMP_DW0(port)); + val = I915_READ(ICL_PORT_COMP_DW0(phy)); val |= COMP_INIT; - I915_WRITE(ICL_PORT_COMP_DW0(port), val); + I915_WRITE(ICL_PORT_COMP_DW0(phy), val); - val = I915_READ(ICL_PORT_CL_DW5(port)); + val = I915_READ(ICL_PORT_CL_DW5(phy)); val |= CL_POWER_DOWN_ENABLE; - I915_WRITE(ICL_PORT_CL_DW5(port), val); + I915_WRITE(ICL_PORT_CL_DW5(phy), val); } } static void icl_combo_phys_uninit(struct drm_i915_private *dev_priv) { - enum port port; + enum phy phy; - for_each_combo_port_reverse(dev_priv, port) { + for_each_combo_phy_reverse(dev_priv, phy) { u32 val; - if (port == PORT_A && - !icl_combo_phy_verify_state(dev_priv, port)) - DRM_WARN("Port %c combo PHY HW state changed unexpectedly\n", - port_name(port)); + if (phy == PHY_A && + !icl_combo_phy_verify_state(dev_priv, phy)) + DRM_WARN("Combo PHY %c HW state changed unexpectedly\n", + phy_name(phy)); /* * Although EHL adds a combo PHY C, there's no PHY_MISC * register for it and no need to program the * DE_IO_COMP_PWR_DOWN setting on PHY C. */ - if (IS_ELKHARTLAKE(dev_priv) && port == PORT_C) + if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C) goto skip_phy_misc; - val = I915_READ(ICL_PHY_MISC(port)); + val = I915_READ(ICL_PHY_MISC(phy)); val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN; - I915_WRITE(ICL_PHY_MISC(port), val); + I915_WRITE(ICL_PHY_MISC(phy), val); skip_phy_misc: - val = I915_READ(ICL_PORT_COMP_DW0(port)); + val = I915_READ(ICL_PORT_COMP_DW0(phy)); val &= ~COMP_INIT; - I915_WRITE(ICL_PORT_COMP_DW0(port), val); + I915_WRITE(ICL_PORT_COMP_DW0(phy), val); } } diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.h b/drivers/gpu/drm/i915/display/intel_combo_phy.h index e6e195a83b19..660886f86c59 100644 --- a/drivers/gpu/drm/i915/display/intel_combo_phy.h +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.h @@ -7,14 +7,14 @@ #define __INTEL_COMBO_PHY_H__ #include <linux/types.h> -#include <drm/i915_drm.h> struct drm_i915_private; +enum phy; void intel_combo_phy_init(struct drm_i915_private *dev_priv); void intel_combo_phy_uninit(struct drm_i915_private *dev_priv); void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv, - enum port port, bool is_dsi, + enum phy phy, bool is_dsi, int lane_count, bool lane_reversal); #endif /* __INTEL_COMBO_PHY_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index b5bc00c4e3fe..d9ea58038642 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -2414,7 +2414,7 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, } static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, - u32 level, enum port port, int type, + u32 level, enum phy phy, int type, int rate) { const struct cnl_ddi_buf_trans *ddi_translations = NULL; @@ -2432,41 +2432,41 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, } /* Set PORT_TX_DW5 */ - val = I915_READ(ICL_PORT_TX_DW5_LN0(port)); + val = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | TAP2_DISABLE | TAP3_DISABLE); val |= SCALING_MODE_SEL(0x2); val |= RTERM_SELECT(0x6); val |= TAP3_DISABLE; - I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val); + I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val); /* Program PORT_TX_DW2 */ - val = I915_READ(ICL_PORT_TX_DW2_LN0(port)); + val = I915_READ(ICL_PORT_TX_DW2_LN0(phy)); val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | RCOMP_SCALAR_MASK); val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); /* Program Rcomp scalar for every table entry */ val |= RCOMP_SCALAR(0x98); - I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val); + I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), val); /* Program PORT_TX_DW4 */ /* We cannot write to GRP. It would overwrite individual loadgen. */ for (ln = 0; ln <= 3; ln++) { - val = I915_READ(ICL_PORT_TX_DW4_LN(ln, port)); + val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy)); val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK); val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); - I915_WRITE(ICL_PORT_TX_DW4_LN(ln, port), val); + I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val); } /* Program PORT_TX_DW7 */ - val = I915_READ(ICL_PORT_TX_DW7_LN0(port)); + val = I915_READ(ICL_PORT_TX_DW7_LN0(phy)); val &= ~N_SCALAR_MASK; val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); - I915_WRITE(ICL_PORT_TX_DW7_GRP(port), val); + I915_WRITE(ICL_PORT_TX_DW7_GRP(phy), val); } static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, @@ -2474,7 +2474,7 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, enum intel_output_type type) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - enum port port = encoder->port; + enum phy phy = intel_port_to_phy(dev_priv, encoder->port); int width = 0; int rate = 0; u32 val; @@ -2495,12 +2495,12 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, * set PORT_PCS_DW1 cmnkeeper_enable to 1b, * else clear to 0b. */ - val = I915_READ(ICL_PORT_PCS_DW1_LN0(port)); + val = I915_READ(ICL_PORT_PCS_DW1_LN0(phy)); if (type == INTEL_OUTPUT_HDMI) val &= ~COMMON_KEEPER_EN; else val |= COMMON_KEEPER_EN; - I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), val); + I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), val); /* 2. Program loadgen select */ /* @@ -2510,33 +2510,33 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) */ for (ln = 0; ln <= 3; ln++) { - val = I915_READ(ICL_PORT_TX_DW4_LN(ln, port)); + val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy)); val &= ~LOADGEN_SELECT; if ((rate <= 600000 && width == 4 && ln >= 1) || (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { val |= LOADGEN_SELECT; } - I915_WRITE(ICL_PORT_TX_DW4_LN(ln, port), val); + I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val); } /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ - val = I915_READ(ICL_PORT_CL_DW5(port)); + val = I915_READ(ICL_PORT_CL_DW5(phy)); val |= SUS_CLOCK_CONFIG; - I915_WRITE(ICL_PORT_CL_DW5(port), val); + I915_WRITE(ICL_PORT_CL_DW5(phy), val); /* 4. Clear training enable to change swing values */ - val = I915_READ(ICL_PORT_TX_DW5_LN0(port)); + val = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); val &= ~TX_TRAINING_EN; - I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val); + I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val); /* 5. Program swing and de-emphasis */ - icl_ddi_combo_vswing_program(dev_priv, level, port, type, rate); + icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate); /* 6. Set training enable to trigger update */ - val = I915_READ(ICL_PORT_TX_DW5_LN0(port)); + val = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); val |= TX_TRAINING_EN; - I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val); + I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val); } static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, @@ -3121,6 +3121,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum port port = encoder->port; + enum phy phy = intel_port_to_phy(dev_priv, port); struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); int level = intel_ddi_dp_level(intel_dp); @@ -3156,7 +3157,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; - intel_combo_phy_power_up_lanes(dev_priv, port, false, + intel_combo_phy_power_up_lanes(dev_priv, phy, false, crtc_state->lane_count, lane_reversal); } diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index d53285fb883f..8a4a57ef82a2 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -268,6 +268,10 @@ enum phy { for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \ for_each_if((__ports_mask) & BIT(__port)) +#define for_each_phy_masked(__phy, __phys_mask) \ + for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \ + for_each_if((__phys_mask) & BIT(__phy)) + #define for_each_crtc(dev, crtc) \ list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 7437fc71d289..a24d1859b37b 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -397,7 +397,7 @@ static void hsw_power_well_disable(struct drm_i915_private *dev_priv, hsw_wait_for_power_well_disable(dev_priv, power_well); } -#define ICL_AUX_PW_TO_PORT(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A) +#define ICL_AUX_PW_TO_PHY(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A) static void icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, @@ -405,21 +405,21 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, { const struct i915_power_well_regs *regs = power_well->desc->hsw.regs; int pw_idx = power_well->desc->hsw.idx; - enum port port = ICL_AUX_PW_TO_PORT(pw_idx); + enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx); u32 val; val = I915_READ(regs->driver); I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx)); - val = I915_READ(ICL_PORT_CL_DW12(port)); - I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX); + val = I915_READ(ICL_PORT_CL_DW12(phy)); + I915_WRITE(ICL_PORT_CL_DW12(phy), val | ICL_LANE_ENABLE_AUX); hsw_wait_for_power_well_enable(dev_priv, power_well); /* Display WA #1178: icl */ if (IS_ICELAKE(dev_priv) && pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B && - !intel_bios_is_port_edp(dev_priv, port)) { + !intel_bios_is_port_edp(dev_priv, (enum port)phy)) { val = I915_READ(ICL_AUX_ANAOVRD1(pw_idx)); val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS; I915_WRITE(ICL_AUX_ANAOVRD1(pw_idx), val); @@ -432,11 +432,11 @@ icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv, { const struct i915_power_well_regs *regs = power_well->desc->hsw.regs; int pw_idx = power_well->desc->hsw.idx; - enum port port = ICL_AUX_PW_TO_PORT(pw_idx); + enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx); u32 val; - val = I915_READ(ICL_PORT_CL_DW12(port)); - I915_WRITE(ICL_PORT_CL_DW12(port), val & ~ICL_LANE_ENABLE_AUX); + val = I915_READ(ICL_PORT_CL_DW12(phy)); + I915_WRITE(ICL_PORT_CL_DW12(phy), val & ~ICL_LANE_ENABLE_AUX); val = I915_READ(regs->driver); I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx)); diff --git a/drivers/gpu/drm/i915/display/intel_dsi.h b/drivers/gpu/drm/i915/display/intel_dsi.h index 6d20434636cd..1cd24bd46518 100644 --- a/drivers/gpu/drm/i915/display/intel_dsi.h +++ b/drivers/gpu/drm/i915/display/intel_dsi.h @@ -49,8 +49,11 @@ struct intel_dsi { struct intel_connector *attached_connector; - /* bit mask of ports being driven */ - u16 ports; + /* bit mask of ports (vlv dsi) or phys (icl dsi) being driven */ + union { + u16 ports; /* VLV DSI */ + u16 phys; /* ICL DSI */ + }; /* if true, use HS mode, otherwise LP */ bool hs; @@ -132,7 +135,10 @@ static inline struct intel_dsi_host *to_intel_dsi_host(struct mipi_dsi_host *h) return container_of(h, struct intel_dsi_host, base); } -#define for_each_dsi_port(__port, __ports_mask) for_each_port_masked(__port, __ports_mask) +#define for_each_dsi_port(__port, __ports_mask) \ + for_each_port_masked(__port, __ports_mask) +#define for_each_dsi_phy(__phy, __phys_mask) \ + for_each_phy_masked(__phy, __phys_mask) static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder) { diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d3fc575a94db..95b9ca1fda2e 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1794,20 +1794,20 @@ enum i915_power_well_id { #define _ICL_COMBOPHY_A 0x162000 #define _ICL_COMBOPHY_B 0x6C000 #define _EHL_COMBOPHY_C 0x160000 -#define _ICL_COMBOPHY(port) _PICK(port, _ICL_COMBOPHY_A, \ +#define _ICL_COMBOPHY(phy) _PICK(phy, _ICL_COMBOPHY_A, \ _ICL_COMBOPHY_B, \ _EHL_COMBOPHY_C) /* CNL/ICL Port CL_DW registers */ -#define _ICL_PORT_CL_DW(dw, port) (_ICL_COMBOPHY(port) + \ +#define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \ 4 * (dw)) #define CNL_PORT_CL1CM_DW5 _MMIO(0x162014) -#define ICL_PORT_CL_DW5(port) _MMIO(_ICL_PORT_CL_DW(5, port)) +#define ICL_PORT_CL_DW5(phy) _MMIO(_ICL_PORT_CL_DW(5, phy)) #define CL_POWER_DOWN_ENABLE (1 << 4) #define SUS_CLOCK_CONFIG (3 << 0) -#define ICL_PORT_CL_DW10(port) _MMIO(_ICL_PORT_CL_DW(10, port)) +#define ICL_PORT_CL_DW10(phy) _MMIO(_ICL_PORT_CL_DW(10, phy)) #define PG_SEQ_DELAY_OVERRIDE_MASK (3 << 25) #define PG_SEQ_DELAY_OVERRIDE_SHIFT 25 #define PG_SEQ_DELAY_OVERRIDE_ENABLE (1 << 24) @@ -1822,23 +1822,23 @@ enum i915_power_well_id { #define PWR_DOWN_LN_MASK (0xf << 4) #define PWR_DOWN_LN_SHIFT 4 -#define ICL_PORT_CL_DW12(port) _MMIO(_ICL_PORT_CL_DW(12, port)) +#define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy)) #define ICL_LANE_ENABLE_AUX (1 << 0) /* CNL/ICL Port COMP_DW registers */ #define _ICL_PORT_COMP 0x100 -#define _ICL_PORT_COMP_DW(dw, port) (_ICL_COMBOPHY(port) + \ +#define _ICL_PORT_COMP_DW(dw, phy) (_ICL_COMBOPHY(phy) + \ _ICL_PORT_COMP + 4 * (dw)) #define CNL_PORT_COMP_DW0 _MMIO(0x162100) -#define ICL_PORT_COMP_DW0(port) _MMIO(_ICL_PORT_COMP_DW(0, port)) +#define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy)) #define COMP_INIT (1 << 31) #define CNL_PORT_COMP_DW1 _MMIO(0x162104) -#define ICL_PORT_COMP_DW1(port) _MMIO(_ICL_PORT_COMP_DW(1, port)) +#define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy)) #define CNL_PORT_COMP_DW3 _MMIO(0x16210c) -#define ICL_PORT_COMP_DW3(port) _MMIO(_ICL_PORT_COMP_DW(3, port)) +#define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy)) #define PROCESS_INFO_DOT_0 (0 << 26) #define PROCESS_INFO_DOT_1 (1 << 26) #define PROCESS_INFO_DOT_4 (2 << 26) @@ -1850,14 +1850,14 @@ enum i915_power_well_id { #define VOLTAGE_INFO_MASK (3 << 24) #define VOLTAGE_INFO_SHIFT 24 -#define ICL_PORT_COMP_DW8(port) _MMIO(_ICL_PORT_COMP_DW(8, port)) +#define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy)) #define IREFGEN (1 << 24) #define CNL_PORT_COMP_DW9 _MMIO(0x162124) -#define ICL_PORT_COMP_DW9(port) _MMIO(_ICL_PORT_COMP_DW(9, port)) +#define ICL_PORT_COMP_DW9(phy) _MMIO(_ICL_PORT_COMP_DW(9, phy)) #define CNL_PORT_COMP_DW10 _MMIO(0x162128) -#define ICL_PORT_COMP_DW10(port) _MMIO(_ICL_PORT_COMP_DW(10, port)) +#define ICL_PORT_COMP_DW10(phy) _MMIO(_ICL_PORT_COMP_DW(10, phy)) /* CNL/ICL Port PCS registers */ #define _CNL_PORT_PCS_DW1_GRP_AE 0x162304 @@ -1870,14 +1870,14 @@ enum i915_power_well_id { #define _CNL_PORT_PCS_DW1_LN0_C 0x162C04 #define _CNL_PORT_PCS_DW1_LN0_D 0x162E04 #define _CNL_PORT_PCS_DW1_LN0_F 0x162804 -#define CNL_PORT_PCS_DW1_GRP(port) _MMIO(_PICK(port, \ +#define CNL_PORT_PCS_DW1_GRP(phy) _MMIO(_PICK(phy, \ _CNL_PORT_PCS_DW1_GRP_AE, \ _CNL_PORT_PCS_DW1_GRP_B, \ _CNL_PORT_PCS_DW1_GRP_C, \ _CNL_PORT_PCS_DW1_GRP_D, \ _CNL_PORT_PCS_DW1_GRP_AE, \ _CNL_PORT_PCS_DW1_GRP_F)) -#define CNL_PORT_PCS_DW1_LN0(port) _MMIO(_PICK(port, \ +#define CNL_PORT_PCS_DW1_LN0(phy) _MMIO(_PICK(phy, \ _CNL_PORT_PCS_DW1_LN0_AE, \ _CNL_PORT_PCS_DW1_LN0_B, \ _CNL_PORT_PCS_DW1_LN0_C, \ @@ -1888,15 +1888,15 @@ enum i915_power_well_id { #define _ICL_PORT_PCS_AUX 0x300 #define _ICL_PORT_PCS_GRP 0x600 #define _ICL_PORT_PCS_LN(ln) (0x800 + (ln) * 0x100) -#define _ICL_PORT_PCS_DW_AUX(dw, port) (_ICL_COMBOPHY(port) + \ +#define _ICL_PORT_PCS_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \ _ICL_PORT_PCS_AUX + 4 * (dw)) -#define _ICL_PORT_PCS_DW_GRP(dw, port) (_ICL_COMBOPHY(port) + \ +#define _ICL_PORT_PCS_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \ _ICL_PORT_PCS_GRP + 4 * (dw)) -#define _ICL_PORT_PCS_DW_LN(dw, ln, port) (_ICL_COMBOPHY(port) + \ +#define _ICL_PORT_PCS_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \ _ICL_PORT_PCS_LN(ln) + 4 * (dw)) -#define ICL_PORT_PCS_DW1_AUX(port) _MMIO(_ICL_PORT_PCS_DW_AUX(1, port)) -#define ICL_PORT_PCS_DW1_GRP(port) _MMIO(_ICL_PORT_PCS_DW_GRP(1, port)) -#define ICL_PORT_PCS_DW1_LN0(port) _MMIO(_ICL_PORT_PCS_DW_LN(1, 0, port)) +#define ICL_PORT_PCS_DW1_AUX(phy) _MMIO(_ICL_PORT_PCS_DW_AUX(1, phy)) +#define ICL_PORT_PCS_DW1_GRP(phy) _MMIO(_ICL_PORT_PCS_DW_GRP(1, phy)) +#define ICL_PORT_PCS_DW1_LN0(phy) _MMIO(_ICL_PORT_PCS_DW_LN(1, 0, phy)) #define COMMON_KEEPER_EN (1 << 26) #define LATENCY_OPTIM_MASK (0x3 << 2) #define LATENCY_OPTIM_VAL(x) ((x) << 2) @@ -1933,18 +1933,18 @@ enum i915_power_well_id { #define _ICL_PORT_TX_GRP 0x680 #define _ICL_PORT_TX_LN(ln) (0x880 + (ln) * 0x100) -#define _ICL_PORT_TX_DW_AUX(dw, port) (_ICL_COMBOPHY(port) + \ +#define _ICL_PORT_TX_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \ _ICL_PORT_TX_AUX + 4 * (dw)) -#define _ICL_PORT_TX_DW_GRP(dw, port) (_ICL_COMBOPHY(port) + \ +#define _ICL_PORT_TX_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \ _ICL_PORT_TX_GRP + 4 * (dw)) -#define _ICL_PORT_TX_DW_LN(dw, ln, port) (_ICL_COMBOPHY(port) + \ +#define _ICL_PORT_TX_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \ _ICL_PORT_TX_LN(ln) + 4 * (dw)) #define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(2, port)) #define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(2, port)) -#define ICL_PORT_TX_DW2_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(2, port)) -#define ICL_PORT_TX_DW2_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(2, port)) -#define ICL_PORT_TX_DW2_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(2, 0, port)) +#define ICL_PORT_TX_DW2_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(2, phy)) +#define ICL_PORT_TX_DW2_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(2, phy)) +#define ICL_PORT_TX_DW2_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(2, 0, phy)) #define SWING_SEL_UPPER(x) (((x) >> 3) << 15) #define SWING_SEL_UPPER_MASK (1 << 15) #define SWING_SEL_LOWER(x) (((x) & 0x7) << 11) @@ -1961,10 +1961,10 @@ enum i915_power_well_id { #define CNL_PORT_TX_DW4_LN(ln, port) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)) + \ ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \ _CNL_PORT_TX_DW4_LN0_AE))) -#define ICL_PORT_TX_DW4_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(4, port)) -#define ICL_PORT_TX_DW4_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(4, port)) -#define ICL_PORT_TX_DW4_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(4, 0, port)) -#define ICL_PORT_TX_DW4_LN(ln, port) _MMIO(_ICL_PORT_TX_DW_LN(4, ln, port)) +#define ICL_PORT_TX_DW4_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(4, phy)) +#define ICL_PORT_TX_DW4_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(4, phy)) +#define ICL_PORT_TX_DW4_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(4, 0, phy)) +#define ICL_PORT_TX_DW4_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(4, ln, phy)) #define LOADGEN_SELECT (1 << 31) #define POST_CURSOR_1(x) ((x) << 12) #define POST_CURSOR_1_MASK (0x3F << 12) @@ -1975,9 +1975,9 @@ enum i915_power_well_id { #define CNL_PORT_TX_DW5_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(5, port)) #define CNL_PORT_TX_DW5_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(5, port)) -#define ICL_PORT_TX_DW5_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(5, port)) -#define ICL_PORT_TX_DW5_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(5, port)) -#define ICL_PORT_TX_DW5_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(5, 0, port)) +#define ICL_PORT_TX_DW5_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(5, phy)) +#define ICL_PORT_TX_DW5_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(5, phy)) +#define ICL_PORT_TX_DW5_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(5, 0, phy)) #define TX_TRAINING_EN (1 << 31) #define TAP2_DISABLE (1 << 30) #define TAP3_DISABLE (1 << 29) @@ -1988,10 +1988,10 @@ enum i915_power_well_id { #define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(7, (port))) #define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(7, (port))) -#define ICL_PORT_TX_DW7_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(7, port)) -#define ICL_PORT_TX_DW7_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(7, port)) -#define ICL_PORT_TX_DW7_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, port)) -#define ICL_PORT_TX_DW7_LN(ln, port) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, port)) +#define ICL_PORT_TX_DW7_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(7, phy)) +#define ICL_PORT_TX_DW7_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(7, phy)) +#define ICL_PORT_TX_DW7_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, phy)) +#define ICL_PORT_TX_DW7_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, phy)) #define N_SCALAR(x) ((x) << 24) #define N_SCALAR_MASK (0x7F << 24) -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v6 3/5] drm/i915/gen11: Convert combo PHY logic to use new 'enum phy' namespace 2019-07-09 18:39 ` [PATCH v6 3/5] drm/i915/gen11: Convert combo PHY logic to use new 'enum phy' namespace Matt Roper @ 2019-09-04 13:42 ` Jani Nikula 2019-09-04 14:57 ` Matt Roper 0 siblings, 1 reply; 13+ messages in thread From: Jani Nikula @ 2019-09-04 13:42 UTC (permalink / raw) To: Matt Roper, intel-gfx On Tue, 09 Jul 2019, Matt Roper <matthew.d.roper@intel.com> wrote: > Convert the code that operates directly on gen11 combo PHY's to use the > new namespace. Combo PHY registers are those named "ICL_PORT_*" plus > ICL_DPHY_CHKN. > > Note that a lot of the PHY programming happens in the MIPI DSI code. > For clarity I've added a for_each_dsi_phy() to loop over the phys used > by DSI. Since DSI always uses A & B on gen11, port=phy in all cases so > it doesn't actually matter which form we use in the DSI code. I've used > the phy iterator in code that's explicitly working with the combo PHY, > but left the rest of the DSI code using the port iterator and namespace > to minimize patch deltas. We can switch the rest of the DSI code over > to use phy terminology later if this winds up being too confusing. One itsy-bitsy detail, where does this initialize intel_dsi->phys? Looking at the code, I'm thinking nowhere. We have an ICL DSI machine in CI, which reports all green on this patch... but most likely the display is all black instead. DSI being DSI, it is entirely possible we have no way of knowing without having a camera capture the display. BR, Jani. > > v6: Drop an include of drm/i915_drm.h; that was previously included just > for the definition of 'enum port' which this patch removes the need > for. (Jose) > > Cc: José Roberto de Souza <jose.souza@intel.com> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > Reviewed-by: José Roberto de Souza <jose.souza@intel.com> > --- > drivers/gpu/drm/i915/display/icl_dsi.c | 127 ++++++++-------- > .../gpu/drm/i915/display/intel_combo_phy.c | 143 +++++++++--------- > .../gpu/drm/i915/display/intel_combo_phy.h | 4 +- > drivers/gpu/drm/i915/display/intel_ddi.c | 45 +++--- > drivers/gpu/drm/i915/display/intel_display.h | 4 + > .../drm/i915/display/intel_display_power.c | 16 +- > drivers/gpu/drm/i915/display/intel_dsi.h | 12 +- > drivers/gpu/drm/i915/i915_reg.h | 74 ++++----- > 8 files changed, 213 insertions(+), 212 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c > index 8f1324c2f539..4d952accfaaa 100644 > --- a/drivers/gpu/drm/i915/display/icl_dsi.c > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c > @@ -202,63 +202,62 @@ static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder) > { > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); > - enum port port; > + enum phy phy; > u32 tmp; > int lane; > > - for_each_dsi_port(port, intel_dsi->ports) { > - > + for_each_dsi_phy(phy, intel_dsi->phys) { > /* > * Program voltage swing and pre-emphasis level values as per > * table in BSPEC under DDI buffer programing > */ > - tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port)); > + tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); > tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK); > tmp |= SCALING_MODE_SEL(0x2); > tmp |= TAP2_DISABLE | TAP3_DISABLE; > tmp |= RTERM_SELECT(0x6); > - I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp); > + I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), tmp); > > - tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port)); > + tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy)); > tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK); > tmp |= SCALING_MODE_SEL(0x2); > tmp |= TAP2_DISABLE | TAP3_DISABLE; > tmp |= RTERM_SELECT(0x6); > - I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp); > + I915_WRITE(ICL_PORT_TX_DW5_AUX(phy), tmp); > > - tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port)); > + tmp = I915_READ(ICL_PORT_TX_DW2_LN0(phy)); > tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | > RCOMP_SCALAR_MASK); > tmp |= SWING_SEL_UPPER(0x2); > tmp |= SWING_SEL_LOWER(0x2); > tmp |= RCOMP_SCALAR(0x98); > - I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp); > + I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), tmp); > > - tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port)); > + tmp = I915_READ(ICL_PORT_TX_DW2_AUX(phy)); > tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | > RCOMP_SCALAR_MASK); > tmp |= SWING_SEL_UPPER(0x2); > tmp |= SWING_SEL_LOWER(0x2); > tmp |= RCOMP_SCALAR(0x98); > - I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp); > + I915_WRITE(ICL_PORT_TX_DW2_AUX(phy), tmp); > > - tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port)); > + tmp = I915_READ(ICL_PORT_TX_DW4_AUX(phy)); > tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | > CURSOR_COEFF_MASK); > tmp |= POST_CURSOR_1(0x0); > tmp |= POST_CURSOR_2(0x0); > tmp |= CURSOR_COEFF(0x3f); > - I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp); > + I915_WRITE(ICL_PORT_TX_DW4_AUX(phy), tmp); > > for (lane = 0; lane <= 3; lane++) { > /* Bspec: must not use GRP register for write */ > - tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, port)); > + tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, phy)); > tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | > CURSOR_COEFF_MASK); > tmp |= POST_CURSOR_1(0x0); > tmp |= POST_CURSOR_2(0x0); > tmp |= CURSOR_COEFF(0x3f); > - I915_WRITE(ICL_PORT_TX_DW4_LN(lane, port), tmp); > + I915_WRITE(ICL_PORT_TX_DW4_LN(lane, phy), tmp); > } > } > } > @@ -364,10 +363,10 @@ static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder) > { > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); > - enum port port; > + enum phy phy; > > - for_each_dsi_port(port, intel_dsi->ports) > - intel_combo_phy_power_up_lanes(dev_priv, port, true, > + for_each_dsi_phy(phy, intel_dsi->phys) > + intel_combo_phy_power_up_lanes(dev_priv, phy, true, > intel_dsi->lane_count, false); > } > > @@ -375,46 +374,46 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder) > { > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); > - enum port port; > + enum phy phy; > u32 tmp; > int lane; > > /* Step 4b(i) set loadgen select for transmit and aux lanes */ > - for_each_dsi_port(port, intel_dsi->ports) { > - tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port)); > + for_each_dsi_phy(phy, intel_dsi->phys) { > + tmp = I915_READ(ICL_PORT_TX_DW4_AUX(phy)); > tmp &= ~LOADGEN_SELECT; > - I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp); > + I915_WRITE(ICL_PORT_TX_DW4_AUX(phy), tmp); > for (lane = 0; lane <= 3; lane++) { > - tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, port)); > + tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, phy)); > tmp &= ~LOADGEN_SELECT; > if (lane != 2) > tmp |= LOADGEN_SELECT; > - I915_WRITE(ICL_PORT_TX_DW4_LN(lane, port), tmp); > + I915_WRITE(ICL_PORT_TX_DW4_LN(lane, phy), tmp); > } > } > > /* Step 4b(ii) set latency optimization for transmit and aux lanes */ > - for_each_dsi_port(port, intel_dsi->ports) { > - tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port)); > + for_each_dsi_phy(phy, intel_dsi->phys) { > + tmp = I915_READ(ICL_PORT_TX_DW2_AUX(phy)); > tmp &= ~FRC_LATENCY_OPTIM_MASK; > tmp |= FRC_LATENCY_OPTIM_VAL(0x5); > - I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp); > - tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port)); > + I915_WRITE(ICL_PORT_TX_DW2_AUX(phy), tmp); > + tmp = I915_READ(ICL_PORT_TX_DW2_LN0(phy)); > tmp &= ~FRC_LATENCY_OPTIM_MASK; > tmp |= FRC_LATENCY_OPTIM_VAL(0x5); > - I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp); > + I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), tmp); > > /* For EHL set latency optimization for PCS_DW1 lanes */ > if (IS_ELKHARTLAKE(dev_priv)) { > - tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(port)); > + tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(phy)); > tmp &= ~LATENCY_OPTIM_MASK; > tmp |= LATENCY_OPTIM_VAL(0); > - I915_WRITE(ICL_PORT_PCS_DW1_AUX(port), tmp); > + I915_WRITE(ICL_PORT_PCS_DW1_AUX(phy), tmp); > > - tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(port)); > + tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(phy)); > tmp &= ~LATENCY_OPTIM_MASK; > tmp |= LATENCY_OPTIM_VAL(0x1); > - I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), tmp); > + I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), tmp); > } > } > > @@ -425,16 +424,16 @@ static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder) > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); > u32 tmp; > - enum port port; > + enum phy phy; > > /* clear common keeper enable bit */ > - for_each_dsi_port(port, intel_dsi->ports) { > - tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(port)); > + for_each_dsi_phy(phy, intel_dsi->phys) { > + tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(phy)); > tmp &= ~COMMON_KEEPER_EN; > - I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), tmp); > - tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(port)); > + I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), tmp); > + tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(phy)); > tmp &= ~COMMON_KEEPER_EN; > - I915_WRITE(ICL_PORT_PCS_DW1_AUX(port), tmp); > + I915_WRITE(ICL_PORT_PCS_DW1_AUX(phy), tmp); > } > > /* > @@ -442,33 +441,33 @@ static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder) > * Note: loadgen select program is done > * as part of lane phy sequence configuration > */ > - for_each_dsi_port(port, intel_dsi->ports) { > - tmp = I915_READ(ICL_PORT_CL_DW5(port)); > + for_each_dsi_phy(phy, intel_dsi->phys) { > + tmp = I915_READ(ICL_PORT_CL_DW5(phy)); > tmp |= SUS_CLOCK_CONFIG; > - I915_WRITE(ICL_PORT_CL_DW5(port), tmp); > + I915_WRITE(ICL_PORT_CL_DW5(phy), tmp); > } > > /* Clear training enable to change swing values */ > - for_each_dsi_port(port, intel_dsi->ports) { > - tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port)); > + for_each_dsi_phy(phy, intel_dsi->phys) { > + tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); > tmp &= ~TX_TRAINING_EN; > - I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp); > - tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port)); > + I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), tmp); > + tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy)); > tmp &= ~TX_TRAINING_EN; > - I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp); > + I915_WRITE(ICL_PORT_TX_DW5_AUX(phy), tmp); > } > > /* Program swing and de-emphasis */ > dsi_program_swing_and_deemphasis(encoder); > > /* Set training enable to trigger update */ > - for_each_dsi_port(port, intel_dsi->ports) { > - tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port)); > + for_each_dsi_phy(phy, intel_dsi->phys) { > + tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); > tmp |= TX_TRAINING_EN; > - I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp); > - tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port)); > + I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), tmp); > + tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy)); > tmp |= TX_TRAINING_EN; > - I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp); > + I915_WRITE(ICL_PORT_TX_DW5_AUX(phy), tmp); > } > } > > @@ -497,6 +496,7 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder) > struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); > u32 tmp; > enum port port; > + enum phy phy; > > /* Program T-INIT master registers */ > for_each_dsi_port(port, intel_dsi->ports) { > @@ -546,10 +546,10 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder) > } > > if (IS_ELKHARTLAKE(dev_priv)) { > - for_each_dsi_port(port, intel_dsi->ports) { > - tmp = I915_READ(ICL_DPHY_CHKN(port)); > + for_each_dsi_phy(phy, intel_dsi->phys) { > + tmp = I915_READ(ICL_DPHY_CHKN(phy)); > tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP; > - I915_WRITE(ICL_DPHY_CHKN(port), tmp); > + I915_WRITE(ICL_DPHY_CHKN(phy), tmp); > } > } > } > @@ -559,15 +559,12 @@ static void gen11_dsi_gate_clocks(struct intel_encoder *encoder) > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); > u32 tmp; > - enum port port; > enum phy phy; > > mutex_lock(&dev_priv->dpll_lock); > tmp = I915_READ(ICL_DPCLKA_CFGCR0); > - for_each_dsi_port(port, intel_dsi->ports) { > - phy = intel_port_to_phy(dev_priv, port); > + for_each_dsi_phy(phy, intel_dsi->phys) > tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); > - } > > I915_WRITE(ICL_DPCLKA_CFGCR0, tmp); > mutex_unlock(&dev_priv->dpll_lock); > @@ -578,15 +575,12 @@ static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder) > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); > u32 tmp; > - enum port port; > enum phy phy; > > mutex_lock(&dev_priv->dpll_lock); > tmp = I915_READ(ICL_DPCLKA_CFGCR0); > - for_each_dsi_port(port, intel_dsi->ports) { > - phy = intel_port_to_phy(dev_priv, port); > + for_each_dsi_phy(phy, intel_dsi->phys) > tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); > - } > > I915_WRITE(ICL_DPCLKA_CFGCR0, tmp); > mutex_unlock(&dev_priv->dpll_lock); > @@ -598,22 +592,19 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder, > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); > struct intel_shared_dpll *pll = crtc_state->shared_dpll; > - enum port port; > enum phy phy; > u32 val; > > mutex_lock(&dev_priv->dpll_lock); > > val = I915_READ(ICL_DPCLKA_CFGCR0); > - for_each_dsi_port(port, intel_dsi->ports) { > - phy = intel_port_to_phy(dev_priv, port); > + for_each_dsi_phy(phy, intel_dsi->phys) { > val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); > val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); > } > I915_WRITE(ICL_DPCLKA_CFGCR0, val); > > - for_each_dsi_port(port, intel_dsi->ports) { > - phy = intel_port_to_phy(dev_priv, port); > + for_each_dsi_phy(phy, intel_dsi->phys) { > val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); > } > I915_WRITE(ICL_DPCLKA_CFGCR0, val); > diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c > index d3d5244765e6..ac8218a040ab 100644 > --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c > @@ -6,13 +6,13 @@ > #include "intel_combo_phy.h" > #include "intel_drv.h" > > -#define for_each_combo_port(__dev_priv, __port) \ > - for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \ > - for_each_if(intel_port_is_combophy(__dev_priv, __port)) > +#define for_each_combo_phy(__dev_priv, __phy) \ > + for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \ > + for_each_if(intel_phy_is_combo(__dev_priv, __phy)) > > -#define for_each_combo_port_reverse(__dev_priv, __port) \ > - for ((__port) = I915_MAX_PORTS; (__port)-- > PORT_A;) \ > - for_each_if(intel_port_is_combophy(__dev_priv, __port)) > +#define for_each_combo_phy_reverse(__dev_priv, __phy) \ > + for ((__phy) = I915_MAX_PHYS; (__phy)-- > PHY_A;) \ > + for_each_if(intel_phy_is_combo(__dev_priv, __phy)) > > enum { > PROCMON_0_85V_DOT_0, > @@ -38,18 +38,17 @@ static const struct cnl_procmon { > }; > > /* > - * CNL has just one set of registers, while ICL has two sets: one for port A and > - * the other for port B. The CNL registers are equivalent to the ICL port A > - * registers, that's why we call the ICL macros even though the function has CNL > - * on its name. > + * CNL has just one set of registers, while gen11 has a set for each combo PHY. > + * The CNL registers are equivalent to the gen11 PHY A registers, that's why we > + * call the ICL macros even though the function has CNL on its name. > */ > static const struct cnl_procmon * > -cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum port port) > +cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy) > { > const struct cnl_procmon *procmon; > u32 val; > > - val = I915_READ(ICL_PORT_COMP_DW3(port)); > + val = I915_READ(ICL_PORT_COMP_DW3(phy)); > switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) { > default: > MISSING_CASE(val); > @@ -75,32 +74,32 @@ cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum port port) > } > > static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv, > - enum port port) > + enum phy phy) > { > const struct cnl_procmon *procmon; > u32 val; > > - procmon = cnl_get_procmon_ref_values(dev_priv, port); > + procmon = cnl_get_procmon_ref_values(dev_priv, phy); > > - val = I915_READ(ICL_PORT_COMP_DW1(port)); > + val = I915_READ(ICL_PORT_COMP_DW1(phy)); > val &= ~((0xff << 16) | 0xff); > val |= procmon->dw1; > - I915_WRITE(ICL_PORT_COMP_DW1(port), val); > + I915_WRITE(ICL_PORT_COMP_DW1(phy), val); > > - I915_WRITE(ICL_PORT_COMP_DW9(port), procmon->dw9); > - I915_WRITE(ICL_PORT_COMP_DW10(port), procmon->dw10); > + I915_WRITE(ICL_PORT_COMP_DW9(phy), procmon->dw9); > + I915_WRITE(ICL_PORT_COMP_DW10(phy), procmon->dw10); > } > > static bool check_phy_reg(struct drm_i915_private *dev_priv, > - enum port port, i915_reg_t reg, u32 mask, > + enum phy phy, i915_reg_t reg, u32 mask, > u32 expected_val) > { > u32 val = I915_READ(reg); > > if ((val & mask) != expected_val) { > - DRM_DEBUG_DRIVER("Port %c combo PHY reg %08x state mismatch: " > + DRM_DEBUG_DRIVER("Combo PHY %c reg %08x state mismatch: " > "current %08x mask %08x expected %08x\n", > - port_name(port), > + phy_name(phy), > reg.reg, val, mask, expected_val); > return false; > } > @@ -109,18 +108,18 @@ static bool check_phy_reg(struct drm_i915_private *dev_priv, > } > > static bool cnl_verify_procmon_ref_values(struct drm_i915_private *dev_priv, > - enum port port) > + enum phy phy) > { > const struct cnl_procmon *procmon; > bool ret; > > - procmon = cnl_get_procmon_ref_values(dev_priv, port); > + procmon = cnl_get_procmon_ref_values(dev_priv, phy); > > - ret = check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW1(port), > + ret = check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW1(phy), > (0xff << 16) | 0xff, procmon->dw1); > - ret &= check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW9(port), > + ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW9(phy), > -1U, procmon->dw9); > - ret &= check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW10(port), > + ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW10(phy), > -1U, procmon->dw10); > > return ret; > @@ -134,15 +133,15 @@ static bool cnl_combo_phy_enabled(struct drm_i915_private *dev_priv) > > static bool cnl_combo_phy_verify_state(struct drm_i915_private *dev_priv) > { > - enum port port = PORT_A; > + enum phy phy = PHY_A; > bool ret; > > if (!cnl_combo_phy_enabled(dev_priv)) > return false; > > - ret = cnl_verify_procmon_ref_values(dev_priv, port); > + ret = cnl_verify_procmon_ref_values(dev_priv, phy); > > - ret &= check_phy_reg(dev_priv, port, CNL_PORT_CL1CM_DW5, > + ret &= check_phy_reg(dev_priv, phy, CNL_PORT_CL1CM_DW5, > CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE); > > return ret; > @@ -157,7 +156,7 @@ static void cnl_combo_phys_init(struct drm_i915_private *dev_priv) > I915_WRITE(CHICKEN_MISC_2, val); > > /* Dummy PORT_A to get the correct CNL register from the ICL macro */ > - cnl_set_procmon_ref_values(dev_priv, PORT_A); > + cnl_set_procmon_ref_values(dev_priv, PHY_A); > > val = I915_READ(CNL_PORT_COMP_DW0); > val |= COMP_INIT; > @@ -181,39 +180,39 @@ static void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv) > } > > static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv, > - enum port port) > + enum phy phy) > { > /* The PHY C added by EHL has no PHY_MISC register */ > - if (IS_ELKHARTLAKE(dev_priv) && port == PORT_C) > - return I915_READ(ICL_PORT_COMP_DW0(port)) & COMP_INIT; > + if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C) > + return I915_READ(ICL_PORT_COMP_DW0(phy)) & COMP_INIT; > else > - return !(I915_READ(ICL_PHY_MISC(port)) & > + return !(I915_READ(ICL_PHY_MISC(phy)) & > ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) && > - (I915_READ(ICL_PORT_COMP_DW0(port)) & COMP_INIT); > + (I915_READ(ICL_PORT_COMP_DW0(phy)) & COMP_INIT); > } > > static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv, > - enum port port) > + enum phy phy) > { > bool ret; > > - if (!icl_combo_phy_enabled(dev_priv, port)) > + if (!icl_combo_phy_enabled(dev_priv, phy)) > return false; > > - ret = cnl_verify_procmon_ref_values(dev_priv, port); > + ret = cnl_verify_procmon_ref_values(dev_priv, phy); > > - if (port == PORT_A) > - ret &= check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW8(port), > + if (phy == PHY_A) > + ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy), > IREFGEN, IREFGEN); > > - ret &= check_phy_reg(dev_priv, port, ICL_PORT_CL_DW5(port), > + ret &= check_phy_reg(dev_priv, phy, ICL_PORT_CL_DW5(phy), > CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE); > > return ret; > } > > void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv, > - enum port port, bool is_dsi, > + enum phy phy, bool is_dsi, > int lane_count, bool lane_reversal) > { > u8 lane_mask; > @@ -258,10 +257,10 @@ void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv, > } > } > > - val = I915_READ(ICL_PORT_CL_DW10(port)); > + val = I915_READ(ICL_PORT_CL_DW10(phy)); > val &= ~PWR_DOWN_LN_MASK; > val |= lane_mask << PWR_DOWN_LN_SHIFT; > - I915_WRITE(ICL_PORT_CL_DW10(port), val); > + I915_WRITE(ICL_PORT_CL_DW10(phy), val); > } > > static u32 ehl_combo_phy_a_mux(struct drm_i915_private *i915, u32 val) > @@ -292,14 +291,14 @@ static u32 ehl_combo_phy_a_mux(struct drm_i915_private *i915, u32 val) > > static void icl_combo_phys_init(struct drm_i915_private *dev_priv) > { > - enum port port; > + enum phy phy; > > - for_each_combo_port(dev_priv, port) { > + for_each_combo_phy(dev_priv, phy) { > u32 val; > > - if (icl_combo_phy_verify_state(dev_priv, port)) { > - DRM_DEBUG_DRIVER("Port %c combo PHY already enabled, won't reprogram it.\n", > - port_name(port)); > + if (icl_combo_phy_verify_state(dev_priv, phy)) { > + DRM_DEBUG_DRIVER("Combo PHY %c already enabled, won't reprogram it.\n", > + phy_name(phy)); > continue; > } > > @@ -308,7 +307,7 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv) > * register for it and no need to program the > * DE_IO_COMP_PWR_DOWN setting on PHY C. > */ > - if (IS_ELKHARTLAKE(dev_priv) && port == PORT_C) > + if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C) > goto skip_phy_misc; > > /* > @@ -319,59 +318,59 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv) > * based on whether our VBT indicates the presence of any > * "internal" child devices. > */ > - val = I915_READ(ICL_PHY_MISC(port)); > - if (IS_ELKHARTLAKE(dev_priv) && port == PORT_A) > + val = I915_READ(ICL_PHY_MISC(phy)); > + if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_A) > val = ehl_combo_phy_a_mux(dev_priv, val); > val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN; > - I915_WRITE(ICL_PHY_MISC(port), val); > + I915_WRITE(ICL_PHY_MISC(phy), val); > > skip_phy_misc: > - cnl_set_procmon_ref_values(dev_priv, port); > + cnl_set_procmon_ref_values(dev_priv, phy); > > - if (port == PORT_A) { > - val = I915_READ(ICL_PORT_COMP_DW8(port)); > + if (phy == PHY_A) { > + val = I915_READ(ICL_PORT_COMP_DW8(phy)); > val |= IREFGEN; > - I915_WRITE(ICL_PORT_COMP_DW8(port), val); > + I915_WRITE(ICL_PORT_COMP_DW8(phy), val); > } > > - val = I915_READ(ICL_PORT_COMP_DW0(port)); > + val = I915_READ(ICL_PORT_COMP_DW0(phy)); > val |= COMP_INIT; > - I915_WRITE(ICL_PORT_COMP_DW0(port), val); > + I915_WRITE(ICL_PORT_COMP_DW0(phy), val); > > - val = I915_READ(ICL_PORT_CL_DW5(port)); > + val = I915_READ(ICL_PORT_CL_DW5(phy)); > val |= CL_POWER_DOWN_ENABLE; > - I915_WRITE(ICL_PORT_CL_DW5(port), val); > + I915_WRITE(ICL_PORT_CL_DW5(phy), val); > } > } > > static void icl_combo_phys_uninit(struct drm_i915_private *dev_priv) > { > - enum port port; > + enum phy phy; > > - for_each_combo_port_reverse(dev_priv, port) { > + for_each_combo_phy_reverse(dev_priv, phy) { > u32 val; > > - if (port == PORT_A && > - !icl_combo_phy_verify_state(dev_priv, port)) > - DRM_WARN("Port %c combo PHY HW state changed unexpectedly\n", > - port_name(port)); > + if (phy == PHY_A && > + !icl_combo_phy_verify_state(dev_priv, phy)) > + DRM_WARN("Combo PHY %c HW state changed unexpectedly\n", > + phy_name(phy)); > > /* > * Although EHL adds a combo PHY C, there's no PHY_MISC > * register for it and no need to program the > * DE_IO_COMP_PWR_DOWN setting on PHY C. > */ > - if (IS_ELKHARTLAKE(dev_priv) && port == PORT_C) > + if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C) > goto skip_phy_misc; > > - val = I915_READ(ICL_PHY_MISC(port)); > + val = I915_READ(ICL_PHY_MISC(phy)); > val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN; > - I915_WRITE(ICL_PHY_MISC(port), val); > + I915_WRITE(ICL_PHY_MISC(phy), val); > > skip_phy_misc: > - val = I915_READ(ICL_PORT_COMP_DW0(port)); > + val = I915_READ(ICL_PORT_COMP_DW0(phy)); > val &= ~COMP_INIT; > - I915_WRITE(ICL_PORT_COMP_DW0(port), val); > + I915_WRITE(ICL_PORT_COMP_DW0(phy), val); > } > } > > diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.h b/drivers/gpu/drm/i915/display/intel_combo_phy.h > index e6e195a83b19..660886f86c59 100644 > --- a/drivers/gpu/drm/i915/display/intel_combo_phy.h > +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.h > @@ -7,14 +7,14 @@ > #define __INTEL_COMBO_PHY_H__ > > #include <linux/types.h> > -#include <drm/i915_drm.h> > > struct drm_i915_private; > +enum phy; > > void intel_combo_phy_init(struct drm_i915_private *dev_priv); > void intel_combo_phy_uninit(struct drm_i915_private *dev_priv); > void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv, > - enum port port, bool is_dsi, > + enum phy phy, bool is_dsi, > int lane_count, bool lane_reversal); > > #endif /* __INTEL_COMBO_PHY_H__ */ > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index b5bc00c4e3fe..d9ea58038642 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -2414,7 +2414,7 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, > } > > static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, > - u32 level, enum port port, int type, > + u32 level, enum phy phy, int type, > int rate) > { > const struct cnl_ddi_buf_trans *ddi_translations = NULL; > @@ -2432,41 +2432,41 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, > } > > /* Set PORT_TX_DW5 */ > - val = I915_READ(ICL_PORT_TX_DW5_LN0(port)); > + val = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); > val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | > TAP2_DISABLE | TAP3_DISABLE); > val |= SCALING_MODE_SEL(0x2); > val |= RTERM_SELECT(0x6); > val |= TAP3_DISABLE; > - I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val); > + I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val); > > /* Program PORT_TX_DW2 */ > - val = I915_READ(ICL_PORT_TX_DW2_LN0(port)); > + val = I915_READ(ICL_PORT_TX_DW2_LN0(phy)); > val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | > RCOMP_SCALAR_MASK); > val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); > val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); > /* Program Rcomp scalar for every table entry */ > val |= RCOMP_SCALAR(0x98); > - I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val); > + I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), val); > > /* Program PORT_TX_DW4 */ > /* We cannot write to GRP. It would overwrite individual loadgen. */ > for (ln = 0; ln <= 3; ln++) { > - val = I915_READ(ICL_PORT_TX_DW4_LN(ln, port)); > + val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy)); > val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | > CURSOR_COEFF_MASK); > val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); > val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); > val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); > - I915_WRITE(ICL_PORT_TX_DW4_LN(ln, port), val); > + I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val); > } > > /* Program PORT_TX_DW7 */ > - val = I915_READ(ICL_PORT_TX_DW7_LN0(port)); > + val = I915_READ(ICL_PORT_TX_DW7_LN0(phy)); > val &= ~N_SCALAR_MASK; > val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); > - I915_WRITE(ICL_PORT_TX_DW7_GRP(port), val); > + I915_WRITE(ICL_PORT_TX_DW7_GRP(phy), val); > } > > static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > @@ -2474,7 +2474,7 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > enum intel_output_type type) > { > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > - enum port port = encoder->port; > + enum phy phy = intel_port_to_phy(dev_priv, encoder->port); > int width = 0; > int rate = 0; > u32 val; > @@ -2495,12 +2495,12 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > * set PORT_PCS_DW1 cmnkeeper_enable to 1b, > * else clear to 0b. > */ > - val = I915_READ(ICL_PORT_PCS_DW1_LN0(port)); > + val = I915_READ(ICL_PORT_PCS_DW1_LN0(phy)); > if (type == INTEL_OUTPUT_HDMI) > val &= ~COMMON_KEEPER_EN; > else > val |= COMMON_KEEPER_EN; > - I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), val); > + I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), val); > > /* 2. Program loadgen select */ > /* > @@ -2510,33 +2510,33 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) > */ > for (ln = 0; ln <= 3; ln++) { > - val = I915_READ(ICL_PORT_TX_DW4_LN(ln, port)); > + val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy)); > val &= ~LOADGEN_SELECT; > > if ((rate <= 600000 && width == 4 && ln >= 1) || > (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { > val |= LOADGEN_SELECT; > } > - I915_WRITE(ICL_PORT_TX_DW4_LN(ln, port), val); > + I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val); > } > > /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ > - val = I915_READ(ICL_PORT_CL_DW5(port)); > + val = I915_READ(ICL_PORT_CL_DW5(phy)); > val |= SUS_CLOCK_CONFIG; > - I915_WRITE(ICL_PORT_CL_DW5(port), val); > + I915_WRITE(ICL_PORT_CL_DW5(phy), val); > > /* 4. Clear training enable to change swing values */ > - val = I915_READ(ICL_PORT_TX_DW5_LN0(port)); > + val = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); > val &= ~TX_TRAINING_EN; > - I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val); > + I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val); > > /* 5. Program swing and de-emphasis */ > - icl_ddi_combo_vswing_program(dev_priv, level, port, type, rate); > + icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate); > > /* 6. Set training enable to trigger update */ > - val = I915_READ(ICL_PORT_TX_DW5_LN0(port)); > + val = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); > val |= TX_TRAINING_EN; > - I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val); > + I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val); > } > > static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > @@ -3121,6 +3121,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, > struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > enum port port = encoder->port; > + enum phy phy = intel_port_to_phy(dev_priv, port); > struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); > bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); > int level = intel_ddi_dp_level(intel_dp); > @@ -3156,7 +3157,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, > bool lane_reversal = > dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; > > - intel_combo_phy_power_up_lanes(dev_priv, port, false, > + intel_combo_phy_power_up_lanes(dev_priv, phy, false, > crtc_state->lane_count, > lane_reversal); > } > diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h > index d53285fb883f..8a4a57ef82a2 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.h > +++ b/drivers/gpu/drm/i915/display/intel_display.h > @@ -268,6 +268,10 @@ enum phy { > for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \ > for_each_if((__ports_mask) & BIT(__port)) > > +#define for_each_phy_masked(__phy, __phys_mask) \ > + for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \ > + for_each_if((__phys_mask) & BIT(__phy)) > + > #define for_each_crtc(dev, crtc) \ > list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c > index 7437fc71d289..a24d1859b37b 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_power.c > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c > @@ -397,7 +397,7 @@ static void hsw_power_well_disable(struct drm_i915_private *dev_priv, > hsw_wait_for_power_well_disable(dev_priv, power_well); > } > > -#define ICL_AUX_PW_TO_PORT(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A) > +#define ICL_AUX_PW_TO_PHY(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A) > > static void > icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, > @@ -405,21 +405,21 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, > { > const struct i915_power_well_regs *regs = power_well->desc->hsw.regs; > int pw_idx = power_well->desc->hsw.idx; > - enum port port = ICL_AUX_PW_TO_PORT(pw_idx); > + enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx); > u32 val; > > val = I915_READ(regs->driver); > I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx)); > > - val = I915_READ(ICL_PORT_CL_DW12(port)); > - I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX); > + val = I915_READ(ICL_PORT_CL_DW12(phy)); > + I915_WRITE(ICL_PORT_CL_DW12(phy), val | ICL_LANE_ENABLE_AUX); > > hsw_wait_for_power_well_enable(dev_priv, power_well); > > /* Display WA #1178: icl */ > if (IS_ICELAKE(dev_priv) && > pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B && > - !intel_bios_is_port_edp(dev_priv, port)) { > + !intel_bios_is_port_edp(dev_priv, (enum port)phy)) { > val = I915_READ(ICL_AUX_ANAOVRD1(pw_idx)); > val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS; > I915_WRITE(ICL_AUX_ANAOVRD1(pw_idx), val); > @@ -432,11 +432,11 @@ icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv, > { > const struct i915_power_well_regs *regs = power_well->desc->hsw.regs; > int pw_idx = power_well->desc->hsw.idx; > - enum port port = ICL_AUX_PW_TO_PORT(pw_idx); > + enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx); > u32 val; > > - val = I915_READ(ICL_PORT_CL_DW12(port)); > - I915_WRITE(ICL_PORT_CL_DW12(port), val & ~ICL_LANE_ENABLE_AUX); > + val = I915_READ(ICL_PORT_CL_DW12(phy)); > + I915_WRITE(ICL_PORT_CL_DW12(phy), val & ~ICL_LANE_ENABLE_AUX); > > val = I915_READ(regs->driver); > I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx)); > diff --git a/drivers/gpu/drm/i915/display/intel_dsi.h b/drivers/gpu/drm/i915/display/intel_dsi.h > index 6d20434636cd..1cd24bd46518 100644 > --- a/drivers/gpu/drm/i915/display/intel_dsi.h > +++ b/drivers/gpu/drm/i915/display/intel_dsi.h > @@ -49,8 +49,11 @@ struct intel_dsi { > > struct intel_connector *attached_connector; > > - /* bit mask of ports being driven */ > - u16 ports; > + /* bit mask of ports (vlv dsi) or phys (icl dsi) being driven */ > + union { > + u16 ports; /* VLV DSI */ > + u16 phys; /* ICL DSI */ > + }; > > /* if true, use HS mode, otherwise LP */ > bool hs; > @@ -132,7 +135,10 @@ static inline struct intel_dsi_host *to_intel_dsi_host(struct mipi_dsi_host *h) > return container_of(h, struct intel_dsi_host, base); > } > > -#define for_each_dsi_port(__port, __ports_mask) for_each_port_masked(__port, __ports_mask) > +#define for_each_dsi_port(__port, __ports_mask) \ > + for_each_port_masked(__port, __ports_mask) > +#define for_each_dsi_phy(__phy, __phys_mask) \ > + for_each_phy_masked(__phy, __phys_mask) > > static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder) > { > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index d3fc575a94db..95b9ca1fda2e 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1794,20 +1794,20 @@ enum i915_power_well_id { > #define _ICL_COMBOPHY_A 0x162000 > #define _ICL_COMBOPHY_B 0x6C000 > #define _EHL_COMBOPHY_C 0x160000 > -#define _ICL_COMBOPHY(port) _PICK(port, _ICL_COMBOPHY_A, \ > +#define _ICL_COMBOPHY(phy) _PICK(phy, _ICL_COMBOPHY_A, \ > _ICL_COMBOPHY_B, \ > _EHL_COMBOPHY_C) > > /* CNL/ICL Port CL_DW registers */ > -#define _ICL_PORT_CL_DW(dw, port) (_ICL_COMBOPHY(port) + \ > +#define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \ > 4 * (dw)) > > #define CNL_PORT_CL1CM_DW5 _MMIO(0x162014) > -#define ICL_PORT_CL_DW5(port) _MMIO(_ICL_PORT_CL_DW(5, port)) > +#define ICL_PORT_CL_DW5(phy) _MMIO(_ICL_PORT_CL_DW(5, phy)) > #define CL_POWER_DOWN_ENABLE (1 << 4) > #define SUS_CLOCK_CONFIG (3 << 0) > > -#define ICL_PORT_CL_DW10(port) _MMIO(_ICL_PORT_CL_DW(10, port)) > +#define ICL_PORT_CL_DW10(phy) _MMIO(_ICL_PORT_CL_DW(10, phy)) > #define PG_SEQ_DELAY_OVERRIDE_MASK (3 << 25) > #define PG_SEQ_DELAY_OVERRIDE_SHIFT 25 > #define PG_SEQ_DELAY_OVERRIDE_ENABLE (1 << 24) > @@ -1822,23 +1822,23 @@ enum i915_power_well_id { > #define PWR_DOWN_LN_MASK (0xf << 4) > #define PWR_DOWN_LN_SHIFT 4 > > -#define ICL_PORT_CL_DW12(port) _MMIO(_ICL_PORT_CL_DW(12, port)) > +#define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy)) > #define ICL_LANE_ENABLE_AUX (1 << 0) > > /* CNL/ICL Port COMP_DW registers */ > #define _ICL_PORT_COMP 0x100 > -#define _ICL_PORT_COMP_DW(dw, port) (_ICL_COMBOPHY(port) + \ > +#define _ICL_PORT_COMP_DW(dw, phy) (_ICL_COMBOPHY(phy) + \ > _ICL_PORT_COMP + 4 * (dw)) > > #define CNL_PORT_COMP_DW0 _MMIO(0x162100) > -#define ICL_PORT_COMP_DW0(port) _MMIO(_ICL_PORT_COMP_DW(0, port)) > +#define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy)) > #define COMP_INIT (1 << 31) > > #define CNL_PORT_COMP_DW1 _MMIO(0x162104) > -#define ICL_PORT_COMP_DW1(port) _MMIO(_ICL_PORT_COMP_DW(1, port)) > +#define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy)) > > #define CNL_PORT_COMP_DW3 _MMIO(0x16210c) > -#define ICL_PORT_COMP_DW3(port) _MMIO(_ICL_PORT_COMP_DW(3, port)) > +#define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy)) > #define PROCESS_INFO_DOT_0 (0 << 26) > #define PROCESS_INFO_DOT_1 (1 << 26) > #define PROCESS_INFO_DOT_4 (2 << 26) > @@ -1850,14 +1850,14 @@ enum i915_power_well_id { > #define VOLTAGE_INFO_MASK (3 << 24) > #define VOLTAGE_INFO_SHIFT 24 > > -#define ICL_PORT_COMP_DW8(port) _MMIO(_ICL_PORT_COMP_DW(8, port)) > +#define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy)) > #define IREFGEN (1 << 24) > > #define CNL_PORT_COMP_DW9 _MMIO(0x162124) > -#define ICL_PORT_COMP_DW9(port) _MMIO(_ICL_PORT_COMP_DW(9, port)) > +#define ICL_PORT_COMP_DW9(phy) _MMIO(_ICL_PORT_COMP_DW(9, phy)) > > #define CNL_PORT_COMP_DW10 _MMIO(0x162128) > -#define ICL_PORT_COMP_DW10(port) _MMIO(_ICL_PORT_COMP_DW(10, port)) > +#define ICL_PORT_COMP_DW10(phy) _MMIO(_ICL_PORT_COMP_DW(10, phy)) > > /* CNL/ICL Port PCS registers */ > #define _CNL_PORT_PCS_DW1_GRP_AE 0x162304 > @@ -1870,14 +1870,14 @@ enum i915_power_well_id { > #define _CNL_PORT_PCS_DW1_LN0_C 0x162C04 > #define _CNL_PORT_PCS_DW1_LN0_D 0x162E04 > #define _CNL_PORT_PCS_DW1_LN0_F 0x162804 > -#define CNL_PORT_PCS_DW1_GRP(port) _MMIO(_PICK(port, \ > +#define CNL_PORT_PCS_DW1_GRP(phy) _MMIO(_PICK(phy, \ > _CNL_PORT_PCS_DW1_GRP_AE, \ > _CNL_PORT_PCS_DW1_GRP_B, \ > _CNL_PORT_PCS_DW1_GRP_C, \ > _CNL_PORT_PCS_DW1_GRP_D, \ > _CNL_PORT_PCS_DW1_GRP_AE, \ > _CNL_PORT_PCS_DW1_GRP_F)) > -#define CNL_PORT_PCS_DW1_LN0(port) _MMIO(_PICK(port, \ > +#define CNL_PORT_PCS_DW1_LN0(phy) _MMIO(_PICK(phy, \ > _CNL_PORT_PCS_DW1_LN0_AE, \ > _CNL_PORT_PCS_DW1_LN0_B, \ > _CNL_PORT_PCS_DW1_LN0_C, \ > @@ -1888,15 +1888,15 @@ enum i915_power_well_id { > #define _ICL_PORT_PCS_AUX 0x300 > #define _ICL_PORT_PCS_GRP 0x600 > #define _ICL_PORT_PCS_LN(ln) (0x800 + (ln) * 0x100) > -#define _ICL_PORT_PCS_DW_AUX(dw, port) (_ICL_COMBOPHY(port) + \ > +#define _ICL_PORT_PCS_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \ > _ICL_PORT_PCS_AUX + 4 * (dw)) > -#define _ICL_PORT_PCS_DW_GRP(dw, port) (_ICL_COMBOPHY(port) + \ > +#define _ICL_PORT_PCS_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \ > _ICL_PORT_PCS_GRP + 4 * (dw)) > -#define _ICL_PORT_PCS_DW_LN(dw, ln, port) (_ICL_COMBOPHY(port) + \ > +#define _ICL_PORT_PCS_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \ > _ICL_PORT_PCS_LN(ln) + 4 * (dw)) > -#define ICL_PORT_PCS_DW1_AUX(port) _MMIO(_ICL_PORT_PCS_DW_AUX(1, port)) > -#define ICL_PORT_PCS_DW1_GRP(port) _MMIO(_ICL_PORT_PCS_DW_GRP(1, port)) > -#define ICL_PORT_PCS_DW1_LN0(port) _MMIO(_ICL_PORT_PCS_DW_LN(1, 0, port)) > +#define ICL_PORT_PCS_DW1_AUX(phy) _MMIO(_ICL_PORT_PCS_DW_AUX(1, phy)) > +#define ICL_PORT_PCS_DW1_GRP(phy) _MMIO(_ICL_PORT_PCS_DW_GRP(1, phy)) > +#define ICL_PORT_PCS_DW1_LN0(phy) _MMIO(_ICL_PORT_PCS_DW_LN(1, 0, phy)) > #define COMMON_KEEPER_EN (1 << 26) > #define LATENCY_OPTIM_MASK (0x3 << 2) > #define LATENCY_OPTIM_VAL(x) ((x) << 2) > @@ -1933,18 +1933,18 @@ enum i915_power_well_id { > #define _ICL_PORT_TX_GRP 0x680 > #define _ICL_PORT_TX_LN(ln) (0x880 + (ln) * 0x100) > > -#define _ICL_PORT_TX_DW_AUX(dw, port) (_ICL_COMBOPHY(port) + \ > +#define _ICL_PORT_TX_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \ > _ICL_PORT_TX_AUX + 4 * (dw)) > -#define _ICL_PORT_TX_DW_GRP(dw, port) (_ICL_COMBOPHY(port) + \ > +#define _ICL_PORT_TX_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \ > _ICL_PORT_TX_GRP + 4 * (dw)) > -#define _ICL_PORT_TX_DW_LN(dw, ln, port) (_ICL_COMBOPHY(port) + \ > +#define _ICL_PORT_TX_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \ > _ICL_PORT_TX_LN(ln) + 4 * (dw)) > > #define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(2, port)) > #define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(2, port)) > -#define ICL_PORT_TX_DW2_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(2, port)) > -#define ICL_PORT_TX_DW2_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(2, port)) > -#define ICL_PORT_TX_DW2_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(2, 0, port)) > +#define ICL_PORT_TX_DW2_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(2, phy)) > +#define ICL_PORT_TX_DW2_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(2, phy)) > +#define ICL_PORT_TX_DW2_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(2, 0, phy)) > #define SWING_SEL_UPPER(x) (((x) >> 3) << 15) > #define SWING_SEL_UPPER_MASK (1 << 15) > #define SWING_SEL_LOWER(x) (((x) & 0x7) << 11) > @@ -1961,10 +1961,10 @@ enum i915_power_well_id { > #define CNL_PORT_TX_DW4_LN(ln, port) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)) + \ > ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \ > _CNL_PORT_TX_DW4_LN0_AE))) > -#define ICL_PORT_TX_DW4_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(4, port)) > -#define ICL_PORT_TX_DW4_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(4, port)) > -#define ICL_PORT_TX_DW4_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(4, 0, port)) > -#define ICL_PORT_TX_DW4_LN(ln, port) _MMIO(_ICL_PORT_TX_DW_LN(4, ln, port)) > +#define ICL_PORT_TX_DW4_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(4, phy)) > +#define ICL_PORT_TX_DW4_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(4, phy)) > +#define ICL_PORT_TX_DW4_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(4, 0, phy)) > +#define ICL_PORT_TX_DW4_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(4, ln, phy)) > #define LOADGEN_SELECT (1 << 31) > #define POST_CURSOR_1(x) ((x) << 12) > #define POST_CURSOR_1_MASK (0x3F << 12) > @@ -1975,9 +1975,9 @@ enum i915_power_well_id { > > #define CNL_PORT_TX_DW5_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(5, port)) > #define CNL_PORT_TX_DW5_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(5, port)) > -#define ICL_PORT_TX_DW5_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(5, port)) > -#define ICL_PORT_TX_DW5_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(5, port)) > -#define ICL_PORT_TX_DW5_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(5, 0, port)) > +#define ICL_PORT_TX_DW5_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(5, phy)) > +#define ICL_PORT_TX_DW5_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(5, phy)) > +#define ICL_PORT_TX_DW5_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(5, 0, phy)) > #define TX_TRAINING_EN (1 << 31) > #define TAP2_DISABLE (1 << 30) > #define TAP3_DISABLE (1 << 29) > @@ -1988,10 +1988,10 @@ enum i915_power_well_id { > > #define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(7, (port))) > #define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(7, (port))) > -#define ICL_PORT_TX_DW7_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(7, port)) > -#define ICL_PORT_TX_DW7_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(7, port)) > -#define ICL_PORT_TX_DW7_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, port)) > -#define ICL_PORT_TX_DW7_LN(ln, port) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, port)) > +#define ICL_PORT_TX_DW7_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(7, phy)) > +#define ICL_PORT_TX_DW7_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(7, phy)) > +#define ICL_PORT_TX_DW7_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, phy)) > +#define ICL_PORT_TX_DW7_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, phy)) > #define N_SCALAR(x) ((x) << 24) > #define N_SCALAR_MASK (0x7F << 24) -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v6 3/5] drm/i915/gen11: Convert combo PHY logic to use new 'enum phy' namespace 2019-09-04 13:42 ` Jani Nikula @ 2019-09-04 14:57 ` Matt Roper 2019-09-04 16:47 ` Jani Nikula 0 siblings, 1 reply; 13+ messages in thread From: Matt Roper @ 2019-09-04 14:57 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx On Wed, Sep 04, 2019 at 04:42:49PM +0300, Jani Nikula wrote: > On Tue, 09 Jul 2019, Matt Roper <matthew.d.roper@intel.com> wrote: > > Convert the code that operates directly on gen11 combo PHY's to use the > > new namespace. Combo PHY registers are those named "ICL_PORT_*" plus > > ICL_DPHY_CHKN. > > > > Note that a lot of the PHY programming happens in the MIPI DSI code. > > For clarity I've added a for_each_dsi_phy() to loop over the phys used > > by DSI. Since DSI always uses A & B on gen11, port=phy in all cases so > > it doesn't actually matter which form we use in the DSI code. I've used > > the phy iterator in code that's explicitly working with the combo PHY, > > but left the rest of the DSI code using the port iterator and namespace > > to minimize patch deltas. We can switch the rest of the DSI code over > > to use phy terminology later if this winds up being too confusing. > > One itsy-bitsy detail, where does this initialize intel_dsi->phys? > Looking at the code, I'm thinking nowhere. At the moment we're relying on the fact that port==phy always for DSI on the platforms this code applies to. intel_dsi->ports is initialized if (dev_priv->vbt.dsi.config->dual_link) intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B); else intel_dsi->ports = BIT(port); and that's unioned with intel_dsi->phys /* bit mask of ports (vlv dsi) or phys (icl dsi) being driven */ union { u16 ports; /* VLV DSI */ u16 phys; /* ICL DSI */ }; so I think the initialization should be the same as it was before this patch. As I mentioned above, this patch only changes the instances of 'enum port' to 'enum phy' where they were specifically touching the combo PHY registers, and left a bunch of the other code using 'enum port' to minimize the initial code diffs. It's probably time now to follow up with another patch that converts the rest of the file to phy usage to avoid confusion; I'll write a patch to do that later today or tomorrow. > > We have an ICL DSI machine in CI, which reports all green on this > patch... but most likely the display is all black instead. DSI being > DSI, it is entirely possible we have no way of knowing without having a > camera capture the display. Hmm. All green all the time or only on specific tests/operations? I assume this is https://intel-gfx-ci.01.org/hardware/fi-icl-dsi/ ? Strangely I don't see an i915_display_info for that machine, but the current CI results seem to be mostly passing. Is there a specific failing test I should look at? Matt > > BR, > Jani. > > > > > > v6: Drop an include of drm/i915_drm.h; that was previously included just > > for the definition of 'enum port' which this patch removes the need > > for. (Jose) > > > > Cc: José Roberto de Souza <jose.souza@intel.com> > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> > > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Reviewed-by: José Roberto de Souza <jose.souza@intel.com> > > --- > > drivers/gpu/drm/i915/display/icl_dsi.c | 127 ++++++++-------- > > .../gpu/drm/i915/display/intel_combo_phy.c | 143 +++++++++--------- > > .../gpu/drm/i915/display/intel_combo_phy.h | 4 +- > > drivers/gpu/drm/i915/display/intel_ddi.c | 45 +++--- > > drivers/gpu/drm/i915/display/intel_display.h | 4 + > > .../drm/i915/display/intel_display_power.c | 16 +- > > drivers/gpu/drm/i915/display/intel_dsi.h | 12 +- > > drivers/gpu/drm/i915/i915_reg.h | 74 ++++----- > > 8 files changed, 213 insertions(+), 212 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c > > index 8f1324c2f539..4d952accfaaa 100644 > > --- a/drivers/gpu/drm/i915/display/icl_dsi.c > > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c > > @@ -202,63 +202,62 @@ static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder) > > { > > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); > > - enum port port; > > + enum phy phy; > > u32 tmp; > > int lane; > > > > - for_each_dsi_port(port, intel_dsi->ports) { > > - > > + for_each_dsi_phy(phy, intel_dsi->phys) { > > /* > > * Program voltage swing and pre-emphasis level values as per > > * table in BSPEC under DDI buffer programing > > */ > > - tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port)); > > + tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); > > tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK); > > tmp |= SCALING_MODE_SEL(0x2); > > tmp |= TAP2_DISABLE | TAP3_DISABLE; > > tmp |= RTERM_SELECT(0x6); > > - I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp); > > + I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), tmp); > > > > - tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port)); > > + tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy)); > > tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK); > > tmp |= SCALING_MODE_SEL(0x2); > > tmp |= TAP2_DISABLE | TAP3_DISABLE; > > tmp |= RTERM_SELECT(0x6); > > - I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp); > > + I915_WRITE(ICL_PORT_TX_DW5_AUX(phy), tmp); > > > > - tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port)); > > + tmp = I915_READ(ICL_PORT_TX_DW2_LN0(phy)); > > tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | > > RCOMP_SCALAR_MASK); > > tmp |= SWING_SEL_UPPER(0x2); > > tmp |= SWING_SEL_LOWER(0x2); > > tmp |= RCOMP_SCALAR(0x98); > > - I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp); > > + I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), tmp); > > > > - tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port)); > > + tmp = I915_READ(ICL_PORT_TX_DW2_AUX(phy)); > > tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | > > RCOMP_SCALAR_MASK); > > tmp |= SWING_SEL_UPPER(0x2); > > tmp |= SWING_SEL_LOWER(0x2); > > tmp |= RCOMP_SCALAR(0x98); > > - I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp); > > + I915_WRITE(ICL_PORT_TX_DW2_AUX(phy), tmp); > > > > - tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port)); > > + tmp = I915_READ(ICL_PORT_TX_DW4_AUX(phy)); > > tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | > > CURSOR_COEFF_MASK); > > tmp |= POST_CURSOR_1(0x0); > > tmp |= POST_CURSOR_2(0x0); > > tmp |= CURSOR_COEFF(0x3f); > > - I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp); > > + I915_WRITE(ICL_PORT_TX_DW4_AUX(phy), tmp); > > > > for (lane = 0; lane <= 3; lane++) { > > /* Bspec: must not use GRP register for write */ > > - tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, port)); > > + tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, phy)); > > tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | > > CURSOR_COEFF_MASK); > > tmp |= POST_CURSOR_1(0x0); > > tmp |= POST_CURSOR_2(0x0); > > tmp |= CURSOR_COEFF(0x3f); > > - I915_WRITE(ICL_PORT_TX_DW4_LN(lane, port), tmp); > > + I915_WRITE(ICL_PORT_TX_DW4_LN(lane, phy), tmp); > > } > > } > > } > > @@ -364,10 +363,10 @@ static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder) > > { > > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); > > - enum port port; > > + enum phy phy; > > > > - for_each_dsi_port(port, intel_dsi->ports) > > - intel_combo_phy_power_up_lanes(dev_priv, port, true, > > + for_each_dsi_phy(phy, intel_dsi->phys) > > + intel_combo_phy_power_up_lanes(dev_priv, phy, true, > > intel_dsi->lane_count, false); > > } > > > > @@ -375,46 +374,46 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder) > > { > > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); > > - enum port port; > > + enum phy phy; > > u32 tmp; > > int lane; > > > > /* Step 4b(i) set loadgen select for transmit and aux lanes */ > > - for_each_dsi_port(port, intel_dsi->ports) { > > - tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port)); > > + for_each_dsi_phy(phy, intel_dsi->phys) { > > + tmp = I915_READ(ICL_PORT_TX_DW4_AUX(phy)); > > tmp &= ~LOADGEN_SELECT; > > - I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp); > > + I915_WRITE(ICL_PORT_TX_DW4_AUX(phy), tmp); > > for (lane = 0; lane <= 3; lane++) { > > - tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, port)); > > + tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, phy)); > > tmp &= ~LOADGEN_SELECT; > > if (lane != 2) > > tmp |= LOADGEN_SELECT; > > - I915_WRITE(ICL_PORT_TX_DW4_LN(lane, port), tmp); > > + I915_WRITE(ICL_PORT_TX_DW4_LN(lane, phy), tmp); > > } > > } > > > > /* Step 4b(ii) set latency optimization for transmit and aux lanes */ > > - for_each_dsi_port(port, intel_dsi->ports) { > > - tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port)); > > + for_each_dsi_phy(phy, intel_dsi->phys) { > > + tmp = I915_READ(ICL_PORT_TX_DW2_AUX(phy)); > > tmp &= ~FRC_LATENCY_OPTIM_MASK; > > tmp |= FRC_LATENCY_OPTIM_VAL(0x5); > > - I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp); > > - tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port)); > > + I915_WRITE(ICL_PORT_TX_DW2_AUX(phy), tmp); > > + tmp = I915_READ(ICL_PORT_TX_DW2_LN0(phy)); > > tmp &= ~FRC_LATENCY_OPTIM_MASK; > > tmp |= FRC_LATENCY_OPTIM_VAL(0x5); > > - I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp); > > + I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), tmp); > > > > /* For EHL set latency optimization for PCS_DW1 lanes */ > > if (IS_ELKHARTLAKE(dev_priv)) { > > - tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(port)); > > + tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(phy)); > > tmp &= ~LATENCY_OPTIM_MASK; > > tmp |= LATENCY_OPTIM_VAL(0); > > - I915_WRITE(ICL_PORT_PCS_DW1_AUX(port), tmp); > > + I915_WRITE(ICL_PORT_PCS_DW1_AUX(phy), tmp); > > > > - tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(port)); > > + tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(phy)); > > tmp &= ~LATENCY_OPTIM_MASK; > > tmp |= LATENCY_OPTIM_VAL(0x1); > > - I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), tmp); > > + I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), tmp); > > } > > } > > > > @@ -425,16 +424,16 @@ static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder) > > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); > > u32 tmp; > > - enum port port; > > + enum phy phy; > > > > /* clear common keeper enable bit */ > > - for_each_dsi_port(port, intel_dsi->ports) { > > - tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(port)); > > + for_each_dsi_phy(phy, intel_dsi->phys) { > > + tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(phy)); > > tmp &= ~COMMON_KEEPER_EN; > > - I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), tmp); > > - tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(port)); > > + I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), tmp); > > + tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(phy)); > > tmp &= ~COMMON_KEEPER_EN; > > - I915_WRITE(ICL_PORT_PCS_DW1_AUX(port), tmp); > > + I915_WRITE(ICL_PORT_PCS_DW1_AUX(phy), tmp); > > } > > > > /* > > @@ -442,33 +441,33 @@ static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder) > > * Note: loadgen select program is done > > * as part of lane phy sequence configuration > > */ > > - for_each_dsi_port(port, intel_dsi->ports) { > > - tmp = I915_READ(ICL_PORT_CL_DW5(port)); > > + for_each_dsi_phy(phy, intel_dsi->phys) { > > + tmp = I915_READ(ICL_PORT_CL_DW5(phy)); > > tmp |= SUS_CLOCK_CONFIG; > > - I915_WRITE(ICL_PORT_CL_DW5(port), tmp); > > + I915_WRITE(ICL_PORT_CL_DW5(phy), tmp); > > } > > > > /* Clear training enable to change swing values */ > > - for_each_dsi_port(port, intel_dsi->ports) { > > - tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port)); > > + for_each_dsi_phy(phy, intel_dsi->phys) { > > + tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); > > tmp &= ~TX_TRAINING_EN; > > - I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp); > > - tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port)); > > + I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), tmp); > > + tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy)); > > tmp &= ~TX_TRAINING_EN; > > - I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp); > > + I915_WRITE(ICL_PORT_TX_DW5_AUX(phy), tmp); > > } > > > > /* Program swing and de-emphasis */ > > dsi_program_swing_and_deemphasis(encoder); > > > > /* Set training enable to trigger update */ > > - for_each_dsi_port(port, intel_dsi->ports) { > > - tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port)); > > + for_each_dsi_phy(phy, intel_dsi->phys) { > > + tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); > > tmp |= TX_TRAINING_EN; > > - I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp); > > - tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port)); > > + I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), tmp); > > + tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy)); > > tmp |= TX_TRAINING_EN; > > - I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp); > > + I915_WRITE(ICL_PORT_TX_DW5_AUX(phy), tmp); > > } > > } > > > > @@ -497,6 +496,7 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder) > > struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); > > u32 tmp; > > enum port port; > > + enum phy phy; > > > > /* Program T-INIT master registers */ > > for_each_dsi_port(port, intel_dsi->ports) { > > @@ -546,10 +546,10 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder) > > } > > > > if (IS_ELKHARTLAKE(dev_priv)) { > > - for_each_dsi_port(port, intel_dsi->ports) { > > - tmp = I915_READ(ICL_DPHY_CHKN(port)); > > + for_each_dsi_phy(phy, intel_dsi->phys) { > > + tmp = I915_READ(ICL_DPHY_CHKN(phy)); > > tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP; > > - I915_WRITE(ICL_DPHY_CHKN(port), tmp); > > + I915_WRITE(ICL_DPHY_CHKN(phy), tmp); > > } > > } > > } > > @@ -559,15 +559,12 @@ static void gen11_dsi_gate_clocks(struct intel_encoder *encoder) > > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); > > u32 tmp; > > - enum port port; > > enum phy phy; > > > > mutex_lock(&dev_priv->dpll_lock); > > tmp = I915_READ(ICL_DPCLKA_CFGCR0); > > - for_each_dsi_port(port, intel_dsi->ports) { > > - phy = intel_port_to_phy(dev_priv, port); > > + for_each_dsi_phy(phy, intel_dsi->phys) > > tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); > > - } > > > > I915_WRITE(ICL_DPCLKA_CFGCR0, tmp); > > mutex_unlock(&dev_priv->dpll_lock); > > @@ -578,15 +575,12 @@ static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder) > > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); > > u32 tmp; > > - enum port port; > > enum phy phy; > > > > mutex_lock(&dev_priv->dpll_lock); > > tmp = I915_READ(ICL_DPCLKA_CFGCR0); > > - for_each_dsi_port(port, intel_dsi->ports) { > > - phy = intel_port_to_phy(dev_priv, port); > > + for_each_dsi_phy(phy, intel_dsi->phys) > > tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); > > - } > > > > I915_WRITE(ICL_DPCLKA_CFGCR0, tmp); > > mutex_unlock(&dev_priv->dpll_lock); > > @@ -598,22 +592,19 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder, > > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); > > struct intel_shared_dpll *pll = crtc_state->shared_dpll; > > - enum port port; > > enum phy phy; > > u32 val; > > > > mutex_lock(&dev_priv->dpll_lock); > > > > val = I915_READ(ICL_DPCLKA_CFGCR0); > > - for_each_dsi_port(port, intel_dsi->ports) { > > - phy = intel_port_to_phy(dev_priv, port); > > + for_each_dsi_phy(phy, intel_dsi->phys) { > > val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); > > val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); > > } > > I915_WRITE(ICL_DPCLKA_CFGCR0, val); > > > > - for_each_dsi_port(port, intel_dsi->ports) { > > - phy = intel_port_to_phy(dev_priv, port); > > + for_each_dsi_phy(phy, intel_dsi->phys) { > > val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); > > } > > I915_WRITE(ICL_DPCLKA_CFGCR0, val); > > diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c > > index d3d5244765e6..ac8218a040ab 100644 > > --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c > > +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c > > @@ -6,13 +6,13 @@ > > #include "intel_combo_phy.h" > > #include "intel_drv.h" > > > > -#define for_each_combo_port(__dev_priv, __port) \ > > - for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \ > > - for_each_if(intel_port_is_combophy(__dev_priv, __port)) > > +#define for_each_combo_phy(__dev_priv, __phy) \ > > + for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \ > > + for_each_if(intel_phy_is_combo(__dev_priv, __phy)) > > > > -#define for_each_combo_port_reverse(__dev_priv, __port) \ > > - for ((__port) = I915_MAX_PORTS; (__port)-- > PORT_A;) \ > > - for_each_if(intel_port_is_combophy(__dev_priv, __port)) > > +#define for_each_combo_phy_reverse(__dev_priv, __phy) \ > > + for ((__phy) = I915_MAX_PHYS; (__phy)-- > PHY_A;) \ > > + for_each_if(intel_phy_is_combo(__dev_priv, __phy)) > > > > enum { > > PROCMON_0_85V_DOT_0, > > @@ -38,18 +38,17 @@ static const struct cnl_procmon { > > }; > > > > /* > > - * CNL has just one set of registers, while ICL has two sets: one for port A and > > - * the other for port B. The CNL registers are equivalent to the ICL port A > > - * registers, that's why we call the ICL macros even though the function has CNL > > - * on its name. > > + * CNL has just one set of registers, while gen11 has a set for each combo PHY. > > + * The CNL registers are equivalent to the gen11 PHY A registers, that's why we > > + * call the ICL macros even though the function has CNL on its name. > > */ > > static const struct cnl_procmon * > > -cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum port port) > > +cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy) > > { > > const struct cnl_procmon *procmon; > > u32 val; > > > > - val = I915_READ(ICL_PORT_COMP_DW3(port)); > > + val = I915_READ(ICL_PORT_COMP_DW3(phy)); > > switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) { > > default: > > MISSING_CASE(val); > > @@ -75,32 +74,32 @@ cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum port port) > > } > > > > static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv, > > - enum port port) > > + enum phy phy) > > { > > const struct cnl_procmon *procmon; > > u32 val; > > > > - procmon = cnl_get_procmon_ref_values(dev_priv, port); > > + procmon = cnl_get_procmon_ref_values(dev_priv, phy); > > > > - val = I915_READ(ICL_PORT_COMP_DW1(port)); > > + val = I915_READ(ICL_PORT_COMP_DW1(phy)); > > val &= ~((0xff << 16) | 0xff); > > val |= procmon->dw1; > > - I915_WRITE(ICL_PORT_COMP_DW1(port), val); > > + I915_WRITE(ICL_PORT_COMP_DW1(phy), val); > > > > - I915_WRITE(ICL_PORT_COMP_DW9(port), procmon->dw9); > > - I915_WRITE(ICL_PORT_COMP_DW10(port), procmon->dw10); > > + I915_WRITE(ICL_PORT_COMP_DW9(phy), procmon->dw9); > > + I915_WRITE(ICL_PORT_COMP_DW10(phy), procmon->dw10); > > } > > > > static bool check_phy_reg(struct drm_i915_private *dev_priv, > > - enum port port, i915_reg_t reg, u32 mask, > > + enum phy phy, i915_reg_t reg, u32 mask, > > u32 expected_val) > > { > > u32 val = I915_READ(reg); > > > > if ((val & mask) != expected_val) { > > - DRM_DEBUG_DRIVER("Port %c combo PHY reg %08x state mismatch: " > > + DRM_DEBUG_DRIVER("Combo PHY %c reg %08x state mismatch: " > > "current %08x mask %08x expected %08x\n", > > - port_name(port), > > + phy_name(phy), > > reg.reg, val, mask, expected_val); > > return false; > > } > > @@ -109,18 +108,18 @@ static bool check_phy_reg(struct drm_i915_private *dev_priv, > > } > > > > static bool cnl_verify_procmon_ref_values(struct drm_i915_private *dev_priv, > > - enum port port) > > + enum phy phy) > > { > > const struct cnl_procmon *procmon; > > bool ret; > > > > - procmon = cnl_get_procmon_ref_values(dev_priv, port); > > + procmon = cnl_get_procmon_ref_values(dev_priv, phy); > > > > - ret = check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW1(port), > > + ret = check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW1(phy), > > (0xff << 16) | 0xff, procmon->dw1); > > - ret &= check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW9(port), > > + ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW9(phy), > > -1U, procmon->dw9); > > - ret &= check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW10(port), > > + ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW10(phy), > > -1U, procmon->dw10); > > > > return ret; > > @@ -134,15 +133,15 @@ static bool cnl_combo_phy_enabled(struct drm_i915_private *dev_priv) > > > > static bool cnl_combo_phy_verify_state(struct drm_i915_private *dev_priv) > > { > > - enum port port = PORT_A; > > + enum phy phy = PHY_A; > > bool ret; > > > > if (!cnl_combo_phy_enabled(dev_priv)) > > return false; > > > > - ret = cnl_verify_procmon_ref_values(dev_priv, port); > > + ret = cnl_verify_procmon_ref_values(dev_priv, phy); > > > > - ret &= check_phy_reg(dev_priv, port, CNL_PORT_CL1CM_DW5, > > + ret &= check_phy_reg(dev_priv, phy, CNL_PORT_CL1CM_DW5, > > CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE); > > > > return ret; > > @@ -157,7 +156,7 @@ static void cnl_combo_phys_init(struct drm_i915_private *dev_priv) > > I915_WRITE(CHICKEN_MISC_2, val); > > > > /* Dummy PORT_A to get the correct CNL register from the ICL macro */ > > - cnl_set_procmon_ref_values(dev_priv, PORT_A); > > + cnl_set_procmon_ref_values(dev_priv, PHY_A); > > > > val = I915_READ(CNL_PORT_COMP_DW0); > > val |= COMP_INIT; > > @@ -181,39 +180,39 @@ static void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv) > > } > > > > static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv, > > - enum port port) > > + enum phy phy) > > { > > /* The PHY C added by EHL has no PHY_MISC register */ > > - if (IS_ELKHARTLAKE(dev_priv) && port == PORT_C) > > - return I915_READ(ICL_PORT_COMP_DW0(port)) & COMP_INIT; > > + if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C) > > + return I915_READ(ICL_PORT_COMP_DW0(phy)) & COMP_INIT; > > else > > - return !(I915_READ(ICL_PHY_MISC(port)) & > > + return !(I915_READ(ICL_PHY_MISC(phy)) & > > ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) && > > - (I915_READ(ICL_PORT_COMP_DW0(port)) & COMP_INIT); > > + (I915_READ(ICL_PORT_COMP_DW0(phy)) & COMP_INIT); > > } > > > > static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv, > > - enum port port) > > + enum phy phy) > > { > > bool ret; > > > > - if (!icl_combo_phy_enabled(dev_priv, port)) > > + if (!icl_combo_phy_enabled(dev_priv, phy)) > > return false; > > > > - ret = cnl_verify_procmon_ref_values(dev_priv, port); > > + ret = cnl_verify_procmon_ref_values(dev_priv, phy); > > > > - if (port == PORT_A) > > - ret &= check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW8(port), > > + if (phy == PHY_A) > > + ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy), > > IREFGEN, IREFGEN); > > > > - ret &= check_phy_reg(dev_priv, port, ICL_PORT_CL_DW5(port), > > + ret &= check_phy_reg(dev_priv, phy, ICL_PORT_CL_DW5(phy), > > CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE); > > > > return ret; > > } > > > > void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv, > > - enum port port, bool is_dsi, > > + enum phy phy, bool is_dsi, > > int lane_count, bool lane_reversal) > > { > > u8 lane_mask; > > @@ -258,10 +257,10 @@ void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv, > > } > > } > > > > - val = I915_READ(ICL_PORT_CL_DW10(port)); > > + val = I915_READ(ICL_PORT_CL_DW10(phy)); > > val &= ~PWR_DOWN_LN_MASK; > > val |= lane_mask << PWR_DOWN_LN_SHIFT; > > - I915_WRITE(ICL_PORT_CL_DW10(port), val); > > + I915_WRITE(ICL_PORT_CL_DW10(phy), val); > > } > > > > static u32 ehl_combo_phy_a_mux(struct drm_i915_private *i915, u32 val) > > @@ -292,14 +291,14 @@ static u32 ehl_combo_phy_a_mux(struct drm_i915_private *i915, u32 val) > > > > static void icl_combo_phys_init(struct drm_i915_private *dev_priv) > > { > > - enum port port; > > + enum phy phy; > > > > - for_each_combo_port(dev_priv, port) { > > + for_each_combo_phy(dev_priv, phy) { > > u32 val; > > > > - if (icl_combo_phy_verify_state(dev_priv, port)) { > > - DRM_DEBUG_DRIVER("Port %c combo PHY already enabled, won't reprogram it.\n", > > - port_name(port)); > > + if (icl_combo_phy_verify_state(dev_priv, phy)) { > > + DRM_DEBUG_DRIVER("Combo PHY %c already enabled, won't reprogram it.\n", > > + phy_name(phy)); > > continue; > > } > > > > @@ -308,7 +307,7 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv) > > * register for it and no need to program the > > * DE_IO_COMP_PWR_DOWN setting on PHY C. > > */ > > - if (IS_ELKHARTLAKE(dev_priv) && port == PORT_C) > > + if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C) > > goto skip_phy_misc; > > > > /* > > @@ -319,59 +318,59 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv) > > * based on whether our VBT indicates the presence of any > > * "internal" child devices. > > */ > > - val = I915_READ(ICL_PHY_MISC(port)); > > - if (IS_ELKHARTLAKE(dev_priv) && port == PORT_A) > > + val = I915_READ(ICL_PHY_MISC(phy)); > > + if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_A) > > val = ehl_combo_phy_a_mux(dev_priv, val); > > val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN; > > - I915_WRITE(ICL_PHY_MISC(port), val); > > + I915_WRITE(ICL_PHY_MISC(phy), val); > > > > skip_phy_misc: > > - cnl_set_procmon_ref_values(dev_priv, port); > > + cnl_set_procmon_ref_values(dev_priv, phy); > > > > - if (port == PORT_A) { > > - val = I915_READ(ICL_PORT_COMP_DW8(port)); > > + if (phy == PHY_A) { > > + val = I915_READ(ICL_PORT_COMP_DW8(phy)); > > val |= IREFGEN; > > - I915_WRITE(ICL_PORT_COMP_DW8(port), val); > > + I915_WRITE(ICL_PORT_COMP_DW8(phy), val); > > } > > > > - val = I915_READ(ICL_PORT_COMP_DW0(port)); > > + val = I915_READ(ICL_PORT_COMP_DW0(phy)); > > val |= COMP_INIT; > > - I915_WRITE(ICL_PORT_COMP_DW0(port), val); > > + I915_WRITE(ICL_PORT_COMP_DW0(phy), val); > > > > - val = I915_READ(ICL_PORT_CL_DW5(port)); > > + val = I915_READ(ICL_PORT_CL_DW5(phy)); > > val |= CL_POWER_DOWN_ENABLE; > > - I915_WRITE(ICL_PORT_CL_DW5(port), val); > > + I915_WRITE(ICL_PORT_CL_DW5(phy), val); > > } > > } > > > > static void icl_combo_phys_uninit(struct drm_i915_private *dev_priv) > > { > > - enum port port; > > + enum phy phy; > > > > - for_each_combo_port_reverse(dev_priv, port) { > > + for_each_combo_phy_reverse(dev_priv, phy) { > > u32 val; > > > > - if (port == PORT_A && > > - !icl_combo_phy_verify_state(dev_priv, port)) > > - DRM_WARN("Port %c combo PHY HW state changed unexpectedly\n", > > - port_name(port)); > > + if (phy == PHY_A && > > + !icl_combo_phy_verify_state(dev_priv, phy)) > > + DRM_WARN("Combo PHY %c HW state changed unexpectedly\n", > > + phy_name(phy)); > > > > /* > > * Although EHL adds a combo PHY C, there's no PHY_MISC > > * register for it and no need to program the > > * DE_IO_COMP_PWR_DOWN setting on PHY C. > > */ > > - if (IS_ELKHARTLAKE(dev_priv) && port == PORT_C) > > + if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C) > > goto skip_phy_misc; > > > > - val = I915_READ(ICL_PHY_MISC(port)); > > + val = I915_READ(ICL_PHY_MISC(phy)); > > val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN; > > - I915_WRITE(ICL_PHY_MISC(port), val); > > + I915_WRITE(ICL_PHY_MISC(phy), val); > > > > skip_phy_misc: > > - val = I915_READ(ICL_PORT_COMP_DW0(port)); > > + val = I915_READ(ICL_PORT_COMP_DW0(phy)); > > val &= ~COMP_INIT; > > - I915_WRITE(ICL_PORT_COMP_DW0(port), val); > > + I915_WRITE(ICL_PORT_COMP_DW0(phy), val); > > } > > } > > > > diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.h b/drivers/gpu/drm/i915/display/intel_combo_phy.h > > index e6e195a83b19..660886f86c59 100644 > > --- a/drivers/gpu/drm/i915/display/intel_combo_phy.h > > +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.h > > @@ -7,14 +7,14 @@ > > #define __INTEL_COMBO_PHY_H__ > > > > #include <linux/types.h> > > -#include <drm/i915_drm.h> > > > > struct drm_i915_private; > > +enum phy; > > > > void intel_combo_phy_init(struct drm_i915_private *dev_priv); > > void intel_combo_phy_uninit(struct drm_i915_private *dev_priv); > > void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv, > > - enum port port, bool is_dsi, > > + enum phy phy, bool is_dsi, > > int lane_count, bool lane_reversal); > > > > #endif /* __INTEL_COMBO_PHY_H__ */ > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > > index b5bc00c4e3fe..d9ea58038642 100644 > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > @@ -2414,7 +2414,7 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, > > } > > > > static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, > > - u32 level, enum port port, int type, > > + u32 level, enum phy phy, int type, > > int rate) > > { > > const struct cnl_ddi_buf_trans *ddi_translations = NULL; > > @@ -2432,41 +2432,41 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, > > } > > > > /* Set PORT_TX_DW5 */ > > - val = I915_READ(ICL_PORT_TX_DW5_LN0(port)); > > + val = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); > > val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | > > TAP2_DISABLE | TAP3_DISABLE); > > val |= SCALING_MODE_SEL(0x2); > > val |= RTERM_SELECT(0x6); > > val |= TAP3_DISABLE; > > - I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val); > > + I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val); > > > > /* Program PORT_TX_DW2 */ > > - val = I915_READ(ICL_PORT_TX_DW2_LN0(port)); > > + val = I915_READ(ICL_PORT_TX_DW2_LN0(phy)); > > val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | > > RCOMP_SCALAR_MASK); > > val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); > > val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); > > /* Program Rcomp scalar for every table entry */ > > val |= RCOMP_SCALAR(0x98); > > - I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val); > > + I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), val); > > > > /* Program PORT_TX_DW4 */ > > /* We cannot write to GRP. It would overwrite individual loadgen. */ > > for (ln = 0; ln <= 3; ln++) { > > - val = I915_READ(ICL_PORT_TX_DW4_LN(ln, port)); > > + val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy)); > > val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | > > CURSOR_COEFF_MASK); > > val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); > > val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); > > val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); > > - I915_WRITE(ICL_PORT_TX_DW4_LN(ln, port), val); > > + I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val); > > } > > > > /* Program PORT_TX_DW7 */ > > - val = I915_READ(ICL_PORT_TX_DW7_LN0(port)); > > + val = I915_READ(ICL_PORT_TX_DW7_LN0(phy)); > > val &= ~N_SCALAR_MASK; > > val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); > > - I915_WRITE(ICL_PORT_TX_DW7_GRP(port), val); > > + I915_WRITE(ICL_PORT_TX_DW7_GRP(phy), val); > > } > > > > static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > > @@ -2474,7 +2474,7 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > > enum intel_output_type type) > > { > > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > - enum port port = encoder->port; > > + enum phy phy = intel_port_to_phy(dev_priv, encoder->port); > > int width = 0; > > int rate = 0; > > u32 val; > > @@ -2495,12 +2495,12 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > > * set PORT_PCS_DW1 cmnkeeper_enable to 1b, > > * else clear to 0b. > > */ > > - val = I915_READ(ICL_PORT_PCS_DW1_LN0(port)); > > + val = I915_READ(ICL_PORT_PCS_DW1_LN0(phy)); > > if (type == INTEL_OUTPUT_HDMI) > > val &= ~COMMON_KEEPER_EN; > > else > > val |= COMMON_KEEPER_EN; > > - I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), val); > > + I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), val); > > > > /* 2. Program loadgen select */ > > /* > > @@ -2510,33 +2510,33 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > > * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) > > */ > > for (ln = 0; ln <= 3; ln++) { > > - val = I915_READ(ICL_PORT_TX_DW4_LN(ln, port)); > > + val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy)); > > val &= ~LOADGEN_SELECT; > > > > if ((rate <= 600000 && width == 4 && ln >= 1) || > > (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { > > val |= LOADGEN_SELECT; > > } > > - I915_WRITE(ICL_PORT_TX_DW4_LN(ln, port), val); > > + I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val); > > } > > > > /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ > > - val = I915_READ(ICL_PORT_CL_DW5(port)); > > + val = I915_READ(ICL_PORT_CL_DW5(phy)); > > val |= SUS_CLOCK_CONFIG; > > - I915_WRITE(ICL_PORT_CL_DW5(port), val); > > + I915_WRITE(ICL_PORT_CL_DW5(phy), val); > > > > /* 4. Clear training enable to change swing values */ > > - val = I915_READ(ICL_PORT_TX_DW5_LN0(port)); > > + val = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); > > val &= ~TX_TRAINING_EN; > > - I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val); > > + I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val); > > > > /* 5. Program swing and de-emphasis */ > > - icl_ddi_combo_vswing_program(dev_priv, level, port, type, rate); > > + icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate); > > > > /* 6. Set training enable to trigger update */ > > - val = I915_READ(ICL_PORT_TX_DW5_LN0(port)); > > + val = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); > > val |= TX_TRAINING_EN; > > - I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val); > > + I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val); > > } > > > > static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > > @@ -3121,6 +3121,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, > > struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); > > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > enum port port = encoder->port; > > + enum phy phy = intel_port_to_phy(dev_priv, port); > > struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); > > bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); > > int level = intel_ddi_dp_level(intel_dp); > > @@ -3156,7 +3157,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, > > bool lane_reversal = > > dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; > > > > - intel_combo_phy_power_up_lanes(dev_priv, port, false, > > + intel_combo_phy_power_up_lanes(dev_priv, phy, false, > > crtc_state->lane_count, > > lane_reversal); > > } > > diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h > > index d53285fb883f..8a4a57ef82a2 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.h > > +++ b/drivers/gpu/drm/i915/display/intel_display.h > > @@ -268,6 +268,10 @@ enum phy { > > for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \ > > for_each_if((__ports_mask) & BIT(__port)) > > > > +#define for_each_phy_masked(__phy, __phys_mask) \ > > + for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \ > > + for_each_if((__phys_mask) & BIT(__phy)) > > + > > #define for_each_crtc(dev, crtc) \ > > list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c > > index 7437fc71d289..a24d1859b37b 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c > > @@ -397,7 +397,7 @@ static void hsw_power_well_disable(struct drm_i915_private *dev_priv, > > hsw_wait_for_power_well_disable(dev_priv, power_well); > > } > > > > -#define ICL_AUX_PW_TO_PORT(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A) > > +#define ICL_AUX_PW_TO_PHY(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A) > > > > static void > > icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, > > @@ -405,21 +405,21 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, > > { > > const struct i915_power_well_regs *regs = power_well->desc->hsw.regs; > > int pw_idx = power_well->desc->hsw.idx; > > - enum port port = ICL_AUX_PW_TO_PORT(pw_idx); > > + enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx); > > u32 val; > > > > val = I915_READ(regs->driver); > > I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx)); > > > > - val = I915_READ(ICL_PORT_CL_DW12(port)); > > - I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX); > > + val = I915_READ(ICL_PORT_CL_DW12(phy)); > > + I915_WRITE(ICL_PORT_CL_DW12(phy), val | ICL_LANE_ENABLE_AUX); > > > > hsw_wait_for_power_well_enable(dev_priv, power_well); > > > > /* Display WA #1178: icl */ > > if (IS_ICELAKE(dev_priv) && > > pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B && > > - !intel_bios_is_port_edp(dev_priv, port)) { > > + !intel_bios_is_port_edp(dev_priv, (enum port)phy)) { > > val = I915_READ(ICL_AUX_ANAOVRD1(pw_idx)); > > val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS; > > I915_WRITE(ICL_AUX_ANAOVRD1(pw_idx), val); > > @@ -432,11 +432,11 @@ icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv, > > { > > const struct i915_power_well_regs *regs = power_well->desc->hsw.regs; > > int pw_idx = power_well->desc->hsw.idx; > > - enum port port = ICL_AUX_PW_TO_PORT(pw_idx); > > + enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx); > > u32 val; > > > > - val = I915_READ(ICL_PORT_CL_DW12(port)); > > - I915_WRITE(ICL_PORT_CL_DW12(port), val & ~ICL_LANE_ENABLE_AUX); > > + val = I915_READ(ICL_PORT_CL_DW12(phy)); > > + I915_WRITE(ICL_PORT_CL_DW12(phy), val & ~ICL_LANE_ENABLE_AUX); > > > > val = I915_READ(regs->driver); > > I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx)); > > diff --git a/drivers/gpu/drm/i915/display/intel_dsi.h b/drivers/gpu/drm/i915/display/intel_dsi.h > > index 6d20434636cd..1cd24bd46518 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dsi.h > > +++ b/drivers/gpu/drm/i915/display/intel_dsi.h > > @@ -49,8 +49,11 @@ struct intel_dsi { > > > > struct intel_connector *attached_connector; > > > > - /* bit mask of ports being driven */ > > - u16 ports; > > + /* bit mask of ports (vlv dsi) or phys (icl dsi) being driven */ > > + union { > > + u16 ports; /* VLV DSI */ > > + u16 phys; /* ICL DSI */ > > + }; > > > > /* if true, use HS mode, otherwise LP */ > > bool hs; > > @@ -132,7 +135,10 @@ static inline struct intel_dsi_host *to_intel_dsi_host(struct mipi_dsi_host *h) > > return container_of(h, struct intel_dsi_host, base); > > } > > > > -#define for_each_dsi_port(__port, __ports_mask) for_each_port_masked(__port, __ports_mask) > > +#define for_each_dsi_port(__port, __ports_mask) \ > > + for_each_port_masked(__port, __ports_mask) > > +#define for_each_dsi_phy(__phy, __phys_mask) \ > > + for_each_phy_masked(__phy, __phys_mask) > > > > static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder) > > { > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > index d3fc575a94db..95b9ca1fda2e 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -1794,20 +1794,20 @@ enum i915_power_well_id { > > #define _ICL_COMBOPHY_A 0x162000 > > #define _ICL_COMBOPHY_B 0x6C000 > > #define _EHL_COMBOPHY_C 0x160000 > > -#define _ICL_COMBOPHY(port) _PICK(port, _ICL_COMBOPHY_A, \ > > +#define _ICL_COMBOPHY(phy) _PICK(phy, _ICL_COMBOPHY_A, \ > > _ICL_COMBOPHY_B, \ > > _EHL_COMBOPHY_C) > > > > /* CNL/ICL Port CL_DW registers */ > > -#define _ICL_PORT_CL_DW(dw, port) (_ICL_COMBOPHY(port) + \ > > +#define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \ > > 4 * (dw)) > > > > #define CNL_PORT_CL1CM_DW5 _MMIO(0x162014) > > -#define ICL_PORT_CL_DW5(port) _MMIO(_ICL_PORT_CL_DW(5, port)) > > +#define ICL_PORT_CL_DW5(phy) _MMIO(_ICL_PORT_CL_DW(5, phy)) > > #define CL_POWER_DOWN_ENABLE (1 << 4) > > #define SUS_CLOCK_CONFIG (3 << 0) > > > > -#define ICL_PORT_CL_DW10(port) _MMIO(_ICL_PORT_CL_DW(10, port)) > > +#define ICL_PORT_CL_DW10(phy) _MMIO(_ICL_PORT_CL_DW(10, phy)) > > #define PG_SEQ_DELAY_OVERRIDE_MASK (3 << 25) > > #define PG_SEQ_DELAY_OVERRIDE_SHIFT 25 > > #define PG_SEQ_DELAY_OVERRIDE_ENABLE (1 << 24) > > @@ -1822,23 +1822,23 @@ enum i915_power_well_id { > > #define PWR_DOWN_LN_MASK (0xf << 4) > > #define PWR_DOWN_LN_SHIFT 4 > > > > -#define ICL_PORT_CL_DW12(port) _MMIO(_ICL_PORT_CL_DW(12, port)) > > +#define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy)) > > #define ICL_LANE_ENABLE_AUX (1 << 0) > > > > /* CNL/ICL Port COMP_DW registers */ > > #define _ICL_PORT_COMP 0x100 > > -#define _ICL_PORT_COMP_DW(dw, port) (_ICL_COMBOPHY(port) + \ > > +#define _ICL_PORT_COMP_DW(dw, phy) (_ICL_COMBOPHY(phy) + \ > > _ICL_PORT_COMP + 4 * (dw)) > > > > #define CNL_PORT_COMP_DW0 _MMIO(0x162100) > > -#define ICL_PORT_COMP_DW0(port) _MMIO(_ICL_PORT_COMP_DW(0, port)) > > +#define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy)) > > #define COMP_INIT (1 << 31) > > > > #define CNL_PORT_COMP_DW1 _MMIO(0x162104) > > -#define ICL_PORT_COMP_DW1(port) _MMIO(_ICL_PORT_COMP_DW(1, port)) > > +#define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy)) > > > > #define CNL_PORT_COMP_DW3 _MMIO(0x16210c) > > -#define ICL_PORT_COMP_DW3(port) _MMIO(_ICL_PORT_COMP_DW(3, port)) > > +#define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy)) > > #define PROCESS_INFO_DOT_0 (0 << 26) > > #define PROCESS_INFO_DOT_1 (1 << 26) > > #define PROCESS_INFO_DOT_4 (2 << 26) > > @@ -1850,14 +1850,14 @@ enum i915_power_well_id { > > #define VOLTAGE_INFO_MASK (3 << 24) > > #define VOLTAGE_INFO_SHIFT 24 > > > > -#define ICL_PORT_COMP_DW8(port) _MMIO(_ICL_PORT_COMP_DW(8, port)) > > +#define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy)) > > #define IREFGEN (1 << 24) > > > > #define CNL_PORT_COMP_DW9 _MMIO(0x162124) > > -#define ICL_PORT_COMP_DW9(port) _MMIO(_ICL_PORT_COMP_DW(9, port)) > > +#define ICL_PORT_COMP_DW9(phy) _MMIO(_ICL_PORT_COMP_DW(9, phy)) > > > > #define CNL_PORT_COMP_DW10 _MMIO(0x162128) > > -#define ICL_PORT_COMP_DW10(port) _MMIO(_ICL_PORT_COMP_DW(10, port)) > > +#define ICL_PORT_COMP_DW10(phy) _MMIO(_ICL_PORT_COMP_DW(10, phy)) > > > > /* CNL/ICL Port PCS registers */ > > #define _CNL_PORT_PCS_DW1_GRP_AE 0x162304 > > @@ -1870,14 +1870,14 @@ enum i915_power_well_id { > > #define _CNL_PORT_PCS_DW1_LN0_C 0x162C04 > > #define _CNL_PORT_PCS_DW1_LN0_D 0x162E04 > > #define _CNL_PORT_PCS_DW1_LN0_F 0x162804 > > -#define CNL_PORT_PCS_DW1_GRP(port) _MMIO(_PICK(port, \ > > +#define CNL_PORT_PCS_DW1_GRP(phy) _MMIO(_PICK(phy, \ > > _CNL_PORT_PCS_DW1_GRP_AE, \ > > _CNL_PORT_PCS_DW1_GRP_B, \ > > _CNL_PORT_PCS_DW1_GRP_C, \ > > _CNL_PORT_PCS_DW1_GRP_D, \ > > _CNL_PORT_PCS_DW1_GRP_AE, \ > > _CNL_PORT_PCS_DW1_GRP_F)) > > -#define CNL_PORT_PCS_DW1_LN0(port) _MMIO(_PICK(port, \ > > +#define CNL_PORT_PCS_DW1_LN0(phy) _MMIO(_PICK(phy, \ > > _CNL_PORT_PCS_DW1_LN0_AE, \ > > _CNL_PORT_PCS_DW1_LN0_B, \ > > _CNL_PORT_PCS_DW1_LN0_C, \ > > @@ -1888,15 +1888,15 @@ enum i915_power_well_id { > > #define _ICL_PORT_PCS_AUX 0x300 > > #define _ICL_PORT_PCS_GRP 0x600 > > #define _ICL_PORT_PCS_LN(ln) (0x800 + (ln) * 0x100) > > -#define _ICL_PORT_PCS_DW_AUX(dw, port) (_ICL_COMBOPHY(port) + \ > > +#define _ICL_PORT_PCS_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \ > > _ICL_PORT_PCS_AUX + 4 * (dw)) > > -#define _ICL_PORT_PCS_DW_GRP(dw, port) (_ICL_COMBOPHY(port) + \ > > +#define _ICL_PORT_PCS_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \ > > _ICL_PORT_PCS_GRP + 4 * (dw)) > > -#define _ICL_PORT_PCS_DW_LN(dw, ln, port) (_ICL_COMBOPHY(port) + \ > > +#define _ICL_PORT_PCS_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \ > > _ICL_PORT_PCS_LN(ln) + 4 * (dw)) > > -#define ICL_PORT_PCS_DW1_AUX(port) _MMIO(_ICL_PORT_PCS_DW_AUX(1, port)) > > -#define ICL_PORT_PCS_DW1_GRP(port) _MMIO(_ICL_PORT_PCS_DW_GRP(1, port)) > > -#define ICL_PORT_PCS_DW1_LN0(port) _MMIO(_ICL_PORT_PCS_DW_LN(1, 0, port)) > > +#define ICL_PORT_PCS_DW1_AUX(phy) _MMIO(_ICL_PORT_PCS_DW_AUX(1, phy)) > > +#define ICL_PORT_PCS_DW1_GRP(phy) _MMIO(_ICL_PORT_PCS_DW_GRP(1, phy)) > > +#define ICL_PORT_PCS_DW1_LN0(phy) _MMIO(_ICL_PORT_PCS_DW_LN(1, 0, phy)) > > #define COMMON_KEEPER_EN (1 << 26) > > #define LATENCY_OPTIM_MASK (0x3 << 2) > > #define LATENCY_OPTIM_VAL(x) ((x) << 2) > > @@ -1933,18 +1933,18 @@ enum i915_power_well_id { > > #define _ICL_PORT_TX_GRP 0x680 > > #define _ICL_PORT_TX_LN(ln) (0x880 + (ln) * 0x100) > > > > -#define _ICL_PORT_TX_DW_AUX(dw, port) (_ICL_COMBOPHY(port) + \ > > +#define _ICL_PORT_TX_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \ > > _ICL_PORT_TX_AUX + 4 * (dw)) > > -#define _ICL_PORT_TX_DW_GRP(dw, port) (_ICL_COMBOPHY(port) + \ > > +#define _ICL_PORT_TX_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \ > > _ICL_PORT_TX_GRP + 4 * (dw)) > > -#define _ICL_PORT_TX_DW_LN(dw, ln, port) (_ICL_COMBOPHY(port) + \ > > +#define _ICL_PORT_TX_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \ > > _ICL_PORT_TX_LN(ln) + 4 * (dw)) > > > > #define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(2, port)) > > #define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(2, port)) > > -#define ICL_PORT_TX_DW2_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(2, port)) > > -#define ICL_PORT_TX_DW2_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(2, port)) > > -#define ICL_PORT_TX_DW2_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(2, 0, port)) > > +#define ICL_PORT_TX_DW2_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(2, phy)) > > +#define ICL_PORT_TX_DW2_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(2, phy)) > > +#define ICL_PORT_TX_DW2_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(2, 0, phy)) > > #define SWING_SEL_UPPER(x) (((x) >> 3) << 15) > > #define SWING_SEL_UPPER_MASK (1 << 15) > > #define SWING_SEL_LOWER(x) (((x) & 0x7) << 11) > > @@ -1961,10 +1961,10 @@ enum i915_power_well_id { > > #define CNL_PORT_TX_DW4_LN(ln, port) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)) + \ > > ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \ > > _CNL_PORT_TX_DW4_LN0_AE))) > > -#define ICL_PORT_TX_DW4_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(4, port)) > > -#define ICL_PORT_TX_DW4_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(4, port)) > > -#define ICL_PORT_TX_DW4_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(4, 0, port)) > > -#define ICL_PORT_TX_DW4_LN(ln, port) _MMIO(_ICL_PORT_TX_DW_LN(4, ln, port)) > > +#define ICL_PORT_TX_DW4_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(4, phy)) > > +#define ICL_PORT_TX_DW4_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(4, phy)) > > +#define ICL_PORT_TX_DW4_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(4, 0, phy)) > > +#define ICL_PORT_TX_DW4_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(4, ln, phy)) > > #define LOADGEN_SELECT (1 << 31) > > #define POST_CURSOR_1(x) ((x) << 12) > > #define POST_CURSOR_1_MASK (0x3F << 12) > > @@ -1975,9 +1975,9 @@ enum i915_power_well_id { > > > > #define CNL_PORT_TX_DW5_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(5, port)) > > #define CNL_PORT_TX_DW5_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(5, port)) > > -#define ICL_PORT_TX_DW5_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(5, port)) > > -#define ICL_PORT_TX_DW5_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(5, port)) > > -#define ICL_PORT_TX_DW5_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(5, 0, port)) > > +#define ICL_PORT_TX_DW5_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(5, phy)) > > +#define ICL_PORT_TX_DW5_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(5, phy)) > > +#define ICL_PORT_TX_DW5_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(5, 0, phy)) > > #define TX_TRAINING_EN (1 << 31) > > #define TAP2_DISABLE (1 << 30) > > #define TAP3_DISABLE (1 << 29) > > @@ -1988,10 +1988,10 @@ enum i915_power_well_id { > > > > #define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(7, (port))) > > #define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(7, (port))) > > -#define ICL_PORT_TX_DW7_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(7, port)) > > -#define ICL_PORT_TX_DW7_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(7, port)) > > -#define ICL_PORT_TX_DW7_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, port)) > > -#define ICL_PORT_TX_DW7_LN(ln, port) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, port)) > > +#define ICL_PORT_TX_DW7_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(7, phy)) > > +#define ICL_PORT_TX_DW7_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(7, phy)) > > +#define ICL_PORT_TX_DW7_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, phy)) > > +#define ICL_PORT_TX_DW7_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, phy)) > > #define N_SCALAR(x) ((x) << 24) > > #define N_SCALAR_MASK (0x7F << 24) > > -- > Jani Nikula, Intel Open Source Graphics Center -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v6 3/5] drm/i915/gen11: Convert combo PHY logic to use new 'enum phy' namespace 2019-09-04 14:57 ` Matt Roper @ 2019-09-04 16:47 ` Jani Nikula 0 siblings, 0 replies; 13+ messages in thread From: Jani Nikula @ 2019-09-04 16:47 UTC (permalink / raw) To: Matt Roper; +Cc: intel-gfx On Wed, 04 Sep 2019, Matt Roper <matthew.d.roper@intel.com> wrote: > On Wed, Sep 04, 2019 at 04:42:49PM +0300, Jani Nikula wrote: >> On Tue, 09 Jul 2019, Matt Roper <matthew.d.roper@intel.com> wrote: >> > Convert the code that operates directly on gen11 combo PHY's to use the >> > new namespace. Combo PHY registers are those named "ICL_PORT_*" plus >> > ICL_DPHY_CHKN. >> > >> > Note that a lot of the PHY programming happens in the MIPI DSI code. >> > For clarity I've added a for_each_dsi_phy() to loop over the phys used >> > by DSI. Since DSI always uses A & B on gen11, port=phy in all cases so >> > it doesn't actually matter which form we use in the DSI code. I've used >> > the phy iterator in code that's explicitly working with the combo PHY, >> > but left the rest of the DSI code using the port iterator and namespace >> > to minimize patch deltas. We can switch the rest of the DSI code over >> > to use phy terminology later if this winds up being too confusing. >> >> One itsy-bitsy detail, where does this initialize intel_dsi->phys? >> Looking at the code, I'm thinking nowhere. > > At the moment we're relying on the fact that port==phy always for DSI on > the platforms this code applies to. intel_dsi->ports is initialized > > if (dev_priv->vbt.dsi.config->dual_link) > intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B); > else > intel_dsi->ports = BIT(port); > > and that's unioned with intel_dsi->phys > > /* bit mask of ports (vlv dsi) or phys (icl dsi) being driven */ > union { > u16 ports; /* VLV DSI */ > u16 phys; /* ICL DSI */ > }; > > so I think the initialization should be the same as it was before this patch. Right, the union is what I missed completely. I was looking for ->phys initialization but couldn't find it. Sorry for the noise! > As I mentioned above, this patch only changes the instances of 'enum port' to > 'enum phy' where they were specifically touching the combo PHY registers, and > left a bunch of the other code using 'enum port' to minimize the initial code > diffs. It's probably time now to follow up with another patch that converts > the rest of the file to phy usage to avoid confusion; I'll write a patch to do > that later today or tomorrow. Do you propose to index the rest of the relevant registers with phy too? (I know there's no effective change, just the name.) Should we change dsi_port_to_transcoder() to dsi_phy_to_transcoder()? In any case I agree some de-confusing would be in order. >> We have an ICL DSI machine in CI, which reports all green on this >> patch... but most likely the display is all black instead. DSI being >> DSI, it is entirely possible we have no way of knowing without having a >> camera capture the display. > > Hmm. All green all the time or only on specific tests/operations? I assume > this is https://intel-gfx-ci.01.org/hardware/fi-icl-dsi/ ? Strangely I don't > see an i915_display_info for that machine, but the current CI results seem to > be mostly passing. Is there a specific failing test I should look at? This was all based on me failing to find the ->phys initialization; I think it's conceivable we wouldn't have received any driver detectable errors even if ->phys were zero. Just a black screen. But again, sorry for the noise! BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v6 4/5] drm/i915: Transition port type checks to phy checks 2019-07-09 18:39 [PATCH v6 0/5] EHL port programming Matt Roper ` (2 preceding siblings ...) 2019-07-09 18:39 ` [PATCH v6 3/5] drm/i915/gen11: Convert combo PHY logic to use new 'enum phy' namespace Matt Roper @ 2019-07-09 18:39 ` Matt Roper 2019-07-09 18:39 ` [PATCH v6 5/5] drm/i915/ehl: Enable DDI-D Matt Roper ` (3 subsequent siblings) 7 siblings, 0 replies; 13+ messages in thread From: Matt Roper @ 2019-07-09 18:39 UTC (permalink / raw) To: intel-gfx; +Cc: Lucas De Marchi Transition the remaining uses of intel_port_is_* over to the equivalent intel_phy_is_* functions and drop the port functions. v5: Fix a call in a debug function that's only called when CONFIG_DRM_I915_DEBUG_RUNTIME_PM is on. (CI) Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> --- drivers/gpu/drm/i915/display/intel_bios.c | 4 +- drivers/gpu/drm/i915/display/intel_ddi.c | 38 ++++++++++++------- drivers/gpu/drm/i915/display/intel_display.c | 38 +++++-------------- .../drm/i915/display/intel_display_power.c | 4 +- drivers/gpu/drm/i915/display/intel_dp.c | 15 +++++--- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 11 +++--- drivers/gpu/drm/i915/intel_drv.h | 2 - 7 files changed, 55 insertions(+), 57 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 0c9808132d67..4fdbb5c35d87 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -28,6 +28,7 @@ #include <drm/drm_dp_helper.h> #include <drm/i915_drm.h> +#include "display/intel_display.h" #include "display/intel_gmbus.h" #include "i915_drv.h" @@ -1733,12 +1734,13 @@ init_vbt_missing_defaults(struct drm_i915_private *dev_priv) for (port = PORT_A; port < I915_MAX_PORTS; port++) { struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port]; + enum phy phy = intel_port_to_phy(dev_priv, port); /* * VBT has the TypeC mode (native,TBT/USB) and we don't want * to detect it. */ - if (intel_port_is_tc(dev_priv, port)) + if (intel_phy_is_tc(dev_priv, phy)) continue; info->supports_dvi = (port != PORT_A && port != PORT_E); diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index d9ea58038642..8f760a3e30fa 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -868,11 +868,12 @@ icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port) { int n_entries, level, default_entry; + enum phy phy = intel_port_to_phy(dev_priv, port); level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; if (INTEL_GEN(dev_priv) >= 11) { - if (intel_port_is_combophy(dev_priv, port)) + if (intel_phy_is_combo(dev_priv, phy)) icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, 0, &n_entries); else @@ -1487,9 +1488,10 @@ static void icl_ddi_clock_get(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state; enum port port = encoder->port; + enum phy phy = intel_port_to_phy(dev_priv, port); int link_clock; - if (intel_port_is_combophy(dev_priv, port)) { + if (intel_phy_is_combo(dev_priv, phy)) { link_clock = cnl_calc_wrpll_link(dev_priv, pll_state); } else { enum intel_dpll_id pll_id = intel_get_shared_dpll_id(dev_priv, @@ -2086,6 +2088,7 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_digital_port *dig_port; + enum phy phy = intel_port_to_phy(dev_priv, encoder->port); /* * TODO: Add support for MST encoders. Atm, the following should never @@ -2103,7 +2106,7 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder, * ports. */ if (intel_crtc_has_dp_encoder(crtc_state) || - intel_port_is_tc(dev_priv, encoder->port)) + intel_phy_is_tc(dev_priv, phy)) intel_display_power_get(dev_priv, intel_ddi_main_link_aux_domain(dig_port)); @@ -2228,10 +2231,11 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder) struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); enum port port = encoder->port; + enum phy phy = intel_port_to_phy(dev_priv, port); int n_entries; if (INTEL_GEN(dev_priv) >= 11) { - if (intel_port_is_combophy(dev_priv, port)) + if (intel_phy_is_combo(dev_priv, phy)) icl_get_combo_buf_trans(dev_priv, encoder->type, intel_dp->link_rate, &n_entries); else @@ -2664,9 +2668,9 @@ static void icl_ddi_vswing_sequence(struct intel_encoder *encoder, enum intel_output_type type) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - enum port port = encoder->port; + enum phy phy = intel_port_to_phy(dev_priv, encoder->port); - if (intel_port_is_combophy(dev_priv, port)) + if (intel_phy_is_combo(dev_priv, phy)) icl_combo_phy_ddi_vswing_sequence(encoder, level, type); else icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level); @@ -2877,6 +2881,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum port port = encoder->port; + enum phy phy = intel_port_to_phy(dev_priv, port); u32 val; const struct intel_shared_dpll *pll = crtc_state->shared_dpll; @@ -2886,7 +2891,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder, mutex_lock(&dev_priv->dpll_lock); if (INTEL_GEN(dev_priv) >= 11) { - if (!intel_port_is_combophy(dev_priv, port)) + if (!intel_phy_is_combo(dev_priv, phy)) I915_WRITE(DDI_CLK_SEL(port), icl_pll_to_ddi_clk_sel(encoder, crtc_state)); } else if (IS_CANNONLAKE(dev_priv)) { @@ -2926,9 +2931,10 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum port port = encoder->port; + enum phy phy = intel_port_to_phy(dev_priv, port); if (INTEL_GEN(dev_priv) >= 11) { - if (!intel_port_is_combophy(dev_priv, port)) + if (!intel_phy_is_combo(dev_priv, phy)) I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); } else if (IS_CANNONLAKE(dev_priv)) { I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) | @@ -3135,7 +3141,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, intel_ddi_clk_select(encoder, crtc_state); - if (!intel_port_is_tc(dev_priv, port) || + if (!intel_phy_is_tc(dev_priv, phy) || dig_port->tc_mode != TC_PORT_TBT_ALT) intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain); @@ -3153,7 +3159,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, else intel_prepare_dp_ddi_buffers(encoder, crtc_state); - if (intel_port_is_combophy(dev_priv, port)) { + if (intel_phy_is_combo(dev_priv, phy)) { bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; @@ -3305,6 +3311,7 @@ static void intel_ddi_post_disable_dp(struct intel_encoder *encoder, struct intel_dp *intel_dp = &dig_port->dp; bool is_mst = intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST); + enum phy phy = intel_port_to_phy(dev_priv, encoder->port); if (!is_mst) { intel_ddi_disable_pipe_clock(old_crtc_state); @@ -3320,7 +3327,7 @@ static void intel_ddi_post_disable_dp(struct intel_encoder *encoder, intel_edp_panel_vdd_on(intel_dp); intel_edp_panel_off(intel_dp); - if (!intel_port_is_tc(dev_priv, encoder->port) || + if (!intel_phy_is_tc(dev_priv, phy) || dig_port->tc_mode != TC_PORT_TBT_ALT) intel_display_power_put_unchecked(dev_priv, dig_port->ddi_io_power_domain); @@ -3670,8 +3677,9 @@ intel_ddi_pre_pll_enable(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); - bool is_tc_port = intel_port_is_tc(dev_priv, encoder->port); enum port port = encoder->port; + enum phy phy = intel_port_to_phy(dev_priv, port); + bool is_tc_port = intel_phy_is_tc(dev_priv, phy); if (is_tc_port) intel_tc_port_get_link(dig_port, crtc_state->lane_count); @@ -3701,7 +3709,8 @@ intel_ddi_post_pll_disable(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); - bool is_tc_port = intel_port_is_tc(dev_priv, encoder->port); + enum phy phy = intel_port_to_phy(dev_priv, encoder->port); + bool is_tc_port = intel_phy_is_tc(dev_priv, phy); if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) intel_display_power_put_unchecked(dev_priv, @@ -4213,6 +4222,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) struct drm_encoder *encoder; bool init_hdmi, init_dp, init_lspcon = false; enum pipe pipe; + enum phy phy = intel_port_to_phy(dev_priv, port); init_hdmi = port_info->supports_dvi || port_info->supports_hdmi; init_dp = port_info->supports_dp; @@ -4276,7 +4286,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port); intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); - if (intel_port_is_tc(dev_priv, port)) { + if (intel_phy_is_tc(dev_priv, phy)) { bool is_legacy = !port_info->supports_typec_usb && !port_info->supports_tbt; diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 44c79f8bd028..c2ed4bd8d56b 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -6671,20 +6671,6 @@ static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state) I915_WRITE(BCLRPAT(crtc->pipe), 0); } -bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port) -{ - if (port == PORT_NONE) - return false; - - if (IS_ELKHARTLAKE(dev_priv)) - return port <= PORT_C; - - if (INTEL_GEN(dev_priv) >= 11) - return port <= PORT_B; - - return false; -} - bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) { if (phy == PHY_NONE) @@ -6699,14 +6685,6 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) return false; } -bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port) -{ - if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv)) - return port >= PORT_C && port <= PORT_F; - - return false; -} - bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy) { if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv)) @@ -6756,8 +6734,9 @@ enum intel_display_power_domain intel_aux_power_domain(struct intel_digital_port *dig_port) { struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); + enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); - if (intel_port_is_tc(dev_priv, dig_port->base.port) && + if (intel_phy_is_tc(dev_priv, phy) && dig_port->tc_mode == TC_PORT_TBT_ALT) { switch (dig_port->aux_ch) { case AUX_CH_C: @@ -10091,16 +10070,17 @@ static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port, struct intel_crtc_state *pipe_config) { + enum phy phy = intel_port_to_phy(dev_priv, port); enum icl_port_dpll_id port_dpll_id; enum intel_dpll_id id; u32 temp; - if (intel_port_is_combophy(dev_priv, port)) { + if (intel_phy_is_combo(dev_priv, phy)) { temp = I915_READ(ICL_DPCLKA_CFGCR0) & - DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); - id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port); + ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); + id = temp >> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); port_dpll_id = ICL_PORT_DPLL_DEFAULT; - } else if (intel_port_is_tc(dev_priv, port)) { + } else if (intel_phy_is_tc(dev_priv, phy)) { u32 clk_sel = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; if (clk_sel == DDI_CLK_SEL_MG) { @@ -16962,9 +16942,11 @@ intel_modeset_setup_hw_state(struct drm_device *dev, /* Sanitize the TypeC port mode upfront, encoders depend on this */ for_each_intel_encoder(dev, encoder) { + enum phy phy = intel_port_to_phy(dev_priv, encoder->port); + /* We need to sanitize only the MST primary port. */ if (encoder->type != INTEL_OUTPUT_DP_MST && - intel_port_is_tc(dev_priv, encoder->port)) + intel_phy_is_tc(dev_priv, phy)) intel_tc_port_sanitize(enc_to_dig_port(&encoder->base)); } diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index a24d1859b37b..7e22a2704843 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -489,7 +489,9 @@ static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv, aux_ch = icl_tc_phy_aux_ch(dev_priv, power_well); for_each_intel_encoder(&dev_priv->drm, encoder) { - if (!intel_port_is_tc(dev_priv, encoder->port)) + enum phy phy = intel_port_to_phy(dev_priv, encoder->port); + + if (!intel_phy_is_tc(dev_priv, phy)) continue; /* We'll check the MST primary port */ diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 0bdb7ecc5a81..a9db16de2999 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -297,9 +297,9 @@ static int icl_max_source_rate(struct intel_dp *intel_dp) { struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); - enum port port = dig_port->base.port; + enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); - if (intel_port_is_combophy(dev_priv, port) && + if (intel_phy_is_combo(dev_priv, phy) && !IS_ELKHARTLAKE(dev_priv) && !intel_dp_is_edp(intel_dp)) return 540000; @@ -1192,7 +1192,8 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp, struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); struct intel_uncore *uncore = &i915->uncore; - bool is_tc_port = intel_port_is_tc(i915, intel_dig_port->base.port); + enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port); + bool is_tc_port = intel_phy_is_tc(i915, phy); i915_reg_t ch_ctl, ch_data[5]; u32 aux_clock_divider; enum intel_display_power_domain aux_domain = @@ -5211,10 +5212,11 @@ static bool icl_digital_port_connected(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); + enum phy phy = intel_port_to_phy(dev_priv, encoder->port); - if (intel_port_is_combophy(dev_priv, encoder->port)) + if (intel_phy_is_combo(dev_priv, phy)) return icl_combo_port_connected(dev_priv, dig_port); - else if (intel_port_is_tc(dev_priv, encoder->port)) + else if (intel_phy_is_tc(dev_priv, phy)) return intel_tc_port_connected(dig_port); else MISSING_CASE(encoder->hpd_pin); @@ -7113,6 +7115,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, struct drm_device *dev = intel_encoder->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); enum port port = intel_encoder->port; + enum phy phy = intel_port_to_phy(dev_priv, port); int type; /* Initialize the work for modeset in case of link train failure */ @@ -7139,7 +7142,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, * Currently we don't support eDP on TypeC ports, although in * theory it could work on TypeC legacy ports. */ - WARN_ON(intel_port_is_tc(dev_priv, port)); + WARN_ON(intel_phy_is_tc(dev_priv, phy)); type = DRM_MODE_CONNECTOR_eDP; } else { type = DRM_MODE_CONNECTOR_DisplayPort; diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index 30d7500eb66c..fc6f3c52629a 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -2584,7 +2584,8 @@ static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state, struct skl_wrpll_params pll_params = { 0 }; bool ret; - if (intel_port_is_tc(dev_priv, encoder->port)) + if (intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, + encoder->port))) ret = icl_calc_tbt_pll(crtc_state, &pll_params); else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) || intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) @@ -3004,14 +3005,14 @@ static bool icl_get_dplls(struct intel_atomic_state *state, struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); - enum port port = encoder->port; + enum phy phy = intel_port_to_phy(dev_priv, encoder->port); - if (intel_port_is_combophy(dev_priv, port)) + if (intel_phy_is_combo(dev_priv, phy)) return icl_get_combo_phy_dpll(state, crtc, encoder); - else if (intel_port_is_tc(dev_priv, port)) + else if (intel_phy_is_tc(dev_priv, phy)) return icl_get_tc_phy_dplls(state, crtc, encoder); - MISSING_CASE(port); + MISSING_CASE(phy); return false; } diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 815c26c0b98c..770f9f6aad84 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1492,9 +1492,7 @@ void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv); void intel_encoder_destroy(struct drm_encoder *encoder); struct drm_display_mode * intel_encoder_current_mode(struct intel_encoder *encoder); -bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port); bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy); -bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port); bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy); enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port); -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v6 5/5] drm/i915/ehl: Enable DDI-D 2019-07-09 18:39 [PATCH v6 0/5] EHL port programming Matt Roper ` (3 preceding siblings ...) 2019-07-09 18:39 ` [PATCH v6 4/5] drm/i915: Transition port type checks to phy checks Matt Roper @ 2019-07-09 18:39 ` Matt Roper 2019-07-09 18:49 ` ✗ Fi.CI.CHECKPATCH: warning for EHL port programming (rev7) Patchwork ` (2 subsequent siblings) 7 siblings, 0 replies; 13+ messages in thread From: Matt Roper @ 2019-07-09 18:39 UTC (permalink / raw) To: intel-gfx EHL has four DDI's (DDI-A and DDI-D share combo PHY A). Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index c2ed4bd8d56b..0286b97caa22 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -15308,6 +15308,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) intel_ddi_init(dev_priv, PORT_A); intel_ddi_init(dev_priv, PORT_B); intel_ddi_init(dev_priv, PORT_C); + intel_ddi_init(dev_priv, PORT_D); icl_dsi_init(dev_priv); } else if (INTEL_GEN(dev_priv) >= 11) { intel_ddi_init(dev_priv, PORT_A); -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 13+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for EHL port programming (rev7) 2019-07-09 18:39 [PATCH v6 0/5] EHL port programming Matt Roper ` (4 preceding siblings ...) 2019-07-09 18:39 ` [PATCH v6 5/5] drm/i915/ehl: Enable DDI-D Matt Roper @ 2019-07-09 18:49 ` Patchwork 2019-07-09 19:45 ` ✓ Fi.CI.BAT: success " Patchwork 2019-07-10 11:29 ` ✓ Fi.CI.IGT: " Patchwork 7 siblings, 0 replies; 13+ messages in thread From: Patchwork @ 2019-07-09 18:49 UTC (permalink / raw) To: Matt Roper; +Cc: intel-gfx == Series Details == Series: EHL port programming (rev7) URL : https://patchwork.freedesktop.org/series/62492/ State : warning == Summary == $ dim checkpatch origin/drm-tip 0cd776d3f169 drm/i915/gen11: Start distinguishing 'phy' from 'port' 97ceed65bf2b drm/i915/gen11: Program ICL_DPCLKA_CFGCR0 according to PHY -:265: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'tc_port' - possible side-effects? #265: FILE: drivers/gpu/drm/i915/i915_reg.h:9709: +#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \ + 21 : (tc_port) + 12)) -:268: WARNING:LONG_LINE: line over 100 characters #268: FILE: drivers/gpu/drm/i915/i915_reg.h:9712: +#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) -:269: WARNING:LONG_LINE: line over 100 characters #269: FILE: drivers/gpu/drm/i915/i915_reg.h:9713: +#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) total: 0 errors, 2 warnings, 1 checks, 212 lines checked 2550905e56cc drm/i915/gen11: Convert combo PHY logic to use new 'enum phy' namespace -:352: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__phy' - possible side-effects? #352: FILE: drivers/gpu/drm/i915/display/intel_combo_phy.c:9: +#define for_each_combo_phy(__dev_priv, __phy) \ + for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \ + for_each_if(intel_phy_is_combo(__dev_priv, __phy)) -:359: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__phy' - possible side-effects? #359: FILE: drivers/gpu/drm/i915/display/intel_combo_phy.c:13: +#define for_each_combo_phy_reverse(__dev_priv, __phy) \ + for ((__phy) = I915_MAX_PHYS; (__phy)-- > PHY_A;) \ + for_each_if(intel_phy_is_combo(__dev_priv, __phy)) -:835: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__phy' - possible side-effects? #835: FILE: drivers/gpu/drm/i915/display/intel_display.h:271: +#define for_each_phy_masked(__phy, __phys_mask) \ + for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \ + for_each_if((__phys_mask) & BIT(__phy)) -:1015: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #1015: FILE: drivers/gpu/drm/i915/i915_reg.h:1880: +#define CNL_PORT_PCS_DW1_LN0(phy) _MMIO(_PICK(phy, \ _CNL_PORT_PCS_DW1_LN0_AE, \ _CNL_PORT_PCS_DW1_LN0_B, \ _CNL_PORT_PCS_DW1_LN0_C, \ total: 1 errors, 0 warnings, 3 checks, 1001 lines checked 2d193fd97d83 drm/i915: Transition port type checks to phy checks a188f8f668e0 drm/i915/ehl: Enable DDI-D _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* ✓ Fi.CI.BAT: success for EHL port programming (rev7) 2019-07-09 18:39 [PATCH v6 0/5] EHL port programming Matt Roper ` (5 preceding siblings ...) 2019-07-09 18:49 ` ✗ Fi.CI.CHECKPATCH: warning for EHL port programming (rev7) Patchwork @ 2019-07-09 19:45 ` Patchwork 2019-07-10 11:29 ` ✓ Fi.CI.IGT: " Patchwork 7 siblings, 0 replies; 13+ messages in thread From: Patchwork @ 2019-07-09 19:45 UTC (permalink / raw) To: Matt Roper; +Cc: intel-gfx == Series Details == Series: EHL port programming (rev7) URL : https://patchwork.freedesktop.org/series/62492/ State : success == Summary == CI Bug Log - changes from CI_DRM_6444 -> Patchwork_13589 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/ Known issues ------------ Here are the changes found in Patchwork_13589 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_exec_create@basic: - fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/fi-icl-u3/igt@gem_exec_create@basic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/fi-icl-u3/igt@gem_exec_create@basic.html #### Possible fixes #### * {igt@gem_ctx_switch@legacy-render}: - fi-icl-guc: [INCOMPLETE][3] ([fdo#107713]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/fi-icl-guc/igt@gem_ctx_switch@legacy-render.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/fi-icl-guc/igt@gem_ctx_switch@legacy-render.html * igt@gem_mmap_gtt@basic-read-no-prefault: - fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/fi-icl-u3/igt@gem_mmap_gtt@basic-read-no-prefault.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/fi-icl-u3/igt@gem_mmap_gtt@basic-read-no-prefault.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045 [fdo#111046 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111046 [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 Participating hosts (53 -> 45) ------------------------------ Missing (8): fi-kbl-soraka fi-byt-j1900 fi-byt-squawks fi-bsw-cyan fi-pnv-d510 fi-icl-y fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_6444 -> Patchwork_13589 CI_DRM_6444: 6e842ef98f5278c942ddd9bbe83b19697deef7b0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5092: 2a66ae6626d5583240509f84117d1345a799b75a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13589: a188f8f668e0e487c1371e5fdcf143811554a74a @ git://anongit.freedesktop.org/gfx-ci/linux == Kernel 32bit build == Warning: Kernel 32bit buildtest failed: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/build_32bit.log CALL scripts/checksyscalls.sh CALL scripts/atomic/check-atomics.sh CHK include/generated/compile.h Kernel: arch/x86/boot/bzImage is ready (#1) Building modules, stage 2. MODPOST 112 modules ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! scripts/Makefile.modpost:91: recipe for target '__modpost' failed make[1]: *** [__modpost] Error 1 Makefile:1287: recipe for target 'modules' failed make: *** [modules] Error 2 == Linux commits == a188f8f668e0 drm/i915/ehl: Enable DDI-D 2d193fd97d83 drm/i915: Transition port type checks to phy checks 2550905e56cc drm/i915/gen11: Convert combo PHY logic to use new 'enum phy' namespace 97ceed65bf2b drm/i915/gen11: Program ICL_DPCLKA_CFGCR0 according to PHY 0cd776d3f169 drm/i915/gen11: Start distinguishing 'phy' from 'port' == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/ _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* ✓ Fi.CI.IGT: success for EHL port programming (rev7) 2019-07-09 18:39 [PATCH v6 0/5] EHL port programming Matt Roper ` (6 preceding siblings ...) 2019-07-09 19:45 ` ✓ Fi.CI.BAT: success " Patchwork @ 2019-07-10 11:29 ` Patchwork 2019-07-11 1:32 ` Matt Roper 7 siblings, 1 reply; 13+ messages in thread From: Patchwork @ 2019-07-10 11:29 UTC (permalink / raw) To: Matt Roper; +Cc: intel-gfx == Series Details == Series: EHL port programming (rev7) URL : https://patchwork.freedesktop.org/series/62492/ State : success == Summary == CI Bug Log - changes from CI_DRM_6444_full -> Patchwork_13589_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_13589_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_exec_parallel@bcs0: - shard-hsw: [PASS][1] -> [INCOMPLETE][2] ([fdo#103540]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-hsw5/igt@gem_exec_parallel@bcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-hsw5/igt@gem_exec_parallel@bcs0.html * igt@kms_color@pipe-c-ctm-green-to-red: - shard-skl: [PASS][3] -> [FAIL][4] ([fdo#107201]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-skl10/igt@kms_color@pipe-c-ctm-green-to-red.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-skl6/igt@kms_color@pipe-c-ctm-green-to-red.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [PASS][5] -> [FAIL][6] ([fdo#105363]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-skl5/igt@kms_flip@flip-vs-expired-vblank.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-skl3/igt@kms_flip@flip-vs-expired-vblank.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite: - shard-iclb: [PASS][7] -> [FAIL][8] ([fdo#103167]) +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite.html * igt@kms_pipe_crc_basic@hang-read-crc-pipe-a: - shard-snb: [PASS][9] -> [SKIP][10] ([fdo#109271]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-snb5/igt@kms_pipe_crc_basic@hang-read-crc-pipe-a.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-snb5/igt@kms_pipe_crc_basic@hang-read-crc-pipe-a.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([fdo#108566]) +5 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-apl8/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-apl5/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt@kms_psr@psr2_dpms: - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#109441]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-iclb2/igt@kms_psr@psr2_dpms.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-iclb3/igt@kms_psr@psr2_dpms.html * igt@kms_rotation_crc@multiplane-rotation-cropping-top: - shard-kbl: [PASS][15] -> [FAIL][16] ([fdo#109016]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-kbl4/igt@kms_rotation_crc@multiplane-rotation-cropping-top.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-kbl3/igt@kms_rotation_crc@multiplane-rotation-cropping-top.html * igt@kms_vblank@pipe-a-wait-forked-hang: - shard-apl: [PASS][17] -> [INCOMPLETE][18] ([fdo#103927]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-apl6/igt@kms_vblank@pipe-a-wait-forked-hang.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-apl7/igt@kms_vblank@pipe-a-wait-forked-hang.html #### Possible fixes #### * igt@i915_suspend@sysfs-reader: - shard-apl: [DMESG-WARN][19] ([fdo#108566]) -> [PASS][20] +3 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-apl2/igt@i915_suspend@sysfs-reader.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-apl2/igt@i915_suspend@sysfs-reader.html * igt@kms_atomic_transition@1x-modeset-transitions-fencing: - shard-iclb: [INCOMPLETE][21] ([fdo#107713]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-iclb4/igt@kms_atomic_transition@1x-modeset-transitions-fencing.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-iclb2/igt@kms_atomic_transition@1x-modeset-transitions-fencing.html * igt@kms_color@pipe-b-ctm-red-to-blue: - shard-skl: [FAIL][23] ([fdo#107201]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-skl4/igt@kms_color@pipe-b-ctm-red-to-blue.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-skl6/igt@kms_color@pipe-b-ctm-red-to-blue.html * igt@kms_cursor_legacy@cursor-vs-flip-atomic: - shard-hsw: [FAIL][25] ([fdo#103355]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-hsw5/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-hsw5/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html * igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled: - shard-skl: [FAIL][27] ([fdo#103184] / [fdo#103232]) -> [PASS][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-skl9/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-skl1/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled.html * igt@kms_flip@modeset-vs-vblank-race: - shard-glk: [FAIL][29] ([fdo#103060]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-glk8/igt@kms_flip@modeset-vs-vblank-race.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-glk2/igt@kms_flip@modeset-vs-vblank-race.html * igt@kms_flip_tiling@flip-changes-tiling-yf: - shard-skl: [FAIL][31] ([fdo#108228] / [fdo#108303]) -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-skl9/igt@kms_flip_tiling@flip-changes-tiling-yf.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-skl1/igt@kms_flip_tiling@flip-changes-tiling-yf.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack: - shard-iclb: [FAIL][33] ([fdo#103167]) -> [PASS][34] +6 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack.html * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min: - shard-skl: [FAIL][35] ([fdo#108145]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html * igt@kms_psr@psr2_primary_page_flip: - shard-iclb: [SKIP][37] ([fdo#109441]) -> [PASS][38] +1 similar issue [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-iclb8/igt@kms_psr@psr2_primary_page_flip.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html * igt@kms_setmode@basic: - shard-apl: [FAIL][39] ([fdo#99912]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-apl8/igt@kms_setmode@basic.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-apl5/igt@kms_setmode@basic.html * igt@tools_test@tools_test: - shard-hsw: [SKIP][41] ([fdo#109271]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-hsw6/igt@tools_test@tools_test.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-hsw6/igt@tools_test@tools_test.html #### Warnings #### * igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack: - shard-skl: [FAIL][43] ([fdo#108040]) -> [FAIL][44] ([fdo#103167]) +1 similar issue [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-skl1/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-skl1/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html [fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060 [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184 [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232 [fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355 [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540 [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363 [fdo#107201]: https://bugs.freedesktop.org/show_bug.cgi?id=107201 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#108040]: https://bugs.freedesktop.org/show_bug.cgi?id=108040 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#108228]: https://bugs.freedesktop.org/show_bug.cgi?id=108228 [fdo#108303]: https://bugs.freedesktop.org/show_bug.cgi?id=108303 [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566 [fdo#109016]: https://bugs.freedesktop.org/show_bug.cgi?id=109016 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912 Participating hosts (10 -> 10) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_6444 -> Patchwork_13589 CI_DRM_6444: 6e842ef98f5278c942ddd9bbe83b19697deef7b0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5092: 2a66ae6626d5583240509f84117d1345a799b75a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13589: a188f8f668e0e487c1371e5fdcf143811554a74a @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/ _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: ✓ Fi.CI.IGT: success for EHL port programming (rev7) 2019-07-10 11:29 ` ✓ Fi.CI.IGT: " Patchwork @ 2019-07-11 1:32 ` Matt Roper 0 siblings, 0 replies; 13+ messages in thread From: Matt Roper @ 2019-07-11 1:32 UTC (permalink / raw) To: intel-gfx On Wed, Jul 10, 2019 at 11:29:40AM +0000, Patchwork wrote: > == Series Details == > > Series: EHL port programming (rev7) > URL : https://patchwork.freedesktop.org/series/62492/ > State : success > > == Summary == > > CI Bug Log - changes from CI_DRM_6444_full -> Patchwork_13589_full > ==================================================== > > Summary > ------- > > **SUCCESS** > > No regressions found. > Series pushed to dinq. Thanks Jose and Ville for the reviews. Matt > > > Known issues > ------------ > > Here are the changes found in Patchwork_13589_full that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt@gem_exec_parallel@bcs0: > - shard-hsw: [PASS][1] -> [INCOMPLETE][2] ([fdo#103540]) > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-hsw5/igt@gem_exec_parallel@bcs0.html > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-hsw5/igt@gem_exec_parallel@bcs0.html > > * igt@kms_color@pipe-c-ctm-green-to-red: > - shard-skl: [PASS][3] -> [FAIL][4] ([fdo#107201]) > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-skl10/igt@kms_color@pipe-c-ctm-green-to-red.html > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-skl6/igt@kms_color@pipe-c-ctm-green-to-red.html > > * igt@kms_flip@flip-vs-expired-vblank: > - shard-skl: [PASS][5] -> [FAIL][6] ([fdo#105363]) +1 similar issue > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-skl5/igt@kms_flip@flip-vs-expired-vblank.html > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-skl3/igt@kms_flip@flip-vs-expired-vblank.html > > * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite: > - shard-iclb: [PASS][7] -> [FAIL][8] ([fdo#103167]) +3 similar issues > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite.html > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite.html > > * igt@kms_pipe_crc_basic@hang-read-crc-pipe-a: > - shard-snb: [PASS][9] -> [SKIP][10] ([fdo#109271]) +1 similar issue > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-snb5/igt@kms_pipe_crc_basic@hang-read-crc-pipe-a.html > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-snb5/igt@kms_pipe_crc_basic@hang-read-crc-pipe-a.html > > * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: > - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([fdo#108566]) +5 similar issues > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-apl8/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-apl5/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html > > * igt@kms_psr@psr2_dpms: > - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#109441]) +1 similar issue > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-iclb2/igt@kms_psr@psr2_dpms.html > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-iclb3/igt@kms_psr@psr2_dpms.html > > * igt@kms_rotation_crc@multiplane-rotation-cropping-top: > - shard-kbl: [PASS][15] -> [FAIL][16] ([fdo#109016]) > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-kbl4/igt@kms_rotation_crc@multiplane-rotation-cropping-top.html > [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-kbl3/igt@kms_rotation_crc@multiplane-rotation-cropping-top.html > > * igt@kms_vblank@pipe-a-wait-forked-hang: > - shard-apl: [PASS][17] -> [INCOMPLETE][18] ([fdo#103927]) > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-apl6/igt@kms_vblank@pipe-a-wait-forked-hang.html > [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-apl7/igt@kms_vblank@pipe-a-wait-forked-hang.html > > > #### Possible fixes #### > > * igt@i915_suspend@sysfs-reader: > - shard-apl: [DMESG-WARN][19] ([fdo#108566]) -> [PASS][20] +3 similar issues > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-apl2/igt@i915_suspend@sysfs-reader.html > [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-apl2/igt@i915_suspend@sysfs-reader.html > > * igt@kms_atomic_transition@1x-modeset-transitions-fencing: > - shard-iclb: [INCOMPLETE][21] ([fdo#107713]) -> [PASS][22] > [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-iclb4/igt@kms_atomic_transition@1x-modeset-transitions-fencing.html > [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-iclb2/igt@kms_atomic_transition@1x-modeset-transitions-fencing.html > > * igt@kms_color@pipe-b-ctm-red-to-blue: > - shard-skl: [FAIL][23] ([fdo#107201]) -> [PASS][24] > [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-skl4/igt@kms_color@pipe-b-ctm-red-to-blue.html > [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-skl6/igt@kms_color@pipe-b-ctm-red-to-blue.html > > * igt@kms_cursor_legacy@cursor-vs-flip-atomic: > - shard-hsw: [FAIL][25] ([fdo#103355]) -> [PASS][26] > [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-hsw5/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html > [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-hsw5/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html > > * igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled: > - shard-skl: [FAIL][27] ([fdo#103184] / [fdo#103232]) -> [PASS][28] > [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-skl9/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled.html > [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-skl1/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled.html > > * igt@kms_flip@modeset-vs-vblank-race: > - shard-glk: [FAIL][29] ([fdo#103060]) -> [PASS][30] > [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-glk8/igt@kms_flip@modeset-vs-vblank-race.html > [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-glk2/igt@kms_flip@modeset-vs-vblank-race.html > > * igt@kms_flip_tiling@flip-changes-tiling-yf: > - shard-skl: [FAIL][31] ([fdo#108228] / [fdo#108303]) -> [PASS][32] > [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-skl9/igt@kms_flip_tiling@flip-changes-tiling-yf.html > [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-skl1/igt@kms_flip_tiling@flip-changes-tiling-yf.html > > * igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack: > - shard-iclb: [FAIL][33] ([fdo#103167]) -> [PASS][34] +6 similar issues > [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack.html > [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack.html > > * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min: > - shard-skl: [FAIL][35] ([fdo#108145]) -> [PASS][36] > [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html > [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html > > * igt@kms_psr@psr2_primary_page_flip: > - shard-iclb: [SKIP][37] ([fdo#109441]) -> [PASS][38] +1 similar issue > [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-iclb8/igt@kms_psr@psr2_primary_page_flip.html > [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html > > * igt@kms_setmode@basic: > - shard-apl: [FAIL][39] ([fdo#99912]) -> [PASS][40] > [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-apl8/igt@kms_setmode@basic.html > [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-apl5/igt@kms_setmode@basic.html > > * igt@tools_test@tools_test: > - shard-hsw: [SKIP][41] ([fdo#109271]) -> [PASS][42] > [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-hsw6/igt@tools_test@tools_test.html > [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-hsw6/igt@tools_test@tools_test.html > > > #### Warnings #### > > * igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack: > - shard-skl: [FAIL][43] ([fdo#108040]) -> [FAIL][44] ([fdo#103167]) +1 similar issue > [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6444/shard-skl1/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html > [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/shard-skl1/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html > > > [fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060 > [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 > [fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184 > [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232 > [fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355 > [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540 > [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 > [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363 > [fdo#107201]: https://bugs.freedesktop.org/show_bug.cgi?id=107201 > [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 > [fdo#108040]: https://bugs.freedesktop.org/show_bug.cgi?id=108040 > [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 > [fdo#108228]: https://bugs.freedesktop.org/show_bug.cgi?id=108228 > [fdo#108303]: https://bugs.freedesktop.org/show_bug.cgi?id=108303 > [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566 > [fdo#109016]: https://bugs.freedesktop.org/show_bug.cgi?id=109016 > [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 > [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 > [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912 > > > Participating hosts (10 -> 10) > ------------------------------ > > No changes in participating hosts > > > Build changes > ------------- > > * Linux: CI_DRM_6444 -> Patchwork_13589 > > CI_DRM_6444: 6e842ef98f5278c942ddd9bbe83b19697deef7b0 @ git://anongit.freedesktop.org/gfx-ci/linux > IGT_5092: 2a66ae6626d5583240509f84117d1345a799b75a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > Patchwork_13589: a188f8f668e0e487c1371e5fdcf143811554a74a @ git://anongit.freedesktop.org/gfx-ci/linux > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13589/ -- Matt Roper Graphics Software Engineer IoTG Platform Enabling & Development Intel Corporation (916) 356-2795 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2019-09-04 16:46 UTC | newest] Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-07-09 18:39 [PATCH v6 0/5] EHL port programming Matt Roper 2019-07-09 18:39 ` [PATCH v6 1/5] drm/i915/gen11: Start distinguishing 'phy' from 'port' Matt Roper 2019-07-09 18:39 ` [PATCH v6 2/5] drm/i915/gen11: Program ICL_DPCLKA_CFGCR0 according to PHY Matt Roper 2019-07-09 18:39 ` [PATCH v6 3/5] drm/i915/gen11: Convert combo PHY logic to use new 'enum phy' namespace Matt Roper 2019-09-04 13:42 ` Jani Nikula 2019-09-04 14:57 ` Matt Roper 2019-09-04 16:47 ` Jani Nikula 2019-07-09 18:39 ` [PATCH v6 4/5] drm/i915: Transition port type checks to phy checks Matt Roper 2019-07-09 18:39 ` [PATCH v6 5/5] drm/i915/ehl: Enable DDI-D Matt Roper 2019-07-09 18:49 ` ✗ Fi.CI.CHECKPATCH: warning for EHL port programming (rev7) Patchwork 2019-07-09 19:45 ` ✓ Fi.CI.BAT: success " Patchwork 2019-07-10 11:29 ` ✓ Fi.CI.IGT: " Patchwork 2019-07-11 1:32 ` Matt Roper
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