[PATCH v3 1/2] drm/i915/display/icl: Bump up the vdisplay to reflect higher transcoder vertical limits

[PATCH v3 1/2] drm/i915/display/icl: Bump up the vdisplay to reflect higher transcoder vertical limits

[Manasi Navare]

On ICL+, the vertical limits for the transcoders are increased to 8192 so bump up
limits in intel_mode_valid()

v3:
* Supported starting ICL (Ville)
* Use the higher limits from TRANS_VTOTAL register (Ville)
v2:
* Checkpatch warning (Manasi)

Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f07081815b80..9883f607bb88 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15764,8 +15764,13 @@ intel_mode_valid(struct drm_device *dev,
 			   DRM_MODE_FLAG_CLKDIV2))
 		return MODE_BAD;
 
-	if (INTEL_GEN(dev_priv) >= 9 ||
-	    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
+	if (INTEL_GEN(dev_priv) >= 11) {
+		hdisplay_max = 8192;
+		vdisplay_max = 8192;
+		htotal_max = 8192;
+		vtotal_max = 8192;
+	} else if (INTEL_GEN(dev_priv) >= 9 ||
+		   IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
 		hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
 		vdisplay_max = 4096;
 		htotal_max = 8192;
-- 
2.19.1

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[PATCH v3 2/2] drm/i915/display/icl: Bump up the plane/fb height

[Manasi Navare]

On ICL+, the max supported plane height is 4320, so bump it up
To support 4320, we need to increase the number of bits used to
read plane_height to 13 as opposed to older 12 bits.

v2:
* ICL plane height supported is 4320 (Ville)
* Add a new line between max width and max height (Jose)

Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 22 ++++++++++++++++++--
 1 file changed, 20 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 9883f607bb88..e4915d68147a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3343,6 +3343,16 @@ static int icl_max_plane_width(const struct drm_framebuffer *fb,
 	return 5120;
 }
 
+static int skl_max_plane_height(void)
+{
+	return 4096;
+}
+
+static int icl_max_plane_height(void)
+{
+	return 4320;
+}
+
 static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
 					   int main_x, int main_y, u32 main_offset)
 {
@@ -3391,7 +3401,7 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
 	int w = drm_rect_width(&plane_state->base.src) >> 16;
 	int h = drm_rect_height(&plane_state->base.src) >> 16;
 	int max_width;
-	int max_height = 4096;
+	int max_height;
 	u32 alignment, offset, aux_offset = plane_state->color_plane[1].offset;
 
 	if (INTEL_GEN(dev_priv) >= 11)
@@ -3401,6 +3411,11 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
 	else
 		max_width = skl_max_plane_width(fb, 0, rotation);
 
+	if (INTEL_GEN(dev_priv) >= 11)
+		max_height = icl_max_plane_height();
+	else
+		max_height = skl_max_plane_height();
+
 	if (w > max_width || h > max_height) {
 		DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
 			      w, h, max_width, max_height);
@@ -9865,7 +9880,10 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
 	offset = I915_READ(PLANE_OFFSET(pipe, plane_id));
 
 	val = I915_READ(PLANE_SIZE(pipe, plane_id));
-	fb->height = ((val >> 16) & 0xfff) + 1;
+	if (INTEL_GEN(dev_priv) >= 12)
+		fb->height = ((val >> 16) & 0x1fff) + 1;
+	else
+		fb->height = ((val >> 16) & 0xfff) + 1;
 	fb->width = ((val >> 0) & 0x1fff) + 1;
 
 	val = I915_READ(PLANE_STRIDE(pipe, plane_id));
-- 
2.19.1

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✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/2] drm/i915/display/icl: Bump up the vdisplay to reflect higher transcoder vertical limits

[Patchwork]

== Series Details ==

Series: series starting with [v3,1/2] drm/i915/display/icl: Bump up the vdisplay to reflect higher transcoder vertical limits
URL   : https://patchwork.freedesktop.org/series/63522/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
60f52512f495 drm/i915/display/icl: Bump up the vdisplay to reflect higher transcoder vertical limits
-:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#10: 
On ICL+, the vertical limits for the transcoders are increased to 8192 so bump up

total: 0 errors, 1 warnings, 0 checks, 15 lines checked
93a807e3e5c2 drm/i915/display/icl: Bump up the plane/fb height

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Re: [PATCH v3 2/2] drm/i915/display/icl: Bump up the plane/fb height

[Ville Syrjälä]

On Wed, Jul 10, 2019 at 02:39:51PM -0700, Manasi Navare wrote:
> On ICL+, the max supported plane height is 4320, so bump it up
> To support 4320, we need to increase the number of bits used to
> read plane_height to 13 as opposed to older 12 bits.
> 
> v2:
> * ICL plane height supported is 4320 (Ville)
> * Add a new line between max width and max height (Jose)
> 
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 22 ++++++++++++++++++--
>  1 file changed, 20 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 9883f607bb88..e4915d68147a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3343,6 +3343,16 @@ static int icl_max_plane_width(const struct drm_framebuffer *fb,
>  	return 5120;
>  }
>  
> +static int skl_max_plane_height(void)
> +{
> +	return 4096;
> +}
> +
> +static int icl_max_plane_height(void)
> +{
> +	return 4320;
> +}
> +
>  static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
>  					   int main_x, int main_y, u32 main_offset)
>  {
> @@ -3391,7 +3401,7 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
>  	int w = drm_rect_width(&plane_state->base.src) >> 16;
>  	int h = drm_rect_height(&plane_state->base.src) >> 16;
>  	int max_width;
> -	int max_height = 4096;
> +	int max_height;
>  	u32 alignment, offset, aux_offset = plane_state->color_plane[1].offset;
>  
>  	if (INTEL_GEN(dev_priv) >= 11)
> @@ -3401,6 +3411,11 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
>  	else
>  		max_width = skl_max_plane_width(fb, 0, rotation);
>  
> +	if (INTEL_GEN(dev_priv) >= 11)
> +		max_height = icl_max_plane_height();
> +	else
> +		max_height = skl_max_plane_height();
> +
>  	if (w > max_width || h > max_height) {
>  		DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
>  			      w, h, max_width, max_height);
> @@ -9865,7 +9880,10 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
>  	offset = I915_READ(PLANE_OFFSET(pipe, plane_id));
>  
>  	val = I915_READ(PLANE_SIZE(pipe, plane_id));
> -	fb->height = ((val >> 16) & 0xfff) + 1;
> +	if (INTEL_GEN(dev_priv) >= 12)
> +		fb->height = ((val >> 16) & 0x1fff) + 1;
> +	else
> +		fb->height = ((val >> 16) & 0xfff) + 1;
>  	fb->width = ((val >> 0) & 0x1fff) + 1;

The extra bits should be mbz I think, so no need for the 'if'.
Just use 0x1fff always, or even extend both masks to 0xffff.

Looks like i9xx_get_initial_plane_config() is also missing a bit or two,
which should be fixed with a separate patch.

>  
>  	val = I915_READ(PLANE_STRIDE(pipe, plane_id));
> -- 
> 2.19.1

-- 
Ville Syrjälä
Intel
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Re: [PATCH v3 1/2] drm/i915/display/icl: Bump up the vdisplay to reflect higher transcoder vertical limits

[Ville Syrjälä]

On Wed, Jul 10, 2019 at 02:39:50PM -0700, Manasi Navare wrote:
> On ICL+, the vertical limits for the transcoders are increased to 8192 so bump up
> limits in intel_mode_valid()
> 
> v3:
> * Supported starting ICL (Ville)
> * Use the higher limits from TRANS_VTOTAL register (Ville)
> v2:
> * Checkpatch warning (Manasi)
> 
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index f07081815b80..9883f607bb88 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -15764,8 +15764,13 @@ intel_mode_valid(struct drm_device *dev,
>  			   DRM_MODE_FLAG_CLKDIV2))
>  		return MODE_BAD;
>  
> -	if (INTEL_GEN(dev_priv) >= 9 ||
> -	    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
> +	if (INTEL_GEN(dev_priv) >= 11) {
> +		hdisplay_max = 8192;
> +		vdisplay_max = 8192;

The horiz limits should be 16k.

> +		htotal_max = 8192;
> +		vtotal_max = 8192;
> +	} else if (INTEL_GEN(dev_priv) >= 9 ||
> +		   IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
>  		hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
>  		vdisplay_max = 4096;
>  		htotal_max = 8192;
> -- 
> 2.19.1

-- 
Ville Syrjälä
Intel
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✓ Fi.CI.BAT: success for series starting with [v3,1/2] drm/i915/display/icl: Bump up the vdisplay to reflect higher transcoder vertical limits

[Patchwork]

== Series Details ==

Series: series starting with [v3,1/2] drm/i915/display/icl: Bump up the vdisplay to reflect higher transcoder vertical limits
URL   : https://patchwork.freedesktop.org/series/63522/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6453 -> Patchwork_13612
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/

Known issues
------------

  Here are the changes found in Patchwork_13612 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_close_race@basic-threads:
    - fi-cml-u2:          [PASS][1] -> [INCOMPLETE][2] ([fdo#110566])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/fi-cml-u2/igt@gem_close_race@basic-threads.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/fi-cml-u2/igt@gem_close_race@basic-threads.html

  * igt@gem_ctx_create@basic-files:
    - fi-icl-u2:          [PASS][3] -> [INCOMPLETE][4] ([fdo#107713] / [fdo#109100])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/fi-icl-u2/igt@gem_ctx_create@basic-files.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/fi-icl-u2/igt@gem_ctx_create@basic-files.html

  * igt@i915_pm_rpm@module-reload:
    - fi-skl-6770hq:      [PASS][5] -> [FAIL][6] ([fdo#108511])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html

  * igt@prime_busy@basic-before-default:
    - fi-icl-dsi:         [PASS][7] -> [INCOMPLETE][8] ([fdo#107713])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/fi-icl-dsi/igt@prime_busy@basic-before-default.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/fi-icl-dsi/igt@prime_busy@basic-before-default.html

  
#### Possible fixes ####

  * igt@i915_selftest@live_execlists:
    - fi-skl-gvtdvm:      [DMESG-FAIL][9] -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html

  * igt@kms_chamelium@hdmi-crc-fast:
    - {fi-icl-u4}:        [FAIL][11] ([fdo#111045] / [fdo#111046 ]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/fi-icl-u4/igt@kms_chamelium@hdmi-crc-fast.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/fi-icl-u4/igt@kms_chamelium@hdmi-crc-fast.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][13] ([fdo#109485]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
    - fi-kbl-7567u:       [FAIL][15] ([fdo#109485]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/fi-kbl-7567u/igt@kms_chamelium@hdmi-hpd-fast.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/fi-kbl-7567u/igt@kms_chamelium@hdmi-hpd-fast.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - fi-blb-e6850:       [INCOMPLETE][17] ([fdo#107718]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/fi-blb-e6850/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/fi-blb-e6850/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  * igt@prime_vgem@basic-fence-flip:
    - fi-ilk-650:         [DMESG-WARN][19] ([fdo#106387]) -> [PASS][20] +1 similar issue
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/fi-ilk-650/igt@prime_vgem@basic-fence-flip.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/fi-ilk-650/igt@prime_vgem@basic-fence-flip.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#106387]: https://bugs.freedesktop.org/show_bug.cgi?id=106387
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
  [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
  [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
  [fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111046 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111046 


Participating hosts (53 -> 46)
------------------------------

  Missing    (7): fi-kbl-soraka fi-byt-squawks fi-bsw-cyan fi-icl-u3 fi-icl-y fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_6453 -> Patchwork_13612

  CI_DRM_6453: ee7ea857b5d32c7b58b5994201e0e1e194266206 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5092: 2a66ae6626d5583240509f84117d1345a799b75a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13612: 93a807e3e5c276ffb89cdd446e93e52bb670b9af @ git://anongit.freedesktop.org/gfx-ci/linux


== Kernel 32bit build ==

Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/build_32bit.log

  CALL    scripts/checksyscalls.sh
  CALL    scripts/atomic/check-atomics.sh
  CHK     include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready  (#1)
  Building modules, stage 2.
  MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1287: recipe for target 'modules' failed
make: *** [modules] Error 2


== Linux commits ==

93a807e3e5c2 drm/i915/display/icl: Bump up the plane/fb height
60f52512f495 drm/i915/display/icl: Bump up the vdisplay to reflect higher transcoder vertical limits

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/
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Re: [PATCH v3 1/2] drm/i915/display/icl: Bump up the vdisplay to reflect higher transcoder vertical limits

[Manasi Navare]

On Thu, Jul 11, 2019 at 01:38:41PM +0300, Ville Syrjälä wrote:
> On Wed, Jul 10, 2019 at 02:39:50PM -0700, Manasi Navare wrote:
> > On ICL+, the vertical limits for the transcoders are increased to 8192 so bump up
> > limits in intel_mode_valid()
> > 
> > v3:
> > * Supported starting ICL (Ville)
> > * Use the higher limits from TRANS_VTOTAL register (Ville)
> > v2:
> > * Checkpatch warning (Manasi)
> > 
> > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c | 9 +++++++--
> >  1 file changed, 7 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index f07081815b80..9883f607bb88 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -15764,8 +15764,13 @@ intel_mode_valid(struct drm_device *dev,
> >  			   DRM_MODE_FLAG_CLKDIV2))
> >  		return MODE_BAD;
> >  
> > -	if (INTEL_GEN(dev_priv) >= 9 ||
> > -	    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
> > +	if (INTEL_GEN(dev_priv) >= 11) {
> > +		hdisplay_max = 8192;
> > +		vdisplay_max = 8192;
> 
> The horiz limits should be 16k.

Oh yes didnt look at the TRANS_HTOTAL so yes thats 14 bits so 16384, will make that change

Manasi

> 
> > +		htotal_max = 8192;
> > +		vtotal_max = 8192;
> > +	} else if (INTEL_GEN(dev_priv) >= 9 ||
> > +		   IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
> >  		hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
> >  		vdisplay_max = 4096;
> >  		htotal_max = 8192;
> > -- 
> > 2.19.1
> 
> -- 
> Ville Syrjälä
> Intel
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✓ Fi.CI.IGT: success for series starting with [v3,1/2] drm/i915/display/icl: Bump up the vdisplay to reflect higher transcoder vertical limits

[Patchwork]

== Series Details ==

Series: series starting with [v3,1/2] drm/i915/display/icl: Bump up the vdisplay to reflect higher transcoder vertical limits
URL   : https://patchwork.freedesktop.org/series/63522/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6453_full -> Patchwork_13612_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_13612_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_balancer@smoke:
    - shard-iclb:         [PASS][1] -> [SKIP][2] ([fdo#110854])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-iclb4/igt@gem_exec_balancer@smoke.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/shard-iclb7/igt@gem_exec_balancer@smoke.html

  * igt@gem_exec_nop@basic-series:
    - shard-iclb:         [PASS][3] -> [INCOMPLETE][4] ([fdo#107713] / [fdo#109100])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-iclb7/igt@gem_exec_nop@basic-series.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/shard-iclb7/igt@gem_exec_nop@basic-series.html

  * igt@gem_exec_suspend@basic-s3:
    - shard-skl:          [PASS][5] -> [INCOMPLETE][6] ([fdo#104108]) +1 similar issue
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-skl4/igt@gem_exec_suspend@basic-s3.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/shard-skl2/igt@gem_exec_suspend@basic-s3.html

  * igt@i915_suspend@fence-restore-tiled2untiled:
    - shard-apl:          [PASS][7] -> [DMESG-WARN][8] ([fdo#108566]) +5 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-apl2/igt@i915_suspend@fence-restore-tiled2untiled.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/shard-apl7/igt@i915_suspend@fence-restore-tiled2untiled.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-kbl:          [PASS][9] -> [INCOMPLETE][10] ([fdo#103665])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-kbl7/igt@kms_flip@flip-vs-suspend.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/shard-kbl7/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
    - shard-iclb:         [PASS][11] -> [FAIL][12] ([fdo#103167]) +4 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
    - shard-skl:          [PASS][13] -> [FAIL][14] ([fdo#108145])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [PASS][15] -> [FAIL][16] ([fdo#108145] / [fdo#110403]) +1 similar issue
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_psr@psr2_sprite_render:
    - shard-iclb:         [PASS][17] -> [SKIP][18] ([fdo#109441])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-iclb2/igt@kms_psr@psr2_sprite_render.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/shard-iclb6/igt@kms_psr@psr2_sprite_render.html

  
#### Possible fixes ####

  * igt@gem_softpin@noreloc-s3:
    - shard-skl:          [INCOMPLETE][19] ([fdo#104108] / [fdo#107773]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-skl9/igt@gem_softpin@noreloc-s3.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/shard-skl6/igt@gem_softpin@noreloc-s3.html

  * igt@kms_color@pipe-b-ctm-red-to-blue:
    - shard-skl:          [FAIL][21] ([fdo#107201]) -> [PASS][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-skl3/igt@kms_color@pipe-b-ctm-red-to-blue.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/shard-skl2/igt@kms_color@pipe-b-ctm-red-to-blue.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-kbl:          [DMESG-WARN][23] ([fdo#108566]) -> [PASS][24] +2 similar issues
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-kbl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/shard-kbl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
    - shard-glk:          [FAIL][25] ([fdo#104873]) -> [PASS][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-glk8/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/shard-glk4/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html

  * igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled:
    - shard-skl:          [FAIL][27] ([fdo#103184] / [fdo#103232]) -> [PASS][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-skl10/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/shard-skl7/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled.html

  * igt@kms_flip@modeset-vs-vblank-race:
    - shard-apl:          [FAIL][29] ([fdo#103060]) -> [PASS][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-apl6/igt@kms_flip@modeset-vs-vblank-race.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/shard-apl4/igt@kms_flip@modeset-vs-vblank-race.html

  * igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack:
    - shard-skl:          [FAIL][31] ([fdo#103167]) -> [PASS][32] +1 similar issue
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-skl7/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/shard-skl7/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff:
    - shard-iclb:         [FAIL][33] ([fdo#103167]) -> [PASS][34] +1 similar issue
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
    - shard-apl:          [DMESG-WARN][35] ([fdo#108566]) -> [PASS][36] +3 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-apl5/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/shard-apl5/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
    - shard-skl:          [FAIL][37] ([fdo#108145]) -> [PASS][38] +1 similar issue
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html

  * igt@kms_psr@psr2_no_drrs:
    - shard-iclb:         [SKIP][39] ([fdo#109441]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-iclb7/igt@kms_psr@psr2_no_drrs.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/shard-iclb2/igt@kms_psr@psr2_no_drrs.html

  * igt@kms_vblank@pipe-c-ts-continuation-suspend:
    - shard-skl:          [INCOMPLETE][41] ([fdo#104108]) -> [PASS][42] +1 similar issue
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-skl5/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/shard-skl9/igt@kms_vblank@pipe-c-ts-continuation-suspend.html

  * igt@perf@polling:
    - shard-skl:          [FAIL][43] ([fdo#110728]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-skl8/igt@perf@polling.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/shard-skl10/igt@perf@polling.html

  * igt@tools_test@tools_test:
    - shard-snb:          [SKIP][45] ([fdo#109271]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6453/shard-snb2/igt@tools_test@tools_test.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/shard-snb7/igt@tools_test@tools_test.html

  
  [fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#104873]: https://bugs.freedesktop.org/show_bug.cgi?id=104873
  [fdo#107201]: https://bugs.freedesktop.org/show_bug.cgi?id=107201
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
  [fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
  [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854


Participating hosts (10 -> 9)
------------------------------

  Missing    (1): pig-glk-j5005 


Build changes
-------------

  * Linux: CI_DRM_6453 -> Patchwork_13612

  CI_DRM_6453: ee7ea857b5d32c7b58b5994201e0e1e194266206 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5092: 2a66ae6626d5583240509f84117d1345a799b75a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13612: 93a807e3e5c276ffb89cdd446e93e52bb670b9af @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13612/
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Re: [PATCH v3 1/2] drm/i915/display/icl: Bump up the vdisplay to reflect higher transcoder vertical limits

[Manasi Navare]

On Thu, Jul 11, 2019 at 01:38:41PM +0300, Ville Syrjälä wrote:
> On Wed, Jul 10, 2019 at 02:39:50PM -0700, Manasi Navare wrote:
> > On ICL+, the vertical limits for the transcoders are increased to 8192 so bump up
> > limits in intel_mode_valid()
> > 
> > v3:
> > * Supported starting ICL (Ville)
> > * Use the higher limits from TRANS_VTOTAL register (Ville)
> > v2:
> > * Checkpatch warning (Manasi)
> > 
> > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c | 9 +++++++--
> >  1 file changed, 7 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index f07081815b80..9883f607bb88 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -15764,8 +15764,13 @@ intel_mode_valid(struct drm_device *dev,
> >  			   DRM_MODE_FLAG_CLKDIV2))
> >  		return MODE_BAD;
> >  
> > -	if (INTEL_GEN(dev_priv) >= 9 ||
> > -	    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
> > +	if (INTEL_GEN(dev_priv) >= 11) {
> > +		hdisplay_max = 8192;
> > +		vdisplay_max = 8192;
> 
> The horiz limits should be 16k.

So the TRANS_HTOTAL has had 14 bits so allowed 16K even for Gen9+, should
this be changed for all?

Manasi

> 
> > +		htotal_max = 8192;
> > +		vtotal_max = 8192;
> > +	} else if (INTEL_GEN(dev_priv) >= 9 ||
> > +		   IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
> >  		hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
> >  		vdisplay_max = 4096;
> >  		htotal_max = 8192;
> > -- 
> > 2.19.1
> 
> -- 
> Ville Syrjälä
> Intel
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Re: [PATCH v3 1/2] drm/i915/display/icl: Bump up the vdisplay to reflect higher transcoder vertical limits

[Ville Syrjälä]

On Thu, Jul 11, 2019 at 04:15:41PM -0700, Manasi Navare wrote:
> On Thu, Jul 11, 2019 at 01:38:41PM +0300, Ville Syrjälä wrote:
> > On Wed, Jul 10, 2019 at 02:39:50PM -0700, Manasi Navare wrote:
> > > On ICL+, the vertical limits for the transcoders are increased to 8192 so bump up
> > > limits in intel_mode_valid()
> > > 
> > > v3:
> > > * Supported starting ICL (Ville)
> > > * Use the higher limits from TRANS_VTOTAL register (Ville)
> > > v2:
> > > * Checkpatch warning (Manasi)
> > > 
> > > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_display.c | 9 +++++++--
> > >  1 file changed, 7 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > index f07081815b80..9883f607bb88 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -15764,8 +15764,13 @@ intel_mode_valid(struct drm_device *dev,
> > >  			   DRM_MODE_FLAG_CLKDIV2))
> > >  		return MODE_BAD;
> > >  
> > > -	if (INTEL_GEN(dev_priv) >= 9 ||
> > > -	    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
> > > +	if (INTEL_GEN(dev_priv) >= 11) {
> > > +		hdisplay_max = 8192;
> > > +		vdisplay_max = 8192;
> > 
> > The horiz limits should be 16k.
> 
> So the TRANS_HTOTAL has had 14 bits so allowed 16K even for Gen9+, should
> this be changed for all?

I think you're looking at the wrong docs if you see 14 bits.

-- 
Ville Syrjälä
Intel
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Re: [PATCH v3 2/2] drm/i915/display/icl: Bump up the plane/fb height

[Manasi Navare]

On Thu, Jul 11, 2019 at 01:38:16PM +0300, Ville Syrjälä wrote:
> On Wed, Jul 10, 2019 at 02:39:51PM -0700, Manasi Navare wrote:
> > On ICL+, the max supported plane height is 4320, so bump it up
> > To support 4320, we need to increase the number of bits used to
> > read plane_height to 13 as opposed to older 12 bits.
> > 
> > v2:
> > * ICL plane height supported is 4320 (Ville)
> > * Add a new line between max width and max height (Jose)
> > 
> > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c | 22 ++++++++++++++++++--
> >  1 file changed, 20 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index 9883f607bb88..e4915d68147a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -3343,6 +3343,16 @@ static int icl_max_plane_width(const struct drm_framebuffer *fb,
> >  	return 5120;
> >  }
> >  
> > +static int skl_max_plane_height(void)
> > +{
> > +	return 4096;
> > +}
> > +
> > +static int icl_max_plane_height(void)
> > +{
> > +	return 4320;
> > +}
> > +
> >  static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
> >  					   int main_x, int main_y, u32 main_offset)
> >  {
> > @@ -3391,7 +3401,7 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
> >  	int w = drm_rect_width(&plane_state->base.src) >> 16;
> >  	int h = drm_rect_height(&plane_state->base.src) >> 16;
> >  	int max_width;
> > -	int max_height = 4096;
> > +	int max_height;
> >  	u32 alignment, offset, aux_offset = plane_state->color_plane[1].offset;
> >  
> >  	if (INTEL_GEN(dev_priv) >= 11)
> > @@ -3401,6 +3411,11 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
> >  	else
> >  		max_width = skl_max_plane_width(fb, 0, rotation);
> >  
> > +	if (INTEL_GEN(dev_priv) >= 11)
> > +		max_height = icl_max_plane_height();
> > +	else
> > +		max_height = skl_max_plane_height();
> > +
> >  	if (w > max_width || h > max_height) {
> >  		DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
> >  			      w, h, max_width, max_height);
> > @@ -9865,7 +9880,10 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
> >  	offset = I915_READ(PLANE_OFFSET(pipe, plane_id));
> >  
> >  	val = I915_READ(PLANE_SIZE(pipe, plane_id));
> > -	fb->height = ((val >> 16) & 0xfff) + 1;
> > +	if (INTEL_GEN(dev_priv) >= 12)
> > +		fb->height = ((val >> 16) & 0x1fff) + 1;
> > +	else
> > +		fb->height = ((val >> 16) & 0xfff) + 1;
> >  	fb->width = ((val >> 0) & 0x1fff) + 1;
> 
> The extra bits should be mbz I think, so no need for the 'if'.
> Just use 0x1fff always, or even extend both masks to 0xffff.

Yes I double checked, all the extra bits (31:28) for older platforms
are MBZ so yes I will just use 0xffff as the mask then

> 
> Looks like i9xx_get_initial_plane_config() is also missing a bit or two,
> which should be fixed with a separate patch.

But isnt that hook for older platforms?

Manasi

> 
> >  
> >  	val = I915_READ(PLANE_STRIDE(pipe, plane_id));
> > -- 
> > 2.19.1
> 
> -- 
> Ville Syrjälä
> Intel
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Re: [PATCH v3 2/2] drm/i915/display/icl: Bump up the plane/fb height

[Ville Syrjälä]

On Fri, Jul 12, 2019 at 01:15:53PM -0700, Manasi Navare wrote:
> On Thu, Jul 11, 2019 at 01:38:16PM +0300, Ville Syrjälä wrote:
> > On Wed, Jul 10, 2019 at 02:39:51PM -0700, Manasi Navare wrote:
> > > On ICL+, the max supported plane height is 4320, so bump it up
> > > To support 4320, we need to increase the number of bits used to
> > > read plane_height to 13 as opposed to older 12 bits.
> > > 
> > > v2:
> > > * ICL plane height supported is 4320 (Ville)
> > > * Add a new line between max width and max height (Jose)
> > > 
> > > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_display.c | 22 ++++++++++++++++++--
> > >  1 file changed, 20 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > index 9883f607bb88..e4915d68147a 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -3343,6 +3343,16 @@ static int icl_max_plane_width(const struct drm_framebuffer *fb,
> > >  	return 5120;
> > >  }
> > >  
> > > +static int skl_max_plane_height(void)
> > > +{
> > > +	return 4096;
> > > +}
> > > +
> > > +static int icl_max_plane_height(void)
> > > +{
> > > +	return 4320;
> > > +}
> > > +
> > >  static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
> > >  					   int main_x, int main_y, u32 main_offset)
> > >  {
> > > @@ -3391,7 +3401,7 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
> > >  	int w = drm_rect_width(&plane_state->base.src) >> 16;
> > >  	int h = drm_rect_height(&plane_state->base.src) >> 16;
> > >  	int max_width;
> > > -	int max_height = 4096;
> > > +	int max_height;
> > >  	u32 alignment, offset, aux_offset = plane_state->color_plane[1].offset;
> > >  
> > >  	if (INTEL_GEN(dev_priv) >= 11)
> > > @@ -3401,6 +3411,11 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
> > >  	else
> > >  		max_width = skl_max_plane_width(fb, 0, rotation);
> > >  
> > > +	if (INTEL_GEN(dev_priv) >= 11)
> > > +		max_height = icl_max_plane_height();
> > > +	else
> > > +		max_height = skl_max_plane_height();
> > > +
> > >  	if (w > max_width || h > max_height) {
> > >  		DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
> > >  			      w, h, max_width, max_height);
> > > @@ -9865,7 +9880,10 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
> > >  	offset = I915_READ(PLANE_OFFSET(pipe, plane_id));
> > >  
> > >  	val = I915_READ(PLANE_SIZE(pipe, plane_id));
> > > -	fb->height = ((val >> 16) & 0xfff) + 1;
> > > +	if (INTEL_GEN(dev_priv) >= 12)
> > > +		fb->height = ((val >> 16) & 0x1fff) + 1;
> > > +	else
> > > +		fb->height = ((val >> 16) & 0xfff) + 1;
> > >  	fb->width = ((val >> 0) & 0x1fff) + 1;
> > 
> > The extra bits should be mbz I think, so no need for the 'if'.
> > Just use 0x1fff always, or even extend both masks to 0xffff.
> 
> Yes I double checked, all the extra bits (31:28) for older platforms
> are MBZ so yes I will just use 0xffff as the mask then
> 
> > 
> > Looks like i9xx_get_initial_plane_config() is also missing a bit or two,
> > which should be fixed with a separate patch.
> 
> But isnt that hook for older platforms?

Yes it is.

-- 
Ville Syrjälä
Intel
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