* [PATCH v2 0/4] Add system mmu support for Armada-806
@ 2019-07-11 15:02 ` Gregory CLEMENT
0 siblings, 0 replies; 29+ messages in thread
From: Gregory CLEMENT @ 2019-07-11 15:02 UTC (permalink / raw)
To: Robin Murphy, Joerg Roedel, linux-kernel, iommu
Cc: Rob Herring, devicetree, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Gregory CLEMENT, Thomas Petazzoni,
linux-arm-kernel, Catalin Marinas, Will Deacon, Antoine Tenart,
Miquèl Raynal, Maxime Chevallier, Nadav Haklai
Hello,
last year a first version of this series was submitted to add support
for IOMMU for AP806, including workaround for accessing ARM SMMU 64bit
registers[1].
For the record, AP-806 can't access SMMU registers with 64bit width,
this patches split the readq/writeq for 32bit access, due to erratanum
#582743.
Based on the feedback from Robin Murphy, I also add code ensuring that
we won't try to use AArch64 format with 32 bits acces.
It was also discussed to not use compatible but propertu to support
this workaround. I agree to make this change if needed, but for now I
would like to have a feedback on the current code to know if it is
acceptable if there is still potential issue.
The series was tested on a vanilla v5.1 kernel, and without the
series, an USB stick was not detected under QEMU whereas with this
series it worked as expected.
Greogry
[1]: https://lkml.org/lkml/2018/10/15/373
Gregory CLEMENT (1):
arm64: dts: marvell: armada-ap806: add smmu support
Hanna Hawa (3):
iommu/arm-smmu: Introduce wrapper for writeq/readq
iommu/arm-smmu: Workaround for Marvell Armada-AP806 SoC erratum
#582743
dt-bindings: iommu/arm,smmu: add compatible string for Marvell
Documentation/arm64/silicon-errata.txt | 2 +
.../devicetree/bindings/iommu/arm,smmu.txt | 1 +
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 17 +++++
drivers/iommu/arm-smmu.c | 74 ++++++++++++++++---
4 files changed, 83 insertions(+), 11 deletions(-)
--
2.20.1
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v2 0/4] Add system mmu support for Armada-806
@ 2019-07-11 15:02 ` Gregory CLEMENT
0 siblings, 0 replies; 29+ messages in thread
From: Gregory CLEMENT @ 2019-07-11 15:02 UTC (permalink / raw)
To: Robin Murphy, Joerg Roedel, linux-kernel, iommu
Cc: devicetree, Jason Cooper, Andrew Lunn, Antoine Tenart,
Catalin Marinas, Gregory CLEMENT, Will Deacon, Maxime Chevallier,
Nadav Haklai, Rob Herring, Thomas Petazzoni, Miquèl Raynal,
linux-arm-kernel, Sebastian Hesselbarth
Hello,
last year a first version of this series was submitted to add support
for IOMMU for AP806, including workaround for accessing ARM SMMU 64bit
registers[1].
For the record, AP-806 can't access SMMU registers with 64bit width,
this patches split the readq/writeq for 32bit access, due to erratanum
#582743.
Based on the feedback from Robin Murphy, I also add code ensuring that
we won't try to use AArch64 format with 32 bits acces.
It was also discussed to not use compatible but propertu to support
this workaround. I agree to make this change if needed, but for now I
would like to have a feedback on the current code to know if it is
acceptable if there is still potential issue.
The series was tested on a vanilla v5.1 kernel, and without the
series, an USB stick was not detected under QEMU whereas with this
series it worked as expected.
Greogry
[1]: https://lkml.org/lkml/2018/10/15/373
Gregory CLEMENT (1):
arm64: dts: marvell: armada-ap806: add smmu support
Hanna Hawa (3):
iommu/arm-smmu: Introduce wrapper for writeq/readq
iommu/arm-smmu: Workaround for Marvell Armada-AP806 SoC erratum
#582743
dt-bindings: iommu/arm,smmu: add compatible string for Marvell
Documentation/arm64/silicon-errata.txt | 2 +
.../devicetree/bindings/iommu/arm,smmu.txt | 1 +
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 17 +++++
drivers/iommu/arm-smmu.c | 74 ++++++++++++++++---
4 files changed, 83 insertions(+), 11 deletions(-)
--
2.20.1
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v2 0/4] Add system mmu support for Armada-806
@ 2019-07-11 15:02 ` Gregory CLEMENT
0 siblings, 0 replies; 29+ messages in thread
From: Gregory CLEMENT @ 2019-07-11 15:02 UTC (permalink / raw)
To: Robin Murphy, Joerg Roedel, linux-kernel, iommu
Cc: devicetree, Jason Cooper, Andrew Lunn, Antoine Tenart,
Catalin Marinas, Gregory CLEMENT, Will Deacon, Maxime Chevallier,
Nadav Haklai, Rob Herring, Thomas Petazzoni, Miquèl Raynal,
linux-arm-kernel, Sebastian Hesselbarth
Hello,
last year a first version of this series was submitted to add support
for IOMMU for AP806, including workaround for accessing ARM SMMU 64bit
registers[1].
For the record, AP-806 can't access SMMU registers with 64bit width,
this patches split the readq/writeq for 32bit access, due to erratanum
#582743.
Based on the feedback from Robin Murphy, I also add code ensuring that
we won't try to use AArch64 format with 32 bits acces.
It was also discussed to not use compatible but propertu to support
this workaround. I agree to make this change if needed, but for now I
would like to have a feedback on the current code to know if it is
acceptable if there is still potential issue.
The series was tested on a vanilla v5.1 kernel, and without the
series, an USB stick was not detected under QEMU whereas with this
series it worked as expected.
Greogry
[1]: https://lkml.org/lkml/2018/10/15/373
Gregory CLEMENT (1):
arm64: dts: marvell: armada-ap806: add smmu support
Hanna Hawa (3):
iommu/arm-smmu: Introduce wrapper for writeq/readq
iommu/arm-smmu: Workaround for Marvell Armada-AP806 SoC erratum
#582743
dt-bindings: iommu/arm,smmu: add compatible string for Marvell
Documentation/arm64/silicon-errata.txt | 2 +
.../devicetree/bindings/iommu/arm,smmu.txt | 1 +
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 17 +++++
drivers/iommu/arm-smmu.c | 74 ++++++++++++++++---
4 files changed, 83 insertions(+), 11 deletions(-)
--
2.20.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v2 1/4] iommu/arm-smmu: Introduce wrapper for writeq/readq
2019-07-11 15:02 ` Gregory CLEMENT
(?)
@ 2019-07-11 15:02 ` Gregory CLEMENT
-1 siblings, 0 replies; 29+ messages in thread
From: Gregory CLEMENT @ 2019-07-11 15:02 UTC (permalink / raw)
To: Robin Murphy, Joerg Roedel, linux-kernel, iommu
Cc: Rob Herring, devicetree, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Gregory CLEMENT, Thomas Petazzoni,
linux-arm-kernel, Catalin Marinas, Will Deacon, Antoine Tenart,
Miquèl Raynal, Maxime Chevallier, Nadav Haklai, Hanna Hawa
From: Hanna Hawa <hannah@marvell.com>
This patch introduces the smmu_writeq_relaxed/smmu_readq_relaxed
helpers, as preparation to add specific Marvell work-around for
accessing 64 bits width registers of ARM SMMU.
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
drivers/iommu/arm-smmu.c | 36 +++++++++++++++++++++++++++---------
1 file changed, 27 insertions(+), 9 deletions(-)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 045d93884164..ac0784b5b675 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -91,9 +91,11 @@
* therefore this actually makes more sense than it might first appear.
*/
#ifdef CONFIG_64BIT
-#define smmu_write_atomic_lq writeq_relaxed
+#define smmu_write_atomic_lq(smmu, val, reg) \
+ smmu_writeq_relaxed(smmu, val, reg)
#else
-#define smmu_write_atomic_lq writel_relaxed
+#define smmu_write_atomic_lq(smmu, val, reg) \
+ writel_relaxed(val, reg)
#endif
/* Translation context bank */
@@ -295,6 +297,19 @@ static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom)
return container_of(dom, struct arm_smmu_domain, domain);
}
+static inline void smmu_writeq_relaxed(struct arm_smmu_device *smmu,
+ u64 val,
+ void __iomem *addr)
+{
+ writeq_relaxed(val, addr);
+}
+
+static inline u64 smmu_readq_relaxed(struct arm_smmu_device *smmu,
+ void __iomem *addr)
+{
+ return readq_relaxed(addr);
+}
+
static void parse_driver_options(struct arm_smmu_device *smmu)
{
int i = 0;
@@ -495,6 +510,7 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
size_t granule, bool leaf, void *cookie)
{
struct arm_smmu_domain *smmu_domain = cookie;
+ struct arm_smmu_device *smmu = smmu_domain->smmu;
struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
void __iomem *reg = ARM_SMMU_CB(smmu_domain->smmu, cfg->cbndx);
@@ -516,7 +532,7 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
iova >>= 12;
iova |= (u64)cfg->asid << 48;
do {
- writeq_relaxed(iova, reg);
+ smmu_writeq_relaxed(smmu, iova, reg);
iova += granule >> 12;
} while (size -= granule);
}
@@ -525,7 +541,7 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
ARM_SMMU_CB_S2_TLBIIPAS2;
iova >>= 12;
do {
- smmu_write_atomic_lq(iova, reg);
+ smmu_write_atomic_lq(smmu, iova, reg);
iova += granule >> 12;
} while (size -= granule);
}
@@ -584,7 +600,7 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
return IRQ_NONE;
fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
- iova = readq_relaxed(cb_base + ARM_SMMU_CB_FAR);
+ iova = smmu_readq_relaxed(smmu, cb_base + ARM_SMMU_CB_FAR);
dev_err_ratelimited(smmu->dev,
"Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cb=%d\n",
@@ -734,9 +750,11 @@ static void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx)
writel_relaxed(cb->ttbr[0], cb_base + ARM_SMMU_CB_TTBR0);
writel_relaxed(cb->ttbr[1], cb_base + ARM_SMMU_CB_TTBR1);
} else {
- writeq_relaxed(cb->ttbr[0], cb_base + ARM_SMMU_CB_TTBR0);
+ smmu_writeq_relaxed(smmu, cb->ttbr[0],
+ cb_base + ARM_SMMU_CB_TTBR0);
if (stage1)
- writeq_relaxed(cb->ttbr[1], cb_base + ARM_SMMU_CB_TTBR1);
+ smmu_writeq_relaxed(smmu, cb->ttbr[1],
+ cb_base + ARM_SMMU_CB_TTBR1);
}
/* MAIRs (stage-1 only) */
@@ -1367,7 +1385,7 @@ static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain,
/* ATS1 registers can only be written atomically */
va = iova & ~0xfffUL;
if (smmu->version == ARM_SMMU_V2)
- smmu_write_atomic_lq(va, cb_base + ARM_SMMU_CB_ATS1PR);
+ smmu_write_atomic_lq(smmu, va, cb_base + ARM_SMMU_CB_ATS1PR);
else /* Register is only 32-bit in v1 */
writel_relaxed(va, cb_base + ARM_SMMU_CB_ATS1PR);
@@ -1380,7 +1398,7 @@ static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain,
return ops->iova_to_phys(ops, iova);
}
- phys = readq_relaxed(cb_base + ARM_SMMU_CB_PAR);
+ phys = smmu_readq_relaxed(smmu, cb_base + ARM_SMMU_CB_PAR);
spin_unlock_irqrestore(&smmu_domain->cb_lock, flags);
if (phys & CB_PAR_F) {
dev_err(dev, "translation fault!\n");
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v2 1/4] iommu/arm-smmu: Introduce wrapper for writeq/readq
@ 2019-07-11 15:02 ` Gregory CLEMENT
0 siblings, 0 replies; 29+ messages in thread
From: Gregory CLEMENT @ 2019-07-11 15:02 UTC (permalink / raw)
To: Robin Murphy, Joerg Roedel, linux-kernel, iommu
Cc: devicetree, Jason Cooper, Andrew Lunn, Antoine Tenart,
Catalin Marinas, Gregory CLEMENT, Will Deacon, Maxime Chevallier,
Nadav Haklai, Rob Herring, Thomas Petazzoni, Miquèl Raynal,
Hanna Hawa, linux-arm-kernel, Sebastian Hesselbarth
From: Hanna Hawa <hannah@marvell.com>
This patch introduces the smmu_writeq_relaxed/smmu_readq_relaxed
helpers, as preparation to add specific Marvell work-around for
accessing 64 bits width registers of ARM SMMU.
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
drivers/iommu/arm-smmu.c | 36 +++++++++++++++++++++++++++---------
1 file changed, 27 insertions(+), 9 deletions(-)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 045d93884164..ac0784b5b675 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -91,9 +91,11 @@
* therefore this actually makes more sense than it might first appear.
*/
#ifdef CONFIG_64BIT
-#define smmu_write_atomic_lq writeq_relaxed
+#define smmu_write_atomic_lq(smmu, val, reg) \
+ smmu_writeq_relaxed(smmu, val, reg)
#else
-#define smmu_write_atomic_lq writel_relaxed
+#define smmu_write_atomic_lq(smmu, val, reg) \
+ writel_relaxed(val, reg)
#endif
/* Translation context bank */
@@ -295,6 +297,19 @@ static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom)
return container_of(dom, struct arm_smmu_domain, domain);
}
+static inline void smmu_writeq_relaxed(struct arm_smmu_device *smmu,
+ u64 val,
+ void __iomem *addr)
+{
+ writeq_relaxed(val, addr);
+}
+
+static inline u64 smmu_readq_relaxed(struct arm_smmu_device *smmu,
+ void __iomem *addr)
+{
+ return readq_relaxed(addr);
+}
+
static void parse_driver_options(struct arm_smmu_device *smmu)
{
int i = 0;
@@ -495,6 +510,7 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
size_t granule, bool leaf, void *cookie)
{
struct arm_smmu_domain *smmu_domain = cookie;
+ struct arm_smmu_device *smmu = smmu_domain->smmu;
struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
void __iomem *reg = ARM_SMMU_CB(smmu_domain->smmu, cfg->cbndx);
@@ -516,7 +532,7 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
iova >>= 12;
iova |= (u64)cfg->asid << 48;
do {
- writeq_relaxed(iova, reg);
+ smmu_writeq_relaxed(smmu, iova, reg);
iova += granule >> 12;
} while (size -= granule);
}
@@ -525,7 +541,7 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
ARM_SMMU_CB_S2_TLBIIPAS2;
iova >>= 12;
do {
- smmu_write_atomic_lq(iova, reg);
+ smmu_write_atomic_lq(smmu, iova, reg);
iova += granule >> 12;
} while (size -= granule);
}
@@ -584,7 +600,7 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
return IRQ_NONE;
fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
- iova = readq_relaxed(cb_base + ARM_SMMU_CB_FAR);
+ iova = smmu_readq_relaxed(smmu, cb_base + ARM_SMMU_CB_FAR);
dev_err_ratelimited(smmu->dev,
"Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cb=%d\n",
@@ -734,9 +750,11 @@ static void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx)
writel_relaxed(cb->ttbr[0], cb_base + ARM_SMMU_CB_TTBR0);
writel_relaxed(cb->ttbr[1], cb_base + ARM_SMMU_CB_TTBR1);
} else {
- writeq_relaxed(cb->ttbr[0], cb_base + ARM_SMMU_CB_TTBR0);
+ smmu_writeq_relaxed(smmu, cb->ttbr[0],
+ cb_base + ARM_SMMU_CB_TTBR0);
if (stage1)
- writeq_relaxed(cb->ttbr[1], cb_base + ARM_SMMU_CB_TTBR1);
+ smmu_writeq_relaxed(smmu, cb->ttbr[1],
+ cb_base + ARM_SMMU_CB_TTBR1);
}
/* MAIRs (stage-1 only) */
@@ -1367,7 +1385,7 @@ static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain,
/* ATS1 registers can only be written atomically */
va = iova & ~0xfffUL;
if (smmu->version == ARM_SMMU_V2)
- smmu_write_atomic_lq(va, cb_base + ARM_SMMU_CB_ATS1PR);
+ smmu_write_atomic_lq(smmu, va, cb_base + ARM_SMMU_CB_ATS1PR);
else /* Register is only 32-bit in v1 */
writel_relaxed(va, cb_base + ARM_SMMU_CB_ATS1PR);
@@ -1380,7 +1398,7 @@ static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain,
return ops->iova_to_phys(ops, iova);
}
- phys = readq_relaxed(cb_base + ARM_SMMU_CB_PAR);
+ phys = smmu_readq_relaxed(smmu, cb_base + ARM_SMMU_CB_PAR);
spin_unlock_irqrestore(&smmu_domain->cb_lock, flags);
if (phys & CB_PAR_F) {
dev_err(dev, "translation fault!\n");
--
2.20.1
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v2 1/4] iommu/arm-smmu: Introduce wrapper for writeq/readq
@ 2019-07-11 15:02 ` Gregory CLEMENT
0 siblings, 0 replies; 29+ messages in thread
From: Gregory CLEMENT @ 2019-07-11 15:02 UTC (permalink / raw)
To: Robin Murphy, Joerg Roedel, linux-kernel, iommu
Cc: devicetree, Jason Cooper, Andrew Lunn, Antoine Tenart,
Catalin Marinas, Gregory CLEMENT, Will Deacon, Maxime Chevallier,
Nadav Haklai, Rob Herring, Thomas Petazzoni, Miquèl Raynal,
Hanna Hawa, linux-arm-kernel, Sebastian Hesselbarth
From: Hanna Hawa <hannah@marvell.com>
This patch introduces the smmu_writeq_relaxed/smmu_readq_relaxed
helpers, as preparation to add specific Marvell work-around for
accessing 64 bits width registers of ARM SMMU.
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
drivers/iommu/arm-smmu.c | 36 +++++++++++++++++++++++++++---------
1 file changed, 27 insertions(+), 9 deletions(-)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 045d93884164..ac0784b5b675 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -91,9 +91,11 @@
* therefore this actually makes more sense than it might first appear.
*/
#ifdef CONFIG_64BIT
-#define smmu_write_atomic_lq writeq_relaxed
+#define smmu_write_atomic_lq(smmu, val, reg) \
+ smmu_writeq_relaxed(smmu, val, reg)
#else
-#define smmu_write_atomic_lq writel_relaxed
+#define smmu_write_atomic_lq(smmu, val, reg) \
+ writel_relaxed(val, reg)
#endif
/* Translation context bank */
@@ -295,6 +297,19 @@ static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom)
return container_of(dom, struct arm_smmu_domain, domain);
}
+static inline void smmu_writeq_relaxed(struct arm_smmu_device *smmu,
+ u64 val,
+ void __iomem *addr)
+{
+ writeq_relaxed(val, addr);
+}
+
+static inline u64 smmu_readq_relaxed(struct arm_smmu_device *smmu,
+ void __iomem *addr)
+{
+ return readq_relaxed(addr);
+}
+
static void parse_driver_options(struct arm_smmu_device *smmu)
{
int i = 0;
@@ -495,6 +510,7 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
size_t granule, bool leaf, void *cookie)
{
struct arm_smmu_domain *smmu_domain = cookie;
+ struct arm_smmu_device *smmu = smmu_domain->smmu;
struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
void __iomem *reg = ARM_SMMU_CB(smmu_domain->smmu, cfg->cbndx);
@@ -516,7 +532,7 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
iova >>= 12;
iova |= (u64)cfg->asid << 48;
do {
- writeq_relaxed(iova, reg);
+ smmu_writeq_relaxed(smmu, iova, reg);
iova += granule >> 12;
} while (size -= granule);
}
@@ -525,7 +541,7 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
ARM_SMMU_CB_S2_TLBIIPAS2;
iova >>= 12;
do {
- smmu_write_atomic_lq(iova, reg);
+ smmu_write_atomic_lq(smmu, iova, reg);
iova += granule >> 12;
} while (size -= granule);
}
@@ -584,7 +600,7 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
return IRQ_NONE;
fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
- iova = readq_relaxed(cb_base + ARM_SMMU_CB_FAR);
+ iova = smmu_readq_relaxed(smmu, cb_base + ARM_SMMU_CB_FAR);
dev_err_ratelimited(smmu->dev,
"Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cb=%d\n",
@@ -734,9 +750,11 @@ static void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx)
writel_relaxed(cb->ttbr[0], cb_base + ARM_SMMU_CB_TTBR0);
writel_relaxed(cb->ttbr[1], cb_base + ARM_SMMU_CB_TTBR1);
} else {
- writeq_relaxed(cb->ttbr[0], cb_base + ARM_SMMU_CB_TTBR0);
+ smmu_writeq_relaxed(smmu, cb->ttbr[0],
+ cb_base + ARM_SMMU_CB_TTBR0);
if (stage1)
- writeq_relaxed(cb->ttbr[1], cb_base + ARM_SMMU_CB_TTBR1);
+ smmu_writeq_relaxed(smmu, cb->ttbr[1],
+ cb_base + ARM_SMMU_CB_TTBR1);
}
/* MAIRs (stage-1 only) */
@@ -1367,7 +1385,7 @@ static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain,
/* ATS1 registers can only be written atomically */
va = iova & ~0xfffUL;
if (smmu->version == ARM_SMMU_V2)
- smmu_write_atomic_lq(va, cb_base + ARM_SMMU_CB_ATS1PR);
+ smmu_write_atomic_lq(smmu, va, cb_base + ARM_SMMU_CB_ATS1PR);
else /* Register is only 32-bit in v1 */
writel_relaxed(va, cb_base + ARM_SMMU_CB_ATS1PR);
@@ -1380,7 +1398,7 @@ static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain,
return ops->iova_to_phys(ops, iova);
}
- phys = readq_relaxed(cb_base + ARM_SMMU_CB_PAR);
+ phys = smmu_readq_relaxed(smmu, cb_base + ARM_SMMU_CB_PAR);
spin_unlock_irqrestore(&smmu_domain->cb_lock, flags);
if (phys & CB_PAR_F) {
dev_err(dev, "translation fault!\n");
--
2.20.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v2 2/4] iommu/arm-smmu: Workaround for Marvell Armada-AP806 SoC erratum #582743
2019-07-11 15:02 ` Gregory CLEMENT
(?)
@ 2019-07-11 15:02 ` Gregory CLEMENT
-1 siblings, 0 replies; 29+ messages in thread
From: Gregory CLEMENT @ 2019-07-11 15:02 UTC (permalink / raw)
To: Robin Murphy, Joerg Roedel, linux-kernel, iommu
Cc: Rob Herring, devicetree, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Gregory CLEMENT, Thomas Petazzoni,
linux-arm-kernel, Catalin Marinas, Will Deacon, Antoine Tenart,
Miquèl Raynal, Maxime Chevallier, Nadav Haklai, Hanna Hawa
From: Hanna Hawa <hannah@marvell.com>
Due to erratum #582743, the Marvell Armada-AP806 can't access 64bit to
ARM SMMUv2 registers.
This patch split the writeq/readq to two accesses of writel/readl.
We also mask the MMU_IDR2.PTFSv8 fields to not use AArch64 format but
only AARCH32_L. Indeed with AArch64 format 32 bits acces is not
supported.
Note that separate writes/reads to 2 is not problem regards to
atomicity, because the driver use the readq/writeq while initialize
the SMMU, report for SMMU fault, and use spinlock in one
case (iova_to_phys).
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
Documentation/arm64/silicon-errata.txt | 2 ++
drivers/iommu/arm-smmu.c | 42 +++++++++++++++++++++++---
2 files changed, 40 insertions(+), 4 deletions(-)
diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
index d1e2bb801e1b..3f78ae7a7690 100644
--- a/Documentation/arm64/silicon-errata.txt
+++ b/Documentation/arm64/silicon-errata.txt
@@ -72,6 +72,8 @@ stable kernels.
| Cavium | ThunderX2 SMMUv3| #74 | N/A |
| Cavium | ThunderX2 SMMUv3| #126 | N/A |
| | | | |
+| Marvell | ARM-MMU-500 | #582743 | N/A |
+| | | | |
| Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 |
| | | | |
| Hisilicon | Hip0{5,6,7} | #161010101 | HISILICON_ERRATUM_161010101 |
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index ac0784b5b675..32536ccae22d 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -126,6 +126,7 @@ enum arm_smmu_arch_version {
enum arm_smmu_implementation {
GENERIC_SMMU,
ARM_MMU500,
+ MRVL_MMU500,
CAVIUM_SMMUV2,
QCOM_SMMUV2,
};
@@ -301,13 +302,35 @@ static inline void smmu_writeq_relaxed(struct arm_smmu_device *smmu,
u64 val,
void __iomem *addr)
{
- writeq_relaxed(val, addr);
+ /*
+ * Marvell Armada-AP806 erratum #582743.
+ * Split all the writeq to double writel
+ */
+ if (smmu->model != MRVL_MMU500) {
+ writeq_relaxed(val, addr);
+ return;
+ }
+
+ writel_relaxed(upper_32_bits(val), addr + 4);
+ writel_relaxed(lower_32_bits(val), addr);
}
static inline u64 smmu_readq_relaxed(struct arm_smmu_device *smmu,
void __iomem *addr)
{
- return readq_relaxed(addr);
+ u64 val;
+
+ /*
+ * Marvell Armada-AP806 erratum #582743.
+ * Split all the readq to double readl
+ */
+ if (smmu->model != MRVL_MMU500)
+ return readq_relaxed(addr);
+
+ val = (u64)readl_relaxed(addr + 4) << 32;
+ val |= readl_relaxed(addr);
+
+ return val;
}
static void parse_driver_options(struct arm_smmu_device *smmu)
@@ -1741,7 +1764,7 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
for (i = 0; i < smmu->num_mapping_groups; ++i)
arm_smmu_write_sme(smmu, i);
- if (smmu->model == ARM_MMU500) {
+ if (smmu->model == ARM_MMU500 || smmu->model == MRVL_MMU500) {
/*
* Before clearing ARM_MMU500_ACTLR_CPRE, need to
* clear CACHE_LOCK bit of ACR first. And, CACHE_LOCK
@@ -1770,7 +1793,7 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
* Disable MMU-500's not-particularly-beneficial next-page
* prefetcher for the sake of errata #841119 and #826419.
*/
- if (smmu->model == ARM_MMU500) {
+ if (smmu->model == ARM_MMU500 || smmu->model == MRVL_MMU500) {
reg = readl_relaxed(cb_base + ARM_SMMU_CB_ACTLR);
reg &= ~ARM_MMU500_ACTLR_CPRE;
writel_relaxed(reg, cb_base + ARM_SMMU_CB_ACTLR);
@@ -1987,6 +2010,15 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
if (id & ID2_VMID16)
smmu->features |= ARM_SMMU_FEAT_VMID16;
+ /*
+ * Armada-AP806 erratum #582743.
+ * Hide the SMMU_IDR2.PTFSv8 fields to sidestep the AArch64
+ * formats altogether and allow using 32 bits access on the
+ * interconnect.
+ */
+ if (smmu->model == MRVL_MMU500)
+ id &= ~(ID2_PTFS_4K | ID2_PTFS_16K | ID2_PTFS_64K);
+
/*
* What the page table walker can address actually depends on which
* descriptor format is in use, but since a) we don't know that yet,
@@ -2053,6 +2085,7 @@ ARM_SMMU_MATCH_DATA(smmu_generic_v1, ARM_SMMU_V1, GENERIC_SMMU);
ARM_SMMU_MATCH_DATA(smmu_generic_v2, ARM_SMMU_V2, GENERIC_SMMU);
ARM_SMMU_MATCH_DATA(arm_mmu401, ARM_SMMU_V1_64K, GENERIC_SMMU);
ARM_SMMU_MATCH_DATA(arm_mmu500, ARM_SMMU_V2, ARM_MMU500);
+ARM_SMMU_MATCH_DATA(mrvl_mmu500, ARM_SMMU_V2, MRVL_MMU500);
ARM_SMMU_MATCH_DATA(cavium_smmuv2, ARM_SMMU_V2, CAVIUM_SMMUV2);
ARM_SMMU_MATCH_DATA(qcom_smmuv2, ARM_SMMU_V2, QCOM_SMMUV2);
@@ -2062,6 +2095,7 @@ static const struct of_device_id arm_smmu_of_match[] = {
{ .compatible = "arm,mmu-400", .data = &smmu_generic_v1 },
{ .compatible = "arm,mmu-401", .data = &arm_mmu401 },
{ .compatible = "arm,mmu-500", .data = &arm_mmu500 },
+ { .compatible = "marvell,mmu-500", .data = &mrvl_mmu500 },
{ .compatible = "cavium,smmu-v2", .data = &cavium_smmuv2 },
{ .compatible = "qcom,smmu-v2", .data = &qcom_smmuv2 },
{ },
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v2 2/4] iommu/arm-smmu: Workaround for Marvell Armada-AP806 SoC erratum #582743
@ 2019-07-11 15:02 ` Gregory CLEMENT
0 siblings, 0 replies; 29+ messages in thread
From: Gregory CLEMENT @ 2019-07-11 15:02 UTC (permalink / raw)
To: Robin Murphy, Joerg Roedel, linux-kernel, iommu
Cc: devicetree, Jason Cooper, Andrew Lunn, Antoine Tenart,
Catalin Marinas, Gregory CLEMENT, Will Deacon, Maxime Chevallier,
Nadav Haklai, Rob Herring, Thomas Petazzoni, Miquèl Raynal,
Hanna Hawa, linux-arm-kernel, Sebastian Hesselbarth
From: Hanna Hawa <hannah@marvell.com>
Due to erratum #582743, the Marvell Armada-AP806 can't access 64bit to
ARM SMMUv2 registers.
This patch split the writeq/readq to two accesses of writel/readl.
We also mask the MMU_IDR2.PTFSv8 fields to not use AArch64 format but
only AARCH32_L. Indeed with AArch64 format 32 bits acces is not
supported.
Note that separate writes/reads to 2 is not problem regards to
atomicity, because the driver use the readq/writeq while initialize
the SMMU, report for SMMU fault, and use spinlock in one
case (iova_to_phys).
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
Documentation/arm64/silicon-errata.txt | 2 ++
drivers/iommu/arm-smmu.c | 42 +++++++++++++++++++++++---
2 files changed, 40 insertions(+), 4 deletions(-)
diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
index d1e2bb801e1b..3f78ae7a7690 100644
--- a/Documentation/arm64/silicon-errata.txt
+++ b/Documentation/arm64/silicon-errata.txt
@@ -72,6 +72,8 @@ stable kernels.
| Cavium | ThunderX2 SMMUv3| #74 | N/A |
| Cavium | ThunderX2 SMMUv3| #126 | N/A |
| | | | |
+| Marvell | ARM-MMU-500 | #582743 | N/A |
+| | | | |
| Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 |
| | | | |
| Hisilicon | Hip0{5,6,7} | #161010101 | HISILICON_ERRATUM_161010101 |
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index ac0784b5b675..32536ccae22d 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -126,6 +126,7 @@ enum arm_smmu_arch_version {
enum arm_smmu_implementation {
GENERIC_SMMU,
ARM_MMU500,
+ MRVL_MMU500,
CAVIUM_SMMUV2,
QCOM_SMMUV2,
};
@@ -301,13 +302,35 @@ static inline void smmu_writeq_relaxed(struct arm_smmu_device *smmu,
u64 val,
void __iomem *addr)
{
- writeq_relaxed(val, addr);
+ /*
+ * Marvell Armada-AP806 erratum #582743.
+ * Split all the writeq to double writel
+ */
+ if (smmu->model != MRVL_MMU500) {
+ writeq_relaxed(val, addr);
+ return;
+ }
+
+ writel_relaxed(upper_32_bits(val), addr + 4);
+ writel_relaxed(lower_32_bits(val), addr);
}
static inline u64 smmu_readq_relaxed(struct arm_smmu_device *smmu,
void __iomem *addr)
{
- return readq_relaxed(addr);
+ u64 val;
+
+ /*
+ * Marvell Armada-AP806 erratum #582743.
+ * Split all the readq to double readl
+ */
+ if (smmu->model != MRVL_MMU500)
+ return readq_relaxed(addr);
+
+ val = (u64)readl_relaxed(addr + 4) << 32;
+ val |= readl_relaxed(addr);
+
+ return val;
}
static void parse_driver_options(struct arm_smmu_device *smmu)
@@ -1741,7 +1764,7 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
for (i = 0; i < smmu->num_mapping_groups; ++i)
arm_smmu_write_sme(smmu, i);
- if (smmu->model == ARM_MMU500) {
+ if (smmu->model == ARM_MMU500 || smmu->model == MRVL_MMU500) {
/*
* Before clearing ARM_MMU500_ACTLR_CPRE, need to
* clear CACHE_LOCK bit of ACR first. And, CACHE_LOCK
@@ -1770,7 +1793,7 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
* Disable MMU-500's not-particularly-beneficial next-page
* prefetcher for the sake of errata #841119 and #826419.
*/
- if (smmu->model == ARM_MMU500) {
+ if (smmu->model == ARM_MMU500 || smmu->model == MRVL_MMU500) {
reg = readl_relaxed(cb_base + ARM_SMMU_CB_ACTLR);
reg &= ~ARM_MMU500_ACTLR_CPRE;
writel_relaxed(reg, cb_base + ARM_SMMU_CB_ACTLR);
@@ -1987,6 +2010,15 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
if (id & ID2_VMID16)
smmu->features |= ARM_SMMU_FEAT_VMID16;
+ /*
+ * Armada-AP806 erratum #582743.
+ * Hide the SMMU_IDR2.PTFSv8 fields to sidestep the AArch64
+ * formats altogether and allow using 32 bits access on the
+ * interconnect.
+ */
+ if (smmu->model == MRVL_MMU500)
+ id &= ~(ID2_PTFS_4K | ID2_PTFS_16K | ID2_PTFS_64K);
+
/*
* What the page table walker can address actually depends on which
* descriptor format is in use, but since a) we don't know that yet,
@@ -2053,6 +2085,7 @@ ARM_SMMU_MATCH_DATA(smmu_generic_v1, ARM_SMMU_V1, GENERIC_SMMU);
ARM_SMMU_MATCH_DATA(smmu_generic_v2, ARM_SMMU_V2, GENERIC_SMMU);
ARM_SMMU_MATCH_DATA(arm_mmu401, ARM_SMMU_V1_64K, GENERIC_SMMU);
ARM_SMMU_MATCH_DATA(arm_mmu500, ARM_SMMU_V2, ARM_MMU500);
+ARM_SMMU_MATCH_DATA(mrvl_mmu500, ARM_SMMU_V2, MRVL_MMU500);
ARM_SMMU_MATCH_DATA(cavium_smmuv2, ARM_SMMU_V2, CAVIUM_SMMUV2);
ARM_SMMU_MATCH_DATA(qcom_smmuv2, ARM_SMMU_V2, QCOM_SMMUV2);
@@ -2062,6 +2095,7 @@ static const struct of_device_id arm_smmu_of_match[] = {
{ .compatible = "arm,mmu-400", .data = &smmu_generic_v1 },
{ .compatible = "arm,mmu-401", .data = &arm_mmu401 },
{ .compatible = "arm,mmu-500", .data = &arm_mmu500 },
+ { .compatible = "marvell,mmu-500", .data = &mrvl_mmu500 },
{ .compatible = "cavium,smmu-v2", .data = &cavium_smmuv2 },
{ .compatible = "qcom,smmu-v2", .data = &qcom_smmuv2 },
{ },
--
2.20.1
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v2 2/4] iommu/arm-smmu: Workaround for Marvell Armada-AP806 SoC erratum #582743
@ 2019-07-11 15:02 ` Gregory CLEMENT
0 siblings, 0 replies; 29+ messages in thread
From: Gregory CLEMENT @ 2019-07-11 15:02 UTC (permalink / raw)
To: Robin Murphy, Joerg Roedel, linux-kernel, iommu
Cc: devicetree, Jason Cooper, Andrew Lunn, Antoine Tenart,
Catalin Marinas, Gregory CLEMENT, Will Deacon, Maxime Chevallier,
Nadav Haklai, Rob Herring, Thomas Petazzoni, Miquèl Raynal,
Hanna Hawa, linux-arm-kernel, Sebastian Hesselbarth
From: Hanna Hawa <hannah@marvell.com>
Due to erratum #582743, the Marvell Armada-AP806 can't access 64bit to
ARM SMMUv2 registers.
This patch split the writeq/readq to two accesses of writel/readl.
We also mask the MMU_IDR2.PTFSv8 fields to not use AArch64 format but
only AARCH32_L. Indeed with AArch64 format 32 bits acces is not
supported.
Note that separate writes/reads to 2 is not problem regards to
atomicity, because the driver use the readq/writeq while initialize
the SMMU, report for SMMU fault, and use spinlock in one
case (iova_to_phys).
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
Documentation/arm64/silicon-errata.txt | 2 ++
drivers/iommu/arm-smmu.c | 42 +++++++++++++++++++++++---
2 files changed, 40 insertions(+), 4 deletions(-)
diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
index d1e2bb801e1b..3f78ae7a7690 100644
--- a/Documentation/arm64/silicon-errata.txt
+++ b/Documentation/arm64/silicon-errata.txt
@@ -72,6 +72,8 @@ stable kernels.
| Cavium | ThunderX2 SMMUv3| #74 | N/A |
| Cavium | ThunderX2 SMMUv3| #126 | N/A |
| | | | |
+| Marvell | ARM-MMU-500 | #582743 | N/A |
+| | | | |
| Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 |
| | | | |
| Hisilicon | Hip0{5,6,7} | #161010101 | HISILICON_ERRATUM_161010101 |
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index ac0784b5b675..32536ccae22d 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -126,6 +126,7 @@ enum arm_smmu_arch_version {
enum arm_smmu_implementation {
GENERIC_SMMU,
ARM_MMU500,
+ MRVL_MMU500,
CAVIUM_SMMUV2,
QCOM_SMMUV2,
};
@@ -301,13 +302,35 @@ static inline void smmu_writeq_relaxed(struct arm_smmu_device *smmu,
u64 val,
void __iomem *addr)
{
- writeq_relaxed(val, addr);
+ /*
+ * Marvell Armada-AP806 erratum #582743.
+ * Split all the writeq to double writel
+ */
+ if (smmu->model != MRVL_MMU500) {
+ writeq_relaxed(val, addr);
+ return;
+ }
+
+ writel_relaxed(upper_32_bits(val), addr + 4);
+ writel_relaxed(lower_32_bits(val), addr);
}
static inline u64 smmu_readq_relaxed(struct arm_smmu_device *smmu,
void __iomem *addr)
{
- return readq_relaxed(addr);
+ u64 val;
+
+ /*
+ * Marvell Armada-AP806 erratum #582743.
+ * Split all the readq to double readl
+ */
+ if (smmu->model != MRVL_MMU500)
+ return readq_relaxed(addr);
+
+ val = (u64)readl_relaxed(addr + 4) << 32;
+ val |= readl_relaxed(addr);
+
+ return val;
}
static void parse_driver_options(struct arm_smmu_device *smmu)
@@ -1741,7 +1764,7 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
for (i = 0; i < smmu->num_mapping_groups; ++i)
arm_smmu_write_sme(smmu, i);
- if (smmu->model == ARM_MMU500) {
+ if (smmu->model == ARM_MMU500 || smmu->model == MRVL_MMU500) {
/*
* Before clearing ARM_MMU500_ACTLR_CPRE, need to
* clear CACHE_LOCK bit of ACR first. And, CACHE_LOCK
@@ -1770,7 +1793,7 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
* Disable MMU-500's not-particularly-beneficial next-page
* prefetcher for the sake of errata #841119 and #826419.
*/
- if (smmu->model == ARM_MMU500) {
+ if (smmu->model == ARM_MMU500 || smmu->model == MRVL_MMU500) {
reg = readl_relaxed(cb_base + ARM_SMMU_CB_ACTLR);
reg &= ~ARM_MMU500_ACTLR_CPRE;
writel_relaxed(reg, cb_base + ARM_SMMU_CB_ACTLR);
@@ -1987,6 +2010,15 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
if (id & ID2_VMID16)
smmu->features |= ARM_SMMU_FEAT_VMID16;
+ /*
+ * Armada-AP806 erratum #582743.
+ * Hide the SMMU_IDR2.PTFSv8 fields to sidestep the AArch64
+ * formats altogether and allow using 32 bits access on the
+ * interconnect.
+ */
+ if (smmu->model == MRVL_MMU500)
+ id &= ~(ID2_PTFS_4K | ID2_PTFS_16K | ID2_PTFS_64K);
+
/*
* What the page table walker can address actually depends on which
* descriptor format is in use, but since a) we don't know that yet,
@@ -2053,6 +2085,7 @@ ARM_SMMU_MATCH_DATA(smmu_generic_v1, ARM_SMMU_V1, GENERIC_SMMU);
ARM_SMMU_MATCH_DATA(smmu_generic_v2, ARM_SMMU_V2, GENERIC_SMMU);
ARM_SMMU_MATCH_DATA(arm_mmu401, ARM_SMMU_V1_64K, GENERIC_SMMU);
ARM_SMMU_MATCH_DATA(arm_mmu500, ARM_SMMU_V2, ARM_MMU500);
+ARM_SMMU_MATCH_DATA(mrvl_mmu500, ARM_SMMU_V2, MRVL_MMU500);
ARM_SMMU_MATCH_DATA(cavium_smmuv2, ARM_SMMU_V2, CAVIUM_SMMUV2);
ARM_SMMU_MATCH_DATA(qcom_smmuv2, ARM_SMMU_V2, QCOM_SMMUV2);
@@ -2062,6 +2095,7 @@ static const struct of_device_id arm_smmu_of_match[] = {
{ .compatible = "arm,mmu-400", .data = &smmu_generic_v1 },
{ .compatible = "arm,mmu-401", .data = &arm_mmu401 },
{ .compatible = "arm,mmu-500", .data = &arm_mmu500 },
+ { .compatible = "marvell,mmu-500", .data = &mrvl_mmu500 },
{ .compatible = "cavium,smmu-v2", .data = &cavium_smmuv2 },
{ .compatible = "qcom,smmu-v2", .data = &qcom_smmuv2 },
{ },
--
2.20.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v2 3/4] dt-bindings: iommu/arm,smmu: add compatible string for Marvell
2019-07-11 15:02 ` Gregory CLEMENT
(?)
@ 2019-07-11 15:02 ` Gregory CLEMENT
-1 siblings, 0 replies; 29+ messages in thread
From: Gregory CLEMENT @ 2019-07-11 15:02 UTC (permalink / raw)
To: Robin Murphy, Joerg Roedel, linux-kernel, iommu
Cc: Rob Herring, devicetree, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Gregory CLEMENT, Thomas Petazzoni,
linux-arm-kernel, Catalin Marinas, Will Deacon, Antoine Tenart,
Miquèl Raynal, Maxime Chevallier, Nadav Haklai, Hanna Hawa
From: Hanna Hawa <hannah@marvell.com>
Add specific compatible string for Marvell usage due errata of
accessing 64bits registers of ARM SMMU, in AP806.
AP806 SoC uses the generic ARM-MMU500, and there's no specific
implementation of Marvell, this compatible is used for errata only.
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
Documentation/devicetree/bindings/iommu/arm,smmu.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
index 3133f3ba7567..7ed58d51846e 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
@@ -16,6 +16,7 @@ conditions.
"arm,mmu-400"
"arm,mmu-401"
"arm,mmu-500"
+ "marvell,mmu-500"
"cavium,smmu-v2"
"qcom,smmu-v2"
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v2 3/4] dt-bindings: iommu/arm, smmu: add compatible string for Marvell
@ 2019-07-11 15:02 ` Gregory CLEMENT
0 siblings, 0 replies; 29+ messages in thread
From: Gregory CLEMENT @ 2019-07-11 15:02 UTC (permalink / raw)
To: Robin Murphy, Joerg Roedel, linux-kernel, iommu
Cc: devicetree, Jason Cooper, Andrew Lunn, Antoine Tenart,
Catalin Marinas, Gregory CLEMENT, Will Deacon, Maxime Chevallier,
Nadav Haklai, Rob Herring, Thomas Petazzoni, Miquèl Raynal,
Hanna Hawa, linux-arm-kernel, Sebastian Hesselbarth
From: Hanna Hawa <hannah@marvell.com>
Add specific compatible string for Marvell usage due errata of
accessing 64bits registers of ARM SMMU, in AP806.
AP806 SoC uses the generic ARM-MMU500, and there's no specific
implementation of Marvell, this compatible is used for errata only.
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
Documentation/devicetree/bindings/iommu/arm,smmu.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
index 3133f3ba7567..7ed58d51846e 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
@@ -16,6 +16,7 @@ conditions.
"arm,mmu-400"
"arm,mmu-401"
"arm,mmu-500"
+ "marvell,mmu-500"
"cavium,smmu-v2"
"qcom,smmu-v2"
--
2.20.1
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v2 3/4] dt-bindings: iommu/arm, smmu: add compatible string for Marvell
@ 2019-07-11 15:02 ` Gregory CLEMENT
0 siblings, 0 replies; 29+ messages in thread
From: Gregory CLEMENT @ 2019-07-11 15:02 UTC (permalink / raw)
To: Robin Murphy, Joerg Roedel, linux-kernel, iommu
Cc: devicetree, Jason Cooper, Andrew Lunn, Antoine Tenart,
Catalin Marinas, Gregory CLEMENT, Will Deacon, Maxime Chevallier,
Nadav Haklai, Rob Herring, Thomas Petazzoni, Miquèl Raynal,
Hanna Hawa, linux-arm-kernel, Sebastian Hesselbarth
From: Hanna Hawa <hannah@marvell.com>
Add specific compatible string for Marvell usage due errata of
accessing 64bits registers of ARM SMMU, in AP806.
AP806 SoC uses the generic ARM-MMU500, and there's no specific
implementation of Marvell, this compatible is used for errata only.
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
Documentation/devicetree/bindings/iommu/arm,smmu.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
index 3133f3ba7567..7ed58d51846e 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
@@ -16,6 +16,7 @@ conditions.
"arm,mmu-400"
"arm,mmu-401"
"arm,mmu-500"
+ "marvell,mmu-500"
"cavium,smmu-v2"
"qcom,smmu-v2"
--
2.20.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v2 4/4] arm64: dts: marvell: armada-ap806: add smmu support
2019-07-11 15:02 ` Gregory CLEMENT
(?)
@ 2019-07-11 15:02 ` Gregory CLEMENT
-1 siblings, 0 replies; 29+ messages in thread
From: Gregory CLEMENT @ 2019-07-11 15:02 UTC (permalink / raw)
To: Robin Murphy, Joerg Roedel, linux-kernel, iommu
Cc: Rob Herring, devicetree, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Gregory CLEMENT, Thomas Petazzoni,
linux-arm-kernel, Catalin Marinas, Will Deacon, Antoine Tenart,
Miquèl Raynal, Maxime Chevallier, Nadav Haklai
Add IOMMU node for Marvell AP806 based SoCs.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index 91dad7e4ee59..8e29d593970a 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@ -115,6 +115,23 @@
interrupts = <17>;
};
+ smmu: iommu@5000000 {
+ compatible = "marvell,mmu-500";
+ reg = <0x100000 0x100000>;
+ dma-coherent;
+ #iommu-cells = <1>;
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
odmi: odmi@300000 {
compatible = "marvell,odmi-controller";
interrupt-controller;
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v2 4/4] arm64: dts: marvell: armada-ap806: add smmu support
@ 2019-07-11 15:02 ` Gregory CLEMENT
0 siblings, 0 replies; 29+ messages in thread
From: Gregory CLEMENT @ 2019-07-11 15:02 UTC (permalink / raw)
To: Robin Murphy, Joerg Roedel, linux-kernel, iommu
Cc: devicetree, Jason Cooper, Andrew Lunn, Antoine Tenart,
Catalin Marinas, Gregory CLEMENT, Will Deacon, Maxime Chevallier,
Nadav Haklai, Rob Herring, Thomas Petazzoni, Miquèl Raynal,
linux-arm-kernel, Sebastian Hesselbarth
Add IOMMU node for Marvell AP806 based SoCs.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index 91dad7e4ee59..8e29d593970a 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@ -115,6 +115,23 @@
interrupts = <17>;
};
+ smmu: iommu@5000000 {
+ compatible = "marvell,mmu-500";
+ reg = <0x100000 0x100000>;
+ dma-coherent;
+ #iommu-cells = <1>;
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
odmi: odmi@300000 {
compatible = "marvell,odmi-controller";
interrupt-controller;
--
2.20.1
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v2 4/4] arm64: dts: marvell: armada-ap806: add smmu support
@ 2019-07-11 15:02 ` Gregory CLEMENT
0 siblings, 0 replies; 29+ messages in thread
From: Gregory CLEMENT @ 2019-07-11 15:02 UTC (permalink / raw)
To: Robin Murphy, Joerg Roedel, linux-kernel, iommu
Cc: devicetree, Jason Cooper, Andrew Lunn, Antoine Tenart,
Catalin Marinas, Gregory CLEMENT, Will Deacon, Maxime Chevallier,
Nadav Haklai, Rob Herring, Thomas Petazzoni, Miquèl Raynal,
linux-arm-kernel, Sebastian Hesselbarth
Add IOMMU node for Marvell AP806 based SoCs.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index 91dad7e4ee59..8e29d593970a 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@ -115,6 +115,23 @@
interrupts = <17>;
};
+ smmu: iommu@5000000 {
+ compatible = "marvell,mmu-500";
+ reg = <0x100000 0x100000>;
+ dma-coherent;
+ #iommu-cells = <1>;
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
odmi: odmi@300000 {
compatible = "marvell,odmi-controller";
interrupt-controller;
--
2.20.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 29+ messages in thread
* Re: [PATCH v2 3/4] dt-bindings: iommu/arm,smmu: add compatible string for Marvell
2019-07-11 15:02 ` Gregory CLEMENT
(?)
(?)
@ 2019-07-24 20:36 ` Rob Herring
-1 siblings, 0 replies; 29+ messages in thread
From: Rob Herring @ 2019-07-24 20:36 UTC (permalink / raw)
To: Gregory CLEMENT
Cc: Robin Murphy, Joerg Roedel, linux-kernel, iommu, devicetree,
Jason Cooper, Andrew Lunn, Sebastian Hesselbarth,
Gregory CLEMENT, Thomas Petazzoni, linux-arm-kernel,
Catalin Marinas, Will Deacon, Antoine Tenart, Miquèl Raynal,
Maxime Chevallier, Nadav Haklai, Hanna Hawa
On Thu, 11 Jul 2019 17:02:41 +0200, Gregory CLEMENT wrote:
> From: Hanna Hawa <hannah@marvell.com>
>
> Add specific compatible string for Marvell usage due errata of
> accessing 64bits registers of ARM SMMU, in AP806.
>
> AP806 SoC uses the generic ARM-MMU500, and there's no specific
> implementation of Marvell, this compatible is used for errata only.
>
> Signed-off-by: Hanna Hawa <hannah@marvell.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> ---
> Documentation/devicetree/bindings/iommu/arm,smmu.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v2 3/4] dt-bindings: iommu/arm,smmu: add compatible string for Marvell
@ 2019-07-24 20:36 ` Rob Herring
0 siblings, 0 replies; 29+ messages in thread
From: Rob Herring @ 2019-07-24 20:36 UTC (permalink / raw)
Cc: Robin Murphy, Joerg Roedel, linux-kernel, iommu, devicetree,
Jason Cooper, Andrew Lunn, Sebastian Hesselbarth,
Gregory CLEMENT, Thomas Petazzoni, linux-arm-kernel,
Catalin Marinas, Will Deacon, Antoine Tenart, Miquèl Raynal,
Maxime Chevallier, Nadav Haklai, Hanna Hawa
On Thu, 11 Jul 2019 17:02:41 +0200, Gregory CLEMENT wrote:
> From: Hanna Hawa <hannah@marvell.com>
>
> Add specific compatible string for Marvell usage due errata of
> accessing 64bits registers of ARM SMMU, in AP806.
>
> AP806 SoC uses the generic ARM-MMU500, and there's no specific
> implementation of Marvell, this compatible is used for errata only.
>
> Signed-off-by: Hanna Hawa <hannah@marvell.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> ---
> Documentation/devicetree/bindings/iommu/arm,smmu.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v2 3/4] dt-bindings: iommu/arm,smmu: add compatible string for Marvell
@ 2019-07-24 20:36 ` Rob Herring
0 siblings, 0 replies; 29+ messages in thread
From: Rob Herring @ 2019-07-24 20:36 UTC (permalink / raw)
To: Gregory CLEMENT
Cc: devicetree, Jason Cooper, Andrew Lunn, Antoine Tenart,
Catalin Marinas, Will Deacon, linux-kernel, Maxime Chevallier,
Nadav Haklai, iommu, Thomas Petazzoni, Miquèl Raynal,
Hanna Hawa, Robin Murphy, Gregory CLEMENT, linux-arm-kernel,
Sebastian Hesselbarth
On Thu, 11 Jul 2019 17:02:41 +0200, Gregory CLEMENT wrote:
> From: Hanna Hawa <hannah@marvell.com>
>
> Add specific compatible string for Marvell usage due errata of
> accessing 64bits registers of ARM SMMU, in AP806.
>
> AP806 SoC uses the generic ARM-MMU500, and there's no specific
> implementation of Marvell, this compatible is used for errata only.
>
> Signed-off-by: Hanna Hawa <hannah@marvell.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> ---
> Documentation/devicetree/bindings/iommu/arm,smmu.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Reviewed-by: Rob Herring <robh@kernel.org>
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v2 3/4] dt-bindings: iommu/arm,smmu: add compatible string for Marvell
@ 2019-07-24 20:36 ` Rob Herring
0 siblings, 0 replies; 29+ messages in thread
From: Rob Herring @ 2019-07-24 20:36 UTC (permalink / raw)
To: Gregory CLEMENT
Cc: devicetree, Jason Cooper, Andrew Lunn, Antoine Tenart,
Catalin Marinas, Joerg Roedel, Will Deacon, linux-kernel,
Maxime Chevallier, Nadav Haklai, iommu, Thomas Petazzoni,
Miquèl Raynal, Hanna Hawa, Robin Murphy, Gregory CLEMENT,
linux-arm-kernel, Sebastian Hesselbarth
On Thu, 11 Jul 2019 17:02:41 +0200, Gregory CLEMENT wrote:
> From: Hanna Hawa <hannah@marvell.com>
>
> Add specific compatible string for Marvell usage due errata of
> accessing 64bits registers of ARM SMMU, in AP806.
>
> AP806 SoC uses the generic ARM-MMU500, and there's no specific
> implementation of Marvell, this compatible is used for errata only.
>
> Signed-off-by: Hanna Hawa <hannah@marvell.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> ---
> Documentation/devicetree/bindings/iommu/arm,smmu.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Reviewed-by: Rob Herring <robh@kernel.org>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v2 1/4] iommu/arm-smmu: Introduce wrapper for writeq/readq
2019-07-11 15:02 ` Gregory CLEMENT
(?)
@ 2019-08-20 12:08 ` Will Deacon
-1 siblings, 0 replies; 29+ messages in thread
From: Will Deacon @ 2019-08-20 12:08 UTC (permalink / raw)
To: Gregory CLEMENT
Cc: Robin Murphy, Joerg Roedel, linux-kernel, iommu, devicetree,
Jason Cooper, Andrew Lunn, Antoine Tenart, Catalin Marinas,
Will Deacon, Maxime Chevallier, Nadav Haklai, Rob Herring,
Thomas Petazzoni, Miquèl Raynal, Hanna Hawa,
linux-arm-kernel, Sebastian Hesselbarth
Hi Gregory, Hanna,
On Thu, Jul 11, 2019 at 05:02:39PM +0200, Gregory CLEMENT wrote:
> From: Hanna Hawa <hannah@marvell.com>
>
> This patch introduces the smmu_writeq_relaxed/smmu_readq_relaxed
> helpers, as preparation to add specific Marvell work-around for
> accessing 64 bits width registers of ARM SMMU.
>
> Signed-off-by: Hanna Hawa <hannah@marvell.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> ---
> drivers/iommu/arm-smmu.c | 36 +++++++++++++++++++++++++++---------
> 1 file changed, 27 insertions(+), 9 deletions(-)
Sorry for the delay in replying to this -- Robin's been reworking the driver
so that implementation quirks can be specified more cleanly. Please can you
take a look at:
https://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git/log/?h=for-joerg/arm-smmu/refactoring
and try to respin your patches on top of that?
Thanks,
Will
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v2 1/4] iommu/arm-smmu: Introduce wrapper for writeq/readq
@ 2019-08-20 12:08 ` Will Deacon
0 siblings, 0 replies; 29+ messages in thread
From: Will Deacon @ 2019-08-20 12:08 UTC (permalink / raw)
To: Gregory CLEMENT
Cc: devicetree, Jason Cooper, Andrew Lunn, Antoine Tenart,
Catalin Marinas, Will Deacon, linux-kernel, Maxime Chevallier,
Nadav Haklai, iommu, Rob Herring, Thomas Petazzoni,
Miquèl Raynal, Robin Murphy, Hanna Hawa, linux-arm-kernel,
Sebastian Hesselbarth
Hi Gregory, Hanna,
On Thu, Jul 11, 2019 at 05:02:39PM +0200, Gregory CLEMENT wrote:
> From: Hanna Hawa <hannah@marvell.com>
>
> This patch introduces the smmu_writeq_relaxed/smmu_readq_relaxed
> helpers, as preparation to add specific Marvell work-around for
> accessing 64 bits width registers of ARM SMMU.
>
> Signed-off-by: Hanna Hawa <hannah@marvell.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> ---
> drivers/iommu/arm-smmu.c | 36 +++++++++++++++++++++++++++---------
> 1 file changed, 27 insertions(+), 9 deletions(-)
Sorry for the delay in replying to this -- Robin's been reworking the driver
so that implementation quirks can be specified more cleanly. Please can you
take a look at:
https://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git/log/?h=for-joerg/arm-smmu/refactoring
and try to respin your patches on top of that?
Thanks,
Will
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v2 1/4] iommu/arm-smmu: Introduce wrapper for writeq/readq
@ 2019-08-20 12:08 ` Will Deacon
0 siblings, 0 replies; 29+ messages in thread
From: Will Deacon @ 2019-08-20 12:08 UTC (permalink / raw)
To: Gregory CLEMENT
Cc: devicetree, Jason Cooper, Andrew Lunn, Antoine Tenart,
Catalin Marinas, Joerg Roedel, Will Deacon, linux-kernel,
Maxime Chevallier, Nadav Haklai, iommu, Rob Herring,
Thomas Petazzoni, Miquèl Raynal, Robin Murphy, Hanna Hawa,
linux-arm-kernel, Sebastian Hesselbarth
Hi Gregory, Hanna,
On Thu, Jul 11, 2019 at 05:02:39PM +0200, Gregory CLEMENT wrote:
> From: Hanna Hawa <hannah@marvell.com>
>
> This patch introduces the smmu_writeq_relaxed/smmu_readq_relaxed
> helpers, as preparation to add specific Marvell work-around for
> accessing 64 bits width registers of ARM SMMU.
>
> Signed-off-by: Hanna Hawa <hannah@marvell.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> ---
> drivers/iommu/arm-smmu.c | 36 +++++++++++++++++++++++++++---------
> 1 file changed, 27 insertions(+), 9 deletions(-)
Sorry for the delay in replying to this -- Robin's been reworking the driver
so that implementation quirks can be specified more cleanly. Please can you
take a look at:
https://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git/log/?h=for-joerg/arm-smmu/refactoring
and try to respin your patches on top of that?
Thanks,
Will
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v2 3/4] dt-bindings: iommu/arm,smmu: add compatible string for Marvell
2019-07-11 15:02 ` Gregory CLEMENT
(?)
@ 2019-08-22 14:16 ` Robin Murphy
-1 siblings, 0 replies; 29+ messages in thread
From: Robin Murphy @ 2019-08-22 14:16 UTC (permalink / raw)
To: Gregory CLEMENT, Joerg Roedel, linux-kernel, iommu
Cc: Rob Herring, devicetree, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Thomas Petazzoni, linux-arm-kernel,
Catalin Marinas, Will Deacon, Antoine Tenart, Miquèl Raynal,
Maxime Chevallier, Nadav Haklai, Hanna Hawa
On 11/07/2019 16:02, Gregory CLEMENT wrote:
> From: Hanna Hawa <hannah@marvell.com>
>
> Add specific compatible string for Marvell usage due errata of
> accessing 64bits registers of ARM SMMU, in AP806.
>
> AP806 SoC uses the generic ARM-MMU500, and there's no specific
> implementation of Marvell, this compatible is used for errata only.
Forgive me for repeating myself[1], but:
"Given that, I think something more specific like:
"marvell,ap806-smmu", "arm,mmu-500";
would be most appropriate. Otherwise, if some future Marvell SoC were to
ever come out with a *different* MMU-500 integration problem, you'd
already have painted yourself into a corner."
Robin.
[1]
https://lore.kernel.org/linux-arm-kernel/3ce1d67a-4e3c-e8d8-f7fc-79649f1def68@arm.com/
> Signed-off-by: Hanna Hawa <hannah@marvell.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> ---
> Documentation/devicetree/bindings/iommu/arm,smmu.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
> index 3133f3ba7567..7ed58d51846e 100644
> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
> @@ -16,6 +16,7 @@ conditions.
> "arm,mmu-400"
> "arm,mmu-401"
> "arm,mmu-500"
> + "marvell,mmu-500"
> "cavium,smmu-v2"
> "qcom,smmu-v2"
>
>
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v2 3/4] dt-bindings: iommu/arm, smmu: add compatible string for Marvell
@ 2019-08-22 14:16 ` Robin Murphy
0 siblings, 0 replies; 29+ messages in thread
From: Robin Murphy @ 2019-08-22 14:16 UTC (permalink / raw)
To: Gregory CLEMENT, Joerg Roedel, linux-kernel, iommu
Cc: devicetree, Jason Cooper, Andrew Lunn, Antoine Tenart,
Catalin Marinas, Hanna Hawa, Will Deacon, Maxime Chevallier,
Nadav Haklai, Rob Herring, Thomas Petazzoni, Miquèl Raynal,
linux-arm-kernel, Sebastian Hesselbarth
On 11/07/2019 16:02, Gregory CLEMENT wrote:
> From: Hanna Hawa <hannah@marvell.com>
>
> Add specific compatible string for Marvell usage due errata of
> accessing 64bits registers of ARM SMMU, in AP806.
>
> AP806 SoC uses the generic ARM-MMU500, and there's no specific
> implementation of Marvell, this compatible is used for errata only.
Forgive me for repeating myself[1], but:
"Given that, I think something more specific like:
"marvell,ap806-smmu", "arm,mmu-500";
would be most appropriate. Otherwise, if some future Marvell SoC were to
ever come out with a *different* MMU-500 integration problem, you'd
already have painted yourself into a corner."
Robin.
[1]
https://lore.kernel.org/linux-arm-kernel/3ce1d67a-4e3c-e8d8-f7fc-79649f1def68@arm.com/
> Signed-off-by: Hanna Hawa <hannah@marvell.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> ---
> Documentation/devicetree/bindings/iommu/arm,smmu.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
> index 3133f3ba7567..7ed58d51846e 100644
> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
> @@ -16,6 +16,7 @@ conditions.
> "arm,mmu-400"
> "arm,mmu-401"
> "arm,mmu-500"
> + "marvell,mmu-500"
> "cavium,smmu-v2"
> "qcom,smmu-v2"
>
>
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v2 3/4] dt-bindings: iommu/arm, smmu: add compatible string for Marvell
@ 2019-08-22 14:16 ` Robin Murphy
0 siblings, 0 replies; 29+ messages in thread
From: Robin Murphy @ 2019-08-22 14:16 UTC (permalink / raw)
To: Gregory CLEMENT, Joerg Roedel, linux-kernel, iommu
Cc: devicetree, Jason Cooper, Andrew Lunn, Antoine Tenart,
Catalin Marinas, Hanna Hawa, Will Deacon, Maxime Chevallier,
Nadav Haklai, Rob Herring, Thomas Petazzoni, Miquèl Raynal,
linux-arm-kernel, Sebastian Hesselbarth
On 11/07/2019 16:02, Gregory CLEMENT wrote:
> From: Hanna Hawa <hannah@marvell.com>
>
> Add specific compatible string for Marvell usage due errata of
> accessing 64bits registers of ARM SMMU, in AP806.
>
> AP806 SoC uses the generic ARM-MMU500, and there's no specific
> implementation of Marvell, this compatible is used for errata only.
Forgive me for repeating myself[1], but:
"Given that, I think something more specific like:
"marvell,ap806-smmu", "arm,mmu-500";
would be most appropriate. Otherwise, if some future Marvell SoC were to
ever come out with a *different* MMU-500 integration problem, you'd
already have painted yourself into a corner."
Robin.
[1]
https://lore.kernel.org/linux-arm-kernel/3ce1d67a-4e3c-e8d8-f7fc-79649f1def68@arm.com/
> Signed-off-by: Hanna Hawa <hannah@marvell.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> ---
> Documentation/devicetree/bindings/iommu/arm,smmu.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
> index 3133f3ba7567..7ed58d51846e 100644
> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
> @@ -16,6 +16,7 @@ conditions.
> "arm,mmu-400"
> "arm,mmu-401"
> "arm,mmu-500"
> + "marvell,mmu-500"
> "cavium,smmu-v2"
> "qcom,smmu-v2"
>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v2 1/4] iommu/arm-smmu: Introduce wrapper for writeq/readq
2019-08-20 12:08 ` Will Deacon
(?)
(?)
@ 2019-08-22 14:30 ` Robin Murphy
-1 siblings, 0 replies; 29+ messages in thread
From: Robin Murphy @ 2019-08-22 14:30 UTC (permalink / raw)
To: Will Deacon, Gregory CLEMENT
Cc: devicetree, Jason Cooper, Andrew Lunn, Antoine Tenart,
Catalin Marinas, Will Deacon, linux-kernel, Maxime Chevallier,
Nadav Haklai, iommu, Rob Herring, Thomas Petazzoni,
Miquèl Raynal, Hanna Hawa, linux-arm-kernel,
Sebastian Hesselbarth
On 20/08/2019 13:08, Will Deacon wrote:
> Hi Gregory, Hanna,
>
> On Thu, Jul 11, 2019 at 05:02:39PM +0200, Gregory CLEMENT wrote:
>> From: Hanna Hawa <hannah@marvell.com>
>>
>> This patch introduces the smmu_writeq_relaxed/smmu_readq_relaxed
>> helpers, as preparation to add specific Marvell work-around for
>> accessing 64 bits width registers of ARM SMMU.
>>
>> Signed-off-by: Hanna Hawa <hannah@marvell.com>
>> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
>> ---
>> drivers/iommu/arm-smmu.c | 36 +++++++++++++++++++++++++++---------
>> 1 file changed, 27 insertions(+), 9 deletions(-)
>
> Sorry for the delay in replying to this -- Robin's been reworking the driver
> so that implementation quirks can be specified more cleanly. Please can you
> take a look at:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git/log/?h=for-joerg/arm-smmu/refactoring
>
> and try to respin your patches on top of that?
Right, the arm_smmu_impl design was specifically anticipating this quirk
as well - it should just be a case of a cfg_probe hook to hide the
features which can't work, plus {read,write}_reg64 hooks to override any
remaining 64-bit accesses with the explicit hi_lo_* variants, munged
together (either statically or dynamically) with the standard MMU-500 hooks.
Robin.
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v2 1/4] iommu/arm-smmu: Introduce wrapper for writeq/readq
@ 2019-08-22 14:30 ` Robin Murphy
0 siblings, 0 replies; 29+ messages in thread
From: Robin Murphy @ 2019-08-22 14:30 UTC (permalink / raw)
To: Will Deacon, Gregory CLEMENT
Cc: devicetree, Jason Cooper, Andrew Lunn, Antoine Tenart,
Catalin Marinas, Hanna Hawa, Will Deacon, linux-kernel,
Maxime Chevallier, Nadav Haklai, iommu, Rob Herring,
Thomas Petazzoni, Miquèl Raynal, linux-arm-kernel,
Sebastian Hesselbarth
On 20/08/2019 13:08, Will Deacon wrote:
> Hi Gregory, Hanna,
>
> On Thu, Jul 11, 2019 at 05:02:39PM +0200, Gregory CLEMENT wrote:
>> From: Hanna Hawa <hannah@marvell.com>
>>
>> This patch introduces the smmu_writeq_relaxed/smmu_readq_relaxed
>> helpers, as preparation to add specific Marvell work-around for
>> accessing 64 bits width registers of ARM SMMU.
>>
>> Signed-off-by: Hanna Hawa <hannah@marvell.com>
>> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
>> ---
>> drivers/iommu/arm-smmu.c | 36 +++++++++++++++++++++++++++---------
>> 1 file changed, 27 insertions(+), 9 deletions(-)
>
> Sorry for the delay in replying to this -- Robin's been reworking the driver
> so that implementation quirks can be specified more cleanly. Please can you
> take a look at:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git/log/?h=for-joerg/arm-smmu/refactoring
>
> and try to respin your patches on top of that?
Right, the arm_smmu_impl design was specifically anticipating this quirk
as well - it should just be a case of a cfg_probe hook to hide the
features which can't work, plus {read,write}_reg64 hooks to override any
remaining 64-bit accesses with the explicit hi_lo_* variants, munged
together (either statically or dynamically) with the standard MMU-500 hooks.
Robin.
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v2 1/4] iommu/arm-smmu: Introduce wrapper for writeq/readq
@ 2019-08-22 14:30 ` Robin Murphy
0 siblings, 0 replies; 29+ messages in thread
From: Robin Murphy @ 2019-08-22 14:30 UTC (permalink / raw)
To: Will Deacon, Gregory CLEMENT
Cc: devicetree, Jason Cooper, Andrew Lunn, Antoine Tenart,
Catalin Marinas, Hanna Hawa, Will Deacon, linux-kernel,
Maxime Chevallier, Nadav Haklai, iommu, Rob Herring,
Thomas Petazzoni, Miquèl Raynal, linux-arm-kernel,
Sebastian Hesselbarth
On 20/08/2019 13:08, Will Deacon wrote:
> Hi Gregory, Hanna,
>
> On Thu, Jul 11, 2019 at 05:02:39PM +0200, Gregory CLEMENT wrote:
>> From: Hanna Hawa <hannah@marvell.com>
>>
>> This patch introduces the smmu_writeq_relaxed/smmu_readq_relaxed
>> helpers, as preparation to add specific Marvell work-around for
>> accessing 64 bits width registers of ARM SMMU.
>>
>> Signed-off-by: Hanna Hawa <hannah@marvell.com>
>> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
>> ---
>> drivers/iommu/arm-smmu.c | 36 +++++++++++++++++++++++++++---------
>> 1 file changed, 27 insertions(+), 9 deletions(-)
>
> Sorry for the delay in replying to this -- Robin's been reworking the driver
> so that implementation quirks can be specified more cleanly. Please can you
> take a look at:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git/log/?h=for-joerg/arm-smmu/refactoring
>
> and try to respin your patches on top of that?
Right, the arm_smmu_impl design was specifically anticipating this quirk
as well - it should just be a case of a cfg_probe hook to hide the
features which can't work, plus {read,write}_reg64 hooks to override any
remaining 64-bit accesses with the explicit hi_lo_* variants, munged
together (either statically or dynamically) with the standard MMU-500 hooks.
Robin.
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v2 1/4] iommu/arm-smmu: Introduce wrapper for writeq/readq
@ 2019-08-22 14:30 ` Robin Murphy
0 siblings, 0 replies; 29+ messages in thread
From: Robin Murphy @ 2019-08-22 14:30 UTC (permalink / raw)
To: Will Deacon, Gregory CLEMENT
Cc: devicetree, Jason Cooper, Andrew Lunn, Antoine Tenart,
Catalin Marinas, Hanna Hawa, Will Deacon, linux-kernel,
Maxime Chevallier, Nadav Haklai, iommu, Rob Herring,
Thomas Petazzoni, Miquèl Raynal, linux-arm-kernel,
Sebastian Hesselbarth
On 20/08/2019 13:08, Will Deacon wrote:
> Hi Gregory, Hanna,
>
> On Thu, Jul 11, 2019 at 05:02:39PM +0200, Gregory CLEMENT wrote:
>> From: Hanna Hawa <hannah@marvell.com>
>>
>> This patch introduces the smmu_writeq_relaxed/smmu_readq_relaxed
>> helpers, as preparation to add specific Marvell work-around for
>> accessing 64 bits width registers of ARM SMMU.
>>
>> Signed-off-by: Hanna Hawa <hannah@marvell.com>
>> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
>> ---
>> drivers/iommu/arm-smmu.c | 36 +++++++++++++++++++++++++++---------
>> 1 file changed, 27 insertions(+), 9 deletions(-)
>
> Sorry for the delay in replying to this -- Robin's been reworking the driver
> so that implementation quirks can be specified more cleanly. Please can you
> take a look at:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git/log/?h=for-joerg/arm-smmu/refactoring
>
> and try to respin your patches on top of that?
Right, the arm_smmu_impl design was specifically anticipating this quirk
as well - it should just be a case of a cfg_probe hook to hide the
features which can't work, plus {read,write}_reg64 hooks to override any
remaining 64-bit accesses with the explicit hi_lo_* variants, munged
together (either statically or dynamically) with the standard MMU-500 hooks.
Robin.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 29+ messages in thread
end of thread, other threads:[~2019-08-22 14:30 UTC | newest]
Thread overview: 29+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-07-11 15:02 [PATCH v2 0/4] Add system mmu support for Armada-806 Gregory CLEMENT
2019-07-11 15:02 ` Gregory CLEMENT
2019-07-11 15:02 ` Gregory CLEMENT
2019-07-11 15:02 ` [PATCH v2 1/4] iommu/arm-smmu: Introduce wrapper for writeq/readq Gregory CLEMENT
2019-07-11 15:02 ` Gregory CLEMENT
2019-07-11 15:02 ` Gregory CLEMENT
2019-08-20 12:08 ` Will Deacon
2019-08-20 12:08 ` Will Deacon
2019-08-20 12:08 ` Will Deacon
2019-08-22 14:30 ` Robin Murphy
2019-08-22 14:30 ` Robin Murphy
2019-08-22 14:30 ` Robin Murphy
2019-08-22 14:30 ` Robin Murphy
2019-07-11 15:02 ` [PATCH v2 2/4] iommu/arm-smmu: Workaround for Marvell Armada-AP806 SoC erratum #582743 Gregory CLEMENT
2019-07-11 15:02 ` Gregory CLEMENT
2019-07-11 15:02 ` Gregory CLEMENT
2019-07-11 15:02 ` [PATCH v2 3/4] dt-bindings: iommu/arm,smmu: add compatible string for Marvell Gregory CLEMENT
2019-07-11 15:02 ` [PATCH v2 3/4] dt-bindings: iommu/arm, smmu: " Gregory CLEMENT
2019-07-11 15:02 ` Gregory CLEMENT
2019-07-24 20:36 ` [PATCH v2 3/4] dt-bindings: iommu/arm,smmu: " Rob Herring
2019-07-24 20:36 ` Rob Herring
2019-07-24 20:36 ` Rob Herring
2019-07-24 20:36 ` Rob Herring
2019-08-22 14:16 ` Robin Murphy
2019-08-22 14:16 ` [PATCH v2 3/4] dt-bindings: iommu/arm, smmu: " Robin Murphy
2019-08-22 14:16 ` Robin Murphy
2019-07-11 15:02 ` [PATCH v2 4/4] arm64: dts: marvell: armada-ap806: add smmu support Gregory CLEMENT
2019-07-11 15:02 ` Gregory CLEMENT
2019-07-11 15:02 ` Gregory CLEMENT
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