[U-Boot] [PATCH v4 0/4] SiFive SPI MMC Support

[U-Boot] [PATCH v4 0/4] SiFive SPI MMC Support

[Anup Patel]

This patchset adds:
1. SiFive SPI driver
2. New MMC SPI driver based on DM_MMC and DM_SPI
3. Enables SiFive SPI driver and MMC SPI driver for SiFive Unleashed board

With this patch series, we can now load files from SD card on SiFive
Unleashed board. Many thanks to Bhargav for porting SiFive SPI driver
and updating MMC SPI driver for us.

These patches can be also found in riscv_unleashed_mmc_spi_v4 branch of:
https//github.com/avpatel/u-boot.git

Changes since v3:
- Removed PATCH2, PATCH3, and PATCH4 because these are already merged
- Added separate patch to use SPI_XFER_xyz flags in MMC_SPI driver
- Use readl/writel directly instead of sifive_spi_read/sifi_spi_write
- Use SPI_XFER_xyz flags to enable/disable chipselect
- Remove unused callback sifive_spi_cs_info()

Changes since v2:
- Minor fixes in PATCH1 which adds SiFive SPI driver
- Removed CONFIG_MMC_SPI_xyz from scripts/config_whitelist.txt
- Removed cmd/mmc_spi and all its refrences as separate patch
- Removed DM_SPI and DM_MMC from SiFive FU540 Kconfig

Changes since v1:
- Make response matching part belongs to mmc_spi_sendcmd()
- Match response to zero for SEND_STATUS (CMD13)
- Add separate patch for updating SiFive FU540 Documentation

Anup Patel (2):
  mmc: mmc_spi: Use SPI_XFER_BEGIN and SPI_XFER_END flags
  doc: sifive-fu540: Update README for SiFive SPI and MMC SPI drivers

Bhargav Shah (2):
  spi: Add SiFive SPI driver
  riscv: sifive: fu540: Enable SiFive SPI and MMC SPI drivers

 board/sifive/fu540/Kconfig |   6 +
 doc/README.sifive-fu540    |   4 +-
 drivers/mmc/mmc_spi.c      |   4 +-
 drivers/spi/Kconfig        |   8 +
 drivers/spi/Makefile       |   1 +
 drivers/spi/spi-sifive.c   | 361 +++++++++++++++++++++++++++++++++++++
 6 files changed, 380 insertions(+), 4 deletions(-)
 create mode 100644 drivers/spi/spi-sifive.c

--
2.17.1

[U-Boot] [PATCH v4 1/4] mmc: mmc_spi: Use SPI_XFER_BEGIN and SPI_XFER_END flags

[Anup Patel]

Most DM based SPI host controller drivers use SPI_XFER_BEGIN and
SPI_XFER_END flags to enable/disable slave chip select.

This patch extends MMC SPI driver to pass SPI_XFER_BEGIN flag when
MMC command is send at start and pass SPI_XFER_END flag using a
dummy transfer (of bitlen = 0) at the end of MMC command.

Suggested-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
 drivers/mmc/mmc_spi.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/mmc_spi.c b/drivers/mmc/mmc_spi.c
index f3d687ae80..350812a04b 100644
--- a/drivers/mmc/mmc_spi.c
+++ b/drivers/mmc/mmc_spi.c
@@ -84,7 +84,7 @@ static int mmc_spi_sendcmd(struct udevice *dev,
 	cmdo[4] = cmdarg >> 8;
 	cmdo[5] = cmdarg;
 	cmdo[6] = (crc7(0, &cmdo[1], 5) << 1) | 0x01;
-	ret = dm_spi_xfer(dev, sizeof(cmdo) * 8, cmdo, NULL, 0);
+	ret = dm_spi_xfer(dev, sizeof(cmdo) * 8, cmdo, NULL, SPI_XFER_BEGIN);
 	if (ret)
 		return ret;
 
@@ -360,6 +360,8 @@ static int dm_mmc_spi_request(struct udevice *dev, struct mmc_cmd *cmd,
 	}
 
 done:
+	dm_spi_xfer(dev, 0, NULL, NULL, SPI_XFER_END);
+
 	dm_spi_release_bus(dev);
 
 	return ret;
-- 
2.17.1

[U-Boot] [PATCH v4 2/4] spi: Add SiFive SPI driver

[Anup Patel]

From: Bhargav Shah <bhargavshah1988@gmail.com>

This patch adds SiFive SPI driver. The driver is 100% DM driver
and it determines input clock using clk framework.

The SiFive SPI block is found on SiFive FU540 SOC and is used to
access flash and MMC devices on SiFive Unleashed board.

This driver implementation is inspired from the Linux SiFive SPI
driver available in Linux-5.2 or higher and SiFive FSBL sources.

Signed-off-by: Bhargav Shah <bhargavshah1988@gmail.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
---
 drivers/spi/Kconfig      |   8 +
 drivers/spi/Makefile     |   1 +
 drivers/spi/spi-sifive.c | 361 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 370 insertions(+)
 create mode 100644 drivers/spi/spi-sifive.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index eb32f082fe..2712bad310 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -224,6 +224,14 @@ config SANDBOX_SPI
 		};
 	  };
 
+config SIFIVE_SPI
+	bool "SiFive SPI driver"
+	help
+	  This driver supports the SiFive SPI IP. If unsure say N.
+	  Enable the SiFive SPI controller driver.
+
+	  The SiFive SPI controller driver is found on various SiFive SoCs.
+
 config SPI_SUNXI
 	bool "Allwinner SoC SPI controllers"
 	help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 8be9a4baa2..09a9d3697e 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -49,6 +49,7 @@ obj-$(CONFIG_PL022_SPI) += pl022_spi.o
 obj-$(CONFIG_RENESAS_RPC_SPI) += renesas_rpc_spi.o
 obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o
 obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
+obj-$(CONFIG_SIFIVE_SPI) += spi-sifive.o
 obj-$(CONFIG_SPI_SUNXI) += spi-sunxi.o
 obj-$(CONFIG_SH_SPI) += sh_spi.o
 obj-$(CONFIG_SH_QSPI) += sh_qspi.o
diff --git a/drivers/spi/spi-sifive.c b/drivers/spi/spi-sifive.c
new file mode 100644
index 0000000000..78eed78650
--- /dev/null
+++ b/drivers/spi/spi-sifive.c
@@ -0,0 +1,361 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 SiFive, Inc.
+ * Copyright 2019 Bhargav Shah <bhargavshah1988@gmail.com>
+ *
+ * SiFive SPI controller driver (master mode only)
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <malloc.h>
+#include <spi.h>
+#include <asm/io.h>
+#include <linux/log2.h>
+#include <clk.h>
+
+#define SIFIVE_SPI_MAX_CS		32
+
+#define SIFIVE_SPI_DEFAULT_DEPTH	8
+#define SIFIVE_SPI_DEFAULT_BITS		8
+
+/* register offsets */
+#define SIFIVE_SPI_REG_SCKDIV            0x00 /* Serial clock divisor */
+#define SIFIVE_SPI_REG_SCKMODE           0x04 /* Serial clock mode */
+#define SIFIVE_SPI_REG_CSID              0x10 /* Chip select ID */
+#define SIFIVE_SPI_REG_CSDEF             0x14 /* Chip select default */
+#define SIFIVE_SPI_REG_CSMODE            0x18 /* Chip select mode */
+#define SIFIVE_SPI_REG_DELAY0            0x28 /* Delay control 0 */
+#define SIFIVE_SPI_REG_DELAY1            0x2c /* Delay control 1 */
+#define SIFIVE_SPI_REG_FMT               0x40 /* Frame format */
+#define SIFIVE_SPI_REG_TXDATA            0x48 /* Tx FIFO data */
+#define SIFIVE_SPI_REG_RXDATA            0x4c /* Rx FIFO data */
+#define SIFIVE_SPI_REG_TXMARK            0x50 /* Tx FIFO watermark */
+#define SIFIVE_SPI_REG_RXMARK            0x54 /* Rx FIFO watermark */
+#define SIFIVE_SPI_REG_FCTRL             0x60 /* SPI flash interface control */
+#define SIFIVE_SPI_REG_FFMT              0x64 /* SPI flash instruction format */
+#define SIFIVE_SPI_REG_IE                0x70 /* Interrupt Enable Register */
+#define SIFIVE_SPI_REG_IP                0x74 /* Interrupt Pendings Register */
+
+/* sckdiv bits */
+#define SIFIVE_SPI_SCKDIV_DIV_MASK       0xfffU
+
+/* sckmode bits */
+#define SIFIVE_SPI_SCKMODE_PHA           BIT(0)
+#define SIFIVE_SPI_SCKMODE_POL           BIT(1)
+#define SIFIVE_SPI_SCKMODE_MODE_MASK     (SIFIVE_SPI_SCKMODE_PHA | \
+					  SIFIVE_SPI_SCKMODE_POL)
+
+/* csmode bits */
+#define SIFIVE_SPI_CSMODE_MODE_AUTO      0U
+#define SIFIVE_SPI_CSMODE_MODE_HOLD      2U
+#define SIFIVE_SPI_CSMODE_MODE_OFF       3U
+
+/* delay0 bits */
+#define SIFIVE_SPI_DELAY0_CSSCK(x)       ((u32)(x))
+#define SIFIVE_SPI_DELAY0_CSSCK_MASK     0xffU
+#define SIFIVE_SPI_DELAY0_SCKCS(x)       ((u32)(x) << 16)
+#define SIFIVE_SPI_DELAY0_SCKCS_MASK     (0xffU << 16)
+
+/* delay1 bits */
+#define SIFIVE_SPI_DELAY1_INTERCS(x)     ((u32)(x))
+#define SIFIVE_SPI_DELAY1_INTERCS_MASK   0xffU
+#define SIFIVE_SPI_DELAY1_INTERXFR(x)    ((u32)(x) << 16)
+#define SIFIVE_SPI_DELAY1_INTERXFR_MASK  (0xffU << 16)
+
+/* fmt bits */
+#define SIFIVE_SPI_FMT_PROTO_SINGLE      0U
+#define SIFIVE_SPI_FMT_PROTO_DUAL        1U
+#define SIFIVE_SPI_FMT_PROTO_QUAD        2U
+#define SIFIVE_SPI_FMT_PROTO_MASK        3U
+#define SIFIVE_SPI_FMT_ENDIAN            BIT(2)
+#define SIFIVE_SPI_FMT_DIR               BIT(3)
+#define SIFIVE_SPI_FMT_LEN(x)            ((u32)(x) << 16)
+#define SIFIVE_SPI_FMT_LEN_MASK          (0xfU << 16)
+
+/* txdata bits */
+#define SIFIVE_SPI_TXDATA_DATA_MASK      0xffU
+#define SIFIVE_SPI_TXDATA_FULL           BIT(31)
+
+/* rxdata bits */
+#define SIFIVE_SPI_RXDATA_DATA_MASK      0xffU
+#define SIFIVE_SPI_RXDATA_EMPTY          BIT(31)
+
+/* ie and ip bits */
+#define SIFIVE_SPI_IP_TXWM               BIT(0)
+#define SIFIVE_SPI_IP_RXWM               BIT(1)
+
+struct sifive_spi {
+	void		*regs;		/* base address of the registers */
+	u32		fifo_depth;
+	u32		bits_per_word;
+	u32		cs_inactive;	/* Level of the CS pins when inactive*/
+	u32		freq;
+	u32		num_cs;
+};
+
+static void sifive_spi_prep_device(struct sifive_spi *spi,
+				   struct dm_spi_slave_platdata *slave)
+{
+	/* Update the chip select polarity */
+	if (slave->mode & SPI_CS_HIGH)
+		spi->cs_inactive &= ~BIT(slave->cs);
+	else
+		spi->cs_inactive |= BIT(slave->cs);
+	writel(spi->cs_inactive, spi->regs + SIFIVE_SPI_REG_CSDEF);
+
+	/* Select the correct device */
+	writel(slave->cs, spi->regs + SIFIVE_SPI_REG_CSID);
+}
+
+static int sifive_spi_set_cs(struct sifive_spi *spi,
+			     struct dm_spi_slave_platdata *slave)
+{
+	u32 cs_mode = SIFIVE_SPI_CSMODE_MODE_HOLD;
+
+	if (slave->cs > spi->num_cs)
+		return -EINVAL;
+
+	if (slave->mode & SPI_CS_HIGH)
+		cs_mode = SIFIVE_SPI_CSMODE_MODE_AUTO;
+
+	writel(cs_mode, spi->regs + SIFIVE_SPI_REG_CSMODE);
+
+	return 0;
+}
+
+static void sifive_spi_clear_cs(struct sifive_spi *spi)
+{
+	writel(SIFIVE_SPI_CSMODE_MODE_AUTO, spi->regs + SIFIVE_SPI_REG_CSMODE);
+}
+
+static void sifive_spi_prep_transfer(struct sifive_spi *spi,
+				     bool is_rx_xfer,
+				     struct dm_spi_slave_platdata *slave)
+{
+	u32 cr;
+
+	/* Modify the SPI protocol mode */
+	cr = readl(spi->regs + SIFIVE_SPI_REG_FMT);
+
+	/* Bits per word ? */
+	cr &= ~SIFIVE_SPI_FMT_LEN_MASK;
+	cr |= SIFIVE_SPI_FMT_LEN(spi->bits_per_word);
+
+	/* LSB first? */
+	cr &= ~SIFIVE_SPI_FMT_ENDIAN;
+	if (slave->mode & SPI_LSB_FIRST)
+		cr |= SIFIVE_SPI_FMT_ENDIAN;
+
+	/* Number of wires ? */
+	cr &= ~SIFIVE_SPI_FMT_PROTO_MASK;
+	if ((slave->mode & SPI_TX_QUAD) || (slave->mode & SPI_RX_QUAD))
+		cr |= SIFIVE_SPI_FMT_PROTO_QUAD;
+	else if ((slave->mode & SPI_TX_DUAL) || (slave->mode & SPI_RX_DUAL))
+		cr |= SIFIVE_SPI_FMT_PROTO_DUAL;
+	else
+		cr |= SIFIVE_SPI_FMT_PROTO_SINGLE;
+
+	/* SPI direction in/out ? */
+	cr &= ~SIFIVE_SPI_FMT_DIR;
+	if (!is_rx_xfer)
+		cr |= SIFIVE_SPI_FMT_DIR;
+
+	writel(cr, spi->regs + SIFIVE_SPI_REG_FMT);
+}
+
+static void sifive_spi_rx(struct sifive_spi *spi, u8 *rx_ptr)
+{
+	u32 data;
+
+	do {
+		data = readl(spi->regs + SIFIVE_SPI_REG_RXDATA);
+	} while (data & SIFIVE_SPI_RXDATA_EMPTY);
+
+	if (rx_ptr)
+		*rx_ptr = data & SIFIVE_SPI_RXDATA_DATA_MASK;
+}
+
+static void sifive_spi_tx(struct sifive_spi *spi, const u8 *tx_ptr)
+{
+	u32 data;
+	u8 tx_data = (tx_ptr) ? *tx_ptr & SIFIVE_SPI_TXDATA_DATA_MASK :
+				SIFIVE_SPI_TXDATA_DATA_MASK;
+
+	do {
+		data = readl(spi->regs + SIFIVE_SPI_REG_TXDATA);
+	} while (data & SIFIVE_SPI_TXDATA_FULL);
+
+	writel(tx_data, spi->regs + SIFIVE_SPI_REG_TXDATA);
+}
+
+static int sifive_spi_xfer(struct udevice *dev, unsigned int bitlen,
+			   const void *dout, void *din, unsigned long flags)
+{
+	struct udevice *bus = dev->parent;
+	struct sifive_spi *spi = dev_get_priv(bus);
+	struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
+	const unsigned char *tx_ptr = dout;
+	u8 *rx_ptr = din;
+	u32 remaining_len;
+	int ret;
+
+	if (flags & SPI_XFER_BEGIN) {
+		sifive_spi_prep_device(spi, slave);
+
+		ret = sifive_spi_set_cs(spi, slave);
+		if (ret)
+			return ret;
+	}
+
+	sifive_spi_prep_transfer(spi, true, slave);
+
+	remaining_len = bitlen / 8;
+
+	while (remaining_len) {
+		int n_words, tx_words, rx_words;
+
+		n_words = min(remaining_len, spi->fifo_depth);
+
+		/* Enqueue n_words for transmission */
+		if (tx_ptr) {
+			for (tx_words = 0; tx_words < n_words; ++tx_words) {
+				sifive_spi_tx(spi, tx_ptr);
+				sifive_spi_rx(spi, NULL);
+				tx_ptr++;
+			}
+		}
+
+		/* Read out all the data from the RX FIFO */
+		if (rx_ptr) {
+			for (rx_words = 0; rx_words < n_words; ++rx_words) {
+				sifive_spi_tx(spi, NULL);
+				sifive_spi_rx(spi, rx_ptr);
+				rx_ptr++;
+			}
+		}
+
+		remaining_len -= n_words;
+	}
+
+	if (flags & SPI_XFER_END)
+		sifive_spi_clear_cs(spi);
+
+	return 0;
+}
+
+static int sifive_spi_set_speed(struct udevice *bus, uint speed)
+{
+	struct sifive_spi *spi = dev_get_priv(bus);
+	u32 scale;
+
+	if (speed > spi->freq)
+		speed = spi->freq;
+
+	/* Cofigure max speed */
+	scale = (DIV_ROUND_UP(spi->freq >> 1, speed) - 1)
+					& SIFIVE_SPI_SCKDIV_DIV_MASK;
+	writel(scale, spi->regs + SIFIVE_SPI_REG_SCKDIV);
+
+	return 0;
+}
+
+static int sifive_spi_set_mode(struct udevice *bus, uint mode)
+{
+	struct sifive_spi *spi = dev_get_priv(bus);
+	u32 cr;
+
+	/* Switch clock mode bits */
+	cr = readl(spi->regs + SIFIVE_SPI_REG_SCKMODE) &
+				~SIFIVE_SPI_SCKMODE_MODE_MASK;
+	if (mode & SPI_CPHA)
+		cr |= SIFIVE_SPI_SCKMODE_PHA;
+	if (mode & SPI_CPOL)
+		cr |= SIFIVE_SPI_SCKMODE_POL;
+
+	writel(cr, spi->regs + SIFIVE_SPI_REG_SCKMODE);
+
+	return 0;
+}
+
+static void sifive_spi_init_hw(struct sifive_spi *spi)
+{
+	u32 cs_bits;
+
+	/* probe the number of CS lines */
+	spi->cs_inactive = readl(spi->regs + SIFIVE_SPI_REG_CSDEF);
+	writel(0xffffffffU, spi->regs + SIFIVE_SPI_REG_CSDEF);
+	cs_bits = readl(spi->regs + SIFIVE_SPI_REG_CSDEF);
+	writel(spi->cs_inactive, spi->regs + SIFIVE_SPI_REG_CSDEF);
+	if (!cs_bits) {
+		printf("Could not auto probe CS lines\n");
+		return;
+	}
+
+	spi->num_cs = ilog2(cs_bits) + 1;
+	if (spi->num_cs > SIFIVE_SPI_MAX_CS) {
+		printf("Invalid number of spi slaves\n");
+		return;
+	}
+
+	/* Watermark interrupts are disabled by default */
+	writel(0, spi->regs + SIFIVE_SPI_REG_IE);
+
+	/* Set CS/SCK Delays and Inactive Time to defaults */
+	writel(SIFIVE_SPI_DELAY0_CSSCK(1) | SIFIVE_SPI_DELAY0_SCKCS(1),
+	       spi->regs + SIFIVE_SPI_REG_DELAY0);
+	writel(SIFIVE_SPI_DELAY1_INTERCS(1) | SIFIVE_SPI_DELAY1_INTERXFR(0),
+	       spi->regs + SIFIVE_SPI_REG_DELAY1);
+
+	/* Exit specialized memory-mapped SPI flash mode */
+	writel(0, spi->regs + SIFIVE_SPI_REG_FCTRL);
+}
+
+static int sifive_spi_probe(struct udevice *bus)
+{
+	struct sifive_spi *spi = dev_get_priv(bus);
+	struct clk clkdev;
+	int ret;
+
+	spi->regs = (void *)(ulong)dev_remap_addr(bus);
+	if (!spi->regs)
+		return -ENODEV;
+
+	spi->fifo_depth = dev_read_u32_default(bus,
+					       "sifive,fifo-depth",
+					       SIFIVE_SPI_DEFAULT_DEPTH);
+
+	spi->bits_per_word = dev_read_u32_default(bus,
+						  "sifive,max-bits-per-word",
+						  SIFIVE_SPI_DEFAULT_BITS);
+
+	ret = clk_get_by_index(bus, 0, &clkdev);
+	if (ret)
+		return ret;
+	spi->freq = clk_get_rate(&clkdev);
+
+	/* init the sifive spi hw */
+	sifive_spi_init_hw(spi);
+
+	return 0;
+}
+
+static const struct dm_spi_ops sifive_spi_ops = {
+	.xfer		= sifive_spi_xfer,
+	.set_speed	= sifive_spi_set_speed,
+	.set_mode	= sifive_spi_set_mode,
+};
+
+static const struct udevice_id sifive_spi_ids[] = {
+	{ .compatible = "sifive,spi0" },
+	{ }
+};
+
+U_BOOT_DRIVER(sifive_spi) = {
+	.name	= "sifive_spi",
+	.id	= UCLASS_SPI,
+	.of_match = sifive_spi_ids,
+	.ops	= &sifive_spi_ops,
+	.priv_auto_alloc_size = sizeof(struct sifive_spi),
+	.probe	= sifive_spi_probe,
+};
-- 
2.17.1

[U-Boot] [PATCH v4 3/4] riscv: sifive: fu540: Enable SiFive SPI and MMC SPI drivers

[Anup Patel]

From: Bhargav Shah <bhargavshah1988@gmail.com>

This patch enables SiFive SPI and MMC SPI drivers for the
SiFive Unleashed board.

Signed-off-by: Bhargav Shah <bhargavshah1988@gmail.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
---
 board/sifive/fu540/Kconfig | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
index f46437901d..662c379b1b 100644
--- a/board/sifive/fu540/Kconfig
+++ b/board/sifive/fu540/Kconfig
@@ -38,6 +38,12 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	imply PHY_LIB
 	imply PHY_MSCC
 	imply SIFIVE_SERIAL
+	imply SPI
+	imply SIFIVE_SPI
+	imply MMC
+	imply MMC_SPI
+	imply MMC_BROKEN_CD
+	imply CMD_MMC
 	imply SMP
 
 endif
-- 
2.17.1

[U-Boot] [PATCH v4 4/4] doc: sifive-fu540: Update README for SiFive SPI and MMC SPI drivers

[Anup Patel]

This patch removes SiFive SPI driver and MMC SPI drive from the TODO
list in SiFive FU540 README.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
---
 doc/README.sifive-fu540 | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/doc/README.sifive-fu540 b/doc/README.sifive-fu540
index 33e03dc861..944ba1c8a0 100644
--- a/doc/README.sifive-fu540
+++ b/doc/README.sifive-fu540
@@ -13,9 +13,7 @@ The support for following drivers are already enabled:
 3. Cadence MACB ethernet driver for networking support.
 
 TODO:
-1. SPI host driver is still missing.
-2. SPI MMC driver does not compile and needs a re-write using U-Boot DM.
-2. U-Boot expects the serial console device entry to be present under /chosen
+1. U-Boot expects the serial console device entry to be present under /chosen
    DT node. Example:
    chosen {
         stdout-path = "/soc/serial at 10010000:115200";
-- 
2.17.1

[U-Boot] [PATCH v4 1/4] mmc: mmc_spi: Use SPI_XFER_BEGIN and SPI_XFER_END flags

[Jagan Teki]

On Tue, Jul 16, 2019 at 9:52 AM Anup Patel <Anup.Patel@wdc.com> wrote:
>
> Most DM based SPI host controller drivers use SPI_XFER_BEGIN and
> SPI_XFER_END flags to enable/disable slave chip select.
>
> This patch extends MMC SPI driver to pass SPI_XFER_BEGIN flag when
> MMC command is send at start and pass SPI_XFER_END flag using a
> dummy transfer (of bitlen = 0) at the end of MMC command.
>
> Suggested-by: Jagan Teki <jagan@amarulasolutions.com>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
>  drivers/mmc/mmc_spi.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/mmc_spi.c b/drivers/mmc/mmc_spi.c
> index f3d687ae80..350812a04b 100644
> --- a/drivers/mmc/mmc_spi.c
> +++ b/drivers/mmc/mmc_spi.c
> @@ -84,7 +84,7 @@ static int mmc_spi_sendcmd(struct udevice *dev,
>         cmdo[4] = cmdarg >> 8;
>         cmdo[5] = cmdarg;
>         cmdo[6] = (crc7(0, &cmdo[1], 5) << 1) | 0x01;
> -       ret = dm_spi_xfer(dev, sizeof(cmdo) * 8, cmdo, NULL, 0);
> +       ret = dm_spi_xfer(dev, sizeof(cmdo) * 8, cmdo, NULL, SPI_XFER_BEGIN);
>         if (ret)
>                 return ret;
>
> @@ -360,6 +360,8 @@ static int dm_mmc_spi_request(struct udevice *dev, struct mmc_cmd *cmd,
>         }
>
>  done:
> +       dm_spi_xfer(dev, 0, NULL, NULL, SPI_XFER_END);
> +

Look like this driver has several dm_spi_xfer in their won sequence,
have you tried of sending command and buf in same spi_xfer call so
dout and din can be NULL based on the read and write? if ie possible
we can manage the transfer flags in single sub call based on data_len
like drivers/mtd/spi/sf.c does.

[U-Boot] [PATCH v4 1/4] mmc: mmc_spi: Use SPI_XFER_BEGIN and SPI_XFER_END flags

[Anup Patel]

On Tue, Jul 16, 2019 at 1:05 PM Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> On Tue, Jul 16, 2019 at 9:52 AM Anup Patel <Anup.Patel@wdc.com> wrote:
> >
> > Most DM based SPI host controller drivers use SPI_XFER_BEGIN and
> > SPI_XFER_END flags to enable/disable slave chip select.
> >
> > This patch extends MMC SPI driver to pass SPI_XFER_BEGIN flag when
> > MMC command is send at start and pass SPI_XFER_END flag using a
> > dummy transfer (of bitlen = 0) at the end of MMC command.
> >
> > Suggested-by: Jagan Teki <jagan@amarulasolutions.com>
> > Signed-off-by: Anup Patel <anup.patel@wdc.com>
> > ---
> >  drivers/mmc/mmc_spi.c | 4 +++-
> >  1 file changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/mmc/mmc_spi.c b/drivers/mmc/mmc_spi.c
> > index f3d687ae80..350812a04b 100644
> > --- a/drivers/mmc/mmc_spi.c
> > +++ b/drivers/mmc/mmc_spi.c
> > @@ -84,7 +84,7 @@ static int mmc_spi_sendcmd(struct udevice *dev,
> >         cmdo[4] = cmdarg >> 8;
> >         cmdo[5] = cmdarg;
> >         cmdo[6] = (crc7(0, &cmdo[1], 5) << 1) | 0x01;
> > -       ret = dm_spi_xfer(dev, sizeof(cmdo) * 8, cmdo, NULL, 0);
> > +       ret = dm_spi_xfer(dev, sizeof(cmdo) * 8, cmdo, NULL, SPI_XFER_BEGIN);
> >         if (ret)
> >                 return ret;
> >
> > @@ -360,6 +360,8 @@ static int dm_mmc_spi_request(struct udevice *dev, struct mmc_cmd *cmd,
> >         }
> >
> >  done:
> > +       dm_spi_xfer(dev, 0, NULL, NULL, SPI_XFER_END);
> > +
>
> Look like this driver has several dm_spi_xfer in their won sequence,
> have you tried of sending command and buf in same spi_xfer call so
> dout and din can be NULL based on the read and write? if ie possible
> we can manage the transfer flags in single sub call based on data_len
> like drivers/mtd/spi/sf.c does.

MMC SPI protocol is very different compared to SPI serial flash.

We have to poll for expected byte pattern when waiting for transfer/command
to complete. We don't know in-advance how many bytes we will have to read.

Regards,
Anup

[U-Boot] [PATCH v4 1/4] mmc: mmc_spi: Use SPI_XFER_BEGIN and SPI_XFER_END flags

[Jagan Teki]

On Tue, Jul 16, 2019 at 1:38 PM Anup Patel <anup@brainfault.org> wrote:
>
> On Tue, Jul 16, 2019 at 1:05 PM Jagan Teki <jagan@amarulasolutions.com> wrote:
> >
> > On Tue, Jul 16, 2019 at 9:52 AM Anup Patel <Anup.Patel@wdc.com> wrote:
> > >
> > > Most DM based SPI host controller drivers use SPI_XFER_BEGIN and
> > > SPI_XFER_END flags to enable/disable slave chip select.
> > >
> > > This patch extends MMC SPI driver to pass SPI_XFER_BEGIN flag when
> > > MMC command is send at start and pass SPI_XFER_END flag using a
> > > dummy transfer (of bitlen = 0) at the end of MMC command.
> > >
> > > Suggested-by: Jagan Teki <jagan@amarulasolutions.com>
> > > Signed-off-by: Anup Patel <anup.patel@wdc.com>
> > > ---
> > >  drivers/mmc/mmc_spi.c | 4 +++-
> > >  1 file changed, 3 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/mmc/mmc_spi.c b/drivers/mmc/mmc_spi.c
> > > index f3d687ae80..350812a04b 100644
> > > --- a/drivers/mmc/mmc_spi.c
> > > +++ b/drivers/mmc/mmc_spi.c
> > > @@ -84,7 +84,7 @@ static int mmc_spi_sendcmd(struct udevice *dev,
> > >         cmdo[4] = cmdarg >> 8;
> > >         cmdo[5] = cmdarg;
> > >         cmdo[6] = (crc7(0, &cmdo[1], 5) << 1) | 0x01;
> > > -       ret = dm_spi_xfer(dev, sizeof(cmdo) * 8, cmdo, NULL, 0);
> > > +       ret = dm_spi_xfer(dev, sizeof(cmdo) * 8, cmdo, NULL, SPI_XFER_BEGIN);
> > >         if (ret)
> > >                 return ret;
> > >
> > > @@ -360,6 +360,8 @@ static int dm_mmc_spi_request(struct udevice *dev, struct mmc_cmd *cmd,
> > >         }
> > >
> > >  done:
> > > +       dm_spi_xfer(dev, 0, NULL, NULL, SPI_XFER_END);
> > > +
> >
> > Look like this driver has several dm_spi_xfer in their won sequence,
> > have you tried of sending command and buf in same spi_xfer call so
> > dout and din can be NULL based on the read and write? if ie possible
> > we can manage the transfer flags in single sub call based on data_len
> > like drivers/mtd/spi/sf.c does.
>
> MMC SPI protocol is very different compared to SPI serial flash.
>
> We have to poll for expected byte pattern when waiting for transfer/command
> to complete. We don't know in-advance how many bytes we will have to read.

Yes, so we begin the transfer and end if successful is it? apart from
this we also need to provide claim and release calls from here,
so-that the sifive spi can handle them accordingly otherwise using
sifive spi may not work with flash.

[U-Boot] [PATCH v4 1/4] mmc: mmc_spi: Use SPI_XFER_BEGIN and SPI_XFER_END flags

[Anup Patel]

On Tue, Jul 16, 2019 at 1:56 PM Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> On Tue, Jul 16, 2019 at 1:38 PM Anup Patel <anup@brainfault.org> wrote:
> >
> > On Tue, Jul 16, 2019 at 1:05 PM Jagan Teki <jagan@amarulasolutions.com> wrote:
> > >
> > > On Tue, Jul 16, 2019 at 9:52 AM Anup Patel <Anup.Patel@wdc.com> wrote:
> > > >
> > > > Most DM based SPI host controller drivers use SPI_XFER_BEGIN and
> > > > SPI_XFER_END flags to enable/disable slave chip select.
> > > >
> > > > This patch extends MMC SPI driver to pass SPI_XFER_BEGIN flag when
> > > > MMC command is send at start and pass SPI_XFER_END flag using a
> > > > dummy transfer (of bitlen = 0) at the end of MMC command.
> > > >
> > > > Suggested-by: Jagan Teki <jagan@amarulasolutions.com>
> > > > Signed-off-by: Anup Patel <anup.patel@wdc.com>
> > > > ---
> > > >  drivers/mmc/mmc_spi.c | 4 +++-
> > > >  1 file changed, 3 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/mmc/mmc_spi.c b/drivers/mmc/mmc_spi.c
> > > > index f3d687ae80..350812a04b 100644
> > > > --- a/drivers/mmc/mmc_spi.c
> > > > +++ b/drivers/mmc/mmc_spi.c
> > > > @@ -84,7 +84,7 @@ static int mmc_spi_sendcmd(struct udevice *dev,
> > > >         cmdo[4] = cmdarg >> 8;
> > > >         cmdo[5] = cmdarg;
> > > >         cmdo[6] = (crc7(0, &cmdo[1], 5) << 1) | 0x01;
> > > > -       ret = dm_spi_xfer(dev, sizeof(cmdo) * 8, cmdo, NULL, 0);
> > > > +       ret = dm_spi_xfer(dev, sizeof(cmdo) * 8, cmdo, NULL, SPI_XFER_BEGIN);
> > > >         if (ret)
> > > >                 return ret;
> > > >
> > > > @@ -360,6 +360,8 @@ static int dm_mmc_spi_request(struct udevice *dev, struct mmc_cmd *cmd,
> > > >         }
> > > >
> > > >  done:
> > > > +       dm_spi_xfer(dev, 0, NULL, NULL, SPI_XFER_END);
> > > > +
> > >
> > > Look like this driver has several dm_spi_xfer in their won sequence,
> > > have you tried of sending command and buf in same spi_xfer call so
> > > dout and din can be NULL based on the read and write? if ie possible
> > > we can manage the transfer flags in single sub call based on data_len
> > > like drivers/mtd/spi/sf.c does.
> >
> > MMC SPI protocol is very different compared to SPI serial flash.
> >
> > We have to poll for expected byte pattern when waiting for transfer/command
> > to complete. We don't know in-advance how many bytes we will have to read.
>
> Yes, so we begin the transfer and end if successful is it? apart from
> this we also need to provide claim and release calls from here,
> so-that the sifive spi can handle them accordingly otherwise using
> sifive spi may not work with flash.

The claim and release functions are already called at beginning and
end of dm_mmc_spi_request() respectively.

[U-Boot] [PATCH v4 1/4] mmc: mmc_spi: Use SPI_XFER_BEGIN and SPI_XFER_END flags

[Jagan Teki]

On Tue, Jul 16, 2019 at 2:22 PM Anup Patel <anup@brainfault.org> wrote:
>
> On Tue, Jul 16, 2019 at 1:56 PM Jagan Teki <jagan@amarulasolutions.com> wrote:
> >
> > On Tue, Jul 16, 2019 at 1:38 PM Anup Patel <anup@brainfault.org> wrote:
> > >
> > > On Tue, Jul 16, 2019 at 1:05 PM Jagan Teki <jagan@amarulasolutions.com> wrote:
> > > >
> > > > On Tue, Jul 16, 2019 at 9:52 AM Anup Patel <Anup.Patel@wdc.com> wrote:
> > > > >
> > > > > Most DM based SPI host controller drivers use SPI_XFER_BEGIN and
> > > > > SPI_XFER_END flags to enable/disable slave chip select.
> > > > >
> > > > > This patch extends MMC SPI driver to pass SPI_XFER_BEGIN flag when
> > > > > MMC command is send at start and pass SPI_XFER_END flag using a
> > > > > dummy transfer (of bitlen = 0) at the end of MMC command.
> > > > >
> > > > > Suggested-by: Jagan Teki <jagan@amarulasolutions.com>
> > > > > Signed-off-by: Anup Patel <anup.patel@wdc.com>
> > > > > ---
> > > > >  drivers/mmc/mmc_spi.c | 4 +++-
> > > > >  1 file changed, 3 insertions(+), 1 deletion(-)
> > > > >
> > > > > diff --git a/drivers/mmc/mmc_spi.c b/drivers/mmc/mmc_spi.c
> > > > > index f3d687ae80..350812a04b 100644
> > > > > --- a/drivers/mmc/mmc_spi.c
> > > > > +++ b/drivers/mmc/mmc_spi.c
> > > > > @@ -84,7 +84,7 @@ static int mmc_spi_sendcmd(struct udevice *dev,
> > > > >         cmdo[4] = cmdarg >> 8;
> > > > >         cmdo[5] = cmdarg;
> > > > >         cmdo[6] = (crc7(0, &cmdo[1], 5) << 1) | 0x01;
> > > > > -       ret = dm_spi_xfer(dev, sizeof(cmdo) * 8, cmdo, NULL, 0);
> > > > > +       ret = dm_spi_xfer(dev, sizeof(cmdo) * 8, cmdo, NULL, SPI_XFER_BEGIN);
> > > > >         if (ret)
> > > > >                 return ret;
> > > > >
> > > > > @@ -360,6 +360,8 @@ static int dm_mmc_spi_request(struct udevice *dev, struct mmc_cmd *cmd,
> > > > >         }
> > > > >
> > > > >  done:
> > > > > +       dm_spi_xfer(dev, 0, NULL, NULL, SPI_XFER_END);
> > > > > +
> > > >
> > > > Look like this driver has several dm_spi_xfer in their won sequence,
> > > > have you tried of sending command and buf in same spi_xfer call so
> > > > dout and din can be NULL based on the read and write? if ie possible
> > > > we can manage the transfer flags in single sub call based on data_len
> > > > like drivers/mtd/spi/sf.c does.
> > >
> > > MMC SPI protocol is very different compared to SPI serial flash.
> > >
> > > We have to poll for expected byte pattern when waiting for transfer/command
> > > to complete. We don't know in-advance how many bytes we will have to read.
> >
> > Yes, so we begin the transfer and end if successful is it? apart from
> > this we also need to provide claim and release calls from here,
> > so-that the sifive spi can handle them accordingly otherwise using
> > sifive spi may not work with flash.
>
> The claim and release functions are already called at beginning and
> end of dm_mmc_spi_request() respectively.

I'm saying from spi driver, since we don't have dedicated bus enable
bit the driver can make use of cs handling. so the claim can return
always 0 in this case.