* [PATCH] drm/i915/ehl: Add support for DPLL4 (v10)
@ 2019-07-03 23:03 Vivek Kasireddy
2019-07-03 23:50 ` ✓ Fi.CI.BAT: success for " Patchwork
` (5 more replies)
0 siblings, 6 replies; 12+ messages in thread
From: Vivek Kasireddy @ 2019-07-03 23:03 UTC (permalink / raw)
To: intel-gfx
This patch adds support for DPLL4 on EHL that include the
following restrictions:
- DPLL4 cannot be used with DDIA (combo port A internal eDP usage).
DPLL4 can be used with other DDIs, including DDID
(combo port A external usage).
- DPLL4 cannot be enabled when DC5 or DC6 are enabled.
- The DPLL4 enable, lock, power enabled, and power state are connected
to the MGPLL1_ENABLE register.
v2: (suggestions from Bob Paauwe)
- Rework ehl_get_dpll() function to call intel_find_shared_dpll() and
iterate twice: once for Combo plls and once for MG plls.
- Use MG pll funcs for DPLL4 instead of creating new ones and modify
mg_pll_enable to include the restrictions for EHL.
v3: Fix compilation error
v4: (suggestions from Lucas and Ville)
- Treat DPLL4 as a combo phy PLL and not as MG PLL
- Disable DC states when this DPLL is being enabled
- Reuse icl_get_dpll instead of creating a separate one for EHL
v5: (suggestion from Ville)
- Refcount the DC OFF power domains during the enabling and disabling
of this DPLL.
v6: rebase
v7: (suggestion from Imre)
- Add a new power domain instead of iterating over the domains
assoicated with DC OFF power well.
v8: (Ville and Imre)
- Rename POWER_DOMAIN_DPLL4 TO POWER_DOMAIN_DPLL_DC_OFF
- Grab a reference in intel_modeset_setup_hw_state() if this
DPLL was already enabled perhaps by BIOS.
- Check for the port type instead of the encoder
v9: (Ville)
- Move the block of code that grabs a reference to the power domain
POWER_DOMAIN_DPLL_DC_OFF to intel_modeset_readout_hw_state() to ensure
that there is a reference present before this DPLL might get disabled.
v10: rebase
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Vivek Kasireddy <vivek.kasireddy@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 7 +++
.../drm/i915/display/intel_display_power.c | 3 ++
.../drm/i915/display/intel_display_power.h | 1 +
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 47 +++++++++++++++++--
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 6 +++
5 files changed, 60 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 919f5ac844c8..557462208462 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -16653,6 +16653,13 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
pll->on = pll->info->funcs->get_hw_state(dev_priv, pll,
&pll->state.hw_state);
+
+ if (IS_ELKHARTLAKE(dev_priv) && pll->on &&
+ pll->info->id == DPLL_ID_EHL_DPLL4) {
+ pll->wakeref = intel_display_power_get(dev_priv,
+ POWER_DOMAIN_DPLL_DC_OFF);
+ }
+
pll->state.crtc_mask = 0;
for_each_intel_crtc(dev, crtc) {
struct intel_crtc_state *crtc_state =
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index c19b958461ca..7437fc71d289 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -118,6 +118,8 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "MODESET";
case POWER_DOMAIN_GT_IRQ:
return "GT_IRQ";
+ case POWER_DOMAIN_DPLL_DC_OFF:
+ return "DPLL_DC_OFF";
default:
MISSING_CASE(domain);
return "?";
@@ -2455,6 +2457,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
ICL_PW_2_POWER_DOMAINS | \
BIT_ULL(POWER_DOMAIN_MODESET) | \
BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_DPLL_DC_OFF) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define ICL_DDI_IO_A_POWER_DOMAINS ( \
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index ff57b0a7fe59..8f43f7051a16 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -59,6 +59,7 @@ enum intel_display_power_domain {
POWER_DOMAIN_GMBUS,
POWER_DOMAIN_MODESET,
POWER_DOMAIN_GT_IRQ,
+ POWER_DOMAIN_DPLL_DC_OFF,
POWER_DOMAIN_INIT,
POWER_DOMAIN_NUM,
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index f953971e7c3b..67cfe836286e 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2905,6 +2905,9 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state,
intel_atomic_get_new_crtc_state(state, crtc);
struct icl_port_dpll *port_dpll =
&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum port port = encoder->port;
+ bool has_dpll4 = false;
if (!icl_calc_dpll_state(crtc_state, encoder, &port_dpll->hw_state)) {
DRM_DEBUG_KMS("Could not calculate combo PHY PLL state.\n");
@@ -2912,10 +2915,14 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state,
return false;
}
+ if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A)
+ has_dpll4 = true;
+
port_dpll->pll = intel_find_shared_dpll(state, crtc,
&port_dpll->hw_state,
DPLL_ID_ICL_DPLL0,
- DPLL_ID_ICL_DPLL1);
+ has_dpll4 ? DPLL_ID_EHL_DPLL4
+ : DPLL_ID_ICL_DPLL1);
if (!port_dpll->pll) {
DRM_DEBUG_KMS("No combo PHY PLL found for port %c\n",
port_name(encoder->port));
@@ -3119,8 +3126,14 @@ static bool combo_pll_get_hw_state(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *hw_state)
{
- return icl_pll_get_hw_state(dev_priv, pll, hw_state,
- CNL_DPLL_ENABLE(pll->info->id));
+ i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
+
+ if (IS_ELKHARTLAKE(dev_priv) &&
+ pll->info->id == DPLL_ID_EHL_DPLL4) {
+ enable_reg = MG_PLL_ENABLE(0);
+ }
+
+ return icl_pll_get_hw_state(dev_priv, pll, hw_state, enable_reg);
}
static bool tbt_pll_get_hw_state(struct drm_i915_private *dev_priv,
@@ -3231,6 +3244,19 @@ static void combo_pll_enable(struct drm_i915_private *dev_priv,
{
i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
+ if (IS_ELKHARTLAKE(dev_priv) &&
+ pll->info->id == DPLL_ID_EHL_DPLL4) {
+ enable_reg = MG_PLL_ENABLE(0);
+
+ /*
+ * We need to disable DC states when this DPLL is enabled.
+ * This can be done by taking a reference on DPLL4 power
+ * domain.
+ */
+ pll->wakeref = intel_display_power_get(dev_priv,
+ POWER_DOMAIN_DPLL_DC_OFF);
+ }
+
icl_pll_power_enable(dev_priv, pll, enable_reg);
icl_dpll_write(dev_priv, pll);
@@ -3326,7 +3352,19 @@ static void icl_pll_disable(struct drm_i915_private *dev_priv,
static void combo_pll_disable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
- icl_pll_disable(dev_priv, pll, CNL_DPLL_ENABLE(pll->info->id));
+ i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
+
+ if (IS_ELKHARTLAKE(dev_priv) &&
+ pll->info->id == DPLL_ID_EHL_DPLL4) {
+ enable_reg = MG_PLL_ENABLE(0);
+ icl_pll_disable(dev_priv, pll, enable_reg);
+
+ intel_display_power_put(dev_priv, POWER_DOMAIN_DPLL_DC_OFF,
+ pll->wakeref);
+ return;
+ }
+
+ icl_pll_disable(dev_priv, pll, enable_reg);
}
static void tbt_pll_disable(struct drm_i915_private *dev_priv,
@@ -3406,6 +3444,7 @@ static const struct intel_dpll_mgr icl_pll_mgr = {
static const struct dpll_info ehl_plls[] = {
{ "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
{ "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
+ { "DPLL 4", &combo_pll_funcs, DPLL_ID_EHL_DPLL4, 0 },
{ },
};
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 1668f8116908..4c2c5e93aff3 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -28,6 +28,7 @@
#include <linux/types.h>
#include "intel_display.h"
+#include "intel_wakeref.h"
/*FIXME: Move this to a more appropriate place. */
#define abs_diff(a, b) ({ \
@@ -118,6 +119,10 @@ enum intel_dpll_id {
* @DPLL_ID_ICL_DPLL1: ICL combo PHY DPLL1
*/
DPLL_ID_ICL_DPLL1 = 1,
+ /**
+ * @DPLL_ID_EHL_DPLL4: EHL combo PHY DPLL4
+ */
+ DPLL_ID_EHL_DPLL4 = 2,
/**
* @DPLL_ID_ICL_TBTPLL: ICL TBT PLL
*/
@@ -320,6 +325,7 @@ struct intel_shared_dpll {
* @info: platform specific info
*/
const struct dpll_info *info;
+ intel_wakeref_t wakeref;
};
#define SKL_DPLL0 0
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/ehl: Add support for DPLL4 (v10)
2019-07-03 23:03 [PATCH] drm/i915/ehl: Add support for DPLL4 (v10) Vivek Kasireddy
@ 2019-07-03 23:50 ` Patchwork
2019-07-05 3:11 ` ✗ Fi.CI.IGT: failure " Patchwork
` (4 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2019-07-03 23:50 UTC (permalink / raw)
To: Vivek Kasireddy; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/ehl: Add support for DPLL4 (v10)
URL : https://patchwork.freedesktop.org/series/63171/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6405 -> Patchwork_13517
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13517/
Known issues
------------
Here are the changes found in Patchwork_13517 that come from known issues:
### IGT changes ###
#### Possible fixes ####
* {igt@gem_ctx_switch@rcs0}:
- fi-icl-guc: [INCOMPLETE][1] ([fdo#107713]) -> [PASS][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6405/fi-icl-guc/igt@gem_ctx_switch@rcs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13517/fi-icl-guc/igt@gem_ctx_switch@rcs0.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111049]: https://bugs.freedesktop.org/show_bug.cgi?id=111049
Participating hosts (53 -> 44)
------------------------------
Additional (2): fi-hsw-4770r fi-cml-u2
Missing (11): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-icl-u2 fi-bsw-cyan fi-byt-clapper fi-icl-u3 fi-icl-y fi-icl-dsi fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_6405 -> Patchwork_13517
CI_DRM_6405: d395f3e20d154dfeabb95117f388f2e953c12ac9 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5082: f7c51e6fbf8da0784b64a1edaee5266aa9b9f829 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13517: a1eedddb57a23f4e611d42d90e26748e6cc39846 @ git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13517/build_32bit.log
CALL scripts/checksyscalls.sh
CALL scripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1287: recipe for target 'modules' failed
make: *** [modules] Error 2
== Linux commits ==
a1eedddb57a2 drm/i915/ehl: Add support for DPLL4 (v10)
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13517/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* ✗ Fi.CI.IGT: failure for drm/i915/ehl: Add support for DPLL4 (v10)
2019-07-03 23:03 [PATCH] drm/i915/ehl: Add support for DPLL4 (v10) Vivek Kasireddy
2019-07-03 23:50 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2019-07-05 3:11 ` Patchwork
2019-07-05 10:23 ` Ville Syrjälä
2019-07-05 10:28 ` [PATCH] " Ville Syrjälä
` (3 subsequent siblings)
5 siblings, 1 reply; 12+ messages in thread
From: Patchwork @ 2019-07-05 3:11 UTC (permalink / raw)
To: Vivek Kasireddy; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/ehl: Add support for DPLL4 (v10)
URL : https://patchwork.freedesktop.org/series/63171/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6405_full -> Patchwork_13517_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_13517_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_13517_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_13517_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_busy@close-race:
- shard-snb: [PASS][1] -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6405/shard-snb4/igt@gem_busy@close-race.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13517/shard-snb6/igt@gem_busy@close-race.html
* igt@runner@aborted:
- shard-snb: NOTRUN -> [FAIL][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13517/shard-snb6/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_13517_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_busy@close-race:
- shard-iclb: [PASS][4] -> [DMESG-FAIL][5] ([fdo#111063])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6405/shard-iclb6/igt@gem_busy@close-race.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13517/shard-iclb7/igt@gem_busy@close-race.html
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [PASS][6] -> [DMESG-WARN][7] ([fdo#108566]) +5 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6405/shard-apl6/igt@gem_workarounds@suspend-resume-context.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13517/shard-apl3/igt@gem_workarounds@suspend-resume-context.html
* igt@i915_pm_rpm@gem-execbuf-stress:
- shard-hsw: [PASS][8] -> [INCOMPLETE][9] ([fdo#103540] / [fdo#107803] / [fdo#107807])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6405/shard-hsw7/igt@i915_pm_rpm@gem-execbuf-stress.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13517/shard-hsw8/igt@i915_pm_rpm@gem-execbuf-stress.html
* igt@i915_suspend@sysfs-reader:
- shard-skl: [PASS][10] -> [INCOMPLETE][11] ([fdo#104108])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6405/shard-skl10/igt@i915_suspend@sysfs-reader.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13517/shard-skl8/igt@i915_suspend@sysfs-reader.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [PASS][12] -> [FAIL][13] ([fdo#105363])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6405/shard-skl8/igt@kms_flip@flip-vs-expired-vblank.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13517/shard-skl1/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-skl: [PASS][14] -> [INCOMPLETE][15] ([fdo#109507])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6405/shard-skl8/igt@kms_flip@flip-vs-suspend-interruptible.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13517/shard-skl8/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render:
- shard-iclb: [PASS][16] -> [FAIL][17] ([fdo#103167]) +1 similar issue
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6405/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13517/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
- shard-iclb: [PASS][18] -> [INCOMPLETE][19] ([fdo#107713] / [fdo#110042])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6405/shard-iclb8/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13517/shard-iclb3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [PASS][20] -> [FAIL][21] ([fdo#108145])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6405/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13517/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_plane_lowres@pipe-a-tiling-y:
- shard-iclb: [PASS][22] -> [FAIL][23] ([fdo#103166])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6405/shard-iclb3/igt@kms_plane_lowres@pipe-a-tiling-y.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13517/shard-iclb8/igt@kms_plane_lowres@pipe-a-tiling-y.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [PASS][24] -> [SKIP][25] ([fdo#109441]) +3 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6405/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13517/shard-iclb4/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][26] -> [FAIL][27] ([fdo#99912])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6405/shard-apl4/igt@kms_setmode@basic.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13517/shard-apl4/igt@kms_setmode@basic.html
#### Possible fixes ####
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-apl: [DMESG-WARN][28] ([fdo#108566]) -> [PASS][29] +2 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6405/shard-apl5/igt@kms_flip@flip-vs-suspend-interruptible.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13517/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite:
- shard-iclb: [FAIL][30] ([fdo#103167]) -> [PASS][31] +1 similar issue
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6405/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13517/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [FAIL][32] ([fdo#108145]) -> [PASS][33]
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6405/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13517/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [SKIP][34] ([fdo#109441]) -> [PASS][35] +5 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6405/shard-iclb3/igt@kms_psr@psr2_sprite_plane_move.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13517/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_setmode@basic:
- shard-skl: [FAIL][36] ([fdo#99912]) -> [PASS][37]
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6405/shard-skl1/igt@kms_setmode@basic.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13517/shard-skl3/igt@kms_setmode@basic.html
#### Warnings ####
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [SKIP][38] ([fdo#109349]) -> [DMESG-WARN][39] ([fdo#107724])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6405/shard-iclb3/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13517/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
* igt@kms_frontbuffer_tracking@fbc-tilingchange:
- shard-skl: [FAIL][40] ([fdo#108040]) -> [FAIL][41] ([fdo#103167])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6405/shard-skl1/igt@kms_frontbuffer_tracking@fbc-tilingchange.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13517/shard-skl3/igt@kms_frontbuffer_tracking@fbc-tilingchange.html
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#107803]: https://bugs.freedesktop.org/show_bug.cgi?id=107803
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#108040]: https://bugs.freedesktop.org/show_bug.cgi?id=108040
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
[fdo#110042]: https://bugs.freedesktop.org/show_bug.cgi?id=110042
[fdo#111063]: https://bugs.freedesktop.org/show_bug.cgi?id=111063
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_6405 -> Patchwork_13517
CI_DRM_6405: d395f3e20d154dfeabb95117f388f2e953c12ac9 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5082: f7c51e6fbf8da0784b64a1edaee5266aa9b9f829 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13517: a1eedddb57a23f4e611d42d90e26748e6cc39846 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13517/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: ✗ Fi.CI.IGT: failure for drm/i915/ehl: Add support for DPLL4 (v10)
2019-07-05 3:11 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2019-07-05 10:23 ` Ville Syrjälä
0 siblings, 0 replies; 12+ messages in thread
From: Ville Syrjälä @ 2019-07-05 10:23 UTC (permalink / raw)
To: intel-gfx
On Fri, Jul 05, 2019 at 03:11:05AM -0000, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/ehl: Add support for DPLL4 (v10)
> URL : https://patchwork.freedesktop.org/series/63171/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_6405_full -> Patchwork_13517_full
> ====================================================
>
> Summary
> -------
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_13517_full absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_13517_full, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
>
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in Patchwork_13517_full:
>
> ### IGT changes ###
>
> #### Possible regressions ####
>
> * igt@gem_busy@close-race:
> - shard-snb: [PASS][1] -> [DMESG-FAIL][2]
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6405/shard-snb4/igt@gem_busy@close-race.html
> [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13517/shard-snb6/igt@gem_busy@close-race.html
Some kind of gem fail. Nothing to do with this patch.
<4> [602.084517] general protection fault: 0000 [#1] PREEMPT SMP PTI
<4> [602.084530] CPU: 1 PID: 2824 Comm: gem_busy Tainted: G U 5.2.0-rc7-CI-Patchwork_13517+ #1
<4> [602.084542] Hardware name: Dell Inc. XPS 8300 /0Y2MRG, BIOS A06 10/17/2011
<4> [602.084611] RIP: 0010:i915_gem_busy_ioctl+0x136/0x5d0 [i915]
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] drm/i915/ehl: Add support for DPLL4 (v10)
2019-07-03 23:03 [PATCH] drm/i915/ehl: Add support for DPLL4 (v10) Vivek Kasireddy
2019-07-03 23:50 ` ✓ Fi.CI.BAT: success for " Patchwork
2019-07-05 3:11 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2019-07-05 10:28 ` Ville Syrjälä
2019-07-10 18:47 ` Ville Syrjälä
` (2 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Ville Syrjälä @ 2019-07-05 10:28 UTC (permalink / raw)
To: Vivek Kasireddy; +Cc: intel-gfx
On Wed, Jul 03, 2019 at 04:03:53PM -0700, Vivek Kasireddy wrote:
> This patch adds support for DPLL4 on EHL that include the
> following restrictions:
>
> - DPLL4 cannot be used with DDIA (combo port A internal eDP usage).
> DPLL4 can be used with other DDIs, including DDID
> (combo port A external usage).
>
> - DPLL4 cannot be enabled when DC5 or DC6 are enabled.
>
> - The DPLL4 enable, lock, power enabled, and power state are connected
> to the MGPLL1_ENABLE register.
>
> v2: (suggestions from Bob Paauwe)
> - Rework ehl_get_dpll() function to call intel_find_shared_dpll() and
> iterate twice: once for Combo plls and once for MG plls.
>
> - Use MG pll funcs for DPLL4 instead of creating new ones and modify
> mg_pll_enable to include the restrictions for EHL.
>
> v3: Fix compilation error
>
> v4: (suggestions from Lucas and Ville)
> - Treat DPLL4 as a combo phy PLL and not as MG PLL
> - Disable DC states when this DPLL is being enabled
> - Reuse icl_get_dpll instead of creating a separate one for EHL
>
> v5: (suggestion from Ville)
> - Refcount the DC OFF power domains during the enabling and disabling
> of this DPLL.
>
> v6: rebase
>
> v7: (suggestion from Imre)
> - Add a new power domain instead of iterating over the domains
> assoicated with DC OFF power well.
>
> v8: (Ville and Imre)
> - Rename POWER_DOMAIN_DPLL4 TO POWER_DOMAIN_DPLL_DC_OFF
> - Grab a reference in intel_modeset_setup_hw_state() if this
> DPLL was already enabled perhaps by BIOS.
> - Check for the port type instead of the encoder
>
> v9: (Ville)
> - Move the block of code that grabs a reference to the power domain
> POWER_DOMAIN_DPLL_DC_OFF to intel_modeset_readout_hw_state() to ensure
> that there is a reference present before this DPLL might get disabled.
>
> v10: rebase
>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Vivek Kasireddy <vivek.kasireddy@intel.com>
lgtm. Picked up José's r-b from an earlier posting (in the future plese
collect those yourself so they don't get lost), and pushed to dinq.
Thanks for the patch.
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] drm/i915/ehl: Add support for DPLL4 (v10)
2019-07-03 23:03 [PATCH] drm/i915/ehl: Add support for DPLL4 (v10) Vivek Kasireddy
` (2 preceding siblings ...)
2019-07-05 10:28 ` [PATCH] " Ville Syrjälä
@ 2019-07-10 18:47 ` Ville Syrjälä
2019-07-17 1:54 ` Vivek Kasireddy
2019-07-17 2:13 ` [PATCH] drm/i915/ehl: Use an id of 4 while accessing DPLL4's CR0 and CR1 Vivek Kasireddy
2019-07-17 3:16 ` ✓ Fi.CI.BAT: success for drm/i915/ehl: Add support for DPLL4 (v10) (rev2) Patchwork
2019-07-17 4:27 ` ✓ Fi.CI.IGT: " Patchwork
5 siblings, 2 replies; 12+ messages in thread
From: Ville Syrjälä @ 2019-07-10 18:47 UTC (permalink / raw)
To: Vivek Kasireddy; +Cc: intel-gfx
On Wed, Jul 03, 2019 at 04:03:53PM -0700, Vivek Kasireddy wrote:
> This patch adds support for DPLL4 on EHL that include the
> following restrictions:
>
> - DPLL4 cannot be used with DDIA (combo port A internal eDP usage).
> DPLL4 can be used with other DDIs, including DDID
> (combo port A external usage).
>
> - DPLL4 cannot be enabled when DC5 or DC6 are enabled.
>
> - The DPLL4 enable, lock, power enabled, and power state are connected
> to the MGPLL1_ENABLE register.
>
> v2: (suggestions from Bob Paauwe)
> - Rework ehl_get_dpll() function to call intel_find_shared_dpll() and
> iterate twice: once for Combo plls and once for MG plls.
>
> - Use MG pll funcs for DPLL4 instead of creating new ones and modify
> mg_pll_enable to include the restrictions for EHL.
>
> v3: Fix compilation error
>
> v4: (suggestions from Lucas and Ville)
> - Treat DPLL4 as a combo phy PLL and not as MG PLL
> - Disable DC states when this DPLL is being enabled
> - Reuse icl_get_dpll instead of creating a separate one for EHL
>
> v5: (suggestion from Ville)
> - Refcount the DC OFF power domains during the enabling and disabling
> of this DPLL.
>
> v6: rebase
>
> v7: (suggestion from Imre)
> - Add a new power domain instead of iterating over the domains
> assoicated with DC OFF power well.
>
> v8: (Ville and Imre)
> - Rename POWER_DOMAIN_DPLL4 TO POWER_DOMAIN_DPLL_DC_OFF
> - Grab a reference in intel_modeset_setup_hw_state() if this
> DPLL was already enabled perhaps by BIOS.
> - Check for the port type instead of the encoder
>
> v9: (Ville)
> - Move the block of code that grabs a reference to the power domain
> POWER_DOMAIN_DPLL_DC_OFF to intel_modeset_readout_hw_state() to ensure
> that there is a reference present before this DPLL might get disabled.
>
> v10: rebase
>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Vivek Kasireddy <vivek.kasireddy@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 7 +++
> .../drm/i915/display/intel_display_power.c | 3 ++
> .../drm/i915/display/intel_display_power.h | 1 +
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 47 +++++++++++++++++--
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 6 +++
> 5 files changed, 60 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 919f5ac844c8..557462208462 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -16653,6 +16653,13 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
>
> pll->on = pll->info->funcs->get_hw_state(dev_priv, pll,
> &pll->state.hw_state);
> +
> + if (IS_ELKHARTLAKE(dev_priv) && pll->on &&
> + pll->info->id == DPLL_ID_EHL_DPLL4) {
> + pll->wakeref = intel_display_power_get(dev_priv,
> + POWER_DOMAIN_DPLL_DC_OFF);
> + }
> +
> pll->state.crtc_mask = 0;
> for_each_intel_crtc(dev, crtc) {
> struct intel_crtc_state *crtc_state =
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index c19b958461ca..7437fc71d289 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -118,6 +118,8 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
> return "MODESET";
> case POWER_DOMAIN_GT_IRQ:
> return "GT_IRQ";
> + case POWER_DOMAIN_DPLL_DC_OFF:
> + return "DPLL_DC_OFF";
> default:
> MISSING_CASE(domain);
> return "?";
> @@ -2455,6 +2457,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> ICL_PW_2_POWER_DOMAINS | \
> BIT_ULL(POWER_DOMAIN_MODESET) | \
> BIT_ULL(POWER_DOMAIN_AUX_A) | \
> + BIT_ULL(POWER_DOMAIN_DPLL_DC_OFF) | \
> BIT_ULL(POWER_DOMAIN_INIT))
>
> #define ICL_DDI_IO_A_POWER_DOMAINS ( \
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
> index ff57b0a7fe59..8f43f7051a16 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -59,6 +59,7 @@ enum intel_display_power_domain {
> POWER_DOMAIN_GMBUS,
> POWER_DOMAIN_MODESET,
> POWER_DOMAIN_GT_IRQ,
> + POWER_DOMAIN_DPLL_DC_OFF,
> POWER_DOMAIN_INIT,
>
> POWER_DOMAIN_NUM,
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index f953971e7c3b..67cfe836286e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -2905,6 +2905,9 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state,
> intel_atomic_get_new_crtc_state(state, crtc);
> struct icl_port_dpll *port_dpll =
> &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + enum port port = encoder->port;
> + bool has_dpll4 = false;
>
> if (!icl_calc_dpll_state(crtc_state, encoder, &port_dpll->hw_state)) {
> DRM_DEBUG_KMS("Could not calculate combo PHY PLL state.\n");
> @@ -2912,10 +2915,14 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state,
> return false;
> }
>
> + if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A)
> + has_dpll4 = true;
> +
> port_dpll->pll = intel_find_shared_dpll(state, crtc,
> &port_dpll->hw_state,
> DPLL_ID_ICL_DPLL0,
> - DPLL_ID_ICL_DPLL1);
> + has_dpll4 ? DPLL_ID_EHL_DPLL4
> + : DPLL_ID_ICL_DPLL1);
> if (!port_dpll->pll) {
> DRM_DEBUG_KMS("No combo PHY PLL found for port %c\n",
> port_name(encoder->port));
> @@ -3119,8 +3126,14 @@ static bool combo_pll_get_hw_state(struct drm_i915_private *dev_priv,
> struct intel_shared_dpll *pll,
> struct intel_dpll_hw_state *hw_state)
> {
> - return icl_pll_get_hw_state(dev_priv, pll, hw_state,
> - CNL_DPLL_ENABLE(pll->info->id));
> + i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
> +
> + if (IS_ELKHARTLAKE(dev_priv) &&
> + pll->info->id == DPLL_ID_EHL_DPLL4) {
> + enable_reg = MG_PLL_ENABLE(0);
> + }
> +
> + return icl_pll_get_hw_state(dev_priv, pll, hw_state, enable_reg);
> }
>
> static bool tbt_pll_get_hw_state(struct drm_i915_private *dev_priv,
> @@ -3231,6 +3244,19 @@ static void combo_pll_enable(struct drm_i915_private *dev_priv,
> {
> i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
>
> + if (IS_ELKHARTLAKE(dev_priv) &&
> + pll->info->id == DPLL_ID_EHL_DPLL4) {
> + enable_reg = MG_PLL_ENABLE(0);
> +
> + /*
> + * We need to disable DC states when this DPLL is enabled.
> + * This can be done by taking a reference on DPLL4 power
> + * domain.
> + */
> + pll->wakeref = intel_display_power_get(dev_priv,
> + POWER_DOMAIN_DPLL_DC_OFF);
> + }
> +
> icl_pll_power_enable(dev_priv, pll, enable_reg);
>
> icl_dpll_write(dev_priv, pll);
> @@ -3326,7 +3352,19 @@ static void icl_pll_disable(struct drm_i915_private *dev_priv,
> static void combo_pll_disable(struct drm_i915_private *dev_priv,
> struct intel_shared_dpll *pll)
> {
> - icl_pll_disable(dev_priv, pll, CNL_DPLL_ENABLE(pll->info->id));
> + i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
> +
> + if (IS_ELKHARTLAKE(dev_priv) &&
> + pll->info->id == DPLL_ID_EHL_DPLL4) {
> + enable_reg = MG_PLL_ENABLE(0);
> + icl_pll_disable(dev_priv, pll, enable_reg);
> +
> + intel_display_power_put(dev_priv, POWER_DOMAIN_DPLL_DC_OFF,
> + pll->wakeref);
> + return;
> + }
> +
> + icl_pll_disable(dev_priv, pll, enable_reg);
> }
>
> static void tbt_pll_disable(struct drm_i915_private *dev_priv,
> @@ -3406,6 +3444,7 @@ static const struct intel_dpll_mgr icl_pll_mgr = {
> static const struct dpll_info ehl_plls[] = {
> { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
> { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
> + { "DPLL 4", &combo_pll_funcs, DPLL_ID_EHL_DPLL4, 0 },
> { },
> };
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index 1668f8116908..4c2c5e93aff3 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -28,6 +28,7 @@
> #include <linux/types.h>
>
> #include "intel_display.h"
> +#include "intel_wakeref.h"
>
> /*FIXME: Move this to a more appropriate place. */
> #define abs_diff(a, b) ({ \
> @@ -118,6 +119,10 @@ enum intel_dpll_id {
> * @DPLL_ID_ICL_DPLL1: ICL combo PHY DPLL1
> */
> DPLL_ID_ICL_DPLL1 = 1,
> + /**
> + * @DPLL_ID_EHL_DPLL4: EHL combo PHY DPLL4
> + */
> + DPLL_ID_EHL_DPLL4 = 2,
While looking at the TGL stuff I noticed that this ID seems to be wrong.
We use this to generate the register offsets but the docs show the
following:
DPLL0_CFGCR0 0x164000
DPLL1_CFGCR0 0x164080
TBTPLL_CFGCR0 0x164100
DPLL4_CFGCR0 0x164200
So the DPLL4 accesses will now land on TBTPLL. The ID if DPLL4 should
really be 4 I guess.
> /**
> * @DPLL_ID_ICL_TBTPLL: ICL TBT PLL
> */
> @@ -320,6 +325,7 @@ struct intel_shared_dpll {
> * @info: platform specific info
> */
> const struct dpll_info *info;
> + intel_wakeref_t wakeref;
> };
>
> #define SKL_DPLL0 0
> --
> 2.21.0
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] drm/i915/ehl: Add support for DPLL4 (v10)
2019-07-10 18:47 ` Ville Syrjälä
@ 2019-07-17 1:54 ` Vivek Kasireddy
2019-07-18 17:14 ` Ville Syrjälä
2019-07-17 2:13 ` [PATCH] drm/i915/ehl: Use an id of 4 while accessing DPLL4's CR0 and CR1 Vivek Kasireddy
1 sibling, 1 reply; 12+ messages in thread
From: Vivek Kasireddy @ 2019-07-17 1:54 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Wed, 10 Jul 2019 21:47:52 +0300
Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
Hi Ville,
> On Wed, Jul 03, 2019 at 04:03:53PM -0700, Vivek Kasireddy wrote:
> > This patch adds support for DPLL4 on EHL that include the
> > following restrictions:
> >
> > - DPLL4 cannot be used with DDIA (combo port A internal eDP usage).
> > DPLL4 can be used with other DDIs, including DDID
> > (combo port A external usage).
> >
> > - DPLL4 cannot be enabled when DC5 or DC6 are enabled.
> >
> > - The DPLL4 enable, lock, power enabled, and power state are
> > connected to the MGPLL1_ENABLE register.
> >
> > v2: (suggestions from Bob Paauwe)
> > - Rework ehl_get_dpll() function to call intel_find_shared_dpll()
> > and iterate twice: once for Combo plls and once for MG plls.
> >
> > - Use MG pll funcs for DPLL4 instead of creating new ones and modify
> > mg_pll_enable to include the restrictions for EHL.
> >
> > v3: Fix compilation error
> >
> > v4: (suggestions from Lucas and Ville)
> > - Treat DPLL4 as a combo phy PLL and not as MG PLL
> > - Disable DC states when this DPLL is being enabled
> > - Reuse icl_get_dpll instead of creating a separate one for EHL
> >
> > v5: (suggestion from Ville)
> > - Refcount the DC OFF power domains during the enabling and
> > disabling of this DPLL.
> >
> > v6: rebase
> >
> > v7: (suggestion from Imre)
> > - Add a new power domain instead of iterating over the domains
> > assoicated with DC OFF power well.
> >
> > v8: (Ville and Imre)
> > - Rename POWER_DOMAIN_DPLL4 TO POWER_DOMAIN_DPLL_DC_OFF
> > - Grab a reference in intel_modeset_setup_hw_state() if this
> > DPLL was already enabled perhaps by BIOS.
> > - Check for the port type instead of the encoder
> >
> > v9: (Ville)
> > - Move the block of code that grabs a reference to the power domain
> > POWER_DOMAIN_DPLL_DC_OFF to intel_modeset_readout_hw_state() to
> > ensure that there is a reference present before this DPLL might get
> > disabled.
> >
> > v10: rebase
> >
> > Cc: José Roberto de Souza <jose.souza@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Cc: Imre Deak <imre.deak@intel.com>
> > Signed-off-by: Vivek Kasireddy <vivek.kasireddy@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 7 +++
> > .../drm/i915/display/intel_display_power.c | 3 ++
> > .../drm/i915/display/intel_display_power.h | 1 +
> > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 47
> > +++++++++++++++++-- drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > | 6 +++ 5 files changed, 60 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c index
> > 919f5ac844c8..557462208462 100644 ---
> > a/drivers/gpu/drm/i915/display/intel_display.c +++
> > b/drivers/gpu/drm/i915/display/intel_display.c @@ -16653,6
> > +16653,13 @@ static void intel_modeset_readout_hw_state(struct
> > drm_device *dev) pll->on = pll->info->funcs->get_hw_state(dev_priv,
> > pll, &pll->state.hw_state);
> > +
> > + if (IS_ELKHARTLAKE(dev_priv) && pll->on &&
> > + pll->info->id == DPLL_ID_EHL_DPLL4) {
> > + pll->wakeref =
> > intel_display_power_get(dev_priv,
> > +
> > POWER_DOMAIN_DPLL_DC_OFF);
> > + }
> > +
> > pll->state.crtc_mask = 0;
> > for_each_intel_crtc(dev, crtc) {
> > struct intel_crtc_state *crtc_state =
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > b/drivers/gpu/drm/i915/display/intel_display_power.c index
> > c19b958461ca..7437fc71d289 100644 ---
> > a/drivers/gpu/drm/i915/display/intel_display_power.c +++
> > b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -118,6
> > +118,8 @@ intel_display_power_domain_str(enum
> > intel_display_power_domain domain) return "MODESET"; case
> > POWER_DOMAIN_GT_IRQ: return "GT_IRQ";
> > + case POWER_DOMAIN_DPLL_DC_OFF:
> > + return "DPLL_DC_OFF";
> > default:
> > MISSING_CASE(domain);
> > return "?";
> > @@ -2455,6 +2457,7 @@ void intel_display_power_put(struct
> > drm_i915_private *dev_priv, ICL_PW_2_POWER_DOMAINS
> > | \ BIT_ULL(POWER_DOMAIN_MODESET)
> > | \ BIT_ULL(POWER_DOMAIN_AUX_A)
> > | \
> > + BIT_ULL(POWER_DOMAIN_DPLL_DC_OFF) |
> > \ BIT_ULL(POWER_DOMAIN_INIT))
> >
> > #define ICL_DDI_IO_A_POWER_DOMAINS ( \
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
> > b/drivers/gpu/drm/i915/display/intel_display_power.h index
> > ff57b0a7fe59..8f43f7051a16 100644 ---
> > a/drivers/gpu/drm/i915/display/intel_display_power.h +++
> > b/drivers/gpu/drm/i915/display/intel_display_power.h @@ -59,6 +59,7
> > @@ enum intel_display_power_domain { POWER_DOMAIN_GMBUS,
> > POWER_DOMAIN_MODESET,
> > POWER_DOMAIN_GT_IRQ,
> > + POWER_DOMAIN_DPLL_DC_OFF,
> > POWER_DOMAIN_INIT,
> >
> > POWER_DOMAIN_NUM,
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index
> > f953971e7c3b..67cfe836286e 100644 ---
> > a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++
> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -2905,6 +2905,9
> > @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state
> > *state, intel_atomic_get_new_crtc_state(state, crtc); struct
> > icl_port_dpll *port_dpll =
> > &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
> > + struct drm_i915_private *dev_priv =
> > to_i915(crtc->base.dev);
> > + enum port port = encoder->port;
> > + bool has_dpll4 = false;
> >
> > if (!icl_calc_dpll_state(crtc_state, encoder,
> > &port_dpll->hw_state)) { DRM_DEBUG_KMS("Could not calculate combo
> > PHY PLL state.\n"); @@ -2912,10 +2915,14 @@ static bool
> > icl_get_combo_phy_dpll(struct intel_atomic_state *state, return
> > false; }
> >
> > + if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A)
> > + has_dpll4 = true;
> > +
> > port_dpll->pll = intel_find_shared_dpll(state, crtc,
> > &port_dpll->hw_state,
> > DPLL_ID_ICL_DPLL0,
> > - DPLL_ID_ICL_DPLL1);
> > + has_dpll4 ?
> > DPLL_ID_EHL_DPLL4
> > + :
> > DPLL_ID_ICL_DPLL1); if (!port_dpll->pll) {
> > DRM_DEBUG_KMS("No combo PHY PLL found for port
> > %c\n", port_name(encoder->port));
> > @@ -3119,8 +3126,14 @@ static bool combo_pll_get_hw_state(struct
> > drm_i915_private *dev_priv, struct intel_shared_dpll *pll,
> > struct intel_dpll_hw_state
> > *hw_state) {
> > - return icl_pll_get_hw_state(dev_priv, pll, hw_state,
> > -
> > CNL_DPLL_ENABLE(pll->info->id));
> > + i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
> > +
> > + if (IS_ELKHARTLAKE(dev_priv) &&
> > + pll->info->id == DPLL_ID_EHL_DPLL4) {
> > + enable_reg = MG_PLL_ENABLE(0);
> > + }
> > +
> > + return icl_pll_get_hw_state(dev_priv, pll, hw_state,
> > enable_reg); }
> >
> > static bool tbt_pll_get_hw_state(struct drm_i915_private *dev_priv,
> > @@ -3231,6 +3244,19 @@ static void combo_pll_enable(struct
> > drm_i915_private *dev_priv, {
> > i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
> >
> > + if (IS_ELKHARTLAKE(dev_priv) &&
> > + pll->info->id == DPLL_ID_EHL_DPLL4) {
> > + enable_reg = MG_PLL_ENABLE(0);
> > +
> > + /*
> > + * We need to disable DC states when this DPLL is
> > enabled.
> > + * This can be done by taking a reference on DPLL4
> > power
> > + * domain.
> > + */
> > + pll->wakeref = intel_display_power_get(dev_priv,
> > +
> > POWER_DOMAIN_DPLL_DC_OFF);
> > + }
> > +
> > icl_pll_power_enable(dev_priv, pll, enable_reg);
> >
> > icl_dpll_write(dev_priv, pll);
> > @@ -3326,7 +3352,19 @@ static void icl_pll_disable(struct
> > drm_i915_private *dev_priv, static void combo_pll_disable(struct
> > drm_i915_private *dev_priv, struct intel_shared_dpll *pll)
> > {
> > - icl_pll_disable(dev_priv, pll,
> > CNL_DPLL_ENABLE(pll->info->id));
> > + i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
> > +
> > + if (IS_ELKHARTLAKE(dev_priv) &&
> > + pll->info->id == DPLL_ID_EHL_DPLL4) {
> > + enable_reg = MG_PLL_ENABLE(0);
> > + icl_pll_disable(dev_priv, pll, enable_reg);
> > +
> > + intel_display_power_put(dev_priv,
> > POWER_DOMAIN_DPLL_DC_OFF,
> > + pll->wakeref);
> > + return;
> > + }
> > +
> > + icl_pll_disable(dev_priv, pll, enable_reg);
> > }
> >
> > static void tbt_pll_disable(struct drm_i915_private *dev_priv,
> > @@ -3406,6 +3444,7 @@ static const struct intel_dpll_mgr
> > icl_pll_mgr = { static const struct dpll_info ehl_plls[] = {
> > { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
> > { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
> > + { "DPLL 4", &combo_pll_funcs, DPLL_ID_EHL_DPLL4, 0 },
> > { },
> > };
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h index
> > 1668f8116908..4c2c5e93aff3 100644 ---
> > a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h +++
> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h @@ -28,6 +28,7 @@
> > #include <linux/types.h>
> >
> > #include "intel_display.h"
> > +#include "intel_wakeref.h"
> >
> > /*FIXME: Move this to a more appropriate place. */
> > #define abs_diff(a, b) ({ \
> > @@ -118,6 +119,10 @@ enum intel_dpll_id {
> > * @DPLL_ID_ICL_DPLL1: ICL combo PHY DPLL1
> > */
> > DPLL_ID_ICL_DPLL1 = 1,
> > + /**
> > + * @DPLL_ID_EHL_DPLL4: EHL combo PHY DPLL4
> > + */
> > + DPLL_ID_EHL_DPLL4 = 2,
>
> While looking at the TGL stuff I noticed that this ID seems to be
> wrong. We use this to generate the register offsets but the docs show
> the following:
>
> DPLL0_CFGCR0 0x164000
> DPLL1_CFGCR0 0x164080
> TBTPLL_CFGCR0 0x164100
> DPLL4_CFGCR0 0x164200
>
> So the DPLL4 accesses will now land on TBTPLL. The ID if DPLL4 should
> really be 4 I guess.
Yes, looks like it should be 4 indeed. However, I was wondering what is
the best way to address this issue. Simply changing the id to 4 isn't
going to work as there are many places in intel_dpll_mgr.c that assume
the dpll id to be the index in the dev_priv->shared_dplls array as
stated in the definition of dpll_info:
/**
* @id: unique indentifier for this DPLL; should match the
index in the
* dev_priv->shared_dplls array
*/
enum intel_dpll_id id;
Should I change all these places that make this assumption and fix them?
Or, should I just simply add an if condition around cr0 and cr1 accesses
in icl_dpll_write and icl_pll_get_hw_state?
Thanks,
Vivek
>
> > /**
> > * @DPLL_ID_ICL_TBTPLL: ICL TBT PLL
> > */
> > @@ -320,6 +325,7 @@ struct intel_shared_dpll {
> > * @info: platform specific info
> > */
> > const struct dpll_info *info;
> > + intel_wakeref_t wakeref;
> > };
> >
> > #define SKL_DPLL0 0
> > --
> > 2.21.0
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH] drm/i915/ehl: Use an id of 4 while accessing DPLL4's CR0 and CR1
2019-07-10 18:47 ` Ville Syrjälä
2019-07-17 1:54 ` Vivek Kasireddy
@ 2019-07-17 2:13 ` Vivek Kasireddy
2019-07-18 17:29 ` Ville Syrjälä
1 sibling, 1 reply; 12+ messages in thread
From: Vivek Kasireddy @ 2019-07-17 2:13 UTC (permalink / raw)
To: intel-gfx
Although, DPLL4 enable and disable is associated with MGPLL1_ENABLE
register, we can use ICL_DPLL_CFGCR0/CR1 macros to access this dpll's
CR0 and CR1 registers by passing an id of 4 to these macros.
Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Vivek Kasireddy <vivek.kasireddy@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 18 ++++++++++++++----
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 319a26a1ec10..f9bdf8514a53 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3127,8 +3127,13 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
hw_state->cfgcr0 = I915_READ(TGL_DPLL_CFGCR0(id));
hw_state->cfgcr1 = I915_READ(TGL_DPLL_CFGCR1(id));
} else {
- hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
- hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
+ if (IS_ELKHARTLAKE(dev_priv) && id == DPLL_ID_EHL_DPLL4) {
+ hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(4));
+ hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(4));
+ } else {
+ hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
+ hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
+ }
}
ret = true;
@@ -3169,8 +3174,13 @@ static void icl_dpll_write(struct drm_i915_private *dev_priv,
cfgcr0_reg = TGL_DPLL_CFGCR0(id);
cfgcr1_reg = TGL_DPLL_CFGCR1(id);
} else {
- cfgcr0_reg = ICL_DPLL_CFGCR0(id);
- cfgcr1_reg = ICL_DPLL_CFGCR1(id);
+ if (IS_ELKHARTLAKE(dev_priv) && id == DPLL_ID_EHL_DPLL4) {
+ cfgcr0_reg = ICL_DPLL_CFGCR0(4);
+ cfgcr1_reg = ICL_DPLL_CFGCR1(4);
+ } else {
+ cfgcr0_reg = ICL_DPLL_CFGCR0(id);
+ cfgcr1_reg = ICL_DPLL_CFGCR1(id);
+ }
}
I915_WRITE(cfgcr0_reg, hw_state->cfgcr0);
--
2.21.0
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/ehl: Add support for DPLL4 (v10) (rev2)
2019-07-03 23:03 [PATCH] drm/i915/ehl: Add support for DPLL4 (v10) Vivek Kasireddy
` (3 preceding siblings ...)
2019-07-10 18:47 ` Ville Syrjälä
@ 2019-07-17 3:16 ` Patchwork
2019-07-17 4:27 ` ✓ Fi.CI.IGT: " Patchwork
5 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2019-07-17 3:16 UTC (permalink / raw)
To: Vivek Kasireddy; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/ehl: Add support for DPLL4 (v10) (rev2)
URL : https://patchwork.freedesktop.org/series/63171/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6495 -> Patchwork_13667
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13667/
Known issues
------------
Here are the changes found in Patchwork_13667 that come from known issues:
### IGT changes ###
#### Possible fixes ####
* igt@i915_module_load@reload-with-fault-injection:
- {fi-icl-u4}: [DMESG-WARN][1] ([fdo#105602] / [fdo#106107] / [fdo#106350]) -> [PASS][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6495/fi-icl-u4/igt@i915_module_load@reload-with-fault-injection.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13667/fi-icl-u4/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u2: [INCOMPLETE][3] ([fdo#107713] / [fdo#108569]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6495/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13667/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
* igt@kms_psr@sprite_plane_onoff:
- {fi-icl-u4}: [DMESG-WARN][5] ([fdo#105602]) -> [PASS][6] +30 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6495/fi-icl-u4/igt@kms_psr@sprite_plane_onoff.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13667/fi-icl-u4/igt@kms_psr@sprite_plane_onoff.html
* igt@prime_vgem@basic-fence-flip:
- fi-ilk-650: [DMESG-WARN][7] ([fdo#106387]) -> [PASS][8] +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6495/fi-ilk-650/igt@prime_vgem@basic-fence-flip.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13667/fi-ilk-650/igt@prime_vgem@basic-fence-flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#106350]: https://bugs.freedesktop.org/show_bug.cgi?id=106350
[fdo#106387]: https://bugs.freedesktop.org/show_bug.cgi?id=106387
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111046 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111046
[fdo#111049]: https://bugs.freedesktop.org/show_bug.cgi?id=111049
Participating hosts (54 -> 47)
------------------------------
Additional (1): fi-icl-dsi
Missing (8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_6495 -> Patchwork_13667
CI_DRM_6495: b782c53ecfa06fdbe9b310dca3f0d477fc833496 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5100: 0ea68a1efbfcc4961f2f816ab59e4ad8136c6250 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13667: 8c1db3015d5380d54d1711f54325e7978cb4bf30 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
8c1db3015d53 drm/i915/ehl: Use an id of 4 while accessing DPLL4's CR0 and CR1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13667/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915/ehl: Add support for DPLL4 (v10) (rev2)
2019-07-03 23:03 [PATCH] drm/i915/ehl: Add support for DPLL4 (v10) Vivek Kasireddy
` (4 preceding siblings ...)
2019-07-17 3:16 ` ✓ Fi.CI.BAT: success for drm/i915/ehl: Add support for DPLL4 (v10) (rev2) Patchwork
@ 2019-07-17 4:27 ` Patchwork
5 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2019-07-17 4:27 UTC (permalink / raw)
To: Vivek Kasireddy; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/ehl: Add support for DPLL4 (v10) (rev2)
URL : https://patchwork.freedesktop.org/series/63171/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6495_full -> Patchwork_13667_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_13667_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@vecs0-s3:
- shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +2 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6495/shard-apl3/igt@gem_ctx_isolation@vecs0-s3.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13667/shard-apl7/igt@gem_ctx_isolation@vecs0-s3.html
* igt@gem_tiled_swapping@non-threaded:
- shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108686])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6495/shard-kbl6/igt@gem_tiled_swapping@non-threaded.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13667/shard-kbl7/igt@gem_tiled_swapping@non-threaded.html
* igt@i915_pm_rpm@system-suspend:
- shard-skl: [PASS][5] -> [INCOMPLETE][6] ([fdo#104108] / [fdo#107807])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6495/shard-skl4/igt@i915_pm_rpm@system-suspend.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13667/shard-skl10/igt@i915_pm_rpm@system-suspend.html
* igt@kms_flip@2x-plain-flip-ts-check:
- shard-glk: [PASS][7] -> [FAIL][8] ([fdo#100368])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6495/shard-glk1/igt@kms_flip@2x-plain-flip-ts-check.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13667/shard-glk3/igt@kms_flip@2x-plain-flip-ts-check.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-pgflip-blt:
- shard-glk: [PASS][9] -> [FAIL][10] ([fdo#103167])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6495/shard-glk8/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-pgflip-blt.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13667/shard-glk8/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-fullscreen:
- shard-hsw: [PASS][11] -> [SKIP][12] ([fdo#109271])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6495/shard-hsw7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-fullscreen.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13667/shard-hsw4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-fullscreen.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-render:
- shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#103167]) +4 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6495/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-render.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13667/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-suspend:
- shard-skl: [PASS][15] -> [INCOMPLETE][16] ([fdo#104108] / [fdo#106978])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6495/shard-skl6/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13667/shard-skl4/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
* igt@kms_plane_lowres@pipe-a-tiling-y:
- shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103166])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6495/shard-iclb1/igt@kms_plane_lowres@pipe-a-tiling-y.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13667/shard-iclb1/igt@kms_plane_lowres@pipe-a-tiling-y.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][19] -> [FAIL][20] ([fdo#99912])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6495/shard-apl4/igt@kms_setmode@basic.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13667/shard-apl8/igt@kms_setmode@basic.html
#### Possible fixes ####
* igt@gem_mmap_gtt@basic-small-copy-odd:
- shard-iclb: [INCOMPLETE][21] ([fdo#107713]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6495/shard-iclb7/igt@gem_mmap_gtt@basic-small-copy-odd.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13667/shard-iclb1/igt@gem_mmap_gtt@basic-small-copy-odd.html
* igt@i915_pm_rc6_residency@rc6-accuracy:
- shard-kbl: [SKIP][23] ([fdo#109271]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6495/shard-kbl2/igt@i915_pm_rc6_residency@rc6-accuracy.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13667/shard-kbl3/igt@i915_pm_rc6_residency@rc6-accuracy.html
- shard-snb: [SKIP][25] ([fdo#109271]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6495/shard-snb2/igt@i915_pm_rc6_residency@rc6-accuracy.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13667/shard-snb6/igt@i915_pm_rc6_residency@rc6-accuracy.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
- shard-hsw: [FAIL][27] ([fdo#105767]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6495/shard-hsw6/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13667/shard-hsw8/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [FAIL][29] ([fdo#105363]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6495/shard-skl9/igt@kms_flip@flip-vs-expired-vblank.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13667/shard-skl2/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-glk: [FAIL][31] ([fdo#105363]) -> [PASS][32] +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6495/shard-glk6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13667/shard-glk2/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-suspend:
- shard-snb: [INCOMPLETE][33] ([fdo#105411]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6495/shard-snb1/igt@kms_flip@flip-vs-suspend.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13667/shard-snb7/igt@kms_flip@flip-vs-suspend.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite:
- shard-iclb: [FAIL][35] ([fdo#103167]) -> [PASS][36] +2 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6495/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13667/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-apl: [DMESG-WARN][37] ([fdo#108566]) -> [PASS][38] +2 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6495/shard-apl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13667/shard-apl8/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
- shard-skl: [INCOMPLETE][39] ([fdo#104108]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6495/shard-skl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13667/shard-skl10/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
* igt@kms_psr@no_drrs:
- shard-iclb: [FAIL][41] ([fdo#108341]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6495/shard-iclb1/igt@kms_psr@no_drrs.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13667/shard-iclb2/igt@kms_psr@no_drrs.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [SKIP][43] ([fdo#109441]) -> [PASS][44] +2 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6495/shard-iclb6/igt@kms_psr@psr2_primary_mmap_cpu.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13667/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@perf@polling:
- shard-skl: [FAIL][45] ([fdo#110728]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6495/shard-skl1/igt@perf@polling.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13667/shard-skl1/igt@perf@polling.html
#### Warnings ####
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-wc:
- shard-skl: [FAIL][47] ([fdo#103167]) -> [FAIL][48] ([fdo#108040])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6495/shard-skl8/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-wc.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13667/shard-skl9/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-wc.html
[fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#105767]: https://bugs.freedesktop.org/show_bug.cgi?id=105767
[fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#108040]: https://bugs.freedesktop.org/show_bug.cgi?id=108040
[fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_6495 -> Patchwork_13667
CI_DRM_6495: b782c53ecfa06fdbe9b310dca3f0d477fc833496 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5100: 0ea68a1efbfcc4961f2f816ab59e4ad8136c6250 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13667: 8c1db3015d5380d54d1711f54325e7978cb4bf30 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13667/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] drm/i915/ehl: Add support for DPLL4 (v10)
2019-07-17 1:54 ` Vivek Kasireddy
@ 2019-07-18 17:14 ` Ville Syrjälä
0 siblings, 0 replies; 12+ messages in thread
From: Ville Syrjälä @ 2019-07-18 17:14 UTC (permalink / raw)
To: Vivek Kasireddy; +Cc: intel-gfx
On Tue, Jul 16, 2019 at 06:54:39PM -0700, Vivek Kasireddy wrote:
> On Wed, 10 Jul 2019 21:47:52 +0300
> Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> Hi Ville,
>
> > On Wed, Jul 03, 2019 at 04:03:53PM -0700, Vivek Kasireddy wrote:
> > > This patch adds support for DPLL4 on EHL that include the
> > > following restrictions:
> > >
> > > - DPLL4 cannot be used with DDIA (combo port A internal eDP usage).
> > > DPLL4 can be used with other DDIs, including DDID
> > > (combo port A external usage).
> > >
> > > - DPLL4 cannot be enabled when DC5 or DC6 are enabled.
> > >
> > > - The DPLL4 enable, lock, power enabled, and power state are
> > > connected to the MGPLL1_ENABLE register.
> > >
> > > v2: (suggestions from Bob Paauwe)
> > > - Rework ehl_get_dpll() function to call intel_find_shared_dpll()
> > > and iterate twice: once for Combo plls and once for MG plls.
> > >
> > > - Use MG pll funcs for DPLL4 instead of creating new ones and modify
> > > mg_pll_enable to include the restrictions for EHL.
> > >
> > > v3: Fix compilation error
> > >
> > > v4: (suggestions from Lucas and Ville)
> > > - Treat DPLL4 as a combo phy PLL and not as MG PLL
> > > - Disable DC states when this DPLL is being enabled
> > > - Reuse icl_get_dpll instead of creating a separate one for EHL
> > >
> > > v5: (suggestion from Ville)
> > > - Refcount the DC OFF power domains during the enabling and
> > > disabling of this DPLL.
> > >
> > > v6: rebase
> > >
> > > v7: (suggestion from Imre)
> > > - Add a new power domain instead of iterating over the domains
> > > assoicated with DC OFF power well.
> > >
> > > v8: (Ville and Imre)
> > > - Rename POWER_DOMAIN_DPLL4 TO POWER_DOMAIN_DPLL_DC_OFF
> > > - Grab a reference in intel_modeset_setup_hw_state() if this
> > > DPLL was already enabled perhaps by BIOS.
> > > - Check for the port type instead of the encoder
> > >
> > > v9: (Ville)
> > > - Move the block of code that grabs a reference to the power domain
> > > POWER_DOMAIN_DPLL_DC_OFF to intel_modeset_readout_hw_state() to
> > > ensure that there is a reference present before this DPLL might get
> > > disabled.
> > >
> > > v10: rebase
> > >
> > > Cc: José Roberto de Souza <jose.souza@intel.com>
> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > Cc: Imre Deak <imre.deak@intel.com>
> > > Signed-off-by: Vivek Kasireddy <vivek.kasireddy@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_display.c | 7 +++
> > > .../drm/i915/display/intel_display_power.c | 3 ++
> > > .../drm/i915/display/intel_display_power.h | 1 +
> > > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 47
> > > +++++++++++++++++-- drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > | 6 +++ 5 files changed, 60 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > b/drivers/gpu/drm/i915/display/intel_display.c index
> > > 919f5ac844c8..557462208462 100644 ---
> > > a/drivers/gpu/drm/i915/display/intel_display.c +++
> > > b/drivers/gpu/drm/i915/display/intel_display.c @@ -16653,6
> > > +16653,13 @@ static void intel_modeset_readout_hw_state(struct
> > > drm_device *dev) pll->on = pll->info->funcs->get_hw_state(dev_priv,
> > > pll, &pll->state.hw_state);
> > > +
> > > + if (IS_ELKHARTLAKE(dev_priv) && pll->on &&
> > > + pll->info->id == DPLL_ID_EHL_DPLL4) {
> > > + pll->wakeref =
> > > intel_display_power_get(dev_priv,
> > > +
> > > POWER_DOMAIN_DPLL_DC_OFF);
> > > + }
> > > +
> > > pll->state.crtc_mask = 0;
> > > for_each_intel_crtc(dev, crtc) {
> > > struct intel_crtc_state *crtc_state =
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > b/drivers/gpu/drm/i915/display/intel_display_power.c index
> > > c19b958461ca..7437fc71d289 100644 ---
> > > a/drivers/gpu/drm/i915/display/intel_display_power.c +++
> > > b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -118,6
> > > +118,8 @@ intel_display_power_domain_str(enum
> > > intel_display_power_domain domain) return "MODESET"; case
> > > POWER_DOMAIN_GT_IRQ: return "GT_IRQ";
> > > + case POWER_DOMAIN_DPLL_DC_OFF:
> > > + return "DPLL_DC_OFF";
> > > default:
> > > MISSING_CASE(domain);
> > > return "?";
> > > @@ -2455,6 +2457,7 @@ void intel_display_power_put(struct
> > > drm_i915_private *dev_priv, ICL_PW_2_POWER_DOMAINS
> > > | \ BIT_ULL(POWER_DOMAIN_MODESET)
> > > | \ BIT_ULL(POWER_DOMAIN_AUX_A)
> > > | \
> > > + BIT_ULL(POWER_DOMAIN_DPLL_DC_OFF) |
> > > \ BIT_ULL(POWER_DOMAIN_INIT))
> > >
> > > #define ICL_DDI_IO_A_POWER_DOMAINS ( \
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
> > > b/drivers/gpu/drm/i915/display/intel_display_power.h index
> > > ff57b0a7fe59..8f43f7051a16 100644 ---
> > > a/drivers/gpu/drm/i915/display/intel_display_power.h +++
> > > b/drivers/gpu/drm/i915/display/intel_display_power.h @@ -59,6 +59,7
> > > @@ enum intel_display_power_domain { POWER_DOMAIN_GMBUS,
> > > POWER_DOMAIN_MODESET,
> > > POWER_DOMAIN_GT_IRQ,
> > > + POWER_DOMAIN_DPLL_DC_OFF,
> > > POWER_DOMAIN_INIT,
> > >
> > > POWER_DOMAIN_NUM,
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index
> > > f953971e7c3b..67cfe836286e 100644 ---
> > > a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++
> > > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -2905,6 +2905,9
> > > @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state
> > > *state, intel_atomic_get_new_crtc_state(state, crtc); struct
> > > icl_port_dpll *port_dpll =
> > > &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
> > > + struct drm_i915_private *dev_priv =
> > > to_i915(crtc->base.dev);
> > > + enum port port = encoder->port;
> > > + bool has_dpll4 = false;
> > >
> > > if (!icl_calc_dpll_state(crtc_state, encoder,
> > > &port_dpll->hw_state)) { DRM_DEBUG_KMS("Could not calculate combo
> > > PHY PLL state.\n"); @@ -2912,10 +2915,14 @@ static bool
> > > icl_get_combo_phy_dpll(struct intel_atomic_state *state, return
> > > false; }
> > >
> > > + if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A)
> > > + has_dpll4 = true;
> > > +
> > > port_dpll->pll = intel_find_shared_dpll(state, crtc,
> > > &port_dpll->hw_state,
> > > DPLL_ID_ICL_DPLL0,
> > > - DPLL_ID_ICL_DPLL1);
> > > + has_dpll4 ?
> > > DPLL_ID_EHL_DPLL4
> > > + :
> > > DPLL_ID_ICL_DPLL1); if (!port_dpll->pll) {
> > > DRM_DEBUG_KMS("No combo PHY PLL found for port
> > > %c\n", port_name(encoder->port));
> > > @@ -3119,8 +3126,14 @@ static bool combo_pll_get_hw_state(struct
> > > drm_i915_private *dev_priv, struct intel_shared_dpll *pll,
> > > struct intel_dpll_hw_state
> > > *hw_state) {
> > > - return icl_pll_get_hw_state(dev_priv, pll, hw_state,
> > > -
> > > CNL_DPLL_ENABLE(pll->info->id));
> > > + i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
> > > +
> > > + if (IS_ELKHARTLAKE(dev_priv) &&
> > > + pll->info->id == DPLL_ID_EHL_DPLL4) {
> > > + enable_reg = MG_PLL_ENABLE(0);
> > > + }
> > > +
> > > + return icl_pll_get_hw_state(dev_priv, pll, hw_state,
> > > enable_reg); }
> > >
> > > static bool tbt_pll_get_hw_state(struct drm_i915_private *dev_priv,
> > > @@ -3231,6 +3244,19 @@ static void combo_pll_enable(struct
> > > drm_i915_private *dev_priv, {
> > > i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
> > >
> > > + if (IS_ELKHARTLAKE(dev_priv) &&
> > > + pll->info->id == DPLL_ID_EHL_DPLL4) {
> > > + enable_reg = MG_PLL_ENABLE(0);
> > > +
> > > + /*
> > > + * We need to disable DC states when this DPLL is
> > > enabled.
> > > + * This can be done by taking a reference on DPLL4
> > > power
> > > + * domain.
> > > + */
> > > + pll->wakeref = intel_display_power_get(dev_priv,
> > > +
> > > POWER_DOMAIN_DPLL_DC_OFF);
> > > + }
> > > +
> > > icl_pll_power_enable(dev_priv, pll, enable_reg);
> > >
> > > icl_dpll_write(dev_priv, pll);
> > > @@ -3326,7 +3352,19 @@ static void icl_pll_disable(struct
> > > drm_i915_private *dev_priv, static void combo_pll_disable(struct
> > > drm_i915_private *dev_priv, struct intel_shared_dpll *pll)
> > > {
> > > - icl_pll_disable(dev_priv, pll,
> > > CNL_DPLL_ENABLE(pll->info->id));
> > > + i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
> > > +
> > > + if (IS_ELKHARTLAKE(dev_priv) &&
> > > + pll->info->id == DPLL_ID_EHL_DPLL4) {
> > > + enable_reg = MG_PLL_ENABLE(0);
> > > + icl_pll_disable(dev_priv, pll, enable_reg);
> > > +
> > > + intel_display_power_put(dev_priv,
> > > POWER_DOMAIN_DPLL_DC_OFF,
> > > + pll->wakeref);
> > > + return;
> > > + }
> > > +
> > > + icl_pll_disable(dev_priv, pll, enable_reg);
> > > }
> > >
> > > static void tbt_pll_disable(struct drm_i915_private *dev_priv,
> > > @@ -3406,6 +3444,7 @@ static const struct intel_dpll_mgr
> > > icl_pll_mgr = { static const struct dpll_info ehl_plls[] = {
> > > { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
> > > { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
> > > + { "DPLL 4", &combo_pll_funcs, DPLL_ID_EHL_DPLL4, 0 },
> > > { },
> > > };
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h index
> > > 1668f8116908..4c2c5e93aff3 100644 ---
> > > a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h +++
> > > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h @@ -28,6 +28,7 @@
> > > #include <linux/types.h>
> > >
> > > #include "intel_display.h"
> > > +#include "intel_wakeref.h"
> > >
> > > /*FIXME: Move this to a more appropriate place. */
> > > #define abs_diff(a, b) ({ \
> > > @@ -118,6 +119,10 @@ enum intel_dpll_id {
> > > * @DPLL_ID_ICL_DPLL1: ICL combo PHY DPLL1
> > > */
> > > DPLL_ID_ICL_DPLL1 = 1,
> > > + /**
> > > + * @DPLL_ID_EHL_DPLL4: EHL combo PHY DPLL4
> > > + */
> > > + DPLL_ID_EHL_DPLL4 = 2,
> >
> > While looking at the TGL stuff I noticed that this ID seems to be
> > wrong. We use this to generate the register offsets but the docs show
> > the following:
> >
> > DPLL0_CFGCR0 0x164000
> > DPLL1_CFGCR0 0x164080
> > TBTPLL_CFGCR0 0x164100
> > DPLL4_CFGCR0 0x164200
> >
> > So the DPLL4 accesses will now land on TBTPLL. The ID if DPLL4 should
> > really be 4 I guess.
> Yes, looks like it should be 4 indeed. However, I was wondering what is
> the best way to address this issue. Simply changing the id to 4 isn't
> going to work as there are many places in intel_dpll_mgr.c that assume
> the dpll id to be the index in the dev_priv->shared_dplls array as
> stated in the definition of dpll_info:
> /**
> * @id: unique indentifier for this DPLL; should match the
> index in the
> * dev_priv->shared_dplls array
> */
> enum intel_dpll_id id;
Ugh. That's a bit unfortunate. I guess it would be nice to abstrace that
away and either allow the array(s) to be sparsely populated, or decouple
the index from the id.
>
> Should I change all these places that make this assumption and fix them?
> Or, should I just simply add an if condition around cr0 and cr1 accesses
> in icl_dpll_write and icl_pll_get_hw_state?
I guess we can go with the simple solution as a quick fix.
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] drm/i915/ehl: Use an id of 4 while accessing DPLL4's CR0 and CR1
2019-07-17 2:13 ` [PATCH] drm/i915/ehl: Use an id of 4 while accessing DPLL4's CR0 and CR1 Vivek Kasireddy
@ 2019-07-18 17:29 ` Ville Syrjälä
0 siblings, 0 replies; 12+ messages in thread
From: Ville Syrjälä @ 2019-07-18 17:29 UTC (permalink / raw)
To: Vivek Kasireddy; +Cc: intel-gfx
On Tue, Jul 16, 2019 at 07:13:16PM -0700, Vivek Kasireddy wrote:
> Although, DPLL4 enable and disable is associated with MGPLL1_ENABLE
> register, we can use ICL_DPLL_CFGCR0/CR1 macros to access this dpll's
> CR0 and CR1 registers by passing an id of 4 to these macros.
>
> Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Vivek Kasireddy <vivek.kasireddy@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 18 ++++++++++++++----
> 1 file changed, 14 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 319a26a1ec10..f9bdf8514a53 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -3127,8 +3127,13 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
> hw_state->cfgcr0 = I915_READ(TGL_DPLL_CFGCR0(id));
> hw_state->cfgcr1 = I915_READ(TGL_DPLL_CFGCR1(id));
> } else {
> - hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
> - hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
> + if (IS_ELKHARTLAKE(dev_priv) && id == DPLL_ID_EHL_DPLL4) {
> + hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(4));
> + hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(4));
> + } else {
> + hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
> + hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
> + }
> }
>
> ret = true;
> @@ -3169,8 +3174,13 @@ static void icl_dpll_write(struct drm_i915_private *dev_priv,
> cfgcr0_reg = TGL_DPLL_CFGCR0(id);
> cfgcr1_reg = TGL_DPLL_CFGCR1(id);
> } else {
> - cfgcr0_reg = ICL_DPLL_CFGCR0(id);
> - cfgcr1_reg = ICL_DPLL_CFGCR1(id);
> + if (IS_ELKHARTLAKE(dev_priv) && id == DPLL_ID_EHL_DPLL4) {
> + cfgcr0_reg = ICL_DPLL_CFGCR0(4);
> + cfgcr1_reg = ICL_DPLL_CFGCR1(4);
> + } else {
> + cfgcr0_reg = ICL_DPLL_CFGCR0(id);
> + cfgcr1_reg = ICL_DPLL_CFGCR1(id);
> + }
I was a bit worried this would also affect other parts of the code, but
at least ICL_DPCLKA_CFGCR0_DDI_CLK_SEL() seems to do the right thing
with the id==2, and I couldn't immediately spot other issues.
Also surprising that ci didn't get confused by the fact that this was posted
as a reply to another series. Generally you should avoid replying with
anything except direct replacements for the original patches in the
series.
Pushed to dinq. Thanks for the patch.
> }
>
> I915_WRITE(cfgcr0_reg, hw_state->cfgcr0);
> --
> 2.21.0
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2019-07-18 17:29 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-07-03 23:03 [PATCH] drm/i915/ehl: Add support for DPLL4 (v10) Vivek Kasireddy
2019-07-03 23:50 ` ✓ Fi.CI.BAT: success for " Patchwork
2019-07-05 3:11 ` ✗ Fi.CI.IGT: failure " Patchwork
2019-07-05 10:23 ` Ville Syrjälä
2019-07-05 10:28 ` [PATCH] " Ville Syrjälä
2019-07-10 18:47 ` Ville Syrjälä
2019-07-17 1:54 ` Vivek Kasireddy
2019-07-18 17:14 ` Ville Syrjälä
2019-07-17 2:13 ` [PATCH] drm/i915/ehl: Use an id of 4 while accessing DPLL4's CR0 and CR1 Vivek Kasireddy
2019-07-18 17:29 ` Ville Syrjälä
2019-07-17 3:16 ` ✓ Fi.CI.BAT: success for drm/i915/ehl: Add support for DPLL4 (v10) (rev2) Patchwork
2019-07-17 4:27 ` ✓ Fi.CI.IGT: " Patchwork
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