* [PATCH 0/3] media: Add support for Cadence CSI2TX version 2.1 @ 2019-07-18 11:15 ` Jan Kotas 0 siblings, 0 replies; 14+ messages in thread From: Jan Kotas @ 2019-07-18 11:15 UTC (permalink / raw) To: maxime.ripard, mchehab, robh+dt, mark.rutland Cc: linux-media, devicetree, linux-kernel, Jan Kotas This patchset adds support for Cadence CSI2TX controller version 2.1. Existing compatibility with v1.3 is maintained. Jan Kotas (3): media: dt-bindings: Update bindings for Cadence CSI2TX version 2.1 media: Add lane checks for Cadence CSI2TX media: Add support for Cadence CSI2TX 2.1 .../devicetree/bindings/media/cdns,csi2tx.txt | 3 +- drivers/media/platform/cadence/cdns-csi2tx.c | 155 ++++++++++++++++----- 2 files changed, 125 insertions(+), 33 deletions(-) -- 2.15.0 ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 0/3] media: Add support for Cadence CSI2TX version 2.1 @ 2019-07-18 11:15 ` Jan Kotas 0 siblings, 0 replies; 14+ messages in thread From: Jan Kotas @ 2019-07-18 11:15 UTC (permalink / raw) To: maxime.ripard, mchehab, robh+dt, mark.rutland Cc: linux-media, devicetree, linux-kernel, Jan Kotas This patchset adds support for Cadence CSI2TX controller version 2.1. Existing compatibility with v1.3 is maintained. Jan Kotas (3): media: dt-bindings: Update bindings for Cadence CSI2TX version 2.1 media: Add lane checks for Cadence CSI2TX media: Add support for Cadence CSI2TX 2.1 .../devicetree/bindings/media/cdns,csi2tx.txt | 3 +- drivers/media/platform/cadence/cdns-csi2tx.c | 155 ++++++++++++++++----- 2 files changed, 125 insertions(+), 33 deletions(-) -- 2.15.0 ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 1/3] media: dt-bindings: Update bindings for Cadence CSI2TX version 2.1 2019-07-18 11:15 ` Jan Kotas @ 2019-07-18 11:15 ` Jan Kotas -1 siblings, 0 replies; 14+ messages in thread From: Jan Kotas @ 2019-07-18 11:15 UTC (permalink / raw) To: maxime.ripard, mchehab, robh+dt, mark.rutland Cc: linux-media, devicetree, linux-kernel, Jan Kotas This patch adds a DT bindings documentation for Cadence CSI2TX v2.1 controller. Signed-off-by: Jan Kotas <jank@cadence.com> --- Documentation/devicetree/bindings/media/cdns,csi2tx.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/media/cdns,csi2tx.txt b/Documentation/devicetree/bindings/media/cdns,csi2tx.txt index 459c6e332..751b9edf1 100644 --- a/Documentation/devicetree/bindings/media/cdns,csi2tx.txt +++ b/Documentation/devicetree/bindings/media/cdns,csi2tx.txt @@ -5,7 +5,8 @@ The Cadence MIPI-CSI2 TX controller is a CSI-2 bridge supporting up to 4 CSI lanes in output, and up to 4 different pixel streams in input. Required properties: - - compatible: must be set to "cdns,csi2tx" + - compatible: must be set to "cdns,csi2tx" or "cdns,csi2tx-1.3" + for version 1.3 of the controller, "cdns,csi2tx-2.1" for v2.1 - reg: base address and size of the memory mapped region - clocks: phandles to the clocks driving the controller - clock-names: must contain: -- 2.15.0 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 1/3] media: dt-bindings: Update bindings for Cadence CSI2TX version 2.1 @ 2019-07-18 11:15 ` Jan Kotas 0 siblings, 0 replies; 14+ messages in thread From: Jan Kotas @ 2019-07-18 11:15 UTC (permalink / raw) To: maxime.ripard, mchehab, robh+dt, mark.rutland Cc: linux-media, devicetree, linux-kernel, Jan Kotas This patch adds a DT bindings documentation for Cadence CSI2TX v2.1 controller. Signed-off-by: Jan Kotas <jank@cadence.com> --- Documentation/devicetree/bindings/media/cdns,csi2tx.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/media/cdns,csi2tx.txt b/Documentation/devicetree/bindings/media/cdns,csi2tx.txt index 459c6e332..751b9edf1 100644 --- a/Documentation/devicetree/bindings/media/cdns,csi2tx.txt +++ b/Documentation/devicetree/bindings/media/cdns,csi2tx.txt @@ -5,7 +5,8 @@ The Cadence MIPI-CSI2 TX controller is a CSI-2 bridge supporting up to 4 CSI lanes in output, and up to 4 different pixel streams in input. Required properties: - - compatible: must be set to "cdns,csi2tx" + - compatible: must be set to "cdns,csi2tx" or "cdns,csi2tx-1.3" + for version 1.3 of the controller, "cdns,csi2tx-2.1" for v2.1 - reg: base address and size of the memory mapped region - clocks: phandles to the clocks driving the controller - clock-names: must contain: -- 2.15.0 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH 1/3] media: dt-bindings: Update bindings for Cadence CSI2TX version 2.1 2019-07-18 11:15 ` Jan Kotas (?) @ 2019-07-20 8:26 ` Maxime Ripard -1 siblings, 0 replies; 14+ messages in thread From: Maxime Ripard @ 2019-07-20 8:26 UTC (permalink / raw) To: Jan Kotas Cc: mchehab, robh+dt, mark.rutland, linux-media, devicetree, linux-kernel [-- Attachment #1: Type: text/plain, Size: 337 bytes --] On Thu, Jul 18, 2019 at 12:15:07PM +0100, Jan Kotas wrote: > This patch adds a DT bindings documentation for > Cadence CSI2TX v2.1 controller. > > Signed-off-by: Jan Kotas <jank@cadence.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 2/3] media: Add lane checks for Cadence CSI2TX 2019-07-18 11:15 ` Jan Kotas @ 2019-07-18 11:15 ` Jan Kotas -1 siblings, 0 replies; 14+ messages in thread From: Jan Kotas @ 2019-07-18 11:15 UTC (permalink / raw) To: maxime.ripard, mchehab, robh+dt, mark.rutland Cc: linux-media, devicetree, linux-kernel, Jan Kotas This patch adds line checks for CSI2TX, to prevent clock lane being used as a data lane. Signed-off-by: Jan Kotas <jank@cadence.com> --- drivers/media/platform/cadence/cdns-csi2tx.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/cadence/cdns-csi2tx.c b/drivers/media/platform/cadence/cdns-csi2tx.c index 5042d053b..232259c71 100644 --- a/drivers/media/platform/cadence/cdns-csi2tx.c +++ b/drivers/media/platform/cadence/cdns-csi2tx.c @@ -2,7 +2,7 @@ /* * Driver for Cadence MIPI-CSI2 TX Controller * - * Copyright (C) 2017-2018 Cadence Design Systems Inc. + * Copyright (C) 2017-2019 Cadence Design Systems Inc. */ #include <linux/clk.h> @@ -434,7 +434,7 @@ static int csi2tx_check_lanes(struct csi2tx_priv *csi2tx) { struct v4l2_fwnode_endpoint v4l2_ep = { .bus_type = 0 }; struct device_node *ep; - int ret; + int ret, i; ep = of_graph_get_endpoint_by_regs(csi2tx->dev->of_node, 0, 0); if (!ep) @@ -461,6 +461,15 @@ static int csi2tx_check_lanes(struct csi2tx_priv *csi2tx) goto out; } + for (i = 0; i < csi2tx->num_lanes; i++) { + if (v4l2_ep.bus.mipi_csi2.data_lanes[i] < 1) { + dev_err(csi2tx->dev, "Invalid lane[%d] number: %u\n", + i, v4l2_ep.bus.mipi_csi2.data_lanes[i]); + ret = -EINVAL; + goto out; + } + } + memcpy(csi2tx->lanes, v4l2_ep.bus.mipi_csi2.data_lanes, sizeof(csi2tx->lanes)); -- 2.15.0 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 2/3] media: Add lane checks for Cadence CSI2TX @ 2019-07-18 11:15 ` Jan Kotas 0 siblings, 0 replies; 14+ messages in thread From: Jan Kotas @ 2019-07-18 11:15 UTC (permalink / raw) To: maxime.ripard, mchehab, robh+dt, mark.rutland Cc: linux-media, devicetree, linux-kernel, Jan Kotas This patch adds line checks for CSI2TX, to prevent clock lane being used as a data lane. Signed-off-by: Jan Kotas <jank@cadence.com> --- drivers/media/platform/cadence/cdns-csi2tx.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/cadence/cdns-csi2tx.c b/drivers/media/platform/cadence/cdns-csi2tx.c index 5042d053b..232259c71 100644 --- a/drivers/media/platform/cadence/cdns-csi2tx.c +++ b/drivers/media/platform/cadence/cdns-csi2tx.c @@ -2,7 +2,7 @@ /* * Driver for Cadence MIPI-CSI2 TX Controller * - * Copyright (C) 2017-2018 Cadence Design Systems Inc. + * Copyright (C) 2017-2019 Cadence Design Systems Inc. */ #include <linux/clk.h> @@ -434,7 +434,7 @@ static int csi2tx_check_lanes(struct csi2tx_priv *csi2tx) { struct v4l2_fwnode_endpoint v4l2_ep = { .bus_type = 0 }; struct device_node *ep; - int ret; + int ret, i; ep = of_graph_get_endpoint_by_regs(csi2tx->dev->of_node, 0, 0); if (!ep) @@ -461,6 +461,15 @@ static int csi2tx_check_lanes(struct csi2tx_priv *csi2tx) goto out; } + for (i = 0; i < csi2tx->num_lanes; i++) { + if (v4l2_ep.bus.mipi_csi2.data_lanes[i] < 1) { + dev_err(csi2tx->dev, "Invalid lane[%d] number: %u\n", + i, v4l2_ep.bus.mipi_csi2.data_lanes[i]); + ret = -EINVAL; + goto out; + } + } + memcpy(csi2tx->lanes, v4l2_ep.bus.mipi_csi2.data_lanes, sizeof(csi2tx->lanes)); -- 2.15.0 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH 2/3] media: Add lane checks for Cadence CSI2TX 2019-07-18 11:15 ` Jan Kotas (?) @ 2019-07-18 11:52 ` Marc Gonzalez 2019-07-18 12:07 ` Jan Kotas -1 siblings, 1 reply; 14+ messages in thread From: Marc Gonzalez @ 2019-07-18 11:52 UTC (permalink / raw) To: Jan Kotas; +Cc: linux-media, LKML On 18/07/2019 13:15, Jan Kotas wrote: > This patch adds line checks for CSI2TX, to prevent > clock lane being used as a data lane. "line checks" or "lane checks? ^_^ NB: commit messages may be up to 72-character-wide ;-) (No need to line-wrap at 50) Regards. ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 2/3] media: Add lane checks for Cadence CSI2TX 2019-07-18 11:52 ` Marc Gonzalez @ 2019-07-18 12:07 ` Jan Kotas 0 siblings, 0 replies; 14+ messages in thread From: Jan Kotas @ 2019-07-18 12:07 UTC (permalink / raw) To: Marc Gonzalez; +Cc: Jan Kotas, linux-media, LKML > On 18 Jul 2019, at 13:52, Marc Gonzalez <marc.w.gonzalez@free.fr> wrote: > > EXTERNAL MAIL > > > On 18/07/2019 13:15, Jan Kotas wrote: > >> This patch adds line checks for CSI2TX, to prevent >> clock lane being used as a data lane. > > "line checks" or "lane checks? ^_^ Yes, you’re right, should be lane checks :) Regards, Jan > > NB: commit messages may be up to 72-character-wide ;-) > (No need to line-wrap at 50) > > Regards. ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 2/3] media: Add lane checks for Cadence CSI2TX 2019-07-18 11:15 ` Jan Kotas (?) (?) @ 2019-07-20 8:26 ` Maxime Ripard -1 siblings, 0 replies; 14+ messages in thread From: Maxime Ripard @ 2019-07-20 8:26 UTC (permalink / raw) To: Jan Kotas Cc: mchehab, robh+dt, mark.rutland, linux-media, devicetree, linux-kernel [-- Attachment #1: Type: text/plain, Size: 357 bytes --] 65;5603;1c On Thu, Jul 18, 2019 at 12:15:08PM +0100, Jan Kotas wrote: > This patch adds line checks for CSI2TX, to prevent > clock lane being used as a data lane. > > Signed-off-by: Jan Kotas <jank@cadence.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 3/3] media: Add support for Cadence CSI2TX 2.1 2019-07-18 11:15 ` Jan Kotas @ 2019-07-18 11:15 ` Jan Kotas -1 siblings, 0 replies; 14+ messages in thread From: Jan Kotas @ 2019-07-18 11:15 UTC (permalink / raw) To: maxime.ripard, mchehab, robh+dt, mark.rutland Cc: linux-media, devicetree, linux-kernel, Jan Kotas This patch adds support for CSI2TX v2.1 version of the controller. Signed-off-by: Jan Kotas <jank@cadence.com> --- drivers/media/platform/cadence/cdns-csi2tx.c | 142 +++++++++++++++++++++------ 1 file changed, 112 insertions(+), 30 deletions(-) diff --git a/drivers/media/platform/cadence/cdns-csi2tx.c b/drivers/media/platform/cadence/cdns-csi2tx.c index 232259c71..e4d08acfb 100644 --- a/drivers/media/platform/cadence/cdns-csi2tx.c +++ b/drivers/media/platform/cadence/cdns-csi2tx.c @@ -52,6 +52,17 @@ #define CSI2TX_STREAM_IF_CFG_REG(n) (0x100 + (n) * 4) #define CSI2TX_STREAM_IF_CFG_FILL_LEVEL(n) ((n) & 0x1f) +/* CSI2TX V2 Registers */ +#define CSI2TX_V2_DPHY_CFG_REG 0x28 +#define CSI2TX_V2_DPHY_CFG_RESET BIT(16) +#define CSI2TX_V2_DPHY_CFG_CLOCK_MODE BIT(10) +#define CSI2TX_V2_DPHY_CFG_MODE_MASK GENMASK(9, 8) +#define CSI2TX_V2_DPHY_CFG_MODE_LPDT (2 << 8) +#define CSI2TX_V2_DPHY_CFG_MODE_HS (1 << 8) +#define CSI2TX_V2_DPHY_CFG_MODE_ULPS (0 << 8) +#define CSI2TX_V2_DPHY_CFG_CLK_ENABLE BIT(4) +#define CSI2TX_V2_DPHY_CFG_LANE_ENABLE(n) BIT(n) + #define CSI2TX_LANES_MAX 4 #define CSI2TX_STREAMS_MAX 4 @@ -70,6 +81,13 @@ struct csi2tx_fmt { u32 bpp; }; +struct csi2tx_priv; + +/* CSI2TX Variant Operations */ +struct csi2tx_vops { + void (*dphy_setup)(struct csi2tx_priv *csi2tx); +}; + struct csi2tx_priv { struct device *dev; unsigned int count; @@ -82,6 +100,8 @@ struct csi2tx_priv { void __iomem *base; + struct csi2tx_vops *vops; + struct clk *esc_clk; struct clk *p_clk; struct clk *pixel_clk[CSI2TX_STREAMS_MAX]; @@ -209,53 +229,92 @@ static const struct v4l2_subdev_pad_ops csi2tx_pad_ops = { .set_fmt = csi2tx_set_pad_format, }; -static void csi2tx_reset(struct csi2tx_priv *csi2tx) +/* Set Wake Up value in the D-PHY */ +static void csi2tx_dphy_set_wakeup(struct csi2tx_priv *csi2tx) { - writel(CSI2TX_CONFIG_SRST_REQ, csi2tx->base + CSI2TX_CONFIG_REG); - - udelay(10); + writel(CSI2TX_DPHY_CLK_WAKEUP_ULPS_CYCLES(32), + csi2tx->base + CSI2TX_DPHY_CLK_WAKEUP_REG); } -static int csi2tx_start(struct csi2tx_priv *csi2tx) +/* + * Finishes the D-PHY initialization + * reg dphy cfg value to be used + */ +static void csi2tx_dphy_init_finish(struct csi2tx_priv *csi2tx, u32 reg) { - struct media_entity *entity = &csi2tx->subdev.entity; - struct media_link *link; unsigned int i; - u32 reg; - csi2tx_reset(csi2tx); + udelay(10); - writel(CSI2TX_CONFIG_CFG_REQ, csi2tx->base + CSI2TX_CONFIG_REG); + /* Enable our (clock and data) lanes */ + reg |= CSI2TX_DPHY_CFG_CLK_ENABLE; + for (i = 0; i < csi2tx->num_lanes; i++) + reg |= CSI2TX_DPHY_CFG_LANE_ENABLE(csi2tx->lanes[i] - 1); + writel(reg, csi2tx->base + CSI2TX_DPHY_CFG_REG); udelay(10); - /* Configure our PPI interface with the D-PHY */ - writel(CSI2TX_DPHY_CLK_WAKEUP_ULPS_CYCLES(32), - csi2tx->base + CSI2TX_DPHY_CLK_WAKEUP_REG); + /* Switch to HS mode */ + reg &= ~CSI2TX_DPHY_CFG_MODE_MASK; + writel(reg | CSI2TX_DPHY_CFG_MODE_HS, + csi2tx->base + CSI2TX_DPHY_CFG_REG); +} + +/* Configures D-PHY in CSIv1.3 */ +static void csi2tx_dphy_setup(struct csi2tx_priv *csi2tx) +{ + u32 reg; + unsigned int i; + + csi2tx_dphy_set_wakeup(csi2tx); /* Put our lanes (clock and data) out of reset */ reg = CSI2TX_DPHY_CFG_CLK_RESET | CSI2TX_DPHY_CFG_MODE_LPDT; for (i = 0; i < csi2tx->num_lanes; i++) - reg |= CSI2TX_DPHY_CFG_LANE_RESET(csi2tx->lanes[i]); + reg |= CSI2TX_DPHY_CFG_LANE_RESET(csi2tx->lanes[i] - 1); writel(reg, csi2tx->base + CSI2TX_DPHY_CFG_REG); - udelay(10); + csi2tx_dphy_init_finish(csi2tx, reg); +} - /* Enable our (clock and data) lanes */ - reg |= CSI2TX_DPHY_CFG_CLK_ENABLE; - for (i = 0; i < csi2tx->num_lanes; i++) - reg |= CSI2TX_DPHY_CFG_LANE_ENABLE(csi2tx->lanes[i]); - writel(reg, csi2tx->base + CSI2TX_DPHY_CFG_REG); +/* Configures D-PHY in CSIv2 */ +static void csi2tx_v2_dphy_setup(struct csi2tx_priv *csi2tx) +{ + u32 reg; + + csi2tx_dphy_set_wakeup(csi2tx); + + /* Put our lanes (clock and data) out of reset */ + reg = CSI2TX_V2_DPHY_CFG_RESET | CSI2TX_V2_DPHY_CFG_MODE_LPDT; + writel(reg, csi2tx->base + CSI2TX_V2_DPHY_CFG_REG); + + csi2tx_dphy_init_finish(csi2tx, reg); +} + +static void csi2tx_reset(struct csi2tx_priv *csi2tx) +{ + writel(CSI2TX_CONFIG_SRST_REQ, csi2tx->base + CSI2TX_CONFIG_REG); udelay(10); +} - /* Switch to HS mode */ - reg &= ~CSI2TX_DPHY_CFG_MODE_MASK; - writel(reg | CSI2TX_DPHY_CFG_MODE_HS, - csi2tx->base + CSI2TX_DPHY_CFG_REG); +static int csi2tx_start(struct csi2tx_priv *csi2tx) +{ + struct media_entity *entity = &csi2tx->subdev.entity; + struct media_link *link; + unsigned int i; + + csi2tx_reset(csi2tx); + + writel(CSI2TX_CONFIG_CFG_REQ, csi2tx->base + CSI2TX_CONFIG_REG); udelay(10); + if (csi2tx->vops && csi2tx->vops->dphy_setup) { + csi2tx->vops->dphy_setup(csi2tx); + udelay(10); + } + /* * Create a static mapping between the CSI virtual channels * and the input streams. @@ -478,9 +537,35 @@ static int csi2tx_check_lanes(struct csi2tx_priv *csi2tx) return ret; } +static const struct csi2tx_vops csi2tx_vops = { + .dphy_setup = csi2tx_dphy_setup, +}; + +static const struct csi2tx_vops csi2tx_v2_vops = { + .dphy_setup = csi2tx_v2_dphy_setup, +}; + +static const struct of_device_id csi2tx_of_table[] = { + { + .compatible = "cdns,csi2tx", + .data = &csi2tx_vops + }, + { + .compatible = "cdns,csi2tx-1.3", + .data = &csi2tx_vops + }, + { + .compatible = "cdns,csi2tx-2.1", + .data = &csi2tx_v2_vops + }, + { } +}; +MODULE_DEVICE_TABLE(of, csi2tx_of_table); + static int csi2tx_probe(struct platform_device *pdev) { struct csi2tx_priv *csi2tx; + const struct of_device_id *of_id; unsigned int i; int ret; @@ -495,6 +580,9 @@ static int csi2tx_probe(struct platform_device *pdev) if (ret) goto err_free_priv; + of_id = of_match_node(csi2tx_of_table, pdev->dev.of_node); + csi2tx->vops = (struct csi2tx_vops *)of_id->data; + v4l2_subdev_init(&csi2tx->subdev, &csi2tx_subdev_ops); csi2tx->subdev.owner = THIS_MODULE; csi2tx->subdev.dev = &pdev->dev; @@ -552,12 +640,6 @@ static int csi2tx_remove(struct platform_device *pdev) return 0; } -static const struct of_device_id csi2tx_of_table[] = { - { .compatible = "cdns,csi2tx" }, - { }, -}; -MODULE_DEVICE_TABLE(of, csi2tx_of_table); - static struct platform_driver csi2tx_driver = { .probe = csi2tx_probe, .remove = csi2tx_remove, -- 2.15.0 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 3/3] media: Add support for Cadence CSI2TX 2.1 @ 2019-07-18 11:15 ` Jan Kotas 0 siblings, 0 replies; 14+ messages in thread From: Jan Kotas @ 2019-07-18 11:15 UTC (permalink / raw) To: maxime.ripard, mchehab, robh+dt, mark.rutland Cc: linux-media, devicetree, linux-kernel, Jan Kotas This patch adds support for CSI2TX v2.1 version of the controller. Signed-off-by: Jan Kotas <jank@cadence.com> --- drivers/media/platform/cadence/cdns-csi2tx.c | 142 +++++++++++++++++++++------ 1 file changed, 112 insertions(+), 30 deletions(-) diff --git a/drivers/media/platform/cadence/cdns-csi2tx.c b/drivers/media/platform/cadence/cdns-csi2tx.c index 232259c71..e4d08acfb 100644 --- a/drivers/media/platform/cadence/cdns-csi2tx.c +++ b/drivers/media/platform/cadence/cdns-csi2tx.c @@ -52,6 +52,17 @@ #define CSI2TX_STREAM_IF_CFG_REG(n) (0x100 + (n) * 4) #define CSI2TX_STREAM_IF_CFG_FILL_LEVEL(n) ((n) & 0x1f) +/* CSI2TX V2 Registers */ +#define CSI2TX_V2_DPHY_CFG_REG 0x28 +#define CSI2TX_V2_DPHY_CFG_RESET BIT(16) +#define CSI2TX_V2_DPHY_CFG_CLOCK_MODE BIT(10) +#define CSI2TX_V2_DPHY_CFG_MODE_MASK GENMASK(9, 8) +#define CSI2TX_V2_DPHY_CFG_MODE_LPDT (2 << 8) +#define CSI2TX_V2_DPHY_CFG_MODE_HS (1 << 8) +#define CSI2TX_V2_DPHY_CFG_MODE_ULPS (0 << 8) +#define CSI2TX_V2_DPHY_CFG_CLK_ENABLE BIT(4) +#define CSI2TX_V2_DPHY_CFG_LANE_ENABLE(n) BIT(n) + #define CSI2TX_LANES_MAX 4 #define CSI2TX_STREAMS_MAX 4 @@ -70,6 +81,13 @@ struct csi2tx_fmt { u32 bpp; }; +struct csi2tx_priv; + +/* CSI2TX Variant Operations */ +struct csi2tx_vops { + void (*dphy_setup)(struct csi2tx_priv *csi2tx); +}; + struct csi2tx_priv { struct device *dev; unsigned int count; @@ -82,6 +100,8 @@ struct csi2tx_priv { void __iomem *base; + struct csi2tx_vops *vops; + struct clk *esc_clk; struct clk *p_clk; struct clk *pixel_clk[CSI2TX_STREAMS_MAX]; @@ -209,53 +229,92 @@ static const struct v4l2_subdev_pad_ops csi2tx_pad_ops = { .set_fmt = csi2tx_set_pad_format, }; -static void csi2tx_reset(struct csi2tx_priv *csi2tx) +/* Set Wake Up value in the D-PHY */ +static void csi2tx_dphy_set_wakeup(struct csi2tx_priv *csi2tx) { - writel(CSI2TX_CONFIG_SRST_REQ, csi2tx->base + CSI2TX_CONFIG_REG); - - udelay(10); + writel(CSI2TX_DPHY_CLK_WAKEUP_ULPS_CYCLES(32), + csi2tx->base + CSI2TX_DPHY_CLK_WAKEUP_REG); } -static int csi2tx_start(struct csi2tx_priv *csi2tx) +/* + * Finishes the D-PHY initialization + * reg dphy cfg value to be used + */ +static void csi2tx_dphy_init_finish(struct csi2tx_priv *csi2tx, u32 reg) { - struct media_entity *entity = &csi2tx->subdev.entity; - struct media_link *link; unsigned int i; - u32 reg; - csi2tx_reset(csi2tx); + udelay(10); - writel(CSI2TX_CONFIG_CFG_REQ, csi2tx->base + CSI2TX_CONFIG_REG); + /* Enable our (clock and data) lanes */ + reg |= CSI2TX_DPHY_CFG_CLK_ENABLE; + for (i = 0; i < csi2tx->num_lanes; i++) + reg |= CSI2TX_DPHY_CFG_LANE_ENABLE(csi2tx->lanes[i] - 1); + writel(reg, csi2tx->base + CSI2TX_DPHY_CFG_REG); udelay(10); - /* Configure our PPI interface with the D-PHY */ - writel(CSI2TX_DPHY_CLK_WAKEUP_ULPS_CYCLES(32), - csi2tx->base + CSI2TX_DPHY_CLK_WAKEUP_REG); + /* Switch to HS mode */ + reg &= ~CSI2TX_DPHY_CFG_MODE_MASK; + writel(reg | CSI2TX_DPHY_CFG_MODE_HS, + csi2tx->base + CSI2TX_DPHY_CFG_REG); +} + +/* Configures D-PHY in CSIv1.3 */ +static void csi2tx_dphy_setup(struct csi2tx_priv *csi2tx) +{ + u32 reg; + unsigned int i; + + csi2tx_dphy_set_wakeup(csi2tx); /* Put our lanes (clock and data) out of reset */ reg = CSI2TX_DPHY_CFG_CLK_RESET | CSI2TX_DPHY_CFG_MODE_LPDT; for (i = 0; i < csi2tx->num_lanes; i++) - reg |= CSI2TX_DPHY_CFG_LANE_RESET(csi2tx->lanes[i]); + reg |= CSI2TX_DPHY_CFG_LANE_RESET(csi2tx->lanes[i] - 1); writel(reg, csi2tx->base + CSI2TX_DPHY_CFG_REG); - udelay(10); + csi2tx_dphy_init_finish(csi2tx, reg); +} - /* Enable our (clock and data) lanes */ - reg |= CSI2TX_DPHY_CFG_CLK_ENABLE; - for (i = 0; i < csi2tx->num_lanes; i++) - reg |= CSI2TX_DPHY_CFG_LANE_ENABLE(csi2tx->lanes[i]); - writel(reg, csi2tx->base + CSI2TX_DPHY_CFG_REG); +/* Configures D-PHY in CSIv2 */ +static void csi2tx_v2_dphy_setup(struct csi2tx_priv *csi2tx) +{ + u32 reg; + + csi2tx_dphy_set_wakeup(csi2tx); + + /* Put our lanes (clock and data) out of reset */ + reg = CSI2TX_V2_DPHY_CFG_RESET | CSI2TX_V2_DPHY_CFG_MODE_LPDT; + writel(reg, csi2tx->base + CSI2TX_V2_DPHY_CFG_REG); + + csi2tx_dphy_init_finish(csi2tx, reg); +} + +static void csi2tx_reset(struct csi2tx_priv *csi2tx) +{ + writel(CSI2TX_CONFIG_SRST_REQ, csi2tx->base + CSI2TX_CONFIG_REG); udelay(10); +} - /* Switch to HS mode */ - reg &= ~CSI2TX_DPHY_CFG_MODE_MASK; - writel(reg | CSI2TX_DPHY_CFG_MODE_HS, - csi2tx->base + CSI2TX_DPHY_CFG_REG); +static int csi2tx_start(struct csi2tx_priv *csi2tx) +{ + struct media_entity *entity = &csi2tx->subdev.entity; + struct media_link *link; + unsigned int i; + + csi2tx_reset(csi2tx); + + writel(CSI2TX_CONFIG_CFG_REQ, csi2tx->base + CSI2TX_CONFIG_REG); udelay(10); + if (csi2tx->vops && csi2tx->vops->dphy_setup) { + csi2tx->vops->dphy_setup(csi2tx); + udelay(10); + } + /* * Create a static mapping between the CSI virtual channels * and the input streams. @@ -478,9 +537,35 @@ static int csi2tx_check_lanes(struct csi2tx_priv *csi2tx) return ret; } +static const struct csi2tx_vops csi2tx_vops = { + .dphy_setup = csi2tx_dphy_setup, +}; + +static const struct csi2tx_vops csi2tx_v2_vops = { + .dphy_setup = csi2tx_v2_dphy_setup, +}; + +static const struct of_device_id csi2tx_of_table[] = { + { + .compatible = "cdns,csi2tx", + .data = &csi2tx_vops + }, + { + .compatible = "cdns,csi2tx-1.3", + .data = &csi2tx_vops + }, + { + .compatible = "cdns,csi2tx-2.1", + .data = &csi2tx_v2_vops + }, + { } +}; +MODULE_DEVICE_TABLE(of, csi2tx_of_table); + static int csi2tx_probe(struct platform_device *pdev) { struct csi2tx_priv *csi2tx; + const struct of_device_id *of_id; unsigned int i; int ret; @@ -495,6 +580,9 @@ static int csi2tx_probe(struct platform_device *pdev) if (ret) goto err_free_priv; + of_id = of_match_node(csi2tx_of_table, pdev->dev.of_node); + csi2tx->vops = (struct csi2tx_vops *)of_id->data; + v4l2_subdev_init(&csi2tx->subdev, &csi2tx_subdev_ops); csi2tx->subdev.owner = THIS_MODULE; csi2tx->subdev.dev = &pdev->dev; @@ -552,12 +640,6 @@ static int csi2tx_remove(struct platform_device *pdev) return 0; } -static const struct of_device_id csi2tx_of_table[] = { - { .compatible = "cdns,csi2tx" }, - { }, -}; -MODULE_DEVICE_TABLE(of, csi2tx_of_table); - static struct platform_driver csi2tx_driver = { .probe = csi2tx_probe, .remove = csi2tx_remove, -- 2.15.0 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH 3/3] media: Add support for Cadence CSI2TX 2.1 2019-07-18 11:15 ` Jan Kotas (?) @ 2019-07-20 8:25 ` Maxime Ripard 2019-07-22 7:07 ` Jan Kotas -1 siblings, 1 reply; 14+ messages in thread From: Maxime Ripard @ 2019-07-20 8:25 UTC (permalink / raw) To: Jan Kotas Cc: mchehab, robh+dt, mark.rutland, linux-media, devicetree, linux-kernel [-- Attachment #1: Type: text/plain, Size: 4320 bytes --] Hi, On Thu, Jul 18, 2019 at 12:15:09PM +0100, Jan Kotas wrote: > This patch adds support for CSI2TX v2.1 version of the controller. > > Signed-off-by: Jan Kotas <jank@cadence.com> > --- > drivers/media/platform/cadence/cdns-csi2tx.c | 142 +++++++++++++++++++++------ > 1 file changed, 112 insertions(+), 30 deletions(-) > > diff --git a/drivers/media/platform/cadence/cdns-csi2tx.c b/drivers/media/platform/cadence/cdns-csi2tx.c > index 232259c71..e4d08acfb 100644 > --- a/drivers/media/platform/cadence/cdns-csi2tx.c > +++ b/drivers/media/platform/cadence/cdns-csi2tx.c > @@ -52,6 +52,17 @@ > #define CSI2TX_STREAM_IF_CFG_REG(n) (0x100 + (n) * 4) > #define CSI2TX_STREAM_IF_CFG_FILL_LEVEL(n) ((n) & 0x1f) > > +/* CSI2TX V2 Registers */ > +#define CSI2TX_V2_DPHY_CFG_REG 0x28 > +#define CSI2TX_V2_DPHY_CFG_RESET BIT(16) > +#define CSI2TX_V2_DPHY_CFG_CLOCK_MODE BIT(10) > +#define CSI2TX_V2_DPHY_CFG_MODE_MASK GENMASK(9, 8) > +#define CSI2TX_V2_DPHY_CFG_MODE_LPDT (2 << 8) > +#define CSI2TX_V2_DPHY_CFG_MODE_HS (1 << 8) > +#define CSI2TX_V2_DPHY_CFG_MODE_ULPS (0 << 8) > +#define CSI2TX_V2_DPHY_CFG_CLK_ENABLE BIT(4) > +#define CSI2TX_V2_DPHY_CFG_LANE_ENABLE(n) BIT(n) > + > #define CSI2TX_LANES_MAX 4 > #define CSI2TX_STREAMS_MAX 4 > > @@ -70,6 +81,13 @@ struct csi2tx_fmt { > u32 bpp; > }; > > +struct csi2tx_priv; > + > +/* CSI2TX Variant Operations */ > +struct csi2tx_vops { > + void (*dphy_setup)(struct csi2tx_priv *csi2tx); > +}; > + > struct csi2tx_priv { > struct device *dev; > unsigned int count; > @@ -82,6 +100,8 @@ struct csi2tx_priv { > > void __iomem *base; > > + struct csi2tx_vops *vops; > + > struct clk *esc_clk; > struct clk *p_clk; > struct clk *pixel_clk[CSI2TX_STREAMS_MAX]; > @@ -209,53 +229,92 @@ static const struct v4l2_subdev_pad_ops csi2tx_pad_ops = { > .set_fmt = csi2tx_set_pad_format, > }; > > -static void csi2tx_reset(struct csi2tx_priv *csi2tx) > +/* Set Wake Up value in the D-PHY */ > +static void csi2tx_dphy_set_wakeup(struct csi2tx_priv *csi2tx) > { > - writel(CSI2TX_CONFIG_SRST_REQ, csi2tx->base + CSI2TX_CONFIG_REG); > - > - udelay(10); > + writel(CSI2TX_DPHY_CLK_WAKEUP_ULPS_CYCLES(32), > + csi2tx->base + CSI2TX_DPHY_CLK_WAKEUP_REG); > } > > -static int csi2tx_start(struct csi2tx_priv *csi2tx) > +/* > + * Finishes the D-PHY initialization > + * reg dphy cfg value to be used > + */ > +static void csi2tx_dphy_init_finish(struct csi2tx_priv *csi2tx, u32 reg) > { > - struct media_entity *entity = &csi2tx->subdev.entity; > - struct media_link *link; > unsigned int i; > - u32 reg; > > - csi2tx_reset(csi2tx); > + udelay(10); > > - writel(CSI2TX_CONFIG_CFG_REQ, csi2tx->base + CSI2TX_CONFIG_REG); > + /* Enable our (clock and data) lanes */ > + reg |= CSI2TX_DPHY_CFG_CLK_ENABLE; > + for (i = 0; i < csi2tx->num_lanes; i++) > + reg |= CSI2TX_DPHY_CFG_LANE_ENABLE(csi2tx->lanes[i] - 1); > + writel(reg, csi2tx->base + CSI2TX_DPHY_CFG_REG); > > udelay(10); > > - /* Configure our PPI interface with the D-PHY */ > - writel(CSI2TX_DPHY_CLK_WAKEUP_ULPS_CYCLES(32), > - csi2tx->base + CSI2TX_DPHY_CLK_WAKEUP_REG); > + /* Switch to HS mode */ > + reg &= ~CSI2TX_DPHY_CFG_MODE_MASK; > + writel(reg | CSI2TX_DPHY_CFG_MODE_HS, > + csi2tx->base + CSI2TX_DPHY_CFG_REG); > +} > + > +/* Configures D-PHY in CSIv1.3 */ > +static void csi2tx_dphy_setup(struct csi2tx_priv *csi2tx) > +{ > + u32 reg; > + unsigned int i; > + > + csi2tx_dphy_set_wakeup(csi2tx); > > /* Put our lanes (clock and data) out of reset */ > reg = CSI2TX_DPHY_CFG_CLK_RESET | CSI2TX_DPHY_CFG_MODE_LPDT; > for (i = 0; i < csi2tx->num_lanes; i++) > - reg |= CSI2TX_DPHY_CFG_LANE_RESET(csi2tx->lanes[i]); > + reg |= CSI2TX_DPHY_CFG_LANE_RESET(csi2tx->lanes[i] - 1); This looks like a separate change? > writel(reg, csi2tx->base + CSI2TX_DPHY_CFG_REG); > > - udelay(10); > + csi2tx_dphy_init_finish(csi2tx, reg); > +} > > - /* Enable our (clock and data) lanes */ > - reg |= CSI2TX_DPHY_CFG_CLK_ENABLE; > - for (i = 0; i < csi2tx->num_lanes; i++) > - reg |= CSI2TX_DPHY_CFG_LANE_ENABLE(csi2tx->lanes[i]); And you have a similar change here that should be in a separate patch, with a proper explanation. Otherwise, the rest looks good. Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 3/3] media: Add support for Cadence CSI2TX 2.1 2019-07-20 8:25 ` Maxime Ripard @ 2019-07-22 7:07 ` Jan Kotas 0 siblings, 0 replies; 14+ messages in thread From: Jan Kotas @ 2019-07-22 7:07 UTC (permalink / raw) To: Maxime Ripard Cc: Jan Kotas, mchehab, Rob Herring, Mark Rutland, linux-media, linux-devicetree, linux-kernel > On 20 Jul 2019, at 10:25, Maxime Ripard <maxime.ripard@bootlin.com> wrote: > > Hi, > > On Thu, Jul 18, 2019 at 12:15:09PM +0100, Jan Kotas wrote: >> /* Put our lanes (clock and data) out of reset */ >> reg = CSI2TX_DPHY_CFG_CLK_RESET | CSI2TX_DPHY_CFG_MODE_LPDT; >> for (i = 0; i < csi2tx->num_lanes; i++) >> - reg |= CSI2TX_DPHY_CFG_LANE_RESET(csi2tx->lanes[i]); >> + reg |= CSI2TX_DPHY_CFG_LANE_RESET(csi2tx->lanes[i] - 1); > > This looks like a separate change? > >> writel(reg, csi2tx->base + CSI2TX_DPHY_CFG_REG); >> >> - udelay(10); >> + csi2tx_dphy_init_finish(csi2tx, reg); >> +} >> >> - /* Enable our (clock and data) lanes */ >> - reg |= CSI2TX_DPHY_CFG_CLK_ENABLE; >> - for (i = 0; i < csi2tx->num_lanes; i++) >> - reg |= CSI2TX_DPHY_CFG_LANE_ENABLE(csi2tx->lanes[i]); > > And you have a similar change here that should be in a separate patch, > with a proper explanation. > > Otherwise, the rest looks good. OK, I’ll create a separate patch with this modification. Jan > Maxime > > -- > Maxime Ripard, Bootlin > Embedded Linux and Kernel engineering > https://bootlin.com ^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2019-07-22 7:07 UTC | newest] Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-07-18 11:15 [PATCH 0/3] media: Add support for Cadence CSI2TX version 2.1 Jan Kotas 2019-07-18 11:15 ` Jan Kotas 2019-07-18 11:15 ` [PATCH 1/3] media: dt-bindings: Update bindings " Jan Kotas 2019-07-18 11:15 ` Jan Kotas 2019-07-20 8:26 ` Maxime Ripard 2019-07-18 11:15 ` [PATCH 2/3] media: Add lane checks for Cadence CSI2TX Jan Kotas 2019-07-18 11:15 ` Jan Kotas 2019-07-18 11:52 ` Marc Gonzalez 2019-07-18 12:07 ` Jan Kotas 2019-07-20 8:26 ` Maxime Ripard 2019-07-18 11:15 ` [PATCH 3/3] media: Add support for Cadence CSI2TX 2.1 Jan Kotas 2019-07-18 11:15 ` Jan Kotas 2019-07-20 8:25 ` Maxime Ripard 2019-07-22 7:07 ` Jan Kotas
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