From: Maxime Ripard <maxime.ripard@bootlin.com>
To: Icenowy Zheng <icenowy@aosc.io>
Cc: Rob Herring <robh+dt@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
Linus Walleij <linus.walleij@linaro.org>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com
Subject: Re: [PATCH v4 2/8] clk: sunxi-ng: v3s: add the missing PLL_DDR1
Date: Sat, 20 Jul 2019 11:43:36 +0200 [thread overview]
Message-ID: <20190720094335.io2dkgen5y4ywgs5@flea> (raw)
In-Reply-To: <20190713034634.44585-3-icenowy@aosc.io>
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On Sat, Jul 13, 2019 at 11:46:28AM +0800, Icenowy Zheng wrote:
> The user manual of V3/V3s/S3 declares a PLL_DDR1, however it's forgot
> when developing the V3s CCU driver.
>
> Add back the missing PLL_DDR1.
>
> Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU")
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
queued for 5.4, thanks
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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WARNING: multiple messages have this Message-ID (diff)
From: Maxime Ripard <maxime.ripard-LDxbnhwyfcJBDgjK7y7TUQ@public.gmane.org>
To: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>,
Linus Walleij
<linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org
Subject: Re: [PATCH v4 2/8] clk: sunxi-ng: v3s: add the missing PLL_DDR1
Date: Sat, 20 Jul 2019 11:43:36 +0200 [thread overview]
Message-ID: <20190720094335.io2dkgen5y4ywgs5@flea> (raw)
In-Reply-To: <20190713034634.44585-3-icenowy-h8G6r0blFSE@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 461 bytes --]
On Sat, Jul 13, 2019 at 11:46:28AM +0800, Icenowy Zheng wrote:
> The user manual of V3/V3s/S3 declares a PLL_DDR1, however it's forgot
> when developing the V3s CCU driver.
>
> Add back the missing PLL_DDR1.
>
> Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU")
> Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
queued for 5.4, thanks
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
WARNING: multiple messages have this Message-ID (diff)
From: Maxime Ripard <maxime.ripard@bootlin.com>
To: Icenowy Zheng <icenowy@aosc.io>
Cc: devicetree@vger.kernel.org,
Linus Walleij <linus.walleij@linaro.org>,
linux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org,
linux-gpio@vger.kernel.org, Chen-Yu Tsai <wens@csie.org>,
Rob Herring <robh+dt@kernel.org>,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v4 2/8] clk: sunxi-ng: v3s: add the missing PLL_DDR1
Date: Sat, 20 Jul 2019 11:43:36 +0200 [thread overview]
Message-ID: <20190720094335.io2dkgen5y4ywgs5@flea> (raw)
In-Reply-To: <20190713034634.44585-3-icenowy@aosc.io>
[-- Attachment #1.1: Type: text/plain, Size: 441 bytes --]
On Sat, Jul 13, 2019 at 11:46:28AM +0800, Icenowy Zheng wrote:
> The user manual of V3/V3s/S3 declares a PLL_DDR1, however it's forgot
> when developing the V3s CCU driver.
>
> Add back the missing PLL_DDR1.
>
> Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU")
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
queued for 5.4, thanks
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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next prev parent reply other threads:[~2019-07-20 9:43 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-13 3:46 [PATCH v4 0/8] Support for Allwinner V3/S3L and Sochip S3 Icenowy Zheng
2019-07-13 3:46 ` Icenowy Zheng
2019-07-13 3:46 ` Icenowy Zheng
2019-07-13 3:46 ` [PATCH v4 1/8] pinctrl: sunxi: v3s: introduce support for V3 Icenowy Zheng
2019-07-13 3:46 ` Icenowy Zheng
2019-07-13 3:46 ` Icenowy Zheng
2019-07-20 9:20 ` Maxime Ripard
2019-07-20 9:20 ` Maxime Ripard
2019-07-20 9:20 ` Maxime Ripard
2019-07-13 3:46 ` [PATCH v4 2/8] clk: sunxi-ng: v3s: add the missing PLL_DDR1 Icenowy Zheng
2019-07-13 3:46 ` Icenowy Zheng
2019-07-20 9:43 ` Maxime Ripard [this message]
2019-07-20 9:43 ` Maxime Ripard
2019-07-20 9:43 ` Maxime Ripard
2019-07-13 3:46 ` [PATCH v4 3/8] dt-bindings: clk: sunxi-ccu: add compatible string for V3 CCU Icenowy Zheng
2019-07-13 3:46 ` Icenowy Zheng
2019-07-20 9:44 ` Maxime Ripard
2019-07-20 9:44 ` Maxime Ripard
2019-07-20 9:44 ` Maxime Ripard
2019-07-13 3:46 ` [PATCH v4 4/8] clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks Icenowy Zheng
2019-07-13 3:46 ` Icenowy Zheng
2019-07-20 9:44 ` Maxime Ripard
2019-07-20 9:44 ` Maxime Ripard
2019-07-20 9:44 ` Maxime Ripard
2019-07-20 9:45 ` Icenowy Zheng
2019-07-20 9:45 ` Icenowy Zheng
2019-07-13 3:46 ` [PATCH v4 5/8] clk: sunxi-ng: v3s: add Allwinner V3 support Icenowy Zheng
2019-07-13 3:46 ` Icenowy Zheng
2019-07-13 3:46 ` Icenowy Zheng
2019-07-20 9:46 ` Maxime Ripard
2019-07-20 9:46 ` Maxime Ripard
2019-07-22 17:07 ` Rob Herring
2019-07-22 17:07 ` Rob Herring
2019-07-22 17:07 ` Rob Herring
2019-07-13 3:46 ` [PATCH v4 6/8] ARM: sunxi: dts: s3/s3l/v3: add DTSI files for S3/S3L/V3 SoCs Icenowy Zheng
2019-07-13 3:46 ` Icenowy Zheng
2019-07-13 3:46 ` Icenowy Zheng
2019-07-20 9:48 ` Maxime Ripard
2019-07-20 9:48 ` Maxime Ripard
2019-07-20 9:48 ` Maxime Ripard
2019-07-20 9:50 ` Icenowy Zheng
2019-07-20 9:50 ` Icenowy Zheng
2019-07-13 3:46 ` [PATCH v4 7/8] dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board Icenowy Zheng
2019-07-13 3:46 ` Icenowy Zheng
2019-07-13 3:46 ` Icenowy Zheng
2019-07-15 17:03 ` Rob Herring
2019-07-15 17:03 ` Rob Herring
2019-07-15 17:03 ` Rob Herring
2019-07-20 10:13 ` Maxime Ripard
2019-07-20 10:13 ` Maxime Ripard
2019-07-20 10:13 ` Maxime Ripard
2019-07-20 11:39 ` Icenowy Zheng
2019-07-20 11:39 ` Icenowy Zheng
2019-07-20 11:39 ` Icenowy Zheng
2019-07-22 19:29 ` Maxime Ripard
2019-07-22 19:29 ` Maxime Ripard
2019-07-24 13:09 ` Icenowy Zheng
2019-07-24 13:09 ` Icenowy Zheng
2019-07-24 14:14 ` Maxime Ripard
2019-07-24 14:14 ` Maxime Ripard
2019-07-24 14:14 ` Maxime Ripard
2019-07-13 3:46 ` [PATCH v4 8/8] ARM: dts: sun8i: s3: add devicetree for Lichee zero plus w/ S3 Icenowy Zheng
2019-07-13 3:46 ` Icenowy Zheng
2019-07-20 10:12 ` Maxime Ripard
2019-07-20 10:12 ` Maxime Ripard
2019-07-20 10:12 ` Maxime Ripard
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