* [PATCH v2 01/19] phy: mvebu-cp110-comphy: Add clocks support
2019-06-27 9:50 [PATCH v2 00/19] Enhance CP110 COMPHY support Miquel Raynal
@ 2019-06-27 9:50 ` Miquel Raynal
2019-06-27 9:50 ` Miquel Raynal
` (11 subsequent siblings)
12 siblings, 0 replies; 49+ messages in thread
From: Miquel Raynal @ 2019-06-27 9:50 UTC (permalink / raw)
To: Gregory Clement, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Kishon Vijay Abraham I
Cc: devicetree, Antoine Tenart, Grzegorz Jaszczyk, Russell King,
Maxime Chevallier, Nadav Haklai, Rob Herring, Thomas Petazzoni,
Miquel Raynal, linux-arm-kernel
There is no public clock tree that implies such dependencies between
the MG/MG-core/AXI clocks and the COMPHY IP but accessing the COMPHY
registers while one of the three clocks are disabled stalls the CPU.
This happens if, for instance, the COMPHY driver probe is deferred
(eg. the USB Vbus regulator driver is not yet visible). The MVPP2
driver which also needs these clocks (among others) will
prepare/enable the clocks, then be deferred, and disable/unprepare
them. Next COMPHY lane to be configured would produce an infinite
stall.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 91 ++++++++++++++++++--
1 file changed, 86 insertions(+), 5 deletions(-)
diff --git a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
index d98e0451f6a1..c3a178747f54 100644
--- a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
+++ b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
@@ -5,6 +5,7 @@
* Antoine Tenart <antoine.tenart@free-electrons.com>
*/
+#include <linux/clk.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/mfd/syscon.h>
@@ -160,6 +161,9 @@ struct mvebu_comphy_priv {
void __iomem *base;
struct regmap *regmap;
struct device *dev;
+ struct clk *mg_domain_clk;
+ struct clk *mg_core_clk;
+ struct clk *axi_clk;
};
struct mvebu_comphy_lane {
@@ -585,12 +589,72 @@ static struct phy *mvebu_comphy_xlate(struct device *dev,
return phy;
}
+static int mvebu_comphy_init_clks(struct mvebu_comphy_priv *priv)
+{
+ int ret;
+
+ priv->mg_domain_clk = devm_clk_get(priv->dev, "mg_clk");
+ if (IS_ERR(priv->mg_domain_clk))
+ return PTR_ERR(priv->mg_domain_clk);
+
+ ret = clk_prepare_enable(priv->mg_domain_clk);
+ if (ret < 0)
+ return ret;
+
+ priv->mg_core_clk = devm_clk_get(priv->dev, "mg_core_clk");
+ if (IS_ERR(priv->mg_core_clk)) {
+ ret = PTR_ERR(priv->mg_core_clk);
+ goto dis_mg_domain_clk;
+ }
+
+ ret = clk_prepare_enable(priv->mg_core_clk);
+ if (ret < 0)
+ goto dis_mg_domain_clk;
+
+ priv->axi_clk = devm_clk_get(priv->dev, "axi_clk");
+ if (IS_ERR(priv->axi_clk)) {
+ ret = PTR_ERR(priv->axi_clk);
+ goto dis_mg_core_clk;
+ }
+
+ ret = clk_prepare_enable(priv->axi_clk);
+ if (ret < 0)
+ goto dis_mg_core_clk;
+
+ return 0;
+
+dis_mg_core_clk:
+ clk_disable_unprepare(priv->mg_core_clk);
+
+dis_mg_domain_clk:
+ clk_disable_unprepare(priv->mg_domain_clk);
+
+ priv->mg_domain_clk = NULL;
+ priv->mg_core_clk = NULL;
+ priv->axi_clk = NULL;
+
+ return ret;
+};
+
+static void mvebu_comphy_disable_unprepare_clks(struct mvebu_comphy_priv *priv)
+{
+ if (priv->axi_clk)
+ clk_disable_unprepare(priv->axi_clk);
+
+ if (priv->mg_core_clk)
+ clk_disable_unprepare(priv->mg_core_clk);
+
+ if (priv->mg_domain_clk)
+ clk_disable_unprepare(priv->mg_domain_clk);
+}
+
static int mvebu_comphy_probe(struct platform_device *pdev)
{
struct mvebu_comphy_priv *priv;
struct phy_provider *provider;
struct device_node *child;
struct resource *res;
+ int ret;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
@@ -607,10 +671,17 @@ static int mvebu_comphy_probe(struct platform_device *pdev)
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
+ /*
+ * Ignore error if clocks have not been initialized properly for DT
+ * compatibility reasons.
+ */
+ ret = mvebu_comphy_init_clks(priv);
+ if (ret)
+ dev_warn(&pdev->dev, "cannot initialize clocks\n");
+
for_each_available_child_of_node(pdev->dev.of_node, child) {
struct mvebu_comphy_lane *lane;
struct phy *phy;
- int ret;
u32 val;
ret = of_property_read_u32(child, "reg", &val);
@@ -626,12 +697,16 @@ static int mvebu_comphy_probe(struct platform_device *pdev)
}
lane = devm_kzalloc(&pdev->dev, sizeof(*lane), GFP_KERNEL);
- if (!lane)
- return -ENOMEM;
+ if (!lane) {
+ ret = -ENOMEM;
+ goto disable_clks;
+ }
phy = devm_phy_create(&pdev->dev, child, &mvebu_comphy_ops);
- if (IS_ERR(phy))
- return PTR_ERR(phy);
+ if (IS_ERR(phy)) {
+ ret = PTR_ERR(phy);
+ goto disable_clks;
+ }
lane->priv = priv;
lane->mode = PHY_MODE_INVALID;
@@ -649,7 +724,13 @@ static int mvebu_comphy_probe(struct platform_device *pdev)
dev_set_drvdata(&pdev->dev, priv);
provider = devm_of_phy_provider_register(&pdev->dev,
mvebu_comphy_xlate);
+
return PTR_ERR_OR_ZERO(provider);
+
+disable_clks:
+ mvebu_comphy_disable_unprepare_clks(priv);
+
+ return ret;
}
static const struct of_device_id mvebu_comphy_of_match_table[] = {
--
2.19.1
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 01/19] phy: mvebu-cp110-comphy: Add clocks support
@ 2019-06-27 9:50 ` Miquel Raynal
0 siblings, 0 replies; 49+ messages in thread
From: Miquel Raynal @ 2019-06-27 9:50 UTC (permalink / raw)
To: Gregory Clement, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Kishon Vijay Abraham I
Cc: devicetree, Antoine Tenart, Grzegorz Jaszczyk, Russell King,
Maxime Chevallier, Nadav Haklai, Rob Herring, Thomas Petazzoni,
Miquel Raynal, linux-arm-kernel
There is no public clock tree that implies such dependencies between
the MG/MG-core/AXI clocks and the COMPHY IP but accessing the COMPHY
registers while one of the three clocks are disabled stalls the CPU.
This happens if, for instance, the COMPHY driver probe is deferred
(eg. the USB Vbus regulator driver is not yet visible). The MVPP2
driver which also needs these clocks (among others) will
prepare/enable the clocks, then be deferred, and disable/unprepare
them. Next COMPHY lane to be configured would produce an infinite
stall.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 91 ++++++++++++++++++--
1 file changed, 86 insertions(+), 5 deletions(-)
diff --git a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
index d98e0451f6a1..c3a178747f54 100644
--- a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
+++ b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
@@ -5,6 +5,7 @@
* Antoine Tenart <antoine.tenart@free-electrons.com>
*/
+#include <linux/clk.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/mfd/syscon.h>
@@ -160,6 +161,9 @@ struct mvebu_comphy_priv {
void __iomem *base;
struct regmap *regmap;
struct device *dev;
+ struct clk *mg_domain_clk;
+ struct clk *mg_core_clk;
+ struct clk *axi_clk;
};
struct mvebu_comphy_lane {
@@ -585,12 +589,72 @@ static struct phy *mvebu_comphy_xlate(struct device *dev,
return phy;
}
+static int mvebu_comphy_init_clks(struct mvebu_comphy_priv *priv)
+{
+ int ret;
+
+ priv->mg_domain_clk = devm_clk_get(priv->dev, "mg_clk");
+ if (IS_ERR(priv->mg_domain_clk))
+ return PTR_ERR(priv->mg_domain_clk);
+
+ ret = clk_prepare_enable(priv->mg_domain_clk);
+ if (ret < 0)
+ return ret;
+
+ priv->mg_core_clk = devm_clk_get(priv->dev, "mg_core_clk");
+ if (IS_ERR(priv->mg_core_clk)) {
+ ret = PTR_ERR(priv->mg_core_clk);
+ goto dis_mg_domain_clk;
+ }
+
+ ret = clk_prepare_enable(priv->mg_core_clk);
+ if (ret < 0)
+ goto dis_mg_domain_clk;
+
+ priv->axi_clk = devm_clk_get(priv->dev, "axi_clk");
+ if (IS_ERR(priv->axi_clk)) {
+ ret = PTR_ERR(priv->axi_clk);
+ goto dis_mg_core_clk;
+ }
+
+ ret = clk_prepare_enable(priv->axi_clk);
+ if (ret < 0)
+ goto dis_mg_core_clk;
+
+ return 0;
+
+dis_mg_core_clk:
+ clk_disable_unprepare(priv->mg_core_clk);
+
+dis_mg_domain_clk:
+ clk_disable_unprepare(priv->mg_domain_clk);
+
+ priv->mg_domain_clk = NULL;
+ priv->mg_core_clk = NULL;
+ priv->axi_clk = NULL;
+
+ return ret;
+};
+
+static void mvebu_comphy_disable_unprepare_clks(struct mvebu_comphy_priv *priv)
+{
+ if (priv->axi_clk)
+ clk_disable_unprepare(priv->axi_clk);
+
+ if (priv->mg_core_clk)
+ clk_disable_unprepare(priv->mg_core_clk);
+
+ if (priv->mg_domain_clk)
+ clk_disable_unprepare(priv->mg_domain_clk);
+}
+
static int mvebu_comphy_probe(struct platform_device *pdev)
{
struct mvebu_comphy_priv *priv;
struct phy_provider *provider;
struct device_node *child;
struct resource *res;
+ int ret;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
@@ -607,10 +671,17 @@ static int mvebu_comphy_probe(struct platform_device *pdev)
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
+ /*
+ * Ignore error if clocks have not been initialized properly for DT
+ * compatibility reasons.
+ */
+ ret = mvebu_comphy_init_clks(priv);
+ if (ret)
+ dev_warn(&pdev->dev, "cannot initialize clocks\n");
+
for_each_available_child_of_node(pdev->dev.of_node, child) {
struct mvebu_comphy_lane *lane;
struct phy *phy;
- int ret;
u32 val;
ret = of_property_read_u32(child, "reg", &val);
@@ -626,12 +697,16 @@ static int mvebu_comphy_probe(struct platform_device *pdev)
}
lane = devm_kzalloc(&pdev->dev, sizeof(*lane), GFP_KERNEL);
- if (!lane)
- return -ENOMEM;
+ if (!lane) {
+ ret = -ENOMEM;
+ goto disable_clks;
+ }
phy = devm_phy_create(&pdev->dev, child, &mvebu_comphy_ops);
- if (IS_ERR(phy))
- return PTR_ERR(phy);
+ if (IS_ERR(phy)) {
+ ret = PTR_ERR(phy);
+ goto disable_clks;
+ }
lane->priv = priv;
lane->mode = PHY_MODE_INVALID;
@@ -649,7 +724,13 @@ static int mvebu_comphy_probe(struct platform_device *pdev)
dev_set_drvdata(&pdev->dev, priv);
provider = devm_of_phy_provider_register(&pdev->dev,
mvebu_comphy_xlate);
+
return PTR_ERR_OR_ZERO(provider);
+
+disable_clks:
+ mvebu_comphy_disable_unprepare_clks(priv);
+
+ return ret;
}
static const struct of_device_id mvebu_comphy_of_match_table[] = {
--
2.19.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 49+ messages in thread* Re: [PATCH v2 01/19] phy: mvebu-cp110-comphy: Add clocks support
2019-06-27 9:50 ` Miquel Raynal
(?)
@ 2019-07-29 8:06 ` Grzegorz Jaszczyk
-1 siblings, 0 replies; 49+ messages in thread
From: Grzegorz Jaszczyk @ 2019-07-29 8:06 UTC (permalink / raw)
To: Miquel Raynal
Cc: Gregory Clement, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Kishon Vijay Abraham I, devicetree,
Thomas Petazzoni, Antoine Tenart, Maxime Chevallier,
Nadav Haklai, Rob Herring, Russell King, linux-arm-kernel
[-- Attachment #1: Type: text/plain, Size: 3079 bytes --]
Hi Miquel,
czw., 27 cze 2019 o 11:51 Miquel Raynal <miquel.raynal@bootlin.com>
napisał(a):
> +static int mvebu_comphy_init_clks(struct mvebu_comphy_priv *priv)
> +{
> + int ret;
> +
> + priv->mg_domain_clk = devm_clk_get(priv->dev, "mg_clk");
> + if (IS_ERR(priv->mg_domain_clk))
> + return PTR_ERR(priv->mg_domain_clk);
> +
> + ret = clk_prepare_enable(priv->mg_domain_clk);
> + if (ret < 0)
> + return ret;
> +
> + priv->mg_core_clk = devm_clk_get(priv->dev, "mg_core_clk");
> + if (IS_ERR(priv->mg_core_clk)) {
> + ret = PTR_ERR(priv->mg_core_clk);
> + goto dis_mg_domain_clk;
> + }
> +
> + ret = clk_prepare_enable(priv->mg_core_clk);
> + if (ret < 0)
> + goto dis_mg_domain_clk;
> +
> + priv->axi_clk = devm_clk_get(priv->dev, "axi_clk");
> + if (IS_ERR(priv->axi_clk)) {
> + ret = PTR_ERR(priv->axi_clk);
> + goto dis_mg_core_clk;
> + }
> +
> + ret = clk_prepare_enable(priv->axi_clk);
> + if (ret < 0)
> + goto dis_mg_core_clk;
> +
> + return 0;
> +
> +dis_mg_core_clk:
> + clk_disable_unprepare(priv->mg_core_clk);
> +
> +dis_mg_domain_clk:
> + clk_disable_unprepare(priv->mg_domain_clk);
> +
> + priv->mg_domain_clk = NULL;
> + priv->mg_core_clk = NULL;
> + priv->axi_clk = NULL;
> +
> + return ret;
> +};
> +
> +static void mvebu_comphy_disable_unprepare_clks(struct mvebu_comphy_priv
> *priv)
> +{
> + if (priv->axi_clk)
> + clk_disable_unprepare(priv->axi_clk);
> +
> + if (priv->mg_core_clk)
> + clk_disable_unprepare(priv->mg_core_clk);
> +
> + if (priv->mg_domain_clk)
> + clk_disable_unprepare(priv->mg_domain_clk);
> +}
> +
> static int mvebu_comphy_probe(struct platform_device *pdev)
> {
> struct mvebu_comphy_priv *priv;
> struct phy_provider *provider;
> struct device_node *child;
> struct resource *res;
> + int ret;
>
> priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
> if (!priv)
> @@ -607,10 +671,17 @@ static int mvebu_comphy_probe(struct platform_device
> *pdev)
> if (IS_ERR(priv->base))
> return PTR_ERR(priv->base);
>
> + /*
> + * Ignore error if clocks have not been initialized properly for DT
> + * compatibility reasons.
> + */
> + ret = mvebu_comphy_init_clks(priv);
> + if (ret)
> + dev_warn(&pdev->dev, "cannot initialize clocks\n");
> +
>
Please request probe retry when clocks are not ready, e.g.:
- if (ret)
+ if (ret) {
+ if (ret == -EPROBE_DEFER)
+ return ret;
dev_warn(&pdev->dev, "cannot initialize clocks\n");
+ }
After that you can put:
Tested-by: Grzegorz Jaszczyk <jaz@semihalf.com>
regards,
Grzegorz
[-- Attachment #2: Type: text/html, Size: 4146 bytes --]
^ permalink raw reply [flat|nested] 49+ messages in thread* Re: [PATCH v2 01/19] phy: mvebu-cp110-comphy: Add clocks support
2019-06-27 9:50 ` Miquel Raynal
(?)
(?)
@ 2019-07-29 8:10 ` Grzegorz Jaszczyk
-1 siblings, 0 replies; 49+ messages in thread
From: Grzegorz Jaszczyk @ 2019-07-29 8:10 UTC (permalink / raw)
To: Miquel Raynal
Cc: Andrew Lunn, Jason Cooper, devicetree, Antoine Tenart,
Gregory Clement, Russell King, Kishon Vijay Abraham I,
Nadav Haklai, Rob Herring, Thomas Petazzoni, Maxime Chevallier,
linux-arm-kernel, Sebastian Hesselbarth
Hi Miquel
czw., 27 cze 2019 o 11:51 Miquel Raynal <miquel.raynal@bootlin.com> napisał(a):
> +static int mvebu_comphy_init_clks(struct mvebu_comphy_priv *priv)
> +{
> + int ret;
> +
> + priv->mg_domain_clk = devm_clk_get(priv->dev, "mg_clk");
> + if (IS_ERR(priv->mg_domain_clk))
> + return PTR_ERR(priv->mg_domain_clk);
> +
> + ret = clk_prepare_enable(priv->mg_domain_clk);
> + if (ret < 0)
> + return ret;
> +
> + priv->mg_core_clk = devm_clk_get(priv->dev, "mg_core_clk");
> + if (IS_ERR(priv->mg_core_clk)) {
> + ret = PTR_ERR(priv->mg_core_clk);
> + goto dis_mg_domain_clk;
> + }
> +
> + ret = clk_prepare_enable(priv->mg_core_clk);
> + if (ret < 0)
> + goto dis_mg_domain_clk;
> +
> + priv->axi_clk = devm_clk_get(priv->dev, "axi_clk");
> + if (IS_ERR(priv->axi_clk)) {
> + ret = PTR_ERR(priv->axi_clk);
> + goto dis_mg_core_clk;
> + }
> +
> + ret = clk_prepare_enable(priv->axi_clk);
> + if (ret < 0)
> + goto dis_mg_core_clk;
> +
> + return 0;
> +
> +dis_mg_core_clk:
> + clk_disable_unprepare(priv->mg_core_clk);
> +
> +dis_mg_domain_clk:
> + clk_disable_unprepare(priv->mg_domain_clk);
> +
> + priv->mg_domain_clk = NULL;
> + priv->mg_core_clk = NULL;
> + priv->axi_clk = NULL;
> +
> + return ret;
> +};
> +
> +static void mvebu_comphy_disable_unprepare_clks(struct mvebu_comphy_priv *priv)
> +{
> + if (priv->axi_clk)
> + clk_disable_unprepare(priv->axi_clk);
> +
> + if (priv->mg_core_clk)
> + clk_disable_unprepare(priv->mg_core_clk);
> +
> + if (priv->mg_domain_clk)
> + clk_disable_unprepare(priv->mg_domain_clk);
> +}
> +
> static int mvebu_comphy_probe(struct platform_device *pdev)
> {
> struct mvebu_comphy_priv *priv;
> struct phy_provider *provider;
> struct device_node *child;
> struct resource *res;
> + int ret;
>
> priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
> if (!priv)
> @@ -607,10 +671,17 @@ static int mvebu_comphy_probe(struct platform_device *pdev)
> if (IS_ERR(priv->base))
> return PTR_ERR(priv->base);
>
> + /*
> + * Ignore error if clocks have not been initialized properly for DT
> + * compatibility reasons.
> + */
> + ret = mvebu_comphy_init_clks(priv);
> + if (ret)
> + dev_warn(&pdev->dev, "cannot initialize clocks\n");
> +
Please request probe retry when clocks are not ready, e.g.:
- if (ret)
+ if (ret) {
+ if (ret == -EPROBE_DEFER)
+ return ret;
dev_warn(&pdev->dev, "cannot initialize clocks\n");
+ }
After that you can put:
Tested-by: Grzegorz Jaszczyk <jaz@semihalf.com>
regards,
Grzegorz
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 02/19] phy: mvebu-cp110-comphy: Explicitly initialize the lane submode
2019-06-27 9:50 [PATCH v2 00/19] Enhance CP110 COMPHY support Miquel Raynal
@ 2019-06-27 9:50 ` Miquel Raynal
2019-06-27 9:50 ` Miquel Raynal
` (11 subsequent siblings)
12 siblings, 0 replies; 49+ messages in thread
From: Miquel Raynal @ 2019-06-27 9:50 UTC (permalink / raw)
To: Gregory Clement, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Kishon Vijay Abraham I
Cc: devicetree, Antoine Tenart, Grzegorz Jaszczyk, Russell King,
Maxime Chevallier, Nadav Haklai, Rob Herring, Thomas Petazzoni,
Miquel Raynal, linux-arm-kernel
Explicitly set the lane submode (enum) to a known invalid value.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
index c3a178747f54..7c70376f8d12 100644
--- a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
+++ b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
@@ -710,6 +710,7 @@ static int mvebu_comphy_probe(struct platform_device *pdev)
lane->priv = priv;
lane->mode = PHY_MODE_INVALID;
+ lane->submode = PHY_INTERFACE_MODE_NA;
lane->id = val;
lane->port = -1;
phy_set_drvdata(phy, lane);
--
2.19.1
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 02/19] phy: mvebu-cp110-comphy: Explicitly initialize the lane submode
@ 2019-06-27 9:50 ` Miquel Raynal
0 siblings, 0 replies; 49+ messages in thread
From: Miquel Raynal @ 2019-06-27 9:50 UTC (permalink / raw)
To: Gregory Clement, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Kishon Vijay Abraham I
Cc: devicetree, Antoine Tenart, Grzegorz Jaszczyk, Russell King,
Maxime Chevallier, Nadav Haklai, Rob Herring, Thomas Petazzoni,
Miquel Raynal, linux-arm-kernel
Explicitly set the lane submode (enum) to a known invalid value.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
index c3a178747f54..7c70376f8d12 100644
--- a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
+++ b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
@@ -710,6 +710,7 @@ static int mvebu_comphy_probe(struct platform_device *pdev)
lane->priv = priv;
lane->mode = PHY_MODE_INVALID;
+ lane->submode = PHY_INTERFACE_MODE_NA;
lane->id = val;
lane->port = -1;
phy_set_drvdata(phy, lane);
--
2.19.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 03/19] phy: mvebu-cp110-comphy: Add SMC call support
2019-06-27 9:50 [PATCH v2 00/19] Enhance CP110 COMPHY support Miquel Raynal
@ 2019-06-27 9:50 ` Miquel Raynal
2019-06-27 9:50 ` Miquel Raynal
` (11 subsequent siblings)
12 siblings, 0 replies; 49+ messages in thread
From: Miquel Raynal @ 2019-06-27 9:50 UTC (permalink / raw)
To: Gregory Clement, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Kishon Vijay Abraham I
Cc: devicetree, Antoine Tenart, Grzegorz Jaszczyk, Russell King,
Maxime Chevallier, Nadav Haklai, Rob Herring, Thomas Petazzoni,
Miquel Raynal, linux-arm-kernel
From: Grzegorz Jaszczyk <jaz@semihalf.com>
Keep the exact same list of supported configurations but first try to
use the firmware's implementation. If it fails, try the legacy method:
Linux implementation.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
[miquel.raynal@bootlin.com: adapt the content to the mainline driver]
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 226 ++++++++++++++++---
1 file changed, 190 insertions(+), 36 deletions(-)
diff --git a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
index 7c70376f8d12..ed643323f4c5 100644
--- a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
+++ b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
@@ -5,6 +5,7 @@
* Antoine Tenart <antoine.tenart@free-electrons.com>
*/
+#include <linux/arm-smccc.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/iopoll.h>
@@ -116,45 +117,89 @@
#define MVEBU_COMPHY_LANES 6
#define MVEBU_COMPHY_PORTS 3
+#define COMPHY_SIP_POWER_ON 0x82000001
+#define COMPHY_SIP_POWER_OFF 0x82000002
+#define COMPHY_FW_NOT_SUPPORTED (-1)
+
+/*
+ * A lane is described by the following bitfields:
+ * [ 1- 0]: COMPHY polarity invertion
+ * [ 2- 7]: COMPHY speed
+ * [ 5-11]: COMPHY port index
+ * [12-16]: COMPHY mode
+ * [17]: Clock source
+ */
+#define COMPHY_FW_POL_OFFSET 0
+#define COMPHY_FW_POL_MASK GENMASK(1, 0)
+#define COMPHY_FW_SPEED_OFFSET 2
+#define COMPHY_FW_SPEED_MASK GENMASK(7, 2)
+#define COMPHY_FW_SPEED_MAX COMPHY_FW_SPEED_MASK
+#define COMPHY_FW_SPEED_1250 0
+#define COMPHY_FW_SPEED_3125 2
+#define COMPHY_FW_SPEED_5000 3
+#define COMPHY_FW_SPEED_103125 6
+#define COMPHY_FW_PORT_OFFSET 8
+#define COMPHY_FW_PORT_MASK GENMASK(11, 8)
+#define COMPHY_FW_MODE_OFFSET 12
+#define COMPHY_FW_MODE_MASK GENMASK(16, 12)
+
+#define COMPHY_FW_PARAM_FULL(mode, port, speed, pol) \
+ ((((pol) << COMPHY_FW_POL_OFFSET) & COMPHY_FW_POL_MASK) | \
+ (((mode) << COMPHY_FW_MODE_OFFSET) & COMPHY_FW_MODE_MASK) | \
+ (((port) << COMPHY_FW_PORT_OFFSET) & COMPHY_FW_PORT_MASK) | \
+ (((speed) << COMPHY_FW_SPEED_OFFSET) & COMPHY_FW_SPEED_MASK))
+
+#define COMPHY_FW_PARAM(mode, port) \
+ COMPHY_FW_PARAM_FULL(mode, port, 0, 0)
+
+#define COMPHY_FW_PARAM_ETH(mode, port, speed) \
+ COMPHY_FW_PARAM_FULL(mode, port, speed, 0)
+
+#define COMPHY_FW_MODE_SGMII 0x2 /* SGMII 1G */
+#define COMPHY_FW_MODE_HS_SGMII 0x3 /* SGMII 2.5G */
+#define COMPHY_FW_MODE_XFI 0x8 /* SFI: 0x9 (is treated like XFI) */
+
struct mvebu_comphy_conf {
enum phy_mode mode;
int submode;
unsigned lane;
unsigned port;
u32 mux;
+ u32 fw_mode;
};
-#define MVEBU_COMPHY_CONF(_lane, _port, _submode, _mux) \
+#define MVEBU_COMPHY_CONF(_lane, _port, _submode, _mux, _fw) \
{ \
.lane = _lane, \
.port = _port, \
.mode = PHY_MODE_ETHERNET, \
.submode = _submode, \
.mux = _mux, \
+ .fw_mode = _fw, \
}
static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = {
/* lane 0 */
- MVEBU_COMPHY_CONF(0, 1, PHY_INTERFACE_MODE_SGMII, 0x1),
- MVEBU_COMPHY_CONF(0, 1, PHY_INTERFACE_MODE_2500BASEX, 0x1),
+ MVEBU_COMPHY_CONF(0, 1, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
+ MVEBU_COMPHY_CONF(0, 1, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
/* lane 1 */
- MVEBU_COMPHY_CONF(1, 2, PHY_INTERFACE_MODE_SGMII, 0x1),
- MVEBU_COMPHY_CONF(1, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1),
+ MVEBU_COMPHY_CONF(1, 2, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
+ MVEBU_COMPHY_CONF(1, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
/* lane 2 */
- MVEBU_COMPHY_CONF(2, 0, PHY_INTERFACE_MODE_SGMII, 0x1),
- MVEBU_COMPHY_CONF(2, 0, PHY_INTERFACE_MODE_2500BASEX, 0x1),
- MVEBU_COMPHY_CONF(2, 0, PHY_INTERFACE_MODE_10GKR, 0x1),
+ MVEBU_COMPHY_CONF(2, 0, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
+ MVEBU_COMPHY_CONF(2, 0, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
+ MVEBU_COMPHY_CONF(2, 0, PHY_INTERFACE_MODE_10GKR, 0x1, COMPHY_FW_MODE_XFI),
/* lane 3 */
- MVEBU_COMPHY_CONF(3, 1, PHY_INTERFACE_MODE_SGMII, 0x2),
- MVEBU_COMPHY_CONF(3, 1, PHY_INTERFACE_MODE_2500BASEX, 0x2),
+ MVEBU_COMPHY_CONF(3, 1, PHY_INTERFACE_MODE_SGMII, 0x2, COMPHY_FW_MODE_SGMII),
+ MVEBU_COMPHY_CONF(3, 1, PHY_INTERFACE_MODE_2500BASEX, 0x2, COMPHY_FW_MODE_HS_SGMII),
/* lane 4 */
- MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_SGMII, 0x2),
- MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_2500BASEX, 0x2),
- MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_10GKR, 0x2),
- MVEBU_COMPHY_CONF(4, 1, PHY_INTERFACE_MODE_SGMII, 0x1),
+ MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_SGMII, 0x2, COMPHY_FW_MODE_SGMII),
+ MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_2500BASEX, 0x2, COMPHY_FW_MODE_HS_SGMII),
+ MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_10GKR, 0x2, COMPHY_FW_MODE_XFI),
+ MVEBU_COMPHY_CONF(4, 1, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
/* lane 5 */
- MVEBU_COMPHY_CONF(5, 2, PHY_INTERFACE_MODE_SGMII, 0x1),
- MVEBU_COMPHY_CONF(5, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1),
+ MVEBU_COMPHY_CONF(5, 2, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
+ MVEBU_COMPHY_CONF(5, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
};
struct mvebu_comphy_priv {
@@ -164,6 +209,7 @@ struct mvebu_comphy_priv {
struct clk *mg_domain_clk;
struct clk *mg_core_clk;
struct clk *axi_clk;
+ unsigned long cp_phys;
};
struct mvebu_comphy_lane {
@@ -174,8 +220,18 @@ struct mvebu_comphy_lane {
int port;
};
-static int mvebu_comphy_get_mux(int lane, int port,
- enum phy_mode mode, int submode)
+static int mvebu_comphy_smc(unsigned long function, unsigned long phys,
+ unsigned long lane, unsigned long mode)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(function, phys, lane, mode, 0, 0, 0, 0, &res);
+
+ return res.a0;
+}
+
+static int mvebu_comphy_get_mode(bool fw_mode, int lane, int port,
+ enum phy_mode mode, int submode)
{
int i, n = ARRAY_SIZE(mvebu_comphy_cp110_modes);
@@ -194,7 +250,22 @@ static int mvebu_comphy_get_mux(int lane, int port,
if (i == n)
return -EINVAL;
- return mvebu_comphy_cp110_modes[i].mux;
+ if (fw_mode)
+ return mvebu_comphy_cp110_modes[i].fw_mode;
+ else
+ return mvebu_comphy_cp110_modes[i].mux;
+}
+
+static inline int mvebu_comphy_get_mux(int lane, int port,
+ enum phy_mode mode, int submode)
+{
+ return mvebu_comphy_get_mode(false, lane, port, mode, submode);
+}
+
+static inline int mvebu_comphy_get_fw_mode(int lane, int port,
+ enum phy_mode mode, int submode)
+{
+ return mvebu_comphy_get_mode(true, lane, port, mode, submode);
}
static void mvebu_comphy_ethernet_init_reset(struct mvebu_comphy_lane *lane)
@@ -480,7 +551,7 @@ static int mvebu_comphy_set_mode_10gkr(struct phy *phy)
return mvebu_comphy_init_plls(lane);
}
-static int mvebu_comphy_power_on(struct phy *phy)
+static int mvebu_comphy_power_on_legacy(struct phy *phy)
{
struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
struct mvebu_comphy_priv *priv = lane->priv;
@@ -521,6 +592,68 @@ static int mvebu_comphy_power_on(struct phy *phy)
return ret;
}
+static int mvebu_comphy_power_on(struct phy *phy)
+{
+ struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
+ struct mvebu_comphy_priv *priv = lane->priv;
+ int fw_mode, fw_speed;
+ u32 fw_param = 0;
+ int ret;
+
+ fw_mode = mvebu_comphy_get_fw_mode(lane->id, lane->port,
+ lane->mode, lane->submode);
+ if (fw_mode < 0)
+ goto try_legacy;
+
+ /* Try SMC flow first */
+ switch (lane->mode) {
+ case PHY_MODE_ETHERNET:
+ switch (lane->submode) {
+ case PHY_INTERFACE_MODE_SGMII:
+ dev_dbg(priv->dev, "set lane %d to 1000BASE-X mode\n",
+ lane->id);
+ fw_speed = COMPHY_FW_SPEED_1250;
+ break;
+ case PHY_INTERFACE_MODE_2500BASEX:
+ dev_dbg(priv->dev, "set lane %d to 2500BASE-X mode\n",
+ lane->id);
+ fw_speed = COMPHY_FW_SPEED_3125;
+ break;
+ case PHY_INTERFACE_MODE_10GKR:
+ dev_dbg(priv->dev, "set lane %d to 10G-KR mode\n",
+ lane->id);
+ fw_speed = COMPHY_FW_SPEED_103125;
+ break;
+ default:
+ dev_err(priv->dev, "unsupported Ethernet mode (%d)\n",
+ lane->submode);
+ return -ENOTSUPP;
+ }
+ fw_param = COMPHY_FW_PARAM_ETH(fw_mode, lane->port, fw_speed);
+ break;
+ default:
+ dev_err(priv->dev, "unsupported PHY mode (%d)\n", lane->mode);
+ return -ENOTSUPP;
+ }
+
+ ret = mvebu_comphy_smc(COMPHY_SIP_POWER_ON, priv->cp_phys, lane->id,
+ fw_param);
+ if (!ret)
+ return ret;
+
+ if (ret == COMPHY_FW_NOT_SUPPORTED)
+ dev_err(priv->dev,
+ "unsupported SMC call, try updating your firmware\n");
+
+ dev_warn(priv->dev,
+ "Firmware could not configure PHY %d with mode %d (ret: %d), trying legacy method\n",
+ ret, lane->id, lane->mode);
+
+try_legacy:
+ /* Fallback to Linux's implementation */
+ return mvebu_comphy_power_on_legacy(phy);
+}
+
static int mvebu_comphy_set_mode(struct phy *phy,
enum phy_mode mode, int submode)
{
@@ -532,7 +665,7 @@ static int mvebu_comphy_set_mode(struct phy *phy,
if (submode == PHY_INTERFACE_MODE_1000BASEX)
submode = PHY_INTERFACE_MODE_SGMII;
- if (mvebu_comphy_get_mux(lane->id, lane->port, mode, submode) < 0)
+ if (mvebu_comphy_get_fw_mode(lane->id, lane->port, mode, submode) < 0)
return -EINVAL;
lane->mode = mode;
@@ -540,27 +673,42 @@ static int mvebu_comphy_set_mode(struct phy *phy,
return 0;
}
+static int mvebu_comphy_power_off_legacy(struct phy *phy)
+{
+ struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
+ struct mvebu_comphy_priv *priv = lane->priv;
+ u32 val;
+
+ val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
+ val &= ~(MVEBU_COMPHY_SERDES_CFG1_RESET |
+ MVEBU_COMPHY_SERDES_CFG1_CORE_RESET |
+ MVEBU_COMPHY_SERDES_CFG1_RF_RESET);
+ writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
+
+ regmap_read(priv->regmap, MVEBU_COMPHY_SELECTOR, &val);
+ val &= ~(0xf << MVEBU_COMPHY_SELECTOR_PHY(lane->id));
+ regmap_write(priv->regmap, MVEBU_COMPHY_SELECTOR, val);
+
+ regmap_read(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, &val);
+ val &= ~(0xf << MVEBU_COMPHY_PIPE_SELECTOR_PIPE(lane->id));
+ regmap_write(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, val);
+
+ return 0;
+}
+
static int mvebu_comphy_power_off(struct phy *phy)
{
struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
struct mvebu_comphy_priv *priv = lane->priv;
- u32 val;
+ int ret;
- val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
- val &= ~(MVEBU_COMPHY_SERDES_CFG1_RESET |
- MVEBU_COMPHY_SERDES_CFG1_CORE_RESET |
- MVEBU_COMPHY_SERDES_CFG1_RF_RESET);
- writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
+ ret = mvebu_comphy_smc(COMPHY_SIP_POWER_OFF, priv->cp_phys,
+ lane->id, 0);
+ if (!ret)
+ return ret;
- regmap_read(priv->regmap, MVEBU_COMPHY_SELECTOR, &val);
- val &= ~(0xf << MVEBU_COMPHY_SELECTOR_PHY(lane->id));
- regmap_write(priv->regmap, MVEBU_COMPHY_SELECTOR, val);
-
- regmap_read(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, &val);
- val &= ~(0xf << MVEBU_COMPHY_PIPE_SELECTOR_PIPE(lane->id));
- regmap_write(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, val);
-
- return 0;
+ /* Fallback to Linux's implementation */
+ return mvebu_comphy_power_off_legacy(phy);
}
static const struct phy_ops mvebu_comphy_ops = {
@@ -679,6 +827,12 @@ static int mvebu_comphy_probe(struct platform_device *pdev)
if (ret)
dev_warn(&pdev->dev, "cannot initialize clocks\n");
+ /*
+ * Hack to retrieve a physical offset relative to this CP that will be
+ * given to the firmware
+ */
+ priv->cp_phys = res->start;
+
for_each_available_child_of_node(pdev->dev.of_node, child) {
struct mvebu_comphy_lane *lane;
struct phy *phy;
--
2.19.1
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 03/19] phy: mvebu-cp110-comphy: Add SMC call support
@ 2019-06-27 9:50 ` Miquel Raynal
0 siblings, 0 replies; 49+ messages in thread
From: Miquel Raynal @ 2019-06-27 9:50 UTC (permalink / raw)
To: Gregory Clement, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Kishon Vijay Abraham I
Cc: devicetree, Antoine Tenart, Grzegorz Jaszczyk, Russell King,
Maxime Chevallier, Nadav Haklai, Rob Herring, Thomas Petazzoni,
Miquel Raynal, linux-arm-kernel
From: Grzegorz Jaszczyk <jaz@semihalf.com>
Keep the exact same list of supported configurations but first try to
use the firmware's implementation. If it fails, try the legacy method:
Linux implementation.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
[miquel.raynal@bootlin.com: adapt the content to the mainline driver]
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 226 ++++++++++++++++---
1 file changed, 190 insertions(+), 36 deletions(-)
diff --git a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
index 7c70376f8d12..ed643323f4c5 100644
--- a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
+++ b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
@@ -5,6 +5,7 @@
* Antoine Tenart <antoine.tenart@free-electrons.com>
*/
+#include <linux/arm-smccc.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/iopoll.h>
@@ -116,45 +117,89 @@
#define MVEBU_COMPHY_LANES 6
#define MVEBU_COMPHY_PORTS 3
+#define COMPHY_SIP_POWER_ON 0x82000001
+#define COMPHY_SIP_POWER_OFF 0x82000002
+#define COMPHY_FW_NOT_SUPPORTED (-1)
+
+/*
+ * A lane is described by the following bitfields:
+ * [ 1- 0]: COMPHY polarity invertion
+ * [ 2- 7]: COMPHY speed
+ * [ 5-11]: COMPHY port index
+ * [12-16]: COMPHY mode
+ * [17]: Clock source
+ */
+#define COMPHY_FW_POL_OFFSET 0
+#define COMPHY_FW_POL_MASK GENMASK(1, 0)
+#define COMPHY_FW_SPEED_OFFSET 2
+#define COMPHY_FW_SPEED_MASK GENMASK(7, 2)
+#define COMPHY_FW_SPEED_MAX COMPHY_FW_SPEED_MASK
+#define COMPHY_FW_SPEED_1250 0
+#define COMPHY_FW_SPEED_3125 2
+#define COMPHY_FW_SPEED_5000 3
+#define COMPHY_FW_SPEED_103125 6
+#define COMPHY_FW_PORT_OFFSET 8
+#define COMPHY_FW_PORT_MASK GENMASK(11, 8)
+#define COMPHY_FW_MODE_OFFSET 12
+#define COMPHY_FW_MODE_MASK GENMASK(16, 12)
+
+#define COMPHY_FW_PARAM_FULL(mode, port, speed, pol) \
+ ((((pol) << COMPHY_FW_POL_OFFSET) & COMPHY_FW_POL_MASK) | \
+ (((mode) << COMPHY_FW_MODE_OFFSET) & COMPHY_FW_MODE_MASK) | \
+ (((port) << COMPHY_FW_PORT_OFFSET) & COMPHY_FW_PORT_MASK) | \
+ (((speed) << COMPHY_FW_SPEED_OFFSET) & COMPHY_FW_SPEED_MASK))
+
+#define COMPHY_FW_PARAM(mode, port) \
+ COMPHY_FW_PARAM_FULL(mode, port, 0, 0)
+
+#define COMPHY_FW_PARAM_ETH(mode, port, speed) \
+ COMPHY_FW_PARAM_FULL(mode, port, speed, 0)
+
+#define COMPHY_FW_MODE_SGMII 0x2 /* SGMII 1G */
+#define COMPHY_FW_MODE_HS_SGMII 0x3 /* SGMII 2.5G */
+#define COMPHY_FW_MODE_XFI 0x8 /* SFI: 0x9 (is treated like XFI) */
+
struct mvebu_comphy_conf {
enum phy_mode mode;
int submode;
unsigned lane;
unsigned port;
u32 mux;
+ u32 fw_mode;
};
-#define MVEBU_COMPHY_CONF(_lane, _port, _submode, _mux) \
+#define MVEBU_COMPHY_CONF(_lane, _port, _submode, _mux, _fw) \
{ \
.lane = _lane, \
.port = _port, \
.mode = PHY_MODE_ETHERNET, \
.submode = _submode, \
.mux = _mux, \
+ .fw_mode = _fw, \
}
static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = {
/* lane 0 */
- MVEBU_COMPHY_CONF(0, 1, PHY_INTERFACE_MODE_SGMII, 0x1),
- MVEBU_COMPHY_CONF(0, 1, PHY_INTERFACE_MODE_2500BASEX, 0x1),
+ MVEBU_COMPHY_CONF(0, 1, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
+ MVEBU_COMPHY_CONF(0, 1, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
/* lane 1 */
- MVEBU_COMPHY_CONF(1, 2, PHY_INTERFACE_MODE_SGMII, 0x1),
- MVEBU_COMPHY_CONF(1, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1),
+ MVEBU_COMPHY_CONF(1, 2, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
+ MVEBU_COMPHY_CONF(1, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
/* lane 2 */
- MVEBU_COMPHY_CONF(2, 0, PHY_INTERFACE_MODE_SGMII, 0x1),
- MVEBU_COMPHY_CONF(2, 0, PHY_INTERFACE_MODE_2500BASEX, 0x1),
- MVEBU_COMPHY_CONF(2, 0, PHY_INTERFACE_MODE_10GKR, 0x1),
+ MVEBU_COMPHY_CONF(2, 0, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
+ MVEBU_COMPHY_CONF(2, 0, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
+ MVEBU_COMPHY_CONF(2, 0, PHY_INTERFACE_MODE_10GKR, 0x1, COMPHY_FW_MODE_XFI),
/* lane 3 */
- MVEBU_COMPHY_CONF(3, 1, PHY_INTERFACE_MODE_SGMII, 0x2),
- MVEBU_COMPHY_CONF(3, 1, PHY_INTERFACE_MODE_2500BASEX, 0x2),
+ MVEBU_COMPHY_CONF(3, 1, PHY_INTERFACE_MODE_SGMII, 0x2, COMPHY_FW_MODE_SGMII),
+ MVEBU_COMPHY_CONF(3, 1, PHY_INTERFACE_MODE_2500BASEX, 0x2, COMPHY_FW_MODE_HS_SGMII),
/* lane 4 */
- MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_SGMII, 0x2),
- MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_2500BASEX, 0x2),
- MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_10GKR, 0x2),
- MVEBU_COMPHY_CONF(4, 1, PHY_INTERFACE_MODE_SGMII, 0x1),
+ MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_SGMII, 0x2, COMPHY_FW_MODE_SGMII),
+ MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_2500BASEX, 0x2, COMPHY_FW_MODE_HS_SGMII),
+ MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_10GKR, 0x2, COMPHY_FW_MODE_XFI),
+ MVEBU_COMPHY_CONF(4, 1, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
/* lane 5 */
- MVEBU_COMPHY_CONF(5, 2, PHY_INTERFACE_MODE_SGMII, 0x1),
- MVEBU_COMPHY_CONF(5, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1),
+ MVEBU_COMPHY_CONF(5, 2, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
+ MVEBU_COMPHY_CONF(5, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
};
struct mvebu_comphy_priv {
@@ -164,6 +209,7 @@ struct mvebu_comphy_priv {
struct clk *mg_domain_clk;
struct clk *mg_core_clk;
struct clk *axi_clk;
+ unsigned long cp_phys;
};
struct mvebu_comphy_lane {
@@ -174,8 +220,18 @@ struct mvebu_comphy_lane {
int port;
};
-static int mvebu_comphy_get_mux(int lane, int port,
- enum phy_mode mode, int submode)
+static int mvebu_comphy_smc(unsigned long function, unsigned long phys,
+ unsigned long lane, unsigned long mode)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(function, phys, lane, mode, 0, 0, 0, 0, &res);
+
+ return res.a0;
+}
+
+static int mvebu_comphy_get_mode(bool fw_mode, int lane, int port,
+ enum phy_mode mode, int submode)
{
int i, n = ARRAY_SIZE(mvebu_comphy_cp110_modes);
@@ -194,7 +250,22 @@ static int mvebu_comphy_get_mux(int lane, int port,
if (i == n)
return -EINVAL;
- return mvebu_comphy_cp110_modes[i].mux;
+ if (fw_mode)
+ return mvebu_comphy_cp110_modes[i].fw_mode;
+ else
+ return mvebu_comphy_cp110_modes[i].mux;
+}
+
+static inline int mvebu_comphy_get_mux(int lane, int port,
+ enum phy_mode mode, int submode)
+{
+ return mvebu_comphy_get_mode(false, lane, port, mode, submode);
+}
+
+static inline int mvebu_comphy_get_fw_mode(int lane, int port,
+ enum phy_mode mode, int submode)
+{
+ return mvebu_comphy_get_mode(true, lane, port, mode, submode);
}
static void mvebu_comphy_ethernet_init_reset(struct mvebu_comphy_lane *lane)
@@ -480,7 +551,7 @@ static int mvebu_comphy_set_mode_10gkr(struct phy *phy)
return mvebu_comphy_init_plls(lane);
}
-static int mvebu_comphy_power_on(struct phy *phy)
+static int mvebu_comphy_power_on_legacy(struct phy *phy)
{
struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
struct mvebu_comphy_priv *priv = lane->priv;
@@ -521,6 +592,68 @@ static int mvebu_comphy_power_on(struct phy *phy)
return ret;
}
+static int mvebu_comphy_power_on(struct phy *phy)
+{
+ struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
+ struct mvebu_comphy_priv *priv = lane->priv;
+ int fw_mode, fw_speed;
+ u32 fw_param = 0;
+ int ret;
+
+ fw_mode = mvebu_comphy_get_fw_mode(lane->id, lane->port,
+ lane->mode, lane->submode);
+ if (fw_mode < 0)
+ goto try_legacy;
+
+ /* Try SMC flow first */
+ switch (lane->mode) {
+ case PHY_MODE_ETHERNET:
+ switch (lane->submode) {
+ case PHY_INTERFACE_MODE_SGMII:
+ dev_dbg(priv->dev, "set lane %d to 1000BASE-X mode\n",
+ lane->id);
+ fw_speed = COMPHY_FW_SPEED_1250;
+ break;
+ case PHY_INTERFACE_MODE_2500BASEX:
+ dev_dbg(priv->dev, "set lane %d to 2500BASE-X mode\n",
+ lane->id);
+ fw_speed = COMPHY_FW_SPEED_3125;
+ break;
+ case PHY_INTERFACE_MODE_10GKR:
+ dev_dbg(priv->dev, "set lane %d to 10G-KR mode\n",
+ lane->id);
+ fw_speed = COMPHY_FW_SPEED_103125;
+ break;
+ default:
+ dev_err(priv->dev, "unsupported Ethernet mode (%d)\n",
+ lane->submode);
+ return -ENOTSUPP;
+ }
+ fw_param = COMPHY_FW_PARAM_ETH(fw_mode, lane->port, fw_speed);
+ break;
+ default:
+ dev_err(priv->dev, "unsupported PHY mode (%d)\n", lane->mode);
+ return -ENOTSUPP;
+ }
+
+ ret = mvebu_comphy_smc(COMPHY_SIP_POWER_ON, priv->cp_phys, lane->id,
+ fw_param);
+ if (!ret)
+ return ret;
+
+ if (ret == COMPHY_FW_NOT_SUPPORTED)
+ dev_err(priv->dev,
+ "unsupported SMC call, try updating your firmware\n");
+
+ dev_warn(priv->dev,
+ "Firmware could not configure PHY %d with mode %d (ret: %d), trying legacy method\n",
+ ret, lane->id, lane->mode);
+
+try_legacy:
+ /* Fallback to Linux's implementation */
+ return mvebu_comphy_power_on_legacy(phy);
+}
+
static int mvebu_comphy_set_mode(struct phy *phy,
enum phy_mode mode, int submode)
{
@@ -532,7 +665,7 @@ static int mvebu_comphy_set_mode(struct phy *phy,
if (submode == PHY_INTERFACE_MODE_1000BASEX)
submode = PHY_INTERFACE_MODE_SGMII;
- if (mvebu_comphy_get_mux(lane->id, lane->port, mode, submode) < 0)
+ if (mvebu_comphy_get_fw_mode(lane->id, lane->port, mode, submode) < 0)
return -EINVAL;
lane->mode = mode;
@@ -540,27 +673,42 @@ static int mvebu_comphy_set_mode(struct phy *phy,
return 0;
}
+static int mvebu_comphy_power_off_legacy(struct phy *phy)
+{
+ struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
+ struct mvebu_comphy_priv *priv = lane->priv;
+ u32 val;
+
+ val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
+ val &= ~(MVEBU_COMPHY_SERDES_CFG1_RESET |
+ MVEBU_COMPHY_SERDES_CFG1_CORE_RESET |
+ MVEBU_COMPHY_SERDES_CFG1_RF_RESET);
+ writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
+
+ regmap_read(priv->regmap, MVEBU_COMPHY_SELECTOR, &val);
+ val &= ~(0xf << MVEBU_COMPHY_SELECTOR_PHY(lane->id));
+ regmap_write(priv->regmap, MVEBU_COMPHY_SELECTOR, val);
+
+ regmap_read(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, &val);
+ val &= ~(0xf << MVEBU_COMPHY_PIPE_SELECTOR_PIPE(lane->id));
+ regmap_write(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, val);
+
+ return 0;
+}
+
static int mvebu_comphy_power_off(struct phy *phy)
{
struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
struct mvebu_comphy_priv *priv = lane->priv;
- u32 val;
+ int ret;
- val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
- val &= ~(MVEBU_COMPHY_SERDES_CFG1_RESET |
- MVEBU_COMPHY_SERDES_CFG1_CORE_RESET |
- MVEBU_COMPHY_SERDES_CFG1_RF_RESET);
- writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
+ ret = mvebu_comphy_smc(COMPHY_SIP_POWER_OFF, priv->cp_phys,
+ lane->id, 0);
+ if (!ret)
+ return ret;
- regmap_read(priv->regmap, MVEBU_COMPHY_SELECTOR, &val);
- val &= ~(0xf << MVEBU_COMPHY_SELECTOR_PHY(lane->id));
- regmap_write(priv->regmap, MVEBU_COMPHY_SELECTOR, val);
-
- regmap_read(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, &val);
- val &= ~(0xf << MVEBU_COMPHY_PIPE_SELECTOR_PIPE(lane->id));
- regmap_write(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, val);
-
- return 0;
+ /* Fallback to Linux's implementation */
+ return mvebu_comphy_power_off_legacy(phy);
}
static const struct phy_ops mvebu_comphy_ops = {
@@ -679,6 +827,12 @@ static int mvebu_comphy_probe(struct platform_device *pdev)
if (ret)
dev_warn(&pdev->dev, "cannot initialize clocks\n");
+ /*
+ * Hack to retrieve a physical offset relative to this CP that will be
+ * given to the firmware
+ */
+ priv->cp_phys = res->start;
+
for_each_available_child_of_node(pdev->dev.of_node, child) {
struct mvebu_comphy_lane *lane;
struct phy *phy;
--
2.19.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 49+ messages in thread* Re: [PATCH v2 03/19] phy: mvebu-cp110-comphy: Add SMC call support
2019-06-27 9:50 ` Miquel Raynal
@ 2019-07-23 8:48 ` Maxime Chevallier
-1 siblings, 0 replies; 49+ messages in thread
From: Maxime Chevallier @ 2019-07-23 8:48 UTC (permalink / raw)
To: Miquel Raynal
Cc: Andrew Lunn, Jason Cooper, devicetree, Antoine Tenart,
Grzegorz Jaszczyk, Gregory Clement, Russell King,
Kishon Vijay Abraham I, Nadav Haklai, Rob Herring,
Thomas Petazzoni, linux-arm-kernel, Sebastian Hesselbarth
Hi Miquel,
Thanks for this, I gave it a quick test and it looks good.
On Thu, 27 Jun 2019 11:50:48 +0200
Miquel Raynal <miquel.raynal@bootlin.com> wrote:
>From: Grzegorz Jaszczyk <jaz@semihalf.com>
>
>Keep the exact same list of supported configurations but first try to
>use the firmware's implementation. If it fails, try the legacy method:
>Linux implementation.
>
>Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
>[miquel.raynal@bootlin.com: adapt the content to the mainline driver]
>Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
[...]
>+ dev_warn(priv->dev,
>+ "Firmware could not configure PHY %d with mode %d (ret: %d), trying legacy method\n",
>+ ret, lane->id, lane->mode);
Small nit, you've got your parameters in the wrong order in that
dev_warn.
Besides that,
Tested-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 03/19] phy: mvebu-cp110-comphy: Add SMC call support
@ 2019-07-23 8:48 ` Maxime Chevallier
0 siblings, 0 replies; 49+ messages in thread
From: Maxime Chevallier @ 2019-07-23 8:48 UTC (permalink / raw)
To: Miquel Raynal
Cc: Andrew Lunn, Jason Cooper, devicetree, Antoine Tenart,
Grzegorz Jaszczyk, Gregory Clement, Russell King,
Kishon Vijay Abraham I, Nadav Haklai, Rob Herring,
Thomas Petazzoni, linux-arm-kernel, Sebastian Hesselbarth
Hi Miquel,
Thanks for this, I gave it a quick test and it looks good.
On Thu, 27 Jun 2019 11:50:48 +0200
Miquel Raynal <miquel.raynal@bootlin.com> wrote:
>From: Grzegorz Jaszczyk <jaz@semihalf.com>
>
>Keep the exact same list of supported configurations but first try to
>use the firmware's implementation. If it fails, try the legacy method:
>Linux implementation.
>
>Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
>[miquel.raynal@bootlin.com: adapt the content to the mainline driver]
>Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
[...]
>+ dev_warn(priv->dev,
>+ "Firmware could not configure PHY %d with mode %d (ret: %d), trying legacy method\n",
>+ ret, lane->id, lane->mode);
Small nit, you've got your parameters in the wrong order in that
dev_warn.
Besides that,
Tested-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 04/19] phy: mvebu-cp110-comphy: List already supported Ethernet modes
2019-06-27 9:50 [PATCH v2 00/19] Enhance CP110 COMPHY support Miquel Raynal
@ 2019-06-27 9:50 ` Miquel Raynal
2019-06-27 9:50 ` Miquel Raynal
` (11 subsequent siblings)
12 siblings, 0 replies; 49+ messages in thread
From: Miquel Raynal @ 2019-06-27 9:50 UTC (permalink / raw)
To: Gregory Clement, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Kishon Vijay Abraham I
Cc: devicetree, Antoine Tenart, Grzegorz Jaszczyk, Russell King,
Maxime Chevallier, Nadav Haklai, Rob Herring, Thomas Petazzoni,
Miquel Raynal, linux-arm-kernel
Currently, the driver supports setting lanes to 1000BASEX, 2500BASEX,
10GKR. Complete the COMPHY modes list by adding two (already
supported) cases for lane 4.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
index ed643323f4c5..db935a19b360 100644
--- a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
+++ b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
@@ -197,6 +197,8 @@ static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = {
MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_2500BASEX, 0x2, COMPHY_FW_MODE_HS_SGMII),
MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_10GKR, 0x2, COMPHY_FW_MODE_XFI),
MVEBU_COMPHY_CONF(4, 1, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
+ MVEBU_COMPHY_CONF(4, 1, PHY_INTERFACE_MODE_2500BASEX, -1, COMPHY_FW_MODE_HS_SGMII),
+ MVEBU_COMPHY_CONF(4, 1, PHY_INTERFACE_MODE_10GKR, -1, COMPHY_FW_MODE_XFI),
/* lane 5 */
MVEBU_COMPHY_CONF(5, 2, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
MVEBU_COMPHY_CONF(5, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
--
2.19.1
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 04/19] phy: mvebu-cp110-comphy: List already supported Ethernet modes
@ 2019-06-27 9:50 ` Miquel Raynal
0 siblings, 0 replies; 49+ messages in thread
From: Miquel Raynal @ 2019-06-27 9:50 UTC (permalink / raw)
To: Gregory Clement, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Kishon Vijay Abraham I
Cc: devicetree, Antoine Tenart, Grzegorz Jaszczyk, Russell King,
Maxime Chevallier, Nadav Haklai, Rob Herring, Thomas Petazzoni,
Miquel Raynal, linux-arm-kernel
Currently, the driver supports setting lanes to 1000BASEX, 2500BASEX,
10GKR. Complete the COMPHY modes list by adding two (already
supported) cases for lane 4.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
index ed643323f4c5..db935a19b360 100644
--- a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
+++ b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
@@ -197,6 +197,8 @@ static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = {
MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_2500BASEX, 0x2, COMPHY_FW_MODE_HS_SGMII),
MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_10GKR, 0x2, COMPHY_FW_MODE_XFI),
MVEBU_COMPHY_CONF(4, 1, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
+ MVEBU_COMPHY_CONF(4, 1, PHY_INTERFACE_MODE_2500BASEX, -1, COMPHY_FW_MODE_HS_SGMII),
+ MVEBU_COMPHY_CONF(4, 1, PHY_INTERFACE_MODE_10GKR, -1, COMPHY_FW_MODE_XFI),
/* lane 5 */
MVEBU_COMPHY_CONF(5, 2, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
MVEBU_COMPHY_CONF(5, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
--
2.19.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 05/19] phy: mvebu-cp110-comphy: Add RXAUI support
2019-06-27 9:50 [PATCH v2 00/19] Enhance CP110 COMPHY support Miquel Raynal
@ 2019-06-27 9:50 ` Miquel Raynal
2019-06-27 9:50 ` Miquel Raynal
` (11 subsequent siblings)
12 siblings, 0 replies; 49+ messages in thread
From: Miquel Raynal @ 2019-06-27 9:50 UTC (permalink / raw)
To: Gregory Clement, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Kishon Vijay Abraham I
Cc: devicetree, Antoine Tenart, Grzegorz Jaszczyk, Russell King,
Maxime Chevallier, Nadav Haklai, Rob Herring, Thomas Petazzoni,
Miquel Raynal, linux-arm-kernel
From: Grzegorz Jaszczyk <jaz@semihalf.com>
Add support for RXAUI mode by adding an entry in the COMPHY modes list.
There is no user for this mode yet so we can enforce an up-to-date
firmware and return an error otherwise without breaking anywone.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
[miquel.raynal@bootlin.com: adapt the content to the mainline driver]
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
index db935a19b360..0dbda2eea5b6 100644
--- a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
+++ b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
@@ -157,6 +157,7 @@
#define COMPHY_FW_MODE_SGMII 0x2 /* SGMII 1G */
#define COMPHY_FW_MODE_HS_SGMII 0x3 /* SGMII 2.5G */
+#define COMPHY_FW_MODE_RXAUI 0x7
#define COMPHY_FW_MODE_XFI 0x8 /* SFI: 0x9 (is treated like XFI) */
struct mvebu_comphy_conf {
@@ -188,18 +189,22 @@ static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = {
/* lane 2 */
MVEBU_COMPHY_CONF(2, 0, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
MVEBU_COMPHY_CONF(2, 0, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
+ MVEBU_COMPHY_CONF(2, 0, PHY_INTERFACE_MODE_RXAUI, -1, COMPHY_FW_MODE_RXAUI),
MVEBU_COMPHY_CONF(2, 0, PHY_INTERFACE_MODE_10GKR, 0x1, COMPHY_FW_MODE_XFI),
/* lane 3 */
MVEBU_COMPHY_CONF(3, 1, PHY_INTERFACE_MODE_SGMII, 0x2, COMPHY_FW_MODE_SGMII),
MVEBU_COMPHY_CONF(3, 1, PHY_INTERFACE_MODE_2500BASEX, 0x2, COMPHY_FW_MODE_HS_SGMII),
+ MVEBU_COMPHY_CONF(3, 1, PHY_INTERFACE_MODE_RXAUI, -1, COMPHY_FW_MODE_RXAUI),
/* lane 4 */
MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_SGMII, 0x2, COMPHY_FW_MODE_SGMII),
MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_2500BASEX, 0x2, COMPHY_FW_MODE_HS_SGMII),
MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_10GKR, 0x2, COMPHY_FW_MODE_XFI),
+ MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_RXAUI, -1, COMPHY_FW_MODE_RXAUI),
MVEBU_COMPHY_CONF(4, 1, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
MVEBU_COMPHY_CONF(4, 1, PHY_INTERFACE_MODE_2500BASEX, -1, COMPHY_FW_MODE_HS_SGMII),
MVEBU_COMPHY_CONF(4, 1, PHY_INTERFACE_MODE_10GKR, -1, COMPHY_FW_MODE_XFI),
/* lane 5 */
+ MVEBU_COMPHY_CONF(5, 1, PHY_INTERFACE_MODE_RXAUI, -1, COMPHY_FW_MODE_RXAUI),
MVEBU_COMPHY_CONF(5, 2, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
MVEBU_COMPHY_CONF(5, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
};
@@ -611,6 +616,11 @@ static int mvebu_comphy_power_on(struct phy *phy)
switch (lane->mode) {
case PHY_MODE_ETHERNET:
switch (lane->submode) {
+ case PHY_INTERFACE_MODE_RXAUI:
+ dev_dbg(priv->dev, "set lane %d to RXAUI mode\n",
+ lane->id);
+ fw_speed = 0;
+ break;
case PHY_INTERFACE_MODE_SGMII:
dev_dbg(priv->dev, "set lane %d to 1000BASE-X mode\n",
lane->id);
--
2.19.1
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 05/19] phy: mvebu-cp110-comphy: Add RXAUI support
@ 2019-06-27 9:50 ` Miquel Raynal
0 siblings, 0 replies; 49+ messages in thread
From: Miquel Raynal @ 2019-06-27 9:50 UTC (permalink / raw)
To: Gregory Clement, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Kishon Vijay Abraham I
Cc: devicetree, Antoine Tenart, Grzegorz Jaszczyk, Russell King,
Maxime Chevallier, Nadav Haklai, Rob Herring, Thomas Petazzoni,
Miquel Raynal, linux-arm-kernel
From: Grzegorz Jaszczyk <jaz@semihalf.com>
Add support for RXAUI mode by adding an entry in the COMPHY modes list.
There is no user for this mode yet so we can enforce an up-to-date
firmware and return an error otherwise without breaking anywone.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
[miquel.raynal@bootlin.com: adapt the content to the mainline driver]
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
index db935a19b360..0dbda2eea5b6 100644
--- a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
+++ b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
@@ -157,6 +157,7 @@
#define COMPHY_FW_MODE_SGMII 0x2 /* SGMII 1G */
#define COMPHY_FW_MODE_HS_SGMII 0x3 /* SGMII 2.5G */
+#define COMPHY_FW_MODE_RXAUI 0x7
#define COMPHY_FW_MODE_XFI 0x8 /* SFI: 0x9 (is treated like XFI) */
struct mvebu_comphy_conf {
@@ -188,18 +189,22 @@ static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = {
/* lane 2 */
MVEBU_COMPHY_CONF(2, 0, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
MVEBU_COMPHY_CONF(2, 0, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
+ MVEBU_COMPHY_CONF(2, 0, PHY_INTERFACE_MODE_RXAUI, -1, COMPHY_FW_MODE_RXAUI),
MVEBU_COMPHY_CONF(2, 0, PHY_INTERFACE_MODE_10GKR, 0x1, COMPHY_FW_MODE_XFI),
/* lane 3 */
MVEBU_COMPHY_CONF(3, 1, PHY_INTERFACE_MODE_SGMII, 0x2, COMPHY_FW_MODE_SGMII),
MVEBU_COMPHY_CONF(3, 1, PHY_INTERFACE_MODE_2500BASEX, 0x2, COMPHY_FW_MODE_HS_SGMII),
+ MVEBU_COMPHY_CONF(3, 1, PHY_INTERFACE_MODE_RXAUI, -1, COMPHY_FW_MODE_RXAUI),
/* lane 4 */
MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_SGMII, 0x2, COMPHY_FW_MODE_SGMII),
MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_2500BASEX, 0x2, COMPHY_FW_MODE_HS_SGMII),
MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_10GKR, 0x2, COMPHY_FW_MODE_XFI),
+ MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_RXAUI, -1, COMPHY_FW_MODE_RXAUI),
MVEBU_COMPHY_CONF(4, 1, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
MVEBU_COMPHY_CONF(4, 1, PHY_INTERFACE_MODE_2500BASEX, -1, COMPHY_FW_MODE_HS_SGMII),
MVEBU_COMPHY_CONF(4, 1, PHY_INTERFACE_MODE_10GKR, -1, COMPHY_FW_MODE_XFI),
/* lane 5 */
+ MVEBU_COMPHY_CONF(5, 1, PHY_INTERFACE_MODE_RXAUI, -1, COMPHY_FW_MODE_RXAUI),
MVEBU_COMPHY_CONF(5, 2, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
MVEBU_COMPHY_CONF(5, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
};
@@ -611,6 +616,11 @@ static int mvebu_comphy_power_on(struct phy *phy)
switch (lane->mode) {
case PHY_MODE_ETHERNET:
switch (lane->submode) {
+ case PHY_INTERFACE_MODE_RXAUI:
+ dev_dbg(priv->dev, "set lane %d to RXAUI mode\n",
+ lane->id);
+ fw_speed = 0;
+ break;
case PHY_INTERFACE_MODE_SGMII:
dev_dbg(priv->dev, "set lane %d to 1000BASE-X mode\n",
lane->id);
--
2.19.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 06/19] phy: mvebu-cp110-comphy: Rename the macro handling only Ethernet modes
2019-06-27 9:50 [PATCH v2 00/19] Enhance CP110 COMPHY support Miquel Raynal
@ 2019-06-27 9:50 ` Miquel Raynal
2019-06-27 9:50 ` Miquel Raynal
` (11 subsequent siblings)
12 siblings, 0 replies; 49+ messages in thread
From: Miquel Raynal @ 2019-06-27 9:50 UTC (permalink / raw)
To: Gregory Clement, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Kishon Vijay Abraham I
Cc: devicetree, Antoine Tenart, Grzegorz Jaszczyk, Russell King,
Maxime Chevallier, Nadav Haklai, Rob Herring, Thomas Petazzoni,
Miquel Raynal, linux-arm-kernel
Before adding support for other PHY modes (not Ethernet ones), let's
rename the MVEBU_COMPHY_CONF macro to a more specific (and shorter)
appellation.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 44 ++++++++++----------
1 file changed, 22 insertions(+), 22 deletions(-)
diff --git a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
index 0dbda2eea5b6..2d8ca678a247 100644
--- a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
+++ b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
@@ -169,7 +169,7 @@ struct mvebu_comphy_conf {
u32 fw_mode;
};
-#define MVEBU_COMPHY_CONF(_lane, _port, _submode, _mux, _fw) \
+#define ETH_CONF(_lane, _port, _submode, _mux, _fw) \
{ \
.lane = _lane, \
.port = _port, \
@@ -181,32 +181,32 @@ struct mvebu_comphy_conf {
static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = {
/* lane 0 */
- MVEBU_COMPHY_CONF(0, 1, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
- MVEBU_COMPHY_CONF(0, 1, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
+ ETH_CONF(0, 1, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
+ ETH_CONF(0, 1, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
/* lane 1 */
- MVEBU_COMPHY_CONF(1, 2, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
- MVEBU_COMPHY_CONF(1, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
+ ETH_CONF(1, 2, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
+ ETH_CONF(1, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
/* lane 2 */
- MVEBU_COMPHY_CONF(2, 0, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
- MVEBU_COMPHY_CONF(2, 0, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
- MVEBU_COMPHY_CONF(2, 0, PHY_INTERFACE_MODE_RXAUI, -1, COMPHY_FW_MODE_RXAUI),
- MVEBU_COMPHY_CONF(2, 0, PHY_INTERFACE_MODE_10GKR, 0x1, COMPHY_FW_MODE_XFI),
+ ETH_CONF(2, 0, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
+ ETH_CONF(2, 0, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
+ ETH_CONF(2, 0, PHY_INTERFACE_MODE_RXAUI, -1, COMPHY_FW_MODE_RXAUI),
+ ETH_CONF(2, 0, PHY_INTERFACE_MODE_10GKR, 0x1, COMPHY_FW_MODE_XFI),
/* lane 3 */
- MVEBU_COMPHY_CONF(3, 1, PHY_INTERFACE_MODE_SGMII, 0x2, COMPHY_FW_MODE_SGMII),
- MVEBU_COMPHY_CONF(3, 1, PHY_INTERFACE_MODE_2500BASEX, 0x2, COMPHY_FW_MODE_HS_SGMII),
- MVEBU_COMPHY_CONF(3, 1, PHY_INTERFACE_MODE_RXAUI, -1, COMPHY_FW_MODE_RXAUI),
+ ETH_CONF(3, 1, PHY_INTERFACE_MODE_SGMII, 0x2, COMPHY_FW_MODE_SGMII),
+ ETH_CONF(3, 1, PHY_INTERFACE_MODE_2500BASEX, 0x2, COMPHY_FW_MODE_HS_SGMII),
+ ETH_CONF(3, 1, PHY_INTERFACE_MODE_RXAUI, -1, COMPHY_FW_MODE_RXAUI),
/* lane 4 */
- MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_SGMII, 0x2, COMPHY_FW_MODE_SGMII),
- MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_2500BASEX, 0x2, COMPHY_FW_MODE_HS_SGMII),
- MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_10GKR, 0x2, COMPHY_FW_MODE_XFI),
- MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_RXAUI, -1, COMPHY_FW_MODE_RXAUI),
- MVEBU_COMPHY_CONF(4, 1, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
- MVEBU_COMPHY_CONF(4, 1, PHY_INTERFACE_MODE_2500BASEX, -1, COMPHY_FW_MODE_HS_SGMII),
- MVEBU_COMPHY_CONF(4, 1, PHY_INTERFACE_MODE_10GKR, -1, COMPHY_FW_MODE_XFI),
+ ETH_CONF(4, 0, PHY_INTERFACE_MODE_SGMII, 0x2, COMPHY_FW_MODE_SGMII),
+ ETH_CONF(4, 0, PHY_INTERFACE_MODE_2500BASEX, 0x2, COMPHY_FW_MODE_HS_SGMII),
+ ETH_CONF(4, 0, PHY_INTERFACE_MODE_10GKR, 0x2, COMPHY_FW_MODE_XFI),
+ ETH_CONF(4, 0, PHY_INTERFACE_MODE_RXAUI, -1, COMPHY_FW_MODE_RXAUI),
+ ETH_CONF(4, 1, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
+ ETH_CONF(4, 1, PHY_INTERFACE_MODE_2500BASEX, -1, COMPHY_FW_MODE_HS_SGMII),
+ ETH_CONF(4, 1, PHY_INTERFACE_MODE_10GKR, -1, COMPHY_FW_MODE_XFI),
/* lane 5 */
- MVEBU_COMPHY_CONF(5, 1, PHY_INTERFACE_MODE_RXAUI, -1, COMPHY_FW_MODE_RXAUI),
- MVEBU_COMPHY_CONF(5, 2, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
- MVEBU_COMPHY_CONF(5, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
+ ETH_CONF(5, 1, PHY_INTERFACE_MODE_RXAUI, -1, COMPHY_FW_MODE_RXAUI),
+ ETH_CONF(5, 2, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
+ ETH_CONF(5, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
};
struct mvebu_comphy_priv {
--
2.19.1
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 06/19] phy: mvebu-cp110-comphy: Rename the macro handling only Ethernet modes
@ 2019-06-27 9:50 ` Miquel Raynal
0 siblings, 0 replies; 49+ messages in thread
From: Miquel Raynal @ 2019-06-27 9:50 UTC (permalink / raw)
To: Gregory Clement, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Kishon Vijay Abraham I
Cc: devicetree, Antoine Tenart, Grzegorz Jaszczyk, Russell King,
Maxime Chevallier, Nadav Haklai, Rob Herring, Thomas Petazzoni,
Miquel Raynal, linux-arm-kernel
Before adding support for other PHY modes (not Ethernet ones), let's
rename the MVEBU_COMPHY_CONF macro to a more specific (and shorter)
appellation.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 44 ++++++++++----------
1 file changed, 22 insertions(+), 22 deletions(-)
diff --git a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
index 0dbda2eea5b6..2d8ca678a247 100644
--- a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
+++ b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
@@ -169,7 +169,7 @@ struct mvebu_comphy_conf {
u32 fw_mode;
};
-#define MVEBU_COMPHY_CONF(_lane, _port, _submode, _mux, _fw) \
+#define ETH_CONF(_lane, _port, _submode, _mux, _fw) \
{ \
.lane = _lane, \
.port = _port, \
@@ -181,32 +181,32 @@ struct mvebu_comphy_conf {
static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = {
/* lane 0 */
- MVEBU_COMPHY_CONF(0, 1, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
- MVEBU_COMPHY_CONF(0, 1, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
+ ETH_CONF(0, 1, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
+ ETH_CONF(0, 1, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
/* lane 1 */
- MVEBU_COMPHY_CONF(1, 2, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
- MVEBU_COMPHY_CONF(1, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
+ ETH_CONF(1, 2, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
+ ETH_CONF(1, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
/* lane 2 */
- MVEBU_COMPHY_CONF(2, 0, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
- MVEBU_COMPHY_CONF(2, 0, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
- MVEBU_COMPHY_CONF(2, 0, PHY_INTERFACE_MODE_RXAUI, -1, COMPHY_FW_MODE_RXAUI),
- MVEBU_COMPHY_CONF(2, 0, PHY_INTERFACE_MODE_10GKR, 0x1, COMPHY_FW_MODE_XFI),
+ ETH_CONF(2, 0, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
+ ETH_CONF(2, 0, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
+ ETH_CONF(2, 0, PHY_INTERFACE_MODE_RXAUI, -1, COMPHY_FW_MODE_RXAUI),
+ ETH_CONF(2, 0, PHY_INTERFACE_MODE_10GKR, 0x1, COMPHY_FW_MODE_XFI),
/* lane 3 */
- MVEBU_COMPHY_CONF(3, 1, PHY_INTERFACE_MODE_SGMII, 0x2, COMPHY_FW_MODE_SGMII),
- MVEBU_COMPHY_CONF(3, 1, PHY_INTERFACE_MODE_2500BASEX, 0x2, COMPHY_FW_MODE_HS_SGMII),
- MVEBU_COMPHY_CONF(3, 1, PHY_INTERFACE_MODE_RXAUI, -1, COMPHY_FW_MODE_RXAUI),
+ ETH_CONF(3, 1, PHY_INTERFACE_MODE_SGMII, 0x2, COMPHY_FW_MODE_SGMII),
+ ETH_CONF(3, 1, PHY_INTERFACE_MODE_2500BASEX, 0x2, COMPHY_FW_MODE_HS_SGMII),
+ ETH_CONF(3, 1, PHY_INTERFACE_MODE_RXAUI, -1, COMPHY_FW_MODE_RXAUI),
/* lane 4 */
- MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_SGMII, 0x2, COMPHY_FW_MODE_SGMII),
- MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_2500BASEX, 0x2, COMPHY_FW_MODE_HS_SGMII),
- MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_10GKR, 0x2, COMPHY_FW_MODE_XFI),
- MVEBU_COMPHY_CONF(4, 0, PHY_INTERFACE_MODE_RXAUI, -1, COMPHY_FW_MODE_RXAUI),
- MVEBU_COMPHY_CONF(4, 1, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
- MVEBU_COMPHY_CONF(4, 1, PHY_INTERFACE_MODE_2500BASEX, -1, COMPHY_FW_MODE_HS_SGMII),
- MVEBU_COMPHY_CONF(4, 1, PHY_INTERFACE_MODE_10GKR, -1, COMPHY_FW_MODE_XFI),
+ ETH_CONF(4, 0, PHY_INTERFACE_MODE_SGMII, 0x2, COMPHY_FW_MODE_SGMII),
+ ETH_CONF(4, 0, PHY_INTERFACE_MODE_2500BASEX, 0x2, COMPHY_FW_MODE_HS_SGMII),
+ ETH_CONF(4, 0, PHY_INTERFACE_MODE_10GKR, 0x2, COMPHY_FW_MODE_XFI),
+ ETH_CONF(4, 0, PHY_INTERFACE_MODE_RXAUI, -1, COMPHY_FW_MODE_RXAUI),
+ ETH_CONF(4, 1, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
+ ETH_CONF(4, 1, PHY_INTERFACE_MODE_2500BASEX, -1, COMPHY_FW_MODE_HS_SGMII),
+ ETH_CONF(4, 1, PHY_INTERFACE_MODE_10GKR, -1, COMPHY_FW_MODE_XFI),
/* lane 5 */
- MVEBU_COMPHY_CONF(5, 1, PHY_INTERFACE_MODE_RXAUI, -1, COMPHY_FW_MODE_RXAUI),
- MVEBU_COMPHY_CONF(5, 2, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
- MVEBU_COMPHY_CONF(5, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
+ ETH_CONF(5, 1, PHY_INTERFACE_MODE_RXAUI, -1, COMPHY_FW_MODE_RXAUI),
+ ETH_CONF(5, 2, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
+ ETH_CONF(5, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
};
struct mvebu_comphy_priv {
--
2.19.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 07/19] phy: mvebu-cp110-comphy: Allow non-Ethernet modes to be configured
2019-06-27 9:50 [PATCH v2 00/19] Enhance CP110 COMPHY support Miquel Raynal
@ 2019-06-27 9:50 ` Miquel Raynal
2019-06-27 9:50 ` Miquel Raynal
` (11 subsequent siblings)
12 siblings, 0 replies; 49+ messages in thread
From: Miquel Raynal @ 2019-06-27 9:50 UTC (permalink / raw)
To: Gregory Clement, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Kishon Vijay Abraham I
Cc: devicetree, Antoine Tenart, Grzegorz Jaszczyk, Russell King,
Maxime Chevallier, Nadav Haklai, Rob Herring, Thomas Petazzoni,
Miquel Raynal, linux-arm-kernel
The COMPHY can configure the SERDES lanes in several non-Ethernet
modes: SATA, USB3, PCIe. Drop the condition limiting the driver to
Ethernet modes only before adding support for more.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
index 2d8ca678a247..224fb5400b96 100644
--- a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
+++ b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
@@ -671,9 +671,6 @@ static int mvebu_comphy_set_mode(struct phy *phy,
{
struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
- if (mode != PHY_MODE_ETHERNET)
- return -EINVAL;
-
if (submode == PHY_INTERFACE_MODE_1000BASEX)
submode = PHY_INTERFACE_MODE_SGMII;
--
2.19.1
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 07/19] phy: mvebu-cp110-comphy: Allow non-Ethernet modes to be configured
@ 2019-06-27 9:50 ` Miquel Raynal
0 siblings, 0 replies; 49+ messages in thread
From: Miquel Raynal @ 2019-06-27 9:50 UTC (permalink / raw)
To: Gregory Clement, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Kishon Vijay Abraham I
Cc: devicetree, Antoine Tenart, Grzegorz Jaszczyk, Russell King,
Maxime Chevallier, Nadav Haklai, Rob Herring, Thomas Petazzoni,
Miquel Raynal, linux-arm-kernel
The COMPHY can configure the SERDES lanes in several non-Ethernet
modes: SATA, USB3, PCIe. Drop the condition limiting the driver to
Ethernet modes only before adding support for more.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
index 2d8ca678a247..224fb5400b96 100644
--- a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
+++ b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
@@ -671,9 +671,6 @@ static int mvebu_comphy_set_mode(struct phy *phy,
{
struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
- if (mode != PHY_MODE_ETHERNET)
- return -EINVAL;
-
if (submode == PHY_INTERFACE_MODE_1000BASEX)
submode = PHY_INTERFACE_MODE_SGMII;
--
2.19.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 08/19] phy: mvebu-cp110-comphy: Add USB3 host/device support
2019-06-27 9:50 [PATCH v2 00/19] Enhance CP110 COMPHY support Miquel Raynal
@ 2019-06-27 9:50 ` Miquel Raynal
2019-06-27 9:50 ` Miquel Raynal
` (11 subsequent siblings)
12 siblings, 0 replies; 49+ messages in thread
From: Miquel Raynal @ 2019-06-27 9:50 UTC (permalink / raw)
To: Gregory Clement, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Kishon Vijay Abraham I
Cc: devicetree, Antoine Tenart, Grzegorz Jaszczyk, Russell King,
Maxime Chevallier, Nadav Haklai, Rob Herring, Thomas Petazzoni,
Miquel Raynal, linux-arm-kernel
From: Grzegorz Jaszczyk <jaz@semihalf.com>
Add USB3 host/device support by adding the right entries in the COMPHY
modes table. A new macro is created to instantiate a "generic" mode
ie. not an Ethernet one. This macro will be re-used when adding SATA
support.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
[miquel.raynal@bootlin.com: adapt the content to the mainline driver]
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 23 ++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
index 224fb5400b96..dfcff7d5dfc2 100644
--- a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
+++ b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
@@ -157,6 +157,8 @@
#define COMPHY_FW_MODE_SGMII 0x2 /* SGMII 1G */
#define COMPHY_FW_MODE_HS_SGMII 0x3 /* SGMII 2.5G */
+#define COMPHY_FW_MODE_USB3H 0x4
+#define COMPHY_FW_MODE_USB3D 0x5
#define COMPHY_FW_MODE_RXAUI 0x7
#define COMPHY_FW_MODE_XFI 0x8 /* SFI: 0x9 (is treated like XFI) */
@@ -179,11 +181,23 @@ struct mvebu_comphy_conf {
.fw_mode = _fw, \
}
+#define GEN_CONF(_lane, _port, _mode, _fw) \
+ { \
+ .lane = _lane, \
+ .port = _port, \
+ .mode = _mode, \
+ .submode = PHY_INTERFACE_MODE_NA, \
+ .mux = -1, \
+ .fw_mode = _fw, \
+ }
+
static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = {
/* lane 0 */
ETH_CONF(0, 1, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
ETH_CONF(0, 1, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
/* lane 1 */
+ GEN_CONF(1, 0, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H),
+ GEN_CONF(1, 0, PHY_MODE_USB_DEVICE_SS, COMPHY_FW_MODE_USB3D),
ETH_CONF(1, 2, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
ETH_CONF(1, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
/* lane 2 */
@@ -191,15 +205,19 @@ static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = {
ETH_CONF(2, 0, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
ETH_CONF(2, 0, PHY_INTERFACE_MODE_RXAUI, -1, COMPHY_FW_MODE_RXAUI),
ETH_CONF(2, 0, PHY_INTERFACE_MODE_10GKR, 0x1, COMPHY_FW_MODE_XFI),
+ GEN_CONF(2, 0, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H),
/* lane 3 */
ETH_CONF(3, 1, PHY_INTERFACE_MODE_SGMII, 0x2, COMPHY_FW_MODE_SGMII),
ETH_CONF(3, 1, PHY_INTERFACE_MODE_2500BASEX, 0x2, COMPHY_FW_MODE_HS_SGMII),
ETH_CONF(3, 1, PHY_INTERFACE_MODE_RXAUI, -1, COMPHY_FW_MODE_RXAUI),
+ GEN_CONF(3, 1, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H),
/* lane 4 */
ETH_CONF(4, 0, PHY_INTERFACE_MODE_SGMII, 0x2, COMPHY_FW_MODE_SGMII),
ETH_CONF(4, 0, PHY_INTERFACE_MODE_2500BASEX, 0x2, COMPHY_FW_MODE_HS_SGMII),
ETH_CONF(4, 0, PHY_INTERFACE_MODE_10GKR, 0x2, COMPHY_FW_MODE_XFI),
ETH_CONF(4, 0, PHY_INTERFACE_MODE_RXAUI, -1, COMPHY_FW_MODE_RXAUI),
+ GEN_CONF(4, 0, PHY_MODE_USB_DEVICE_SS, COMPHY_FW_MODE_USB3D),
+ GEN_CONF(4, 1, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H),
ETH_CONF(4, 1, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
ETH_CONF(4, 1, PHY_INTERFACE_MODE_2500BASEX, -1, COMPHY_FW_MODE_HS_SGMII),
ETH_CONF(4, 1, PHY_INTERFACE_MODE_10GKR, -1, COMPHY_FW_MODE_XFI),
@@ -643,6 +661,11 @@ static int mvebu_comphy_power_on(struct phy *phy)
}
fw_param = COMPHY_FW_PARAM_ETH(fw_mode, lane->port, fw_speed);
break;
+ case PHY_MODE_USB_HOST_SS:
+ case PHY_MODE_USB_DEVICE_SS:
+ dev_dbg(priv->dev, "set lane %d to USB3 mode\n", lane->id);
+ fw_param = COMPHY_FW_PARAM(fw_mode, lane->port);
+ break;
default:
dev_err(priv->dev, "unsupported PHY mode (%d)\n", lane->mode);
return -ENOTSUPP;
--
2.19.1
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 08/19] phy: mvebu-cp110-comphy: Add USB3 host/device support
@ 2019-06-27 9:50 ` Miquel Raynal
0 siblings, 0 replies; 49+ messages in thread
From: Miquel Raynal @ 2019-06-27 9:50 UTC (permalink / raw)
To: Gregory Clement, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Kishon Vijay Abraham I
Cc: devicetree, Antoine Tenart, Grzegorz Jaszczyk, Russell King,
Maxime Chevallier, Nadav Haklai, Rob Herring, Thomas Petazzoni,
Miquel Raynal, linux-arm-kernel
From: Grzegorz Jaszczyk <jaz@semihalf.com>
Add USB3 host/device support by adding the right entries in the COMPHY
modes table. A new macro is created to instantiate a "generic" mode
ie. not an Ethernet one. This macro will be re-used when adding SATA
support.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
[miquel.raynal@bootlin.com: adapt the content to the mainline driver]
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 23 ++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
index 224fb5400b96..dfcff7d5dfc2 100644
--- a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
+++ b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
@@ -157,6 +157,8 @@
#define COMPHY_FW_MODE_SGMII 0x2 /* SGMII 1G */
#define COMPHY_FW_MODE_HS_SGMII 0x3 /* SGMII 2.5G */
+#define COMPHY_FW_MODE_USB3H 0x4
+#define COMPHY_FW_MODE_USB3D 0x5
#define COMPHY_FW_MODE_RXAUI 0x7
#define COMPHY_FW_MODE_XFI 0x8 /* SFI: 0x9 (is treated like XFI) */
@@ -179,11 +181,23 @@ struct mvebu_comphy_conf {
.fw_mode = _fw, \
}
+#define GEN_CONF(_lane, _port, _mode, _fw) \
+ { \
+ .lane = _lane, \
+ .port = _port, \
+ .mode = _mode, \
+ .submode = PHY_INTERFACE_MODE_NA, \
+ .mux = -1, \
+ .fw_mode = _fw, \
+ }
+
static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = {
/* lane 0 */
ETH_CONF(0, 1, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
ETH_CONF(0, 1, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
/* lane 1 */
+ GEN_CONF(1, 0, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H),
+ GEN_CONF(1, 0, PHY_MODE_USB_DEVICE_SS, COMPHY_FW_MODE_USB3D),
ETH_CONF(1, 2, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
ETH_CONF(1, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
/* lane 2 */
@@ -191,15 +205,19 @@ static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = {
ETH_CONF(2, 0, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
ETH_CONF(2, 0, PHY_INTERFACE_MODE_RXAUI, -1, COMPHY_FW_MODE_RXAUI),
ETH_CONF(2, 0, PHY_INTERFACE_MODE_10GKR, 0x1, COMPHY_FW_MODE_XFI),
+ GEN_CONF(2, 0, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H),
/* lane 3 */
ETH_CONF(3, 1, PHY_INTERFACE_MODE_SGMII, 0x2, COMPHY_FW_MODE_SGMII),
ETH_CONF(3, 1, PHY_INTERFACE_MODE_2500BASEX, 0x2, COMPHY_FW_MODE_HS_SGMII),
ETH_CONF(3, 1, PHY_INTERFACE_MODE_RXAUI, -1, COMPHY_FW_MODE_RXAUI),
+ GEN_CONF(3, 1, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H),
/* lane 4 */
ETH_CONF(4, 0, PHY_INTERFACE_MODE_SGMII, 0x2, COMPHY_FW_MODE_SGMII),
ETH_CONF(4, 0, PHY_INTERFACE_MODE_2500BASEX, 0x2, COMPHY_FW_MODE_HS_SGMII),
ETH_CONF(4, 0, PHY_INTERFACE_MODE_10GKR, 0x2, COMPHY_FW_MODE_XFI),
ETH_CONF(4, 0, PHY_INTERFACE_MODE_RXAUI, -1, COMPHY_FW_MODE_RXAUI),
+ GEN_CONF(4, 0, PHY_MODE_USB_DEVICE_SS, COMPHY_FW_MODE_USB3D),
+ GEN_CONF(4, 1, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H),
ETH_CONF(4, 1, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
ETH_CONF(4, 1, PHY_INTERFACE_MODE_2500BASEX, -1, COMPHY_FW_MODE_HS_SGMII),
ETH_CONF(4, 1, PHY_INTERFACE_MODE_10GKR, -1, COMPHY_FW_MODE_XFI),
@@ -643,6 +661,11 @@ static int mvebu_comphy_power_on(struct phy *phy)
}
fw_param = COMPHY_FW_PARAM_ETH(fw_mode, lane->port, fw_speed);
break;
+ case PHY_MODE_USB_HOST_SS:
+ case PHY_MODE_USB_DEVICE_SS:
+ dev_dbg(priv->dev, "set lane %d to USB3 mode\n", lane->id);
+ fw_param = COMPHY_FW_PARAM(fw_mode, lane->port);
+ break;
default:
dev_err(priv->dev, "unsupported PHY mode (%d)\n", lane->mode);
return -ENOTSUPP;
--
2.19.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 09/19] phy: mvebu-cp110-comphy: Add SATA support
2019-06-27 9:50 [PATCH v2 00/19] Enhance CP110 COMPHY support Miquel Raynal
@ 2019-06-27 9:50 ` Miquel Raynal
2019-06-27 9:50 ` Miquel Raynal
` (11 subsequent siblings)
12 siblings, 0 replies; 49+ messages in thread
From: Miquel Raynal @ 2019-06-27 9:50 UTC (permalink / raw)
To: Gregory Clement, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Kishon Vijay Abraham I
Cc: devicetree, Antoine Tenart, Grzegorz Jaszczyk, Russell King,
Maxime Chevallier, Nadav Haklai, Rob Herring, Thomas Petazzoni,
Miquel Raynal, linux-arm-kernel
From: Grzegorz Jaszczyk <jaz@semihalf.com>
Add the corresponding entries in the COMPHY modes table.
SATA support does not need any additional care.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
[miquel.raynal@bootlin.com: adapt the content to the mainline driver]
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
index dfcff7d5dfc2..6f8ae72fb9a9 100644
--- a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
+++ b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
@@ -155,6 +155,7 @@
#define COMPHY_FW_PARAM_ETH(mode, port, speed) \
COMPHY_FW_PARAM_FULL(mode, port, speed, 0)
+#define COMPHY_FW_MODE_SATA 0x1
#define COMPHY_FW_MODE_SGMII 0x2 /* SGMII 1G */
#define COMPHY_FW_MODE_HS_SGMII 0x3 /* SGMII 2.5G */
#define COMPHY_FW_MODE_USB3H 0x4
@@ -195,9 +196,11 @@ static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = {
/* lane 0 */
ETH_CONF(0, 1, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
ETH_CONF(0, 1, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
+ GEN_CONF(0, 1, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),
/* lane 1 */
GEN_CONF(1, 0, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H),
GEN_CONF(1, 0, PHY_MODE_USB_DEVICE_SS, COMPHY_FW_MODE_USB3D),
+ GEN_CONF(1, 0, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),
ETH_CONF(1, 2, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
ETH_CONF(1, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
/* lane 2 */
@@ -206,11 +209,13 @@ static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = {
ETH_CONF(2, 0, PHY_INTERFACE_MODE_RXAUI, -1, COMPHY_FW_MODE_RXAUI),
ETH_CONF(2, 0, PHY_INTERFACE_MODE_10GKR, 0x1, COMPHY_FW_MODE_XFI),
GEN_CONF(2, 0, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H),
+ GEN_CONF(2, 0, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),
/* lane 3 */
ETH_CONF(3, 1, PHY_INTERFACE_MODE_SGMII, 0x2, COMPHY_FW_MODE_SGMII),
ETH_CONF(3, 1, PHY_INTERFACE_MODE_2500BASEX, 0x2, COMPHY_FW_MODE_HS_SGMII),
ETH_CONF(3, 1, PHY_INTERFACE_MODE_RXAUI, -1, COMPHY_FW_MODE_RXAUI),
GEN_CONF(3, 1, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H),
+ GEN_CONF(3, 1, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),
/* lane 4 */
ETH_CONF(4, 0, PHY_INTERFACE_MODE_SGMII, 0x2, COMPHY_FW_MODE_SGMII),
ETH_CONF(4, 0, PHY_INTERFACE_MODE_2500BASEX, 0x2, COMPHY_FW_MODE_HS_SGMII),
@@ -223,6 +228,7 @@ static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = {
ETH_CONF(4, 1, PHY_INTERFACE_MODE_10GKR, -1, COMPHY_FW_MODE_XFI),
/* lane 5 */
ETH_CONF(5, 1, PHY_INTERFACE_MODE_RXAUI, -1, COMPHY_FW_MODE_RXAUI),
+ GEN_CONF(5, 1, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),
ETH_CONF(5, 2, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
ETH_CONF(5, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
};
@@ -666,6 +672,10 @@ static int mvebu_comphy_power_on(struct phy *phy)
dev_dbg(priv->dev, "set lane %d to USB3 mode\n", lane->id);
fw_param = COMPHY_FW_PARAM(fw_mode, lane->port);
break;
+ case PHY_MODE_SATA:
+ dev_dbg(priv->dev, "set lane %d to SATA mode\n", lane->id);
+ fw_param = COMPHY_FW_PARAM(fw_mode, lane->port);
+ break;
default:
dev_err(priv->dev, "unsupported PHY mode (%d)\n", lane->mode);
return -ENOTSUPP;
--
2.19.1
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 09/19] phy: mvebu-cp110-comphy: Add SATA support
@ 2019-06-27 9:50 ` Miquel Raynal
0 siblings, 0 replies; 49+ messages in thread
From: Miquel Raynal @ 2019-06-27 9:50 UTC (permalink / raw)
To: Gregory Clement, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Kishon Vijay Abraham I
Cc: devicetree, Antoine Tenart, Grzegorz Jaszczyk, Russell King,
Maxime Chevallier, Nadav Haklai, Rob Herring, Thomas Petazzoni,
Miquel Raynal, linux-arm-kernel
From: Grzegorz Jaszczyk <jaz@semihalf.com>
Add the corresponding entries in the COMPHY modes table.
SATA support does not need any additional care.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
[miquel.raynal@bootlin.com: adapt the content to the mainline driver]
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
index dfcff7d5dfc2..6f8ae72fb9a9 100644
--- a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
+++ b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
@@ -155,6 +155,7 @@
#define COMPHY_FW_PARAM_ETH(mode, port, speed) \
COMPHY_FW_PARAM_FULL(mode, port, speed, 0)
+#define COMPHY_FW_MODE_SATA 0x1
#define COMPHY_FW_MODE_SGMII 0x2 /* SGMII 1G */
#define COMPHY_FW_MODE_HS_SGMII 0x3 /* SGMII 2.5G */
#define COMPHY_FW_MODE_USB3H 0x4
@@ -195,9 +196,11 @@ static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = {
/* lane 0 */
ETH_CONF(0, 1, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
ETH_CONF(0, 1, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
+ GEN_CONF(0, 1, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),
/* lane 1 */
GEN_CONF(1, 0, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H),
GEN_CONF(1, 0, PHY_MODE_USB_DEVICE_SS, COMPHY_FW_MODE_USB3D),
+ GEN_CONF(1, 0, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),
ETH_CONF(1, 2, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
ETH_CONF(1, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
/* lane 2 */
@@ -206,11 +209,13 @@ static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = {
ETH_CONF(2, 0, PHY_INTERFACE_MODE_RXAUI, -1, COMPHY_FW_MODE_RXAUI),
ETH_CONF(2, 0, PHY_INTERFACE_MODE_10GKR, 0x1, COMPHY_FW_MODE_XFI),
GEN_CONF(2, 0, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H),
+ GEN_CONF(2, 0, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),
/* lane 3 */
ETH_CONF(3, 1, PHY_INTERFACE_MODE_SGMII, 0x2, COMPHY_FW_MODE_SGMII),
ETH_CONF(3, 1, PHY_INTERFACE_MODE_2500BASEX, 0x2, COMPHY_FW_MODE_HS_SGMII),
ETH_CONF(3, 1, PHY_INTERFACE_MODE_RXAUI, -1, COMPHY_FW_MODE_RXAUI),
GEN_CONF(3, 1, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H),
+ GEN_CONF(3, 1, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),
/* lane 4 */
ETH_CONF(4, 0, PHY_INTERFACE_MODE_SGMII, 0x2, COMPHY_FW_MODE_SGMII),
ETH_CONF(4, 0, PHY_INTERFACE_MODE_2500BASEX, 0x2, COMPHY_FW_MODE_HS_SGMII),
@@ -223,6 +228,7 @@ static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = {
ETH_CONF(4, 1, PHY_INTERFACE_MODE_10GKR, -1, COMPHY_FW_MODE_XFI),
/* lane 5 */
ETH_CONF(5, 1, PHY_INTERFACE_MODE_RXAUI, -1, COMPHY_FW_MODE_RXAUI),
+ GEN_CONF(5, 1, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),
ETH_CONF(5, 2, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
ETH_CONF(5, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
};
@@ -666,6 +672,10 @@ static int mvebu_comphy_power_on(struct phy *phy)
dev_dbg(priv->dev, "set lane %d to USB3 mode\n", lane->id);
fw_param = COMPHY_FW_PARAM(fw_mode, lane->port);
break;
+ case PHY_MODE_SATA:
+ dev_dbg(priv->dev, "set lane %d to SATA mode\n", lane->id);
+ fw_param = COMPHY_FW_PARAM(fw_mode, lane->port);
+ break;
default:
dev_err(priv->dev, "unsupported PHY mode (%d)\n", lane->mode);
return -ENOTSUPP;
--
2.19.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 10/19] phy: mvebu-cp110-comphy: Cosmetic change in a helper
2019-06-27 9:50 [PATCH v2 00/19] Enhance CP110 COMPHY support Miquel Raynal
@ 2019-06-27 9:50 ` Miquel Raynal
2019-06-27 9:50 ` Miquel Raynal
` (11 subsequent siblings)
12 siblings, 0 replies; 49+ messages in thread
From: Miquel Raynal @ 2019-06-27 9:50 UTC (permalink / raw)
To: Gregory Clement, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Kishon Vijay Abraham I
Cc: devicetree, Antoine Tenart, Grzegorz Jaszczyk, Russell King,
Maxime Chevallier, Nadav Haklai, Rob Herring, Thomas Petazzoni,
Miquel Raynal, linux-arm-kernel
Before adding more logic, simplify a bit the writing of the
mvebu_comphy_get_mode() helper by using a pointer instead of
referencing a configuration with the entire table name.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
index 6f8ae72fb9a9..fa222cf8f47b 100644
--- a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
+++ b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
@@ -265,16 +265,18 @@ static int mvebu_comphy_get_mode(bool fw_mode, int lane, int port,
enum phy_mode mode, int submode)
{
int i, n = ARRAY_SIZE(mvebu_comphy_cp110_modes);
+ const struct mvebu_comphy_conf *conf;
/* Unused PHY mux value is 0x0 */
if (mode == PHY_MODE_INVALID)
return 0;
for (i = 0; i < n; i++) {
- if (mvebu_comphy_cp110_modes[i].lane == lane &&
- mvebu_comphy_cp110_modes[i].port == port &&
- mvebu_comphy_cp110_modes[i].mode == mode &&
- mvebu_comphy_cp110_modes[i].submode == submode)
+ conf = &mvebu_comphy_cp110_modes[i];
+ if (conf->lane == lane &&
+ conf->port == port &&
+ conf->mode == mode &&
+ conf->submode == submode)
break;
}
@@ -282,9 +284,9 @@ static int mvebu_comphy_get_mode(bool fw_mode, int lane, int port,
return -EINVAL;
if (fw_mode)
- return mvebu_comphy_cp110_modes[i].fw_mode;
+ return conf->fw_mode;
else
- return mvebu_comphy_cp110_modes[i].mux;
+ return conf->mux;
}
static inline int mvebu_comphy_get_mux(int lane, int port,
--
2.19.1
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 10/19] phy: mvebu-cp110-comphy: Cosmetic change in a helper
@ 2019-06-27 9:50 ` Miquel Raynal
0 siblings, 0 replies; 49+ messages in thread
From: Miquel Raynal @ 2019-06-27 9:50 UTC (permalink / raw)
To: Gregory Clement, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Kishon Vijay Abraham I
Cc: devicetree, Antoine Tenart, Grzegorz Jaszczyk, Russell King,
Maxime Chevallier, Nadav Haklai, Rob Herring, Thomas Petazzoni,
Miquel Raynal, linux-arm-kernel
Before adding more logic, simplify a bit the writing of the
mvebu_comphy_get_mode() helper by using a pointer instead of
referencing a configuration with the entire table name.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
index 6f8ae72fb9a9..fa222cf8f47b 100644
--- a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
+++ b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
@@ -265,16 +265,18 @@ static int mvebu_comphy_get_mode(bool fw_mode, int lane, int port,
enum phy_mode mode, int submode)
{
int i, n = ARRAY_SIZE(mvebu_comphy_cp110_modes);
+ const struct mvebu_comphy_conf *conf;
/* Unused PHY mux value is 0x0 */
if (mode == PHY_MODE_INVALID)
return 0;
for (i = 0; i < n; i++) {
- if (mvebu_comphy_cp110_modes[i].lane == lane &&
- mvebu_comphy_cp110_modes[i].port == port &&
- mvebu_comphy_cp110_modes[i].mode == mode &&
- mvebu_comphy_cp110_modes[i].submode == submode)
+ conf = &mvebu_comphy_cp110_modes[i];
+ if (conf->lane == lane &&
+ conf->port == port &&
+ conf->mode == mode &&
+ conf->submode == submode)
break;
}
@@ -282,9 +284,9 @@ static int mvebu_comphy_get_mode(bool fw_mode, int lane, int port,
return -EINVAL;
if (fw_mode)
- return mvebu_comphy_cp110_modes[i].fw_mode;
+ return conf->fw_mode;
else
- return mvebu_comphy_cp110_modes[i].mux;
+ return conf->mux;
}
static inline int mvebu_comphy_get_mux(int lane, int port,
--
2.19.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 11/19] phy: mvebu-cp110-comphy: Add PCIe support
2019-06-27 9:50 [PATCH v2 00/19] Enhance CP110 COMPHY support Miquel Raynal
@ 2019-06-27 9:50 ` Miquel Raynal
2019-06-27 9:50 ` Miquel Raynal
` (11 subsequent siblings)
12 siblings, 0 replies; 49+ messages in thread
From: Miquel Raynal @ 2019-06-27 9:50 UTC (permalink / raw)
To: Gregory Clement, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Kishon Vijay Abraham I
Cc: devicetree, Antoine Tenart, Grzegorz Jaszczyk, Russell King,
Maxime Chevallier, Nadav Haklai, Rob Herring, Thomas Petazzoni,
Miquel Raynal, linux-arm-kernel
From: Grzegorz Jaszczyk <jaz@semihalf.com>
Add PCIe support by filling the COMPHY modes table.
Also add a new macro to generate the right value for the firmware
depending on the width (PCI x1, x2, x4, etc). The width will be passed
by the core as the "submode" argument of the ->set_mode() callback. If
this argument is zero, default to x1 mode.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
[miquel.raynal@bootlin.com: adapt the content to the mainline driver]
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 37 +++++++++++++++++---
1 file changed, 32 insertions(+), 5 deletions(-)
diff --git a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
index fa222cf8f47b..3fb5517a6d30 100644
--- a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
+++ b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
@@ -128,6 +128,7 @@
* [ 5-11]: COMPHY port index
* [12-16]: COMPHY mode
* [17]: Clock source
+ * [18-20]: PCIe width (x1, x2, x4)
*/
#define COMPHY_FW_POL_OFFSET 0
#define COMPHY_FW_POL_MASK GENMASK(1, 0)
@@ -142,24 +143,31 @@
#define COMPHY_FW_PORT_MASK GENMASK(11, 8)
#define COMPHY_FW_MODE_OFFSET 12
#define COMPHY_FW_MODE_MASK GENMASK(16, 12)
+#define COMPHY_FW_WIDTH_OFFSET 18
+#define COMPHY_FW_WIDTH_MASK GENMASK(20, 18)
-#define COMPHY_FW_PARAM_FULL(mode, port, speed, pol) \
+#define COMPHY_FW_PARAM_FULL(mode, port, speed, pol, width) \
((((pol) << COMPHY_FW_POL_OFFSET) & COMPHY_FW_POL_MASK) | \
(((mode) << COMPHY_FW_MODE_OFFSET) & COMPHY_FW_MODE_MASK) | \
(((port) << COMPHY_FW_PORT_OFFSET) & COMPHY_FW_PORT_MASK) | \
- (((speed) << COMPHY_FW_SPEED_OFFSET) & COMPHY_FW_SPEED_MASK))
+ (((speed) << COMPHY_FW_SPEED_OFFSET) & COMPHY_FW_SPEED_MASK) | \
+ (((width) << COMPHY_FW_WIDTH_OFFSET) & COMPHY_FW_WIDTH_MASK))
#define COMPHY_FW_PARAM(mode, port) \
- COMPHY_FW_PARAM_FULL(mode, port, 0, 0)
+ COMPHY_FW_PARAM_FULL(mode, port, COMPHY_FW_SPEED_MAX, 0, 0)
#define COMPHY_FW_PARAM_ETH(mode, port, speed) \
- COMPHY_FW_PARAM_FULL(mode, port, speed, 0)
+ COMPHY_FW_PARAM_FULL(mode, port, speed, 0, 0)
+
+#define COMPHY_FW_PARAM_PCIE(mode, port, width) \
+ COMPHY_FW_PARAM_FULL(mode, port, COMPHY_FW_SPEED_5000, 0, width)
#define COMPHY_FW_MODE_SATA 0x1
#define COMPHY_FW_MODE_SGMII 0x2 /* SGMII 1G */
#define COMPHY_FW_MODE_HS_SGMII 0x3 /* SGMII 2.5G */
#define COMPHY_FW_MODE_USB3H 0x4
#define COMPHY_FW_MODE_USB3D 0x5
+#define COMPHY_FW_MODE_PCIE 0x6
#define COMPHY_FW_MODE_RXAUI 0x7
#define COMPHY_FW_MODE_XFI 0x8 /* SFI: 0x9 (is treated like XFI) */
@@ -194,6 +202,7 @@ struct mvebu_comphy_conf {
static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = {
/* lane 0 */
+ GEN_CONF(0, 0, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE),
ETH_CONF(0, 1, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
ETH_CONF(0, 1, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
GEN_CONF(0, 1, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),
@@ -201,6 +210,7 @@ static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = {
GEN_CONF(1, 0, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H),
GEN_CONF(1, 0, PHY_MODE_USB_DEVICE_SS, COMPHY_FW_MODE_USB3D),
GEN_CONF(1, 0, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),
+ GEN_CONF(1, 0, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE),
ETH_CONF(1, 2, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
ETH_CONF(1, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
/* lane 2 */
@@ -210,7 +220,9 @@ static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = {
ETH_CONF(2, 0, PHY_INTERFACE_MODE_10GKR, 0x1, COMPHY_FW_MODE_XFI),
GEN_CONF(2, 0, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H),
GEN_CONF(2, 0, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),
+ GEN_CONF(2, 0, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE),
/* lane 3 */
+ GEN_CONF(3, 0, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE),
ETH_CONF(3, 1, PHY_INTERFACE_MODE_SGMII, 0x2, COMPHY_FW_MODE_SGMII),
ETH_CONF(3, 1, PHY_INTERFACE_MODE_2500BASEX, 0x2, COMPHY_FW_MODE_HS_SGMII),
ETH_CONF(3, 1, PHY_INTERFACE_MODE_RXAUI, -1, COMPHY_FW_MODE_RXAUI),
@@ -223,6 +235,7 @@ static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = {
ETH_CONF(4, 0, PHY_INTERFACE_MODE_RXAUI, -1, COMPHY_FW_MODE_RXAUI),
GEN_CONF(4, 0, PHY_MODE_USB_DEVICE_SS, COMPHY_FW_MODE_USB3D),
GEN_CONF(4, 1, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H),
+ GEN_CONF(4, 1, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE),
ETH_CONF(4, 1, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
ETH_CONF(4, 1, PHY_INTERFACE_MODE_2500BASEX, -1, COMPHY_FW_MODE_HS_SGMII),
ETH_CONF(4, 1, PHY_INTERFACE_MODE_10GKR, -1, COMPHY_FW_MODE_XFI),
@@ -231,6 +244,7 @@ static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = {
GEN_CONF(5, 1, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),
ETH_CONF(5, 2, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
ETH_CONF(5, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
+ GEN_CONF(5, 2, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE),
};
struct mvebu_comphy_priv {
@@ -265,6 +279,8 @@ static int mvebu_comphy_get_mode(bool fw_mode, int lane, int port,
enum phy_mode mode, int submode)
{
int i, n = ARRAY_SIZE(mvebu_comphy_cp110_modes);
+ /* Ignore PCIe submode: it represents the width */
+ bool ignore_submode = (mode == PHY_MODE_PCIE);
const struct mvebu_comphy_conf *conf;
/* Unused PHY mux value is 0x0 */
@@ -276,7 +292,7 @@ static int mvebu_comphy_get_mode(bool fw_mode, int lane, int port,
if (conf->lane == lane &&
conf->port == port &&
conf->mode == mode &&
- conf->submode == submode)
+ (conf->submode == submode || ignore_submode))
break;
}
@@ -678,6 +694,12 @@ static int mvebu_comphy_power_on(struct phy *phy)
dev_dbg(priv->dev, "set lane %d to SATA mode\n", lane->id);
fw_param = COMPHY_FW_PARAM(fw_mode, lane->port);
break;
+ case PHY_MODE_PCIE:
+ dev_dbg(priv->dev, "set lane %d to PCIe mode (x%d)\n", lane->id,
+ lane->submode);
+ fw_param = COMPHY_FW_PARAM_PCIE(fw_mode, lane->port,
+ lane->submode);
+ break;
default:
dev_err(priv->dev, "unsupported PHY mode (%d)\n", lane->mode);
return -ENOTSUPP;
@@ -714,6 +736,11 @@ static int mvebu_comphy_set_mode(struct phy *phy,
lane->mode = mode;
lane->submode = submode;
+
+ /* PCIe submode represents the width */
+ if (mode == PHY_MODE_PCIE && !lane->submode)
+ lane->submode = 1;
+
return 0;
}
--
2.19.1
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 11/19] phy: mvebu-cp110-comphy: Add PCIe support
@ 2019-06-27 9:50 ` Miquel Raynal
0 siblings, 0 replies; 49+ messages in thread
From: Miquel Raynal @ 2019-06-27 9:50 UTC (permalink / raw)
To: Gregory Clement, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Kishon Vijay Abraham I
Cc: devicetree, Antoine Tenart, Grzegorz Jaszczyk, Russell King,
Maxime Chevallier, Nadav Haklai, Rob Herring, Thomas Petazzoni,
Miquel Raynal, linux-arm-kernel
From: Grzegorz Jaszczyk <jaz@semihalf.com>
Add PCIe support by filling the COMPHY modes table.
Also add a new macro to generate the right value for the firmware
depending on the width (PCI x1, x2, x4, etc). The width will be passed
by the core as the "submode" argument of the ->set_mode() callback. If
this argument is zero, default to x1 mode.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
[miquel.raynal@bootlin.com: adapt the content to the mainline driver]
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 37 +++++++++++++++++---
1 file changed, 32 insertions(+), 5 deletions(-)
diff --git a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
index fa222cf8f47b..3fb5517a6d30 100644
--- a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
+++ b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
@@ -128,6 +128,7 @@
* [ 5-11]: COMPHY port index
* [12-16]: COMPHY mode
* [17]: Clock source
+ * [18-20]: PCIe width (x1, x2, x4)
*/
#define COMPHY_FW_POL_OFFSET 0
#define COMPHY_FW_POL_MASK GENMASK(1, 0)
@@ -142,24 +143,31 @@
#define COMPHY_FW_PORT_MASK GENMASK(11, 8)
#define COMPHY_FW_MODE_OFFSET 12
#define COMPHY_FW_MODE_MASK GENMASK(16, 12)
+#define COMPHY_FW_WIDTH_OFFSET 18
+#define COMPHY_FW_WIDTH_MASK GENMASK(20, 18)
-#define COMPHY_FW_PARAM_FULL(mode, port, speed, pol) \
+#define COMPHY_FW_PARAM_FULL(mode, port, speed, pol, width) \
((((pol) << COMPHY_FW_POL_OFFSET) & COMPHY_FW_POL_MASK) | \
(((mode) << COMPHY_FW_MODE_OFFSET) & COMPHY_FW_MODE_MASK) | \
(((port) << COMPHY_FW_PORT_OFFSET) & COMPHY_FW_PORT_MASK) | \
- (((speed) << COMPHY_FW_SPEED_OFFSET) & COMPHY_FW_SPEED_MASK))
+ (((speed) << COMPHY_FW_SPEED_OFFSET) & COMPHY_FW_SPEED_MASK) | \
+ (((width) << COMPHY_FW_WIDTH_OFFSET) & COMPHY_FW_WIDTH_MASK))
#define COMPHY_FW_PARAM(mode, port) \
- COMPHY_FW_PARAM_FULL(mode, port, 0, 0)
+ COMPHY_FW_PARAM_FULL(mode, port, COMPHY_FW_SPEED_MAX, 0, 0)
#define COMPHY_FW_PARAM_ETH(mode, port, speed) \
- COMPHY_FW_PARAM_FULL(mode, port, speed, 0)
+ COMPHY_FW_PARAM_FULL(mode, port, speed, 0, 0)
+
+#define COMPHY_FW_PARAM_PCIE(mode, port, width) \
+ COMPHY_FW_PARAM_FULL(mode, port, COMPHY_FW_SPEED_5000, 0, width)
#define COMPHY_FW_MODE_SATA 0x1
#define COMPHY_FW_MODE_SGMII 0x2 /* SGMII 1G */
#define COMPHY_FW_MODE_HS_SGMII 0x3 /* SGMII 2.5G */
#define COMPHY_FW_MODE_USB3H 0x4
#define COMPHY_FW_MODE_USB3D 0x5
+#define COMPHY_FW_MODE_PCIE 0x6
#define COMPHY_FW_MODE_RXAUI 0x7
#define COMPHY_FW_MODE_XFI 0x8 /* SFI: 0x9 (is treated like XFI) */
@@ -194,6 +202,7 @@ struct mvebu_comphy_conf {
static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = {
/* lane 0 */
+ GEN_CONF(0, 0, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE),
ETH_CONF(0, 1, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
ETH_CONF(0, 1, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
GEN_CONF(0, 1, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),
@@ -201,6 +210,7 @@ static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = {
GEN_CONF(1, 0, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H),
GEN_CONF(1, 0, PHY_MODE_USB_DEVICE_SS, COMPHY_FW_MODE_USB3D),
GEN_CONF(1, 0, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),
+ GEN_CONF(1, 0, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE),
ETH_CONF(1, 2, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
ETH_CONF(1, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
/* lane 2 */
@@ -210,7 +220,9 @@ static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = {
ETH_CONF(2, 0, PHY_INTERFACE_MODE_10GKR, 0x1, COMPHY_FW_MODE_XFI),
GEN_CONF(2, 0, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H),
GEN_CONF(2, 0, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),
+ GEN_CONF(2, 0, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE),
/* lane 3 */
+ GEN_CONF(3, 0, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE),
ETH_CONF(3, 1, PHY_INTERFACE_MODE_SGMII, 0x2, COMPHY_FW_MODE_SGMII),
ETH_CONF(3, 1, PHY_INTERFACE_MODE_2500BASEX, 0x2, COMPHY_FW_MODE_HS_SGMII),
ETH_CONF(3, 1, PHY_INTERFACE_MODE_RXAUI, -1, COMPHY_FW_MODE_RXAUI),
@@ -223,6 +235,7 @@ static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = {
ETH_CONF(4, 0, PHY_INTERFACE_MODE_RXAUI, -1, COMPHY_FW_MODE_RXAUI),
GEN_CONF(4, 0, PHY_MODE_USB_DEVICE_SS, COMPHY_FW_MODE_USB3D),
GEN_CONF(4, 1, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H),
+ GEN_CONF(4, 1, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE),
ETH_CONF(4, 1, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
ETH_CONF(4, 1, PHY_INTERFACE_MODE_2500BASEX, -1, COMPHY_FW_MODE_HS_SGMII),
ETH_CONF(4, 1, PHY_INTERFACE_MODE_10GKR, -1, COMPHY_FW_MODE_XFI),
@@ -231,6 +244,7 @@ static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = {
GEN_CONF(5, 1, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),
ETH_CONF(5, 2, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
ETH_CONF(5, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),
+ GEN_CONF(5, 2, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE),
};
struct mvebu_comphy_priv {
@@ -265,6 +279,8 @@ static int mvebu_comphy_get_mode(bool fw_mode, int lane, int port,
enum phy_mode mode, int submode)
{
int i, n = ARRAY_SIZE(mvebu_comphy_cp110_modes);
+ /* Ignore PCIe submode: it represents the width */
+ bool ignore_submode = (mode == PHY_MODE_PCIE);
const struct mvebu_comphy_conf *conf;
/* Unused PHY mux value is 0x0 */
@@ -276,7 +292,7 @@ static int mvebu_comphy_get_mode(bool fw_mode, int lane, int port,
if (conf->lane == lane &&
conf->port == port &&
conf->mode == mode &&
- conf->submode == submode)
+ (conf->submode == submode || ignore_submode))
break;
}
@@ -678,6 +694,12 @@ static int mvebu_comphy_power_on(struct phy *phy)
dev_dbg(priv->dev, "set lane %d to SATA mode\n", lane->id);
fw_param = COMPHY_FW_PARAM(fw_mode, lane->port);
break;
+ case PHY_MODE_PCIE:
+ dev_dbg(priv->dev, "set lane %d to PCIe mode (x%d)\n", lane->id,
+ lane->submode);
+ fw_param = COMPHY_FW_PARAM_PCIE(fw_mode, lane->port,
+ lane->submode);
+ break;
default:
dev_err(priv->dev, "unsupported PHY mode (%d)\n", lane->mode);
return -ENOTSUPP;
@@ -714,6 +736,11 @@ static int mvebu_comphy_set_mode(struct phy *phy,
lane->mode = mode;
lane->submode = submode;
+
+ /* PCIe submode represents the width */
+ if (mode == PHY_MODE_PCIE && !lane->submode)
+ lane->submode = 1;
+
return 0;
}
--
2.19.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 12/19] phy: mvebu-cp110-comphy: Update comment about powering off all lanes at boot
2019-06-27 9:50 [PATCH v2 00/19] Enhance CP110 COMPHY support Miquel Raynal
@ 2019-06-27 9:50 ` Miquel Raynal
2019-06-27 9:50 ` Miquel Raynal
` (11 subsequent siblings)
12 siblings, 0 replies; 49+ messages in thread
From: Miquel Raynal @ 2019-06-27 9:50 UTC (permalink / raw)
To: Gregory Clement, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Kishon Vijay Abraham I
Cc: devicetree, Antoine Tenart, Grzegorz Jaszczyk, Russell King,
Maxime Chevallier, Nadav Haklai, Rob Herring, Thomas Petazzoni,
Miquel Raynal, linux-arm-kernel
Now that all COMPHY modes are supported by the driver, update the
comment stating that mvebu_comphy_power_off() should be called for
each lane. This is still wrong because for compatibility reasons, it
might break users running an old firmware (the driver only uses SMC
calls for SATA, USB and PCIe configuration, there is no code in Linux
to fallback on in these cases.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
index 3fb5517a6d30..36b2056eac99 100644
--- a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
+++ b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
@@ -941,9 +941,11 @@ static int mvebu_comphy_probe(struct platform_device *pdev)
phy_set_drvdata(phy, lane);
/*
- * Once all modes are supported in this driver we should call
+ * All modes are supported in this driver so we could call
* mvebu_comphy_power_off(phy) here to avoid relying on the
- * bootloader/firmware configuration.
+ * bootloader/firmware configuration, but for compatibility
+ * reasons we cannot de-configure the COMPHY without being sure
+ * that the firmware is up-to-date and fully-featured.
*/
}
--
2.19.1
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 12/19] phy: mvebu-cp110-comphy: Update comment about powering off all lanes at boot
@ 2019-06-27 9:50 ` Miquel Raynal
0 siblings, 0 replies; 49+ messages in thread
From: Miquel Raynal @ 2019-06-27 9:50 UTC (permalink / raw)
To: Gregory Clement, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Kishon Vijay Abraham I
Cc: devicetree, Antoine Tenart, Grzegorz Jaszczyk, Russell King,
Maxime Chevallier, Nadav Haklai, Rob Herring, Thomas Petazzoni,
Miquel Raynal, linux-arm-kernel
Now that all COMPHY modes are supported by the driver, update the
comment stating that mvebu_comphy_power_off() should be called for
each lane. This is still wrong because for compatibility reasons, it
might break users running an old firmware (the driver only uses SMC
calls for SATA, USB and PCIe configuration, there is no code in Linux
to fallback on in these cases.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
index 3fb5517a6d30..36b2056eac99 100644
--- a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
+++ b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
@@ -941,9 +941,11 @@ static int mvebu_comphy_probe(struct platform_device *pdev)
phy_set_drvdata(phy, lane);
/*
- * Once all modes are supported in this driver we should call
+ * All modes are supported in this driver so we could call
* mvebu_comphy_power_off(phy) here to avoid relying on the
- * bootloader/firmware configuration.
+ * bootloader/firmware configuration, but for compatibility
+ * reasons we cannot de-configure the COMPHY without being sure
+ * that the firmware is up-to-date and fully-featured.
*/
}
--
2.19.1
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^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 13/19] dt-bindings: phy: Add Marvell COMPHY clocks
2019-06-27 9:50 [PATCH v2 00/19] Enhance CP110 COMPHY support Miquel Raynal
@ 2019-06-27 12:24 ` Miquel Raynal
2019-06-27 9:50 ` Miquel Raynal
` (11 subsequent siblings)
12 siblings, 0 replies; 49+ messages in thread
From: Miquel Raynal @ 2019-06-27 12:24 UTC (permalink / raw)
To: Gregory Clement, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Kishon Vijay Abraham I
Cc: devicetree, Antoine Tenart, Grzegorz Jaszczyk, Russell King,
Maxime Chevallier, Nadav Haklai, Rob Herring, Thomas Petazzoni,
Miquel Raynal, linux-arm-kernel
Marvell CP110 COMPHY block is fed by 3 clocks. Describe each of them in the
bindings.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
.../devicetree/bindings/phy/phy-mvebu-comphy.txt | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt b/Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt
index cf2cd86db267..8c60e6985950 100644
--- a/Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt
+++ b/Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt
@@ -25,6 +25,13 @@ Required properties:
- #address-cells: should be 1.
- #size-cells: should be 0.
+Optional properlties:
+
+- clocks: pointers to the reference clocks for this device (CP110 only),
+ consequently: MG clock, MG Core clock, AXI clock.
+- clock-names: names of used clocks for CP110 only, must be :
+ "mg_clk", "mg_core_clk" and "axi_clk".
+
A sub-node is required for each comphy lane provided by the comphy.
Required properties (child nodes):
@@ -39,6 +46,9 @@ Examples:
compatible = "marvell,comphy-cp110";
reg = <0x120000 0x6000>;
marvell,system-controller = <&cpm_syscon0>;
+ clocks = <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 6>,
+ <&CP110_LABEL(clk) 1 18>;
+ clock-names = "mg_clk", "mg_core_clk", "axi_clk";
#address-cells = <1>;
#size-cells = <0>;
--
2.19.1
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 13/19] dt-bindings: phy: Add Marvell COMPHY clocks
@ 2019-06-27 12:24 ` Miquel Raynal
0 siblings, 0 replies; 49+ messages in thread
From: Miquel Raynal @ 2019-06-27 12:24 UTC (permalink / raw)
To: Gregory Clement, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Kishon Vijay Abraham I
Cc: devicetree, Antoine Tenart, Grzegorz Jaszczyk, Russell King,
Maxime Chevallier, Nadav Haklai, Rob Herring, Thomas Petazzoni,
Miquel Raynal, linux-arm-kernel
Marvell CP110 COMPHY block is fed by 3 clocks. Describe each of them in the
bindings.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
.../devicetree/bindings/phy/phy-mvebu-comphy.txt | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt b/Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt
index cf2cd86db267..8c60e6985950 100644
--- a/Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt
+++ b/Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt
@@ -25,6 +25,13 @@ Required properties:
- #address-cells: should be 1.
- #size-cells: should be 0.
+Optional properlties:
+
+- clocks: pointers to the reference clocks for this device (CP110 only),
+ consequently: MG clock, MG Core clock, AXI clock.
+- clock-names: names of used clocks for CP110 only, must be :
+ "mg_clk", "mg_core_clk" and "axi_clk".
+
A sub-node is required for each comphy lane provided by the comphy.
Required properties (child nodes):
@@ -39,6 +46,9 @@ Examples:
compatible = "marvell,comphy-cp110";
reg = <0x120000 0x6000>;
marvell,system-controller = <&cpm_syscon0>;
+ clocks = <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 6>,
+ <&CP110_LABEL(clk) 1 18>;
+ clock-names = "mg_clk", "mg_core_clk", "axi_clk";
#address-cells = <1>;
#size-cells = <0>;
--
2.19.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 14/19] dt-bindings: pci: add PHY properties to Armada 7K/8K controller bindings
2019-06-27 12:24 ` Miquel Raynal
@ 2019-06-27 12:25 ` Miquel Raynal
-1 siblings, 0 replies; 49+ messages in thread
From: Miquel Raynal @ 2019-06-27 12:25 UTC (permalink / raw)
To: Gregory Clement, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Kishon Vijay Abraham I
Cc: devicetree, Antoine Tenart, Grzegorz Jaszczyk, Russell King,
Maxime Chevallier, Nadav Haklai, Rob Herring, Thomas Petazzoni,
Miquel Raynal, linux-arm-kernel
Armada CP110 PCIe controller can have a PHY (for configuring SERDES
lanes). Describe these two properties in the bindings.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
Documentation/devicetree/bindings/pci/pci-armada8k.txt | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/pci-armada8k.txt b/Documentation/devicetree/bindings/pci/pci-armada8k.txt
index 9e3fc15e1af8..a373a80524db 100644
--- a/Documentation/devicetree/bindings/pci/pci-armada8k.txt
+++ b/Documentation/devicetree/bindings/pci/pci-armada8k.txt
@@ -17,6 +17,10 @@ Required properties:
name must be "core" for the first clock and "reg" for the second
one
+Optional properties:
+- phys: phandle to the PHY node (generic PHY bindings).
+- phy-names: names of the PHYs.
+
Example:
pcie@f2600000 {
--
2.19.1
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 14/19] dt-bindings: pci: add PHY properties to Armada 7K/8K controller bindings
@ 2019-06-27 12:25 ` Miquel Raynal
0 siblings, 0 replies; 49+ messages in thread
From: Miquel Raynal @ 2019-06-27 12:25 UTC (permalink / raw)
To: Gregory Clement, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Kishon Vijay Abraham I
Cc: devicetree, Antoine Tenart, Grzegorz Jaszczyk, Russell King,
Maxime Chevallier, Nadav Haklai, Rob Herring, Thomas Petazzoni,
Miquel Raynal, linux-arm-kernel
Armada CP110 PCIe controller can have a PHY (for configuring SERDES
lanes). Describe these two properties in the bindings.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
Documentation/devicetree/bindings/pci/pci-armada8k.txt | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/pci-armada8k.txt b/Documentation/devicetree/bindings/pci/pci-armada8k.txt
index 9e3fc15e1af8..a373a80524db 100644
--- a/Documentation/devicetree/bindings/pci/pci-armada8k.txt
+++ b/Documentation/devicetree/bindings/pci/pci-armada8k.txt
@@ -17,6 +17,10 @@ Required properties:
name must be "core" for the first clock and "reg" for the second
one
+Optional properties:
+- phys: phandle to the PHY node (generic PHY bindings).
+- phy-names: names of the PHYs.
+
Example:
pcie@f2600000 {
--
2.19.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 49+ messages in thread* Re: [PATCH v2 14/19] dt-bindings: pci: add PHY properties to Armada 7K/8K controller bindings
2019-06-27 12:25 ` Miquel Raynal
@ 2019-07-22 17:52 ` Rob Herring
-1 siblings, 0 replies; 49+ messages in thread
From: Rob Herring @ 2019-07-22 17:52 UTC (permalink / raw)
To: Miquel Raynal
Cc: Andrew Lunn, Jason Cooper, devicetree, Antoine Tenart,
Grzegorz Jaszczyk, Gregory Clement, Russell King,
Kishon Vijay Abraham I, Nadav Haklai, Thomas Petazzoni,
Maxime Chevallier, linux-arm-kernel, Sebastian Hesselbarth
On Thu, Jun 27, 2019 at 02:25:00PM +0200, Miquel Raynal wrote:
> Armada CP110 PCIe controller can have a PHY (for configuring SERDES
> lanes). Describe these two properties in the bindings.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> ---
> Documentation/devicetree/bindings/pci/pci-armada8k.txt | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/pci-armada8k.txt b/Documentation/devicetree/bindings/pci/pci-armada8k.txt
> index 9e3fc15e1af8..a373a80524db 100644
> --- a/Documentation/devicetree/bindings/pci/pci-armada8k.txt
> +++ b/Documentation/devicetree/bindings/pci/pci-armada8k.txt
> @@ -17,6 +17,10 @@ Required properties:
> name must be "core" for the first clock and "reg" for the second
> one
>
> +Optional properties:
> +- phys: phandle to the PHY node (generic PHY bindings).
> +- phy-names: names of the PHYs.
How many? If only 1, you don't really need phy-names.
> +
> Example:
>
> pcie@f2600000 {
> --
> 2.19.1
>
^ permalink raw reply [flat|nested] 49+ messages in thread* Re: [PATCH v2 14/19] dt-bindings: pci: add PHY properties to Armada 7K/8K controller bindings
@ 2019-07-22 17:52 ` Rob Herring
0 siblings, 0 replies; 49+ messages in thread
From: Rob Herring @ 2019-07-22 17:52 UTC (permalink / raw)
To: Miquel Raynal
Cc: Andrew Lunn, Jason Cooper, devicetree, Antoine Tenart,
Grzegorz Jaszczyk, Gregory Clement, Russell King,
Kishon Vijay Abraham I, Nadav Haklai, Thomas Petazzoni,
Maxime Chevallier, linux-arm-kernel, Sebastian Hesselbarth
On Thu, Jun 27, 2019 at 02:25:00PM +0200, Miquel Raynal wrote:
> Armada CP110 PCIe controller can have a PHY (for configuring SERDES
> lanes). Describe these two properties in the bindings.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> ---
> Documentation/devicetree/bindings/pci/pci-armada8k.txt | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/pci-armada8k.txt b/Documentation/devicetree/bindings/pci/pci-armada8k.txt
> index 9e3fc15e1af8..a373a80524db 100644
> --- a/Documentation/devicetree/bindings/pci/pci-armada8k.txt
> +++ b/Documentation/devicetree/bindings/pci/pci-armada8k.txt
> @@ -17,6 +17,10 @@ Required properties:
> name must be "core" for the first clock and "reg" for the second
> one
>
> +Optional properties:
> +- phys: phandle to the PHY node (generic PHY bindings).
> +- phy-names: names of the PHYs.
How many? If only 1, you don't really need phy-names.
> +
> Example:
>
> pcie@f2600000 {
> --
> 2.19.1
>
_______________________________________________
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^ permalink raw reply [flat|nested] 49+ messages in thread* Re: [PATCH v2 14/19] dt-bindings: pci: add PHY properties to Armada 7K/8K controller bindings
2019-07-22 17:52 ` Rob Herring
(?)
@ 2019-07-23 8:35 ` Miquel Raynal
-1 siblings, 0 replies; 49+ messages in thread
From: Miquel Raynal @ 2019-07-23 8:35 UTC (permalink / raw)
To: Rob Herring
Cc: Andrew Lunn, Jason Cooper, devicetree, Antoine Tenart,
Grzegorz Jaszczyk, Gregory Clement, Russell King,
Kishon Vijay Abraham I, Nadav Haklai, Thomas Petazzoni,
Maxime Chevallier, linux-arm-kernel, Sebastian Hesselbarth
Hi Rob,
Rob Herring <robh@kernel.org> wrote on Mon, 22 Jul 2019 11:52:25 -0600:
> On Thu, Jun 27, 2019 at 02:25:00PM +0200, Miquel Raynal wrote:
> > Armada CP110 PCIe controller can have a PHY (for configuring SERDES
> > lanes). Describe these two properties in the bindings.
> >
> > Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> > ---
> > Documentation/devicetree/bindings/pci/pci-armada8k.txt | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/pci-armada8k.txt b/Documentation/devicetree/bindings/pci/pci-armada8k.txt
> > index 9e3fc15e1af8..a373a80524db 100644
> > --- a/Documentation/devicetree/bindings/pci/pci-armada8k.txt
> > +++ b/Documentation/devicetree/bindings/pci/pci-armada8k.txt
> > @@ -17,6 +17,10 @@ Required properties:
> > name must be "core" for the first clock and "reg" for the second
> > one
> >
> > +Optional properties:
> > +- phys: phandle to the PHY node (generic PHY bindings).
> > +- phy-names: names of the PHYs.
>
> How many? If only 1, you don't really need phy-names.
I thought it was preferred to always add phy-names, but ok, I'll drop
the property.
Thanks,
Miquèl
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 14/19] dt-bindings: pci: add PHY properties to Armada 7K/8K controller bindings
2019-07-22 17:52 ` Rob Herring
(?)
(?)
@ 2019-07-24 15:56 ` Miquel Raynal
-1 siblings, 0 replies; 49+ messages in thread
From: Miquel Raynal @ 2019-07-24 15:56 UTC (permalink / raw)
To: Rob Herring
Cc: Andrew Lunn, Jason Cooper, devicetree, Antoine Tenart,
Grzegorz Jaszczyk, Gregory Clement, Russell King,
Kishon Vijay Abraham I, Nadav Haklai, Thomas Petazzoni,
Maxime Chevallier, linux-arm-kernel, Sebastian Hesselbarth
Hi Rob,
Rob Herring <robh@kernel.org> wrote on Mon, 22 Jul 2019 11:52:25 -0600:
> On Thu, Jun 27, 2019 at 02:25:00PM +0200, Miquel Raynal wrote:
> > Armada CP110 PCIe controller can have a PHY (for configuring SERDES
> > lanes). Describe these two properties in the bindings.
> >
> > Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> > ---
> > Documentation/devicetree/bindings/pci/pci-armada8k.txt | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/pci-armada8k.txt b/Documentation/devicetree/bindings/pci/pci-armada8k.txt
> > index 9e3fc15e1af8..a373a80524db 100644
> > --- a/Documentation/devicetree/bindings/pci/pci-armada8k.txt
> > +++ b/Documentation/devicetree/bindings/pci/pci-armada8k.txt
> > @@ -17,6 +17,10 @@ Required properties:
> > name must be "core" for the first clock and "reg" for the second
> > one
> >
> > +Optional properties:
> > +- phys: phandle to the PHY node (generic PHY bindings).
> > +- phy-names: names of the PHYs.
>
> How many? If only 1, you don't really need phy-names.
Actually it depends on the board. For instance, the MacchiatoBin has
four of them:
--- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
@@ -186,6 +186,10 @@
reset-gpios = <&cp0_gpio2 20 GPIO_ACTIVE_LOW>;
ranges = <0x81000000 0x0 0xf9010000 0x0 0xf9010000 0x0 0x10000
0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>;
+ phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>,
+ <&cp0_comphy2 0>, <&cp0_comphy3 0>;
+ phy-names = "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy",
+ "cp0-pcie0-x4-lane2-phy", "cp0-pcie0-x4-lane3-phy";
status = "okay";
};
Thanks,
Miquèl
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 15/19] arm64: dts: marvell: Add CP110 COMPHY clocks
2019-06-27 12:24 ` Miquel Raynal
@ 2019-06-27 12:25 ` Miquel Raynal
-1 siblings, 0 replies; 49+ messages in thread
From: Miquel Raynal @ 2019-06-27 12:25 UTC (permalink / raw)
To: Gregory Clement, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Kishon Vijay Abraham I
Cc: devicetree, Antoine Tenart, Grzegorz Jaszczyk, Russell King,
Maxime Chevallier, Nadav Haklai, Rob Herring, Thomas Petazzoni,
Miquel Raynal, linux-arm-kernel
Declare the three clocks feeding the COMPHY block.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
index 4d6e4a097f72..404b6ac82aa0 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
@@ -133,6 +133,9 @@
compatible = "marvell,comphy-cp110";
reg = <0x120000 0x6000>;
marvell,system-controller = <&CP110_LABEL(syscon0)>;
+ clocks = <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 6>,
+ <&CP110_LABEL(clk) 1 18>;
+ clock-names = "mg_clk", "mg_core_clk", "axi_clk";
#address-cells = <1>;
#size-cells = <0>;
--
2.19.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 15/19] arm64: dts: marvell: Add CP110 COMPHY clocks
@ 2019-06-27 12:25 ` Miquel Raynal
0 siblings, 0 replies; 49+ messages in thread
From: Miquel Raynal @ 2019-06-27 12:25 UTC (permalink / raw)
To: Gregory Clement, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Kishon Vijay Abraham I
Cc: devicetree, Antoine Tenart, Grzegorz Jaszczyk, Russell King,
Maxime Chevallier, Nadav Haklai, Rob Herring, Thomas Petazzoni,
Miquel Raynal, linux-arm-kernel
Declare the three clocks feeding the COMPHY block.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
index 4d6e4a097f72..404b6ac82aa0 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
@@ -133,6 +133,9 @@
compatible = "marvell,comphy-cp110";
reg = <0x120000 0x6000>;
marvell,system-controller = <&CP110_LABEL(syscon0)>;
+ clocks = <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 6>,
+ <&CP110_LABEL(clk) 1 18>;
+ clock-names = "mg_clk", "mg_core_clk", "axi_clk";
#address-cells = <1>;
#size-cells = <0>;
--
2.19.1
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 16/19] arm64: dts: marvell: Add 7k/8k per-port PHYs in SATA nodes
2019-06-27 12:24 ` Miquel Raynal
@ 2019-06-27 12:25 ` Miquel Raynal
-1 siblings, 0 replies; 49+ messages in thread
From: Miquel Raynal @ 2019-06-27 12:25 UTC (permalink / raw)
To: Gregory Clement, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Kishon Vijay Abraham I
Cc: devicetree, Antoine Tenart, Grzegorz Jaszczyk, Russell King,
Maxime Chevallier, Nadav Haklai, Rob Herring, Thomas Petazzoni,
Miquel Raynal, linux-arm-kernel
Fill-in the missing SATA phys/phy-names DT properties of Armada 7k/8k
based boards.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
.../arm64/boot/dts/marvell/armada-7040-db.dts | 5 +++++
.../marvell/armada-8040-clearfog-gt-8k.dts | 5 +++++
.../arm64/boot/dts/marvell/armada-8040-db.dts | 18 ++++++++++++++++++
.../boot/dts/marvell/armada-8040-mcbin.dtsi | 19 +++++++++++++++++--
arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 10 ++++++++++
5 files changed, 55 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
index d20d84ce7ca8..1f6f79ea286b 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
@@ -191,6 +191,11 @@
&cp0_sata0 {
status = "okay";
+
+ sata-port@1 {
+ phys = <&cp0_comphy3 1>;
+ phy-names = "cp0-sata0-1-phy";
+ };
};
&cp0_usb3_0 {
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
index 9143aa13ceb1..afa98636cb33 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
@@ -347,6 +347,11 @@
&cp1_sata0 {
pinctrl-0 = <&cp0_pci1_reset_pins>;
status = "okay";
+
+ sata-port@1 {
+ phys = <&cp1_comphy0 1>;
+ phy-names = "cp1-sata0-1-phy";
+ };
};
&cp1_mdio {
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
index 9f4f939ab65f..4a68f99fb001 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
@@ -146,6 +146,15 @@
/* CON4 on CP0 expansion */
&cp0_sata0 {
status = "okay";
+
+ sata-port@0 {
+ phys = <&cp0_comphy1 0>;
+ phy-names = "cp0-sata0-0-phy";
+ };
+ sata-port@1 {
+ phys = <&cp0_comphy3 1>;
+ phy-names = "cp0-sata0-1-phy";
+ };
};
/* CON9 on CP0 expansion */
@@ -276,6 +285,15 @@
/* CON4 on CP1 expansion */
&cp1_sata0 {
status = "okay";
+
+ sata-port@0 {
+ phys = <&cp1_comphy1 0>;
+ phy-names = "cp1-sata0-0-phy";
+ };
+ sata-port@1 {
+ phys = <&cp1_comphy3 1>;
+ phy-names = "cp1-sata0-1-phy";
+ };
};
/* CON9 on CP1 expansion */
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
index 329f8ceeebea..a3f2bd64a750 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
@@ -237,8 +237,13 @@
};
&cp0_sata0 {
- /* CPM Lane 0 - U29 */
status = "okay";
+
+ /* CPM Lane 5 - U29 */
+ sata-port@1 {
+ phys = <&cp0_comphy5 1>;
+ phy-names = "cp0-sata0-1-phy";
+ };
};
&cp0_sdhci0 {
@@ -322,9 +327,19 @@
};
&cp1_sata0 {
+ status = "okay";
+
/* CPS Lane 1 - U32 */
+ sata-port@0 {
+ phys = <&cp1_comphy1 0>;
+ phy-names = "cp1-sata0-0-phy";
+ };
+
/* CPS Lane 3 - U31 */
- status = "okay";
+ sata-port@1 {
+ phys = <&cp1_comphy3 1>;
+ phy-names = "cp1-sata0-1-phy";
+ };
};
&cp1_spi1 {
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
index 404b6ac82aa0..c1764ed7e980 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
@@ -307,7 +307,17 @@
interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&CP110_LABEL(clk) 1 15>,
<&CP110_LABEL(clk) 1 16>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
+
+ sata-port@0 {
+ reg = <0>;
+ };
+
+ sata-port@1 {
+ reg = <1>;
+ };
};
CP110_LABEL(xor0): xor@6a0000 {
--
2.19.1
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 16/19] arm64: dts: marvell: Add 7k/8k per-port PHYs in SATA nodes
@ 2019-06-27 12:25 ` Miquel Raynal
0 siblings, 0 replies; 49+ messages in thread
From: Miquel Raynal @ 2019-06-27 12:25 UTC (permalink / raw)
To: Gregory Clement, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Kishon Vijay Abraham I
Cc: devicetree, Antoine Tenart, Grzegorz Jaszczyk, Russell King,
Maxime Chevallier, Nadav Haklai, Rob Herring, Thomas Petazzoni,
Miquel Raynal, linux-arm-kernel
Fill-in the missing SATA phys/phy-names DT properties of Armada 7k/8k
based boards.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
.../arm64/boot/dts/marvell/armada-7040-db.dts | 5 +++++
.../marvell/armada-8040-clearfog-gt-8k.dts | 5 +++++
.../arm64/boot/dts/marvell/armada-8040-db.dts | 18 ++++++++++++++++++
.../boot/dts/marvell/armada-8040-mcbin.dtsi | 19 +++++++++++++++++--
arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 10 ++++++++++
5 files changed, 55 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
index d20d84ce7ca8..1f6f79ea286b 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
@@ -191,6 +191,11 @@
&cp0_sata0 {
status = "okay";
+
+ sata-port@1 {
+ phys = <&cp0_comphy3 1>;
+ phy-names = "cp0-sata0-1-phy";
+ };
};
&cp0_usb3_0 {
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
index 9143aa13ceb1..afa98636cb33 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
@@ -347,6 +347,11 @@
&cp1_sata0 {
pinctrl-0 = <&cp0_pci1_reset_pins>;
status = "okay";
+
+ sata-port@1 {
+ phys = <&cp1_comphy0 1>;
+ phy-names = "cp1-sata0-1-phy";
+ };
};
&cp1_mdio {
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
index 9f4f939ab65f..4a68f99fb001 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
@@ -146,6 +146,15 @@
/* CON4 on CP0 expansion */
&cp0_sata0 {
status = "okay";
+
+ sata-port@0 {
+ phys = <&cp0_comphy1 0>;
+ phy-names = "cp0-sata0-0-phy";
+ };
+ sata-port@1 {
+ phys = <&cp0_comphy3 1>;
+ phy-names = "cp0-sata0-1-phy";
+ };
};
/* CON9 on CP0 expansion */
@@ -276,6 +285,15 @@
/* CON4 on CP1 expansion */
&cp1_sata0 {
status = "okay";
+
+ sata-port@0 {
+ phys = <&cp1_comphy1 0>;
+ phy-names = "cp1-sata0-0-phy";
+ };
+ sata-port@1 {
+ phys = <&cp1_comphy3 1>;
+ phy-names = "cp1-sata0-1-phy";
+ };
};
/* CON9 on CP1 expansion */
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
index 329f8ceeebea..a3f2bd64a750 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
@@ -237,8 +237,13 @@
};
&cp0_sata0 {
- /* CPM Lane 0 - U29 */
status = "okay";
+
+ /* CPM Lane 5 - U29 */
+ sata-port@1 {
+ phys = <&cp0_comphy5 1>;
+ phy-names = "cp0-sata0-1-phy";
+ };
};
&cp0_sdhci0 {
@@ -322,9 +327,19 @@
};
&cp1_sata0 {
+ status = "okay";
+
/* CPS Lane 1 - U32 */
+ sata-port@0 {
+ phys = <&cp1_comphy1 0>;
+ phy-names = "cp1-sata0-0-phy";
+ };
+
/* CPS Lane 3 - U31 */
- status = "okay";
+ sata-port@1 {
+ phys = <&cp1_comphy3 1>;
+ phy-names = "cp1-sata0-1-phy";
+ };
};
&cp1_spi1 {
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
index 404b6ac82aa0..c1764ed7e980 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
@@ -307,7 +307,17 @@
interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&CP110_LABEL(clk) 1 15>,
<&CP110_LABEL(clk) 1 16>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
+
+ sata-port@0 {
+ reg = <0>;
+ };
+
+ sata-port@1 {
+ reg = <1>;
+ };
};
CP110_LABEL(xor0): xor@6a0000 {
--
2.19.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 17/19] arm64: dts: marvell: Add 7k/8k PHYs in USB3 nodes
2019-06-27 12:24 ` Miquel Raynal
@ 2019-06-27 12:25 ` Miquel Raynal
-1 siblings, 0 replies; 49+ messages in thread
From: Miquel Raynal @ 2019-06-27 12:25 UTC (permalink / raw)
To: Gregory Clement, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Kishon Vijay Abraham I
Cc: devicetree, Antoine Tenart, Grzegorz Jaszczyk, Russell King,
Maxime Chevallier, Nadav Haklai, Rob Herring, Thomas Petazzoni,
Miquel Raynal, linux-arm-kernel
Fill-in the missing USB3 phys/phy-names DT properties of Armada 7k/8k
based boards. Only update nodes actually enabling USB3 in the default
(mainline) configuration. A few USB nodes are enabled but there is
only USB2 working on them.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
arch/arm64/boot/dts/marvell/armada-7040-db.dts | 4 ++++
arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts | 2 ++
arch/arm64/boot/dts/marvell/armada-8040-db.dts | 2 ++
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi | 2 ++
4 files changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
index 1f6f79ea286b..81b54a6ccfe5 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
@@ -200,11 +200,15 @@
&cp0_usb3_0 {
usb-phy = <&cp0_usb3_0_phy>;
+ phys = <&cp0_comphy1 0>;
+ phy-names = "cp0-usb3h0-comphy";
status = "okay";
};
&cp0_usb3_1 {
usb-phy = <&cp0_usb3_1_phy>;
+ phys = <&cp0_comphy4 1>;
+ phy-names = "cp0-usb3h1-comphy";
status = "okay";
};
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
index afa98636cb33..f5af42aa31c7 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
@@ -473,5 +473,7 @@
&cp1_usb3_0 {
usb-phy = <&usb3h0_phy>;
+ phys = <&cp1_comphy2 0>;
+ phy-names = "cp1-usb3h0-comphy";
status = "okay";
};
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
index 4a68f99fb001..f74513056d41 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
@@ -166,6 +166,8 @@
/* CON10 on CP0 expansion */
&cp0_usb3_1 {
usb-phy = <&cp0_usb3_1_phy>;
+ phys = <&cp0_comphy4 1>;
+ phy-names = "cp0-usb3h1-comphy";
status = "okay";
};
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
index a3f2bd64a750..50688271158d 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
@@ -357,5 +357,7 @@
&cp1_usb3_0 {
/* CPS Lane 2 - CON7 */
usb-phy = <&usb3h0_phy>;
+ phys = <&cp1_comphy2 0>;
+ phy-names = "cp1-usb3h0-comphy";
status = "okay";
};
--
2.19.1
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 17/19] arm64: dts: marvell: Add 7k/8k PHYs in USB3 nodes
@ 2019-06-27 12:25 ` Miquel Raynal
0 siblings, 0 replies; 49+ messages in thread
From: Miquel Raynal @ 2019-06-27 12:25 UTC (permalink / raw)
To: Gregory Clement, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Kishon Vijay Abraham I
Cc: devicetree, Antoine Tenart, Grzegorz Jaszczyk, Russell King,
Maxime Chevallier, Nadav Haklai, Rob Herring, Thomas Petazzoni,
Miquel Raynal, linux-arm-kernel
Fill-in the missing USB3 phys/phy-names DT properties of Armada 7k/8k
based boards. Only update nodes actually enabling USB3 in the default
(mainline) configuration. A few USB nodes are enabled but there is
only USB2 working on them.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
arch/arm64/boot/dts/marvell/armada-7040-db.dts | 4 ++++
arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts | 2 ++
arch/arm64/boot/dts/marvell/armada-8040-db.dts | 2 ++
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi | 2 ++
4 files changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
index 1f6f79ea286b..81b54a6ccfe5 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
@@ -200,11 +200,15 @@
&cp0_usb3_0 {
usb-phy = <&cp0_usb3_0_phy>;
+ phys = <&cp0_comphy1 0>;
+ phy-names = "cp0-usb3h0-comphy";
status = "okay";
};
&cp0_usb3_1 {
usb-phy = <&cp0_usb3_1_phy>;
+ phys = <&cp0_comphy4 1>;
+ phy-names = "cp0-usb3h1-comphy";
status = "okay";
};
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
index afa98636cb33..f5af42aa31c7 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
@@ -473,5 +473,7 @@
&cp1_usb3_0 {
usb-phy = <&usb3h0_phy>;
+ phys = <&cp1_comphy2 0>;
+ phy-names = "cp1-usb3h0-comphy";
status = "okay";
};
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
index 4a68f99fb001..f74513056d41 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
@@ -166,6 +166,8 @@
/* CON10 on CP0 expansion */
&cp0_usb3_1 {
usb-phy = <&cp0_usb3_1_phy>;
+ phys = <&cp0_comphy4 1>;
+ phy-names = "cp0-usb3h1-comphy";
status = "okay";
};
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
index a3f2bd64a750..50688271158d 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
@@ -357,5 +357,7 @@
&cp1_usb3_0 {
/* CPS Lane 2 - CON7 */
usb-phy = <&usb3h0_phy>;
+ phys = <&cp1_comphy2 0>;
+ phy-names = "cp1-usb3h0-comphy";
status = "okay";
};
--
2.19.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 18/19] arm64: dts: marvell: Add 7k/8k PHYs in PCIe nodes
2019-06-27 12:24 ` Miquel Raynal
@ 2019-06-27 12:25 ` Miquel Raynal
-1 siblings, 0 replies; 49+ messages in thread
From: Miquel Raynal @ 2019-06-27 12:25 UTC (permalink / raw)
To: Gregory Clement, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Kishon Vijay Abraham I
Cc: devicetree, Antoine Tenart, Grzegorz Jaszczyk, Russell King,
Maxime Chevallier, Nadav Haklai, Rob Herring, Thomas Petazzoni,
Miquel Raynal, linux-arm-kernel
Fill-in the missing PCIe phys/phy-names DT properties of Armada 7k/8k
based boards.
The MacchiatoBin is a bit particular as the Armada8k-PCI IP supports
x4 link widths and in this case the PHY for each lane must be
referenced.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
arch/arm64/boot/dts/marvell/armada-7040-db.dts | 2 ++
.../boot/dts/marvell/armada-8040-clearfog-gt-8k.dts | 2 ++
arch/arm64/boot/dts/marvell/armada-8040-db.dts | 10 ++++++++++
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi | 4 ++++
4 files changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
index 81b54a6ccfe5..e169800cf3f1 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
@@ -96,6 +96,8 @@
&cp0_pcie2 {
status = "okay";
+ phys = <&cp0_comphy5 2>;
+ phy-names = "cp0-pcie2-x1-phy";
};
&cp0_i2c0 {
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
index f5af42aa31c7..078ea1748b60 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
@@ -242,6 +242,8 @@
pinctrl-names = "default";
pinctrl-0 = <&cp0_pci0_reset_pins &cp0_wlan_disable_pins>;
reset-gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>;
+ phys = <&cp0_comphy0 0>;
+ phy-names = "cp0-pcie0-x1-phy";
status = "okay";
};
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
index f74513056d41..a8db6b449f0e 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
@@ -111,11 +111,15 @@
/* CON6 on CP0 expansion */
&cp0_pcie0 {
+ phys = <&cp0_comphy0 0>;
+ phy-names = "cp0-pcie0-x1-phy";
status = "okay";
};
/* CON5 on CP0 expansion */
&cp0_pcie2 {
+ phys = <&cp0_comphy5 2>;
+ phy-names = "cp0-pcie2-x1-phy";
status = "okay";
};
@@ -201,16 +205,22 @@
/* CON6 on CP1 expansion */
&cp1_pcie0 {
+ phys = <&cp1_comphy0 0>;
+ phy-names = "cp1-pcie0-x1-phy";
status = "okay";
};
/* CON7 on CP1 expansion */
&cp1_pcie1 {
+ phys = <&cp1_comphy4 1>;
+ phy-names = "cp1-pcie1-x1-phy";
status = "okay";
};
/* CON5 on CP1 expansion */
&cp1_pcie2 {
+ phys = <&cp1_comphy5 2>;
+ phy-names = "cp1-pcie2-x1-phy";
status = "okay";
};
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
index 50688271158d..9f9d36541ccb 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
@@ -184,6 +184,10 @@
num-lanes = <4>;
num-viewport = <8>;
reset-gpios = <&cp0_gpio2 20 GPIO_ACTIVE_LOW>;
+ phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>,
+ <&cp0_comphy2 0>, <&cp0_comphy3 0>;
+ phy-names = "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy",
+ "cp0-pcie0-x4-lane2-phy", "cp0-pcie0-x4-lane3-phy";
status = "okay";
};
--
2.19.1
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 18/19] arm64: dts: marvell: Add 7k/8k PHYs in PCIe nodes
@ 2019-06-27 12:25 ` Miquel Raynal
0 siblings, 0 replies; 49+ messages in thread
From: Miquel Raynal @ 2019-06-27 12:25 UTC (permalink / raw)
To: Gregory Clement, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Kishon Vijay Abraham I
Cc: devicetree, Antoine Tenart, Grzegorz Jaszczyk, Russell King,
Maxime Chevallier, Nadav Haklai, Rob Herring, Thomas Petazzoni,
Miquel Raynal, linux-arm-kernel
Fill-in the missing PCIe phys/phy-names DT properties of Armada 7k/8k
based boards.
The MacchiatoBin is a bit particular as the Armada8k-PCI IP supports
x4 link widths and in this case the PHY for each lane must be
referenced.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
arch/arm64/boot/dts/marvell/armada-7040-db.dts | 2 ++
.../boot/dts/marvell/armada-8040-clearfog-gt-8k.dts | 2 ++
arch/arm64/boot/dts/marvell/armada-8040-db.dts | 10 ++++++++++
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi | 4 ++++
4 files changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
index 81b54a6ccfe5..e169800cf3f1 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
@@ -96,6 +96,8 @@
&cp0_pcie2 {
status = "okay";
+ phys = <&cp0_comphy5 2>;
+ phy-names = "cp0-pcie2-x1-phy";
};
&cp0_i2c0 {
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
index f5af42aa31c7..078ea1748b60 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
@@ -242,6 +242,8 @@
pinctrl-names = "default";
pinctrl-0 = <&cp0_pci0_reset_pins &cp0_wlan_disable_pins>;
reset-gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>;
+ phys = <&cp0_comphy0 0>;
+ phy-names = "cp0-pcie0-x1-phy";
status = "okay";
};
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
index f74513056d41..a8db6b449f0e 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
@@ -111,11 +111,15 @@
/* CON6 on CP0 expansion */
&cp0_pcie0 {
+ phys = <&cp0_comphy0 0>;
+ phy-names = "cp0-pcie0-x1-phy";
status = "okay";
};
/* CON5 on CP0 expansion */
&cp0_pcie2 {
+ phys = <&cp0_comphy5 2>;
+ phy-names = "cp0-pcie2-x1-phy";
status = "okay";
};
@@ -201,16 +205,22 @@
/* CON6 on CP1 expansion */
&cp1_pcie0 {
+ phys = <&cp1_comphy0 0>;
+ phy-names = "cp1-pcie0-x1-phy";
status = "okay";
};
/* CON7 on CP1 expansion */
&cp1_pcie1 {
+ phys = <&cp1_comphy4 1>;
+ phy-names = "cp1-pcie1-x1-phy";
status = "okay";
};
/* CON5 on CP1 expansion */
&cp1_pcie2 {
+ phys = <&cp1_comphy5 2>;
+ phy-names = "cp1-pcie2-x1-phy";
status = "okay";
};
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
index 50688271158d..9f9d36541ccb 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
@@ -184,6 +184,10 @@
num-lanes = <4>;
num-viewport = <8>;
reset-gpios = <&cp0_gpio2 20 GPIO_ACTIVE_LOW>;
+ phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>,
+ <&cp0_comphy2 0>, <&cp0_comphy3 0>;
+ phy-names = "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy",
+ "cp0-pcie0-x4-lane2-phy", "cp0-pcie0-x4-lane3-phy";
status = "okay";
};
--
2.19.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 19/19] arm64: dts: marvell: Convert 7k/8k usb-phy properties to phy-supply
2019-06-27 12:24 ` Miquel Raynal
@ 2019-06-27 12:25 ` Miquel Raynal
-1 siblings, 0 replies; 49+ messages in thread
From: Miquel Raynal @ 2019-06-27 12:25 UTC (permalink / raw)
To: Gregory Clement, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Kishon Vijay Abraham I
Cc: devicetree, Antoine Tenart, Grzegorz Jaszczyk, Russell King,
Maxime Chevallier, Nadav Haklai, Martin Blumenstingl,
Rob Herring, Thomas Petazzoni, Miquel Raynal, linux-arm-kernel
Update Aramda 7k/8k DTs to use the phy-supply property of the (recent)
generic PHY framework instead of the (legacy) usb-phy preperty. Both
enable the supply when the PHY is enabled.
The COMPHY nodes only provide SERDES lanes configuration. The power
supply that is represented by the phy-supply property is just a
regulator wired to the USB connector, hence the creation of connector
nodes as child of the COMPHY nodes and the supply attached to it.
Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
.../arm64/boot/dts/marvell/armada-7040-db.dts | 26 ++++++++++---------
.../marvell/armada-8040-clearfog-gt-8k.dts | 13 +++++-----
.../arm64/boot/dts/marvell/armada-8040-db.dts | 13 +++++-----
.../boot/dts/marvell/armada-8040-mcbin.dtsi | 13 +++++-----
4 files changed, 35 insertions(+), 30 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
index e169800cf3f1..b478063ab0b4 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
@@ -45,16 +45,6 @@
enable-active-high;
gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
};
-
- cp0_usb3_0_phy: cp0-usb3-0-phy {
- compatible = "usb-nop-xceiv";
- vcc-supply = <&cp0_reg_usb3_0_vbus>;
- };
-
- cp0_usb3_1_phy: cp0-usb3-1-phy {
- compatible = "usb-nop-xceiv";
- vcc-supply = <&cp0_reg_usb3_1_vbus>;
- };
};
&i2c0 {
@@ -200,15 +190,27 @@
};
};
+&cp0_comphy1 {
+ cp0_usbh0_con: connector {
+ compatible = "usb-a-connector";
+ phy-supply = <&cp0_reg_usb3_0_vbus>;
+ };
+};
+
&cp0_usb3_0 {
- usb-phy = <&cp0_usb3_0_phy>;
phys = <&cp0_comphy1 0>;
phy-names = "cp0-usb3h0-comphy";
status = "okay";
};
+&cp0_comphy4 {
+ cp0_usbh1_con: connector {
+ compatible = "usb-a-connector";
+ phy-supply = <&cp0_reg_usb3_1_vbus>;
+ };
+};
+
&cp0_usb3_1 {
- usb-phy = <&cp0_usb3_1_phy>;
phys = <&cp0_comphy4 1>;
phy-names = "cp0-usb3h1-comphy";
status = "okay";
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
index 078ea1748b60..2ae847a42258 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
@@ -51,11 +51,6 @@
status = "okay";
};
- usb3h0_phy: usb3_phy0 {
- compatible = "usb-nop-xceiv";
- vcc-supply = <&v_5v0_usb3_hst_vbus>;
- };
-
sfp_cp0_eth0: sfp-cp0-eth0 {
compatible = "sff,sfp";
i2c-bus = <&cp0_i2c1>;
@@ -473,8 +468,14 @@
};
};
+&cp1_comphy2 {
+ cp1_usbh0_con: connector {
+ compatible = "usb-a-connector";
+ phy-supply = <&v_5v0_usb3_hst_vbus>;
+ };
+};
+
&cp1_usb3_0 {
- usb-phy = <&usb3h0_phy>;
phys = <&cp1_comphy2 0>;
phy-names = "cp1-usb3h0-comphy";
status = "okay";
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
index a8db6b449f0e..77057628f507 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
@@ -52,11 +52,6 @@
vcc-supply = <&cp0_reg_usb3_0_vbus>;
};
- cp0_usb3_1_phy: cp0-usb3-1-phy {
- compatible = "usb-nop-xceiv";
- vcc-supply = <&cp0_reg_usb3_1_vbus>;
- };
-
cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus {
compatible = "regulator-fixed";
regulator-name = "cp1-usb3h0-vbus";
@@ -167,9 +162,15 @@
status = "okay";
};
+&cp0_comphy4 {
+ cp0_usbh1_con: connector {
+ compatible = "usb-a-connector";
+ phy-supply = <&cp0_reg_usb3_1_vbus>;
+ };
+};
+
/* CON10 on CP0 expansion */
&cp0_usb3_1 {
- usb-phy = <&cp0_usb3_1_phy>;
phys = <&cp0_comphy4 1>;
phy-names = "cp0-usb3h1-comphy";
status = "okay";
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
index 9f9d36541ccb..fada138b8b26 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
@@ -61,11 +61,6 @@
status = "okay";
};
- usb3h0_phy: usb3_phy0 {
- compatible = "usb-nop-xceiv";
- vcc-supply = <&v_5v0_usb3_hst_vbus>;
- };
-
sfp_eth0: sfp-eth0 {
/* CON15,16 - CPM lane 4 */
compatible = "sff,sfp";
@@ -358,9 +353,15 @@
};
};
+&cp1_comphy2 {
+ cp1_usbh0_con: connector {
+ compatible = "usb-a-connector";
+ phy-supply = <&v_5v0_usb3_hst_vbus>;
+ };
+};
+
&cp1_usb3_0 {
/* CPS Lane 2 - CON7 */
- usb-phy = <&usb3h0_phy>;
phys = <&cp1_comphy2 0>;
phy-names = "cp1-usb3h0-comphy";
status = "okay";
--
2.19.1
^ permalink raw reply related [flat|nested] 49+ messages in thread* [PATCH v2 19/19] arm64: dts: marvell: Convert 7k/8k usb-phy properties to phy-supply
@ 2019-06-27 12:25 ` Miquel Raynal
0 siblings, 0 replies; 49+ messages in thread
From: Miquel Raynal @ 2019-06-27 12:25 UTC (permalink / raw)
To: Gregory Clement, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, Kishon Vijay Abraham I
Cc: devicetree, Antoine Tenart, Grzegorz Jaszczyk, Russell King,
Maxime Chevallier, Nadav Haklai, Martin Blumenstingl,
Rob Herring, Thomas Petazzoni, Miquel Raynal, linux-arm-kernel
Update Aramda 7k/8k DTs to use the phy-supply property of the (recent)
generic PHY framework instead of the (legacy) usb-phy preperty. Both
enable the supply when the PHY is enabled.
The COMPHY nodes only provide SERDES lanes configuration. The power
supply that is represented by the phy-supply property is just a
regulator wired to the USB connector, hence the creation of connector
nodes as child of the COMPHY nodes and the supply attached to it.
Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
.../arm64/boot/dts/marvell/armada-7040-db.dts | 26 ++++++++++---------
.../marvell/armada-8040-clearfog-gt-8k.dts | 13 +++++-----
.../arm64/boot/dts/marvell/armada-8040-db.dts | 13 +++++-----
.../boot/dts/marvell/armada-8040-mcbin.dtsi | 13 +++++-----
4 files changed, 35 insertions(+), 30 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
index e169800cf3f1..b478063ab0b4 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
@@ -45,16 +45,6 @@
enable-active-high;
gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
};
-
- cp0_usb3_0_phy: cp0-usb3-0-phy {
- compatible = "usb-nop-xceiv";
- vcc-supply = <&cp0_reg_usb3_0_vbus>;
- };
-
- cp0_usb3_1_phy: cp0-usb3-1-phy {
- compatible = "usb-nop-xceiv";
- vcc-supply = <&cp0_reg_usb3_1_vbus>;
- };
};
&i2c0 {
@@ -200,15 +190,27 @@
};
};
+&cp0_comphy1 {
+ cp0_usbh0_con: connector {
+ compatible = "usb-a-connector";
+ phy-supply = <&cp0_reg_usb3_0_vbus>;
+ };
+};
+
&cp0_usb3_0 {
- usb-phy = <&cp0_usb3_0_phy>;
phys = <&cp0_comphy1 0>;
phy-names = "cp0-usb3h0-comphy";
status = "okay";
};
+&cp0_comphy4 {
+ cp0_usbh1_con: connector {
+ compatible = "usb-a-connector";
+ phy-supply = <&cp0_reg_usb3_1_vbus>;
+ };
+};
+
&cp0_usb3_1 {
- usb-phy = <&cp0_usb3_1_phy>;
phys = <&cp0_comphy4 1>;
phy-names = "cp0-usb3h1-comphy";
status = "okay";
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
index 078ea1748b60..2ae847a42258 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
@@ -51,11 +51,6 @@
status = "okay";
};
- usb3h0_phy: usb3_phy0 {
- compatible = "usb-nop-xceiv";
- vcc-supply = <&v_5v0_usb3_hst_vbus>;
- };
-
sfp_cp0_eth0: sfp-cp0-eth0 {
compatible = "sff,sfp";
i2c-bus = <&cp0_i2c1>;
@@ -473,8 +468,14 @@
};
};
+&cp1_comphy2 {
+ cp1_usbh0_con: connector {
+ compatible = "usb-a-connector";
+ phy-supply = <&v_5v0_usb3_hst_vbus>;
+ };
+};
+
&cp1_usb3_0 {
- usb-phy = <&usb3h0_phy>;
phys = <&cp1_comphy2 0>;
phy-names = "cp1-usb3h0-comphy";
status = "okay";
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
index a8db6b449f0e..77057628f507 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
@@ -52,11 +52,6 @@
vcc-supply = <&cp0_reg_usb3_0_vbus>;
};
- cp0_usb3_1_phy: cp0-usb3-1-phy {
- compatible = "usb-nop-xceiv";
- vcc-supply = <&cp0_reg_usb3_1_vbus>;
- };
-
cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus {
compatible = "regulator-fixed";
regulator-name = "cp1-usb3h0-vbus";
@@ -167,9 +162,15 @@
status = "okay";
};
+&cp0_comphy4 {
+ cp0_usbh1_con: connector {
+ compatible = "usb-a-connector";
+ phy-supply = <&cp0_reg_usb3_1_vbus>;
+ };
+};
+
/* CON10 on CP0 expansion */
&cp0_usb3_1 {
- usb-phy = <&cp0_usb3_1_phy>;
phys = <&cp0_comphy4 1>;
phy-names = "cp0-usb3h1-comphy";
status = "okay";
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
index 9f9d36541ccb..fada138b8b26 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
@@ -61,11 +61,6 @@
status = "okay";
};
- usb3h0_phy: usb3_phy0 {
- compatible = "usb-nop-xceiv";
- vcc-supply = <&v_5v0_usb3_hst_vbus>;
- };
-
sfp_eth0: sfp-eth0 {
/* CON15,16 - CPM lane 4 */
compatible = "sff,sfp";
@@ -358,9 +353,15 @@
};
};
+&cp1_comphy2 {
+ cp1_usbh0_con: connector {
+ compatible = "usb-a-connector";
+ phy-supply = <&v_5v0_usb3_hst_vbus>;
+ };
+};
+
&cp1_usb3_0 {
/* CPS Lane 2 - CON7 */
- usb-phy = <&usb3h0_phy>;
phys = <&cp1_comphy2 0>;
phy-names = "cp1-usb3h0-comphy";
status = "okay";
--
2.19.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 49+ messages in thread
* Re: [PATCH v2 13/19] dt-bindings: phy: Add Marvell COMPHY clocks
2019-06-27 12:24 ` Miquel Raynal
@ 2019-07-22 17:51 ` Rob Herring
-1 siblings, 0 replies; 49+ messages in thread
From: Rob Herring @ 2019-07-22 17:51 UTC (permalink / raw)
Cc: Andrew Lunn, Jason Cooper, devicetree, Antoine Tenart,
Grzegorz Jaszczyk, Gregory Clement, Russell King,
Kishon Vijay Abraham I, Nadav Haklai, Thomas Petazzoni,
Miquel Raynal, Maxime Chevallier, linux-arm-kernel,
Sebastian Hesselbarth
On Thu, 27 Jun 2019 14:24:59 +0200, Miquel Raynal wrote:
> Marvell CP110 COMPHY block is fed by 3 clocks. Describe each of them in the
> bindings.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> ---
> .../devicetree/bindings/phy/phy-mvebu-comphy.txt | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 13/19] dt-bindings: phy: Add Marvell COMPHY clocks
@ 2019-07-22 17:51 ` Rob Herring
0 siblings, 0 replies; 49+ messages in thread
From: Rob Herring @ 2019-07-22 17:51 UTC (permalink / raw)
To: Miquel Raynal
Cc: Andrew Lunn, Jason Cooper, devicetree, Antoine Tenart,
Grzegorz Jaszczyk, Gregory Clement, Russell King,
Kishon Vijay Abraham I, Nadav Haklai, Thomas Petazzoni,
Miquel Raynal, Maxime Chevallier, linux-arm-kernel,
Sebastian Hesselbarth
On Thu, 27 Jun 2019 14:24:59 +0200, Miquel Raynal wrote:
> Marvell CP110 COMPHY block is fed by 3 clocks. Describe each of them in the
> bindings.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> ---
> .../devicetree/bindings/phy/phy-mvebu-comphy.txt | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
Reviewed-by: Rob Herring <robh@kernel.org>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 49+ messages in thread