* [PATCH 1/9] drm/i915: Use variable for debugfs device status
2019-07-24 17:12 [PATCH 0/9] Refactor to expand subslice mask (rev 2) Stuart Summers
@ 2019-07-24 17:12 ` Stuart Summers
2019-07-24 17:12 ` [PATCH 2/9] drm/i915: Add function to set SSEU info per platform Stuart Summers
` (10 subsequent siblings)
11 siblings, 0 replies; 23+ messages in thread
From: Stuart Summers @ 2019-07-24 17:12 UTC (permalink / raw)
To: intel-gfx
Use a local variable to find SSEU runtime information
in various debugfs functions.
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 6d3911469801..14eadab4209b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3929,8 +3929,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
sseu->slice_mask |= BIT(s);
if (IS_GEN9_BC(dev_priv))
- sseu->subslice_mask[s] =
- RUNTIME_INFO(dev_priv)->sseu.subslice_mask[s];
+ sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
@@ -3957,6 +3956,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
struct sseu_dev_info *sseu)
{
+ const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
int s;
@@ -3964,10 +3964,10 @@ static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
if (sseu->slice_mask) {
sseu->eu_per_subslice =
- RUNTIME_INFO(dev_priv)->sseu.eu_per_subslice;
+ info->sseu.eu_per_subslice;
for (s = 0; s < fls(sseu->slice_mask); s++) {
sseu->subslice_mask[s] =
- RUNTIME_INFO(dev_priv)->sseu.subslice_mask[s];
+ info->sseu.subslice_mask[s];
}
sseu->eu_total = sseu->eu_per_subslice *
intel_sseu_subslice_total(sseu);
@@ -3975,7 +3975,7 @@ static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
/* subtract fused off EU(s) from enabled slice(s) */
for (s = 0; s < fls(sseu->slice_mask); s++) {
u8 subslice_7eu =
- RUNTIME_INFO(dev_priv)->sseu.subslice_7eu[s];
+ info->sseu.subslice_7eu[s];
sseu->eu_total -= hweight8(subslice_7eu);
}
@@ -4022,6 +4022,7 @@ static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
static int i915_sseu_status(struct seq_file *m, void *unused)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
+ const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
struct sseu_dev_info sseu;
intel_wakeref_t wakeref;
@@ -4029,14 +4030,13 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
return -ENODEV;
seq_puts(m, "SSEU Device Info\n");
- i915_print_sseu_info(m, true, &RUNTIME_INFO(dev_priv)->sseu);
+ i915_print_sseu_info(m, true, &info->sseu);
seq_puts(m, "SSEU Device Status\n");
memset(&sseu, 0, sizeof(sseu));
- sseu.max_slices = RUNTIME_INFO(dev_priv)->sseu.max_slices;
- sseu.max_subslices = RUNTIME_INFO(dev_priv)->sseu.max_subslices;
- sseu.max_eus_per_subslice =
- RUNTIME_INFO(dev_priv)->sseu.max_eus_per_subslice;
+ sseu.max_slices = info->sseu.max_slices;
+ sseu.max_subslices = info->sseu.max_subslices;
+ sseu.max_eus_per_subslice = info->sseu.max_eus_per_subslice;
with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) {
if (IS_CHERRYVIEW(dev_priv))
--
2.21.0.5.gaeb582a983
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 2/9] drm/i915: Add function to set SSEU info per platform
2019-07-24 17:12 [PATCH 0/9] Refactor to expand subslice mask (rev 2) Stuart Summers
2019-07-24 17:12 ` [PATCH 1/9] drm/i915: Use variable for debugfs device status Stuart Summers
@ 2019-07-24 17:12 ` Stuart Summers
2019-07-24 17:12 ` [PATCH 3/9] drm/i915: Add subslice stride runtime parameter Stuart Summers
` (9 subsequent siblings)
11 siblings, 0 replies; 23+ messages in thread
From: Stuart Summers @ 2019-07-24 17:12 UTC (permalink / raw)
To: intel-gfx
Add a new function to allow each platform to set maximum
slice, subslice, and EU information to reduce code duplication.
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 8 +++++
drivers/gpu/drm/i915/gt/intel_sseu.h | 3 ++
drivers/gpu/drm/i915/i915_debugfs.c | 6 ++--
drivers/gpu/drm/i915/intel_device_info.c | 39 +++++++++---------------
4 files changed, 28 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index a0756f006f5f..08b74ae40739 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -8,6 +8,14 @@
#include "intel_lrc_reg.h"
#include "intel_sseu.h"
+void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
+ u8 max_subslices, u8 max_eus_per_subslice)
+{
+ sseu->max_slices = max_slices;
+ sseu->max_subslices = max_subslices;
+ sseu->max_eus_per_subslice = max_eus_per_subslice;
+}
+
unsigned int
intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index b50d0401a4e2..64e47dad07be 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -63,6 +63,9 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
return value;
}
+void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
+ u8 max_subslices, u8 max_eus_per_subslice);
+
unsigned int
intel_sseu_subslice_total(const struct sseu_dev_info *sseu);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 14eadab4209b..011ed2fd391d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4034,9 +4034,9 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
seq_puts(m, "SSEU Device Status\n");
memset(&sseu, 0, sizeof(sseu));
- sseu.max_slices = info->sseu.max_slices;
- sseu.max_subslices = info->sseu.max_subslices;
- sseu.max_eus_per_subslice = info->sseu.max_eus_per_subslice;
+ intel_sseu_set_info(&sseu, info->sseu.max_slices,
+ info->sseu.max_subslices,
+ info->sseu.max_eus_per_subslice);
with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) {
if (IS_CHERRYVIEW(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index f99c9fd497b2..9a79d9d547c5 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -191,15 +191,10 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
u8 eu_en;
int s;
- if (IS_ELKHARTLAKE(dev_priv)) {
- sseu->max_slices = 1;
- sseu->max_subslices = 4;
- sseu->max_eus_per_subslice = 8;
- } else {
- sseu->max_slices = 1;
- sseu->max_subslices = 8;
- sseu->max_eus_per_subslice = 8;
- }
+ if (IS_ELKHARTLAKE(dev_priv))
+ intel_sseu_set_info(sseu, 1, 4, 8);
+ else
+ intel_sseu_set_info(sseu, 1, 8, 8);
s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK;
ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE);
@@ -236,11 +231,10 @@ static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
const int eu_mask = 0xff;
u32 subslice_mask, eu_en;
+ intel_sseu_set_info(sseu, 6, 4, 8);
+
sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
GEN10_F2_S_ENA_SHIFT;
- sseu->max_slices = 6;
- sseu->max_subslices = 4;
- sseu->max_eus_per_subslice = 8;
subslice_mask = (1 << 4) - 1;
subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
@@ -314,9 +308,7 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
fuse = I915_READ(CHV_FUSE_GT);
sseu->slice_mask = BIT(0);
- sseu->max_slices = 1;
- sseu->max_subslices = 2;
- sseu->max_eus_per_subslice = 8;
+ intel_sseu_set_info(sseu, 1, 2, 8);
if (!(fuse & CHV_FGT_DISABLE_SS0)) {
u8 disabled_mask =
@@ -372,9 +364,8 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
/* BXT has a single slice and at most 3 subslices. */
- sseu->max_slices = IS_GEN9_LP(dev_priv) ? 1 : 3;
- sseu->max_subslices = IS_GEN9_LP(dev_priv) ? 3 : 4;
- sseu->max_eus_per_subslice = 8;
+ intel_sseu_set_info(sseu, IS_GEN9_LP(dev_priv) ? 1 : 3,
+ IS_GEN9_LP(dev_priv) ? 3 : 4, 8);
/*
* The subslice disable field is global, i.e. it applies
@@ -473,9 +464,7 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
fuse2 = I915_READ(GEN8_FUSE2);
sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
- sseu->max_slices = 3;
- sseu->max_subslices = 3;
- sseu->max_eus_per_subslice = 8;
+ intel_sseu_set_info(sseu, 3, 3, 8);
/*
* The subslice disable field is global, i.e. it applies
@@ -577,9 +566,6 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
break;
}
- sseu->max_slices = hweight8(sseu->slice_mask);
- sseu->max_subslices = hweight8(sseu->subslice_mask[0]);
-
fuse1 = I915_READ(HSW_PAVP_FUSE1);
switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) {
default:
@@ -596,7 +582,10 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
sseu->eu_per_subslice = 6;
break;
}
- sseu->max_eus_per_subslice = sseu->eu_per_subslice;
+
+ intel_sseu_set_info(sseu, hweight8(sseu->slice_mask),
+ hweight8(sseu->subslice_mask[0]),
+ sseu->eu_per_subslice);
for (s = 0; s < sseu->max_slices; s++) {
for (ss = 0; ss < sseu->max_subslices; ss++) {
--
2.21.0.5.gaeb582a983
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 3/9] drm/i915: Add subslice stride runtime parameter
2019-07-24 17:12 [PATCH 0/9] Refactor to expand subslice mask (rev 2) Stuart Summers
2019-07-24 17:12 ` [PATCH 1/9] drm/i915: Use variable for debugfs device status Stuart Summers
2019-07-24 17:12 ` [PATCH 2/9] drm/i915: Add function to set SSEU info per platform Stuart Summers
@ 2019-07-24 17:12 ` Stuart Summers
2019-07-24 17:12 ` [PATCH 4/9] drm/i915: Add EU " Stuart Summers
` (8 subsequent siblings)
11 siblings, 0 replies; 23+ messages in thread
From: Stuart Summers @ 2019-07-24 17:12 UTC (permalink / raw)
To: intel-gfx
Add a new parameter, ss_stride, to the runtime info
structure. This is used to mirror the userspace concept
of subslice stride, which is a range of subslices per slice.
This patch simply adds the definition and updates usage
in the QUERY_TOPOLOGY_INFO handler.
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 2 ++
drivers/gpu/drm/i915/gt/intel_sseu.h | 2 ++
drivers/gpu/drm/i915/i915_query.c | 5 ++---
3 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 08b74ae40739..2d9e6fa4ee46 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -14,6 +14,8 @@ void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
sseu->max_slices = max_slices;
sseu->max_subslices = max_subslices;
sseu->max_eus_per_subslice = max_eus_per_subslice;
+
+ sseu->ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
}
unsigned int
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 64e47dad07be..b0101e1c69bd 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -33,6 +33,8 @@ struct sseu_dev_info {
u8 max_subslices;
u8 max_eus_per_subslice;
+ u8 ss_stride;
+
/* We don't have more than 8 eus per subslice at the moment and as we
* store eus enabled using bits, no need to multiply by eus per
* subslice.
diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index 7b7016171057..e4aeb7369026 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -37,7 +37,6 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
struct drm_i915_query_topology_info topo;
u32 slice_length, subslice_length, eu_length, total_length;
- u8 subslice_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
u8 eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
int ret;
@@ -50,7 +49,7 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
slice_length = sizeof(sseu->slice_mask);
- subslice_length = sseu->max_slices * subslice_stride;
+ subslice_length = sseu->max_slices * sseu->ss_stride;
eu_length = sseu->max_slices * sseu->max_subslices * eu_stride;
total_length = sizeof(topo) + slice_length + subslice_length +
eu_length;
@@ -69,7 +68,7 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
topo.max_eus_per_subslice = sseu->max_eus_per_subslice;
topo.subslice_offset = slice_length;
- topo.subslice_stride = subslice_stride;
+ topo.subslice_stride = sseu->ss_stride;
topo.eu_offset = slice_length + subslice_length;
topo.eu_stride = eu_stride;
--
2.21.0.5.gaeb582a983
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 4/9] drm/i915: Add EU stride runtime parameter
2019-07-24 17:12 [PATCH 0/9] Refactor to expand subslice mask (rev 2) Stuart Summers
` (2 preceding siblings ...)
2019-07-24 17:12 ` [PATCH 3/9] drm/i915: Add subslice stride runtime parameter Stuart Summers
@ 2019-07-24 17:12 ` Stuart Summers
2019-07-24 17:12 ` [PATCH 5/9] drm/i915: Add function to set subslices Stuart Summers
` (7 subsequent siblings)
11 siblings, 0 replies; 23+ messages in thread
From: Stuart Summers @ 2019-07-24 17:12 UTC (permalink / raw)
To: intel-gfx
Add a new SSEU runtime parameter, eu_stride, which is
used to mirror the userspace concept of a range of EUs
per subslice.
This patch simply adds the parameter and updates usage
in the QUERY_TOPOLOGY_INFO handler.
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 1 +
drivers/gpu/drm/i915/gt/intel_sseu.h | 1 +
drivers/gpu/drm/i915/i915_query.c | 5 ++---
drivers/gpu/drm/i915/intel_device_info.c | 9 ++++-----
4 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 2d9e6fa4ee46..71abf0c9a46b 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -16,6 +16,7 @@ void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
sseu->max_eus_per_subslice = max_eus_per_subslice;
sseu->ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
+ sseu->eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
}
unsigned int
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index b0101e1c69bd..fe22d5b18e67 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -34,6 +34,7 @@ struct sseu_dev_info {
u8 max_eus_per_subslice;
u8 ss_stride;
+ u8 eu_stride;
/* We don't have more than 8 eus per subslice at the moment and as we
* store eus enabled using bits, no need to multiply by eus per
diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index e4aeb7369026..ac8ac59c4860 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -37,7 +37,6 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
struct drm_i915_query_topology_info topo;
u32 slice_length, subslice_length, eu_length, total_length;
- u8 eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
int ret;
if (query_item->flags != 0)
@@ -50,7 +49,7 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
slice_length = sizeof(sseu->slice_mask);
subslice_length = sseu->max_slices * sseu->ss_stride;
- eu_length = sseu->max_slices * sseu->max_subslices * eu_stride;
+ eu_length = sseu->max_slices * sseu->max_subslices * sseu->eu_stride;
total_length = sizeof(topo) + slice_length + subslice_length +
eu_length;
@@ -70,7 +69,7 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
topo.subslice_offset = slice_length;
topo.subslice_stride = sseu->ss_stride;
topo.eu_offset = slice_length + subslice_length;
- topo.eu_stride = eu_stride;
+ topo.eu_stride = sseu->eu_stride;
if (__copy_to_user(u64_to_user_ptr(query_item->data_ptr),
&topo, sizeof(topo)))
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 9a79d9d547c5..7de7b7b540cb 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -118,10 +118,9 @@ void intel_device_info_dump_runtime(const struct intel_runtime_info *info,
static int sseu_eu_idx(const struct sseu_dev_info *sseu, int slice,
int subslice)
{
- int subslice_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
- int slice_stride = sseu->max_subslices * subslice_stride;
+ int slice_stride = sseu->max_subslices * sseu->eu_stride;
- return slice * slice_stride + subslice * subslice_stride;
+ return slice * slice_stride + subslice * sseu->eu_stride;
}
static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
@@ -130,7 +129,7 @@ static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
int i, offset = sseu_eu_idx(sseu, slice, subslice);
u16 eu_mask = 0;
- for (i = 0; i < GEN_SSEU_STRIDE(sseu->max_eus_per_subslice); i++) {
+ for (i = 0; i < sseu->eu_stride; i++) {
eu_mask |= ((u16)sseu->eu_mask[offset + i]) <<
(i * BITS_PER_BYTE);
}
@@ -143,7 +142,7 @@ static void sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice,
{
int i, offset = sseu_eu_idx(sseu, slice, subslice);
- for (i = 0; i < GEN_SSEU_STRIDE(sseu->max_eus_per_subslice); i++) {
+ for (i = 0; i < sseu->eu_stride; i++) {
sseu->eu_mask[offset + i] =
(eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
}
--
2.21.0.5.gaeb582a983
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 5/9] drm/i915: Add function to set subslices
2019-07-24 17:12 [PATCH 0/9] Refactor to expand subslice mask (rev 2) Stuart Summers
` (3 preceding siblings ...)
2019-07-24 17:12 ` [PATCH 4/9] drm/i915: Add EU " Stuart Summers
@ 2019-07-24 17:12 ` Stuart Summers
2019-07-24 17:12 ` [PATCH 6/9] drm/i915: Add function to determine if a slice has a subslice Stuart Summers
` (6 subsequent siblings)
11 siblings, 0 replies; 23+ messages in thread
From: Stuart Summers @ 2019-07-24 17:12 UTC (permalink / raw)
To: intel-gfx
Add a new function to set a range of subslices for a
specified slice based on a given mask.
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 10 +++++
drivers/gpu/drm/i915/gt/intel_sseu.h | 3 ++
drivers/gpu/drm/i915/intel_device_info.c | 53 ++++++++++++++----------
3 files changed, 45 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 71abf0c9a46b..607c1447287c 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -30,6 +30,16 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
return total;
}
+void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
+ u32 ss_mask)
+{
+ int i, offset = slice * sseu->ss_stride;
+
+ for (i = 0; i < sseu->ss_stride; i++)
+ sseu->subslice_mask[offset + i] =
+ (ss_mask >> (BITS_PER_BYTE * i)) & 0xff;
+}
+
unsigned int
intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index fe22d5b18e67..2261d4e7d98b 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -75,6 +75,9 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu);
unsigned int
intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice);
+void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
+ u32 ss_mask);
+
u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
const struct intel_sseu *req_sseu);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 7de7b7b540cb..22b59fdb31fc 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -206,7 +206,10 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
int ss;
sseu->slice_mask |= BIT(s);
- sseu->subslice_mask[s] = (ss_en >> ss_idx) & ss_en_mask;
+
+ intel_sseu_set_subslices(sseu, s, (ss_en >> ss_idx) &
+ ss_en_mask);
+
for (ss = 0; ss < sseu->max_subslices; ss++) {
if (sseu->subslice_mask[s] & BIT(ss))
sseu_set_eus(sseu, s, ss, eu_en);
@@ -235,14 +238,6 @@ static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
GEN10_F2_S_ENA_SHIFT;
- subslice_mask = (1 << 4) - 1;
- subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
- GEN10_F2_SS_DIS_SHIFT);
-
- /*
- * Slice0 can have up to 3 subslices, but there are only 2 in
- * slice1/2.
- */
sseu->subslice_mask[0] = subslice_mask;
for (s = 1; s < sseu->max_slices; s++)
sseu->subslice_mask[s] = subslice_mask & 0x3;
@@ -270,14 +265,25 @@ static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
eu_en = ~I915_READ(GEN10_EU_DISABLE3);
sseu_set_eus(sseu, 5, 1, eu_en & eu_mask);
- /* Do a second pass where we mark the subslices disabled if all their
- * eus are off.
- */
+ subslice_mask = (1 << 4) - 1;
+ subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
+ GEN10_F2_SS_DIS_SHIFT);
+
for (s = 0; s < sseu->max_slices; s++) {
+ u32 subslice_mask_with_eus = subslice_mask;
+
for (ss = 0; ss < sseu->max_subslices; ss++) {
if (sseu_get_eus(sseu, s, ss) == 0)
- sseu->subslice_mask[s] &= ~BIT(ss);
+ subslice_mask_with_eus &= ~BIT(ss);
}
+
+ /*
+ * Slice0 can have up to 3 subslices, but there are only 2 in
+ * slice1/2.
+ */
+ intel_sseu_set_subslices(sseu, s, s == 0 ?
+ subslice_mask_with_eus :
+ subslice_mask_with_eus & 0x3);
}
sseu->eu_total = compute_eu_total(sseu);
@@ -303,6 +309,7 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
{
struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
u32 fuse;
+ u8 subslice_mask;
fuse = I915_READ(CHV_FUSE_GT);
@@ -316,7 +323,7 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
(((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >>
CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);
- sseu->subslice_mask[0] |= BIT(0);
+ subslice_mask |= BIT(0);
sseu_set_eus(sseu, 0, 0, ~disabled_mask);
}
@@ -327,10 +334,12 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
(((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >>
CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4);
- sseu->subslice_mask[0] |= BIT(1);
+ subslice_mask |= BIT(1);
sseu_set_eus(sseu, 0, 1, ~disabled_mask);
}
+ intel_sseu_set_subslices(sseu, 0, subslice_mask);
+
sseu->eu_total = compute_eu_total(sseu);
/*
@@ -383,7 +392,7 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
/* skip disabled slice */
continue;
- sseu->subslice_mask[s] = subslice_mask;
+ intel_sseu_set_subslices(sseu, s, subslice_mask);
eu_disable = I915_READ(GEN9_EU_DISABLE(s));
for (ss = 0; ss < sseu->max_subslices; ss++) {
@@ -490,7 +499,7 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
/* skip disabled slice */
continue;
- sseu->subslice_mask[s] = subslice_mask;
+ intel_sseu_set_subslices(sseu, s, subslice_mask);
for (ss = 0; ss < sseu->max_subslices; ss++) {
u8 eu_disabled_mask;
@@ -541,6 +550,7 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
u32 fuse1;
int s, ss;
+ u32 subslice_mask;
/*
* There isn't a register to tell us how many slices/subslices. We
@@ -552,16 +562,15 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
/* fall through */
case 1:
sseu->slice_mask = BIT(0);
- sseu->subslice_mask[0] = BIT(0);
+ subslice_mask = BIT(0);
break;
case 2:
sseu->slice_mask = BIT(0);
- sseu->subslice_mask[0] = BIT(0) | BIT(1);
+ subslice_mask = BIT(0) | BIT(1);
break;
case 3:
sseu->slice_mask = BIT(0) | BIT(1);
- sseu->subslice_mask[0] = BIT(0) | BIT(1);
- sseu->subslice_mask[1] = BIT(0) | BIT(1);
+ subslice_mask = BIT(0) | BIT(1);
break;
}
@@ -587,6 +596,8 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
sseu->eu_per_subslice);
for (s = 0; s < sseu->max_slices; s++) {
+ intel_sseu_set_subslices(sseu, s, subslice_mask);
+
for (ss = 0; ss < sseu->max_subslices; ss++) {
sseu_set_eus(sseu, s, ss,
(1UL << sseu->eu_per_subslice) - 1);
--
2.21.0.5.gaeb582a983
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 6/9] drm/i915: Add function to determine if a slice has a subslice
2019-07-24 17:12 [PATCH 0/9] Refactor to expand subslice mask (rev 2) Stuart Summers
` (4 preceding siblings ...)
2019-07-24 17:12 ` [PATCH 5/9] drm/i915: Add function to set subslices Stuart Summers
@ 2019-07-24 17:12 ` Stuart Summers
2019-07-24 17:12 ` [PATCH 7/9] drm/i915: Refactor instdone loops on new subslice functions Stuart Summers
` (5 subsequent siblings)
11 siblings, 0 replies; 23+ messages in thread
From: Stuart Summers @ 2019-07-24 17:12 UTC (permalink / raw)
To: intel-gfx
Add a new function to determine whether a particular slice
has a given subslice.
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/i915/gt/intel_sseu.h | 10 ++++++++++
drivers/gpu/drm/i915/intel_device_info.c | 9 ++++-----
2 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 2261d4e7d98b..0ecc1c35a7a1 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -66,6 +66,16 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
return value;
}
+static inline bool
+intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice,
+ int subslice)
+{
+ u8 mask = sseu->subslice_mask[slice * sseu->ss_stride +
+ subslice / BITS_PER_BYTE];
+
+ return mask & BIT(subslice % BITS_PER_BYTE);
+}
+
void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
u8 max_subslices, u8 max_eus_per_subslice);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 22b59fdb31fc..723b1fde5fc4 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -210,10 +210,9 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
intel_sseu_set_subslices(sseu, s, (ss_en >> ss_idx) &
ss_en_mask);
- for (ss = 0; ss < sseu->max_subslices; ss++) {
- if (sseu->subslice_mask[s] & BIT(ss))
+ for (ss = 0; ss < sseu->max_subslices; ss++)
+ if (intel_sseu_has_subslice(sseu, s, ss))
sseu_set_eus(sseu, s, ss, eu_en);
- }
}
}
sseu->eu_per_subslice = hweight8(eu_en);
@@ -399,7 +398,7 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
int eu_per_ss;
u8 eu_disabled_mask;
- if (!(sseu->subslice_mask[s] & BIT(ss)))
+ if (!intel_sseu_has_subslice(sseu, s, ss))
/* skip disabled subslice */
continue;
@@ -505,7 +504,7 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
u8 eu_disabled_mask;
u32 n_disabled;
- if (!(sseu->subslice_mask[s] & BIT(ss)))
+ if (!intel_sseu_has_subslice(sseu, s, ss))
/* skip disabled subslice */
continue;
--
2.21.0.5.gaeb582a983
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 7/9] drm/i915: Refactor instdone loops on new subslice functions
2019-07-24 17:12 [PATCH 0/9] Refactor to expand subslice mask (rev 2) Stuart Summers
` (5 preceding siblings ...)
2019-07-24 17:12 ` [PATCH 6/9] drm/i915: Add function to determine if a slice has a subslice Stuart Summers
@ 2019-07-24 17:12 ` Stuart Summers
2019-07-24 17:12 ` [PATCH 8/9] drm/i915: Add new function to copy subslices for a slice Stuart Summers
` (4 subsequent siblings)
11 siblings, 0 replies; 23+ messages in thread
From: Stuart Summers @ 2019-07-24 17:12 UTC (permalink / raw)
To: intel-gfx
Refactor instdone loops to use the new intel_sseu_has_subslice
function.
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 +-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 31 ++++++++++----------
drivers/gpu/drm/i915/gt/intel_hangcheck.c | 3 +-
drivers/gpu/drm/i915/i915_debugfs.c | 5 ++--
drivers/gpu/drm/i915/i915_gpu_error.c | 5 ++--
5 files changed, 25 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 65cbf1d9118d..c42bccccc18e 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1009,6 +1009,7 @@ void intel_engine_get_instdone(struct intel_engine_cs *engine,
struct intel_instdone *instdone)
{
struct drm_i915_private *i915 = engine->i915;
+ const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
struct intel_uncore *uncore = engine->uncore;
u32 mmio_base = engine->mmio_base;
int slice;
@@ -1026,7 +1027,7 @@ void intel_engine_get_instdone(struct intel_engine_cs *engine,
instdone->slice_common =
intel_uncore_read(uncore, GEN7_SC_INSTDONE);
- for_each_instdone_slice_subslice(i915, slice, subslice) {
+ for_each_instdone_slice_subslice(i915, sseu, slice, subslice) {
instdone->sampler[slice][subslice] =
read_subslice_reg(engine, slice, subslice,
GEN7_SAMPLER_INSTDONE);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 8be63019d707..6174b29045f6 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -540,20 +540,19 @@ intel_engine_is_virtual(const struct intel_engine_cs *engine)
return engine->flags & I915_ENGINE_IS_VIRTUAL;
}
-#define instdone_slice_mask(dev_priv__) \
- (IS_GEN(dev_priv__, 7) ? \
- 1 : RUNTIME_INFO(dev_priv__)->sseu.slice_mask)
-
-#define instdone_subslice_mask(dev_priv__) \
- (IS_GEN(dev_priv__, 7) ? \
- 1 : RUNTIME_INFO(dev_priv__)->sseu.subslice_mask[0])
-
-#define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \
- for ((slice__) = 0, (subslice__) = 0; \
- (slice__) < I915_MAX_SLICES; \
- (subslice__) = ((subslice__) + 1) < I915_MAX_SUBSLICES ? (subslice__) + 1 : 0, \
- (slice__) += ((subslice__) == 0)) \
- for_each_if((BIT(slice__) & instdone_slice_mask(dev_priv__)) && \
- (BIT(subslice__) & instdone_subslice_mask(dev_priv__)))
-
+#define instdone_has_slice(dev_priv___, sseu___, slice___) \
+ ((IS_GEN(dev_priv___, 7) ? 1 : ((sseu___)->slice_mask)) & \
+ BIT(slice___))
+
+#define instdone_has_subslice(dev_priv__, sseu__, slice__, subslice__) \
+ (IS_GEN(dev_priv__, 7) ? (1 & BIT(subslice__)) : \
+ intel_sseu_has_subslice(sseu__, 0, subslice__))
+
+#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
+ for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
+ (subslice_) = ((subslice_) + 1) % I915_MAX_SUBSLICES, \
+ (slice_) += ((subslice_) == 0)) \
+ for_each_if((instdone_has_slice(dev_priv_, sseu_, slice_)) && \
+ (instdone_has_subslice(dev_priv_, sseu_, slice_, \
+ subslice_)))
#endif /* __INTEL_ENGINE_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_hangcheck.c b/drivers/gpu/drm/i915/gt/intel_hangcheck.c
index 05d042cdefe2..40f62f780be5 100644
--- a/drivers/gpu/drm/i915/gt/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/intel_hangcheck.c
@@ -53,6 +53,7 @@ static bool instdone_unchanged(u32 current_instdone, u32 *old_instdone)
static bool subunits_stuck(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
+ const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
struct intel_instdone instdone;
struct intel_instdone *accu_instdone = &engine->hangcheck.instdone;
bool stuck;
@@ -71,7 +72,7 @@ static bool subunits_stuck(struct intel_engine_cs *engine)
stuck &= instdone_unchanged(instdone.slice_common,
&accu_instdone->slice_common);
- for_each_instdone_slice_subslice(dev_priv, slice, subslice) {
+ for_each_instdone_slice_subslice(dev_priv, sseu, slice, subslice) {
stuck &= instdone_unchanged(instdone.sampler[slice][subslice],
&accu_instdone->sampler[slice][subslice]);
stuck &= instdone_unchanged(instdone.row[slice][subslice],
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 011ed2fd391d..a61d31fc482f 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1048,6 +1048,7 @@ static void i915_instdone_info(struct drm_i915_private *dev_priv,
struct seq_file *m,
struct intel_instdone *instdone)
{
+ const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
int slice;
int subslice;
@@ -1063,11 +1064,11 @@ static void i915_instdone_info(struct drm_i915_private *dev_priv,
if (INTEL_GEN(dev_priv) <= 6)
return;
- for_each_instdone_slice_subslice(dev_priv, slice, subslice)
+ for_each_instdone_slice_subslice(dev_priv, sseu, slice, subslice)
seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
slice, subslice, instdone->sampler[slice][subslice]);
- for_each_instdone_slice_subslice(dev_priv, slice, subslice)
+ for_each_instdone_slice_subslice(dev_priv, sseu, slice, subslice)
seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n",
slice, subslice, instdone->row[slice][subslice]);
}
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 2193687eac72..843bca37577b 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -443,6 +443,7 @@ static void err_compression_marker(struct drm_i915_error_state_buf *m)
static void error_print_instdone(struct drm_i915_error_state_buf *m,
const struct drm_i915_error_engine *ee)
{
+ const struct sseu_dev_info *sseu = &RUNTIME_INFO(m->i915)->sseu;
int slice;
int subslice;
@@ -458,12 +459,12 @@ static void error_print_instdone(struct drm_i915_error_state_buf *m,
if (INTEL_GEN(m->i915) <= 6)
return;
- for_each_instdone_slice_subslice(m->i915, slice, subslice)
+ for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice)
err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
slice, subslice,
ee->instdone.sampler[slice][subslice]);
- for_each_instdone_slice_subslice(m->i915, slice, subslice)
+ for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice)
err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n",
slice, subslice,
ee->instdone.row[slice][subslice]);
--
2.21.0.5.gaeb582a983
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 8/9] drm/i915: Add new function to copy subslices for a slice
2019-07-24 17:12 [PATCH 0/9] Refactor to expand subslice mask (rev 2) Stuart Summers
` (6 preceding siblings ...)
2019-07-24 17:12 ` [PATCH 7/9] drm/i915: Refactor instdone loops on new subslice functions Stuart Summers
@ 2019-07-24 17:12 ` Stuart Summers
2019-07-24 17:12 ` [PATCH 9/9] drm/i915: Expand subslice mask Stuart Summers
` (3 subsequent siblings)
11 siblings, 0 replies; 23+ messages in thread
From: Stuart Summers @ 2019-07-24 17:12 UTC (permalink / raw)
To: intel-gfx
Add a new function to copy subslices for a specified slice
between intel_sseu structures for the purpose of determining
power-gate status.
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 21 +++++++++++++++------
1 file changed, 15 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index a61d31fc482f..7f842506b9ea 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3806,6 +3806,15 @@ i915_cache_sharing_set(void *data, u64 val)
return 0;
}
+static void
+intel_sseu_copy_subslices(const struct sseu_dev_info *sseu, int slice,
+ u8 *to_mask)
+{
+ int offset = slice * sseu->ss_stride;
+
+ memcpy(&to_mask[offset], &sseu->subslice_mask[offset], sseu->ss_stride);
+}
+
DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
i915_cache_sharing_get, i915_cache_sharing_set,
"%llu\n");
@@ -3879,7 +3888,7 @@ static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
continue;
sseu->slice_mask |= BIT(s);
- sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
+ intel_sseu_copy_subslices(&info->sseu, s, sseu->subslice_mask);
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
@@ -3930,7 +3939,8 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
sseu->slice_mask |= BIT(s);
if (IS_GEN9_BC(dev_priv))
- sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
+ intel_sseu_copy_subslices(&info->sseu, s,
+ sseu->subslice_mask);
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
@@ -3966,10 +3976,9 @@ static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
if (sseu->slice_mask) {
sseu->eu_per_subslice =
info->sseu.eu_per_subslice;
- for (s = 0; s < fls(sseu->slice_mask); s++) {
- sseu->subslice_mask[s] =
- info->sseu.subslice_mask[s];
- }
+ for (s = 0; s < fls(sseu->slice_mask); s++)
+ intel_sseu_copy_subslices(&info->sseu, s,
+ sseu->subslice_mask);
sseu->eu_total = sseu->eu_per_subslice *
intel_sseu_subslice_total(sseu);
--
2.21.0.5.gaeb582a983
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 9/9] drm/i915: Expand subslice mask
2019-07-24 17:12 [PATCH 0/9] Refactor to expand subslice mask (rev 2) Stuart Summers
` (7 preceding siblings ...)
2019-07-24 17:12 ` [PATCH 8/9] drm/i915: Add new function to copy subslices for a slice Stuart Summers
@ 2019-07-24 17:12 ` Stuart Summers
2019-07-24 17:28 ` ✗ Fi.CI.CHECKPATCH: warning for Refactor to expand subslice mask (rev 2) Patchwork
` (2 subsequent siblings)
11 siblings, 0 replies; 23+ messages in thread
From: Stuart Summers @ 2019-07-24 17:12 UTC (permalink / raw)
To: intel-gfx
Currently, the subslice_mask runtime parameter is stored as an
array of subslices per slice. Expand the subslice mask array to
better match what is presented to userspace through the
I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is
then calculated:
slice * subslice stride + subslice index / 8
v2: Fix 32-bit build
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 27 ++++++++++++++++++++-
drivers/gpu/drm/i915/gt/intel_sseu.h | 5 +++-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +--
drivers/gpu/drm/i915/i915_debugfs.c | 5 +++-
drivers/gpu/drm/i915/intel_device_info.c | 8 +++---
5 files changed, 39 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 607c1447287c..e426f34b4dd6 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -30,6 +30,31 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
return total;
}
+u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice)
+{
+ int i, offset = slice * sseu->ss_stride;
+ u32 mask = 0;
+
+ if (slice >= sseu->max_slices) {
+ DRM_ERROR("%s: invalid slice %d, max: %d\n",
+ __func__, slice, sseu->max_slices);
+ return 0;
+ }
+
+ if (sseu->ss_stride > sizeof(mask)) {
+ DRM_ERROR("%s: invalid subslice stride %d, max: %u\n",
+ __func__, sseu->ss_stride,
+ (unsigned int)sizeof(mask));
+ return 0;
+ }
+
+ for (i = 0; i < sseu->ss_stride; i++)
+ mask |= (u32)sseu->subslice_mask[offset + i] <<
+ i * BITS_PER_BYTE;
+
+ return mask;
+}
+
void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
u32 ss_mask)
{
@@ -43,7 +68,7 @@ void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
unsigned int
intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
{
- return hweight8(sseu->subslice_mask[slice]);
+ return hweight32(intel_sseu_get_subslices(sseu, slice));
}
u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 0ecc1c35a7a1..2291764b7db5 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -15,10 +15,11 @@ struct drm_i915_private;
#define GEN_MAX_SLICES (6) /* CNL upper bound */
#define GEN_MAX_SUBSLICES (8) /* ICL upper bound */
#define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
+#define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES)
struct sseu_dev_info {
u8 slice_mask;
- u8 subslice_mask[GEN_MAX_SLICES];
+ u8 subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE];
u16 eu_total;
u8 eu_per_subslice;
u8 min_eu_in_pool;
@@ -85,6 +86,8 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu);
unsigned int
intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice);
+u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice);
+
void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
u32 ss_mask);
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 704ace01e7f5..7ec60435d871 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -794,8 +794,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
}
slice = fls(sseu->slice_mask) - 1;
- GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
- subslice = fls(l3_en & sseu->subslice_mask[slice]);
+ subslice = fls(l3_en & intel_sseu_get_subslices(sseu, slice));
if (!subslice) {
DRM_WARN("No common index found between subslice mask %x and L3 bank mask %x!\n",
sseu->subslice_mask[slice], l3_en);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 7f842506b9ea..96a25a770ade 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3944,13 +3944,16 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
+ u8 ss_idx = s * info->sseu.ss_stride +
+ ss / BITS_PER_BYTE;
if (IS_GEN9_LP(dev_priv)) {
if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
/* skip disabled subslice */
continue;
- sseu->subslice_mask[s] |= BIT(ss);
+ sseu->subslice_mask[ss_idx] |=
+ BIT(ss % BITS_PER_BYTE);
}
eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 723b1fde5fc4..04dde4f204c3 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -93,9 +93,9 @@ static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
hweight8(sseu->slice_mask), sseu->slice_mask);
drm_printf(p, "subslice total: %u\n", intel_sseu_subslice_total(sseu));
for (s = 0; s < sseu->max_slices; s++) {
- drm_printf(p, "slice%d: %u subslices, mask=%04x\n",
+ drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
s, intel_sseu_subslices_per_slice(sseu, s),
- sseu->subslice_mask[s]);
+ intel_sseu_get_subslices(sseu, s));
}
drm_printf(p, "EU total: %u\n", sseu->eu_total);
drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice);
@@ -159,9 +159,9 @@ void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
}
for (s = 0; s < sseu->max_slices; s++) {
- drm_printf(p, "slice%d: %u subslice(s) (0x%hhx):\n",
+ drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n",
s, intel_sseu_subslices_per_slice(sseu, s),
- sseu->subslice_mask[s]);
+ intel_sseu_get_subslices(sseu, s));
for (ss = 0; ss < sseu->max_subslices; ss++) {
u16 enabled_eus = sseu_get_eus(sseu, s, ss);
--
2.21.0.5.gaeb582a983
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 23+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for Refactor to expand subslice mask (rev 2)
2019-07-24 17:12 [PATCH 0/9] Refactor to expand subslice mask (rev 2) Stuart Summers
` (8 preceding siblings ...)
2019-07-24 17:12 ` [PATCH 9/9] drm/i915: Expand subslice mask Stuart Summers
@ 2019-07-24 17:28 ` Patchwork
2019-07-24 19:39 ` ✓ Fi.CI.BAT: success " Patchwork
2019-07-24 21:01 ` ✗ Fi.CI.IGT: failure " Patchwork
11 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2019-07-24 17:28 UTC (permalink / raw)
To: Stuart Summers; +Cc: intel-gfx
== Series Details ==
Series: Refactor to expand subslice mask (rev 2)
URL : https://patchwork.freedesktop.org/series/64188/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d83520f343cd drm/i915: Use variable for debugfs device status
c7ec1447ee8f drm/i915: Add function to set SSEU info per platform
f98badbf8128 drm/i915: Add subslice stride runtime parameter
c4939aa73937 drm/i915: Add EU stride runtime parameter
4bbfa8ad97d1 drm/i915: Add function to set subslices
e91ccd3ed614 drm/i915: Add function to determine if a slice has a subslice
90de02581fa8 drm/i915: Refactor instdone loops on new subslice functions
-:60: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'subslice__' - possible side-effects?
#60: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:547:
+#define instdone_has_subslice(dev_priv__, sseu__, slice__, subslice__) \
+ (IS_GEN(dev_priv__, 7) ? (1 & BIT(subslice__)) : \
+ intel_sseu_has_subslice(sseu__, 0, subslice__))
-:64: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv_' - possible side-effects?
#64: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:551:
+#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
+ for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
+ (subslice_) = ((subslice_) + 1) % I915_MAX_SUBSLICES, \
+ (slice_) += ((subslice_) == 0)) \
+ for_each_if((instdone_has_slice(dev_priv_, sseu_, slice_)) && \
+ (instdone_has_subslice(dev_priv_, sseu_, slice_, \
+ subslice_)))
-:64: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'sseu_' - possible side-effects?
#64: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:551:
+#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
+ for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
+ (subslice_) = ((subslice_) + 1) % I915_MAX_SUBSLICES, \
+ (slice_) += ((subslice_) == 0)) \
+ for_each_if((instdone_has_slice(dev_priv_, sseu_, slice_)) && \
+ (instdone_has_subslice(dev_priv_, sseu_, slice_, \
+ subslice_)))
-:64: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'slice_' - possible side-effects?
#64: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:551:
+#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
+ for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
+ (subslice_) = ((subslice_) + 1) % I915_MAX_SUBSLICES, \
+ (slice_) += ((subslice_) == 0)) \
+ for_each_if((instdone_has_slice(dev_priv_, sseu_, slice_)) && \
+ (instdone_has_subslice(dev_priv_, sseu_, slice_, \
+ subslice_)))
-:64: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'subslice_' - possible side-effects?
#64: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:551:
+#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
+ for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
+ (subslice_) = ((subslice_) + 1) % I915_MAX_SUBSLICES, \
+ (slice_) += ((subslice_) == 0)) \
+ for_each_if((instdone_has_slice(dev_priv_, sseu_, slice_)) && \
+ (instdone_has_subslice(dev_priv_, sseu_, slice_, \
+ subslice_)))
total: 0 errors, 0 warnings, 5 checks, 106 lines checked
22e6e3567db7 drm/i915: Add new function to copy subslices for a slice
6c805dfa2b2a drm/i915: Expand subslice mask
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 23+ messages in thread
* ✓ Fi.CI.BAT: success for Refactor to expand subslice mask (rev 2)
2019-07-24 17:12 [PATCH 0/9] Refactor to expand subslice mask (rev 2) Stuart Summers
` (9 preceding siblings ...)
2019-07-24 17:28 ` ✗ Fi.CI.CHECKPATCH: warning for Refactor to expand subslice mask (rev 2) Patchwork
@ 2019-07-24 19:39 ` Patchwork
2019-07-24 21:01 ` ✗ Fi.CI.IGT: failure " Patchwork
11 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2019-07-24 19:39 UTC (permalink / raw)
To: Stuart Summers; +Cc: intel-gfx
== Series Details ==
Series: Refactor to expand subslice mask (rev 2)
URL : https://patchwork.freedesktop.org/series/64188/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6545 -> Patchwork_13739
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/
Known issues
------------
Here are the changes found in Patchwork_13739 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_module_load@reload-with-fault-injection:
- fi-snb-2600: [PASS][1] -> [INCOMPLETE][2] ([fdo#105411])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-snb-2600/igt@i915_module_load@reload-with-fault-injection.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/fi-snb-2600/igt@i915_module_load@reload-with-fault-injection.html
* igt@vgem_basic@debugfs:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-icl-u3/igt@vgem_basic@debugfs.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/fi-icl-u3/igt@vgem_basic@debugfs.html
#### Possible fixes ####
* igt@gem_ctx_create@basic-files:
- fi-icl-u2: [INCOMPLETE][5] ([fdo#107713] / [fdo#109100]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-icl-u2/igt@gem_ctx_create@basic-files.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/fi-icl-u2/igt@gem_ctx_create@basic-files.html
* igt@i915_selftest@live_hangcheck:
- fi-kbl-guc: [INCOMPLETE][7] ([fdo#108744]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-kbl-guc/igt@i915_selftest@live_hangcheck.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/fi-kbl-guc/igt@i915_selftest@live_hangcheck.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u: [WARN][9] ([fdo#109380]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-kbl-7567u/igt@kms_chamelium@common-hpd-after-suspend.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/fi-kbl-7567u/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u3: [FAIL][11] ([fdo#103167]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-icl-u3/igt@kms_frontbuffer_tracking@basic.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/fi-icl-u3/igt@kms_frontbuffer_tracking@basic.html
- {fi-icl-u4}: [FAIL][13] ([fdo#103167]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-icl-u4/igt@kms_frontbuffer_tracking@basic.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/fi-icl-u4/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_pipe_crc_basic@read-crc-pipe-c:
- fi-kbl-7567u: [SKIP][15] ([fdo#109271]) -> [PASS][16] +23 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/fi-kbl-7567u/igt@kms_pipe_crc_basic@read-crc-pipe-c.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/fi-kbl-7567u/igt@kms_pipe_crc_basic@read-crc-pipe-c.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109380]: https://bugs.freedesktop.org/show_bug.cgi?id=109380
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111046 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111046
[fdo#111049]: https://bugs.freedesktop.org/show_bug.cgi?id=111049
Participating hosts (52 -> 44)
------------------------------
Additional (1): fi-skl-gvtdvm
Missing (9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-icl-guc fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6545 -> Patchwork_13739
CI-20190529: 20190529
CI_DRM_6545: a6efe73f1e086c7935d56b08342f9e1c5565fcf3 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5109: e5fd509e16ec649436be31f38eaa5b85cb7f72f1 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13739: 6c805dfa2b2aa200593b17947e683a2781992c7a @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
6c805dfa2b2a drm/i915: Expand subslice mask
22e6e3567db7 drm/i915: Add new function to copy subslices for a slice
90de02581fa8 drm/i915: Refactor instdone loops on new subslice functions
e91ccd3ed614 drm/i915: Add function to determine if a slice has a subslice
4bbfa8ad97d1 drm/i915: Add function to set subslices
c4939aa73937 drm/i915: Add EU stride runtime parameter
f98badbf8128 drm/i915: Add subslice stride runtime parameter
c7ec1447ee8f drm/i915: Add function to set SSEU info per platform
d83520f343cd drm/i915: Use variable for debugfs device status
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 23+ messages in thread
* ✗ Fi.CI.IGT: failure for Refactor to expand subslice mask (rev 2)
2019-07-24 17:12 [PATCH 0/9] Refactor to expand subslice mask (rev 2) Stuart Summers
` (10 preceding siblings ...)
2019-07-24 19:39 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-07-24 21:01 ` Patchwork
2019-07-24 21:08 ` Summers, Stuart
11 siblings, 1 reply; 23+ messages in thread
From: Patchwork @ 2019-07-24 21:01 UTC (permalink / raw)
To: Stuart Summers; +Cc: intel-gfx
== Series Details ==
Series: Refactor to expand subslice mask (rev 2)
URL : https://patchwork.freedesktop.org/series/64188/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6545_full -> Patchwork_13739_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_13739_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_13739_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_13739_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_query@query-topology-matches-eu-total:
- shard-hsw: [PASS][1] -> [FAIL][2] +3 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-hsw7/igt@i915_query@query-topology-matches-eu-total.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-hsw1/igt@i915_query@query-topology-matches-eu-total.html
Known issues
------------
Here are the changes found in Patchwork_13739_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@rcs0-s3:
- shard-apl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108566])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-apl8/igt@gem_ctx_isolation@rcs0-s3.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-apl3/igt@gem_ctx_isolation@rcs0-s3.html
* igt@gem_tiled_swapping@non-threaded:
- shard-apl: [PASS][5] -> [DMESG-WARN][6] ([fdo#108686])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-apl5/igt@gem_tiled_swapping@non-threaded.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-apl7/igt@gem_tiled_swapping@non-threaded.html
* igt@i915_pm_rc6_residency@rc6-accuracy:
- shard-kbl: [PASS][7] -> [SKIP][8] ([fdo#109271])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-kbl1/igt@i915_pm_rc6_residency@rc6-accuracy.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-kbl1/igt@i915_pm_rc6_residency@rc6-accuracy.html
* igt@i915_query@query-topology-coherent-slice-mask:
- shard-hsw: [PASS][9] -> [SKIP][10] ([fdo#109271])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-hsw4/igt@i915_query@query-topology-coherent-slice-mask.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-hsw5/igt@i915_query@query-topology-coherent-slice-mask.html
* igt@kms_cursor_legacy@cursor-vs-flip-toggle:
- shard-hsw: [PASS][11] -> [FAIL][12] ([fdo#103355])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-hsw1/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-hsw6/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: [PASS][13] -> [FAIL][14] ([fdo#105363])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-skl10/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-skl8/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([fdo#108566]) +2 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_flip_tiling@flip-to-x-tiled:
- shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108134])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-skl10/igt@kms_flip_tiling@flip-to-x-tiled.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-skl3/igt@kms_flip_tiling@flip-to-x-tiled.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render:
- shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103167]) +7 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-skl: [PASS][21] -> [INCOMPLETE][22] ([fdo#104108])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-skl6/igt@kms_frontbuffer_tracking@fbc-suspend.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-skl3/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-kbl: [PASS][23] -> [INCOMPLETE][24] ([fdo#103665])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-kbl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-kbl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_psr2_su@page_flip:
- shard-iclb: [PASS][25] -> [SKIP][26] ([fdo#109642] / [fdo#111068])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb2/igt@kms_psr2_su@page_flip.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-iclb4/igt@kms_psr2_su@page_flip.html
* igt@perf_pmu@init-busy-vcs2:
- shard-iclb: [PASS][27] -> [INCOMPLETE][28] ([fdo#107713])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb2/igt@perf_pmu@init-busy-vcs2.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-iclb4/igt@perf_pmu@init-busy-vcs2.html
#### Possible fixes ####
* igt@gem_exec_balancer@smoke:
- shard-iclb: [SKIP][29] ([fdo#110854]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb6/igt@gem_exec_balancer@smoke.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-iclb4/igt@gem_exec_balancer@smoke.html
* igt@i915_selftest@live_hangcheck:
- shard-iclb: [INCOMPLETE][31] ([fdo#107713] / [fdo#108569]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb6/igt@i915_selftest@live_hangcheck.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-iclb6/igt@i915_selftest@live_hangcheck.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [FAIL][33] ([fdo#105363]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-skl9/igt@kms_flip@flip-vs-expired-vblank.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-skl4/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-apl: [DMESG-WARN][35] ([fdo#108566]) -> [PASS][36] +4 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-apl4/igt@kms_flip@flip-vs-suspend-interruptible.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
- shard-iclb: [FAIL][37] ([fdo#103167]) -> [PASS][38] +3 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [FAIL][39] ([fdo#108145]) -> [PASS][40] +1 similar issue
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_psr@cursor_plane_onoff:
- shard-iclb: [INCOMPLETE][41] ([fdo#107713]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb1/igt@kms_psr@cursor_plane_onoff.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-iclb1/igt@kms_psr@cursor_plane_onoff.html
* igt@kms_psr@psr2_primary_mmap_gtt:
- shard-iclb: [SKIP][43] ([fdo#109441]) -> [PASS][44] +2 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb4/igt@kms_psr@psr2_primary_mmap_gtt.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html
#### Warnings ####
* igt@gem_tiled_swapping@non-threaded:
- shard-skl: [FAIL][45] ([fdo#108686]) -> [SKIP][46] ([fdo#109271])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-skl8/igt@gem_tiled_swapping@non-threaded.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-skl5/igt@gem_tiled_swapping@non-threaded.html
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108134]: https://bugs.freedesktop.org/show_bug.cgi?id=108134
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6545 -> Patchwork_13739
CI-20190529: 20190529
CI_DRM_6545: a6efe73f1e086c7935d56b08342f9e1c5565fcf3 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5109: e5fd509e16ec649436be31f38eaa5b85cb7f72f1 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13739: 6c805dfa2b2aa200593b17947e683a2781992c7a @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: ✗ Fi.CI.IGT: failure for Refactor to expand subslice mask (rev 2)
2019-07-24 21:01 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2019-07-24 21:08 ` Summers, Stuart
0 siblings, 0 replies; 23+ messages in thread
From: Summers, Stuart @ 2019-07-24 21:08 UTC (permalink / raw)
To: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 12400 bytes --]
On Wed, 2019-07-24 at 21:01 +0000, Patchwork wrote:
> == Series Details ==
>
> Series: Refactor to expand subslice mask (rev 2)
> URL : https://patchwork.freedesktop.org/series/64188/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_6545_full -> Patchwork_13739_full
> ====================================================
>
> Summary
> -------
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_13739_full absolutely
> need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the
> changes
> introduced in Patchwork_13739_full, please notify your bug team to
> allow them
> to document this new failure mode, which will reduce false
> positives in CI.
>
>
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in
> Patchwork_13739_full:
>
> ### IGT changes ###
>
> #### Possible regressions ####
>
> * igt@i915_query@query-topology-matches-eu-total:
> - shard-hsw: [PASS][1] -> [FAIL][2] +3 similar issues
> [1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-hsw7/igt@i915_query@query-topology-matches-eu-total.html
> [2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-hsw1/igt@i915_query@query-topology-matches-eu-total.html
Looks like this series is causing a regression on HSW. I'll fix this
issue before posting the next revision. For now, please hold off on
review.
Thanks,
Stuart
>
>
> Known issues
> ------------
>
> Here are the changes found in Patchwork_13739_full that come from
> known issues:
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@gem_ctx_isolation@rcs0-s3:
> - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108566])
> [3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-apl8/igt@gem_ctx_isolation@rcs0-s3.html
> [4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-apl3/igt@gem_ctx_isolation@rcs0-s3.html
>
> * igt@gem_tiled_swapping@non-threaded:
> - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([fdo#108686])
> [5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-apl5/igt@gem_tiled_swapping@non-threaded.html
> [6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-apl7/igt@gem_tiled_swapping@non-threaded.html
>
> * igt@i915_pm_rc6_residency@rc6-accuracy:
> - shard-kbl: [PASS][7] -> [SKIP][8] ([fdo#109271])
> [7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-kbl1/igt@i915_pm_rc6_residency@rc6-accuracy.html
> [8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-kbl1/igt@i915_pm_rc6_residency@rc6-accuracy.html
>
> * igt@i915_query@query-topology-coherent-slice-mask:
> - shard-hsw: [PASS][9] -> [SKIP][10] ([fdo#109271])
> [9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-hsw4/igt@i915_query@query-topology-coherent-slice-mask.html
> [10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-hsw5/igt@i915_query@query-topology-coherent-slice-mask.html
>
> * igt@kms_cursor_legacy@cursor-vs-flip-toggle:
> - shard-hsw: [PASS][11] -> [FAIL][12] ([fdo#103355])
> [11]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-hsw1/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
> [12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-hsw6/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
>
> * igt@kms_flip@flip-vs-expired-vblank-interruptible:
> - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#105363])
> [13]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-skl10/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
> [14]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-skl8/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
>
> * igt@kms_flip@flip-vs-suspend-interruptible:
> - shard-kbl: [PASS][15] -> [DMESG-WARN][16]
> ([fdo#108566]) +2 similar issues
> [15]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible.html
> [16]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible.html
>
> * igt@kms_flip_tiling@flip-to-x-tiled:
> - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108134])
> [17]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-skl10/igt@kms_flip_tiling@flip-to-x-tiled.html
> [18]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-skl3/igt@kms_flip_tiling@flip-to-x-tiled.html
>
> * igt@kms
> _frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render:
> - shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103167]) +7
> similar issues
> [19]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html
> [20]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html
>
> * igt@kms_frontbuffer_tracking@fbc-suspend:
> - shard-skl: [PASS][21] -> [INCOMPLETE][22]
> ([fdo#104108])
> [21]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-skl6/igt@kms_frontbuffer_tracking@fbc-suspend.html
> [22]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-skl3/igt@kms_frontbuffer_tracking@fbc-suspend.html
>
> * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
> - shard-kbl: [PASS][23] -> [INCOMPLETE][24]
> ([fdo#103665])
> [23]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-kbl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
> [24]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-kbl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
>
> * igt@kms_psr2_su@page_flip:
> - shard-iclb: [PASS][25] -> [SKIP][26] ([fdo#109642] /
> [fdo#111068])
> [25]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb2/igt@kms_psr2_su@page_flip.html
> [26]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-iclb4/igt@kms_psr2_su@page_flip.html
>
> * igt@perf_pmu@init-busy-vcs2:
> - shard-iclb: [PASS][27] -> [INCOMPLETE][28]
> ([fdo#107713])
> [27]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb2/igt@perf_pmu@init-busy-vcs2.html
> [28]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-iclb4/igt@perf_pmu@init-busy-vcs2.html
>
>
> #### Possible fixes ####
>
> * igt@gem_exec_balancer@smoke:
> - shard-iclb: [SKIP][29] ([fdo#110854]) -> [PASS][30]
> [29]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb6/igt@gem_exec_balancer@smoke.html
> [30]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-iclb4/igt@gem_exec_balancer@smoke.html
>
> * igt@i915_selftest@live_hangcheck:
> - shard-iclb: [INCOMPLETE][31] ([fdo#107713] /
> [fdo#108569]) -> [PASS][32]
> [31]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb6/igt@i915_selftest@live_hangcheck.html
> [32]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-iclb6/igt@i915_selftest@live_hangcheck.html
>
> * igt@kms_flip@flip-vs-expired-vblank:
> - shard-skl: [FAIL][33] ([fdo#105363]) -> [PASS][34]
> [33]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-skl9/igt@kms_flip@flip-vs-expired-vblank.html
> [34]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-skl4/igt@kms_flip@flip-vs-expired-vblank.html
>
> * igt@kms_flip@flip-vs-suspend-interruptible:
> - shard-apl: [DMESG-WARN][35] ([fdo#108566]) ->
> [PASS][36] +4 similar issues
> [35]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-apl4/igt@kms_flip@flip-vs-suspend-interruptible.html
> [36]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible.html
>
> * igt@kms
> _frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
> - shard-iclb: [FAIL][37] ([fdo#103167]) -> [PASS][38] +3
> similar issues
> [37]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
> [38]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
>
> * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
> - shard-skl: [FAIL][39] ([fdo#108145]) -> [PASS][40] +1
> similar issue
> [39]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
> [40]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
>
> * igt@kms_psr@cursor_plane_onoff:
> - shard-iclb: [INCOMPLETE][41] ([fdo#107713]) ->
> [PASS][42]
> [41]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb1/igt@kms_psr@cursor_plane_onoff.html
> [42]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-iclb1/igt@kms_psr@cursor_plane_onoff.html
>
> * igt@kms_psr@psr2_primary_mmap_gtt:
> - shard-iclb: [SKIP][43] ([fdo#109441]) -> [PASS][44] +2
> similar issues
> [43]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb4/igt@kms_psr@psr2_primary_mmap_gtt.html
> [44]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html
>
>
> #### Warnings ####
>
> * igt@gem_tiled_swapping@non-threaded:
> - shard-skl: [FAIL][45] ([fdo#108686]) -> [SKIP][46]
> ([fdo#109271])
> [45]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-skl8/igt@gem_tiled_swapping@non-threaded.html
> [46]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-skl5/igt@gem_tiled_swapping@non-threaded.html
>
>
> [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
> [fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355
> [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
> [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
> [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
> [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
> [fdo#108134]: https://bugs.freedesktop.org/show_bug.cgi?id=108134
> [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
> [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
> [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
> [fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
> [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
> [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
> [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
> [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
> [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
>
>
> Participating hosts (9 -> 9)
> ------------------------------
>
> No changes in participating hosts
>
>
> Build changes
> -------------
>
> * CI: CI-20190529 -> None
> * Linux: CI_DRM_6545 -> Patchwork_13739
>
> CI-20190529: 20190529
> CI_DRM_6545: a6efe73f1e086c7935d56b08342f9e1c5565fcf3 @
> git://anongit.freedesktop.org/gfx-ci/linux
> IGT_5109: e5fd509e16ec649436be31f38eaa5b85cb7f72f1 @
> git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
> Patchwork_13739: 6c805dfa2b2aa200593b17947e683a2781992c7a @
> git://anongit.freedesktop.org/gfx-ci/linux
> piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
> git://anongit.freedesktop.org/piglit
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/
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