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* [PATCH] drm/amd/powerplay: minor fixes around SW SMU power and fan setting
@ 2019-07-25  2:39 Evan Quan
       [not found] ` <20190725023930.22521-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
  0 siblings, 1 reply; 6+ messages in thread
From: Evan Quan @ 2019-07-25  2:39 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Evan Quan

Add checking for possible invalid input and null pointer. And
drop redundant code.

Change-Id: I6ebd6acd944e821fb19af77ed1eaa8c4b1d407ce
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c    | 22 ++++++++++-----------
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 24 +++++++++++------------
 2 files changed, 21 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index bdf537d3f459..9aa00d67e61d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1667,20 +1667,16 @@ static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
 	     (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 		return -EINVAL;
 
-	if (is_support_sw_smu(adev)) {
-		err = kstrtoint(buf, 10, &value);
-		if (err)
-			return err;
+	err = kstrtoint(buf, 10, &value);
+	if (err)
+		return err;
 
+	if (is_support_sw_smu(adev)) {
 		smu_set_fan_control_mode(&adev->smu, value);
 	} else {
 		if (!adev->powerplay.pp_funcs->set_fan_control_mode)
 			return -EINVAL;
 
-		err = kstrtoint(buf, 10, &value);
-		if (err)
-			return err;
-
 		amdgpu_dpm_set_fan_control_mode(adev, value);
 	}
 
@@ -2100,16 +2096,18 @@ static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
 		return err;
 
 	value = value / 1000000; /* convert to Watt */
+
 	if (is_support_sw_smu(adev)) {
-		adev->smu.funcs->set_power_limit(&adev->smu, value);
+		err = smu_set_power_limit(&adev->smu, value);
 	} else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit) {
 		err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
-		if (err)
-			return err;
 	} else {
-		return -EINVAL;
+		err = -EINVAL;
 	}
 
+	if (err)
+		return err;
+
 	return count;
 }
 
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index d1486c3e1357..8ac9acabebf8 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1092,6 +1092,8 @@ static int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
 		max_power_limit *= (100 + smu->smu_table.TDPODLimit);
 		max_power_limit /= 100;
 	}
+	if (n > max_power_limit)
+		return -EINVAL;
 
 	if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
 		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n);
@@ -1407,17 +1409,17 @@ smu_v11_0_get_fan_control_mode(struct smu_context *smu)
 }
 
 static int
-smu_v11_0_smc_fan_control(struct smu_context *smu, bool start)
+smu_v11_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
 {
 	int ret = 0;
 
 	if (smu_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
 		return 0;
 
-	ret = smu_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, start);
+	ret = smu_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
 	if (ret)
 		pr_err("[%s]%s smc FAN CONTROL feature failed!",
-		       __func__, (start ? "Start" : "Stop"));
+		       __func__, (auto_fan_control ? "Start" : "Stop"));
 
 	return ret;
 }
@@ -1441,16 +1443,15 @@ static int
 smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
 {
 	struct amdgpu_device *adev = smu->adev;
-	uint32_t duty100;
-	uint32_t duty;
+	uint32_t duty100, duty;
 	uint64_t tmp64;
-	bool stop = 0;
 
 	if (speed > 100)
 		speed = 100;
 
-	if (smu_v11_0_smc_fan_control(smu, stop))
+	if (smu_v11_0_auto_fan_control(smu, 0))
 		return -EINVAL;
+
 	duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
 				CG_FDO_CTRL1, FMAX_DUTY100);
 	if (!duty100)
@@ -1472,18 +1473,16 @@ smu_v11_0_set_fan_control_mode(struct smu_context *smu,
 			       uint32_t mode)
 {
 	int ret = 0;
-	bool start = 1;
-	bool stop  = 0;
 
 	switch (mode) {
 	case AMD_FAN_CTRL_NONE:
 		ret = smu_v11_0_set_fan_speed_percent(smu, 100);
 		break;
 	case AMD_FAN_CTRL_MANUAL:
-		ret = smu_v11_0_smc_fan_control(smu, stop);
+		ret = smu_v11_0_auto_fan_control(smu, 0);
 		break;
 	case AMD_FAN_CTRL_AUTO:
-		ret = smu_v11_0_smc_fan_control(smu, start);
+		ret = smu_v11_0_auto_fan_control(smu, 1);
 		break;
 	default:
 		break;
@@ -1503,13 +1502,12 @@ static int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
 	struct amdgpu_device *adev = smu->adev;
 	int ret;
 	uint32_t tach_period, crystal_clock_freq;
-	bool stop = 0;
 
 	if (!speed)
 		return -EINVAL;
 
 	mutex_lock(&(smu->mutex));
-	ret = smu_v11_0_smc_fan_control(smu, stop);
+	ret = smu_v11_0_auto_fan_control(smu, 0);
 	if (ret)
 		goto set_fan_speed_rpm_failed;
 
-- 
2.22.0

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 6+ messages in thread

* [PATCH 2/2] drm/amd/powerplay: enable SW SMU reset functionality
       [not found] ` <20190725023930.22521-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
@ 2019-07-25  2:39   ` Evan Quan
       [not found]     ` <20190725023930.22521-2-evan.quan-5C7GfCeVMHo@public.gmane.org>
  2019-07-25 12:53   ` [PATCH] drm/amd/powerplay: minor fixes around SW SMU power and fan setting Deucher, Alexander
  1 sibling, 1 reply; 6+ messages in thread
From: Evan Quan @ 2019-07-25  2:39 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Evan Quan

Move SMU irq handler register to sw_init as that's totally
software related. Otherwise, it will prevent SMU reset working.

Change-Id: Ibd3e48ae9a90ab57f42b3f2ddbb736deeebc8715
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 6935a00cd389..a5079b93caa3 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -741,6 +741,12 @@ static int smu_sw_init(void *handle)
 		return ret;
 	}
 
+	ret = smu_register_irq_handler(smu);
+	if (ret) {
+		pr_err("Failed to register smc irq handler!\n");
+		return ret;
+	}
+
 	return 0;
 }
 
@@ -750,6 +756,9 @@ static int smu_sw_fini(void *handle)
 	struct smu_context *smu = &adev->smu;
 	int ret;
 
+	kfree(smu->irq_source);
+	smu->irq_source = NULL;
+
 	ret = smu_smc_table_sw_fini(smu);
 	if (ret) {
 		pr_err("Failed to sw fini smc table!\n");
@@ -1061,10 +1070,6 @@ static int smu_hw_init(void *handle)
 	if (ret)
 		goto failed;
 
-	ret = smu_register_irq_handler(smu);
-	if (ret)
-		goto failed;
-
 	if (!smu->pm_enabled)
 		adev->pm.dpm_enabled = false;
 	else
@@ -1094,9 +1099,6 @@ static int smu_hw_fini(void *handle)
 	kfree(table_context->overdrive_table);
 	table_context->overdrive_table = NULL;
 
-	kfree(smu->irq_source);
-	smu->irq_source = NULL;
-
 	ret = smu_fini_fb_allocations(smu);
 	if (ret)
 		return ret;
-- 
2.22.0

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 6+ messages in thread

* Re: [PATCH] drm/amd/powerplay: minor fixes around SW SMU power and fan setting
       [not found] ` <20190725023930.22521-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
  2019-07-25  2:39   ` [PATCH 2/2] drm/amd/powerplay: enable SW SMU reset functionality Evan Quan
@ 2019-07-25 12:53   ` Deucher, Alexander
  1 sibling, 0 replies; 6+ messages in thread
From: Deucher, Alexander @ 2019-07-25 12:53 UTC (permalink / raw)
  To: Quan, Evan, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW


[-- Attachment #1.1: Type: text/plain, Size: 6471 bytes --]

Reviewed-by: Alex Deucher <alexander.deucher-5C7GfCeVMHo@public.gmane.org>
________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Evan Quan <evan.quan-5C7GfCeVMHo@public.gmane.org>
Sent: Wednesday, July 24, 2019 10:39 PM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
Cc: Quan, Evan <Evan.Quan-5C7GfCeVMHo@public.gmane.org>
Subject: [PATCH] drm/amd/powerplay: minor fixes around SW SMU power and fan setting

Add checking for possible invalid input and null pointer. And
drop redundant code.

Change-Id: I6ebd6acd944e821fb19af77ed1eaa8c4b1d407ce
Signed-off-by: Evan Quan <evan.quan-5C7GfCeVMHo@public.gmane.org>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c    | 22 ++++++++++-----------
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 24 +++++++++++------------
 2 files changed, 21 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index bdf537d3f459..9aa00d67e61d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1667,20 +1667,16 @@ static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
                 return -EINVAL;

-       if (is_support_sw_smu(adev)) {
-               err = kstrtoint(buf, 10, &value);
-               if (err)
-                       return err;
+       err = kstrtoint(buf, 10, &value);
+       if (err)
+               return err;

+       if (is_support_sw_smu(adev)) {
                 smu_set_fan_control_mode(&adev->smu, value);
         } else {
                 if (!adev->powerplay.pp_funcs->set_fan_control_mode)
                         return -EINVAL;

-               err = kstrtoint(buf, 10, &value);
-               if (err)
-                       return err;
-
                 amdgpu_dpm_set_fan_control_mode(adev, value);
         }

@@ -2100,16 +2096,18 @@ static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
                 return err;

         value = value / 1000000; /* convert to Watt */
+
         if (is_support_sw_smu(adev)) {
-               adev->smu.funcs->set_power_limit(&adev->smu, value);
+               err = smu_set_power_limit(&adev->smu, value);
         } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit) {
                 err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
-               if (err)
-                       return err;
         } else {
-               return -EINVAL;
+               err = -EINVAL;
         }

+       if (err)
+               return err;
+
         return count;
 }

diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index d1486c3e1357..8ac9acabebf8 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1092,6 +1092,8 @@ static int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
                 max_power_limit *= (100 + smu->smu_table.TDPODLimit);
                 max_power_limit /= 100;
         }
+       if (n > max_power_limit)
+               return -EINVAL;

         if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n);
@@ -1407,17 +1409,17 @@ smu_v11_0_get_fan_control_mode(struct smu_context *smu)
 }

 static int
-smu_v11_0_smc_fan_control(struct smu_context *smu, bool start)
+smu_v11_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
 {
         int ret = 0;

         if (smu_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
                 return 0;

-       ret = smu_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, start);
+       ret = smu_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
         if (ret)
                 pr_err("[%s]%s smc FAN CONTROL feature failed!",
-                      __func__, (start ? "Start" : "Stop"));
+                      __func__, (auto_fan_control ? "Start" : "Stop"));

         return ret;
 }
@@ -1441,16 +1443,15 @@ static int
 smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
 {
         struct amdgpu_device *adev = smu->adev;
-       uint32_t duty100;
-       uint32_t duty;
+       uint32_t duty100, duty;
         uint64_t tmp64;
-       bool stop = 0;

         if (speed > 100)
                 speed = 100;

-       if (smu_v11_0_smc_fan_control(smu, stop))
+       if (smu_v11_0_auto_fan_control(smu, 0))
                 return -EINVAL;
+
         duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
                                 CG_FDO_CTRL1, FMAX_DUTY100);
         if (!duty100)
@@ -1472,18 +1473,16 @@ smu_v11_0_set_fan_control_mode(struct smu_context *smu,
                                uint32_t mode)
 {
         int ret = 0;
-       bool start = 1;
-       bool stop  = 0;

         switch (mode) {
         case AMD_FAN_CTRL_NONE:
                 ret = smu_v11_0_set_fan_speed_percent(smu, 100);
                 break;
         case AMD_FAN_CTRL_MANUAL:
-               ret = smu_v11_0_smc_fan_control(smu, stop);
+               ret = smu_v11_0_auto_fan_control(smu, 0);
                 break;
         case AMD_FAN_CTRL_AUTO:
-               ret = smu_v11_0_smc_fan_control(smu, start);
+               ret = smu_v11_0_auto_fan_control(smu, 1);
                 break;
         default:
                 break;
@@ -1503,13 +1502,12 @@ static int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
         struct amdgpu_device *adev = smu->adev;
         int ret;
         uint32_t tach_period, crystal_clock_freq;
-       bool stop = 0;

         if (!speed)
                 return -EINVAL;

         mutex_lock(&(smu->mutex));
-       ret = smu_v11_0_smc_fan_control(smu, stop);
+       ret = smu_v11_0_auto_fan_control(smu, 0);
         if (ret)
                 goto set_fan_speed_rpm_failed;

--
2.22.0

_______________________________________________
amd-gfx mailing list
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

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_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 6+ messages in thread

* Re: [PATCH 2/2] drm/amd/powerplay: enable SW SMU reset functionality
       [not found]     ` <20190725023930.22521-2-evan.quan-5C7GfCeVMHo@public.gmane.org>
@ 2019-07-25 13:08       ` Wang, Kevin(Yang)
       [not found]         ` <MN2PR12MB3296605E0E8E85F415368D46A2C10-rweVpJHSKTqAm9ToKNQgFgdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
  0 siblings, 1 reply; 6+ messages in thread
From: Wang, Kevin(Yang) @ 2019-07-25 13:08 UTC (permalink / raw)
  To: Quan, Evan, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW


[-- Attachment #1.1: Type: text/plain, Size: 2995 bytes --]

I don't recommend that, because obviously this is a hardware operation, so why need to move it  into sw init?
Is this a workaround solution, or is it specific to which asic?
and set pptable from sysfs and do baco reset operation need to call these functions, have you test it?
the function in amdgpu_smu.c and smu_v11_0.c need work correctly in all asic,
it needs to be done carefully, unless there is a good reason.

Best Regards,
Kevin

________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Evan Quan <evan.quan-5C7GfCeVMHo@public.gmane.org>
Sent: Thursday, July 25, 2019 10:39 AM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
Cc: Quan, Evan <Evan.Quan-5C7GfCeVMHo@public.gmane.org>
Subject: [PATCH 2/2] drm/amd/powerplay: enable SW SMU reset functionality

Move SMU irq handler register to sw_init as that's totally
software related. Otherwise, it will prevent SMU reset working.

Change-Id: Ibd3e48ae9a90ab57f42b3f2ddbb736deeebc8715
Signed-off-by: Evan Quan <evan.quan-5C7GfCeVMHo@public.gmane.org>
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 6935a00cd389..a5079b93caa3 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -741,6 +741,12 @@ static int smu_sw_init(void *handle)
                 return ret;
         }

+       ret = smu_register_irq_handler(smu);
+       if (ret) {
+               pr_err("Failed to register smc irq handler!\n");
+               return ret;
+       }
+
         return 0;
 }

@@ -750,6 +756,9 @@ static int smu_sw_fini(void *handle)
         struct smu_context *smu = &adev->smu;
         int ret;

+       kfree(smu->irq_source);
+       smu->irq_source = NULL;
+
         ret = smu_smc_table_sw_fini(smu);
         if (ret) {
                 pr_err("Failed to sw fini smc table!\n");
@@ -1061,10 +1070,6 @@ static int smu_hw_init(void *handle)
         if (ret)
                 goto failed;

-       ret = smu_register_irq_handler(smu);
-       if (ret)
-               goto failed;
-
         if (!smu->pm_enabled)
                 adev->pm.dpm_enabled = false;
         else
@@ -1094,9 +1099,6 @@ static int smu_hw_fini(void *handle)
         kfree(table_context->overdrive_table);
         table_context->overdrive_table = NULL;

-       kfree(smu->irq_source);
-       smu->irq_source = NULL;
-
         ret = smu_fini_fb_allocations(smu);
         if (ret)
                 return ret;
--
2.22.0

_______________________________________________
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amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

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[-- Attachment #2: Type: text/plain, Size: 153 bytes --]

_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 6+ messages in thread

* RE: [PATCH 2/2] drm/amd/powerplay: enable SW SMU reset functionality
       [not found]         ` <MN2PR12MB3296605E0E8E85F415368D46A2C10-rweVpJHSKTqAm9ToKNQgFgdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
@ 2019-07-26  1:03           ` Quan, Evan
       [not found]             ` <MN2PR12MB33446FE3CFFC12443A9FFB9CE4C00-rweVpJHSKToDMgCC8P//OwdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
  0 siblings, 1 reply; 6+ messages in thread
From: Quan, Evan @ 2019-07-26  1:03 UTC (permalink / raw)
  To: Wang, Kevin(Yang), amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW


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It's a bug fix for uploading new pptable from sysfs.
And it's not hardware involved. The real hardware operation involved with this is in smu_v11_0_enable_thermal_alert.
And in old powerplay routine, this is also put in sw_init and we do not find any problem with that until now.

Regards,
Evan
From: Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>
Sent: Thursday, July 25, 2019 9:08 PM
To: Quan, Evan <Evan.Quan-5C7GfCeVMHo@public.gmane.org>; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: Re: [PATCH 2/2] drm/amd/powerplay: enable SW SMU reset functionality

I don't recommend that, because obviously this is a hardware operation, so why need to move it  into sw init?
Is this a workaround solution, or is it specific to which asic?
and set pptable from sysfs and do baco reset operation need to call these functions, have you test it?
the function in amdgpu_smu.c and smu_v11_0.c need work correctly in all asic,
it needs to be done carefully, unless there is a good reason.

Best Regards,
Kevin

________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-bounces@lists.freedesktop.org>> on behalf of Evan Quan <evan.quan-5C7GfCeVMHo@public.gmane.org<mailto:evan.quan-5C7GfCeVMHo@public.gmane.org>>
Sent: Thursday, July 25, 2019 10:39 AM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>>
Cc: Quan, Evan <Evan.Quan-5C7GfCeVMHo@public.gmane.org<mailto:Evan.Quan-5C7GfCeVMHo@public.gmane.org>>
Subject: [PATCH 2/2] drm/amd/powerplay: enable SW SMU reset functionality

Move SMU irq handler register to sw_init as that's totally
software related. Otherwise, it will prevent SMU reset working.

Change-Id: Ibd3e48ae9a90ab57f42b3f2ddbb736deeebc8715
Signed-off-by: Evan Quan <evan.quan-5C7GfCeVMHo@public.gmane.org<mailto:evan.quan-5C7GfCeVMHo@public.gmane.org>>
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 6935a00cd389..a5079b93caa3 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -741,6 +741,12 @@ static int smu_sw_init(void *handle)
                 return ret;
         }

+       ret = smu_register_irq_handler(smu);
+       if (ret) {
+               pr_err("Failed to register smc irq handler!\n");
+               return ret;
+       }
+
         return 0;
 }

@@ -750,6 +756,9 @@ static int smu_sw_fini(void *handle)
         struct smu_context *smu = &adev->smu;
         int ret;

+       kfree(smu->irq_source);
+       smu->irq_source = NULL;
+
         ret = smu_smc_table_sw_fini(smu);
         if (ret) {
                 pr_err("Failed to sw fini smc table!\n");
@@ -1061,10 +1070,6 @@ static int smu_hw_init(void *handle)
         if (ret)
                 goto failed;

-       ret = smu_register_irq_handler(smu);
-       if (ret)
-               goto failed;
-
         if (!smu->pm_enabled)
                 adev->pm.dpm_enabled = false;
         else
@@ -1094,9 +1099,6 @@ static int smu_hw_fini(void *handle)
         kfree(table_context->overdrive_table);
         table_context->overdrive_table = NULL;

-       kfree(smu->irq_source);
-       smu->irq_source = NULL;
-
         ret = smu_fini_fb_allocations(smu);
         if (ret)
                 return ret;
--
2.22.0

_______________________________________________
amd-gfx mailing list
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

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_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 6+ messages in thread

* RE: [PATCH 2/2] drm/amd/powerplay: enable SW SMU reset functionality
       [not found]             ` <MN2PR12MB33446FE3CFFC12443A9FFB9CE4C00-rweVpJHSKToDMgCC8P//OwdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
@ 2019-07-26  3:59               ` Feng, Kenneth
  0 siblings, 0 replies; 6+ messages in thread
From: Feng, Kenneth @ 2019-07-26  3:59 UTC (permalink / raw)
  To: Quan, Evan, Wang, Kevin(Yang), amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW


[-- Attachment #1.1: Type: text/plain, Size: 4668 bytes --]

I think that's ok to put in sw_init.

Reviewed-by: Kenneth Feng <kenneth.feng-5C7GfCeVMHo@public.gmane.org<mailto:kenneth.feng-5C7GfCeVMHo@public.gmane.org>>


From: amd-gfx [mailto:amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org] On Behalf Of Quan, Evan
Sent: Friday, July 26, 2019 9:04 AM
To: Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: RE: [PATCH 2/2] drm/amd/powerplay: enable SW SMU reset functionality

[CAUTION: External Email]
It's a bug fix for uploading new pptable from sysfs.
And it's not hardware involved. The real hardware operation involved with this is in smu_v11_0_enable_thermal_alert.
And in old powerplay routine, this is also put in sw_init and we do not find any problem with that until now.

Regards,
Evan
From: Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org<mailto:Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>>
Sent: Thursday, July 25, 2019 9:08 PM
To: Quan, Evan <Evan.Quan-5C7GfCeVMHo@public.gmane.org<mailto:Evan.Quan-5C7GfCeVMHo@public.gmane.org>>; amd-gfx@lists.freedesktop.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
Subject: Re: [PATCH 2/2] drm/amd/powerplay: enable SW SMU reset functionality

I don't recommend that, because obviously this is a hardware operation, so why need to move it  into sw init?
Is this a workaround solution, or is it specific to which asic?
and set pptable from sysfs and do baco reset operation need to call these functions, have you test it?
the function in amdgpu_smu.c and smu_v11_0.c need work correctly in all asic,
it needs to be done carefully, unless there is a good reason.

Best Regards,
Kevin

________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-bounces@lists.freedesktop.org>> on behalf of Evan Quan <evan.quan-5C7GfCeVMHo@public.gmane.org<mailto:evan.quan-5C7GfCeVMHo@public.gmane.org>>
Sent: Thursday, July 25, 2019 10:39 AM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>>
Cc: Quan, Evan <Evan.Quan-5C7GfCeVMHo@public.gmane.org<mailto:Evan.Quan-5C7GfCeVMHo@public.gmane.org>>
Subject: [PATCH 2/2] drm/amd/powerplay: enable SW SMU reset functionality

Move SMU irq handler register to sw_init as that's totally
software related. Otherwise, it will prevent SMU reset working.

Change-Id: Ibd3e48ae9a90ab57f42b3f2ddbb736deeebc8715
Signed-off-by: Evan Quan <evan.quan-5C7GfCeVMHo@public.gmane.org<mailto:evan.quan-5C7GfCeVMHo@public.gmane.org>>
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 6935a00cd389..a5079b93caa3 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -741,6 +741,12 @@ static int smu_sw_init(void *handle)
                 return ret;
         }

+       ret = smu_register_irq_handler(smu);
+       if (ret) {
+               pr_err("Failed to register smc irq handler!\n");
+               return ret;
+       }
+
         return 0;
 }

@@ -750,6 +756,9 @@ static int smu_sw_fini(void *handle)
         struct smu_context *smu = &adev->smu;
         int ret;

+       kfree(smu->irq_source);
+       smu->irq_source = NULL;
+
         ret = smu_smc_table_sw_fini(smu);
         if (ret) {
                 pr_err("Failed to sw fini smc table!\n");
@@ -1061,10 +1070,6 @@ static int smu_hw_init(void *handle)
         if (ret)
                 goto failed;

-       ret = smu_register_irq_handler(smu);
-       if (ret)
-               goto failed;
-
         if (!smu->pm_enabled)
                 adev->pm.dpm_enabled = false;
         else
@@ -1094,9 +1099,6 @@ static int smu_hw_fini(void *handle)
         kfree(table_context->overdrive_table);
         table_context->overdrive_table = NULL;

-       kfree(smu->irq_source);
-       smu->irq_source = NULL;
-
         ret = smu_fini_fb_allocations(smu);
         if (ret)
                 return ret;
--
2.22.0

_______________________________________________
amd-gfx mailing list
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

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_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2019-07-26  3:59 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-07-25  2:39 [PATCH] drm/amd/powerplay: minor fixes around SW SMU power and fan setting Evan Quan
     [not found] ` <20190725023930.22521-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
2019-07-25  2:39   ` [PATCH 2/2] drm/amd/powerplay: enable SW SMU reset functionality Evan Quan
     [not found]     ` <20190725023930.22521-2-evan.quan-5C7GfCeVMHo@public.gmane.org>
2019-07-25 13:08       ` Wang, Kevin(Yang)
     [not found]         ` <MN2PR12MB3296605E0E8E85F415368D46A2C10-rweVpJHSKTqAm9ToKNQgFgdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2019-07-26  1:03           ` Quan, Evan
     [not found]             ` <MN2PR12MB33446FE3CFFC12443A9FFB9CE4C00-rweVpJHSKToDMgCC8P//OwdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2019-07-26  3:59               ` Feng, Kenneth
2019-07-25 12:53   ` [PATCH] drm/amd/powerplay: minor fixes around SW SMU power and fan setting Deucher, Alexander

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