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* [v2 0/6] Support mipi dsi video mode on TGL
@ 2019-07-30  7:36 Vandita Kulkarni
  2019-07-30  7:36 ` [v2 1/6] drm/i915/tgl/dsi: Program TRANS_VBLANK register Vandita Kulkarni
                   ` (8 more replies)
  0 siblings, 9 replies; 13+ messages in thread
From: Vandita Kulkarni @ 2019-07-30  7:36 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula

Most of the sequence remains as same as that of ICL.
This series includes the changes needed for TGL.

Vandita Kulkarni (6):
  drm/i915/tgl/dsi: Program TRANS_VBLANK register
  drm/i915/tgl/dsi: Set latency PCS_DW1 for tgl
  drm/i915/tgl/dsi: Do not override TA_SURE
  drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping
  drm/i915/tgl: Add mipi dsi support for TGL
  drm/i915/tgl/dsi: Enable blanking packets during BLLP for video mode

 drivers/gpu/drm/i915/display/icl_dsi.c       | 54 ++++++++++++++------
 drivers/gpu/drm/i915/display/intel_display.c |  1 +
 drivers/gpu/drm/i915/i915_reg.h              |  1 +
 3 files changed, 40 insertions(+), 16 deletions(-)

-- 
2.21.0.5.gaeb582a

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 13+ messages in thread
* [v2 1/6] drm/i915/tgl/dsi: Program TRANS_VBLANK register
  2019-07-30  7:36 [v2 0/6] Support mipi dsi video mode on TGL Vandita Kulkarni
@ 2019-07-30  7:36 ` Vandita Kulkarni
  2019-08-07 10:53   ` Shankar, Uma
  2019-07-30  7:36 ` [v2 2/6] drm/i915/tgl/dsi: Set latency PCS_DW1 for tgl Vandita Kulkarni
                   ` (7 subsequent siblings)
  8 siblings, 1 reply; 13+ messages in thread
From: Vandita Kulkarni @ 2019-07-30  7:36 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula

Program vblank register for mipi dsi in video mode
on TGL.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index a42348be0438..7b8fdb16b651 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -862,6 +862,15 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
 		dsi_trans = dsi_port_to_transcoder(port);
 		I915_WRITE(VSYNCSHIFT(dsi_trans), vsync_shift);
 	}
+
+	/* program TRANS_VBLANK register, should be same as vtotal programmed */
+	if (INTEL_GEN(dev_priv) >= 12) {
+		for_each_dsi_port(port, intel_dsi->ports) {
+			dsi_trans = dsi_port_to_transcoder(port);
+			I915_WRITE(VBLANK(dsi_trans),
+				   (vactive - 1) | ((vtotal - 1) << 16));
+		}
+	}
 }
 
 static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
-- 
2.21.0.5.gaeb582a

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^ permalink raw reply related	[flat|nested] 13+ messages in thread
* [v2 2/6] drm/i915/tgl/dsi: Set latency PCS_DW1 for tgl
  2019-07-30  7:36 [v2 0/6] Support mipi dsi video mode on TGL Vandita Kulkarni
  2019-07-30  7:36 ` [v2 1/6] drm/i915/tgl/dsi: Program TRANS_VBLANK register Vandita Kulkarni
@ 2019-07-30  7:36 ` Vandita Kulkarni
  2019-07-30  7:36 ` [v2 3/6] drm/i915/tgl/dsi: Do not override TA_SURE Vandita Kulkarni
                   ` (6 subsequent siblings)
  8 siblings, 0 replies; 13+ messages in thread
From: Vandita Kulkarni @ 2019-07-30  7:36 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula

Latency programming remains same as that of ICL and
setting latency otimization for PCS_DW1 lanes is same as
that of EHL, hence extending it to TGL.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 7b8fdb16b651..3185cb0bae41 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -403,8 +403,8 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
 		tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
 		I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), tmp);
 
-		/* For EHL set latency optimization for PCS_DW1 lanes */
-		if (IS_ELKHARTLAKE(dev_priv)) {
+		/* For EHL, TGL, set latency optimization for PCS_DW1 lanes */
+		if (IS_ELKHARTLAKE(dev_priv) || (INTEL_GEN(dev_priv) >= 12)) {
 			tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(phy));
 			tmp &= ~LATENCY_OPTIM_MASK;
 			tmp |= LATENCY_OPTIM_VAL(0);
-- 
2.21.0.5.gaeb582a

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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 13+ messages in thread
* [v2 3/6] drm/i915/tgl/dsi: Do not override TA_SURE
  2019-07-30  7:36 [v2 0/6] Support mipi dsi video mode on TGL Vandita Kulkarni
  2019-07-30  7:36 ` [v2 1/6] drm/i915/tgl/dsi: Program TRANS_VBLANK register Vandita Kulkarni
  2019-07-30  7:36 ` [v2 2/6] drm/i915/tgl/dsi: Set latency PCS_DW1 for tgl Vandita Kulkarni
@ 2019-07-30  7:36 ` Vandita Kulkarni
  2019-07-30  7:36 ` [v2 4/6] drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping Vandita Kulkarni
                   ` (5 subsequent siblings)
  8 siblings, 0 replies; 13+ messages in thread
From: Vandita Kulkarni @ 2019-07-30  7:36 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula

Do not override TA_SURE timing parameter to
zero for DSI 8X frequency 800MHz or below on
TGL.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 26 ++++++++++++++------------
 1 file changed, 14 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 3185cb0bae41..c6cda529c5bb 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -530,18 +530,20 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
 	 * a value '0' inside TA_PARAM_REGISTERS otherwise
 	 * leave all fields at HW default values.
 	 */
-	if (intel_dsi_bitrate(intel_dsi) <= 800000) {
-		for_each_dsi_port(port, intel_dsi->ports) {
-			tmp = I915_READ(DPHY_TA_TIMING_PARAM(port));
-			tmp &= ~TA_SURE_MASK;
-			tmp |= TA_SURE_OVERRIDE | TA_SURE(0);
-			I915_WRITE(DPHY_TA_TIMING_PARAM(port), tmp);
-
-			/* shadow register inside display core */
-			tmp = I915_READ(DSI_TA_TIMING_PARAM(port));
-			tmp &= ~TA_SURE_MASK;
-			tmp |= TA_SURE_OVERRIDE | TA_SURE(0);
-			I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp);
+	if (IS_GEN(dev_priv, 11)) {
+		if (intel_dsi_bitrate(intel_dsi) <= 800000) {
+			for_each_dsi_port(port, intel_dsi->ports) {
+				tmp = I915_READ(DPHY_TA_TIMING_PARAM(port));
+				tmp &= ~TA_SURE_MASK;
+				tmp |= TA_SURE_OVERRIDE | TA_SURE(0);
+				I915_WRITE(DPHY_TA_TIMING_PARAM(port), tmp);
+
+				/* shadow register inside display core */
+				tmp = I915_READ(DSI_TA_TIMING_PARAM(port));
+				tmp &= ~TA_SURE_MASK;
+				tmp |= TA_SURE_OVERRIDE | TA_SURE(0);
+				I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp);
+			}
 		}
 	}
 
-- 
2.21.0.5.gaeb582a

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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 13+ messages in thread
* [v2 4/6] drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping
  2019-07-30  7:36 [v2 0/6] Support mipi dsi video mode on TGL Vandita Kulkarni
                   ` (2 preceding siblings ...)
  2019-07-30  7:36 ` [v2 3/6] drm/i915/tgl/dsi: Do not override TA_SURE Vandita Kulkarni
@ 2019-07-30  7:36 ` Vandita Kulkarni
  2019-07-30  7:36 ` [v2 5/6] drm/i915/tgl: Add mipi dsi support for TGL Vandita Kulkarni
                   ` (4 subsequent siblings)
  8 siblings, 0 replies; 13+ messages in thread
From: Vandita Kulkarni @ 2019-07-30  7:36 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula

For TGL, there is no need to keep DDI clock on till IO enabling
for mipi dsi.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index c6cda529c5bb..eaf2779b89b8 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -607,7 +607,10 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder,
 	I915_WRITE(ICL_DPCLKA_CFGCR0, val);
 
 	for_each_dsi_phy(phy, intel_dsi->phys) {
-		val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
+		if (INTEL_GEN(dev_priv) >= 12)
+			val |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
+		else
+			val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
 	}
 	I915_WRITE(ICL_DPCLKA_CFGCR0, val);
 
@@ -951,6 +954,8 @@ static void
 gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
 			      const struct intel_crtc_state *pipe_config)
 {
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
 	/* step 4a: power up all lanes of the DDI used by DSI */
 	gen11_dsi_power_up_lanes(encoder);
 
@@ -973,7 +978,8 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
 	gen11_dsi_configure_transcoder(encoder, pipe_config);
 
 	/* Step 4l: Gate DDI clocks */
-	gen11_dsi_gate_clocks(encoder);
+	if (IS_GEN(dev_priv, 11))
+		gen11_dsi_gate_clocks(encoder);
 }
 
 static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
-- 
2.21.0.5.gaeb582a

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 13+ messages in thread
* [v2 5/6] drm/i915/tgl: Add mipi dsi support for TGL
  2019-07-30  7:36 [v2 0/6] Support mipi dsi video mode on TGL Vandita Kulkarni
                   ` (3 preceding siblings ...)
  2019-07-30  7:36 ` [v2 4/6] drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping Vandita Kulkarni
@ 2019-07-30  7:36 ` Vandita Kulkarni
  2019-08-07 10:55   ` Shankar, Uma
  2019-07-30  7:36 ` [v2 6/6] drm/i915/tgl/dsi: Enable blanking packets during BLLP for video mode Vandita Kulkarni
                   ` (3 subsequent siblings)
  8 siblings, 1 reply; 13+ messages in thread
From: Vandita Kulkarni @ 2019-07-30  7:36 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula

Most of the functions and mipi dsi sequence remains
same as of ICL for TGL. Hence extending the support
to TGL.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 9e4ee29fd0fc..71ae62e94767 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15319,6 +15319,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
 		intel_ddi_init(dev_priv, PORT_A);
 		intel_ddi_init(dev_priv, PORT_B);
 		intel_ddi_init(dev_priv, PORT_C);
+		icl_dsi_init(dev_priv);
 	} else if (IS_ELKHARTLAKE(dev_priv)) {
 		intel_ddi_init(dev_priv, PORT_A);
 		intel_ddi_init(dev_priv, PORT_B);
-- 
2.21.0.5.gaeb582a

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 13+ messages in thread
* [v2 6/6] drm/i915/tgl/dsi: Enable blanking packets during BLLP for video mode
  2019-07-30  7:36 [v2 0/6] Support mipi dsi video mode on TGL Vandita Kulkarni
                   ` (4 preceding siblings ...)
  2019-07-30  7:36 ` [v2 5/6] drm/i915/tgl: Add mipi dsi support for TGL Vandita Kulkarni
@ 2019-07-30  7:36 ` Vandita Kulkarni
  2019-08-07 11:07   ` Shankar, Uma
  2019-07-30  8:44 ` ✓ Fi.CI.BAT: success for Support mipi dsi video mode on TGL (rev2) Patchwork
                   ` (2 subsequent siblings)
  8 siblings, 1 reply; 13+ messages in thread
From: Vandita Kulkarni @ 2019-07-30  7:36 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula

Blanking packet bit will control whether the transcoder allows the link
to enter the LP state during BLLP regions (assuming there is enough time),
or whether it will keep the link in the HS state with a Blanking Packet

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 5 +++++
 drivers/gpu/drm/i915/i915_reg.h        | 1 +
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index eaf2779b89b8..ae33639d48ba 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -685,6 +685,11 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
 			break;
 		}
 
+		if (INTEL_GEN(dev_priv) >= 12) {
+			if (is_vid_mode(intel_dsi))
+				tmp |= BLANKING_PACKET_ENABLE;
+		}
+
 		/* program DSI operation mode */
 		if (is_vid_mode(intel_dsi)) {
 			tmp &= ~OP_MODE_MASK;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d2b76121d863..1a847f443ef7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10979,6 +10979,7 @@ enum skl_power_gate {
 #define  CALIBRATION_DISABLED		(0x0 << 4)
 #define  CALIBRATION_ENABLED_INITIAL_ONLY	(0x2 << 4)
 #define  CALIBRATION_ENABLED_INITIAL_PERIODIC	(0x3 << 4)
+#define  BLANKING_PACKET_ENABLE		(1 << 2)
 #define  S3D_ORIENTATION_LANDSCAPE	(1 << 1)
 #define  EOTP_DISABLED			(1 << 0)
 
-- 
2.21.0.5.gaeb582a

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 13+ messages in thread
* ✓ Fi.CI.BAT: success for Support mipi dsi video mode on TGL (rev2)
  2019-07-30  7:36 [v2 0/6] Support mipi dsi video mode on TGL Vandita Kulkarni
                   ` (5 preceding siblings ...)
  2019-07-30  7:36 ` [v2 6/6] drm/i915/tgl/dsi: Enable blanking packets during BLLP for video mode Vandita Kulkarni
@ 2019-07-30  8:44 ` Patchwork
  2019-08-08 12:55 ` [v2 0/6] Support mipi dsi video mode on TGL Shankar, Uma
  2019-08-12 14:04 ` ✗ Fi.CI.BAT: failure for Support mipi dsi video mode on TGL (rev3) Patchwork
  8 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2019-07-30  8:44 UTC (permalink / raw)
  To: Vandita Kulkarni; +Cc: intel-gfx

== Series Details ==

Series: Support mipi dsi video mode on TGL (rev2)
URL   : https://patchwork.freedesktop.org/series/63058/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6576 -> Patchwork_13794
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13794/

Known issues
------------

  Here are the changes found in Patchwork_13794 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@debugfs_test@read_all_entries:
    - fi-icl-u3:          [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6576/fi-icl-u3/igt@debugfs_test@read_all_entries.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13794/fi-icl-u3/igt@debugfs_test@read_all_entries.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-icl-u2:          [PASS][3] -> [FAIL][4] ([fdo#103167])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6576/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13794/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html

  
#### Possible fixes ####

  * igt@kms_busy@basic-flip-a:
    - fi-kbl-7567u:       [SKIP][5] ([fdo#109271] / [fdo#109278]) -> [PASS][6] +2 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6576/fi-kbl-7567u/igt@kms_busy@basic-flip-a.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13794/fi-kbl-7567u/igt@kms_busy@basic-flip-a.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-icl-u2:          [FAIL][7] ([fdo#109483]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6576/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13794/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html

  
#### Warnings ####

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][9] ([fdo#109485]) -> [FAIL][10] ([fdo#109483])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6576/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13794/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
  [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485


Participating hosts (51 -> 47)
------------------------------

  Additional (1): fi-icl-guc 
  Missing    (5): fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6576 -> Patchwork_13794

  CI-20190529: 20190529
  CI_DRM_6576: 4040b4c4ab647422d82100c8b091d34b6a82f572 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5115: 21be7a02ac8a8ff46b561c36a69e4dd5a0c2938b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13794: 24de3eb4ec729c2f80ce8af4aa20ee234224370d @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

24de3eb4ec72 drm/i915/tgl/dsi: Enable blanking packets during BLLP for video mode
092128c1b8d5 drm/i915/tgl: Add mipi dsi support for TGL
59319ff6e0f1 drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping
2af770081f04 drm/i915/tgl/dsi: Do not override TA_SURE
84e4be711802 drm/i915/tgl/dsi: Set latency PCS_DW1 for tgl
823eaa1a31fe drm/i915/tgl/dsi: Program TRANS_VBLANK register

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13794/
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^ permalink raw reply	[flat|nested] 13+ messages in thread
* Re: [v2 1/6] drm/i915/tgl/dsi: Program TRANS_VBLANK register
  2019-07-30  7:36 ` [v2 1/6] drm/i915/tgl/dsi: Program TRANS_VBLANK register Vandita Kulkarni
@ 2019-08-07 10:53   ` Shankar, Uma
  0 siblings, 0 replies; 13+ messages in thread
From: Shankar, Uma @ 2019-08-07 10:53 UTC (permalink / raw)
  To: Kulkarni, Vandita, intel-gfx; +Cc: Nikula, Jani



>-----Original Message-----
>From: Kulkarni, Vandita
>Sent: Tuesday, July 30, 2019 1:07 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Nikula, Jani <jani.nikula@intel.com>; ville.syrjala@linux.intel.com; Shankar, Uma
><uma.shankar@intel.com>; Kulkarni, Vandita <vandita.kulkarni@intel.com>
>Subject: [v2 1/6] drm/i915/tgl/dsi: Program TRANS_VBLANK register
>
>Program vblank register for mipi dsi in video mode on TGL.

Looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

>Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>---
> drivers/gpu/drm/i915/display/icl_dsi.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
>b/drivers/gpu/drm/i915/display/icl_dsi.c
>index a42348be0438..7b8fdb16b651 100644
>--- a/drivers/gpu/drm/i915/display/icl_dsi.c
>+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
>@@ -862,6 +862,15 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder
>*encoder,
> 		dsi_trans = dsi_port_to_transcoder(port);
> 		I915_WRITE(VSYNCSHIFT(dsi_trans), vsync_shift);
> 	}
>+
>+	/* program TRANS_VBLANK register, should be same as vtotal programmed
>*/
>+	if (INTEL_GEN(dev_priv) >= 12) {
>+		for_each_dsi_port(port, intel_dsi->ports) {
>+			dsi_trans = dsi_port_to_transcoder(port);
>+			I915_WRITE(VBLANK(dsi_trans),
>+				   (vactive - 1) | ((vtotal - 1) << 16));
>+		}
>+	}
> }
>
> static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
>--
>2.21.0.5.gaeb582a

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^ permalink raw reply	[flat|nested] 13+ messages in thread
* Re: [v2 5/6] drm/i915/tgl: Add mipi dsi support for TGL
  2019-07-30  7:36 ` [v2 5/6] drm/i915/tgl: Add mipi dsi support for TGL Vandita Kulkarni
@ 2019-08-07 10:55   ` Shankar, Uma
  0 siblings, 0 replies; 13+ messages in thread
From: Shankar, Uma @ 2019-08-07 10:55 UTC (permalink / raw)
  To: Kulkarni, Vandita, intel-gfx; +Cc: Nikula, Jani



>-----Original Message-----
>From: Kulkarni, Vandita
>Sent: Tuesday, July 30, 2019 1:07 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Nikula, Jani <jani.nikula@intel.com>; ville.syrjala@linux.intel.com; Shankar, Uma
><uma.shankar@intel.com>; Kulkarni, Vandita <vandita.kulkarni@intel.com>
>Subject: [v2 5/6] drm/i915/tgl: Add mipi dsi support for TGL
>
>Most of the functions and mipi dsi sequence remains same as of ICL for TGL. Hence
>extending the support to TGL.

Looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

>Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>---
> drivers/gpu/drm/i915/display/intel_display.c | 1 +
> 1 file changed, 1 insertion(+)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>b/drivers/gpu/drm/i915/display/intel_display.c
>index 9e4ee29fd0fc..71ae62e94767 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.c
>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>@@ -15319,6 +15319,7 @@ static void intel_setup_outputs(struct drm_i915_private
>*dev_priv)
> 		intel_ddi_init(dev_priv, PORT_A);
> 		intel_ddi_init(dev_priv, PORT_B);
> 		intel_ddi_init(dev_priv, PORT_C);
>+		icl_dsi_init(dev_priv);
> 	} else if (IS_ELKHARTLAKE(dev_priv)) {
> 		intel_ddi_init(dev_priv, PORT_A);
> 		intel_ddi_init(dev_priv, PORT_B);
>--
>2.21.0.5.gaeb582a

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^ permalink raw reply	[flat|nested] 13+ messages in thread
* Re: [v2 6/6] drm/i915/tgl/dsi: Enable blanking packets during BLLP for video mode
  2019-07-30  7:36 ` [v2 6/6] drm/i915/tgl/dsi: Enable blanking packets during BLLP for video mode Vandita Kulkarni
@ 2019-08-07 11:07   ` Shankar, Uma
  0 siblings, 0 replies; 13+ messages in thread
From: Shankar, Uma @ 2019-08-07 11:07 UTC (permalink / raw)
  To: Kulkarni, Vandita, intel-gfx; +Cc: Nikula, Jani



>-----Original Message-----
>From: Kulkarni, Vandita
>Sent: Tuesday, July 30, 2019 1:07 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Nikula, Jani <jani.nikula@intel.com>; ville.syrjala@linux.intel.com; Shankar, Uma
><uma.shankar@intel.com>; Kulkarni, Vandita <vandita.kulkarni@intel.com>
>Subject: [v2 6/6] drm/i915/tgl/dsi: Enable blanking packets during BLLP for video
>mode
>
>Blanking packet bit will control whether the transcoder allows the link to enter the LP
>state during BLLP regions (assuming there is enough time), or whether it will keep the
>link in the HS state with a Blanking Packet

Looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

>Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>---
> drivers/gpu/drm/i915/display/icl_dsi.c | 5 +++++
> drivers/gpu/drm/i915/i915_reg.h        | 1 +
> 2 files changed, 6 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
>b/drivers/gpu/drm/i915/display/icl_dsi.c
>index eaf2779b89b8..ae33639d48ba 100644
>--- a/drivers/gpu/drm/i915/display/icl_dsi.c
>+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
>@@ -685,6 +685,11 @@ gen11_dsi_configure_transcoder(struct intel_encoder
>*encoder,
> 			break;
> 		}
>
>+		if (INTEL_GEN(dev_priv) >= 12) {
>+			if (is_vid_mode(intel_dsi))
>+				tmp |= BLANKING_PACKET_ENABLE;
>+		}
>+
> 		/* program DSI operation mode */
> 		if (is_vid_mode(intel_dsi)) {
> 			tmp &= ~OP_MODE_MASK;
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index
>d2b76121d863..1a847f443ef7 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -10979,6 +10979,7 @@ enum skl_power_gate {
> #define  CALIBRATION_DISABLED		(0x0 << 4)
> #define  CALIBRATION_ENABLED_INITIAL_ONLY	(0x2 << 4)
> #define  CALIBRATION_ENABLED_INITIAL_PERIODIC	(0x3 << 4)
>+#define  BLANKING_PACKET_ENABLE		(1 << 2)
> #define  S3D_ORIENTATION_LANDSCAPE	(1 << 1)
> #define  EOTP_DISABLED			(1 << 0)
>
>--
>2.21.0.5.gaeb582a

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^ permalink raw reply	[flat|nested] 13+ messages in thread
* Re: [v2 0/6] Support mipi dsi video mode on TGL
  2019-07-30  7:36 [v2 0/6] Support mipi dsi video mode on TGL Vandita Kulkarni
                   ` (6 preceding siblings ...)
  2019-07-30  8:44 ` ✓ Fi.CI.BAT: success for Support mipi dsi video mode on TGL (rev2) Patchwork
@ 2019-08-08 12:55 ` Shankar, Uma
  2019-08-12 14:04 ` ✗ Fi.CI.BAT: failure for Support mipi dsi video mode on TGL (rev3) Patchwork
  8 siblings, 0 replies; 13+ messages in thread
From: Shankar, Uma @ 2019-08-08 12:55 UTC (permalink / raw)
  To: Kulkarni, Vandita, intel-gfx; +Cc: Nikula, Jani



>-----Original Message-----
>From: Kulkarni, Vandita
>Sent: Tuesday, July 30, 2019 1:07 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Nikula, Jani <jani.nikula@intel.com>; ville.syrjala@linux.intel.com; Shankar, Uma
><uma.shankar@intel.com>; Kulkarni, Vandita <vandita.kulkarni@intel.com>
>Subject: [v2 0/6] Support mipi dsi video mode on TGL
>
>Most of the sequence remains as same as that of ICL.
>This series includes the changes needed for TGL.

Series pushed to dinq. Thanks for the patches.

Regards,
Uma Shankar

>Vandita Kulkarni (6):
>  drm/i915/tgl/dsi: Program TRANS_VBLANK register
>  drm/i915/tgl/dsi: Set latency PCS_DW1 for tgl
>  drm/i915/tgl/dsi: Do not override TA_SURE
>  drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping
>  drm/i915/tgl: Add mipi dsi support for TGL
>  drm/i915/tgl/dsi: Enable blanking packets during BLLP for video mode
>
> drivers/gpu/drm/i915/display/icl_dsi.c       | 54 ++++++++++++++------
> drivers/gpu/drm/i915/display/intel_display.c |  1 +
> drivers/gpu/drm/i915/i915_reg.h              |  1 +
> 3 files changed, 40 insertions(+), 16 deletions(-)
>
>--
>2.21.0.5.gaeb582a

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^ permalink raw reply	[flat|nested] 13+ messages in thread
* ✗ Fi.CI.BAT: failure for Support mipi dsi video mode on TGL (rev3)
  2019-07-30  7:36 [v2 0/6] Support mipi dsi video mode on TGL Vandita Kulkarni
                   ` (7 preceding siblings ...)
  2019-08-08 12:55 ` [v2 0/6] Support mipi dsi video mode on TGL Shankar, Uma
@ 2019-08-12 14:04 ` Patchwork
  8 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2019-08-12 14:04 UTC (permalink / raw)
  To: Vandita Kulkarni; +Cc: intel-gfx

== Series Details ==

Series: Support mipi dsi video mode on TGL (rev3)
URL   : https://patchwork.freedesktop.org/series/63058/
State : failure

== Summary ==

Applying: drm/i915/tgl/dsi: Program TRANS_VBLANK register
Using index info to reconstruct a base tree...
M	drivers/gpu/drm/i915/display/icl_dsi.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/display/icl_dsi.c
No changes -- Patch already applied.
Applying: drm/i915/tgl/dsi: Set latency PCS_DW1 for tgl
Using index info to reconstruct a base tree...
M	drivers/gpu/drm/i915/display/icl_dsi.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/display/icl_dsi.c
No changes -- Patch already applied.
Applying: drm/i915/tgl/dsi: Do not override TA_SURE
Using index info to reconstruct a base tree...
M	drivers/gpu/drm/i915/display/icl_dsi.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/display/icl_dsi.c
No changes -- Patch already applied.
Applying: drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping
Using index info to reconstruct a base tree...
M	drivers/gpu/drm/i915/display/icl_dsi.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/display/icl_dsi.c
No changes -- Patch already applied.
Applying: drm/i915/tgl: Add mipi dsi support for TGL
Using index info to reconstruct a base tree...
M	drivers/gpu/drm/i915/display/intel_display.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/display/intel_display.c
No changes -- Patch already applied.
Applying: drm/i915/tgl/dsi: Enable blanking packets during BLLP for video mode
Using index info to reconstruct a base tree...
M	drivers/gpu/drm/i915/display/icl_dsi.c
M	drivers/gpu/drm/i915/i915_reg.h
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/i915_reg.h
No changes -- Patch already applied.

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^ permalink raw reply	[flat|nested] 13+ messages in thread
end of thread, other threads:[~2019-08-12 14:04 UTC | newest]

Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-07-30  7:36 [v2 0/6] Support mipi dsi video mode on TGL Vandita Kulkarni
2019-07-30  7:36 ` [v2 1/6] drm/i915/tgl/dsi: Program TRANS_VBLANK register Vandita Kulkarni
2019-08-07 10:53   ` Shankar, Uma
2019-07-30  7:36 ` [v2 2/6] drm/i915/tgl/dsi: Set latency PCS_DW1 for tgl Vandita Kulkarni
2019-07-30  7:36 ` [v2 3/6] drm/i915/tgl/dsi: Do not override TA_SURE Vandita Kulkarni
2019-07-30  7:36 ` [v2 4/6] drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping Vandita Kulkarni
2019-07-30  7:36 ` [v2 5/6] drm/i915/tgl: Add mipi dsi support for TGL Vandita Kulkarni
2019-08-07 10:55   ` Shankar, Uma
2019-07-30  7:36 ` [v2 6/6] drm/i915/tgl/dsi: Enable blanking packets during BLLP for video mode Vandita Kulkarni
2019-08-07 11:07   ` Shankar, Uma
2019-07-30  8:44 ` ✓ Fi.CI.BAT: success for Support mipi dsi video mode on TGL (rev2) Patchwork
2019-08-08 12:55 ` [v2 0/6] Support mipi dsi video mode on TGL Shankar, Uma
2019-08-12 14:04 ` ✗ Fi.CI.BAT: failure for Support mipi dsi video mode on TGL (rev3) Patchwork

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