* [PATCH 1/2] drm/amdgpu: Update NBIO headers to add TXCLK3/4
@ 2019-08-01 11:48 Russell, Kent
[not found] ` <20190801114828.12273-1-kent.russell-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 3+ messages in thread
From: Russell, Kent @ 2019-08-01 11:48 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Russell, Kent
These are added for VG20, and are needed for PCIe bandwidth.
Change-Id: I54474bb53ed563d083521d24944f5f97d372f001
Signed-off-by: Kent Russell <kent.russell@amd.com>
---
.../include/asic_reg/nbio/nbio_7_0_sh_mask.h | 30 +++++++++++++++++++
.../amd/include/asic_reg/nbio/nbio_7_0_smn.h | 6 ++++
2 files changed, 36 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h
index 88602479a1aa..ee8c15e4543d 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h
@@ -74709,6 +74709,36 @@
//PCIE_PERF_COUNT1_TXCLK2
#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT 0x0
#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK 0xFFFFFFFFL
+//PCIE_PERF_CNTL_TXCLK3
+#define PCIE_PERF_CNTL_TXCLK3__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_TXCLK3__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_TXCLK3__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_TXCLK3__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_CNTL_TXCLK3__EVENT0_SEL_MASK 0x000000FFL
+#define PCIE_PERF_CNTL_TXCLK3__EVENT1_SEL_MASK 0x0000FF00L
+#define PCIE_PERF_CNTL_TXCLK3__COUNTER0_UPPER_MASK 0x00FF0000L
+#define PCIE_PERF_CNTL_TXCLK3__COUNTER1_UPPER_MASK 0xFF000000L
+//PCIE_PERF_COUNT0_TXCLK3
+#define PCIE_PERF_COUNT0_TXCLK3__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT0_TXCLK3__COUNTER0_MASK 0xFFFFFFFFL
+//PCIE_PERF_COUNT1_TXCLK3
+#define PCIE_PERF_COUNT1_TXCLK3__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_COUNT1_TXCLK3__COUNTER1_MASK 0xFFFFFFFFL
+//PCIE_PERF_CNTL_TXCLK4
+#define PCIE_PERF_CNTL_TXCLK4__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_TXCLK4__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_TXCLK4__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_TXCLK4__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_CNTL_TXCLK4__EVENT0_SEL_MASK 0x000000FFL
+#define PCIE_PERF_CNTL_TXCLK4__EVENT1_SEL_MASK 0x0000FF00L
+#define PCIE_PERF_CNTL_TXCLK4__COUNTER0_UPPER_MASK 0x00FF0000L
+#define PCIE_PERF_CNTL_TXCLK4__COUNTER1_UPPER_MASK 0xFF000000L
+//PCIE_PERF_COUNT0_TXCLK4
+#define PCIE_PERF_COUNT0_TXCLK4__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT0_TXCLK4__COUNTER0_MASK 0xFFFFFFFFL
+//PCIE_PERF_COUNT1_TXCLK4
+#define PCIE_PERF_COUNT1_TXCLK4__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_COUNT1_TXCLK4__COUNTER1_MASK 0xFFFFFFFFL
//PCIE_PRBS_CLR
#define PCIE_PRBS_CLR__PRBS_CLR__SHIFT 0x0
#define PCIE_PRBS_CLR__PRBS_POLARITY_EN__SHIFT 0x18
diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h
index caf5ffdc130a..6702575bc6e3 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h
@@ -50,6 +50,12 @@
#define smnPCIE_PERF_CNTL_TXCLK2 0x11180254
#define smnPCIE_PERF_COUNT0_TXCLK2 0x11180258
#define smnPCIE_PERF_COUNT1_TXCLK2 0x1118025c
+#define smnPCIE_PERF_CNTL_TXCLK3 0x1118021c
+#define smnPCIE_PERF_COUNT0_TXCLK3 0x11180220
+#define smnPCIE_PERF_COUNT1_TXCLK3 0x11180224
+#define smnPCIE_PERF_CNTL_TXCLK4 0x11180228
+#define smnPCIE_PERF_COUNT0_TXCLK4 0x1118022c
+#define smnPCIE_PERF_COUNT1_TXCLK4 0x11180230
#define smnPCIE_RX_NUM_NAK 0x11180038
#define smnPCIE_RX_NUM_NAK_GENERATED 0x1118003c
--
2.17.1
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* [PATCH 2/2] drm/amdgpu: Fix pcie_bw on Vega20
[not found] ` <20190801114828.12273-1-kent.russell-5C7GfCeVMHo@public.gmane.org>
@ 2019-08-01 11:48 ` Russell, Kent
2019-08-01 15:44 ` [PATCH 1/2] drm/amdgpu: Update NBIO headers to add TXCLK3/4 Deucher, Alexander
1 sibling, 0 replies; 3+ messages in thread
From: Russell, Kent @ 2019-08-01 11:48 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Russell, Kent
The registers used for VG20 are different in that certain performance
counters were split off to TXCLK3/4. Vega10/12 doesn't have this, so add
a new vg20_get_pcie_usage to reflect this change.
Change-Id: Iec4bf608411b46f0827e7ffeb74ce93e1fd3d1b8
Signed-off-by: Kent Russell <kent.russell@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 60 ++++++++++++++++++++++++++----
1 file changed, 52 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index dc553978d23a..6b8542873393 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -784,14 +784,9 @@ static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
/* Set the 2 events that we wish to watch, defined above */
/* Reg 40 is # received msgs */
+ /* Reg 104 is # of posted requests sent */
perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
- /* Pre-VG20, Reg 104 is # of posted requests sent. On VG20 it's 108 */
- if (adev->asic_type == CHIP_VEGA20)
- perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK,
- EVENT1_SEL, 108);
- else
- perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK,
- EVENT1_SEL, 104);
+ perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
/* Write to enable desired perf counters */
WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
@@ -821,6 +816,55 @@ static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
*count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
}
+static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
+ uint64_t *count1)
+{
+ uint32_t perfctr = 0;
+ uint64_t cnt0_of, cnt1_of;
+ int tmp;
+
+ /* This reports 0 on APUs, so return to avoid writing/reading registers
+ * that may or may not be different from their GPU counterparts
+ */
+ if (adev->flags & AMD_IS_APU)
+ return;
+
+ /* Set the 2 events that we wish to watch, defined above */
+ /* Reg 40 is # received msgs */
+ /* Reg 108 is # of posted requests sent on VG20 */
+ perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
+ EVENT0_SEL, 40);
+ perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
+ EVENT1_SEL, 108);
+
+ /* Write to enable desired perf counters */
+ WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr);
+ /* Zero out and enable the perf counters
+ * Write 0x5:
+ * Bit 0 = Start all counters(1)
+ * Bit 2 = Global counter reset enable(1)
+ */
+ WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
+
+ msleep(1000);
+
+ /* Load the shadow and disable the perf counters
+ * Write 0x2:
+ * Bit 0 = Stop counters(0)
+ * Bit 1 = Load the shadow counters(1)
+ */
+ WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
+
+ /* Read register values to get any >32bit overflow */
+ tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3);
+ cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER);
+ cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER);
+
+ /* Get the values and add the overflow */
+ *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32);
+ *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32);
+}
+
static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
{
u32 sol_reg;
@@ -892,7 +936,7 @@ static const struct amdgpu_asic_funcs vega20_asic_funcs =
.invalidate_hdp = &soc15_invalidate_hdp,
.need_full_reset = &soc15_need_full_reset,
.init_doorbell_index = &vega20_doorbell_index_init,
- .get_pcie_usage = &soc15_get_pcie_usage,
+ .get_pcie_usage = &vega20_get_pcie_usage,
.need_reset_on_init = &soc15_need_reset_on_init,
.get_pcie_replay_count = &soc15_get_pcie_replay_count,
};
--
2.17.1
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^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH 1/2] drm/amdgpu: Update NBIO headers to add TXCLK3/4
[not found] ` <20190801114828.12273-1-kent.russell-5C7GfCeVMHo@public.gmane.org>
2019-08-01 11:48 ` [PATCH 2/2] drm/amdgpu: Fix pcie_bw on Vega20 Russell, Kent
@ 2019-08-01 15:44 ` Deucher, Alexander
1 sibling, 0 replies; 3+ messages in thread
From: Deucher, Alexander @ 2019-08-01 15:44 UTC (permalink / raw)
To: Russell, Kent, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
[-- Attachment #1.1: Type: text/plain, Size: 6127 bytes --]
Series is:
Reviewed-by: Alex Deucher <alexander.deucher-5C7GfCeVMHo@public.gmane.org>
________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Russell, Kent <Kent.Russell-5C7GfCeVMHo@public.gmane.org>
Sent: Thursday, August 1, 2019 7:48 AM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
Cc: Russell, Kent <Kent.Russell-5C7GfCeVMHo@public.gmane.org>
Subject: [PATCH 1/2] drm/amdgpu: Update NBIO headers to add TXCLK3/4
These are added for VG20, and are needed for PCIe bandwidth.
Change-Id: I54474bb53ed563d083521d24944f5f97d372f001
Signed-off-by: Kent Russell <kent.russell-5C7GfCeVMHo@public.gmane.org>
---
.../include/asic_reg/nbio/nbio_7_0_sh_mask.h | 30 +++++++++++++++++++
.../amd/include/asic_reg/nbio/nbio_7_0_smn.h | 6 ++++
2 files changed, 36 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h
index 88602479a1aa..ee8c15e4543d 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h
@@ -74709,6 +74709,36 @@
//PCIE_PERF_COUNT1_TXCLK2
#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT 0x0
#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK 0xFFFFFFFFL
+//PCIE_PERF_CNTL_TXCLK3
+#define PCIE_PERF_CNTL_TXCLK3__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_TXCLK3__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_TXCLK3__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_TXCLK3__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_CNTL_TXCLK3__EVENT0_SEL_MASK 0x000000FFL
+#define PCIE_PERF_CNTL_TXCLK3__EVENT1_SEL_MASK 0x0000FF00L
+#define PCIE_PERF_CNTL_TXCLK3__COUNTER0_UPPER_MASK 0x00FF0000L
+#define PCIE_PERF_CNTL_TXCLK3__COUNTER1_UPPER_MASK 0xFF000000L
+//PCIE_PERF_COUNT0_TXCLK3
+#define PCIE_PERF_COUNT0_TXCLK3__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT0_TXCLK3__COUNTER0_MASK 0xFFFFFFFFL
+//PCIE_PERF_COUNT1_TXCLK3
+#define PCIE_PERF_COUNT1_TXCLK3__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_COUNT1_TXCLK3__COUNTER1_MASK 0xFFFFFFFFL
+//PCIE_PERF_CNTL_TXCLK4
+#define PCIE_PERF_CNTL_TXCLK4__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_TXCLK4__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_TXCLK4__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_TXCLK4__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_CNTL_TXCLK4__EVENT0_SEL_MASK 0x000000FFL
+#define PCIE_PERF_CNTL_TXCLK4__EVENT1_SEL_MASK 0x0000FF00L
+#define PCIE_PERF_CNTL_TXCLK4__COUNTER0_UPPER_MASK 0x00FF0000L
+#define PCIE_PERF_CNTL_TXCLK4__COUNTER1_UPPER_MASK 0xFF000000L
+//PCIE_PERF_COUNT0_TXCLK4
+#define PCIE_PERF_COUNT0_TXCLK4__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT0_TXCLK4__COUNTER0_MASK 0xFFFFFFFFL
+//PCIE_PERF_COUNT1_TXCLK4
+#define PCIE_PERF_COUNT1_TXCLK4__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_COUNT1_TXCLK4__COUNTER1_MASK 0xFFFFFFFFL
//PCIE_PRBS_CLR
#define PCIE_PRBS_CLR__PRBS_CLR__SHIFT 0x0
#define PCIE_PRBS_CLR__PRBS_POLARITY_EN__SHIFT 0x18
diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h
index caf5ffdc130a..6702575bc6e3 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h
@@ -50,6 +50,12 @@
#define smnPCIE_PERF_CNTL_TXCLK2 0x11180254
#define smnPCIE_PERF_COUNT0_TXCLK2 0x11180258
#define smnPCIE_PERF_COUNT1_TXCLK2 0x1118025c
+#define smnPCIE_PERF_CNTL_TXCLK3 0x1118021c
+#define smnPCIE_PERF_COUNT0_TXCLK3 0x11180220
+#define smnPCIE_PERF_COUNT1_TXCLK3 0x11180224
+#define smnPCIE_PERF_CNTL_TXCLK4 0x11180228
+#define smnPCIE_PERF_COUNT0_TXCLK4 0x1118022c
+#define smnPCIE_PERF_COUNT1_TXCLK4 0x11180230
#define smnPCIE_RX_NUM_NAK 0x11180038
#define smnPCIE_RX_NUM_NAK_GENERATED 0x1118003c
--
2.17.1
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2019-08-01 11:48 [PATCH 1/2] drm/amdgpu: Update NBIO headers to add TXCLK3/4 Russell, Kent
[not found] ` <20190801114828.12273-1-kent.russell-5C7GfCeVMHo@public.gmane.org>
2019-08-01 11:48 ` [PATCH 2/2] drm/amdgpu: Fix pcie_bw on Vega20 Russell, Kent
2019-08-01 15:44 ` [PATCH 1/2] drm/amdgpu: Update NBIO headers to add TXCLK3/4 Deucher, Alexander
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