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* [PATCH 0/5] enable umc ras ce interrupt v2
@ 2019-08-01 11:54 Tao Zhou
       [not found] ` <20190801115454.21867-1-tao.zhou1-5C7GfCeVMHo@public.gmane.org>
  0 siblings, 1 reply; 7+ messages in thread
From: Tao Zhou @ 2019-08-01 11:54 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
	hawking.zhang-5C7GfCeVMHo, dennis.li-5C7GfCeVMHo,
	guchun.chen-5C7GfCeVMHo, xinhui.pan-5C7GfCeVMHo
  Cc: Tao Zhou

These patches add support for umc ce interrupt, the interrupt is controlled by a error count threshold.

v2: correct typo in commit description and update comment of patch #2
add patch #5 to replace AMDGPU_RAS_UE with AMDGPU_RAS_SUCCESS

Tao Zhou (5):
  drm/amdgpu: support ce interrupt in ras module
  drm/amdgpu: implement umc ras init function
  drm/amdgpu: update the calc algorithm of umc ecc error count
  drm/amdgpu: only uncorrectable error needs gpu reset
  drm/amdgpu: replace AMDGPU_RAS_UE with AMDGPU_RAS_SUCCESS

 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 14 ++++++---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c   |  2 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   |  8 +++--
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c  |  2 +-
 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c   | 42 ++++++++++++++++++++++---
 drivers/gpu/drm/amd/amdgpu/umc_v6_1.h   |  7 +++++
 6 files changed, 62 insertions(+), 13 deletions(-)

-- 
2.17.1

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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 7+ messages in thread
* [PATCH 1/5] drm/amdgpu: support ce interrupt in ras module
       [not found] ` <20190801115454.21867-1-tao.zhou1-5C7GfCeVMHo@public.gmane.org>
@ 2019-08-01 11:54   ` Tao Zhou
  2019-08-01 11:54   ` [PATCH 2/5] drm/amdgpu: implement umc ras init function Tao Zhou
                     ` (4 subsequent siblings)
  5 siblings, 0 replies; 7+ messages in thread
From: Tao Zhou @ 2019-08-01 11:54 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
	hawking.zhang-5C7GfCeVMHo, dennis.li-5C7GfCeVMHo,
	guchun.chen-5C7GfCeVMHo, xinhui.pan-5C7GfCeVMHo
  Cc: Tao Zhou

correctable error can also trigger interrupt in some ras blocks

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 094c27000b83..4a0dc5269ddf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -1047,12 +1047,12 @@ static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
 			 * the error.
 			 */
 			if (ret == AMDGPU_RAS_UE) {
+				/* these counts could be left as 0 if
+				 * some blocks do not count error number
+				 */
 				obj->err_data.ue_count += err_data.ue_count;
+				obj->err_data.ce_count += err_data.ce_count;
 			}
-			/* Might need get ce count by register, but not all IP
-			 * saves ce count, some IP just use one bit or two bits
-			 * to indicate ce happened.
-			 */
 		}
 	}
 }
@@ -1549,6 +1549,10 @@ int amdgpu_ras_init(struct amdgpu_device *adev)
 	if (amdgpu_ras_fs_init(adev))
 		goto fs_out;
 
+	/* ras init for each ras block */
+	if (adev->umc.funcs->ras_init)
+		adev->umc.funcs->ras_init(adev);
+
 	DRM_INFO("RAS INFO: ras initialized successfully, "
 			"hardware ability[%x] ras_mask[%x]\n",
 			con->hw_supported, con->supported);
-- 
2.17.1

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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 7+ messages in thread
* [PATCH 2/5] drm/amdgpu: implement umc ras init function
       [not found] ` <20190801115454.21867-1-tao.zhou1-5C7GfCeVMHo@public.gmane.org>
  2019-08-01 11:54   ` [PATCH 1/5] drm/amdgpu: support ce interrupt in ras module Tao Zhou
@ 2019-08-01 11:54   ` Tao Zhou
  2019-08-01 11:54   ` [PATCH 3/5] drm/amdgpu: update the calc algorithm of umc ecc error count Tao Zhou
                     ` (3 subsequent siblings)
  5 siblings, 0 replies; 7+ messages in thread
From: Tao Zhou @ 2019-08-01 11:54 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
	hawking.zhang-5C7GfCeVMHo, dennis.li-5C7GfCeVMHo,
	guchun.chen-5C7GfCeVMHo, xinhui.pan-5C7GfCeVMHo
  Cc: Tao Zhou

enable umc ce interrupt and initialize ecc error count

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c | 32 +++++++++++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/umc_v6_1.h |  7 ++++++
 2 files changed, 39 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
index 5747a0252624..0ab2e96b4f77 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
@@ -207,9 +207,41 @@ static void umc_v6_1_query_ras_error_address(struct amdgpu_device *adev,
 	amdgpu_umc_for_each_channel(umc_v6_1_query_error_address);
 }
 
+static void umc_v6_1_ras_init_per_channel(struct amdgpu_device *adev,
+					 struct ras_err_data *err_data,
+					 uint32_t umc_reg_offset, uint32_t channel_index)
+{
+	uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr;
+	uint32_t ecc_err_cnt_addr;
+
+	ecc_err_cnt_sel_addr =
+		SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel);
+	ecc_err_cnt_addr =
+		SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt);
+
+	/* select the lower chip and check the error count */
+	ecc_err_cnt_sel = RREG32(ecc_err_cnt_sel_addr + umc_reg_offset);
+	ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,
+					EccErrCntCsSel, 0);
+	/* set ce error interrupt type to APIC based interrupt */
+	ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,
+					EccErrInt, 0x1);
+	WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel);
+	/* set error count to initial value */
+	WREG32(ecc_err_cnt_addr + umc_reg_offset, UMC_V6_1_CE_CNT_INIT);
+
+	/* select the higher chip and check the err counter */
+	ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,
+					EccErrCntCsSel, 1);
+	WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel);
+	WREG32(ecc_err_cnt_addr + umc_reg_offset, UMC_V6_1_CE_CNT_INIT);
+}
+
 static void umc_v6_1_ras_init(struct amdgpu_device *adev)
 {
+	void *ras_error_status = NULL;
 
+	amdgpu_umc_for_each_channel(umc_v6_1_ras_init_per_channel);
 }
 
 const struct amdgpu_umc_funcs umc_v6_1_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h
index ad4598c0e495..dab9cbd292c5 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h
@@ -37,6 +37,13 @@
 /* UMC regiser per channel offset */
 #define UMC_V6_1_PER_CHANNEL_OFFSET		0x800
 
+/* EccErrCnt max value */
+#define UMC_V6_1_CE_CNT_MAX		0xffff
+/* umc ce interrupt threshold */
+#define UMC_V6_1_CE_INT_THRESHOLD	0xffff
+/* umc ce count initial value */
+#define UMC_V6_1_CE_CNT_INIT	(UMC_V6_1_CE_CNT_MAX - UMC_V6_1_CE_INT_THRESHOLD)
+
 extern const struct amdgpu_umc_funcs umc_v6_1_funcs;
 extern const uint32_t
 	umc_v6_1_channel_idx_tbl[UMC_V6_1_UMC_INSTANCE_NUM][UMC_V6_1_CHANNEL_INSTANCE_NUM];
-- 
2.17.1

_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 7+ messages in thread
* [PATCH 3/5] drm/amdgpu: update the calc algorithm of umc ecc error count
       [not found] ` <20190801115454.21867-1-tao.zhou1-5C7GfCeVMHo@public.gmane.org>
  2019-08-01 11:54   ` [PATCH 1/5] drm/amdgpu: support ce interrupt in ras module Tao Zhou
  2019-08-01 11:54   ` [PATCH 2/5] drm/amdgpu: implement umc ras init function Tao Zhou
@ 2019-08-01 11:54   ` Tao Zhou
  2019-08-01 11:54   ` [PATCH 4/5] drm/amdgpu: only uncorrectable error needs gpu reset Tao Zhou
                     ` (2 subsequent siblings)
  5 siblings, 0 replies; 7+ messages in thread
From: Tao Zhou @ 2019-08-01 11:54 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
	hawking.zhang-5C7GfCeVMHo, dennis.li-5C7GfCeVMHo,
	guchun.chen-5C7GfCeVMHo, xinhui.pan-5C7GfCeVMHo
  Cc: Tao Zhou

the initial value of ecc error count can be adjusted

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
index 0ab2e96b4f77..034b78691128 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
@@ -98,9 +98,10 @@ static void umc_v6_1_query_correctable_error_count(struct amdgpu_device *adev,
 	WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel);
 	ecc_err_cnt = RREG32(ecc_err_cnt_addr + umc_reg_offset);
 	*error_count +=
-		REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt);
+		(REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) -
+		 UMC_V6_1_CE_CNT_INIT);
 	/* clear the lower chip err count */
-	WREG32(ecc_err_cnt_addr + umc_reg_offset, 0);
+	WREG32(ecc_err_cnt_addr + umc_reg_offset, UMC_V6_1_CE_CNT_INIT);
 
 	/* select the higher chip and check the err counter */
 	ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,
@@ -108,9 +109,10 @@ static void umc_v6_1_query_correctable_error_count(struct amdgpu_device *adev,
 	WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel);
 	ecc_err_cnt = RREG32(ecc_err_cnt_addr + umc_reg_offset);
 	*error_count +=
-		REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt);
+		(REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) -
+		UMC_V6_1_CE_CNT_INIT);
 	/* clear the higher chip err count */
-	WREG32(ecc_err_cnt_addr + umc_reg_offset, 0);
+	WREG32(ecc_err_cnt_addr + umc_reg_offset, UMC_V6_1_CE_CNT_INIT);
 
 	/* check for SRAM correctable error
 	  MCUMC_STATUS is a 64 bit register */
-- 
2.17.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 7+ messages in thread
* [PATCH 4/5] drm/amdgpu: only uncorrectable error needs gpu reset
       [not found] ` <20190801115454.21867-1-tao.zhou1-5C7GfCeVMHo@public.gmane.org>
                     ` (2 preceding siblings ...)
  2019-08-01 11:54   ` [PATCH 3/5] drm/amdgpu: update the calc algorithm of umc ecc error count Tao Zhou
@ 2019-08-01 11:54   ` Tao Zhou
  2019-08-01 11:54   ` [PATCH 5/5] drm/amdgpu: replace AMDGPU_RAS_UE with AMDGPU_RAS_SUCCESS Tao Zhou
  2019-08-01 12:56   ` [PATCH 0/5] enable umc ras ce interrupt v2 Zhang, Hawking
  5 siblings, 0 replies; 7+ messages in thread
From: Tao Zhou @ 2019-08-01 11:54 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
	hawking.zhang-5C7GfCeVMHo, dennis.li-5C7GfCeVMHo,
	guchun.chen-5C7GfCeVMHo, xinhui.pan-5C7GfCeVMHo
  Cc: Tao Zhou

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 05cbd90d9b6c..b6edad8bb31c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -250,7 +250,11 @@ static int gmc_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
 	 */
 	if (adev->umc.funcs->query_ras_error_address)
 		adev->umc.funcs->query_ras_error_address(adev, err_data);
-	amdgpu_ras_reset_gpu(adev, 0);
+	
+	/* only uncorrectable error needs gpu reset */
+	if (err_data->ue_count)
+		amdgpu_ras_reset_gpu(adev, 0);
+
 	return AMDGPU_RAS_UE;
 }
 
-- 
2.17.1

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https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 7+ messages in thread
* [PATCH 5/5] drm/amdgpu: replace AMDGPU_RAS_UE with AMDGPU_RAS_SUCCESS
       [not found] ` <20190801115454.21867-1-tao.zhou1-5C7GfCeVMHo@public.gmane.org>
                     ` (3 preceding siblings ...)
  2019-08-01 11:54   ` [PATCH 4/5] drm/amdgpu: only uncorrectable error needs gpu reset Tao Zhou
@ 2019-08-01 11:54   ` Tao Zhou
  2019-08-01 12:56   ` [PATCH 0/5] enable umc ras ce interrupt v2 Zhang, Hawking
  5 siblings, 0 replies; 7+ messages in thread
From: Tao Zhou @ 2019-08-01 11:54 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
	hawking.zhang-5C7GfCeVMHo, dennis.li-5C7GfCeVMHo,
	guchun.chen-5C7GfCeVMHo, xinhui.pan-5C7GfCeVMHo
  Cc: Tao Zhou

ce can also trigger interrupt, and even both ce and ue error can be
found in one ras query, distinguishing between ce and ue in interrupt
handler is uncessary.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c   | 2 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   | 2 +-
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c  | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 4a0dc5269ddf..d2e8a85f6e38 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -1046,7 +1046,7 @@ static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
 			 * But leave IP do that recovery, here we just dispatch
 			 * the error.
 			 */
-			if (ret == AMDGPU_RAS_UE) {
+			if (ret == AMDGPU_RAS_SUCCESS) {
 				/* these counts could be left as 0 if
 				 * some blocks do not count error number
 				 */
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index bcd0301eee1e..e60920d57b8f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -5647,7 +5647,7 @@ static int gfx_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
 	if (adev->gfx.funcs->query_ras_error_count)
 		adev->gfx.funcs->query_ras_error_count(adev, err_data);
 	amdgpu_ras_reset_gpu(adev, 0);
-	return AMDGPU_RAS_UE;
+	return AMDGPU_RAS_SUCCESS;
 }
 
 static const struct {
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index b6edad8bb31c..a219bab82310 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -255,7 +255,7 @@ static int gmc_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
 	if (err_data->ue_count)
 		amdgpu_ras_reset_gpu(adev, 0);
 
-	return AMDGPU_RAS_UE;
+	return AMDGPU_RAS_SUCCESS;
 }
 
 static int gmc_v9_0_process_ecc_irq(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 2ffc9a41d8b1..7acb854a2979 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -1982,7 +1982,7 @@ static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
 
 	amdgpu_ras_reset_gpu(adev, 0);
 
-	return AMDGPU_RAS_UE;
+	return AMDGPU_RAS_SUCCESS;
 }
 
 static int sdma_v4_0_process_ecc_irq(struct amdgpu_device *adev,
-- 
2.17.1

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https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 7+ messages in thread
* RE: [PATCH 0/5] enable umc ras ce interrupt v2
       [not found] ` <20190801115454.21867-1-tao.zhou1-5C7GfCeVMHo@public.gmane.org>
                     ` (4 preceding siblings ...)
  2019-08-01 11:54   ` [PATCH 5/5] drm/amdgpu: replace AMDGPU_RAS_UE with AMDGPU_RAS_SUCCESS Tao Zhou
@ 2019-08-01 12:56   ` Zhang, Hawking
  5 siblings, 0 replies; 7+ messages in thread
From: Zhang, Hawking @ 2019-08-01 12:56 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Li, Dennis, Chen,
	Guchun, Pan, Xinhui
  Cc: Zhou1, Tao

Series is

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>

Regards,
Hawking
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Tao Zhou
Sent: 2019年8月1日 19:55
To: amd-gfx@lists.freedesktop.org; Zhang, Hawking <Hawking.Zhang@amd.com>; Li, Dennis <Dennis.Li@amd.com>; Chen, Guchun <Guchun.Chen@amd.com>; Pan, Xinhui <Xinhui.Pan@amd.com>
Cc: Zhou1, Tao <Tao.Zhou1@amd.com>
Subject: [PATCH 0/5] enable umc ras ce interrupt v2

These patches add support for umc ce interrupt, the interrupt is controlled by a error count threshold.

v2: correct typo in commit description and update comment of patch #2 add patch #5 to replace AMDGPU_RAS_UE with AMDGPU_RAS_SUCCESS

Tao Zhou (5):
  drm/amdgpu: support ce interrupt in ras module
  drm/amdgpu: implement umc ras init function
  drm/amdgpu: update the calc algorithm of umc ecc error count
  drm/amdgpu: only uncorrectable error needs gpu reset
  drm/amdgpu: replace AMDGPU_RAS_UE with AMDGPU_RAS_SUCCESS

 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 14 ++++++---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c   |  2 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   |  8 +++--
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c  |  2 +-
 drivers/gpu/drm/amd/amdgpu/umc_v6_1.c   | 42 ++++++++++++++++++++++---
 drivers/gpu/drm/amd/amdgpu/umc_v6_1.h   |  7 +++++
 6 files changed, 62 insertions(+), 13 deletions(-)

--
2.17.1

_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 7+ messages in thread
end of thread, other threads:[~2019-08-01 12:56 UTC | newest]

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2019-08-01 11:54 [PATCH 0/5] enable umc ras ce interrupt v2 Tao Zhou
     [not found] ` <20190801115454.21867-1-tao.zhou1-5C7GfCeVMHo@public.gmane.org>
2019-08-01 11:54   ` [PATCH 1/5] drm/amdgpu: support ce interrupt in ras module Tao Zhou
2019-08-01 11:54   ` [PATCH 2/5] drm/amdgpu: implement umc ras init function Tao Zhou
2019-08-01 11:54   ` [PATCH 3/5] drm/amdgpu: update the calc algorithm of umc ecc error count Tao Zhou
2019-08-01 11:54   ` [PATCH 4/5] drm/amdgpu: only uncorrectable error needs gpu reset Tao Zhou
2019-08-01 11:54   ` [PATCH 5/5] drm/amdgpu: replace AMDGPU_RAS_UE with AMDGPU_RAS_SUCCESS Tao Zhou
2019-08-01 12:56   ` [PATCH 0/5] enable umc ras ce interrupt v2 Zhang, Hawking

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