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* [PATCH 1/2] drm/i915/pmu: Atomically acquire the gt_pm wakeref
@ 2019-08-01 18:26 Chris Wilson
  2019-08-01 18:26 ` [PATCH 2/2] drm/i915/pmu: Use GT parked for estimating RC6 while asleep Chris Wilson
                   ` (2 more replies)
  0 siblings, 3 replies; 7+ messages in thread
From: Chris Wilson @ 2019-08-01 18:26 UTC (permalink / raw)
  To: intel-gfx

Currently, we only sample if the intel_gt is awake, but we acquire our
own runtime_pm wakeref. Since intel_gt has transitioned to tracking its
own wakeref, we can atomically test and acquire that wakeref instead.

v2: Take engine->wakeref for engine sampling

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt_pm.h |  8 +++++-
 drivers/gpu/drm/i915/i915_pmu.c       | 40 ++++++++++++---------------
 2 files changed, 25 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.h b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
index 527894fe1345..e8a18d4b27c9 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
@@ -9,7 +9,8 @@
 
 #include <linux/types.h>
 
-struct intel_gt;
+#include "intel_gt_types.h"
+#include "intel_wakeref.h"
 
 enum {
 	INTEL_GT_UNPARK,
@@ -19,6 +20,11 @@ enum {
 void intel_gt_pm_get(struct intel_gt *gt);
 void intel_gt_pm_put(struct intel_gt *gt);
 
+static inline bool intel_gt_pm_get_if_awake(struct intel_gt *gt)
+{
+	return intel_wakeref_get_if_active(&gt->wakeref);
+}
+
 void intel_gt_pm_init_early(struct intel_gt *gt);
 
 void intel_gt_sanitize(struct intel_gt *gt, bool force);
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index eff86483bec0..4d7cabeea687 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -8,6 +8,8 @@
 #include <linux/pm_runtime.h>
 
 #include "gt/intel_engine.h"
+#include "gt/intel_engine_pm.h"
+#include "gt/intel_gt_pm.h"
 
 #include "i915_drv.h"
 #include "i915_pmu.h"
@@ -161,27 +163,24 @@ engines_sample(struct drm_i915_private *dev_priv, unsigned int period_ns)
 {
 	struct intel_engine_cs *engine;
 	enum intel_engine_id id;
-	intel_wakeref_t wakeref;
-	unsigned long flags;
 
 	if ((dev_priv->pmu.enable & ENGINE_SAMPLE_MASK) == 0)
 		return;
 
-	wakeref = 0;
-	if (READ_ONCE(dev_priv->gt.awake))
-		wakeref = intel_runtime_pm_get_if_in_use(&dev_priv->runtime_pm);
-	if (!wakeref)
-		return;
-
-	spin_lock_irqsave(&dev_priv->uncore.lock, flags);
 	for_each_engine(engine, dev_priv, id) {
 		struct intel_engine_pmu *pmu = &engine->pmu;
+		unsigned long flags;
 		bool busy;
 		u32 val;
 
+		if (!intel_engine_pm_get_if_awake(engine))
+			continue;
+
+		spin_lock_irqsave(&dev_priv->uncore.lock, flags);
+
 		val = I915_READ_FW(RING_CTL(engine->mmio_base));
 		if (val == 0) /* powerwell off => engine idle */
-			continue;
+			goto skip;
 
 		if (val & RING_WAIT)
 			add_sample(&pmu->sample[I915_SAMPLE_WAIT], period_ns);
@@ -202,10 +201,11 @@ engines_sample(struct drm_i915_private *dev_priv, unsigned int period_ns)
 		}
 		if (busy)
 			add_sample(&pmu->sample[I915_SAMPLE_BUSY], period_ns);
-	}
-	spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
 
-	intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
+skip:
+		spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
+		intel_engine_pm_put(engine);
+	}
 }
 
 static void
@@ -222,15 +222,11 @@ frequency_sample(struct drm_i915_private *dev_priv, unsigned int period_ns)
 		u32 val;
 
 		val = dev_priv->gt_pm.rps.cur_freq;
-		if (dev_priv->gt.awake) {
-			intel_wakeref_t wakeref;
-
-			with_intel_runtime_pm_if_in_use(&dev_priv->runtime_pm,
-							wakeref) {
-				val = intel_uncore_read_notrace(&dev_priv->uncore,
-								GEN6_RPSTAT1);
-				val = intel_get_cagf(dev_priv, val);
-			}
+		if (intel_gt_pm_get_if_awake(&dev_priv->gt)) {
+			val = intel_uncore_read_notrace(&dev_priv->uncore,
+							GEN6_RPSTAT1);
+			val = intel_get_cagf(dev_priv, val);
+			intel_gt_pm_put(&dev_priv->gt);
 		}
 
 		add_sample_mult(&dev_priv->pmu.sample[__I915_SAMPLE_FREQ_ACT],
-- 
2.23.0.rc0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 7+ messages in thread

* [PATCH 2/2] drm/i915/pmu: Use GT parked for estimating RC6 while asleep
  2019-08-01 18:26 [PATCH 1/2] drm/i915/pmu: Atomically acquire the gt_pm wakeref Chris Wilson
@ 2019-08-01 18:26 ` Chris Wilson
  2019-08-01 19:16   ` Chris Wilson
  2019-08-02  8:41   ` Tvrtko Ursulin
  2019-08-01 22:57 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/pmu: Atomically acquire the gt_pm wakeref Patchwork
  2019-08-02 20:14 ` ✓ Fi.CI.IGT: " Patchwork
  2 siblings, 2 replies; 7+ messages in thread
From: Chris Wilson @ 2019-08-01 18:26 UTC (permalink / raw)
  To: intel-gfx

As we track when we put the GT device to sleep upon idling, we can use
that callback to sample the current rc6 counters and record the
timestamp for estimating samples after that point while asleep.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c |  21 ++---
 drivers/gpu/drm/i915/i915_pmu.c     | 122 ++++++++++++++--------------
 drivers/gpu/drm/i915/i915_pmu.h     |   4 +-
 3 files changed, 71 insertions(+), 76 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 24787bb48c9f..a96e630d3f86 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -39,6 +39,7 @@
 #include "display/intel_psr.h"
 
 #include "gem/i915_gem_context.h"
+#include "gt/intel_gt_pm.h"
 #include "gt/intel_reset.h"
 #include "gt/uc/intel_guc_submission.h"
 
@@ -4057,13 +4058,11 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
 static int i915_forcewake_open(struct inode *inode, struct file *file)
 {
 	struct drm_i915_private *i915 = inode->i_private;
+	struct intel_gt *gt = &i915->gt;
 
-	if (INTEL_GEN(i915) < 6)
-		return 0;
-
-	file->private_data =
-		(void *)(uintptr_t)intel_runtime_pm_get(&i915->runtime_pm);
-	intel_uncore_forcewake_user_get(&i915->uncore);
+	intel_gt_pm_get(gt);
+	if (INTEL_GEN(i915) >= 6)
+		intel_uncore_forcewake_user_get(gt->uncore);
 
 	return 0;
 }
@@ -4071,13 +4070,11 @@ static int i915_forcewake_open(struct inode *inode, struct file *file)
 static int i915_forcewake_release(struct inode *inode, struct file *file)
 {
 	struct drm_i915_private *i915 = inode->i_private;
+	struct intel_gt *gt = &i915->gt;
 
-	if (INTEL_GEN(i915) < 6)
-		return 0;
-
-	intel_uncore_forcewake_user_put(&i915->uncore);
-	intel_runtime_pm_put(&i915->runtime_pm,
-			     (intel_wakeref_t)(uintptr_t)file->private_data);
+	if (INTEL_GEN(i915) >= 6)
+		intel_uncore_forcewake_user_put(&i915->uncore);
+	intel_gt_pm_put(gt);
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 4d7cabeea687..680618bd385c 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -114,17 +114,50 @@ static bool pmu_needs_timer(struct drm_i915_private *i915, bool gpu_active)
 	return enable;
 }
 
+static u64 __get_rc6(struct intel_gt *gt)
+{
+	struct drm_i915_private *i915 = gt->i915;
+	u64 val;
+
+	val = intel_rc6_residency_ns(i915,
+				     IS_VALLEYVIEW(i915) ?
+				     VLV_GT_RENDER_RC6 :
+				     GEN6_GT_GFX_RC6);
+
+	if (HAS_RC6p(i915))
+		val += intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6p);
+
+	if (HAS_RC6pp(i915))
+		val += intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6pp);
+
+	return val;
+}
+
 void i915_pmu_gt_parked(struct drm_i915_private *i915)
 {
+	u64 val;
+
 	if (!i915->pmu.base.event_init)
 		return;
 
+	val = 0;
+	if (i915->pmu.sample[__I915_SAMPLE_RC6].cur)
+		val = __get_rc6(&i915->gt);
+
 	spin_lock_irq(&i915->pmu.lock);
+
+	if (val >= i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur) {
+		i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur = 0;
+		i915->pmu.sample[__I915_SAMPLE_RC6].cur = val;
+	}
+	i915->pmu.sleep_timestamp = jiffies;
+
 	/*
 	 * Signal sampling timer to stop if only engine events are enabled and
 	 * GPU went idle.
 	 */
 	i915->pmu.timer_enabled = pmu_needs_timer(i915, false);
+
 	spin_unlock_irq(&i915->pmu.lock);
 }
 
@@ -145,10 +178,23 @@ void i915_pmu_gt_unparked(struct drm_i915_private *i915)
 		return;
 
 	spin_lock_irq(&i915->pmu.lock);
+
 	/*
 	 * Re-enable sampling timer when GPU goes active.
 	 */
 	__i915_pmu_maybe_start_timer(i915);
+
+	/* Estimate how long we slept and accumulate that into rc6 counters */
+	if (i915->pmu.sample[__I915_SAMPLE_RC6].cur) {
+		u64 val;
+
+		val = jiffies - i915->pmu.sleep_timestamp;
+		val = jiffies_to_nsecs(val);
+		val += i915->pmu.sample[__I915_SAMPLE_RC6].cur;
+
+		i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur = val;
+	}
+
 	spin_unlock_irq(&i915->pmu.lock);
 }
 
@@ -417,36 +463,17 @@ static int i915_pmu_event_init(struct perf_event *event)
 	return 0;
 }
 
-static u64 __get_rc6(struct drm_i915_private *i915)
+static u64 get_rc6(struct intel_gt *gt)
 {
-	u64 val;
-
-	val = intel_rc6_residency_ns(i915,
-				     IS_VALLEYVIEW(i915) ?
-				     VLV_GT_RENDER_RC6 :
-				     GEN6_GT_GFX_RC6);
-
-	if (HAS_RC6p(i915))
-		val += intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6p);
-
-	if (HAS_RC6pp(i915))
-		val += intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6pp);
-
-	return val;
-}
-
-static u64 get_rc6(struct drm_i915_private *i915)
-{
-#if IS_ENABLED(CONFIG_PM)
-	struct intel_runtime_pm *rpm = &i915->runtime_pm;
-	intel_wakeref_t wakeref;
+	struct drm_i915_private *i915 = gt->i915;
 	unsigned long flags;
 	u64 val;
 
-	wakeref = intel_runtime_pm_get_if_in_use(rpm);
-	if (wakeref) {
-		val = __get_rc6(i915);
-		intel_runtime_pm_put(rpm, wakeref);
+	spin_lock_irqsave(&i915->pmu.lock, flags);
+
+	if (intel_gt_pm_get_if_awake(gt)) {
+		val = __get_rc6(gt);
+		intel_gt_pm_put(gt);
 
 		/*
 		 * If we are coming back from being runtime suspended we must
@@ -454,7 +481,6 @@ static u64 get_rc6(struct drm_i915_private *i915)
 		 * previously.
 		 */
 
-		spin_lock_irqsave(&i915->pmu.lock, flags);
 
 		if (val >= i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur) {
 			i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur = 0;
@@ -462,11 +488,7 @@ static u64 get_rc6(struct drm_i915_private *i915)
 		} else {
 			val = i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur;
 		}
-
-		spin_unlock_irqrestore(&i915->pmu.lock, flags);
 	} else {
-		struct device *kdev = rpm->kdev;
-
 		/*
 		 * We are runtime suspended.
 		 *
@@ -474,42 +496,18 @@ static u64 get_rc6(struct drm_i915_private *i915)
 		 * on top of the last known real value, as the approximated RC6
 		 * counter value.
 		 */
-		spin_lock_irqsave(&i915->pmu.lock, flags);
 
-		/*
-		 * After the above branch intel_runtime_pm_get_if_in_use failed
-		 * to get the runtime PM reference we cannot assume we are in
-		 * runtime suspend since we can either: a) race with coming out
-		 * of it before we took the power.lock, or b) there are other
-		 * states than suspended which can bring us here.
-		 *
-		 * We need to double-check that we are indeed currently runtime
-		 * suspended and if not we cannot do better than report the last
-		 * known RC6 value.
-		 */
-		if (pm_runtime_status_suspended(kdev)) {
-			val = pm_runtime_suspended_time(kdev);
+		val = jiffies - i915->pmu.sleep_timestamp;
+		val = jiffies_to_nsecs(val);
+		val += i915->pmu.sample[__I915_SAMPLE_RC6].cur;
 
-			if (!i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur)
-				i915->pmu.suspended_time_last = val;
+		i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur = val;
 
-			val -= i915->pmu.suspended_time_last;
-			val += i915->pmu.sample[__I915_SAMPLE_RC6].cur;
-
-			i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur = val;
-		} else if (i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur) {
-			val = i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur;
-		} else {
-			val = i915->pmu.sample[__I915_SAMPLE_RC6].cur;
-		}
-
-		spin_unlock_irqrestore(&i915->pmu.lock, flags);
 	}
 
+	spin_unlock_irqrestore(&i915->pmu.lock, flags);
+
 	return val;
-#else
-	return __get_rc6(i915);
-#endif
 }
 
 static u64 __i915_pmu_event_read(struct perf_event *event)
@@ -550,7 +548,7 @@ static u64 __i915_pmu_event_read(struct perf_event *event)
 			val = count_interrupts(i915);
 			break;
 		case I915_PMU_RC6_RESIDENCY:
-			val = get_rc6(i915);
+			val = get_rc6(&i915->gt);
 			break;
 		}
 	}
diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h
index 4fc4f2478301..6fa0240a1704 100644
--- a/drivers/gpu/drm/i915/i915_pmu.h
+++ b/drivers/gpu/drm/i915/i915_pmu.h
@@ -97,9 +97,9 @@ struct i915_pmu {
 	 */
 	struct i915_pmu_sample sample[__I915_NUM_PMU_SAMPLERS];
 	/**
-	 * @suspended_time_last: Cached suspend time from PM core.
+	 * @sleep_timestamp: Last time GT parked for RC6 estimation.
 	 */
-	u64 suspended_time_last;
+	unsigned long sleep_timestamp;
 	/**
 	 * @i915_attr: Memory block holding device attributes.
 	 */
-- 
2.23.0.rc0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 7+ messages in thread

* Re: [PATCH 2/2] drm/i915/pmu: Use GT parked for estimating RC6 while asleep
  2019-08-01 18:26 ` [PATCH 2/2] drm/i915/pmu: Use GT parked for estimating RC6 while asleep Chris Wilson
@ 2019-08-01 19:16   ` Chris Wilson
  2019-08-02  8:41   ` Tvrtko Ursulin
  1 sibling, 0 replies; 7+ messages in thread
From: Chris Wilson @ 2019-08-01 19:16 UTC (permalink / raw)
  To: intel-gfx

Quoting Chris Wilson (2019-08-01 19:26:57)
> As we track when we put the GT device to sleep upon idling, we can use
> that callback to sample the current rc6 counters and record the
> timestamp for estimating samples after that point while asleep.
> 

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105010
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 7+ messages in thread

* ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/pmu: Atomically acquire the gt_pm wakeref
  2019-08-01 18:26 [PATCH 1/2] drm/i915/pmu: Atomically acquire the gt_pm wakeref Chris Wilson
  2019-08-01 18:26 ` [PATCH 2/2] drm/i915/pmu: Use GT parked for estimating RC6 while asleep Chris Wilson
@ 2019-08-01 22:57 ` Patchwork
  2019-08-02 20:14 ` ✓ Fi.CI.IGT: " Patchwork
  2 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2019-08-01 22:57 UTC (permalink / raw)
  To: Chris Wilson; +Cc: intel-gfx

== Series Details ==

Series: series starting with [1/2] drm/i915/pmu: Atomically acquire the gt_pm wakeref
URL   : https://patchwork.freedesktop.org/series/64562/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6607 -> Patchwork_13842
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/

Known issues
------------

  Here are the changes found in Patchwork_13842 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@prime_vgem@basic-fence-read:
    - fi-bsw-kefka:       [PASS][1] -> [INCOMPLETE][2] ([fdo#111278])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/fi-bsw-kefka/igt@prime_vgem@basic-fence-read.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/fi-bsw-kefka/igt@prime_vgem@basic-fence-read.html
    - fi-pnv-d510:        [PASS][3] -> [INCOMPLETE][4] ([fdo#110740])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/fi-pnv-d510/igt@prime_vgem@basic-fence-read.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/fi-pnv-d510/igt@prime_vgem@basic-fence-read.html

  * igt@prime_vgem@basic-sync-default:
    - fi-bxt-j4205:       [PASS][5] -> [FAIL][6] ([fdo#111277]) +1 similar issue
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/fi-bxt-j4205/igt@prime_vgem@basic-sync-default.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/fi-bxt-j4205/igt@prime_vgem@basic-sync-default.html

  * igt@prime_vgem@basic-write:
    - fi-gdg-551:         [PASS][7] -> [FAIL][8] ([fdo#111276])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/fi-gdg-551/igt@prime_vgem@basic-write.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/fi-gdg-551/igt@prime_vgem@basic-write.html

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s4-devices:
    - fi-blb-e6850:       [INCOMPLETE][9] ([fdo#107718]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/fi-blb-e6850/igt@gem_exec_suspend@basic-s4-devices.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/fi-blb-e6850/igt@gem_exec_suspend@basic-s4-devices.html

  * igt@gem_mmap_gtt@basic-small-bo-tiledx:
    - fi-glk-dsi:         [INCOMPLETE][11] ([fdo#103359] / [k.org#198133]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/fi-glk-dsi/igt@gem_mmap_gtt@basic-small-bo-tiledx.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/fi-glk-dsi/igt@gem_mmap_gtt@basic-small-bo-tiledx.html

  * igt@i915_pm_rpm@module-reload:
    - fi-skl-6260u:       [INCOMPLETE][13] ([fdo#107807]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/fi-skl-6260u/igt@i915_pm_rpm@module-reload.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/fi-skl-6260u/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live_reset:
    - fi-icl-u3:          [INCOMPLETE][15] ([fdo#107713]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/fi-icl-u3/igt@i915_selftest@live_reset.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/fi-icl-u3/igt@i915_selftest@live_reset.html

  * igt@prime_vgem@basic-fence-mmap:
    - fi-byt-n2820:       [INCOMPLETE][17] ([fdo#102657] / [fdo#111276]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/fi-byt-n2820/igt@prime_vgem@basic-fence-mmap.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/fi-byt-n2820/igt@prime_vgem@basic-fence-mmap.html
    - fi-elk-e7500:       [INCOMPLETE][19] ([fdo#103989] / [fdo#111276]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/fi-elk-e7500/igt@prime_vgem@basic-fence-mmap.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/fi-elk-e7500/igt@prime_vgem@basic-fence-mmap.html

  
#### Warnings ####

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - fi-kbl-guc:         [SKIP][21] ([fdo#109271]) -> [FAIL][22] ([fdo#110829])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/fi-kbl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/fi-kbl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#102657]: https://bugs.freedesktop.org/show_bug.cgi?id=102657
  [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
  [fdo#103989]: https://bugs.freedesktop.org/show_bug.cgi?id=103989
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
  [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#110740]: https://bugs.freedesktop.org/show_bug.cgi?id=110740
  [fdo#110829]: https://bugs.freedesktop.org/show_bug.cgi?id=110829
  [fdo#111276]: https://bugs.freedesktop.org/show_bug.cgi?id=111276
  [fdo#111277]: https://bugs.freedesktop.org/show_bug.cgi?id=111277
  [fdo#111278]: https://bugs.freedesktop.org/show_bug.cgi?id=111278
  [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133


Participating hosts (49 -> 41)
------------------------------

  Additional (1): fi-apl-guc 
  Missing    (9): fi-kbl-soraka fi-bdw-5557u fi-byt-squawks fi-bsw-cyan fi-kbl-x1275 fi-icl-y fi-bdw-samus fi-byt-clapper fi-skl-6700k2 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6607 -> Patchwork_13842

  CI-20190529: 20190529
  CI_DRM_6607: 5c251d6325ce1f77306f3507009e95361a36f1e3 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5120: b3138fbea79d5d7935e53530b90efe3e816236f4 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13842: ad1216792a60af09d296f08a09f880ef7fed0590 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

ad1216792a60 drm/i915/pmu: Use GT parked for estimating RC6 while asleep
90a118c17012 drm/i915/pmu: Atomically acquire the gt_pm wakeref

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH 2/2] drm/i915/pmu: Use GT parked for estimating RC6 while asleep
  2019-08-01 18:26 ` [PATCH 2/2] drm/i915/pmu: Use GT parked for estimating RC6 while asleep Chris Wilson
  2019-08-01 19:16   ` Chris Wilson
@ 2019-08-02  8:41   ` Tvrtko Ursulin
  2019-08-02  8:59     ` Chris Wilson
  1 sibling, 1 reply; 7+ messages in thread
From: Tvrtko Ursulin @ 2019-08-02  8:41 UTC (permalink / raw)
  To: Chris Wilson, intel-gfx


On 01/08/2019 19:26, Chris Wilson wrote:
> As we track when we put the GT device to sleep upon idling, we can use
> that callback to sample the current rc6 counters and record the
> timestamp for estimating samples after that point while asleep.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_debugfs.c |  21 ++---
>   drivers/gpu/drm/i915/i915_pmu.c     | 122 ++++++++++++++--------------
>   drivers/gpu/drm/i915/i915_pmu.h     |   4 +-
>   3 files changed, 71 insertions(+), 76 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 24787bb48c9f..a96e630d3f86 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -39,6 +39,7 @@
>   #include "display/intel_psr.h"
>   
>   #include "gem/i915_gem_context.h"
> +#include "gt/intel_gt_pm.h"
>   #include "gt/intel_reset.h"
>   #include "gt/uc/intel_guc_submission.h"
>   
> @@ -4057,13 +4058,11 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
>   static int i915_forcewake_open(struct inode *inode, struct file *file)
>   {
>   	struct drm_i915_private *i915 = inode->i_private;
> +	struct intel_gt *gt = &i915->gt;
>   
> -	if (INTEL_GEN(i915) < 6)
> -		return 0;
> -
> -	file->private_data =
> -		(void *)(uintptr_t)intel_runtime_pm_get(&i915->runtime_pm);
> -	intel_uncore_forcewake_user_get(&i915->uncore);
> +	intel_gt_pm_get(gt);
> +	if (INTEL_GEN(i915) >= 6)
> +		intel_uncore_forcewake_user_get(gt->uncore);
>   
>   	return 0;
>   }
> @@ -4071,13 +4070,11 @@ static int i915_forcewake_open(struct inode *inode, struct file *file)
>   static int i915_forcewake_release(struct inode *inode, struct file *file)
>   {
>   	struct drm_i915_private *i915 = inode->i_private;
> +	struct intel_gt *gt = &i915->gt;
>   
> -	if (INTEL_GEN(i915) < 6)
> -		return 0;
> -
> -	intel_uncore_forcewake_user_put(&i915->uncore);
> -	intel_runtime_pm_put(&i915->runtime_pm,
> -			     (intel_wakeref_t)(uintptr_t)file->private_data);
> +	if (INTEL_GEN(i915) >= 6)
> +		intel_uncore_forcewake_user_put(&i915->uncore);
> +	intel_gt_pm_put(gt);
>   
>   	return 0;
>   }
> diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
> index 4d7cabeea687..680618bd385c 100644
> --- a/drivers/gpu/drm/i915/i915_pmu.c
> +++ b/drivers/gpu/drm/i915/i915_pmu.c
> @@ -114,17 +114,50 @@ static bool pmu_needs_timer(struct drm_i915_private *i915, bool gpu_active)
>   	return enable;
>   }
>   
> +static u64 __get_rc6(struct intel_gt *gt)
> +{
> +	struct drm_i915_private *i915 = gt->i915;
> +	u64 val;
> +
> +	val = intel_rc6_residency_ns(i915,
> +				     IS_VALLEYVIEW(i915) ?
> +				     VLV_GT_RENDER_RC6 :
> +				     GEN6_GT_GFX_RC6);
> +
> +	if (HAS_RC6p(i915))
> +		val += intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6p);
> +
> +	if (HAS_RC6pp(i915))
> +		val += intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6pp);
> +
> +	return val;
> +}
> +
>   void i915_pmu_gt_parked(struct drm_i915_private *i915)
>   {
> +	u64 val;
> +
>   	if (!i915->pmu.base.event_init)
>   		return;
>   
> +	val = 0;
> +	if (i915->pmu.sample[__I915_SAMPLE_RC6].cur)
> +		val = __get_rc6(&i915->gt);

The conditional could be racy outside the lock. If a parallel perf 
reader updates .cur from zero to non-zero the house keep below would see 
val as zero. Perhaps you can store val = __get_rc6 outside the lock, and 
then decide which val to use inside the lock?

> +
>   	spin_lock_irq(&i915->pmu.lock);
> +
> +	if (val >= i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur) {
> +		i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur = 0;
> +		i915->pmu.sample[__I915_SAMPLE_RC6].cur = val;
> +	}
> +	i915->pmu.sleep_timestamp = jiffies;

ktime would be better I think. More precision but just why use archaic 
jiffies.

> +
>   	/*
>   	 * Signal sampling timer to stop if only engine events are enabled and
>   	 * GPU went idle.
>   	 */
>   	i915->pmu.timer_enabled = pmu_needs_timer(i915, false);
> +
>   	spin_unlock_irq(&i915->pmu.lock);
>   }
>   
> @@ -145,10 +178,23 @@ void i915_pmu_gt_unparked(struct drm_i915_private *i915)
>   		return;
>   
>   	spin_lock_irq(&i915->pmu.lock);
> +
>   	/*
>   	 * Re-enable sampling timer when GPU goes active.
>   	 */
>   	__i915_pmu_maybe_start_timer(i915);
> +
> +	/* Estimate how long we slept and accumulate that into rc6 counters */
> +	if (i915->pmu.sample[__I915_SAMPLE_RC6].cur) {
> +		u64 val;
> +
> +		val = jiffies - i915->pmu.sleep_timestamp;
> +		val = jiffies_to_nsecs(val);
> +		val += i915->pmu.sample[__I915_SAMPLE_RC6].cur;
> +
> +		i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur = val;
> +	}
> +
>   	spin_unlock_irq(&i915->pmu.lock);
>   }
>   
> @@ -417,36 +463,17 @@ static int i915_pmu_event_init(struct perf_event *event)
>   	return 0;
>   }
>   
> -static u64 __get_rc6(struct drm_i915_private *i915)
> +static u64 get_rc6(struct intel_gt *gt)
>   {
> -	u64 val;
> -
> -	val = intel_rc6_residency_ns(i915,
> -				     IS_VALLEYVIEW(i915) ?
> -				     VLV_GT_RENDER_RC6 :
> -				     GEN6_GT_GFX_RC6);
> -
> -	if (HAS_RC6p(i915))
> -		val += intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6p);
> -
> -	if (HAS_RC6pp(i915))
> -		val += intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6pp);
> -
> -	return val;
> -}
> -
> -static u64 get_rc6(struct drm_i915_private *i915)
> -{
> -#if IS_ENABLED(CONFIG_PM)

We still end up with never getting into estimation mode, even when 
parked, right? Hm.. why I added this.. never mind.

> -	struct intel_runtime_pm *rpm = &i915->runtime_pm;
> -	intel_wakeref_t wakeref;
> +	struct drm_i915_private *i915 = gt->i915;
>   	unsigned long flags;
>   	u64 val;
>   
> -	wakeref = intel_runtime_pm_get_if_in_use(rpm);
> -	if (wakeref) {
> -		val = __get_rc6(i915);
> -		intel_runtime_pm_put(rpm, wakeref);
> +	spin_lock_irqsave(&i915->pmu.lock, flags);
> +
> +	if (intel_gt_pm_get_if_awake(gt)) {
> +		val = __get_rc6(gt);

I thought earlier in the patch you were avoiding to call __get_rc6 under 
the irq off lock. It looks to be safe, unless I am missing yet another 
nasty cpu hotplug lock interaction, but it would be good to be consistent.

> +		intel_gt_pm_put(gt);
>   
>   		/*
>   		 * If we are coming back from being runtime suspended we must
> @@ -454,7 +481,6 @@ static u64 get_rc6(struct drm_i915_private *i915)
>   		 * previously.
>   		 */
>   
> -		spin_lock_irqsave(&i915->pmu.lock, flags);
>   
>   		if (val >= i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur) {
>   			i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur = 0;
> @@ -462,11 +488,7 @@ static u64 get_rc6(struct drm_i915_private *i915)
>   		} else {
>   			val = i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur;
>   		}
> -
> -		spin_unlock_irqrestore(&i915->pmu.lock, flags);
>   	} else {
> -		struct device *kdev = rpm->kdev;
> -
>   		/*
>   		 * We are runtime suspended.
>   		 *
> @@ -474,42 +496,18 @@ static u64 get_rc6(struct drm_i915_private *i915)
>   		 * on top of the last known real value, as the approximated RC6
>   		 * counter value.
>   		 */
> -		spin_lock_irqsave(&i915->pmu.lock, flags);
>   
> -		/*
> -		 * After the above branch intel_runtime_pm_get_if_in_use failed
> -		 * to get the runtime PM reference we cannot assume we are in
> -		 * runtime suspend since we can either: a) race with coming out
> -		 * of it before we took the power.lock, or b) there are other
> -		 * states than suspended which can bring us here.
> -		 *
> -		 * We need to double-check that we are indeed currently runtime
> -		 * suspended and if not we cannot do better than report the last
> -		 * known RC6 value.
> -		 */

You think this race is not a concern any more? The issue of inconsistent 
state in core isn't any more since 2924bdee21edd, although I am not sure 
if 3b4ed2e2eb558 broke it. Presumably not since I reviewed it back then. 
But if we got woken up by now reader will see too much rc6 sleep. I 
guess it's noise level. Can't imagine even IGT would be so sensitive to 
get affected by it.

> -		if (pm_runtime_status_suspended(kdev)) {
> -			val = pm_runtime_suspended_time(kdev);
> +		val = jiffies - i915->pmu.sleep_timestamp;
> +		val = jiffies_to_nsecs(val);
> +		val += i915->pmu.sample[__I915_SAMPLE_RC6].cur;
>   
> -			if (!i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur)
> -				i915->pmu.suspended_time_last = val;
> +		i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur = val;
>   
> -			val -= i915->pmu.suspended_time_last;
> -			val += i915->pmu.sample[__I915_SAMPLE_RC6].cur;
> -
> -			i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur = val;
> -		} else if (i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur) {
> -			val = i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur;
> -		} else {
> -			val = i915->pmu.sample[__I915_SAMPLE_RC6].cur;
> -		}
> -
> -		spin_unlock_irqrestore(&i915->pmu.lock, flags);
>   	}
>   
> +	spin_unlock_irqrestore(&i915->pmu.lock, flags);
> +
>   	return val;
> -#else
> -	return __get_rc6(i915);
> -#endif
>   }
>   
>   static u64 __i915_pmu_event_read(struct perf_event *event)
> @@ -550,7 +548,7 @@ static u64 __i915_pmu_event_read(struct perf_event *event)
>   			val = count_interrupts(i915);
>   			break;
>   		case I915_PMU_RC6_RESIDENCY:
> -			val = get_rc6(i915);
> +			val = get_rc6(&i915->gt);
>   			break;
>   		}
>   	}
> diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h
> index 4fc4f2478301..6fa0240a1704 100644
> --- a/drivers/gpu/drm/i915/i915_pmu.h
> +++ b/drivers/gpu/drm/i915/i915_pmu.h
> @@ -97,9 +97,9 @@ struct i915_pmu {
>   	 */
>   	struct i915_pmu_sample sample[__I915_NUM_PMU_SAMPLERS];
>   	/**
> -	 * @suspended_time_last: Cached suspend time from PM core.
> +	 * @sleep_timestamp: Last time GT parked for RC6 estimation.
>   	 */
> -	u64 suspended_time_last;
> +	unsigned long sleep_timestamp;
>   	/**
>   	 * @i915_attr: Memory block holding device attributes.
>   	 */
> 

Yeah I like it. Much better that we stay within confines of our own 
code. I wonder what it will mean if this fixes the occasional IGT fails. 
That something in core rpm subsystem accounting was going wrong?

Regards,

Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH 2/2] drm/i915/pmu: Use GT parked for estimating RC6 while asleep
  2019-08-02  8:41   ` Tvrtko Ursulin
@ 2019-08-02  8:59     ` Chris Wilson
  0 siblings, 0 replies; 7+ messages in thread
From: Chris Wilson @ 2019-08-02  8:59 UTC (permalink / raw)
  To: Tvrtko Ursulin, intel-gfx

Quoting Tvrtko Ursulin (2019-08-02 09:41:26)
> 
> On 01/08/2019 19:26, Chris Wilson wrote:
> > As we track when we put the GT device to sleep upon idling, we can use
> > that callback to sample the current rc6 counters and record the
> > timestamp for estimating samples after that point while asleep.
> > 
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > ---
> >   drivers/gpu/drm/i915/i915_debugfs.c |  21 ++---
> >   drivers/gpu/drm/i915/i915_pmu.c     | 122 ++++++++++++++--------------
> >   drivers/gpu/drm/i915/i915_pmu.h     |   4 +-
> >   3 files changed, 71 insertions(+), 76 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > index 24787bb48c9f..a96e630d3f86 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -39,6 +39,7 @@
> >   #include "display/intel_psr.h"
> >   
> >   #include "gem/i915_gem_context.h"
> > +#include "gt/intel_gt_pm.h"
> >   #include "gt/intel_reset.h"
> >   #include "gt/uc/intel_guc_submission.h"
> >   
> > @@ -4057,13 +4058,11 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
> >   static int i915_forcewake_open(struct inode *inode, struct file *file)
> >   {
> >       struct drm_i915_private *i915 = inode->i_private;
> > +     struct intel_gt *gt = &i915->gt;
> >   
> > -     if (INTEL_GEN(i915) < 6)
> > -             return 0;
> > -
> > -     file->private_data =
> > -             (void *)(uintptr_t)intel_runtime_pm_get(&i915->runtime_pm);
> > -     intel_uncore_forcewake_user_get(&i915->uncore);
> > +     intel_gt_pm_get(gt);
> > +     if (INTEL_GEN(i915) >= 6)
> > +             intel_uncore_forcewake_user_get(gt->uncore);
> >   
> >       return 0;
> >   }
> > @@ -4071,13 +4070,11 @@ static int i915_forcewake_open(struct inode *inode, struct file *file)
> >   static int i915_forcewake_release(struct inode *inode, struct file *file)
> >   {
> >       struct drm_i915_private *i915 = inode->i_private;
> > +     struct intel_gt *gt = &i915->gt;
> >   
> > -     if (INTEL_GEN(i915) < 6)
> > -             return 0;
> > -
> > -     intel_uncore_forcewake_user_put(&i915->uncore);
> > -     intel_runtime_pm_put(&i915->runtime_pm,
> > -                          (intel_wakeref_t)(uintptr_t)file->private_data);
> > +     if (INTEL_GEN(i915) >= 6)
> > +             intel_uncore_forcewake_user_put(&i915->uncore);
> > +     intel_gt_pm_put(gt);
> >   
> >       return 0;
> >   }
> > diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
> > index 4d7cabeea687..680618bd385c 100644
> > --- a/drivers/gpu/drm/i915/i915_pmu.c
> > +++ b/drivers/gpu/drm/i915/i915_pmu.c
> > @@ -114,17 +114,50 @@ static bool pmu_needs_timer(struct drm_i915_private *i915, bool gpu_active)
> >       return enable;
> >   }
> >   
> > +static u64 __get_rc6(struct intel_gt *gt)
> > +{
> > +     struct drm_i915_private *i915 = gt->i915;
> > +     u64 val;
> > +
> > +     val = intel_rc6_residency_ns(i915,
> > +                                  IS_VALLEYVIEW(i915) ?
> > +                                  VLV_GT_RENDER_RC6 :
> > +                                  GEN6_GT_GFX_RC6);
> > +
> > +     if (HAS_RC6p(i915))
> > +             val += intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6p);
> > +
> > +     if (HAS_RC6pp(i915))
> > +             val += intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6pp);
> > +
> > +     return val;
> > +}
> > +
> >   void i915_pmu_gt_parked(struct drm_i915_private *i915)
> >   {
> > +     u64 val;
> > +
> >       if (!i915->pmu.base.event_init)
> >               return;
> >   
> > +     val = 0;
> > +     if (i915->pmu.sample[__I915_SAMPLE_RC6].cur)
> > +             val = __get_rc6(&i915->gt);
> 
> The conditional could be racy outside the lock. If a parallel perf 
> reader updates .cur from zero to non-zero the house keep below would see 
> val as zero. Perhaps you can store val = __get_rc6 outside the lock, and 
> then decide which val to use inside the lock?

I don't think it matters tbh if we regard the pmu as being off and it is
switched on as we park as it doesn't affect the estimation.

It's inside the lock on one branch, so no real excuse not to do so here.

> >       spin_lock_irq(&i915->pmu.lock);
> > +
> > +     if (val >= i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur) {
> > +             i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur = 0;
> > +             i915->pmu.sample[__I915_SAMPLE_RC6].cur = val;
> > +     }
> > +     i915->pmu.sleep_timestamp = jiffies;
> 
> ktime would be better I think. More precision but just why use archaic 
> jiffies.

It's only a coarse estimate, but your wish is my command :-)

> > -static u64 get_rc6(struct drm_i915_private *i915)
> > -{
> > -#if IS_ENABLED(CONFIG_PM)
> 
> We still end up with never getting into estimation mode, even when 
> parked, right? Hm.. why I added this.. never mind.

As we were using pm_runtime, we depended upon its structs.

> > -     struct intel_runtime_pm *rpm = &i915->runtime_pm;
> > -     intel_wakeref_t wakeref;
> > +     struct drm_i915_private *i915 = gt->i915;
> >       unsigned long flags;
> >       u64 val;
> >   
> > -     wakeref = intel_runtime_pm_get_if_in_use(rpm);
> > -     if (wakeref) {
> > -             val = __get_rc6(i915);
> > -             intel_runtime_pm_put(rpm, wakeref);
> > +     spin_lock_irqsave(&i915->pmu.lock, flags);
> > +
> > +     if (intel_gt_pm_get_if_awake(gt)) {
> > +             val = __get_rc6(gt);
> 
> I thought earlier in the patch you were avoiding to call __get_rc6 under 
> the irq off lock. It looks to be safe, unless I am missing yet another 
> nasty cpu hotplug lock interaction, but it would be good to be consistent.

It's slow, that's all I'm worrying about. Think byt/bsw where it's not
just a register read but a round-trip to the PCU. I suggest not looking
at intel_sideband and especially not the w/a for the pcu!

> > +             intel_gt_pm_put(gt);
> >   
> >               /*
> >                * If we are coming back from being runtime suspended we must
> > @@ -454,7 +481,6 @@ static u64 get_rc6(struct drm_i915_private *i915)
> >                * previously.
> >                */
> >   
> > -             spin_lock_irqsave(&i915->pmu.lock, flags);
> >   
> >               if (val >= i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur) {
> >                       i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur = 0;
> > @@ -462,11 +488,7 @@ static u64 get_rc6(struct drm_i915_private *i915)
> >               } else {
> >                       val = i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur;
> >               }
> > -
> > -             spin_unlock_irqrestore(&i915->pmu.lock, flags);
> >       } else {
> > -             struct device *kdev = rpm->kdev;
> > -
> >               /*
> >                * We are runtime suspended.
> >                *
> > @@ -474,42 +496,18 @@ static u64 get_rc6(struct drm_i915_private *i915)
> >                * on top of the last known real value, as the approximated RC6
> >                * counter value.
> >                */
> > -             spin_lock_irqsave(&i915->pmu.lock, flags);
> >   
> > -             /*
> > -              * After the above branch intel_runtime_pm_get_if_in_use failed
> > -              * to get the runtime PM reference we cannot assume we are in
> > -              * runtime suspend since we can either: a) race with coming out
> > -              * of it before we took the power.lock, or b) there are other
> > -              * states than suspended which can bring us here.
> > -              *
> > -              * We need to double-check that we are indeed currently runtime
> > -              * suspended and if not we cannot do better than report the last
> > -              * known RC6 value.
> > -              */
> 
> You think this race is not a concern any more? The issue of inconsistent 
> state in core isn't any more since 2924bdee21edd, although I am not sure 
> if 3b4ed2e2eb558 broke it. Presumably not since I reviewed it back then. 
> But if we got woken up by now reader will see too much rc6 sleep. I 
> guess it's noise level. Can't imagine even IGT would be so sensitive to 
> get affected by it.

No, by using our own metrics we don't touch pm_runtime at all or subject
to its whims. Our locking with own parking we can make solid.

> > diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h
> > index 4fc4f2478301..6fa0240a1704 100644
> > --- a/drivers/gpu/drm/i915/i915_pmu.h
> > +++ b/drivers/gpu/drm/i915/i915_pmu.h
> > @@ -97,9 +97,9 @@ struct i915_pmu {
> >        */
> >       struct i915_pmu_sample sample[__I915_NUM_PMU_SAMPLERS];
> >       /**
> > -      * @suspended_time_last: Cached suspend time from PM core.
> > +      * @sleep_timestamp: Last time GT parked for RC6 estimation.
> >        */
> > -     u64 suspended_time_last;
> > +     unsigned long sleep_timestamp;
> >       /**
> >        * @i915_attr: Memory block holding device attributes.
> >        */
> > 
> 
> Yeah I like it. Much better that we stay within confines of our own 
> code. I wonder what it will mean if this fixes the occasional IGT fails. 
> That something in core rpm subsystem accounting was going wrong?

The errors are small and quite sporadic, so could just be something as
simple as a partial wakeup attempt fudging the timings?
-Chris
_______________________________________________
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^ permalink raw reply	[flat|nested] 7+ messages in thread

* ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/pmu: Atomically acquire the gt_pm wakeref
  2019-08-01 18:26 [PATCH 1/2] drm/i915/pmu: Atomically acquire the gt_pm wakeref Chris Wilson
  2019-08-01 18:26 ` [PATCH 2/2] drm/i915/pmu: Use GT parked for estimating RC6 while asleep Chris Wilson
  2019-08-01 22:57 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/pmu: Atomically acquire the gt_pm wakeref Patchwork
@ 2019-08-02 20:14 ` Patchwork
  2 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2019-08-02 20:14 UTC (permalink / raw)
  To: Chris Wilson; +Cc: intel-gfx

== Series Details ==

Series: series starting with [1/2] drm/i915/pmu: Atomically acquire the gt_pm wakeref
URL   : https://patchwork.freedesktop.org/series/64562/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6607_full -> Patchwork_13842_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_13842_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_isolation@bcs0-s3:
    - shard-skl:          [PASS][1] -> [INCOMPLETE][2] ([fdo#104108])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/shard-skl8/igt@gem_ctx_isolation@bcs0-s3.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/shard-skl6/igt@gem_ctx_isolation@bcs0-s3.html

  * igt@i915_suspend@forcewake:
    - shard-iclb:         [PASS][3] -> [INCOMPLETE][4] ([fdo#107713])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/shard-iclb6/igt@i915_suspend@forcewake.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/shard-iclb8/igt@i915_suspend@forcewake.html
    - shard-hsw:          [PASS][5] -> [INCOMPLETE][6] ([fdo#103540])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/shard-hsw1/igt@i915_suspend@forcewake.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/shard-hsw4/igt@i915_suspend@forcewake.html
    - shard-glk:          [PASS][7] -> [INCOMPLETE][8] ([fdo#103359] / [k.org#198133])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/shard-glk6/igt@i915_suspend@forcewake.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/shard-glk7/igt@i915_suspend@forcewake.html
    - shard-apl:          [PASS][9] -> [INCOMPLETE][10] ([fdo#103927])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/shard-apl7/igt@i915_suspend@forcewake.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/shard-apl2/igt@i915_suspend@forcewake.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-apl:          [PASS][11] -> [DMESG-WARN][12] ([fdo#108566]) +4 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/shard-apl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/shard-apl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-glk:          [PASS][13] -> [FAIL][14] ([fdo#105363])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/shard-glk2/igt@kms_flip@flip-vs-expired-vblank.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/shard-glk2/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt:
    - shard-iclb:         [PASS][15] -> [FAIL][16] ([fdo#103167]) +2 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
    - shard-skl:          [PASS][17] -> [FAIL][18] ([fdo#108145])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html

  * igt@kms_plane_lowres@pipe-a-tiling-y:
    - shard-iclb:         [PASS][19] -> [FAIL][20] ([fdo#103166])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-y.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/shard-iclb8/igt@kms_plane_lowres@pipe-a-tiling-y.html

  * igt@kms_psr@psr2_cursor_mmap_cpu:
    - shard-iclb:         [PASS][21] -> [SKIP][22] ([fdo#109441]) +2 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/shard-iclb6/igt@kms_psr@psr2_cursor_mmap_cpu.html

  * igt@kms_setmode@basic:
    - shard-apl:          [PASS][23] -> [FAIL][24] ([fdo#99912])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/shard-apl4/igt@kms_setmode@basic.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/shard-apl8/igt@kms_setmode@basic.html

  * igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend:
    - shard-kbl:          [PASS][25] -> [INCOMPLETE][26] ([fdo#103665])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/shard-kbl4/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/shard-kbl2/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html

  * igt@perf@blocking:
    - shard-skl:          [PASS][27] -> [FAIL][28] ([fdo#110728]) +1 similar issue
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/shard-skl3/igt@perf@blocking.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/shard-skl2/igt@perf@blocking.html

  * igt@prime_vgem@basic-sync-default:
    - shard-apl:          [PASS][29] -> [FAIL][30] ([fdo#111277])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/shard-apl4/igt@prime_vgem@basic-sync-default.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/shard-apl5/igt@prime_vgem@basic-sync-default.html

  * igt@prime_vgem@sync-render:
    - shard-apl:          [PASS][31] -> [FAIL][32] ([fdo#111276])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/shard-apl6/igt@prime_vgem@sync-render.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/shard-apl4/igt@prime_vgem@sync-render.html

  
#### Possible fixes ####

  * igt@gem_eio@in-flight-contexts-immediate:
    - shard-skl:          [DMESG-WARN][33] -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/shard-skl3/igt@gem_eio@in-flight-contexts-immediate.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/shard-skl2/igt@gem_eio@in-flight-contexts-immediate.html

  * igt@gem_softpin@noreloc-s3:
    - shard-apl:          [DMESG-WARN][35] ([fdo#108566]) -> [PASS][36] +1 similar issue
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/shard-apl6/igt@gem_softpin@noreloc-s3.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/shard-apl4/igt@gem_softpin@noreloc-s3.html

  * igt@i915_pm_rpm@i2c:
    - shard-hsw:          [FAIL][37] ([fdo#104097]) -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/shard-hsw2/igt@i915_pm_rpm@i2c.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/shard-hsw4/igt@i915_pm_rpm@i2c.html

  * igt@i915_pm_rpm@modeset-non-lpsp-stress:
    - shard-kbl:          [DMESG-WARN][39] ([fdo#103313] / [fdo#105345]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/shard-kbl2/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/shard-kbl6/igt@i915_pm_rpm@modeset-non-lpsp-stress.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-skl:          [INCOMPLETE][41] ([fdo#110741]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/shard-skl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/shard-skl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
    - shard-hsw:          [FAIL][43] ([fdo#105767]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/shard-hsw8/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/shard-hsw2/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-skl:          [FAIL][45] ([fdo#105363]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/shard-skl2/igt@kms_flip@flip-vs-expired-vblank.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/shard-skl8/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-kbl:          [DMESG-WARN][47] ([fdo#108566]) -> [PASS][48] +1 similar issue
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite:
    - shard-iclb:         [FAIL][49] ([fdo#103167]) -> [PASS][50] +3 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite.html

  * igt@kms_psr@psr2_cursor_render:
    - shard-iclb:         [SKIP][51] ([fdo#109441]) -> [PASS][52] +1 similar issue
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/shard-iclb4/igt@kms_psr@psr2_cursor_render.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/shard-iclb2/igt@kms_psr@psr2_cursor_render.html

  * igt@perf_pmu@rc6:
    - shard-kbl:          [SKIP][53] ([fdo#109271]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/shard-kbl1/igt@perf_pmu@rc6.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/shard-kbl2/igt@perf_pmu@rc6.html

  * igt@prime_vgem@basic-wait-default:
    - shard-apl:          [FAIL][55] ([fdo#111277]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/shard-apl3/igt@prime_vgem@basic-wait-default.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/shard-apl1/igt@prime_vgem@basic-wait-default.html

  
#### Warnings ####

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-pgflip-blt:
    - shard-skl:          [FAIL][57] ([fdo#108040]) -> [FAIL][58] ([fdo#103167])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/shard-skl9/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-pgflip-blt.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/shard-skl3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt:
    - shard-skl:          [FAIL][59] ([fdo#103167]) -> [FAIL][60] ([fdo#108040])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6607/shard-skl9/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/shard-skl3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt.html

  
  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103313]: https://bugs.freedesktop.org/show_bug.cgi?id=103313
  [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
  [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
  [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#104097]: https://bugs.freedesktop.org/show_bug.cgi?id=104097
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#105345]: https://bugs.freedesktop.org/show_bug.cgi?id=105345
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#105767]: https://bugs.freedesktop.org/show_bug.cgi?id=105767
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#108040]: https://bugs.freedesktop.org/show_bug.cgi?id=108040
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
  [fdo#110741]: https://bugs.freedesktop.org/show_bug.cgi?id=110741
  [fdo#111276]: https://bugs.freedesktop.org/show_bug.cgi?id=111276
  [fdo#111277]: https://bugs.freedesktop.org/show_bug.cgi?id=111277
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
  [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6607 -> Patchwork_13842

  CI-20190529: 20190529
  CI_DRM_6607: 5c251d6325ce1f77306f3507009e95361a36f1e3 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5120: b3138fbea79d5d7935e53530b90efe3e816236f4 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13842: ad1216792a60af09d296f08a09f880ef7fed0590 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13842/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 7+ messages in thread

end of thread, other threads:[~2019-08-02 20:14 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-08-01 18:26 [PATCH 1/2] drm/i915/pmu: Atomically acquire the gt_pm wakeref Chris Wilson
2019-08-01 18:26 ` [PATCH 2/2] drm/i915/pmu: Use GT parked for estimating RC6 while asleep Chris Wilson
2019-08-01 19:16   ` Chris Wilson
2019-08-02  8:41   ` Tvrtko Ursulin
2019-08-02  8:59     ` Chris Wilson
2019-08-01 22:57 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/pmu: Atomically acquire the gt_pm wakeref Patchwork
2019-08-02 20:14 ` ✓ Fi.CI.IGT: " Patchwork

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