* [PATCH 00/36] DC Patches 19 Aug 2019
@ 2019-08-19 14:34 Bhawanpreet Lakha
[not found] ` <20190819143515.21653-1-Bhawanpreet.Lakha-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 37+ messages in thread
From: Bhawanpreet Lakha @ 2019-08-19 14:34 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Bhawanpreet Lakha
Summary Of Changes
*ODM fixes
*Gamma logging
*DSC fixes
Ahmad Othman (1):
drm/amd/display: Refactoring VTEM
Anthony Koo (2):
drm/amd/display: 3.2.47
drm/amd/display: 3.2.48
Bayan Zabihiyan (2):
drm/amd/display: add Cursor Degamma logic for DCN2
drm/amd/display: Expose OTG_V_TOTAL_MID for HW Diags
Charlene Liu (2):
drm/amd/display: support spdif
drm/amd/display: set av_mute in hw_init for HDMI
David Francis (1):
drm/amd/display: MST topology debugfs
Derek Lai (1):
drm/amd/display: Use res_cap to acquire i2c instead of pipe count
Dmytro Laktyushkin (6):
drm/amd/display: re structure odm to allow 4 to 1 support
drm/amd/display: fix dp stream enable
drm/amd/display: fix odm pipe copy
drm/amd/display: fix dcn20 odm dpp programming
drm/amd/display: fix odm stream release
drm/amd/display: fix odm validation
Ilya Bakoulin (1):
drm/amd/display: set Hratio and VRatio in dml
Jaehyun Chung (2):
drm/amd/display: Add VM page fault handle implementation
drm/amd/display: Enable HW rotation
Joseph Gravenor (1):
drm/amd/display: Implement voltage limitation stub
Joshua Aberback (1):
drm/amd/display: Properly read LVTMA_PWRSEQ_CNTL
Josip Pavic (1):
drm/amd/display: load iram for abm 2.3
Julian Parkin (1):
drm/amd/display: Delete dead code in command_table_helper
Jun Lei (2):
drm/amd/display: fix DML not calculating delivery time
drm/amd/display: revert wait in pipelock
Martin Leung (1):
drm/amd/display: cleaned up coding error in init_hw
Nikola Cornij (2):
drm/amd/display: Zero-out dsc init regs
drm/amd/display: Fix number of slices not being checked for dsc
Qingqing Zhuo (2):
drm/amd/display: refactor Device ID for external chips
drm/amd/display: remove unused function
Su Sung Chung (1):
drm/amd/display: fix audio endpoint not getting disabled issue
Wyatt Wood (2):
drm/amd/display: add null checks before logging
drm/amd/display: Add Logging for Gamma Related information
Yogesh Mohan Marimuthu (1):
drm/amd/display: fix trigger not generated for freesync
Zi Yu Liao (2):
drm/amd/display: fix MPO HUBP underflow with Scatter Gather
drm/amd/display: fix stuck test pattern on right half of display
hersen wu (1):
drm/amd/display: flicking observed while installing driver on Navi10
CF
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 24 ++
.../bios/dce110/command_table_helper_dce110.c | 36 +--
.../dce112/command_table_helper2_dce112.c | 36 +--
.../bios/dce112/command_table_helper_dce112.c | 36 +--
.../gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 10 +-
drivers/gpu/drm/amd/display/dc/core/dc.c | 27 +-
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 +-
.../gpu/drm/amd/display/dc/core/dc_link_ddc.c | 2 +-
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 56 ++--
.../drm/amd/display/dc/core/dc_link_hwss.c | 40 +--
.../gpu/drm/amd/display/dc/core/dc_resource.c | 231 ++++++---------
drivers/gpu/drm/amd/display/dc/dc.h | 3 +-
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 5 +-
.../gpu/drm/amd/display/dc/dce/dce_audio.c | 4 +-
.../gpu/drm/amd/display/dc/dce/dce_hwseq.h | 43 ++-
.../gpu/drm/amd/display/dc/dce/dce_i2c_hw.c | 3 +-
.../display/dc/dce110/dce110_hw_sequencer.c | 50 ++--
.../display/dc/dce110/dce110_hw_sequencer.h | 4 +-
.../gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 16 +-
.../gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 2 +-
.../drm/amd/display/dc/dcn10/dcn10_hubbub.h | 6 +-
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 149 ++++++----
.../amd/display/dc/dcn10/dcn10_link_encoder.c | 23 ++
.../amd/display/dc/dcn10/dcn10_link_encoder.h | 2 +
.../gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 15 +
.../gpu/drm/amd/display/dc/dcn10/dcn10_optc.h | 8 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c | 10 +-
.../gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h | 2 +-
.../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 4 +-
.../drm/amd/display/dc/dcn20/dcn20_hubbub.c | 5 +
.../drm/amd/display/dc/dcn20/dcn20_hubbub.h | 9 +-
.../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 18 +-
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c | 140 +++++----
.../drm/amd/display/dc/dcn20/dcn20_hwseq.h | 2 +-
.../amd/display/dc/dcn20/dcn20_link_encoder.c | 1 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_opp.c | 1 -
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 268 ++++++++++-------
.../display/dc/dcn20/dcn20_stream_encoder.c | 2 +-
.../dc/dml/dcn20/display_mode_vba_20v2.c | 27 ++
.../drm/amd/display/dc/dml/display_mode_vba.c | 4 +
.../gpu/drm/amd/display/dc/inc/core_types.h | 9 +-
.../gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 2 +
drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h | 2 +-
.../drm/amd/display/dc/inc/hw/link_encoder.h | 2 +
drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 5 -
.../amd/display/dc/inc/hw/stream_encoder.h | 2 +-
.../amd/display/dc/inc/hw/timing_generator.h | 2 +
.../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 8 +-
drivers/gpu/drm/amd/display/dc/inc/resource.h | 3 -
.../amd/display/include/ddc_service_types.h | 10 +-
.../amd/display/modules/color/color_gamma.c | 4 +-
.../amd/display/modules/freesync/freesync.c | 276 ++++--------------
.../amd/display/modules/inc/mod_freesync.h | 2 +
.../amd/display/modules/inc/mod_info_packet.h | 2 +-
.../display/modules/info_packet/info_packet.c | 88 ++++++
.../amd/display/modules/power/power_helpers.c | 121 +++++++-
56 files changed, 1045 insertions(+), 821 deletions(-)
--
2.17.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 01/36] drm/amd/display: re structure odm to allow 4 to 1 support
[not found] ` <20190819143515.21653-1-Bhawanpreet.Lakha-5C7GfCeVMHo@public.gmane.org>
@ 2019-08-19 14:34 ` Bhawanpreet Lakha
2019-08-19 14:34 ` [PATCH 02/36] drm/amd/display: Delete dead code in command_table_helper Bhawanpreet Lakha
` (34 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Bhawanpreet Lakha @ 2019-08-19 14:34 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Dmytro Laktyushkin
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Currently odm is handled using top_bottom pipe by special casing
the differing opps to differentiate from mpc combine.
Since top/bottom pipe list was made to track mpc muxing this creates
difficulties in adding a 4 pipe odm case support.
Rather than continue using mpc combine list, this change reworks odm
to use it's own linked list to keep track of odm combine pipes. This
also opens up options for using mpo with odm, if a practical use case
is ever found.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 10 +-
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 33 ++-
.../drm/amd/display/dc/core/dc_link_hwss.c | 36 +--
.../gpu/drm/amd/display/dc/core/dc_resource.c | 150 ++++-------
.../display/dc/dce110/dce110_hw_sequencer.c | 7 +-
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 +-
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c | 90 ++++---
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 244 ++++++++++++------
.../display/dc/dcn20/dcn20_stream_encoder.c | 2 +-
.../gpu/drm/amd/display/dc/inc/core_types.h | 2 +
.../amd/display/dc/inc/hw/stream_encoder.h | 2 +-
drivers/gpu/drm/amd/display/dc/inc/resource.h | 3 -
12 files changed, 316 insertions(+), 265 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 77ac7f707ec5..62d5f454f824 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1857,9 +1857,7 @@ static void commit_planes_do_stream_update(struct dc *dc,
for (j = 0; j < dc->res_pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
- if (!pipe_ctx->top_pipe &&
- pipe_ctx->stream &&
- pipe_ctx->stream == stream) {
+ if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe && pipe_ctx->stream == stream) {
if (stream_update->periodic_interrupt0 &&
dc->hwss.setup_periodic_interrupt)
@@ -1885,7 +1883,7 @@ static void commit_planes_do_stream_update(struct dc *dc,
if (stream_update->dither_option) {
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
- struct pipe_ctx *odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
+ struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
#endif
resource_build_bit_depth_reduction_params(pipe_ctx->stream,
&pipe_ctx->stream->bit_depth_params);
@@ -1893,10 +1891,12 @@ static void commit_planes_do_stream_update(struct dc *dc,
&stream->bit_depth_params,
&stream->clamping);
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
- if (odm_pipe)
+ while (odm_pipe) {
odm_pipe->stream_res.opp->funcs->opp_program_fmt(odm_pipe->stream_res.opp,
&stream->bit_depth_params,
&stream->clamping);
+ odm_pipe = odm_pipe->next_odm_pipe;
+ }
#endif
}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 2e87942b3e9c..2aa44b28b673 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -3095,14 +3095,19 @@ static void set_crtc_test_pattern(struct dc_link *link,
controller_test_pattern, color_depth);
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
else if (opp->funcs->opp_set_disp_pattern_generator) {
- struct pipe_ctx *bot_odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
+ struct pipe_ctx *odm_pipe;
+ int opp_cnt = 1;
- if (bot_odm_pipe) {
- struct output_pixel_processor *bot_opp = bot_odm_pipe->stream_res.opp;
+ for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
+ opp_cnt++;
- bot_opp->funcs->opp_program_bit_depth_reduction(bot_opp, ¶ms);
- width /= 2;
- bot_opp->funcs->opp_set_disp_pattern_generator(bot_opp,
+ width /= opp_cnt;
+
+ for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
+ struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
+
+ odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, ¶ms);
+ odm_opp->funcs->opp_set_disp_pattern_generator(odm_opp,
controller_test_pattern,
color_depth,
NULL,
@@ -3131,14 +3136,18 @@ static void set_crtc_test_pattern(struct dc_link *link,
color_depth);
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
else if (opp->funcs->opp_set_disp_pattern_generator) {
- struct pipe_ctx *bot_odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
+ struct pipe_ctx *odm_pipe;
+ int opp_cnt = 1;
+
+ for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
+ opp_cnt++;
- if (bot_odm_pipe) {
- struct output_pixel_processor *bot_opp = bot_odm_pipe->stream_res.opp;
+ width /= opp_cnt;
+ for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
+ struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
- bot_opp->funcs->opp_program_bit_depth_reduction(bot_opp, ¶ms);
- width /= 2;
- bot_opp->funcs->opp_set_disp_pattern_generator(bot_opp,
+ odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, ¶ms);
+ odm_opp->funcs->opp_set_disp_pattern_generator(odm_opp,
CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
color_depth,
NULL,
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index 35c5467e60e8..fe9a4e4b9d1f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -275,7 +275,7 @@ void dp_retrain_link_dp_test(struct dc_link *link,
for (i = 0; i < MAX_PIPES; i++) {
if (pipes[i].stream != NULL &&
- !pipes[i].top_pipe &&
+ !pipes[i].top_pipe && !pipes[i].prev_odm_pipe &&
pipes[i].stream->link != NULL &&
pipes[i].stream_res.stream_enc != NULL) {
udelay(100);
@@ -381,7 +381,11 @@ void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
struct dc *core_dc = pipe_ctx->stream->ctx->dc;
struct dc_stream_state *stream = pipe_ctx->stream;
- struct pipe_ctx *odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
+ struct pipe_ctx *odm_pipe;
+ int opp_cnt = 1;
+
+ for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
+ opp_cnt++;
if (enable) {
struct dsc_config dsc_cfg;
@@ -389,26 +393,24 @@ void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
enum optc_dsc_mode optc_dsc_mode;
/* Enable DSC hw block */
- dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
+ dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;
dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
dsc_cfg.color_depth = stream->timing.display_color_depth;
dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
+ ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);
+ dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
+
+ dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);
+ dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
+ for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
+ struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc;
- if (odm_pipe) {
- struct display_stream_compressor *bot_dsc = odm_pipe->stream_res.dsc;
-
- dsc_cfg.pic_width /= 2;
- ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % 2 == 0);
- dsc_cfg.dc_dsc_cfg.num_slices_h /= 2;
- dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);
- bot_dsc->funcs->dsc_set_config(bot_dsc, &dsc_cfg, &dsc_optc_cfg);
- dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
- bot_dsc->funcs->dsc_enable(bot_dsc, odm_pipe->stream_res.opp->inst);
- } else {
- dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);
- dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
+ odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg);
+ odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst);
}
+ dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt;
+ dsc_cfg.pic_width *= opp_cnt;
optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED;
@@ -449,7 +451,7 @@ void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
/* disable DSC block */
pipe_ctx->stream_res.dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc);
- if (odm_pipe)
+ for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc);
}
}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index fa94dfc04dce..1464f4c60089 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1114,8 +1114,9 @@ struct pipe_ctx *resource_get_head_pipe_for_stream(
{
int i;
for (i = 0; i < MAX_PIPES; i++) {
- if (res_ctx->pipe_ctx[i].stream == stream &&
- !res_ctx->pipe_ctx[i].top_pipe) {
+ if (res_ctx->pipe_ctx[i].stream == stream
+ && !res_ctx->pipe_ctx[i].top_pipe
+ && !res_ctx->pipe_ctx[i].prev_odm_pipe) {
return &res_ctx->pipe_ctx[i];
break;
}
@@ -1123,15 +1124,11 @@ struct pipe_ctx *resource_get_head_pipe_for_stream(
return NULL;
}
-static struct pipe_ctx *resource_get_tail_pipe_for_stream(
+static struct pipe_ctx *resource_get_tail_pipe(
struct resource_context *res_ctx,
- struct dc_stream_state *stream)
+ struct pipe_ctx *head_pipe)
{
- struct pipe_ctx *head_pipe, *tail_pipe;
- head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
-
- if (!head_pipe)
- return NULL;
+ struct pipe_ctx *tail_pipe;
tail_pipe = head_pipe->bottom_pipe;
@@ -1147,31 +1144,20 @@ static struct pipe_ctx *resource_get_tail_pipe_for_stream(
* A free_pipe for a stream is defined here as a pipe
* that has no surface attached yet
*/
-static struct pipe_ctx *acquire_free_pipe_for_stream(
+static struct pipe_ctx *acquire_free_pipe_for_head(
struct dc_state *context,
const struct resource_pool *pool,
- struct dc_stream_state *stream)
+ struct pipe_ctx *head_pipe)
{
int i;
struct resource_context *res_ctx = &context->res_ctx;
- struct pipe_ctx *head_pipe = NULL;
-
- /* Find head pipe, which has the back end set up*/
-
- head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
-
- if (!head_pipe) {
- ASSERT(0);
- return NULL;
- }
-
if (!head_pipe->plane_state)
return head_pipe;
/* Re-use pipe already acquired for this stream if available*/
for (i = pool->pipe_count - 1; i >= 0; i--) {
- if (res_ctx->pipe_ctx[i].stream == stream &&
+ if (res_ctx->pipe_ctx[i].stream == head_pipe->stream &&
!res_ctx->pipe_ctx[i].plane_state) {
return &res_ctx->pipe_ctx[i];
}
@@ -1185,8 +1171,7 @@ static struct pipe_ctx *acquire_free_pipe_for_stream(
if (!pool->funcs->acquire_idle_pipe_for_layer)
return NULL;
- return pool->funcs->acquire_idle_pipe_for_layer(context, pool, stream);
-
+ return pool->funcs->acquire_idle_pipe_for_layer(context, pool, head_pipe->stream);
}
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
@@ -1200,7 +1185,7 @@ static int acquire_first_split_pipe(
for (i = 0; i < pool->pipe_count; i++) {
struct pipe_ctx *split_pipe = &res_ctx->pipe_ctx[i];
- if (split_pipe->top_pipe && !dc_res_is_odm_head_pipe(split_pipe) &&
+ if (split_pipe->top_pipe &&
split_pipe->top_pipe->plane_state == split_pipe->plane_state) {
split_pipe->top_pipe->bottom_pipe = split_pipe->bottom_pipe;
if (split_pipe->bottom_pipe)
@@ -1261,39 +1246,41 @@ bool dc_add_plane_to_context(
return false;
}
- tail_pipe = resource_get_tail_pipe_for_stream(&context->res_ctx, stream);
- ASSERT(tail_pipe);
+ /* retain new surface, but only once per stream */
+ dc_plane_state_retain(plane_state);
- free_pipe = acquire_free_pipe_for_stream(context, pool, stream);
+ while (head_pipe) {
+ tail_pipe = resource_get_tail_pipe(&context->res_ctx, head_pipe);
+ ASSERT(tail_pipe);
-#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
- if (!free_pipe) {
- int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
- if (pipe_idx >= 0)
- free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
- }
-#endif
- if (!free_pipe)
- return false;
+ free_pipe = acquire_free_pipe_for_head(context, pool, head_pipe);
- /* retain new surfaces */
- dc_plane_state_retain(plane_state);
- free_pipe->plane_state = plane_state;
-
- if (head_pipe != free_pipe) {
- free_pipe->stream_res.tg = tail_pipe->stream_res.tg;
- free_pipe->stream_res.abm = tail_pipe->stream_res.abm;
- free_pipe->stream_res.opp = tail_pipe->stream_res.opp;
- free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc;
- free_pipe->stream_res.audio = tail_pipe->stream_res.audio;
- free_pipe->clock_source = tail_pipe->clock_source;
- free_pipe->top_pipe = tail_pipe;
- tail_pipe->bottom_pipe = free_pipe;
- } else if (free_pipe->bottom_pipe && free_pipe->bottom_pipe->plane_state == NULL) {
- ASSERT(free_pipe->bottom_pipe->stream_res.opp != free_pipe->stream_res.opp);
- free_pipe->bottom_pipe->plane_state = plane_state;
- }
+ #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ if (!free_pipe) {
+ int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
+ if (pipe_idx >= 0)
+ free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
+ }
+ #endif
+ if (!free_pipe) {
+ dc_plane_state_release(plane_state);
+ return false;
+ }
+ free_pipe->plane_state = plane_state;
+
+ if (head_pipe != free_pipe) {
+ free_pipe->stream_res.tg = tail_pipe->stream_res.tg;
+ free_pipe->stream_res.abm = tail_pipe->stream_res.abm;
+ free_pipe->stream_res.opp = tail_pipe->stream_res.opp;
+ free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc;
+ free_pipe->stream_res.audio = tail_pipe->stream_res.audio;
+ free_pipe->clock_source = tail_pipe->clock_source;
+ free_pipe->top_pipe = tail_pipe;
+ tail_pipe->bottom_pipe = free_pipe;
+ }
+ head_pipe = head_pipe->next_odm_pipe;
+ }
/* assign new surfaces*/
stream_status->plane_states[stream_status->plane_count] = plane_state;
@@ -1302,35 +1289,6 @@ bool dc_add_plane_to_context(
return true;
}
-struct pipe_ctx *dc_res_get_odm_bottom_pipe(struct pipe_ctx *pipe_ctx)
-{
- struct pipe_ctx *bottom_pipe = pipe_ctx->bottom_pipe;
-
- /* ODM should only be updated once per otg */
- if (pipe_ctx->top_pipe)
- return NULL;
-
- while (bottom_pipe) {
- if (bottom_pipe->stream_res.opp != pipe_ctx->stream_res.opp)
- break;
- bottom_pipe = bottom_pipe->bottom_pipe;
- }
-
- return bottom_pipe;
-}
-
-bool dc_res_is_odm_head_pipe(struct pipe_ctx *pipe_ctx)
-{
- struct pipe_ctx *top_pipe = pipe_ctx->top_pipe;
-
- if (!top_pipe)
- return false;
- if (top_pipe && top_pipe->stream_res.opp == pipe_ctx->stream_res.opp)
- return false;
-
- return true;
-}
-
bool dc_remove_plane_from_context(
const struct dc *dc,
struct dc_stream_state *stream,
@@ -1357,12 +1315,6 @@ bool dc_remove_plane_from_context(
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
if (pipe_ctx->plane_state == plane_state) {
- if (dc_res_is_odm_head_pipe(pipe_ctx)) {
- pipe_ctx->plane_state = NULL;
- pipe_ctx->bottom_pipe = NULL;
- continue;
- }
-
if (pipe_ctx->top_pipe)
pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
@@ -1377,13 +1329,10 @@ bool dc_remove_plane_from_context(
* For head pipe detach surfaces from pipe for tail
* pipe just zero it out
*/
- if (!pipe_ctx->top_pipe) {
+ if (!pipe_ctx->top_pipe)
pipe_ctx->plane_state = NULL;
- if (!dc_res_get_odm_bottom_pipe(pipe_ctx))
- pipe_ctx->bottom_pipe = NULL;
- } else {
+ else
memset(pipe_ctx, 0, sizeof(*pipe_ctx));
- }
}
}
@@ -1752,9 +1701,6 @@ enum dc_status dc_remove_stream_from_ctx(
for (i = 0; i < MAX_PIPES; i++) {
if (new_ctx->res_ctx.pipe_ctx[i].stream == stream &&
!new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
- struct pipe_ctx *odm_pipe =
- dc_res_get_odm_bottom_pipe(&new_ctx->res_ctx.pipe_ctx[i]);
-
del_pipe = &new_ctx->res_ctx.pipe_ctx[i];
ASSERT(del_pipe->stream_res.stream_enc);
@@ -1779,8 +1725,6 @@ enum dc_status dc_remove_stream_from_ctx(
dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream);
memset(del_pipe, 0, sizeof(*del_pipe));
- if (odm_pipe)
- memset(odm_pipe, 0, sizeof(*odm_pipe));
break;
}
@@ -2494,6 +2438,12 @@ void dc_resource_state_copy_construct(
if (cur_pipe->bottom_pipe)
cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
+
+ if (cur_pipe->next_odm_pipe)
+ cur_pipe->next_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx];
+
+ if (cur_pipe->prev_odm_pipe)
+ cur_pipe->prev_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx];
}
for (i = 0; i < dst_ctx->stream_count; i++) {
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 5a046e5bc756..2693404cab1a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1338,7 +1338,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(
struct drr_params params = {0};
unsigned int event_triggers = 0;
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
- struct pipe_ctx *odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
+ struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
#endif
if (dc->hwss.disable_stream_gating) {
@@ -1406,7 +1406,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(
&stream->bit_depth_params,
&stream->clamping);
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
- if (odm_pipe) {
+ while (odm_pipe) {
odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion(
odm_pipe->stream_res.opp,
COLOR_SPACE_YCBCR601,
@@ -1417,6 +1417,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(
odm_pipe->stream_res.opp,
&stream->bit_depth_params,
&stream->clamping);
+ odm_pipe = odm_pipe->next_odm_pipe;
}
#endif
@@ -2076,7 +2077,7 @@ enum dc_status dce110_apply_ctx_to_hw(
if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
continue;
- if (pipe_ctx->top_pipe)
+ if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe)
continue;
status = apply_single_controller_ctx_to_hw(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 9fe2fff67dc5..8bdda64b0525 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2536,7 +2536,7 @@ struct pipe_ctx *find_top_pipe_for_stream(
if (pipe_ctx->stream != stream)
continue;
- if (!pipe_ctx->top_pipe)
+ if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe)
return pipe_ctx;
}
return NULL;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index fa8a73f6c8e3..033a6ac68ecf 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -529,11 +529,9 @@ enum dc_status dcn20_enable_stream_timing(
struct dc_stream_state *stream = pipe_ctx->stream;
struct drr_params params = {0};
unsigned int event_triggers = 0;
-
-
-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
- struct pipe_ctx *odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
-#endif
+ struct pipe_ctx *odm_pipe;
+ int opp_cnt = 1;
+ int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
/* by upper caller loop, pipe0 is parent pipe and be called first.
* back end is set up by for pipe0. Other children pipe share back end
@@ -544,14 +542,17 @@ enum dc_status dcn20_enable_stream_timing(
/* TODO check if timing_changed, disable stream if timing changed */
- if (odm_pipe) {
- int opp_inst[2] = { pipe_ctx->stream_res.opp->inst, odm_pipe->stream_res.opp->inst };
+ for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
+ opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
+ opp_cnt++;
+ }
+ if (opp_cnt > 1)
pipe_ctx->stream_res.tg->funcs->set_odm_combine(
pipe_ctx->stream_res.tg,
- opp_inst, 2,
+ opp_inst, opp_cnt,
&pipe_ctx->stream->timing);
- }
+
/* HW program guide assume display already disable
* by unplug sequence. OTG assume stop.
*/
@@ -579,7 +580,7 @@ enum dc_status dcn20_enable_stream_timing(
pipe_ctx->stream_res.tg->funcs->setup_global_lock(
pipe_ctx->stream_res.tg);
- if (odm_pipe)
+ for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
odm_pipe->stream_res.opp,
true);
@@ -665,7 +666,7 @@ bool dcn20_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
*/
if (mpc->funcs->power_on_mpc_mem_pwr)
mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);
- if ((pipe_ctx->top_pipe == NULL || dc_res_is_odm_head_pipe(pipe_ctx))
+ if (pipe_ctx->top_pipe == NULL
&& mpc->funcs->set_output_gamma && stream->out_transfer_func) {
if (stream->out_transfer_func->type == TF_TYPE_HWPWL)
params = &stream->out_transfer_func->pwl;
@@ -827,17 +828,21 @@ bool dcn20_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
static void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
{
- struct pipe_ctx *combine_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
+ struct pipe_ctx *odm_pipe;
+ int opp_cnt = 1;
+ int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
- if (combine_pipe) {
- int opp_inst[2] = { pipe_ctx->stream_res.opp->inst,
- combine_pipe->stream_res.opp->inst };
+ for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
+ opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
+ opp_cnt++;
+ }
+ if (opp_cnt > 1)
pipe_ctx->stream_res.tg->funcs->set_odm_combine(
pipe_ctx->stream_res.tg,
- opp_inst, 2,
+ opp_inst, opp_cnt,
&pipe_ctx->stream->timing);
- } else
+ else
pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
}
@@ -852,7 +857,8 @@ void dcn20_blank_pixel_data(
struct dc_stream_state *stream = pipe_ctx->stream;
enum dc_color_space color_space = stream->output_color_space;
enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR;
- struct pipe_ctx *bot_odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
+ struct pipe_ctx *odm_pipe;
+ int odm_cnt = 1;
int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top;
@@ -860,8 +866,10 @@ void dcn20_blank_pixel_data(
/* get opp dpg blank color */
color_space_to_black_color(dc, color_space, &black_color);
- if (bot_odm_pipe)
- width = width / 2;
+ for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
+ odm_cnt++;
+
+ width = width / odm_cnt;
if (blank) {
if (stream_res->abm)
@@ -881,9 +889,9 @@ void dcn20_blank_pixel_data(
width,
height);
- if (bot_odm_pipe) {
- bot_odm_pipe->stream_res.opp->funcs->opp_set_disp_pattern_generator(
- bot_odm_pipe->stream_res.opp,
+ for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
+ odm_pipe->stream_res.opp->funcs->opp_set_disp_pattern_generator(
+ odm_pipe->stream_res.opp,
dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE ?
CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern,
stream->timing.display_color_depth,
@@ -1025,7 +1033,7 @@ static void dcn20_program_all_pipe_in_tree(
struct pipe_ctx *pipe_ctx,
struct dc_state *context)
{
- if (pipe_ctx->top_pipe == NULL) {
+ if (pipe_ctx->top_pipe == NULL && !pipe_ctx->prev_odm_pipe) {
bool blank = !is_pipe_tree_visible(pipe_ctx);
pipe_ctx->stream_res.tg->funcs->program_global_sync(
@@ -1316,8 +1324,8 @@ bool dcn20_update_bandwidth(
pipe_ctx->stream_res.tg->funcs->set_vtg_params(
pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
-
- dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);
+ if (pipe_ctx->prev_odm_pipe == NULL)
+ dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);
}
pipe_ctx->plane_res.hubp->funcs->hubp_setup(
@@ -1407,12 +1415,15 @@ static void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx
{
#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
struct dce_hwseq *hws = dc->hwseq;
- struct pipe_ctx *bot_odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
if (pipe_ctx->stream_res.dsc) {
+ struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
+
dcn20_dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true);
- if (bot_odm_pipe)
- dcn20_dsc_pg_control(hws, bot_odm_pipe->stream_res.dsc->inst, true);
+ while (odm_pipe) {
+ dcn20_dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, true);
+ odm_pipe = odm_pipe->next_odm_pipe;
+ }
}
#endif
}
@@ -1421,12 +1432,15 @@ static void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
{
#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
struct dce_hwseq *hws = dc->hwseq;
- struct pipe_ctx *bot_odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
if (pipe_ctx->stream_res.dsc) {
+ struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
+
dcn20_dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false);
- if (bot_odm_pipe)
- dcn20_dsc_pg_control(hws, bot_odm_pipe->stream_res.dsc->inst, false);
+ while (odm_pipe) {
+ dcn20_dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, false);
+ odm_pipe = odm_pipe->next_odm_pipe;
+ }
}
#endif
}
@@ -1556,18 +1570,22 @@ void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
struct encoder_unblank_param params = { { 0 } };
struct dc_stream_state *stream = pipe_ctx->stream;
struct dc_link *link = stream->link;
- params.odm = dc_res_get_odm_bottom_pipe(pipe_ctx);
+ struct pipe_ctx *odm_pipe;
+ params.opp_cnt = 1;
+ for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
+ params.opp_cnt++;
+ }
/* only 3 items below are used by unblank */
params.timing = pipe_ctx->stream->timing;
params.link_settings.link_rate = link_settings->link_rate;
if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
- if (optc1_is_two_pixels_per_containter(&stream->timing) || params.odm)
+ if (optc1_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt)
params.timing.pix_clk_100hz /= 2;
pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine(
- pipe_ctx->stream_res.stream_enc, params.odm);
+ pipe_ctx->stream_res.stream_enc, params.opp_cnt);
pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms);
}
@@ -1658,7 +1676,7 @@ static void dcn20_reset_hw_ctx_wrap(
if (!pipe_ctx_old->stream)
continue;
- if (pipe_ctx_old->top_pipe)
+ if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe)
continue;
if (!pipe_ctx->stream ||
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index c59f31dcdc0d..aa1342ccf8b4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1317,7 +1317,11 @@ static void get_pixel_clock_parameters(
struct pixel_clk_params *pixel_clk_params)
{
const struct dc_stream_state *stream = pipe_ctx->stream;
- bool odm_combine = dc_res_get_odm_bottom_pipe(pipe_ctx) != NULL;
+ struct pipe_ctx *odm_pipe;
+ int opp_cnt = 1;
+
+ for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
+ opp_cnt++;
pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
pixel_clk_params->encoder_object_id = stream->link->link_enc->id;
@@ -1335,7 +1339,9 @@ static void get_pixel_clock_parameters(
if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
pixel_clk_params->color_depth = COLOR_DEPTH_888;
- if (optc1_is_two_pixels_per_containter(&stream->timing) || odm_combine)
+ if (opp_cnt == 4)
+ pixel_clk_params->requested_pix_clk_100hz /= 4;
+ else if (optc1_is_two_pixels_per_containter(&stream->timing) || opp_cnt == 2)
pixel_clk_params->requested_pix_clk_100hz /= 2;
if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
@@ -1479,22 +1485,16 @@ static enum dc_status remove_dsc_from_stream_resource(struct dc *dc,
for (i = 0; i < MAX_PIPES; i++) {
if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
- break;
+
+ if (pipe_ctx->stream_res.dsc)
+ release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc);
}
}
if (!pipe_ctx)
return DC_ERROR_UNEXPECTED;
-
- if (pipe_ctx->stream_res.dsc) {
- struct pipe_ctx *odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
-
- release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc);
- if (odm_pipe)
- release_dsc(&new_ctx->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc);
- }
-
- return DC_OK;
+ else
+ return DC_OK;
}
#endif
@@ -1593,17 +1593,94 @@ static void swizzle_to_dml_params(
}
}
-static bool dcn20_split_stream_for_combine(
+static bool dcn20_split_stream_for_odm(
+ struct resource_context *res_ctx,
+ const struct resource_pool *pool,
+ struct pipe_ctx *prev_odm_pipe,
+ struct pipe_ctx *next_odm_pipe)
+{
+ int pipe_idx = next_odm_pipe->pipe_idx;
+ struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data;
+ struct pipe_ctx *sec_next_pipe = next_odm_pipe->next_odm_pipe;
+ int new_width;
+
+ *next_odm_pipe = *prev_odm_pipe;
+ next_odm_pipe->next_odm_pipe = sec_next_pipe;
+
+ next_odm_pipe->pipe_idx = pipe_idx;
+ next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx];
+ next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx];
+ next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx];
+ next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx];
+ next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx];
+ next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst;
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ next_odm_pipe->stream_res.dsc = NULL;
+#endif
+ if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) {
+ ASSERT(!next_odm_pipe->next_odm_pipe);
+ next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe;
+ next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe;
+ }
+ prev_odm_pipe->next_odm_pipe = next_odm_pipe;
+ next_odm_pipe->prev_odm_pipe = prev_odm_pipe;
+ ASSERT(next_odm_pipe->top_pipe == NULL);
+
+ if (prev_odm_pipe->plane_state) {
+ /* HACTIVE halved for odm combine */
+ sd->h_active /= 2;
+ /* Copy scl_data to secondary pipe */
+ next_odm_pipe->plane_res.scl_data = *sd;
+
+ /* Calculate new vp and recout for left pipe */
+ /* Need at least 16 pixels width per side */
+ if (sd->recout.x + 16 >= sd->h_active)
+ return false;
+ new_width = sd->h_active - sd->recout.x;
+ sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
+ sd->ratios.horz, sd->recout.width - new_width));
+ sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
+ sd->ratios.horz_c, sd->recout.width - new_width));
+ sd->recout.width = new_width;
+
+ /* Calculate new vp and recout for right pipe */
+ sd = &next_odm_pipe->plane_res.scl_data;
+ new_width = sd->recout.width + sd->recout.x - sd->h_active;
+ /* Need at least 16 pixels width per side */
+ if (new_width <= 16)
+ return false;
+ sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
+ sd->ratios.horz, sd->recout.width - new_width));
+ sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
+ sd->ratios.horz_c, sd->recout.width - new_width));
+ sd->recout.width = new_width;
+ sd->viewport.x += dc_fixpt_floor(dc_fixpt_mul_int(
+ sd->ratios.horz, sd->h_active - sd->recout.x));
+ sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int(
+ sd->ratios.horz_c, sd->h_active - sd->recout.x));
+ sd->recout.x = 0;
+ }
+ next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx];
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ if (next_odm_pipe->stream->timing.flags.DSC == 1) {
+ acquire_dsc(res_ctx, pool, &next_odm_pipe->stream_res.dsc);
+ ASSERT(next_odm_pipe->stream_res.dsc);
+ if (next_odm_pipe->stream_res.dsc == NULL)
+ return false;
+ }
+#endif
+
+ return true;
+}
+
+static void dcn20_split_stream_for_mpc(
struct resource_context *res_ctx,
const struct resource_pool *pool,
struct pipe_ctx *primary_pipe,
- struct pipe_ctx *secondary_pipe,
- bool is_odm_combine)
+ struct pipe_ctx *secondary_pipe)
{
int pipe_idx = secondary_pipe->pipe_idx;
- struct scaler_data *sd = &primary_pipe->plane_res.scl_data;
struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe;
- int new_width;
*secondary_pipe = *primary_pipe;
secondary_pipe->bottom_pipe = sec_bot_pipe;
@@ -1626,57 +1703,9 @@ static bool dcn20_split_stream_for_combine(
primary_pipe->bottom_pipe = secondary_pipe;
secondary_pipe->top_pipe = primary_pipe;
- if (is_odm_combine) {
- if (primary_pipe->plane_state) {
- /* HACTIVE halved for odm combine */
- sd->h_active /= 2;
- /* Copy scl_data to secondary pipe */
- secondary_pipe->plane_res.scl_data = *sd;
-
- /* Calculate new vp and recout for left pipe */
- /* Need at least 16 pixels width per side */
- if (sd->recout.x + 16 >= sd->h_active)
- return false;
- new_width = sd->h_active - sd->recout.x;
- sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
- sd->ratios.horz, sd->recout.width - new_width));
- sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
- sd->ratios.horz_c, sd->recout.width - new_width));
- sd->recout.width = new_width;
-
- /* Calculate new vp and recout for right pipe */
- sd = &secondary_pipe->plane_res.scl_data;
- new_width = sd->recout.width + sd->recout.x - sd->h_active;
- /* Need at least 16 pixels width per side */
- if (new_width <= 16)
- return false;
- sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
- sd->ratios.horz, sd->recout.width - new_width));
- sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
- sd->ratios.horz_c, sd->recout.width - new_width));
- sd->recout.width = new_width;
- sd->viewport.x += dc_fixpt_floor(dc_fixpt_mul_int(
- sd->ratios.horz, sd->h_active - sd->recout.x));
- sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int(
- sd->ratios.horz_c, sd->h_active - sd->recout.x));
- sd->recout.x = 0;
- }
- secondary_pipe->stream_res.opp = pool->opps[secondary_pipe->pipe_idx];
-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
- if (secondary_pipe->stream->timing.flags.DSC == 1) {
- acquire_dsc(res_ctx, pool, &secondary_pipe->stream_res.dsc);
- ASSERT(secondary_pipe->stream_res.dsc);
- if (secondary_pipe->stream_res.dsc == NULL)
- return false;
- }
-#endif
- } else {
- ASSERT(primary_pipe->plane_state);
- resource_build_scaling_params(primary_pipe);
- resource_build_scaling_params(secondary_pipe);
- }
-
- return true;
+ ASSERT(primary_pipe->plane_state);
+ resource_build_scaling_params(primary_pipe);
+ resource_build_scaling_params(secondary_pipe);
}
void dcn20_populate_dml_writeback_from_context(
@@ -2106,20 +2135,24 @@ static bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
struct dc_stream_state *stream = pipe_ctx->stream;
struct dsc_config dsc_cfg;
+ struct pipe_ctx *odm_pipe;
+ int opp_cnt = 1;
+
+ for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
+ opp_cnt++;
/* Only need to validate top pipe */
- if (pipe_ctx->top_pipe || !stream || !stream->timing.flags.DSC)
+ if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC)
continue;
- dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left
- + stream->timing.h_border_right;
+ dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left
+ + stream->timing.h_border_right) / opp_cnt;
dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top
+ stream->timing.v_border_bottom;
- if (dc_res_get_odm_bottom_pipe(pipe_ctx))
- dsc_cfg.pic_width /= 2;
dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
dsc_cfg.color_depth = stream->timing.display_color_depth;
dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
+ dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg))
return false;
@@ -2143,6 +2176,8 @@ static struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
* if this primary pipe has a bottom pipe in prev. state
* and if the bottom pipe is still available (which it should be),
* pick that pipe as secondary
+ * Same logic applies for ODM pipes. Since mpo is not allowed with odm
+ * check in else case.
*/
if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe) {
preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx;
@@ -2150,6 +2185,12 @@ static struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
secondary_pipe->pipe_idx = preferred_pipe_idx;
}
+ } else if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe) {
+ preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx;
+ if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
+ secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
+ secondary_pipe->pipe_idx = preferred_pipe_idx;
+ }
}
/*
@@ -2220,6 +2261,38 @@ bool dcn20_fast_validate_bw(
if (!pipes)
return false;
+ /* merge previously split odm pipes since mode support needs to make the decision */
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+ struct pipe_ctx *odm_pipe = pipe->next_odm_pipe;
+
+ if (pipe->prev_odm_pipe)
+ continue;
+
+ pipe->next_odm_pipe = NULL;
+ while (odm_pipe) {
+ struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;
+
+ odm_pipe->plane_state = NULL;
+ odm_pipe->stream = NULL;
+ odm_pipe->top_pipe = NULL;
+ odm_pipe->bottom_pipe = NULL;
+ odm_pipe->prev_odm_pipe = NULL;
+ odm_pipe->next_odm_pipe = NULL;
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ if (odm_pipe->stream_res.dsc)
+ release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc);
+#endif
+ /* Clear plane_res and stream_res */
+ memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res));
+ memset(&odm_pipe->stream_res, 0, sizeof(odm_pipe->stream_res));
+ odm_pipe = next_odm_pipe;
+ }
+ if (pipe->plane_state)
+ resource_build_scaling_params(pipe);
+ }
+
+ /* merge previously mpc split pipes since mode support needs to make the decision */
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
@@ -2227,7 +2300,6 @@ bool dcn20_fast_validate_bw(
if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state)
continue;
- /* merge previously split pipe since mode support needs to make the decision */
pipe->bottom_pipe = hsplit_pipe->bottom_pipe;
if (hsplit_pipe->bottom_pipe)
hsplit_pipe->bottom_pipe->top_pipe = pipe;
@@ -2235,10 +2307,7 @@ bool dcn20_fast_validate_bw(
hsplit_pipe->stream = NULL;
hsplit_pipe->top_pipe = NULL;
hsplit_pipe->bottom_pipe = NULL;
-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
- if (hsplit_pipe->stream_res.dsc && hsplit_pipe->stream_res.dsc != pipe->stream_res.dsc)
- release_dsc(&context->res_ctx, dc->res_pool, &hsplit_pipe->stream_res.dsc);
-#endif
+
/* Clear plane_res and stream_res */
memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res));
memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res));
@@ -2351,10 +2420,9 @@ bool dcn20_fast_validate_bw(
if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
ASSERT(hsplit_pipe);
- if (!dcn20_split_stream_for_combine(
+ if (!dcn20_split_stream_for_odm(
&context->res_ctx, dc->res_pool,
- pipe, hsplit_pipe,
- true))
+ pipe, hsplit_pipe))
goto validate_fail;
pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
dcn20_build_mapped_resource(dc, context, pipe->stream);
@@ -2395,11 +2463,15 @@ bool dcn20_fast_validate_bw(
if (!hsplit_pipe)
continue;
- if (!dcn20_split_stream_for_combine(
+ if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
+ if (!dcn20_split_stream_for_odm(
+ &context->res_ctx, dc->res_pool,
+ pipe, hsplit_pipe))
+ goto validate_fail;
+ } else
+ dcn20_split_stream_for_mpc(
&context->res_ctx, dc->res_pool,
- pipe, hsplit_pipe,
- context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]))
- goto validate_fail;
+ pipe, hsplit_pipe);
pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
}
} else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
index 6d54942ab98b..488fb5c71dd0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
@@ -466,7 +466,7 @@ void enc2_stream_encoder_dp_unblank(
uint64_t m_vid_l = n_vid;
/* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */
- if (is_two_pixels_per_containter(¶m->timing) || param->odm) {
+ if (is_two_pixels_per_containter(¶m->timing) || param->opp_cnt) {
/*this logic should be the same in get_pixel_clock_parameters() */
n_multiply = 1;
}
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index 74186cf1c285..bfe0d06d1c20 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -297,6 +297,8 @@ struct pipe_ctx {
struct pipe_ctx *top_pipe;
struct pipe_ctx *bottom_pipe;
+ struct pipe_ctx *next_odm_pipe;
+ struct pipe_ctx *prev_odm_pipe;
#ifdef CONFIG_DRM_AMD_DC_DCN1_0
struct _vcs_dpi_display_dlg_regs_st dlg_regs;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
index 8bb3e3d56ac9..fe9b7a10a1c3 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
@@ -91,7 +91,7 @@ struct encoder_unblank_param {
struct dc_link_settings link_settings;
struct dc_crtc_timing timing;
#ifdef CONFIG_DRM_AMD_DC_DCN2_0
- bool odm;
+ int opp_cnt;
#endif
};
diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h
index 47f81072d7e9..1cc1c8ce633b 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/resource.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h
@@ -179,7 +179,4 @@ void update_audio_usage(
unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format);
-struct pipe_ctx *dc_res_get_odm_bottom_pipe(struct pipe_ctx *pipe_ctx);
-bool dc_res_is_odm_head_pipe(struct pipe_ctx *pipe_ctx);
-
#endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ */
--
2.17.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 02/36] drm/amd/display: Delete dead code in command_table_helper
[not found] ` <20190819143515.21653-1-Bhawanpreet.Lakha-5C7GfCeVMHo@public.gmane.org>
2019-08-19 14:34 ` [PATCH 01/36] drm/amd/display: re structure odm to allow 4 to 1 support Bhawanpreet Lakha
@ 2019-08-19 14:34 ` Bhawanpreet Lakha
2019-08-19 14:34 ` [PATCH 03/36] drm/amd/display: fix audio endpoint not getting disabled issue Bhawanpreet Lakha
` (33 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Bhawanpreet Lakha @ 2019-08-19 14:34 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Julian Parkin
From: Julian Parkin <julian.parkin@amd.com>
[Why]
dig_encoder_sel_to_atom will always return zero on any ASIC version
past DCE80 since programming of the FE selection is handled by
driver, but the translation code was left in the function, making
it look like a coding error.
[How]
Remove code that has no effect, and replace with a comment describing
why it returns zero.
Signed-off-by: Julian Parkin <julian.parkin@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
.../bios/dce110/command_table_helper_dce110.c | 36 +++----------------
.../dce112/command_table_helper2_dce112.c | 36 +++----------------
.../bios/dce112/command_table_helper_dce112.c | 36 +++----------------
3 files changed, 12 insertions(+), 96 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c b/drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c
index ca24154468c7..11bf247bb180 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c
@@ -153,38 +153,10 @@ static uint8_t hpd_sel_to_atom(enum hpd_source_id id)
static uint8_t dig_encoder_sel_to_atom(enum engine_id id)
{
- uint8_t atom_dig_encoder_sel = 0;
-
- switch (id) {
- case ENGINE_ID_DIGA:
- atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGA_SEL;
- break;
- case ENGINE_ID_DIGB:
- atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGB_SEL;
- break;
- case ENGINE_ID_DIGC:
- atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGC_SEL;
- break;
- case ENGINE_ID_DIGD:
- atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGD_SEL;
- break;
- case ENGINE_ID_DIGE:
- atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGE_SEL;
- break;
- case ENGINE_ID_DIGF:
- atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGF_SEL;
- break;
- case ENGINE_ID_DIGG:
- atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGG_SEL;
- break;
- case ENGINE_ID_UNKNOWN:
- /* No DIG_FRONT is associated to DIG_BACKEND */
- atom_dig_encoder_sel = 0;
- break;
- default:
- atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGA_SEL;
- break;
- }
+ /* On any ASIC after DCE80, we manually program the DIG_FE
+ * selection (see connect_dig_be_to_fe function of the link
+ * encoder), so translation should always return 0 (no FE).
+ */
return 0;
}
diff --git a/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c b/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c
index 0237ae575068..755b6e33140a 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c
@@ -150,38 +150,10 @@ static uint8_t hpd_sel_to_atom(enum hpd_source_id id)
static uint8_t dig_encoder_sel_to_atom(enum engine_id id)
{
- uint8_t atom_dig_encoder_sel = 0;
-
- switch (id) {
- case ENGINE_ID_DIGA:
- atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGA_SEL;
- break;
- case ENGINE_ID_DIGB:
- atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGB_SEL;
- break;
- case ENGINE_ID_DIGC:
- atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGC_SEL;
- break;
- case ENGINE_ID_DIGD:
- atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGD_SEL;
- break;
- case ENGINE_ID_DIGE:
- atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGE_SEL;
- break;
- case ENGINE_ID_DIGF:
- atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGF_SEL;
- break;
- case ENGINE_ID_DIGG:
- atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGG_SEL;
- break;
- case ENGINE_ID_UNKNOWN:
- /* No DIG_FRONT is associated to DIG_BACKEND */
- atom_dig_encoder_sel = 0;
- break;
- default:
- atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGA_SEL;
- break;
- }
+ /* On any ASIC after DCE80, we manually program the DIG_FE
+ * selection (see connect_dig_be_to_fe function of the link
+ * encoder), so translation should always return 0 (no FE).
+ */
return 0;
}
diff --git a/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c b/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c
index 452034f83e4c..06b4f7fa4a50 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c
@@ -150,38 +150,10 @@ static uint8_t hpd_sel_to_atom(enum hpd_source_id id)
static uint8_t dig_encoder_sel_to_atom(enum engine_id id)
{
- uint8_t atom_dig_encoder_sel = 0;
-
- switch (id) {
- case ENGINE_ID_DIGA:
- atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGA_SEL;
- break;
- case ENGINE_ID_DIGB:
- atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGB_SEL;
- break;
- case ENGINE_ID_DIGC:
- atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGC_SEL;
- break;
- case ENGINE_ID_DIGD:
- atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGD_SEL;
- break;
- case ENGINE_ID_DIGE:
- atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGE_SEL;
- break;
- case ENGINE_ID_DIGF:
- atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGF_SEL;
- break;
- case ENGINE_ID_DIGG:
- atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGG_SEL;
- break;
- case ENGINE_ID_UNKNOWN:
- /* No DIG_FRONT is associated to DIG_BACKEND */
- atom_dig_encoder_sel = 0;
- break;
- default:
- atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGA_SEL;
- break;
- }
+ /* On any ASIC after DCE80, we manually program the DIG_FE
+ * selection (see connect_dig_be_to_fe function of the link
+ * encoder), so translation should always return 0 (no FE).
+ */
return 0;
}
--
2.17.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 03/36] drm/amd/display: fix audio endpoint not getting disabled issue
[not found] ` <20190819143515.21653-1-Bhawanpreet.Lakha-5C7GfCeVMHo@public.gmane.org>
2019-08-19 14:34 ` [PATCH 01/36] drm/amd/display: re structure odm to allow 4 to 1 support Bhawanpreet Lakha
2019-08-19 14:34 ` [PATCH 02/36] drm/amd/display: Delete dead code in command_table_helper Bhawanpreet Lakha
@ 2019-08-19 14:34 ` Bhawanpreet Lakha
2019-08-19 14:34 ` [PATCH 04/36] drm/amd/display: fix MPO HUBP underflow with Scatter Gather Bhawanpreet Lakha
` (32 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Bhawanpreet Lakha @ 2019-08-19 14:34 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Su Sung Chung
From: Su Sung Chung <Su.Chung@amd.com>
[Why]
Disable_audio_stream gets enum option as a paramenter which will decide
if we free acquired resources or not. However checks for the option is
guarded by the other condition which check if audio stream is getting
diabled more than once. With both conditions combined, if we attempt to
disable audio stream twice in a row, first with keep and second with
free as an option, we will never free any resources, which will make
system think there is audio endpoint connected even after we plug out
the device
[How]
Get rid of option as parameter to disable_audio_stream and move the part
of the code that free acquired resources to outside where to keep or to
free resources is actually determined
Signed-off-by: Su Sung Chung <Su.Chung@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 6 ++-
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 +-
.../drm/amd/display/dc/core/dc_link_hwss.c | 4 +-
.../display/dc/dce110/dce110_hw_sequencer.c | 40 +++++++++++--------
.../display/dc/dce110/dce110_hw_sequencer.h | 4 +-
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 20 ++++++++--
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c | 24 ++++++++---
.../drm/amd/display/dc/dcn20/dcn20_hwseq.h | 2 +-
.../gpu/drm/amd/display/dc/inc/core_types.h | 7 +---
.../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 5 +--
10 files changed, 74 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 62d5f454f824..2b5299e40d66 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1915,7 +1915,11 @@ static void commit_planes_do_stream_update(struct dc *dc,
dc->hwss.pipe_control_lock(dc, pipe_ctx, true);
if (*stream_update->dpms_off) {
- core_link_disable_stream(pipe_ctx, KEEP_ACQUIRED_RESOURCE);
+ core_link_disable_stream(pipe_ctx);
+ /* for dpms, keep acquired resources*/
+ if (pipe_ctx->stream_res.audio && !dc->debug.az_endpoint_mute_only)
+ pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
+
dc->hwss.optimize_bandwidth(dc, dc->current_state);
} else {
if (!dc->optimize_seamless_boot)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 78c4d07253bb..cb909197b76f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2806,7 +2806,7 @@ void core_link_enable_stream(
#endif
}
-void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option)
+void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
{
struct dc *core_dc = pipe_ctx->stream->ctx->dc;
struct dc_stream_state *stream = pipe_ctx->stream;
@@ -2841,7 +2841,7 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option)
write_i2c_redriver_setting(pipe_ctx, false);
}
}
- core_dc->hwss.disable_stream(pipe_ctx, option);
+ core_dc->hwss.disable_stream(pipe_ctx);
disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index fe9a4e4b9d1f..79438c4f1e20 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -289,7 +289,9 @@ void dp_retrain_link_dp_test(struct dc_link *link,
dp_receiver_power_ctrl(link, false);
- link->dc->hwss.disable_stream(&pipes[i], KEEP_ACQUIRED_RESOURCE);
+ link->dc->hwss.disable_stream(&pipes[i]);
+ if ((&pipes[i])->stream_res.audio && !link->dc->debug.az_endpoint_mute_only)
+ (&pipes[i])->stream_res.audio->funcs->az_disable((&pipes[i])->stream_res.audio);
link->link_enc->funcs->disable_output(
link->link_enc,
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 2693404cab1a..c2d026ba269f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -978,7 +978,7 @@ void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)
}
}
-void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx, int option)
+void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx)
{
struct dc *dc;
struct pp_smu_funcs *pp_smu = NULL;
@@ -1001,24 +1001,13 @@ void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx, int option)
if (dc->res_pool->pp_smu)
pp_smu = dc->res_pool->pp_smu;
- if (option != KEEP_ACQUIRED_RESOURCE ||
- !dc->debug.az_endpoint_mute_only)
- /*only disalbe az_endpoint if power down or free*/
- pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
-
if (dc_is_dp_signal(pipe_ctx->stream->signal))
pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable(
pipe_ctx->stream_res.stream_enc);
else
pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable(
pipe_ctx->stream_res.stream_enc);
- /*don't free audio if it is from retrain or internal disable stream*/
- if (option == FREE_ACQUIRED_RESOURCE && dc->caps.dynamic_audio == true) {
- /*we have to dynamic arbitrate the audio endpoints*/
- /*we free the resource, need reset is_audio_acquired*/
- update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, pipe_ctx->stream_res.audio, false);
- pipe_ctx->stream_res.audio = NULL;
- }
+
if (clk_mgr->funcs->enable_pme_wa)
/*this is the first audio. apply the PME w/a in order to wake AZ from D3*/
clk_mgr->funcs->enable_pme_wa(clk_mgr);
@@ -1031,7 +1020,7 @@ void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx, int option)
}
}
-void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option)
+void dce110_disable_stream(struct pipe_ctx *pipe_ctx)
{
struct dc_stream_state *stream = pipe_ctx->stream;
struct dc_link *link = stream->link;
@@ -1048,7 +1037,7 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option)
pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets(
pipe_ctx->stream_res.stream_enc);
- dc->hwss.disable_audio_stream(pipe_ctx, option);
+ dc->hwss.disable_audio_stream(pipe_ctx);
link->link_enc->funcs->connect_dig_be_to_fe(
link->link_enc,
@@ -1911,8 +1900,25 @@ static void dce110_reset_hw_ctx_wrap(
/* Disable if new stream is null. O/w, if stream is
* disabled already, no need to disable again.
*/
- if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off)
- core_link_disable_stream(pipe_ctx_old, FREE_ACQUIRED_RESOURCE);
+ if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off) {
+ core_link_disable_stream(pipe_ctx_old);
+
+ /* free acquired resources*/
+ if (pipe_ctx_old->stream_res.audio) {
+ /*disable az_endpoint*/
+ pipe_ctx_old->stream_res.audio->funcs->
+ az_disable(pipe_ctx_old->stream_res.audio);
+
+ /*free audio*/
+ if (dc->caps.dynamic_audio == true) {
+ /*we have to dynamic arbitrate the audio endpoints*/
+ /*we free the resource, need reset is_audio_acquired*/
+ update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
+ pipe_ctx_old->stream_res.audio, false);
+ pipe_ctx_old->stream_res.audio = NULL;
+ }
+ }
+ }
pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true);
if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) {
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
index 668feb0d169d..2f9b7dbdf415 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
@@ -42,7 +42,7 @@ enum dc_status dce110_apply_ctx_to_hw(
void dce110_enable_stream(struct pipe_ctx *pipe_ctx);
-void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option);
+void dce110_disable_stream(struct pipe_ctx *pipe_ctx);
void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
struct dc_link_settings *link_settings);
@@ -50,7 +50,7 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
void dce110_blank_stream(struct pipe_ctx *pipe_ctx);
void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx);
-void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx, int option);
+void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx);
void dce110_update_info_frame(struct pipe_ctx *pipe_ctx);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 8bdda64b0525..f6f20050e389 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -827,11 +827,23 @@ static void dcn10_reset_back_end_for_pipe(
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
/* DPMS may already disable */
if (!pipe_ctx->stream->dpms_off)
- core_link_disable_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE);
- else if (pipe_ctx->stream_res.audio) {
- dc->hwss.disable_audio_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE);
+ core_link_disable_stream(pipe_ctx);
+ else if (pipe_ctx->stream_res.audio)
+ dc->hwss.disable_audio_stream(pipe_ctx);
+
+ if (pipe_ctx->stream_res.audio) {
+ /*disable az_endpoint*/
+ pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
+
+ /*free audio*/
+ if (dc->caps.dynamic_audio == true) {
+ /*we have to dynamic arbitrate the audio endpoints*/
+ /*we free the resource, need reset is_audio_acquired*/
+ update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
+ pipe_ctx->stream_res.audio, false);
+ pipe_ctx->stream_res.audio = NULL;
+ }
}
-
}
/* by upper caller loop, parent pipe: pipe0, will be reset last.
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 033a6ac68ecf..687d670fbd5d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1465,9 +1465,9 @@ void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx)
hubp->funcs->dmdata_set_attributes(hubp, &attr);
}
-void dcn20_disable_stream(struct pipe_ctx *pipe_ctx, int option)
+void dcn20_disable_stream(struct pipe_ctx *pipe_ctx)
{
- dce110_disable_stream(pipe_ctx, option);
+ dce110_disable_stream(pipe_ctx);
}
static void dcn20_init_vm_ctx(
@@ -1621,9 +1621,23 @@ static void dcn20_reset_back_end_for_pipe(
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
/* DPMS may already disable */
if (!pipe_ctx->stream->dpms_off)
- core_link_disable_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE);
- else if (pipe_ctx->stream_res.audio) {
- dc->hwss.disable_audio_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE);
+ core_link_disable_stream(pipe_ctx);
+ else if (pipe_ctx->stream_res.audio)
+ dc->hwss.disable_audio_stream(pipe_ctx);
+
+ /* free acquired resources */
+ if (pipe_ctx->stream_res.audio) {
+ /*disable az_endpoint*/
+ pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
+
+ /*free audio*/
+ if (dc->caps.dynamic_audio == true) {
+ /*we have to dynamic arbitrate the audio endpoints*/
+ /*we free the resource, need reset is_audio_acquired*/
+ update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
+ pipe_ctx->stream_res.audio, false);
+ pipe_ctx->stream_res.audio = NULL;
+ }
}
}
#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
index 689c2765b071..92ab3dd91814 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
@@ -75,7 +75,7 @@ bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx);
void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx);
-void dcn20_disable_stream(struct pipe_ctx *pipe_ctx, int option);
+void dcn20_disable_stream(struct pipe_ctx *pipe_ctx);
void dcn20_program_tripleBuffer(
const struct dc *dc,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index bfe0d06d1c20..df28fbc4c63c 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -63,11 +63,6 @@ struct link_init_data {
TODO: remove it when DC is complete. */
};
-enum {
- FREE_ACQUIRED_RESOURCE = 0,
- KEEP_ACQUIRED_RESOURCE = 1,
-};
-
struct dc_link *link_create(const struct link_init_data *init_params);
void link_destroy(struct dc_link **link);
@@ -82,7 +77,7 @@ void core_link_enable_stream(
struct dc_state *state,
struct pipe_ctx *pipe_ctx);
-void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option);
+void core_link_disable_stream(struct pipe_ctx *pipe_ctx);
void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
/********** DAL Core*********************/
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 80de2febd7cb..68b1185f0636 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -196,8 +196,7 @@ struct hw_sequencer_funcs {
void (*enable_stream)(struct pipe_ctx *pipe_ctx);
- void (*disable_stream)(struct pipe_ctx *pipe_ctx,
- int option);
+ void (*disable_stream)(struct pipe_ctx *pipe_ctx);
void (*unblank_stream)(struct pipe_ctx *pipe_ctx,
struct dc_link_settings *link_settings);
@@ -206,7 +205,7 @@ struct hw_sequencer_funcs {
void (*enable_audio_stream)(struct pipe_ctx *pipe_ctx);
- void (*disable_audio_stream)(struct pipe_ctx *pipe_ctx, int option);
+ void (*disable_audio_stream)(struct pipe_ctx *pipe_ctx);
void (*pipe_control_lock)(
struct dc *dc,
--
2.17.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 04/36] drm/amd/display: fix MPO HUBP underflow with Scatter Gather
[not found] ` <20190819143515.21653-1-Bhawanpreet.Lakha-5C7GfCeVMHo@public.gmane.org>
` (2 preceding siblings ...)
2019-08-19 14:34 ` [PATCH 03/36] drm/amd/display: fix audio endpoint not getting disabled issue Bhawanpreet Lakha
@ 2019-08-19 14:34 ` Bhawanpreet Lakha
2019-08-19 14:34 ` [PATCH 05/36] drm/amd/display: load iram for abm 2.3 Bhawanpreet Lakha
` (31 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Bhawanpreet Lakha @ 2019-08-19 14:34 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Zi Yu Liao
From: Zi Yu Liao <ziyu.liao@amd.com>
[why]
With Scatter Gather enabled, HUBP underflows during MPO enabled video
playback. hubp_init has a register write that fixes this problem, but
the register is cleared when HUBP gets power gated.
[how]
Make a call to hubp_init during enable_plane, so that the fix can
be applied after HUBP powers back on again.
Signed-off-by: Zi Yu Liao <ziyu.liao@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 687d670fbd5d..aee624371728 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -938,6 +938,9 @@ void dcn20_enable_plane(
/* enable DCFCLK current DCHUB */
pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);
+ /* initialize HUBP on power up */
+ pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp);
+
/* make sure OPP_PIPE_CLOCK_EN = 1 */
pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
pipe_ctx->stream_res.opp,
--
2.17.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 05/36] drm/amd/display: load iram for abm 2.3
[not found] ` <20190819143515.21653-1-Bhawanpreet.Lakha-5C7GfCeVMHo@public.gmane.org>
` (3 preceding siblings ...)
2019-08-19 14:34 ` [PATCH 04/36] drm/amd/display: fix MPO HUBP underflow with Scatter Gather Bhawanpreet Lakha
@ 2019-08-19 14:34 ` Bhawanpreet Lakha
2019-08-19 14:34 ` [PATCH 06/36] drm/amd/display: fix dp stream enable Bhawanpreet Lakha
` (30 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Bhawanpreet Lakha @ 2019-08-19 14:34 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Josip Pavic
From: Josip Pavic <Josip.Pavic@amd.com>
[Why]
ABM 2.3 firmware expects information in iRAM that differs from previous
versions of ABM, so a mechanism is required to provide it with that
information.
[How]
Extend the existing iRAM definition to include parameters added by
ABM 2.3, and load it if DMCU is running ABM 2.3.
Signed-off-by: Josip Pavic <Josip.Pavic@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
.../amd/display/modules/power/power_helpers.c | 121 ++++++++++++++++--
1 file changed, 109 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
index b3810b864676..05e2be856037 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
@@ -66,6 +66,39 @@ static const unsigned char abm_config[abm_defines_max_config][abm_defines_max_le
{ 3, 6, 10, 12 }, /* Alt #3 - Super aggressiveness */
};
+struct abm_parameters {
+ unsigned char min_reduction;
+ unsigned char max_reduction;
+ unsigned char bright_pos_gain;
+ unsigned char dark_pos_gain;
+ unsigned char brightness_gain;
+ unsigned char contrast_factor;
+ unsigned char deviation_gain;
+ unsigned char min_knee;
+ unsigned char max_knee;
+};
+
+static const struct abm_parameters abm_settings_config0[abm_defines_max_level] = {
+// min_red max_red bright_pos dark_pos brightness_gain contrast deviation min_knee max_knee
+ {0xff, 0xbf, 0x20, 0x00, 0xff, 0x99, 0xb3, 0x40, 0xE0},
+ {0xff, 0x85, 0x20, 0x00, 0xff, 0x90, 0xa8, 0x40, 0xE0},
+ {0xff, 0x40, 0x20, 0x00, 0xff, 0x90, 0x68, 0x40, 0xE0},
+ {0x82, 0x4d, 0x20, 0x00, 0x00, 0x90, 0xb3, 0x70, 0x70},
+};
+
+static const struct abm_parameters abm_settings_config1[abm_defines_max_level] = {
+// min_red max_red bright_pos dark_pos brightness_gain contrast deviation min_knee max_knee
+ {0xf0, 0xd9, 0x20, 0x00, 0x00, 0xa8, 0xb3, 0x70, 0x70},
+ {0xcd, 0xa5, 0x20, 0x00, 0x00, 0xa8, 0xb3, 0x70, 0x70},
+ {0x99, 0x65, 0x20, 0x00, 0x00, 0xa8, 0xb3, 0x70, 0x70},
+ {0x82, 0x4d, 0x20, 0x00, 0x00, 0xa8, 0xb3, 0x70, 0x70},
+};
+
+static const struct abm_parameters * const abm_settings[] = {
+ abm_settings_config0,
+ abm_settings_config1,
+};
+
#define NUM_AMBI_LEVEL 5
#define NUM_AGGR_LEVEL 4
#define NUM_POWER_FN_SEGS 8
@@ -131,11 +164,13 @@ struct iram_table_v_2_2 {
uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x16 U0.8 */
uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x2a U2.6 */
uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x3e U2.6 */
- uint8_t hybridFactor[NUM_AGGR_LEVEL]; /* 0x52 U0.8 */
- uint8_t contrastFactor[NUM_AGGR_LEVEL]; /* 0x56 U0.8 */
+ uint8_t hybrid_factor[NUM_AGGR_LEVEL]; /* 0x52 U0.8 */
+ uint8_t contrast_factor[NUM_AGGR_LEVEL]; /* 0x56 U0.8 */
uint8_t deviation_gain[NUM_AGGR_LEVEL]; /* 0x5a U0.8 */
uint8_t iir_curve[NUM_AMBI_LEVEL]; /* 0x5e U0.8 */
- uint8_t pad[29]; /* 0x63 U0.8 */
+ uint8_t min_knee[NUM_AGGR_LEVEL]; /* 0x63 U0.8 */
+ uint8_t max_knee[NUM_AGGR_LEVEL]; /* 0x67 U0.8 */
+ uint8_t pad[21]; /* 0x6b U0.8 */
/* parameters for crgb conversion */
uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; /* 0x80 U3.13 */
@@ -501,15 +536,72 @@ void fill_iram_v_2_2(struct iram_table_v_2_2 *ram_table, struct dmcu_iram_parame
ram_table->dark_pos_gain[4][2] = 0x00;
ram_table->dark_pos_gain[4][3] = 0x00;
- ram_table->hybridFactor[0] = 0xff;
- ram_table->hybridFactor[1] = 0xff;
- ram_table->hybridFactor[2] = 0xff;
- ram_table->hybridFactor[3] = 0xc0;
+ ram_table->hybrid_factor[0] = 0xff;
+ ram_table->hybrid_factor[1] = 0xff;
+ ram_table->hybrid_factor[2] = 0xff;
+ ram_table->hybrid_factor[3] = 0xc0;
- ram_table->contrastFactor[0] = 0x99;
- ram_table->contrastFactor[1] = 0x99;
- ram_table->contrastFactor[2] = 0x90;
- ram_table->contrastFactor[3] = 0x80;
+ ram_table->contrast_factor[0] = 0x99;
+ ram_table->contrast_factor[1] = 0x99;
+ ram_table->contrast_factor[2] = 0x90;
+ ram_table->contrast_factor[3] = 0x80;
+
+ ram_table->iir_curve[0] = 0x65;
+ ram_table->iir_curve[1] = 0x65;
+ ram_table->iir_curve[2] = 0x65;
+ ram_table->iir_curve[3] = 0x65;
+ ram_table->iir_curve[4] = 0x65;
+
+ //Gamma 2.2
+ ram_table->crgb_thresh[0] = cpu_to_be16(0x127c);
+ ram_table->crgb_thresh[1] = cpu_to_be16(0x151b);
+ ram_table->crgb_thresh[2] = cpu_to_be16(0x17d5);
+ ram_table->crgb_thresh[3] = cpu_to_be16(0x1a56);
+ ram_table->crgb_thresh[4] = cpu_to_be16(0x1c83);
+ ram_table->crgb_thresh[5] = cpu_to_be16(0x1e72);
+ ram_table->crgb_thresh[6] = cpu_to_be16(0x20f0);
+ ram_table->crgb_thresh[7] = cpu_to_be16(0x232b);
+ ram_table->crgb_offset[0] = cpu_to_be16(0x2999);
+ ram_table->crgb_offset[1] = cpu_to_be16(0x3999);
+ ram_table->crgb_offset[2] = cpu_to_be16(0x4666);
+ ram_table->crgb_offset[3] = cpu_to_be16(0x5999);
+ ram_table->crgb_offset[4] = cpu_to_be16(0x6333);
+ ram_table->crgb_offset[5] = cpu_to_be16(0x7800);
+ ram_table->crgb_offset[6] = cpu_to_be16(0x8c00);
+ ram_table->crgb_offset[7] = cpu_to_be16(0xa000);
+ ram_table->crgb_slope[0] = cpu_to_be16(0x3609);
+ ram_table->crgb_slope[1] = cpu_to_be16(0x2dfa);
+ ram_table->crgb_slope[2] = cpu_to_be16(0x27ea);
+ ram_table->crgb_slope[3] = cpu_to_be16(0x235d);
+ ram_table->crgb_slope[4] = cpu_to_be16(0x2042);
+ ram_table->crgb_slope[5] = cpu_to_be16(0x1dc3);
+ ram_table->crgb_slope[6] = cpu_to_be16(0x1b1a);
+ ram_table->crgb_slope[7] = cpu_to_be16(0x1910);
+
+ fill_backlight_transform_table_v_2_2(
+ params, ram_table);
+}
+
+void fill_iram_v_2_3(struct iram_table_v_2_2 *ram_table, struct dmcu_iram_parameters params)
+{
+ unsigned int i, j;
+ unsigned int set = params.set;
+
+ ram_table->flags = 0x0;
+ for (i = 0; i < NUM_AGGR_LEVEL; i++) {
+ ram_table->hybrid_factor[i] = abm_settings[set][i].brightness_gain;
+ ram_table->contrast_factor[i] = abm_settings[set][i].contrast_factor;
+ ram_table->deviation_gain[i] = abm_settings[set][i].deviation_gain;
+ ram_table->min_knee[i] = abm_settings[set][i].min_knee;
+ ram_table->max_knee[i] = abm_settings[set][i].max_knee;
+
+ for (j = 0; j < NUM_AMBI_LEVEL; j++) {
+ ram_table->min_reduction[j][i] = abm_settings[set][i].min_reduction;
+ ram_table->max_reduction[j][i] = abm_settings[set][i].max_reduction;
+ ram_table->bright_pos_gain[j][i] = abm_settings[set][i].bright_pos_gain;
+ ram_table->dark_pos_gain[j][i] = abm_settings[set][i].dark_pos_gain;
+ }
+ }
ram_table->iir_curve[0] = 0x65;
ram_table->iir_curve[1] = 0x65;
@@ -561,7 +653,12 @@ bool dmcu_load_iram(struct dmcu *dmcu,
memset(&ram_table, 0, sizeof(ram_table));
- if (dmcu->dmcu_version.abm_version == 0x22) {
+ if (dmcu->dmcu_version.abm_version == 0x23) {
+ fill_iram_v_2_3((struct iram_table_v_2_2 *)ram_table, params);
+
+ result = dmcu->funcs->load_iram(
+ dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2_2);
+ } else if (dmcu->dmcu_version.abm_version == 0x22) {
fill_iram_v_2_2((struct iram_table_v_2_2 *)ram_table, params);
result = dmcu->funcs->load_iram(
--
2.17.1
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^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 06/36] drm/amd/display: fix dp stream enable
[not found] ` <20190819143515.21653-1-Bhawanpreet.Lakha-5C7GfCeVMHo@public.gmane.org>
` (4 preceding siblings ...)
2019-08-19 14:34 ` [PATCH 05/36] drm/amd/display: load iram for abm 2.3 Bhawanpreet Lakha
@ 2019-08-19 14:34 ` Bhawanpreet Lakha
2019-08-19 14:34 ` [PATCH 07/36] drm/amd/display: set Hratio and VRatio in dml Bhawanpreet Lakha
` (29 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Bhawanpreet Lakha @ 2019-08-19 14:34 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Dmytro Laktyushkin
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
A previous odm change broke stream enable by always setting
n_multiply as if odm was on.
This fixes the check for odm by making sure opp count is >1
rather than not 0.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 4 ++--
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index aee624371728..87ba8efc51ab 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1585,10 +1585,10 @@ void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
params.link_settings.link_rate = link_settings->link_rate;
if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
- if (optc1_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt)
+ if (optc1_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1)
params.timing.pix_clk_100hz /= 2;
pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine(
- pipe_ctx->stream_res.stream_enc, params.opp_cnt);
+ pipe_ctx->stream_res.stream_enc, params.opp_cnt > 1);
pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms);
}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
index 488fb5c71dd0..2ed3b561ebbd 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
@@ -466,7 +466,7 @@ void enc2_stream_encoder_dp_unblank(
uint64_t m_vid_l = n_vid;
/* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */
- if (is_two_pixels_per_containter(¶m->timing) || param->opp_cnt) {
+ if (is_two_pixels_per_containter(¶m->timing) || param->opp_cnt > 1) {
/*this logic should be the same in get_pixel_clock_parameters() */
n_multiply = 1;
}
--
2.17.1
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^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 07/36] drm/amd/display: set Hratio and VRatio in dml
[not found] ` <20190819143515.21653-1-Bhawanpreet.Lakha-5C7GfCeVMHo@public.gmane.org>
` (5 preceding siblings ...)
2019-08-19 14:34 ` [PATCH 06/36] drm/amd/display: fix dp stream enable Bhawanpreet Lakha
@ 2019-08-19 14:34 ` Bhawanpreet Lakha
2019-08-19 14:34 ` [PATCH 08/36] drm/amd/display: add null checks before logging Bhawanpreet Lakha
` (28 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Bhawanpreet Lakha @ 2019-08-19 14:34 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Ilya Bakoulin
From: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
Set the writeback Hratio and Vratio in dml.
Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index bd634dce6f3a..65cf4edddaff 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -466,6 +466,10 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib)
dout->wb.wb_dst_width;
mode_lib->vba.WritebackDestinationHeight[mode_lib->vba.NumberOfActivePlanes] =
dout->wb.wb_dst_height;
+ mode_lib->vba.WritebackHRatio[mode_lib->vba.NumberOfActivePlanes] =
+ dout->wb.wb_hratio;
+ mode_lib->vba.WritebackVRatio[mode_lib->vba.NumberOfActivePlanes] =
+ dout->wb.wb_vratio;
mode_lib->vba.WritebackPixelFormat[mode_lib->vba.NumberOfActivePlanes] =
(enum source_format_class) (dout->wb.wb_pixel_format);
mode_lib->vba.WritebackHTaps[mode_lib->vba.NumberOfActivePlanes] =
--
2.17.1
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 08/36] drm/amd/display: add null checks before logging
[not found] ` <20190819143515.21653-1-Bhawanpreet.Lakha-5C7GfCeVMHo@public.gmane.org>
` (6 preceding siblings ...)
2019-08-19 14:34 ` [PATCH 07/36] drm/amd/display: set Hratio and VRatio in dml Bhawanpreet Lakha
@ 2019-08-19 14:34 ` Bhawanpreet Lakha
2019-08-19 14:34 ` [PATCH 09/36] drm/amd/display: Implement voltage limitation stub Bhawanpreet Lakha
` (27 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Bhawanpreet Lakha @ 2019-08-19 14:34 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Wyatt Wood
From: Wyatt Wood <wyatt.wood@amd.com>
Adding NULL checks to various parameters in log_tf, to avoid
nullptr errors
Signed-off-by: Wyatt Wood <wyatt.wood@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: Nikola Cornij <Nikola.Cornij@amd.com>
---
.../gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index f6f20050e389..0e55df3db53c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1502,9 +1502,12 @@ dcn10_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
} else
dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS);
- log_tf(stream->ctx,
- stream->out_transfer_func,
- dpp->regamma_params.hw_points_num);
+ if (stream != NULL && stream->ctx != NULL &&
+ stream->out_transfer_func != NULL) {
+ log_tf(stream->ctx,
+ stream->out_transfer_func,
+ dpp->regamma_params.hw_points_num);
+ }
return true;
}
--
2.17.1
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 09/36] drm/amd/display: Implement voltage limitation stub
[not found] ` <20190819143515.21653-1-Bhawanpreet.Lakha-5C7GfCeVMHo@public.gmane.org>
` (7 preceding siblings ...)
2019-08-19 14:34 ` [PATCH 08/36] drm/amd/display: add null checks before logging Bhawanpreet Lakha
@ 2019-08-19 14:34 ` Bhawanpreet Lakha
2019-08-19 14:34 ` [PATCH 10/36] drm/amd/display: Zero-out dsc init regs Bhawanpreet Lakha
` (26 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Bhawanpreet Lakha @ 2019-08-19 14:34 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Joseph Gravenor
From: Joseph Gravenor <joseph.gravenor@amd.com>
add new function to get the voltage at the end of
dcn_validate_bandwidth, to check against the
highest voltage we allow.
Created a stub to allow for optimizations
Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: Sun peng Li <Sunpeng.Li@amd.com>
---
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 061c6e3a3088..383f4f8db8f4 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -705,6 +705,13 @@ static void hack_bounding_box(struct dcn_bw_internal_vars *v,
hack_force_pipe_split(v, context->streams[0]->timing.pix_clk_100hz);
}
+
+unsigned int get_highest_allowed_voltage_level(uint32_t hw_internal_rev)
+{
+ /* we are ok with all levels */
+ return 4;
+}
+
bool dcn_validate_bandwidth(
struct dc *dc,
struct dc_state *context,
@@ -732,6 +739,7 @@ bool dcn_validate_bandwidth(
memset(v, 0, sizeof(*v));
kernel_fpu_begin();
+
v->sr_exit_time = dc->dcn_soc->sr_exit_time;
v->sr_enter_plus_exit_time = dc->dcn_soc->sr_enter_plus_exit_time;
v->urgent_latency = dc->dcn_soc->urgent_latency;
@@ -1268,7 +1276,7 @@ bool dcn_validate_bandwidth(
PERFORMANCE_TRACE_END();
BW_VAL_TRACE_FINISH();
- if (bw_limit_pass && v->voltage_level != 5)
+ if (bw_limit_pass && v->voltage_level <= get_highest_allowed_voltage_level(dc->ctx->asic_id.hw_internal_rev))
return true;
else
return false;
--
2.17.1
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 10/36] drm/amd/display: Zero-out dsc init regs
[not found] ` <20190819143515.21653-1-Bhawanpreet.Lakha-5C7GfCeVMHo@public.gmane.org>
` (8 preceding siblings ...)
2019-08-19 14:34 ` [PATCH 09/36] drm/amd/display: Implement voltage limitation stub Bhawanpreet Lakha
@ 2019-08-19 14:34 ` Bhawanpreet Lakha
2019-08-19 14:34 ` [PATCH 11/36] drm/amd/display: refactor Device ID for external chips Bhawanpreet Lakha
` (25 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Bhawanpreet Lakha @ 2019-08-19 14:34 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Nikola Cornij
From: Nikola Cornij <nikola.cornij@amd.com>
[why]
Before a statically allocated PPS data structure, that did
get zeroed-out at startup, had been re-used for making packed PPS
SDP. With S3 fix, using a non-initialized PPS data structure was
introduced, while wrongly assuming it'd get initialized before it's
populated. As a consequence 'vbr_enable' and perhaps some other
fields are left uninitialized when making packed PPS SDP. This can
affect 'simple_422' as well because of the way PPS SDP packing is
done (the fields are not masked first, only shifted). The behavior
will be different, depending on the content of uninitialized data.
[how]
Zero-out PPS data structure at initialization time before it's
populated
Fixes: 3b87378c604e929015385e5cc76d0bbd55c05347
drm/amd/display: Set DSC before DIG front-end is connected to its back-end
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
index 379c9e4ac63b..c4f861e6bd53 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
@@ -447,6 +447,8 @@ static void dsc_init_reg_values(struct dsc_reg_values *reg_vals)
{
int i;
+ memset(reg_vals, 0, sizeof(struct dsc_reg_values));
+
/* Non-PPS values */
reg_vals->dsc_clock_enable = 1;
reg_vals->dsc_clock_gating_disable = 0;
--
2.17.1
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^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 11/36] drm/amd/display: refactor Device ID for external chips
[not found] ` <20190819143515.21653-1-Bhawanpreet.Lakha-5C7GfCeVMHo@public.gmane.org>
` (9 preceding siblings ...)
2019-08-19 14:34 ` [PATCH 10/36] drm/amd/display: Zero-out dsc init regs Bhawanpreet Lakha
@ 2019-08-19 14:34 ` Bhawanpreet Lakha
2019-08-19 14:34 ` [PATCH 12/36] drm/amd/display: Add VM page fault handle implementation Bhawanpreet Lakha
` (24 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Bhawanpreet Lakha @ 2019-08-19 14:34 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Qingqing Zhuo
From: Qingqing Zhuo <qingqing.zhuo@amd.com>
IEEE OUI will now be used while referring to certain vendors.
instead of normal index
Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
.../gpu/drm/amd/display/dc/core/dc_link_ddc.c | 2 +-
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 21 ++++++++++++++-----
.../amd/display/include/ddc_service_types.h | 10 +++++----
3 files changed, 23 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
index 94064d8ce303..7fd2d1358f1b 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
@@ -292,7 +292,7 @@ static uint32_t defer_delay_converter_wa(
{
struct dc_link *link = ddc->link;
- if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_4 &&
+ if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_0080E1 &&
!memcmp(link->dpcd_caps.branch_dev_name,
DP_DVI_CONVERTER_ID_4,
sizeof(link->dpcd_caps.branch_dev_name)))
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 2aa44b28b673..40067403b043 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2684,13 +2684,13 @@ static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
switch (link->dpcd_caps.branch_dev_id) {
- /* Some active dongles (DP-VGA, DP-DLDVI converters) power down
+ /* 0010FA active dongles (DP-VGA, DP-DLDVI converters) power down
* all internal circuits including AUX communication preventing
* reading DPCD table and EDID (spec violation).
* Encoder will skip DP RX power down on disable_output to
* keep receiver powered all the time.*/
- case DP_BRANCH_DEVICE_ID_1:
- case DP_BRANCH_DEVICE_ID_4:
+ case DP_BRANCH_DEVICE_ID_0010FA:
+ case DP_BRANCH_DEVICE_ID_0080E1:
link->wa_flags.dp_keep_receiver_powered = true;
break;
@@ -3394,7 +3394,13 @@ enum dp_panel_mode dp_get_panel_mode(struct dc_link *link)
if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) {
switch (link->dpcd_caps.branch_dev_id) {
- case DP_BRANCH_DEVICE_ID_2:
+ case DP_BRANCH_DEVICE_ID_0022B9:
+ /* alternate scrambler reset is required for Travis
+ * for the case when external chip does not
+ * provide sink device id, alternate scrambler
+ * scheme will be overriden later by querying
+ * Encoder features
+ */
if (strncmp(
link->dpcd_caps.branch_dev_name,
DP_VGA_LVDS_CONVERTER_ID_2,
@@ -3404,7 +3410,12 @@ enum dp_panel_mode dp_get_panel_mode(struct dc_link *link)
return DP_PANEL_MODE_SPECIAL;
}
break;
- case DP_BRANCH_DEVICE_ID_3:
+ case DP_BRANCH_DEVICE_ID_00001A:
+ /* alternate scrambler reset is required for Travis
+ * for the case when external chip does not provide
+ * sink device id, alternate scrambler scheme will
+ * be overriden later by querying Encoder feature
+ */
if (strncmp(link->dpcd_caps.branch_dev_name,
DP_VGA_LVDS_CONVERTER_ID_3,
sizeof(
diff --git a/drivers/gpu/drm/amd/display/include/ddc_service_types.h b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
index d968956a10cd..18961707db23 100644
--- a/drivers/gpu/drm/amd/display/include/ddc_service_types.h
+++ b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
@@ -25,10 +25,12 @@
#ifndef __DAL_DDC_SERVICE_TYPES_H__
#define __DAL_DDC_SERVICE_TYPES_H__
-#define DP_BRANCH_DEVICE_ID_1 0x0010FA
-#define DP_BRANCH_DEVICE_ID_2 0x0022B9
-#define DP_BRANCH_DEVICE_ID_3 0x00001A
-#define DP_BRANCH_DEVICE_ID_4 0x0080e1
+/* 0010FA dongles (ST Micro) external converter chip id */
+#define DP_BRANCH_DEVICE_ID_0010FA 0x0010FA
+/* 0022B9 external converter chip id */
+#define DP_BRANCH_DEVICE_ID_0022B9 0x0022B9
+#define DP_BRANCH_DEVICE_ID_00001A 0x00001A
+#define DP_BRANCH_DEVICE_ID_0080E1 0x0080e1
enum ddc_result {
DDC_RESULT_UNKNOWN = 0,
--
2.17.1
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 12/36] drm/amd/display: Add VM page fault handle implementation
[not found] ` <20190819143515.21653-1-Bhawanpreet.Lakha-5C7GfCeVMHo@public.gmane.org>
` (10 preceding siblings ...)
2019-08-19 14:34 ` [PATCH 11/36] drm/amd/display: refactor Device ID for external chips Bhawanpreet Lakha
@ 2019-08-19 14:34 ` Bhawanpreet Lakha
2019-08-19 14:34 ` [PATCH 13/36] drm/amd/display: cleaned up coding error in init_hw Bhawanpreet Lakha
` (23 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Bhawanpreet Lakha @ 2019-08-19 14:34 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Jaehyun Chung
From: Jaehyun Chung <jaehyun.chung@amd.com>
[How] Allocate memory for default page and program memory block addr
into default page addr register.
Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h | 6 +++++-
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c | 5 +++++
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h | 9 +++++++--
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 1 +
drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 2 ++
6 files changed, 21 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 3ef269f82478..6ee82ec6e28a 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -423,6 +423,7 @@ struct dc_phy_addr_space_config {
} gart_config;
bool valid;
+ uint64_t page_table_default_page_addr;
};
struct dc_virtual_addr_space_config {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
index 70e5d84fc69a..c8ae3023fda2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
@@ -119,6 +119,8 @@ struct dcn_hubbub_registers {
uint32_t DCN_VM_AGP_BOT;
uint32_t DCN_VM_AGP_TOP;
uint32_t DCN_VM_AGP_BASE;
+ uint32_t DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB;
+ uint32_t DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB;
};
/* set field name */
@@ -196,7 +198,9 @@ struct dcn_hubbub_registers {
type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A;\
type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B;\
type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;\
- type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D
+ type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;\
+ type DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB;\
+ type DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB
#define HUBBUB_STUTTER_REG_FIELD_LIST(type) \
type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A;\
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
index f13e039f8ef4..b83c022e2c6f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
@@ -380,6 +380,11 @@ int hubbub2_init_dchub_sys_ctx(struct hubbub *hubbub,
REG_SET(DCN_VM_AGP_BASE, 0,
AGP_BASE, pa_config->system_aperture.agp_base >> 24);
+ REG_SET(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0,
+ DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, (pa_config->page_table_default_page_addr >> 44) & 0xF);
+ REG_SET(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0,
+ DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, (pa_config->page_table_default_page_addr >> 12) & 0xFFFFFFFF);
+
if (pa_config->gart_config.page_table_start_addr != pa_config->gart_config.page_table_end_addr) {
phys_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr >> 12;
phys_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr >> 12;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h
index caf7273ca240..0d0caa6de935 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h
@@ -45,7 +45,10 @@
#define HUBBUB_REG_LIST_DCN20(id)\
HUBBUB_REG_LIST_DCN20_COMMON(), \
HUBBUB_SR_WATERMARK_REG_LIST(), \
- HUBBUB_VM_REG_LIST()
+ HUBBUB_VM_REG_LIST(),\
+ SR(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB),\
+ SR(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB)
+
#define HUBBUB_MASK_SH_LIST_DCN20(mask_sh)\
HUBBUB_MASK_SH_LIST_DCN_COMMON(mask_sh), \
@@ -56,7 +59,9 @@
HUBBUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET, mask_sh), \
HUBBUB_SF(DCN_VM_AGP_BOT, AGP_BOT, mask_sh), \
HUBBUB_SF(DCN_VM_AGP_TOP, AGP_TOP, mask_sh), \
- HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh)
+ HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh), \
+ HUBBUB_SF(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, mask_sh), \
+ HUBBUB_SF(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, mask_sh)
struct dcn20_hubbub {
struct hubbub base;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 87ba8efc51ab..4a74a4fb3ab9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1508,6 +1508,7 @@ static int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_ph
config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr;
config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr;
config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr;
+ config.page_table_default_page_addr = pa_config->page_table_default_page_addr;
return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);
}
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
index c1f29b1654d9..a6297219d7fc 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
@@ -80,6 +80,8 @@ struct dcn_hubbub_phys_addr_config {
uint64_t page_table_end_addr;
uint64_t page_table_base_addr;
} gart_config;
+
+ uint64_t page_table_default_page_addr;
};
struct dcn_hubbub_virt_addr_config {
--
2.17.1
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^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 13/36] drm/amd/display: cleaned up coding error in init_hw
[not found] ` <20190819143515.21653-1-Bhawanpreet.Lakha-5C7GfCeVMHo@public.gmane.org>
` (11 preceding siblings ...)
2019-08-19 14:34 ` [PATCH 12/36] drm/amd/display: Add VM page fault handle implementation Bhawanpreet Lakha
@ 2019-08-19 14:34 ` Bhawanpreet Lakha
2019-08-19 14:34 ` [PATCH 14/36] drm/amd/display: remove unused function Bhawanpreet Lakha
` (22 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Bhawanpreet Lakha @ 2019-08-19 14:34 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Martin Leung
From: Martin Leung <martin.leung@amd.com>
[why]
during a refactor a redundant code that has unknown behaviour was added.
[how]
removed old bad code
Fixes: 7b0b6ee982ab018ecce70f661e676d059bfe8270
drm/amd/display: Make init_hw and init_pipes generic for seamless boot
Signed-off-by: Martin Leung <martin.leung@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
.../gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 11 -----------
1 file changed, 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 0e55df3db53c..d9ce06b1d9c0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1267,19 +1267,8 @@ static void dcn10_init_hw(struct dc *dc)
*/
if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.power_down_display_on_boot) {
dc->hwss.init_pipes(dc, dc->current_state);
- for (i = 0; i < res_pool->pipe_count; i++) {
- struct hubp *hubp = res_pool->hubps[i];
- struct dpp *dpp = res_pool->dpps[i];
-
- hubp->funcs->hubp_init(hubp);
- res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst;
- dc->hwss.plane_atomic_power_down(dc, dpp, hubp);
- }
-
- apply_DEGVIDCN10_253_wa(dc);
}
-
for (i = 0; i < res_pool->audio_count; i++) {
struct audio *audio = res_pool->audios[i];
--
2.17.1
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^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 14/36] drm/amd/display: remove unused function
[not found] ` <20190819143515.21653-1-Bhawanpreet.Lakha-5C7GfCeVMHo@public.gmane.org>
` (12 preceding siblings ...)
2019-08-19 14:34 ` [PATCH 13/36] drm/amd/display: cleaned up coding error in init_hw Bhawanpreet Lakha
@ 2019-08-19 14:34 ` Bhawanpreet Lakha
2019-08-19 14:34 ` [PATCH 15/36] drm/amd/display: 3.2.47 Bhawanpreet Lakha
` (21 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Bhawanpreet Lakha @ 2019-08-19 14:34 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Qingqing Zhuo
From: Qingqing Zhuo <qingqing.zhuo@amd.com>
[Why]
This function is not being used, it was left in
when introducing DCN2
[How]
Remove the function
Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c | 1 -
drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 5 -----
2 files changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c
index d9e7c711a71c..40164ed015ea 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c
@@ -332,7 +332,6 @@ static struct opp_funcs dcn20_opp_funcs = {
.opp_set_disp_pattern_generator = opp2_set_disp_pattern_generator,
.dpg_is_blanked = opp2_dpg_is_blanked,
.opp_dpg_set_blank_color = opp2_dpg_set_blank_color,
- .opp_convert_pti = NULL,
.opp_destroy = opp1_destroy,
.opp_program_left_edge_extra_pixel = opp2_program_left_edge_extra_pixel,
};
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
index 5d8a7bcccc6f..957e9047381a 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
@@ -316,11 +316,6 @@ struct opp_funcs {
bool (*dpg_is_blanked)(
struct output_pixel_processor *opp);
- void (*opp_convert_pti)(
- struct output_pixel_processor *opp,
- bool enable,
- bool polarity);
-
void (*opp_dpg_set_blank_color)(
struct output_pixel_processor *opp,
const struct tg_color *color);
--
2.17.1
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 15/36] drm/amd/display: 3.2.47
[not found] ` <20190819143515.21653-1-Bhawanpreet.Lakha-5C7GfCeVMHo@public.gmane.org>
` (13 preceding siblings ...)
2019-08-19 14:34 ` [PATCH 14/36] drm/amd/display: remove unused function Bhawanpreet Lakha
@ 2019-08-19 14:34 ` Bhawanpreet Lakha
2019-08-19 14:34 ` [PATCH 16/36] drm/amd/display: Refactoring VTEM Bhawanpreet Lakha
` (20 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Bhawanpreet Lakha @ 2019-08-19 14:34 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Anthony Koo
From: Anthony Koo <Anthony.Koo@amd.com>
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 6ee82ec6e28a..239cb0952c61 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -39,7 +39,7 @@
#include "inc/hw/dmcu.h"
#include "dml/display_mode_lib.h"
-#define DC_VER "3.2.46"
+#define DC_VER "3.2.47"
#define MAX_SURFACES 3
#define MAX_PLANES 6
--
2.17.1
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^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 16/36] drm/amd/display: Refactoring VTEM
[not found] ` <20190819143515.21653-1-Bhawanpreet.Lakha-5C7GfCeVMHo@public.gmane.org>
` (14 preceding siblings ...)
2019-08-19 14:34 ` [PATCH 15/36] drm/amd/display: 3.2.47 Bhawanpreet Lakha
@ 2019-08-19 14:34 ` Bhawanpreet Lakha
2019-08-19 14:34 ` [PATCH 17/36] drm/amd/display: support spdif Bhawanpreet Lakha
` (19 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Bhawanpreet Lakha @ 2019-08-19 14:34 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Ahmad Othman
From: Ahmad Othman <ahmad.othman@amd.com>
[Why]
Video Timing Extended Metadata packet (VTEM) is not
specific to freesync. So move it out of freesync module
[How]
- Moved VTEM from freesync module to info_packet module
- Created new structure for VTEM parameters that can be used for VRR
and FVA
Signed-off-by: Ahmad Othman <ahmad.othman@amd.com>
Reviewed-by: Chris Park <Chris.Park@amd.com>
Acked-by: Ahmad Othman <Ahmad.Othman@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
.../amd/display/modules/freesync/freesync.c | 276 ++++--------------
.../amd/display/modules/inc/mod_freesync.h | 2 +
.../amd/display/modules/inc/mod_info_packet.h | 2 +-
.../display/modules/info_packet/info_packet.c | 88 ++++++
4 files changed, 148 insertions(+), 220 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index 000a9db9dad8..107d81ea689b 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -50,93 +50,6 @@ struct core_freesync {
struct dc *dc;
};
-void setFieldWithMask(unsigned char *dest, unsigned int mask, unsigned int value)
-{
- unsigned int shift = 0;
-
- if (!mask || !dest)
- return;
-
- while (!((mask >> shift) & 1))
- shift++;
-
- //reset
- *dest = *dest & ~mask;
- //set
- //dont let value span past mask
- value = value & (mask >> shift);
- //insert value
- *dest = *dest | (value << shift);
-}
-
-// VTEM Byte Offset
-#define VRR_VTEM_PB0 0
-#define VRR_VTEM_PB1 1
-#define VRR_VTEM_PB2 2
-#define VRR_VTEM_PB3 3
-#define VRR_VTEM_PB4 4
-#define VRR_VTEM_PB5 5
-#define VRR_VTEM_PB6 6
-
-#define VRR_VTEM_MD0 7
-#define VRR_VTEM_MD1 8
-#define VRR_VTEM_MD2 9
-#define VRR_VTEM_MD3 10
-
-
-// VTEM Byte Masks
-//PB0
-#define MASK__VRR_VTEM_PB0__RESERVED0 0x01
-#define MASK__VRR_VTEM_PB0__SYNC 0x02
-#define MASK__VRR_VTEM_PB0__VFR 0x04
-#define MASK__VRR_VTEM_PB0__AFR 0x08
-#define MASK__VRR_VTEM_PB0__DS_TYPE 0x30
- //0: Periodic pseudo-static EM Data Set
- //1: Periodic dynamic EM Data Set
- //2: Unique EM Data Set
- //3: Reserved
-#define MASK__VRR_VTEM_PB0__END 0x40
-#define MASK__VRR_VTEM_PB0__NEW 0x80
-
-//PB1
-#define MASK__VRR_VTEM_PB1__RESERVED1 0xFF
-
-//PB2
-#define MASK__VRR_VTEM_PB2__ORGANIZATION_ID 0xFF
- //0: This is a Vendor Specific EM Data Set
- //1: This EM Data Set is defined by This Specification (HDMI 2.1 r102.clean)
- //2: This EM Data Set is defined by CTA-861-G
- //3: This EM Data Set is defined by VESA
-//PB3
-#define MASK__VRR_VTEM_PB3__DATA_SET_TAG_MSB 0xFF
-//PB4
-#define MASK__VRR_VTEM_PB4__DATA_SET_TAG_LSB 0xFF
-//PB5
-#define MASK__VRR_VTEM_PB5__DATA_SET_LENGTH_MSB 0xFF
-//PB6
-#define MASK__VRR_VTEM_PB6__DATA_SET_LENGTH_LSB 0xFF
-
-
-
-//PB7-27 (20 bytes):
-//PB7 = MD0
-#define MASK__VRR_VTEM_MD0__VRR_EN 0x01
-#define MASK__VRR_VTEM_MD0__M_CONST 0x02
-#define MASK__VRR_VTEM_MD0__RESERVED2 0x0C
-#define MASK__VRR_VTEM_MD0__FVA_FACTOR_M1 0xF0
-
-//MD1
-#define MASK__VRR_VTEM_MD1__BASE_VFRONT 0xFF
-
-//MD2
-#define MASK__VRR_VTEM_MD2__BASE_REFRESH_RATE_98 0x03
-#define MASK__VRR_VTEM_MD2__RB 0x04
-#define MASK__VRR_VTEM_MD2__RESERVED3 0xF8
-
-//MD3
-#define MASK__VRR_VTEM_MD3__BASE_REFRESH_RATE_07 0xFF
-
-
#define MOD_FREESYNC_TO_CORE(mod_freesync)\
container_of(mod_freesync, struct core_freesync, public)
@@ -572,22 +485,64 @@ bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync,
return false;
}
-static void build_vrr_infopacket_header_vtem(enum signal_type signal,
+static void build_vrr_infopacket_data(const struct mod_vrr_params *vrr,
struct dc_info_packet *infopacket)
{
- // HEADER
-
- // HB0, HB1, HB2 indicates PacketType VTEMPacket
- infopacket->hb0 = 0x7F;
- infopacket->hb1 = 0xC0;
- infopacket->hb2 = 0x00; //sequence_index
-
- setFieldWithMask(&infopacket->sb[VRR_VTEM_PB0], MASK__VRR_VTEM_PB0__VFR, 1);
- setFieldWithMask(&infopacket->sb[VRR_VTEM_PB2], MASK__VRR_VTEM_PB2__ORGANIZATION_ID, 1);
- setFieldWithMask(&infopacket->sb[VRR_VTEM_PB3], MASK__VRR_VTEM_PB3__DATA_SET_TAG_MSB, 0);
- setFieldWithMask(&infopacket->sb[VRR_VTEM_PB4], MASK__VRR_VTEM_PB4__DATA_SET_TAG_LSB, 1);
- setFieldWithMask(&infopacket->sb[VRR_VTEM_PB5], MASK__VRR_VTEM_PB5__DATA_SET_LENGTH_MSB, 0);
- setFieldWithMask(&infopacket->sb[VRR_VTEM_PB6], MASK__VRR_VTEM_PB6__DATA_SET_LENGTH_LSB, 4);
+ /* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */
+ infopacket->sb[1] = 0x1A;
+
+ /* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */
+ infopacket->sb[2] = 0x00;
+
+ /* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */
+ infopacket->sb[3] = 0x00;
+
+ /* PB4 = Reserved */
+
+ /* PB5 = Reserved */
+
+ /* PB6 = [Bits 7:3 = Reserved] */
+
+ /* PB6 = [Bit 0 = FreeSync Supported] */
+ if (vrr->state != VRR_STATE_UNSUPPORTED)
+ infopacket->sb[6] |= 0x01;
+
+ /* PB6 = [Bit 1 = FreeSync Enabled] */
+ if (vrr->state != VRR_STATE_DISABLED &&
+ vrr->state != VRR_STATE_UNSUPPORTED)
+ infopacket->sb[6] |= 0x02;
+
+ /* PB6 = [Bit 2 = FreeSync Active] */
+ if (vrr->state == VRR_STATE_ACTIVE_VARIABLE ||
+ vrr->state == VRR_STATE_ACTIVE_FIXED)
+ infopacket->sb[6] |= 0x04;
+
+ /* PB7 = FreeSync Minimum refresh rate (Hz) */
+ infopacket->sb[7] = (unsigned char)(vrr->min_refresh_in_uhz / 1000000);
+
+ /* PB8 = FreeSync Maximum refresh rate (Hz)
+ * Note: We should never go above the field rate of the mode timing set.
+ */
+ infopacket->sb[8] = (unsigned char)(vrr->max_refresh_in_uhz / 1000000);
+
+
+ //FreeSync HDR
+ infopacket->sb[9] = 0;
+ infopacket->sb[10] = 0;
+}
+
+static void build_vrr_infopacket_fs2_data(enum color_transfer_func app_tf,
+ struct dc_info_packet *infopacket)
+{
+ if (app_tf != TRANSFER_FUNC_UNKNOWN) {
+ infopacket->valid = true;
+
+ infopacket->sb[6] |= 0x08; // PB6 = [Bit 3 = Native Color Active]
+
+ if (app_tf == TRANSFER_FUNC_GAMMA_22) {
+ infopacket->sb[9] |= 0x04; // PB6 = [Bit 2 = Gamma 2.2 EOTF Active]
+ }
+ }
}
static void build_vrr_infopacket_header_v1(enum signal_type signal,
@@ -688,105 +643,6 @@ static void build_vrr_infopacket_header_v2(enum signal_type signal,
}
}
-static void build_vrr_vtem_infopacket_data(const struct dc_stream_state *stream,
- const struct mod_vrr_params *vrr,
- struct dc_info_packet *infopacket)
-{
- unsigned int fieldRateInHz;
-
- if (vrr->state == VRR_STATE_ACTIVE_VARIABLE ||
- vrr->state == VRR_STATE_ACTIVE_FIXED) {
- setFieldWithMask(&infopacket->sb[VRR_VTEM_MD0], MASK__VRR_VTEM_MD0__VRR_EN, 1);
- } else {
- setFieldWithMask(&infopacket->sb[VRR_VTEM_MD0], MASK__VRR_VTEM_MD0__VRR_EN, 0);
- }
-
- if (!stream->timing.vic) {
- setFieldWithMask(&infopacket->sb[VRR_VTEM_MD1], MASK__VRR_VTEM_MD1__BASE_VFRONT,
- stream->timing.v_front_porch);
-
-
- /* TODO: In dal2, we check mode flags for a reduced blanking timing.
- * Need a way to relay that information to this function.
- * if("ReducedBlanking")
- * {
- * setFieldWithMask(&infopacket->sb[VRR_VTEM_MD2], MASK__VRR_VTEM_MD2__RB, 1;
- * }
- */
-
- //TODO: DAL2 does FixPoint and rounding. Here we might need to account for that
- fieldRateInHz = (stream->timing.pix_clk_100hz * 100)/
- (stream->timing.h_total * stream->timing.v_total);
-
- setFieldWithMask(&infopacket->sb[VRR_VTEM_MD2], MASK__VRR_VTEM_MD2__BASE_REFRESH_RATE_98,
- fieldRateInHz >> 8);
- setFieldWithMask(&infopacket->sb[VRR_VTEM_MD3], MASK__VRR_VTEM_MD3__BASE_REFRESH_RATE_07,
- fieldRateInHz);
-
- }
- infopacket->valid = true;
-}
-
-static void build_vrr_infopacket_data(const struct mod_vrr_params *vrr,
- struct dc_info_packet *infopacket)
-{
- /* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */
- infopacket->sb[1] = 0x1A;
-
- /* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */
- infopacket->sb[2] = 0x00;
-
- /* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */
- infopacket->sb[3] = 0x00;
-
- /* PB4 = Reserved */
-
- /* PB5 = Reserved */
-
- /* PB6 = [Bits 7:3 = Reserved] */
-
- /* PB6 = [Bit 0 = FreeSync Supported] */
- if (vrr->state != VRR_STATE_UNSUPPORTED)
- infopacket->sb[6] |= 0x01;
-
- /* PB6 = [Bit 1 = FreeSync Enabled] */
- if (vrr->state != VRR_STATE_DISABLED &&
- vrr->state != VRR_STATE_UNSUPPORTED)
- infopacket->sb[6] |= 0x02;
-
- /* PB6 = [Bit 2 = FreeSync Active] */
- if (vrr->state == VRR_STATE_ACTIVE_VARIABLE ||
- vrr->state == VRR_STATE_ACTIVE_FIXED)
- infopacket->sb[6] |= 0x04;
-
- /* PB7 = FreeSync Minimum refresh rate (Hz) */
- infopacket->sb[7] = (unsigned char)(vrr->min_refresh_in_uhz / 1000000);
-
- /* PB8 = FreeSync Maximum refresh rate (Hz)
- * Note: We should never go above the field rate of the mode timing set.
- */
- infopacket->sb[8] = (unsigned char)(vrr->max_refresh_in_uhz / 1000000);
-
-
- //FreeSync HDR
- infopacket->sb[9] = 0;
- infopacket->sb[10] = 0;
-}
-
-static void build_vrr_infopacket_fs2_data(enum color_transfer_func app_tf,
- struct dc_info_packet *infopacket)
-{
- if (app_tf != TRANSFER_FUNC_UNKNOWN) {
- infopacket->valid = true;
-
- infopacket->sb[6] |= 0x08; // PB6 = [Bit 3 = Native Color Active]
-
- if (app_tf == TRANSFER_FUNC_GAMMA_22) {
- infopacket->sb[9] |= 0x04; // PB6 = [Bit 2 = Gamma 2.2 EOTF Active]
- }
- }
-}
-
static void build_vrr_infopacket_checksum(unsigned int *payload_size,
struct dc_info_packet *infopacket)
{
@@ -839,21 +695,6 @@ static void build_vrr_infopacket_v2(enum signal_type signal,
infopacket->valid = true;
}
-static void build_vrr_infopacket_vtem(const struct dc_stream_state *stream,
- const struct mod_vrr_params *vrr,
- struct dc_info_packet *infopacket)
-{
- //VTEM info packet for HdmiVrr
-
- memset(infopacket, 0, sizeof(struct dc_info_packet));
-
- //VTEM Packet is structured differently
- build_vrr_infopacket_header_vtem(stream->signal, infopacket);
- build_vrr_vtem_infopacket_data(stream, vrr, infopacket);
-
- infopacket->valid = true;
-}
-
void mod_freesync_build_vrr_infopacket(struct mod_freesync *mod_freesync,
const struct dc_stream_state *stream,
const struct mod_vrr_params *vrr,
@@ -866,16 +707,13 @@ void mod_freesync_build_vrr_infopacket(struct mod_freesync *mod_freesync,
* Check if Freesync is supported. Return if false. If true,
* set the corresponding bit in the info packet
*/
- if (!vrr->supported || (!vrr->send_info_frame && packet_type != PACKET_TYPE_VTEM))
+ if (!vrr->supported || (!vrr->send_info_frame))
return;
switch (packet_type) {
case PACKET_TYPE_FS2:
build_vrr_infopacket_v2(stream->signal, vrr, app_tf, infopacket);
break;
- case PACKET_TYPE_VTEM:
- build_vrr_infopacket_vtem(stream, vrr, infopacket);
- break;
case PACKET_TYPE_VRR:
case PACKET_TYPE_FS1:
default:
diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
index dcef85994c45..dc187844d10b 100644
--- a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
+++ b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
@@ -173,4 +173,6 @@ bool mod_freesync_is_valid_range(struct mod_freesync *mod_freesync,
uint32_t min_refresh_request_in_uhz,
uint32_t max_refresh_request_in_uhz);
+
+
#endif
diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h b/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h
index 5b1c9a4c7643..d930bdecb117 100644
--- a/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h
+++ b/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h
@@ -27,10 +27,10 @@
#define MOD_INFO_PACKET_H_
#include "mod_shared.h"
-
//Forward Declarations
struct dc_stream_state;
struct dc_info_packet;
+struct mod_vrr_params;
void mod_build_vsc_infopacket(const struct dc_stream_state *stream,
struct dc_info_packet *info_packet);
diff --git a/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c b/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
index bc13c552797f..5f4b98df3d92 100644
--- a/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
+++ b/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
@@ -27,9 +27,78 @@
#include "core_types.h"
#include "dc_types.h"
#include "mod_shared.h"
+#include "mod_freesync.h"
+#include "dc.h"
#define HDMI_INFOFRAME_TYPE_VENDOR 0x81
+// VTEM Byte Offset
+#define VTEM_PB0 0
+#define VTEM_PB1 1
+#define VTEM_PB2 2
+#define VTEM_PB3 3
+#define VTEM_PB4 4
+#define VTEM_PB5 5
+#define VTEM_PB6 6
+
+#define VTEM_MD0 7
+#define VTEM_MD1 8
+#define VTEM_MD2 9
+#define VTEM_MD3 10
+
+
+// VTEM Byte Masks
+//PB0
+#define MASK_VTEM_PB0__RESERVED0 0x01
+#define MASK_VTEM_PB0__SYNC 0x02
+#define MASK_VTEM_PB0__VFR 0x04
+#define MASK_VTEM_PB0__AFR 0x08
+#define MASK_VTEM_PB0__DS_TYPE 0x30
+ //0: Periodic pseudo-static EM Data Set
+ //1: Periodic dynamic EM Data Set
+ //2: Unique EM Data Set
+ //3: Reserved
+#define MASK_VTEM_PB0__END 0x40
+#define MASK_VTEM_PB0__NEW 0x80
+
+//PB1
+#define MASK_VTEM_PB1__RESERVED1 0xFF
+
+//PB2
+#define MASK_VTEM_PB2__ORGANIZATION_ID 0xFF
+ //0: This is a Vendor Specific EM Data Set
+ //1: This EM Data Set is defined by This Specification (HDMI 2.1 r102.clean)
+ //2: This EM Data Set is defined by CTA-861-G
+ //3: This EM Data Set is defined by VESA
+//PB3
+#define MASK_VTEM_PB3__DATA_SET_TAG_MSB 0xFF
+//PB4
+#define MASK_VTEM_PB4__DATA_SET_TAG_LSB 0xFF
+//PB5
+#define MASK_VTEM_PB5__DATA_SET_LENGTH_MSB 0xFF
+//PB6
+#define MASK_VTEM_PB6__DATA_SET_LENGTH_LSB 0xFF
+
+
+
+//PB7-27 (20 bytes):
+//PB7 = MD0
+#define MASK_VTEM_MD0__VRR_EN 0x01
+#define MASK_VTEM_MD0__M_CONST 0x02
+#define MASK_VTEM_MD0__RESERVED2 0x0C
+#define MASK_VTEM_MD0__FVA_FACTOR_M1 0xF0
+
+//MD1
+#define MASK_VTEM_MD1__BASE_VFRONT 0xFF
+
+//MD2
+#define MASK_VTEM_MD2__BASE_REFRESH_RATE_98 0x03
+#define MASK_VTEM_MD2__RB 0x04
+#define MASK_VTEM_MD2__RESERVED3 0xF8
+
+//MD3
+#define MASK_VTEM_MD3__BASE_REFRESH_RATE_07 0xFF
+
enum ColorimetryRGBDP {
ColorimetryRGB_DP_sRGB = 0,
ColorimetryRGB_DP_AdobeRGB = 3,
@@ -45,6 +114,25 @@ enum ColorimetryYCCDP {
ColorimetryYCC_DP_ITU2020YCbCr = 7,
};
+void setFieldWithMask(unsigned char *dest, unsigned int mask, unsigned int value)
+{
+ unsigned int shift = 0;
+
+ if (!mask || !dest)
+ return;
+
+ while (!((mask >> shift) & 1))
+ shift++;
+
+ //reset
+ *dest = *dest & ~mask;
+ //set
+ //dont let value span past mask
+ value = value & (mask >> shift);
+ //insert value
+ *dest = *dest | (value << shift);
+}
+
void mod_build_vsc_infopacket(const struct dc_stream_state *stream,
struct dc_info_packet *info_packet)
{
--
2.17.1
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^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 17/36] drm/amd/display: support spdif
[not found] ` <20190819143515.21653-1-Bhawanpreet.Lakha-5C7GfCeVMHo@public.gmane.org>
` (15 preceding siblings ...)
2019-08-19 14:34 ` [PATCH 16/36] drm/amd/display: Refactoring VTEM Bhawanpreet Lakha
@ 2019-08-19 14:34 ` Bhawanpreet Lakha
2019-08-19 14:34 ` [PATCH 18/36] drm/amd/display: fix stuck test pattern on right half of display Bhawanpreet Lakha
` (18 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Bhawanpreet Lakha @ 2019-08-19 14:34 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Charlene Liu
From: Charlene Liu <charlene.liu@amd.com>
[Description]
port spdif fix to staging:
spdif hardwired to afmt inst 1.
spdif func pointer
spdif resource allocation (reserve last audio endpoint for spdif only)
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 17 ++++++++---------
drivers/gpu/drm/amd/display/dc/dce/dce_audio.c | 4 ++--
2 files changed, 10 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 1464f4c60089..953ba4d02a1e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -259,12 +259,10 @@ bool resource_construct(
DC_ERR("DC: failed to create audio!\n");
return false;
}
-
if (!aud->funcs->endpoint_valid(aud)) {
aud->funcs->destroy(&aud);
break;
}
-
pool->audios[i] = aud;
pool->audio_count++;
}
@@ -1618,24 +1616,25 @@ static struct audio *find_first_free_audio(
const struct resource_pool *pool,
enum engine_id id)
{
- int i;
- for (i = 0; i < pool->audio_count; i++) {
+ int i, available_audio_count;
+
+ available_audio_count = pool->audio_count;
+
+ for (i = 0; i < available_audio_count; i++) {
if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) {
/*we have enough audio endpoint, find the matching inst*/
if (id != i)
continue;
-
return pool->audios[i];
}
}
- /* use engine id to find free audio */
- if ((id < pool->audio_count) && (res_ctx->is_audio_acquired[id] == false)) {
+ /* use engine id to find free audio */
+ if ((id < available_audio_count) && (res_ctx->is_audio_acquired[id] == false)) {
return pool->audios[id];
}
-
/*not found the matching one, first come first serve*/
- for (i = 0; i < pool->audio_count; i++) {
+ for (i = 0; i < available_audio_count; i++) {
if (res_ctx->is_audio_acquired[i] == false) {
return pool->audios[i];
}
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
index b7d63ca126df..bdcc3c8a6a91 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
@@ -611,6 +611,8 @@ void dce_aud_az_configure(
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1,
value);
+ DC_LOG_HW_AUDIO("\n\tAUDIO:az_configure: index: %u data, 0x%x, displayName %s: \n",
+ audio->inst, value, audio_info->display_name);
/*
*write the port ID:
@@ -920,7 +922,6 @@ static const struct audio_funcs funcs = {
.az_configure = dce_aud_az_configure,
.destroy = dce_aud_destroy,
};
-
void dce_aud_destroy(struct audio **audio)
{
struct dce_audio *aud = DCE_AUD(*audio);
@@ -951,7 +952,6 @@ struct audio *dce_audio_create(
audio->regs = reg;
audio->shifts = shifts;
audio->masks = masks;
-
return &audio->base;
}
--
2.17.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 18/36] drm/amd/display: fix stuck test pattern on right half of display
[not found] ` <20190819143515.21653-1-Bhawanpreet.Lakha-5C7GfCeVMHo@public.gmane.org>
` (16 preceding siblings ...)
2019-08-19 14:34 ` [PATCH 17/36] drm/amd/display: support spdif Bhawanpreet Lakha
@ 2019-08-19 14:34 ` Bhawanpreet Lakha
2019-08-19 14:34 ` [PATCH 19/36] drm/amd/display: fix trigger not generated for freesync Bhawanpreet Lakha
` (17 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Bhawanpreet Lakha @ 2019-08-19 14:34 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Zi Yu Liao
From: Zi Yu Liao <ziyu.liao@amd.com>
[why]
With visual confirm enabled, displays where ODM combine is enabled
has a test pattern stuck on the right half of the display even
though the display is unblanked.
[how]
Add a condition to not show the colour ramp test pattern when the
display is unblanked.
Signed-off-by: Zi Yu Liao <ziyu.liao@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 4a74a4fb3ab9..31a985858bae 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -892,7 +892,7 @@ void dcn20_blank_pixel_data(
for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
odm_pipe->stream_res.opp->funcs->opp_set_disp_pattern_generator(
odm_pipe->stream_res.opp,
- dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE ?
+ dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE && blank ?
CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern,
stream->timing.display_color_depth,
&black_color,
--
2.17.1
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^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 19/36] drm/amd/display: fix trigger not generated for freesync
[not found] ` <20190819143515.21653-1-Bhawanpreet.Lakha-5C7GfCeVMHo@public.gmane.org>
` (17 preceding siblings ...)
2019-08-19 14:34 ` [PATCH 18/36] drm/amd/display: fix stuck test pattern on right half of display Bhawanpreet Lakha
@ 2019-08-19 14:34 ` Bhawanpreet Lakha
2019-08-19 14:34 ` [PATCH 20/36] drm/amd/display: fix odm pipe copy Bhawanpreet Lakha
` (16 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Bhawanpreet Lakha @ 2019-08-19 14:34 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Yogesh Mohan Marimuthu
From: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com>
[Why]
In newer hardware MANUAL_FLOW_CONTROL is not a trigger bit. Due to this
front porch is fixed and in these hardware freesync does not work.
[How]
Change the programming to generate a pulse so that the event will be
triggered, front porch will be cut short and freesync will work.
Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
index e5e5be63032b..e98e6bab4808 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
@@ -825,6 +825,9 @@ void optc1_program_manual_trigger(struct timing_generator *optc)
REG_SET(OTG_MANUAL_FLOW_CONTROL, 0,
MANUAL_FLOW_CONTROL, 1);
+
+ REG_SET(OTG_MANUAL_FLOW_CONTROL, 0,
+ MANUAL_FLOW_CONTROL, 0);
}
--
2.17.1
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^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 20/36] drm/amd/display: fix odm pipe copy
[not found] ` <20190819143515.21653-1-Bhawanpreet.Lakha-5C7GfCeVMHo@public.gmane.org>
` (18 preceding siblings ...)
2019-08-19 14:34 ` [PATCH 19/36] drm/amd/display: fix trigger not generated for freesync Bhawanpreet Lakha
@ 2019-08-19 14:34 ` Bhawanpreet Lakha
2019-08-19 14:35 ` [PATCH 21/36] drm/amd/display: Fix number of slices not being checked for dsc Bhawanpreet Lakha
` (15 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Bhawanpreet Lakha @ 2019-08-19 14:34 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Dmytro Laktyushkin
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
ODM next and prev pipe were missing from dc_copy_state
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 6 ++++++
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 2b5299e40d66..e09c639685fc 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1227,6 +1227,12 @@ struct dc_state *dc_copy_state(struct dc_state *src_ctx)
if (cur_pipe->bottom_pipe)
cur_pipe->bottom_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
+ if (cur_pipe->prev_odm_pipe)
+ cur_pipe->prev_odm_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx];
+
+ if (cur_pipe->next_odm_pipe)
+ cur_pipe->next_odm_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx];
+
}
for (i = 0; i < new_ctx->stream_count; i++) {
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 40067403b043..f5742719b5d9 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -3188,7 +3188,7 @@ bool dc_link_dp_set_test_pattern(
memset(&training_pattern, 0, sizeof(training_pattern));
for (i = 0; i < MAX_PIPES; i++) {
- if (pipes[i].stream->link == link) {
+ if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
pipe_ctx = &pipes[i];
break;
}
--
2.17.1
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^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 21/36] drm/amd/display: Fix number of slices not being checked for dsc
[not found] ` <20190819143515.21653-1-Bhawanpreet.Lakha-5C7GfCeVMHo@public.gmane.org>
` (19 preceding siblings ...)
2019-08-19 14:34 ` [PATCH 20/36] drm/amd/display: fix odm pipe copy Bhawanpreet Lakha
@ 2019-08-19 14:35 ` Bhawanpreet Lakha
2019-08-19 14:35 ` [PATCH 22/36] drm/amd/display: fix dcn20 odm dpp programming Bhawanpreet Lakha
` (14 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Bhawanpreet Lakha @ 2019-08-19 14:35 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Nikola Cornij
From: Nikola Cornij <nikola.cornij@amd.com>
[why]
num_slices_h was not being checked
[How]
Fix the typo and check num_slices_h
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
index c4f861e6bd53..1b419407af94 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
@@ -322,7 +322,7 @@ static bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_
dsc_cfg->dc_dsc_cfg.linebuf_depth == 0)));
ASSERT(96 <= dsc_cfg->dc_dsc_cfg.bits_per_pixel && dsc_cfg->dc_dsc_cfg.bits_per_pixel <= 0x3ff); // 6.0 <= bits_per_pixel <= 63.9375
- if (!dsc_cfg->dc_dsc_cfg.num_slices_v || !dsc_cfg->dc_dsc_cfg.num_slices_v ||
+ if (!dsc_cfg->dc_dsc_cfg.num_slices_v || !dsc_cfg->dc_dsc_cfg.num_slices_h ||
!(dsc_cfg->dc_dsc_cfg.version_minor == 1 || dsc_cfg->dc_dsc_cfg.version_minor == 2) ||
!dsc_cfg->pic_width || !dsc_cfg->pic_height ||
!((dsc_cfg->dc_dsc_cfg.version_minor == 1 && // v1.1 line buffer depth range:
--
2.17.1
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^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 22/36] drm/amd/display: fix dcn20 odm dpp programming
[not found] ` <20190819143515.21653-1-Bhawanpreet.Lakha-5C7GfCeVMHo@public.gmane.org>
` (20 preceding siblings ...)
2019-08-19 14:35 ` [PATCH 21/36] drm/amd/display: Fix number of slices not being checked for dsc Bhawanpreet Lakha
@ 2019-08-19 14:35 ` Bhawanpreet Lakha
2019-08-19 14:35 ` [PATCH 23/36] drm/amd/display: fix odm stream release Bhawanpreet Lakha
` (13 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Bhawanpreet Lakha @ 2019-08-19 14:35 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Dmytro Laktyushkin
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
dcn20 requires special casing for odm.
This change treats odm as alternative to mpc tree on dcn20.
This is planned to be fixed in a future refactor
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 1 +
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 7 ++++++-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index e09c639685fc..ac55644247ca 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2023,6 +2023,7 @@ static void commit_planes_for_stream(struct dc *dc,
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
if (!pipe_ctx->top_pipe &&
+ !pipe_ctx->prev_odm_pipe &&
pipe_ctx->stream &&
pipe_ctx->stream == stream) {
struct dc_stream_status *stream_status = NULL;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 31a985858bae..99733e1a8958 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1058,8 +1058,13 @@ static void dcn20_program_all_pipe_in_tree(
if (pipe_ctx->plane_state != NULL)
dcn20_program_pipe(dc, pipe_ctx, context);
- if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx)
+ if (pipe_ctx->bottom_pipe != NULL) {
+ ASSERT(pipe_ctx->bottom_pipe != pipe_ctx);
dcn20_program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
+ } else if (pipe_ctx->next_odm_pipe != NULL) {
+ ASSERT(pipe_ctx->next_odm_pipe != pipe_ctx);
+ dcn20_program_all_pipe_in_tree(dc, pipe_ctx->next_odm_pipe, context);
+ }
}
void dcn20_pipe_control_lock_global(
--
2.17.1
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^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 23/36] drm/amd/display: fix odm stream release
[not found] ` <20190819143515.21653-1-Bhawanpreet.Lakha-5C7GfCeVMHo@public.gmane.org>
` (21 preceding siblings ...)
2019-08-19 14:35 ` [PATCH 22/36] drm/amd/display: fix dcn20 odm dpp programming Bhawanpreet Lakha
@ 2019-08-19 14:35 ` Bhawanpreet Lakha
2019-08-19 14:35 ` [PATCH 24/36] drm/amd/display: fix odm validation Bhawanpreet Lakha
` (12 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Bhawanpreet Lakha @ 2019-08-19 14:35 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Dmytro Laktyushkin
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Need to memset all odm pipes when calling dc_remove_stream_from_ctx
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 65 +++++++++----------
1 file changed, 32 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 953ba4d02a1e..6e88cb0fffce 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1111,13 +1111,12 @@ struct pipe_ctx *resource_get_head_pipe_for_stream(
struct dc_stream_state *stream)
{
int i;
+
for (i = 0; i < MAX_PIPES; i++) {
if (res_ctx->pipe_ctx[i].stream == stream
&& !res_ctx->pipe_ctx[i].top_pipe
- && !res_ctx->pipe_ctx[i].prev_odm_pipe) {
+ && !res_ctx->pipe_ctx[i].prev_odm_pipe)
return &res_ctx->pipe_ctx[i];
- break;
- }
}
return NULL;
}
@@ -1694,45 +1693,45 @@ enum dc_status dc_remove_stream_from_ctx(
{
int i;
struct dc_context *dc_ctx = dc->ctx;
- struct pipe_ctx *del_pipe = NULL;
+ struct pipe_ctx *del_pipe = resource_get_head_pipe_for_stream(&new_ctx->res_ctx, stream);
+ struct pipe_ctx *odm_pipe;
- /* Release primary pipe */
- for (i = 0; i < MAX_PIPES; i++) {
- if (new_ctx->res_ctx.pipe_ctx[i].stream == stream &&
- !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
- del_pipe = &new_ctx->res_ctx.pipe_ctx[i];
+ if (!del_pipe) {
+ DC_ERROR("Pipe not found for stream %p !\n", stream);
+ return DC_ERROR_UNEXPECTED;
+ }
- ASSERT(del_pipe->stream_res.stream_enc);
- update_stream_engine_usage(
- &new_ctx->res_ctx,
- dc->res_pool,
- del_pipe->stream_res.stream_enc,
- false);
+ odm_pipe = del_pipe->next_odm_pipe;
- if (del_pipe->stream_res.audio)
- update_audio_usage(
- &new_ctx->res_ctx,
- dc->res_pool,
- del_pipe->stream_res.audio,
- false);
+ /* Release primary pipe */
+ ASSERT(del_pipe->stream_res.stream_enc);
+ update_stream_engine_usage(
+ &new_ctx->res_ctx,
+ dc->res_pool,
+ del_pipe->stream_res.stream_enc,
+ false);
- resource_unreference_clock_source(&new_ctx->res_ctx,
- dc->res_pool,
- del_pipe->clock_source);
+ if (del_pipe->stream_res.audio)
+ update_audio_usage(
+ &new_ctx->res_ctx,
+ dc->res_pool,
+ del_pipe->stream_res.audio,
+ false);
- if (dc->res_pool->funcs->remove_stream_from_ctx)
- dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream);
+ resource_unreference_clock_source(&new_ctx->res_ctx,
+ dc->res_pool,
+ del_pipe->clock_source);
- memset(del_pipe, 0, sizeof(*del_pipe));
+ if (dc->res_pool->funcs->remove_stream_from_ctx)
+ dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream);
- break;
- }
- }
+ while (odm_pipe) {
+ struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;
- if (!del_pipe) {
- DC_ERROR("Pipe not found for stream %p !\n", stream);
- return DC_ERROR_UNEXPECTED;
+ memset(odm_pipe, 0, sizeof(*odm_pipe));
+ odm_pipe = next_odm_pipe;
}
+ memset(del_pipe, 0, sizeof(*del_pipe));
for (i = 0; i < new_ctx->stream_count; i++)
if (new_ctx->streams[i] == stream)
--
2.17.1
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^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 24/36] drm/amd/display: fix odm validation
[not found] ` <20190819143515.21653-1-Bhawanpreet.Lakha-5C7GfCeVMHo@public.gmane.org>
` (22 preceding siblings ...)
2019-08-19 14:35 ` [PATCH 23/36] drm/amd/display: fix odm stream release Bhawanpreet Lakha
@ 2019-08-19 14:35 ` Bhawanpreet Lakha
2019-08-19 14:35 ` [PATCH 25/36] drm/amd/display: add Cursor Degamma logic for DCN2 Bhawanpreet Lakha
` (11 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Bhawanpreet Lakha @ 2019-08-19 14:35 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Dmytro Laktyushkin
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Update bw validation to use prev and next odm pipe pointers
for populating dml inputs.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 40 +++++++++----------
1 file changed, 19 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index aa1342ccf8b4..477885816854 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1600,12 +1600,8 @@ static bool dcn20_split_stream_for_odm(
struct pipe_ctx *next_odm_pipe)
{
int pipe_idx = next_odm_pipe->pipe_idx;
- struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data;
- struct pipe_ctx *sec_next_pipe = next_odm_pipe->next_odm_pipe;
- int new_width;
*next_odm_pipe = *prev_odm_pipe;
- next_odm_pipe->next_odm_pipe = sec_next_pipe;
next_odm_pipe->pipe_idx = pipe_idx;
next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx];
@@ -1627,11 +1623,11 @@ static bool dcn20_split_stream_for_odm(
ASSERT(next_odm_pipe->top_pipe == NULL);
if (prev_odm_pipe->plane_state) {
+ struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data;
+ int new_width;
+
/* HACTIVE halved for odm combine */
sd->h_active /= 2;
- /* Copy scl_data to secondary pipe */
- next_odm_pipe->plane_res.scl_data = *sd;
-
/* Calculate new vp and recout for left pipe */
/* Need at least 16 pixels width per side */
if (sd->recout.x + 16 >= sd->h_active)
@@ -1645,10 +1641,12 @@ static bool dcn20_split_stream_for_odm(
/* Calculate new vp and recout for right pipe */
sd = &next_odm_pipe->plane_res.scl_data;
- new_width = sd->recout.width + sd->recout.x - sd->h_active;
+ /* HACTIVE halved for odm combine */
+ sd->h_active /= 2;
/* Need at least 16 pixels width per side */
if (new_width <= 16)
return false;
+ new_width = sd->recout.width + sd->recout.x - sd->h_active;
sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
sd->ratios.horz, sd->recout.width - new_width));
sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
@@ -1818,6 +1816,19 @@ int dcn20_populate_dml_pipes_from_context(
pipes[pipe_cnt].dout.dp_lanes = 4;
pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min;
pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max;
+ pipes[pipe_cnt].pipe.dest.odm_combine = res_ctx->pipe_ctx[i].prev_odm_pipe
+ || res_ctx->pipe_ctx[i].next_odm_pipe;
+ pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
+ if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state
+ == res_ctx->pipe_ctx[i].plane_state)
+ pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx;
+ else if (res_ctx->pipe_ctx[i].prev_odm_pipe) {
+ struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].prev_odm_pipe;
+
+ while (first_pipe->prev_odm_pipe)
+ first_pipe = first_pipe->prev_odm_pipe;
+ pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx;
+ }
switch (res_ctx->pipe_ctx[i].stream->signal) {
case SIGNAL_TYPE_DISPLAY_PORT_MST:
@@ -1870,7 +1881,6 @@ int dcn20_populate_dml_pipes_from_context(
break;
}
-
switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) {
case PIXEL_ENCODING_RGB:
case PIXEL_ENCODING_YCBCR444:
@@ -1892,10 +1902,6 @@ int dcn20_populate_dml_pipes_from_context(
pipes[pipe_cnt].dout.output_format = dm_444;
pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
}
- pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
- if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state
- == res_ctx->pipe_ctx[i].plane_state)
- pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx;
/* todo: default max for now, until there is logic reflecting this in dc*/
pipes[pipe_cnt].dout.output_bpc = 12;
@@ -1944,14 +1950,6 @@ int dcn20_populate_dml_pipes_from_context(
&& res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln)
|| (res_ctx->pipe_ctx[i].top_pipe
&& res_ctx->pipe_ctx[i].top_pipe->plane_state == pln);
- pipes[pipe_cnt].pipe.dest.odm_combine = (res_ctx->pipe_ctx[i].bottom_pipe
- && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln
- && res_ctx->pipe_ctx[i].bottom_pipe->stream_res.opp
- != res_ctx->pipe_ctx[i].stream_res.opp)
- || (res_ctx->pipe_ctx[i].top_pipe
- && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln
- && res_ctx->pipe_ctx[i].top_pipe->stream_res.opp
- != res_ctx->pipe_ctx[i].stream_res.opp);
pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90
|| pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz;
pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y;
--
2.17.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 25/36] drm/amd/display: add Cursor Degamma logic for DCN2
[not found] ` <20190819143515.21653-1-Bhawanpreet.Lakha-5C7GfCeVMHo@public.gmane.org>
` (23 preceding siblings ...)
2019-08-19 14:35 ` [PATCH 24/36] drm/amd/display: fix odm validation Bhawanpreet Lakha
@ 2019-08-19 14:35 ` Bhawanpreet Lakha
2019-08-19 14:35 ` [PATCH 26/36] drm/amd/display: Enable HW rotation Bhawanpreet Lakha
` (10 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Bhawanpreet Lakha @ 2019-08-19 14:35 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Bayan Zabihiyan
From: Bayan Zabihiyan <bayan.zabihiyan@amd.com>
[Why]
We need to have the ability to to tell us set degamma on the cursor.
[How]
Pass a flag down to register programming that tells us if the
current surface format needs cursor degamma.
Signed-off-by: Bayan Zabihiyan <bayan.zabihiyan@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 3 ++-
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 3 ++-
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 2 +-
.../gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c | 10 +++++++---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h | 2 +-
drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h | 2 +-
7 files changed, 15 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index 929c4eadc1dc..f35826d5d1e5 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -516,7 +516,8 @@ union dc_cursor_attribute_flags {
uint32_t INVERT_PIXEL_DATA:1;
uint32_t ZERO_EXPANSION:1;
uint32_t MIN_MAX_INVERT:1;
- uint32_t RESERVED:25;
+ uint32_t ENABLE_CURSOR_DEGAMMA:1;
+ uint32_t RESERVED:24;
} bits;
uint32_t value;
};
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
index b95ec73fcae3..23b2361cec62 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
@@ -426,8 +426,9 @@ void dpp1_cnv_setup (
void dpp1_set_cursor_attributes(
struct dpp *dpp_base,
- enum dc_cursor_color_format color_format)
+ struct dc_cursor_attributes *cursor_attributes)
{
+ enum dc_cursor_color_format color_format = cursor_attributes->color_format;
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
REG_UPDATE_2(CURSOR0_CONTROL,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
index 8a5517eebb7c..e2c613611ac9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
@@ -1368,7 +1368,7 @@ enum dcn10_input_csc_select {
void dpp1_set_cursor_attributes(
struct dpp *dpp_base,
- enum dc_cursor_color_format color_format);
+ struct dc_cursor_attributes *cursor_attributes);
void dpp1_set_cursor_position(
struct dpp *dpp_base,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index d9ce06b1d9c0..bfd402bede94 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2986,7 +2986,7 @@ static void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(
pipe_ctx->plane_res.hubp, attributes);
pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(
- pipe_ctx->plane_res.dpp, attributes->color_format);
+ pipe_ctx->plane_res.dpp, attributes);
}
static void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
index db311574f42f..2f5aade1e882 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
@@ -342,14 +342,18 @@ void dpp2_cnv_set_alpha_keyer(
void dpp2_set_cursor_attributes(
struct dpp *dpp_base,
- enum dc_cursor_color_format color_format)
+ struct dc_cursor_attributes *cursor_attributes)
{
+ enum dc_cursor_color_format color_format = cursor_attributes->color_format;
struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
int cur_rom_en = 0;
if (color_format == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA ||
- color_format == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA)
- cur_rom_en = 1;
+ color_format == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA) {
+ if (cursor_attributes->attribute_flags.bits.ENABLE_CURSOR_DEGAMMA) {
+ cur_rom_en = 1;
+ }
+ }
REG_UPDATE_3(CURSOR0_CONTROL,
CUR0_MODE, color_format,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h
index 1f5d99a6d240..290b2854bd2c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h
@@ -676,7 +676,7 @@ void dscl2_calc_lb_num_partitions(
void dpp2_set_cursor_attributes(
struct dpp *dpp_base,
- enum dc_cursor_color_format color_format);
+ struct dc_cursor_attributes *cursor_attributes);
void dpp2_dummy_program_input_lut(
struct dpp *dpp_base,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
index 9b69a06ab46f..474c7194a9f8 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
@@ -201,7 +201,7 @@ struct dpp_funcs {
void (*set_cursor_attributes)(
struct dpp *dpp_base,
- enum dc_cursor_color_format color_format);
+ struct dc_cursor_attributes *cursor_attributes);
void (*set_cursor_position)(
struct dpp *dpp_base,
--
2.17.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 26/36] drm/amd/display: Enable HW rotation
[not found] ` <20190819143515.21653-1-Bhawanpreet.Lakha-5C7GfCeVMHo@public.gmane.org>
` (24 preceding siblings ...)
2019-08-19 14:35 ` [PATCH 25/36] drm/amd/display: add Cursor Degamma logic for DCN2 Bhawanpreet Lakha
@ 2019-08-19 14:35 ` Bhawanpreet Lakha
2019-08-19 14:35 ` [PATCH 27/36] drm/amd/display: Add Logging for Gamma Related information Bhawanpreet Lakha
` (9 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Bhawanpreet Lakha @ 2019-08-19 14:35 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Jaehyun Chung
From: Jaehyun Chung <jaehyun.chung@amd.com>
[Why] HW rotation is not enabled. Calculations for cursor rotation
are wrong for the values passed to set_cursor_position.
[How] Swap Src rect and height and vertically mirror surface for
the correct surface rotation direction. Cursor position is rotated
according to angle. Offset calculations are tweaked for non-rotated
cursor hotspot and width/height.
Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
.../gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 13 +++++++
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 34 +++++++++++++++++++
.../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 18 +++++++---
3 files changed, 60 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
index 23b2361cec62..d8b2da18db39 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
@@ -457,6 +457,19 @@ void dpp1_set_cursor_position(
int src_y_offset = pos->y - pos->y_hotspot - param->viewport.y;
uint32_t cur_en = pos->enable ? 1 : 0;
+ // Cursor width/height and hotspots need to be rotated for offset calculation
+ if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) {
+ swap(width, height);
+ if (param->rotation == ROTATION_ANGLE_90) {
+ src_x_offset = pos->x - pos->y_hotspot - param->viewport.x;
+ src_y_offset = pos->y - pos->x_hotspot - param->viewport.y;
+ }
+ } else if (param->rotation == ROTATION_ANGLE_180) {
+ src_x_offset = pos->x - param->viewport.x;
+ src_y_offset = pos->y - param->viewport.y;
+ }
+
+
if (src_x_offset >= (int)param->viewport.width)
cur_en = 0; /* not visible beyond right edge*/
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index bfd402bede94..004675db686d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2975,6 +2975,40 @@ static void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
== PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
pos_cpy.enable = false;
+ // Swap axis and mirror horizontally
+ if (param.rotation == ROTATION_ANGLE_90) {
+ uint32_t temp_x = pos_cpy.x;
+ pos_cpy.x = pipe_ctx->plane_res.scl_data.viewport.width -
+ (pos_cpy.y - pipe_ctx->plane_res.scl_data.viewport.x) + pipe_ctx->plane_res.scl_data.viewport.x;
+ pos_cpy.y = temp_x;
+ }
+ // Swap axis and mirror vertically
+ else if (param.rotation == ROTATION_ANGLE_270) {
+ uint32_t temp_y = pos_cpy.y;
+ if (pos_cpy.x > pipe_ctx->plane_res.scl_data.viewport.height) {
+ pos_cpy.x = pos_cpy.x - pipe_ctx->plane_res.scl_data.viewport.height;
+ pos_cpy.y = pipe_ctx->plane_res.scl_data.viewport.height - pos_cpy.x;
+ } else {
+ pos_cpy.y = 2 * pipe_ctx->plane_res.scl_data.viewport.height - pos_cpy.x;
+ }
+ pos_cpy.x = temp_y;
+ }
+ // Mirror horizontally and vertically
+ else if (param.rotation == ROTATION_ANGLE_180) {
+ if (pos_cpy.x >= pipe_ctx->plane_res.scl_data.viewport.width + pipe_ctx->plane_res.scl_data.viewport.x) {
+ pos_cpy.x = 2 * pipe_ctx->plane_res.scl_data.viewport.width
+ - pos_cpy.x + 2 * pipe_ctx->plane_res.scl_data.viewport.x;
+ } else {
+ uint32_t temp_x = pos_cpy.x;
+ pos_cpy.x = 2 * pipe_ctx->plane_res.scl_data.viewport.x - pos_cpy.x;
+ if (temp_x >= pipe_ctx->plane_res.scl_data.viewport.x + (int)hubp->curs_attr.width
+ || pos_cpy.x <= (int)hubp->curs_attr.width + pipe_ctx->plane_state->src_rect.x) {
+ pos_cpy.x = temp_x + pipe_ctx->plane_res.scl_data.viewport.width;
+ }
+ }
+ pos_cpy.y = pipe_ctx->plane_res.scl_data.viewport.height - pos_cpy.y;
+ }
+
hubp->funcs->set_cursor_position(hubp, &pos_cpy, ¶m);
dpp->funcs->set_cursor_position(dpp, &pos_cpy, ¶m, hubp->curs_attr.width, hubp->curs_attr.height);
}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
index b4b384c7fa9b..69e2aae42394 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
@@ -945,6 +945,8 @@ void hubp2_cursor_set_position(
int src_y_offset = pos->y - pos->y_hotspot - param->viewport.y;
int x_hotspot = pos->x_hotspot;
int y_hotspot = pos->y_hotspot;
+ int cursor_height = (int)hubp->curs_attr.height;
+ int cursor_width = (int)hubp->curs_attr.width;
uint32_t dst_x_offset;
uint32_t cur_en = pos->enable ? 1 : 0;
@@ -958,10 +960,16 @@ void hubp2_cursor_set_position(
if (hubp->curs_attr.address.quad_part == 0)
return;
+ // Rotated cursor width/height and hotspots tweaks for offset calculation
if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) {
- src_x_offset = pos->y - pos->y_hotspot - param->viewport.x;
- y_hotspot = pos->x_hotspot;
- x_hotspot = pos->y_hotspot;
+ swap(cursor_height, cursor_width);
+ if (param->rotation == ROTATION_ANGLE_90) {
+ src_x_offset = pos->x - pos->y_hotspot - param->viewport.x;
+ src_y_offset = pos->y - pos->x_hotspot - param->viewport.y;
+ }
+ } else if (param->rotation == ROTATION_ANGLE_180) {
+ src_x_offset = pos->x - param->viewport.x;
+ src_y_offset = pos->y - param->viewport.y;
}
if (param->mirror) {
@@ -983,13 +991,13 @@ void hubp2_cursor_set_position(
if (src_x_offset >= (int)param->viewport.width)
cur_en = 0; /* not visible beyond right edge*/
- if (src_x_offset + (int)hubp->curs_attr.width <= 0)
+ if (src_x_offset + cursor_width <= 0)
cur_en = 0; /* not visible beyond left edge*/
if (src_y_offset >= (int)param->viewport.height)
cur_en = 0; /* not visible beyond bottom edge*/
- if (src_y_offset + (int)hubp->curs_attr.height <= 0)
+ if (src_y_offset + cursor_height <= 0)
cur_en = 0; /* not visible beyond top edge*/
if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)
--
2.17.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 27/36] drm/amd/display: Add Logging for Gamma Related information
[not found] ` <20190819143515.21653-1-Bhawanpreet.Lakha-5C7GfCeVMHo@public.gmane.org>
` (25 preceding siblings ...)
2019-08-19 14:35 ` [PATCH 26/36] drm/amd/display: Enable HW rotation Bhawanpreet Lakha
@ 2019-08-19 14:35 ` Bhawanpreet Lakha
2019-08-19 14:35 ` [PATCH 28/36] drm/amd/display: set av_mute in hw_init for HDMI Bhawanpreet Lakha
` (8 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Bhawanpreet Lakha @ 2019-08-19 14:35 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Wyatt Wood
From: Wyatt Wood <wyatt.wood@amd.com>
[Why]
A recent bug showed that logging would be useful in debugging
various gamma issues.
[How]
Add logging in dc.
Fix formatting for easier graphing.
Signed-off-by: Wyatt Wood <wyatt.wood@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
.../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 12 ++++++------
.../gpu/drm/amd/display/modules/color/color_gamma.c | 4 ++--
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 004675db686d..0e7d929c254c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1451,15 +1451,15 @@ static void log_tf(struct dc_context *ctx,
DC_LOG_ALL_TF_CHANNELS("Logging all channels...");
for (i = 0; i < hw_points_num; i++) {
- DC_LOG_GAMMA("R %d %llu\n", i, tf->tf_pts.red[i].value);
- DC_LOG_ALL_TF_CHANNELS("G %d, %llu\n", i, tf->tf_pts.green[i].value);
- DC_LOG_ALL_TF_CHANNELS("B %d, %llu\n", i, tf->tf_pts.blue[i].value);
+ DC_LOG_GAMMA("R\t%d\t%llu\n", i, tf->tf_pts.red[i].value);
+ DC_LOG_ALL_TF_CHANNELS("G\t%d\t%llu\n", i, tf->tf_pts.green[i].value);
+ DC_LOG_ALL_TF_CHANNELS("B\t%d\t%llu\n", i, tf->tf_pts.blue[i].value);
}
for (i = hw_points_num; i < MAX_NUM_HW_POINTS; i++) {
- DC_LOG_ALL_GAMMA("R %d %llu\n", i, tf->tf_pts.red[i].value);
- DC_LOG_ALL_TF_CHANNELS("G %d %llu\n", i, tf->tf_pts.green[i].value);
- DC_LOG_ALL_TF_CHANNELS("B %d %llu\n", i, tf->tf_pts.blue[i].value);
+ DC_LOG_ALL_GAMMA("R\t%d\t%llu\n", i, tf->tf_pts.red[i].value);
+ DC_LOG_ALL_TF_CHANNELS("G\t%d\t%llu\n", i, tf->tf_pts.green[i].value);
+ DC_LOG_ALL_TF_CHANNELS("B\t%d\t%llu\n", i, tf->tf_pts.blue[i].value);
}
}
diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
index 8f78ea226dae..19475cf5ab72 100644
--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
@@ -99,10 +99,10 @@ void log_x_points_distribution(struct dal_logger *logger)
int i = 0;
if (logger != NULL) {
- LOG_GAMMA_WRITE("]Log X Distribution\n");
+ LOG_GAMMA_WRITE("Log X Distribution\n");
for (i = 0; i < MAX_HW_POINTS; i++)
- LOG_GAMMA_WRITE("]%llu\n", coordinates_x[i].x.value);
+ LOG_GAMMA_WRITE("%llu\n", coordinates_x[i].x.value);
}
}
--
2.17.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 28/36] drm/amd/display: set av_mute in hw_init for HDMI
[not found] ` <20190819143515.21653-1-Bhawanpreet.Lakha-5C7GfCeVMHo@public.gmane.org>
` (26 preceding siblings ...)
2019-08-19 14:35 ` [PATCH 27/36] drm/amd/display: Add Logging for Gamma Related information Bhawanpreet Lakha
@ 2019-08-19 14:35 ` Bhawanpreet Lakha
2019-08-19 14:35 ` [PATCH 29/36] drm/amd/display: MST topology debugfs Bhawanpreet Lakha
` (7 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Bhawanpreet Lakha @ 2019-08-19 14:35 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Charlene Liu
From: Charlene Liu <charlene.liu@amd.com>
[Description]
OS will reserve HW state in UEFI mode.
Driver init_hw reset to RGB which caused HDMI green in YCbCr mode.
read HW blank_color based on acc_mode.
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
.../amd/display/dc/dcn10/dcn10_link_encoder.c | 23 +++++++++++++++++++
.../amd/display/dc/dcn10/dcn10_link_encoder.h | 2 ++
.../amd/display/dc/dcn20/dcn20_link_encoder.c | 1 +
.../drm/amd/display/dc/inc/hw/link_encoder.h | 2 ++
4 files changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
index e4c7ecd87de7..4034f7787a35 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
@@ -86,6 +86,7 @@ static const struct link_encoder_funcs dcn10_lnk_enc_funcs = {
.disable_hpd = dcn10_link_encoder_disable_hpd,
.is_dig_enabled = dcn10_is_dig_enabled,
.get_dig_frontend = dcn10_get_dig_frontend,
+ .get_dig_mode = dcn10_get_dig_mode,
.destroy = dcn10_link_encoder_destroy
};
@@ -1394,3 +1395,25 @@ void dcn10_aux_initialize(struct dcn10_link_encoder *enc10)
AUX_REG_UPDATE(AUX_DPHY_RX_CONTROL0,
AUX_RX_RECEIVE_WINDOW, 0);
}
+
+enum signal_type dcn10_get_dig_mode(
+ struct link_encoder *enc)
+{
+ struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+ uint32_t value;
+ REG_GET(DIG_BE_CNTL, DIG_MODE, &value);
+ switch (value) {
+ case 1:
+ return SIGNAL_TYPE_DISPLAY_PORT;
+ case 2:
+ return SIGNAL_TYPE_DVI_SINGLE_LINK;
+ case 3:
+ return SIGNAL_TYPE_HDMI_TYPE_A;
+ case 5:
+ return SIGNAL_TYPE_DISPLAY_PORT_MST;
+ default:
+ return SIGNAL_TYPE_NONE;
+ }
+ return SIGNAL_TYPE_NONE;
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
index f3e57343417c..8bf5f0f2301d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
@@ -515,4 +515,6 @@ unsigned int dcn10_get_dig_frontend(struct link_encoder *enc);
void dcn10_aux_initialize(struct dcn10_link_encoder *enc10);
+enum signal_type dcn10_get_dig_mode(
+ struct link_encoder *enc);
#endif /* __DC_LINK_ENCODER__DCN10_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
index f495582e9e87..e476f27aa3a9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
@@ -341,6 +341,7 @@ static const struct link_encoder_funcs dcn20_link_enc_funcs = {
.fec_set_enable = enc2_fec_set_enable,
.fec_set_ready = enc2_fec_set_ready,
.fec_is_active = enc2_fec_is_active,
+ .get_dig_mode = dcn10_get_dig_mode,
.get_dig_frontend = dcn10_get_dig_frontend,
};
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
index 7001bfbd6681..abb4e4237fb6 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
@@ -184,6 +184,8 @@ struct link_encoder_funcs {
bool (*fec_is_active)(struct link_encoder *enc);
#endif
bool (*is_in_alt_mode) (struct link_encoder *enc);
+ enum signal_type (*get_dig_mode)(
+ struct link_encoder *enc);
};
#endif /* LINK_ENCODER_H_ */
--
2.17.1
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 29/36] drm/amd/display: MST topology debugfs
[not found] ` <20190819143515.21653-1-Bhawanpreet.Lakha-5C7GfCeVMHo@public.gmane.org>
` (27 preceding siblings ...)
2019-08-19 14:35 ` [PATCH 28/36] drm/amd/display: set av_mute in hw_init for HDMI Bhawanpreet Lakha
@ 2019-08-19 14:35 ` Bhawanpreet Lakha
2019-08-19 14:35 ` [PATCH 30/36] drm/amd/display: fix DML not calculating delivery time Bhawanpreet Lakha
` (6 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Bhawanpreet Lakha @ 2019-08-19 14:35 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: David Francis
From: David Francis <David.Francis@amd.com>
DRM provides drm_dp_mst_dump_topology, which prints
useful information about MST devices
Hook this up to a debugfs file named amdgpu_mst_topology
Signed-off-by: David Francis <David.Francis@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 24 +++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 406129e67e79..97bbb934cc04 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -1051,9 +1051,33 @@ static int target_backlight_read(struct seq_file *m, void *data)
return 0;
}
+static int mst_topo(struct seq_file *m, void *unused)
+{
+ struct drm_info_node *node = (struct drm_info_node *)m->private;
+ struct drm_device *dev = node->minor->dev;
+ struct drm_connector *connector;
+ struct drm_connector_list_iter conn_iter;
+ struct amdgpu_dm_connector *aconnector;
+
+ drm_connector_list_iter_begin(dev, &conn_iter);
+ drm_for_each_connector_iter(connector, &conn_iter) {
+ if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
+ continue;
+
+ aconnector = to_amdgpu_dm_connector(connector);
+
+ seq_printf(m, "\nMST topology for connector %d\n", aconnector->connector_id);
+ drm_dp_mst_dump_topology(m, &aconnector->mst_mgr);
+ }
+ drm_connector_list_iter_end(&conn_iter);
+
+ return 0;
+}
+
static const struct drm_info_list amdgpu_dm_debugfs_list[] = {
{"amdgpu_current_backlight_pwm", ¤t_backlight_read},
{"amdgpu_target_backlight_pwm", &target_backlight_read},
+ {"amdgpu_mst_topology", &mst_topo},
};
/*
--
2.17.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 30/36] drm/amd/display: fix DML not calculating delivery time
[not found] ` <20190819143515.21653-1-Bhawanpreet.Lakha-5C7GfCeVMHo@public.gmane.org>
` (28 preceding siblings ...)
2019-08-19 14:35 ` [PATCH 29/36] drm/amd/display: MST topology debugfs Bhawanpreet Lakha
@ 2019-08-19 14:35 ` Bhawanpreet Lakha
2019-08-19 14:35 ` [PATCH 31/36] drm/amd/display: Expose OTG_V_TOTAL_MID for HW Diags Bhawanpreet Lakha
` (5 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Bhawanpreet Lakha @ 2019-08-19 14:35 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Jun Lei
From: Jun Lei <Jun.Lei@amd.com>
[why]
Calculating DCFCLK DS time requires calculating
delivery time for luma/chroma, but this value is
not calculated in DMLv2, it was inadvertently
removed when porting DMLv2
[how]
Add the calculation back
Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
.../dc/dml/dcn20/display_mode_vba_20v2.c | 27 +++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
index 22455db54980..0fafd693ffb4 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
@@ -1475,6 +1475,33 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP
/ mode_lib->vba.ReturnBW;
mode_lib->vba.LastPixelOfLineExtraWatermark = 0;
+ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
+ if (mode_lib->vba.VRatio[k] <= 1.0)
+ mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k] =
+ (double) mode_lib->vba.SwathWidthY[k]
+ * mode_lib->vba.DPPPerPlane[k]
+ / mode_lib->vba.HRatio[k]
+ / mode_lib->vba.PixelClock[k];
+ else
+ mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k] =
+ (double) mode_lib->vba.SwathWidthY[k]
+ / mode_lib->vba.PSCL_THROUGHPUT_LUMA[k]
+ / mode_lib->vba.DPPCLK[k];
+
+ if (mode_lib->vba.BytePerPixelDETC[k] == 0)
+ mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k] = 0.0;
+ else if (mode_lib->vba.VRatio[k] / 2.0 <= 1.0)
+ mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k] =
+ mode_lib->vba.SwathWidthY[k] / 2.0
+ * mode_lib->vba.DPPPerPlane[k]
+ / (mode_lib->vba.HRatio[k] / 2.0)
+ / mode_lib->vba.PixelClock[k];
+ else
+ mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k] =
+ mode_lib->vba.SwathWidthY[k] / 2.0
+ / mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k]
+ / mode_lib->vba.DPPCLK[k];
+ }
mode_lib->vba.UrgentExtraLatency = mode_lib->vba.UrgentRoundTripAndOutOfOrderLatency
+ (mode_lib->vba.TotalActiveDPP * mode_lib->vba.PixelChunkSizeInKByte
--
2.17.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 31/36] drm/amd/display: Expose OTG_V_TOTAL_MID for HW Diags
[not found] ` <20190819143515.21653-1-Bhawanpreet.Lakha-5C7GfCeVMHo@public.gmane.org>
` (29 preceding siblings ...)
2019-08-19 14:35 ` [PATCH 30/36] drm/amd/display: fix DML not calculating delivery time Bhawanpreet Lakha
@ 2019-08-19 14:35 ` Bhawanpreet Lakha
2019-08-19 14:35 ` [PATCH 32/36] drm/amd/display: Use res_cap to acquire i2c instead of pipe count Bhawanpreet Lakha
` (4 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Bhawanpreet Lakha @ 2019-08-19 14:35 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Bayan Zabihiyan
From: Bayan Zabihiyan <bayan.zabihiyan@amd.com>
[Why]
Existing HW Features, HW Diags test requested that the
registers be exposed.
[How]
Add V_TOTAL_MID to existing DC structures.
Make sure values are passed down throughout DC
Add Register definition.
Program the additional registers
Add additional Logic for V_TOTAL_CONTROL.
Signed-off-by: Bayan Zabihiyan <bayan.zabihiyan@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 4 +++-
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 2 ++
.../drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 3 ++-
.../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 5 ++++-
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 12 ++++++++++++
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h | 8 ++++++++
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 2 ++
.../gpu/drm/amd/display/dc/inc/hw/timing_generator.h | 2 ++
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 3 ++-
9 files changed, 37 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index ac55644247ca..6904f1591ada 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -288,7 +288,9 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc,
dc->hwss.set_drr(&pipe,
1,
adjust->v_total_min,
- adjust->v_total_max);
+ adjust->v_total_max,
+ adjust->v_total_mid,
+ adjust->v_total_mid_frame_num);
ret = true;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index f35826d5d1e5..0b8700a8a94a 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -757,6 +757,8 @@ struct crtc_trigger_info {
struct dc_crtc_timing_adjust {
uint32_t v_total_min;
uint32_t v_total_max;
+ uint32_t v_total_mid;
+ uint32_t v_total_mid_frame_num;
};
#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index c2d026ba269f..c273490ddcab 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1716,7 +1716,8 @@ void dce110_set_safe_displaymarks(
******************************************************************************/
static void set_drr(struct pipe_ctx **pipe_ctx,
- int num_pipes, int vmin, int vmax)
+ int num_pipes, unsigned int vmin, unsigned int vmax,
+ unsigned int vmid, unsigned int vmid_frame_number)
{
int i = 0;
struct drr_params params = {0};
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 0e7d929c254c..3272da955b6d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2746,7 +2746,8 @@ static void dcn10_optimize_bandwidth(
}
static void dcn10_set_drr(struct pipe_ctx **pipe_ctx,
- int num_pipes, int vmin, int vmax)
+ int num_pipes, unsigned int vmin, unsigned int vmax,
+ unsigned int vmid, unsigned int vmid_frame_number)
{
int i = 0;
struct drr_params params = {0};
@@ -2755,6 +2756,8 @@ static void dcn10_set_drr(struct pipe_ctx **pipe_ctx,
params.vertical_total_max = vmax;
params.vertical_total_min = vmin;
+ params.vertical_total_mid = vmid;
+ params.vertical_total_mid_frame_num = vmid_frame_number;
/* TODO: If multiple pipes are to be supported, you need
* some GSL stuff. Static screen triggers may be programmed differently
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
index e98e6bab4808..e74a07d03fde 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
@@ -850,6 +850,18 @@ void optc1_set_drr(
params->vertical_total_max > 0 &&
params->vertical_total_min > 0) {
+ if (params->vertical_total_mid != 0) {
+
+ REG_SET(OTG_V_TOTAL_MID, 0,
+ OTG_V_TOTAL_MID, params->vertical_total_mid - 1);
+
+ REG_UPDATE_2(OTG_V_TOTAL_CONTROL,
+ OTG_VTOTAL_MID_REPLACING_MAX_EN, 1,
+ OTG_VTOTAL_MID_FRAME_NUM,
+ (uint8_t)params->vertical_total_mid_frame_num);
+
+ }
+
REG_SET(OTG_V_TOTAL_MAX, 0,
OTG_V_TOTAL_MAX, params->vertical_total_max - 1);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
index 82d91ab54ba5..83575599672e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
@@ -54,6 +54,7 @@
SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\
SRI(OTG_STEREO_STATUS, OTG, inst),\
SRI(OTG_V_TOTAL_MAX, OTG, inst),\
+ SRI(OTG_V_TOTAL_MID, OTG, inst),\
SRI(OTG_V_TOTAL_MIN, OTG, inst),\
SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\
SRI(OTG_TRIGA_CNTL, OTG, inst),\
@@ -125,6 +126,7 @@ struct dcn_optc_registers {
uint32_t OTG_3D_STRUCTURE_CONTROL;
uint32_t OTG_STEREO_STATUS;
uint32_t OTG_V_TOTAL_MAX;
+ uint32_t OTG_V_TOTAL_MID;
uint32_t OTG_V_TOTAL_MIN;
uint32_t OTG_V_TOTAL_CONTROL;
uint32_t OTG_TRIGA_CNTL;
@@ -214,12 +216,15 @@ struct dcn_optc_registers {
SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\
SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\
SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\
+ SF(OTG0_OTG_V_TOTAL_MID, OTG_V_TOTAL_MID, mask_sh),\
SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK_EN, mask_sh),\
SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\
+ SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\
+ SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_FRAME_NUM, mask_sh),\
SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\
SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\
SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\
@@ -348,9 +353,12 @@ struct dcn_optc_registers {
type OTG_3D_STRUCTURE_V_UPDATE_MODE;\
type OTG_3D_STRUCTURE_STEREO_SEL_OVR;\
type OTG_V_TOTAL_MAX;\
+ type OTG_V_TOTAL_MID;\
type OTG_V_TOTAL_MIN;\
type OTG_V_TOTAL_MIN_SEL;\
type OTG_V_TOTAL_MAX_SEL;\
+ type OTG_VTOTAL_MID_REPLACING_MAX_EN;\
+ type OTG_VTOTAL_MID_FRAME_NUM;\
type OTG_FORCE_LOCK_ON_EVENT;\
type OTG_SET_V_TOTAL_MIN_MASK_EN;\
type OTG_SET_V_TOTAL_MIN_MASK;\
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 99733e1a8958..fb7a244eafca 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -601,6 +601,8 @@ enum dc_status dcn20_enable_stream_timing(
params.vertical_total_min = stream->adjust.v_total_min;
params.vertical_total_max = stream->adjust.v_total_max;
+ params.vertical_total_mid = stream->adjust.v_total_mid;
+ params.vertical_total_mid_frame_num = stream->adjust.v_total_mid_frame_num;
if (pipe_ctx->stream_res.tg->funcs->set_drr)
pipe_ctx->stream_res.tg->funcs->set_drr(
pipe_ctx->stream_res.tg, ¶ms);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
index f607ef24c766..c16bcd2812bf 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
@@ -59,6 +59,8 @@ struct gsl_params {
struct drr_params {
uint32_t vertical_total_min;
uint32_t vertical_total_max;
+ uint32_t vertical_total_mid;
+ uint32_t vertical_total_mid_frame_num;
bool immediate_flip;
};
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 68b1185f0636..732a93df1844 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -237,7 +237,8 @@ struct hw_sequencer_funcs {
#endif
void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes,
- int vmin, int vmax);
+ unsigned int vmin, unsigned int vmax,
+ unsigned int vmid, unsigned int vmid_frame_number);
void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes,
struct crtc_position *position);
--
2.17.1
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 32/36] drm/amd/display: Use res_cap to acquire i2c instead of pipe count
[not found] ` <20190819143515.21653-1-Bhawanpreet.Lakha-5C7GfCeVMHo@public.gmane.org>
` (30 preceding siblings ...)
2019-08-19 14:35 ` [PATCH 31/36] drm/amd/display: Expose OTG_V_TOTAL_MID for HW Diags Bhawanpreet Lakha
@ 2019-08-19 14:35 ` Bhawanpreet Lakha
2019-08-19 14:35 ` [PATCH 33/36] drm/amd/display: revert wait in pipelock Bhawanpreet Lakha
` (3 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Bhawanpreet Lakha @ 2019-08-19 14:35 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Derek Lai
From: Derek Lai <Derek.Lai@amd.com>
[Why]
We should be using the ddc_num from res_caps. As the
pipe count != number of i2c resources.
[How]
Use ddc_num from res_cap instead of pipe count.
Signed-off-by: Derek Lai <Derek.Lai@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
index caace5229826..0495a1b5dd74 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
@@ -22,6 +22,7 @@
* Authors: AMD
*
*/
+#include "resource.h"
#include "dce_i2c.h"
#include "dce_i2c_hw.h"
#include "reg_helper.h"
@@ -387,7 +388,7 @@ struct dce_i2c_hw *acquire_i2c_hw_engine(
if (ddc->hw_info.hw_supported) {
enum gpio_ddc_line line = dal_ddc_get_line(ddc);
- if (line < pool->pipe_count)
+ if (line < pool->res_cap->num_ddc)
dce_i2c_hw = pool->hw_i2cs[line];
}
--
2.17.1
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^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 33/36] drm/amd/display: revert wait in pipelock
[not found] ` <20190819143515.21653-1-Bhawanpreet.Lakha-5C7GfCeVMHo@public.gmane.org>
` (31 preceding siblings ...)
2019-08-19 14:35 ` [PATCH 32/36] drm/amd/display: Use res_cap to acquire i2c instead of pipe count Bhawanpreet Lakha
@ 2019-08-19 14:35 ` Bhawanpreet Lakha
2019-08-19 14:35 ` [PATCH 34/36] drm/amd/display: Properly read LVTMA_PWRSEQ_CNTL Bhawanpreet Lakha
` (2 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Bhawanpreet Lakha @ 2019-08-19 14:35 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Jun Lei
From: Jun Lei <Jun.Lei@amd.com>
[why]
Previous workaround to prevent a vsync flip to be converted
to immediate flip is no longer needed, and is risky because
there are cases where it can result in infinite loop.
[how]
Remove wait loop (which is potentially infinite) before locking
pipe
Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 11 -----------
1 file changed, 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index fb7a244eafca..69d600183db8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1107,17 +1107,6 @@ void dcn20_pipe_control_lock(
if (pipe->plane_state != NULL)
flip_immediate = pipe->plane_state->flip_immediate;
- if (flip_immediate && lock) {
- while (pipe->plane_res.hubp->funcs->hubp_is_flip_pending(pipe->plane_res.hubp)) {
- udelay(1);
- }
-
- if (pipe->bottom_pipe != NULL)
- while (pipe->bottom_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(pipe->bottom_pipe->plane_res.hubp)) {
- udelay(1);
- }
- }
-
/* In flip immediate and pipe splitting case, we need to use GSL
* for synchronization. Only do setup on locking and on flip type change.
*/
--
2.17.1
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^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 34/36] drm/amd/display: Properly read LVTMA_PWRSEQ_CNTL
[not found] ` <20190819143515.21653-1-Bhawanpreet.Lakha-5C7GfCeVMHo@public.gmane.org>
` (32 preceding siblings ...)
2019-08-19 14:35 ` [PATCH 33/36] drm/amd/display: revert wait in pipelock Bhawanpreet Lakha
@ 2019-08-19 14:35 ` Bhawanpreet Lakha
2019-08-19 14:35 ` [PATCH 35/36] drm/amd/display: flicking observed while installing driver on Navi10 CF Bhawanpreet Lakha
2019-08-19 14:35 ` [PATCH 36/36] drm/amd/display: 3.2.48 Bhawanpreet Lakha
35 siblings, 0 replies; 37+ messages in thread
From: Bhawanpreet Lakha @ 2019-08-19 14:35 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Joshua Aberback
From: Joshua Aberback <joshua.aberback@amd.com>
[Why]
The register LVTMA_PWRSEQ_CNTL is used to determine the power state of the
embedded display. Currently we do not actually read this register's values,
so during power down we think that this display is already off, so we skip
calling into VBIOS to actually turn it off.
[How]
- add relevant fields to shift / mask initialization
Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
.../gpu/drm/amd/display/dc/dce/dce_hwseq.h | 43 ++++++++-----------
1 file changed, 17 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index f62eb2e43d7f..7d93babaa2fb 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -416,36 +416,34 @@ struct dce_hwseq_registers {
HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh),\
HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh)
+#define HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)\
+ HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\
+ HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, mask_sh),\
+ HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh),\
+ HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
+
#define HWSEQ_DCE8_MASK_SH_LIST(mask_sh)\
.DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \
HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\
HWS_SF(BLND_, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\
HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\
HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh),\
- HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\
- HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\
- HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)
+ HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\
+ HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)
#define HWSEQ_DCE10_MASK_SH_LIST(mask_sh)\
HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE_),\
HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND_),\
- HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_), \
- HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
- HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
+ HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\
+ HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)
#define HWSEQ_DCE11_MASK_SH_LIST(mask_sh)\
HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\
SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh),\
- HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\
- HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, mask_sh),\
- HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh),\
- HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\
HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)
#define HWSEQ_DCE112_MASK_SH_LIST(mask_sh)\
HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\
- HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\
- HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\
HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_)
#define HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh)\
@@ -453,18 +451,15 @@ struct dce_hwseq_registers {
SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\
SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\
SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\
- SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh), \
- HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
- HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
+ SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh)
#define HWSEQ_DCE12_MASK_SH_LIST(mask_sh)\
HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE0_DCFE_),\
HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND0_BLND_),\
HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\
HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_),\
- HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh), \
- HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
- HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
+ HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh),\
+ HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)
#define HWSEQ_VG20_MASK_SH_LIST(mask_sh)\
HWSEQ_DCE12_MASK_SH_LIST(mask_sh),\
@@ -527,10 +522,7 @@ struct dce_hwseq_registers {
HWS_SF(, D4VGA_CONTROL, D4VGA_MODE_ENABLE, mask_sh),\
HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\
HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh),\
- HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
- HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, mask_sh), \
- HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh), \
- HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
+ HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
#define HWSEQ_DCN2_MASK_SH_LIST(mask_sh)\
@@ -591,8 +583,7 @@ struct dce_hwseq_registers {
HWS_SF(, DOMAIN20_PG_STATUS, DOMAIN20_PGFSM_PWR_STATUS, mask_sh), \
HWS_SF(, DOMAIN21_PG_STATUS, DOMAIN21_PGFSM_PWR_STATUS, mask_sh), \
HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
- HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
- HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
+ HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)
#endif
#define HWSEQ_REG_FIELD_LIST(type) \
@@ -627,9 +618,9 @@ struct dce_hwseq_registers {
type ENABLE_L1_TLB;\
type SYSTEM_ACCESS_MODE;\
type LVTMA_BLON;\
- type LVTMA_PWRSEQ_TARGET_STATE_R;\
type LVTMA_DIGON;\
- type LVTMA_DIGON_OVRD;
+ type LVTMA_DIGON_OVRD;\
+ type LVTMA_PWRSEQ_TARGET_STATE_R;
#define HWSEQ_DCN_REG_FIELD_LIST(type) \
type HUBP_VTG_SEL; \
--
2.17.1
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 35/36] drm/amd/display: flicking observed while installing driver on Navi10 CF
[not found] ` <20190819143515.21653-1-Bhawanpreet.Lakha-5C7GfCeVMHo@public.gmane.org>
` (33 preceding siblings ...)
2019-08-19 14:35 ` [PATCH 34/36] drm/amd/display: Properly read LVTMA_PWRSEQ_CNTL Bhawanpreet Lakha
@ 2019-08-19 14:35 ` Bhawanpreet Lakha
2019-08-19 14:35 ` [PATCH 36/36] drm/amd/display: 3.2.48 Bhawanpreet Lakha
35 siblings, 0 replies; 37+ messages in thread
From: Bhawanpreet Lakha @ 2019-08-19 14:35 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: hersen wu
From: hersen wu <hersenxs.wu@amd.com>
[WHY] value of dchub_ref_clock is decided by dchubbub global timer
settings which is programmed by vbios command table disp_init.
for multi-GPU case, vbios is posted only for primary GPU. without
vbios posted for the secondary GPU, value of dchub_ref_clock is not
set properly. this value will affect dcn bandwidth calcuation and
cause underflow. user will see screen flicking during driver
installation for dual GPU case.
[HOW] dc init_hw always call vbios command table disp_init to
make sure dchubbub global timer is configured and enable.
Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 1 +
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 54 +++++++++----------
2 files changed, 28 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 6e88cb0fffce..adbf2d4e1723 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -169,6 +169,7 @@ struct resource_pool *dc_create_resource_pool(struct dc *dc,
default:
break;
}
+
if (res_pool != NULL) {
if (dc->ctx->dc_bios->fw_info_valid) {
res_pool->ref_clocks.xtalin_clock_inKhz =
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 3272da955b6d..5b9dd169a16f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1208,34 +1208,34 @@ static void dcn10_init_hw(struct dc *dc)
return;
}
- if (!dcb->funcs->is_accelerated_mode(dcb)) {
- dc->hwss.bios_golden_init(dc);
- if (dc->ctx->dc_bios->fw_info_valid) {
- res_pool->ref_clocks.xtalin_clock_inKhz =
- dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
-
- if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
- if (res_pool->dccg && res_pool->hubbub) {
-
- (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
- dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
- &res_pool->ref_clocks.dccg_ref_clock_inKhz);
-
- (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
- res_pool->ref_clocks.dccg_ref_clock_inKhz,
- &res_pool->ref_clocks.dchub_ref_clock_inKhz);
- } else {
- // Not all ASICs have DCCG sw component
- res_pool->ref_clocks.dccg_ref_clock_inKhz =
- res_pool->ref_clocks.xtalin_clock_inKhz;
- res_pool->ref_clocks.dchub_ref_clock_inKhz =
- res_pool->ref_clocks.xtalin_clock_inKhz;
- }
- }
- } else
- ASSERT_CRITICAL(false);
+ if (!dcb->funcs->is_accelerated_mode(dcb))
dc->hwss.disable_vga(dc->hwseq);
- }
+
+ dc->hwss.bios_golden_init(dc);
+ if (dc->ctx->dc_bios->fw_info_valid) {
+ res_pool->ref_clocks.xtalin_clock_inKhz =
+ dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
+
+ if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ if (res_pool->dccg && res_pool->hubbub) {
+
+ (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
+ dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
+ &res_pool->ref_clocks.dccg_ref_clock_inKhz);
+
+ (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
+ res_pool->ref_clocks.dccg_ref_clock_inKhz,
+ &res_pool->ref_clocks.dchub_ref_clock_inKhz);
+ } else {
+ // Not all ASICs have DCCG sw component
+ res_pool->ref_clocks.dccg_ref_clock_inKhz =
+ res_pool->ref_clocks.xtalin_clock_inKhz;
+ res_pool->ref_clocks.dchub_ref_clock_inKhz =
+ res_pool->ref_clocks.xtalin_clock_inKhz;
+ }
+ }
+ } else
+ ASSERT_CRITICAL(false);
for (i = 0; i < dc->link_count; i++) {
/* Power up AND update implementation according to the
--
2.17.1
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 36/36] drm/amd/display: 3.2.48
[not found] ` <20190819143515.21653-1-Bhawanpreet.Lakha-5C7GfCeVMHo@public.gmane.org>
` (34 preceding siblings ...)
2019-08-19 14:35 ` [PATCH 35/36] drm/amd/display: flicking observed while installing driver on Navi10 CF Bhawanpreet Lakha
@ 2019-08-19 14:35 ` Bhawanpreet Lakha
35 siblings, 0 replies; 37+ messages in thread
From: Bhawanpreet Lakha @ 2019-08-19 14:35 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Anthony Koo
From: Anthony Koo <Anthony.Koo@amd.com>
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 239cb0952c61..8ff595e66a6c 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -39,7 +39,7 @@
#include "inc/hw/dmcu.h"
#include "dml/display_mode_lib.h"
-#define DC_VER "3.2.47"
+#define DC_VER "3.2.48"
#define MAX_SURFACES 3
#define MAX_PLANES 6
--
2.17.1
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 37+ messages in thread
end of thread, other threads:[~2019-08-19 14:35 UTC | newest]
Thread overview: 37+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-08-19 14:34 [PATCH 00/36] DC Patches 19 Aug 2019 Bhawanpreet Lakha
[not found] ` <20190819143515.21653-1-Bhawanpreet.Lakha-5C7GfCeVMHo@public.gmane.org>
2019-08-19 14:34 ` [PATCH 01/36] drm/amd/display: re structure odm to allow 4 to 1 support Bhawanpreet Lakha
2019-08-19 14:34 ` [PATCH 02/36] drm/amd/display: Delete dead code in command_table_helper Bhawanpreet Lakha
2019-08-19 14:34 ` [PATCH 03/36] drm/amd/display: fix audio endpoint not getting disabled issue Bhawanpreet Lakha
2019-08-19 14:34 ` [PATCH 04/36] drm/amd/display: fix MPO HUBP underflow with Scatter Gather Bhawanpreet Lakha
2019-08-19 14:34 ` [PATCH 05/36] drm/amd/display: load iram for abm 2.3 Bhawanpreet Lakha
2019-08-19 14:34 ` [PATCH 06/36] drm/amd/display: fix dp stream enable Bhawanpreet Lakha
2019-08-19 14:34 ` [PATCH 07/36] drm/amd/display: set Hratio and VRatio in dml Bhawanpreet Lakha
2019-08-19 14:34 ` [PATCH 08/36] drm/amd/display: add null checks before logging Bhawanpreet Lakha
2019-08-19 14:34 ` [PATCH 09/36] drm/amd/display: Implement voltage limitation stub Bhawanpreet Lakha
2019-08-19 14:34 ` [PATCH 10/36] drm/amd/display: Zero-out dsc init regs Bhawanpreet Lakha
2019-08-19 14:34 ` [PATCH 11/36] drm/amd/display: refactor Device ID for external chips Bhawanpreet Lakha
2019-08-19 14:34 ` [PATCH 12/36] drm/amd/display: Add VM page fault handle implementation Bhawanpreet Lakha
2019-08-19 14:34 ` [PATCH 13/36] drm/amd/display: cleaned up coding error in init_hw Bhawanpreet Lakha
2019-08-19 14:34 ` [PATCH 14/36] drm/amd/display: remove unused function Bhawanpreet Lakha
2019-08-19 14:34 ` [PATCH 15/36] drm/amd/display: 3.2.47 Bhawanpreet Lakha
2019-08-19 14:34 ` [PATCH 16/36] drm/amd/display: Refactoring VTEM Bhawanpreet Lakha
2019-08-19 14:34 ` [PATCH 17/36] drm/amd/display: support spdif Bhawanpreet Lakha
2019-08-19 14:34 ` [PATCH 18/36] drm/amd/display: fix stuck test pattern on right half of display Bhawanpreet Lakha
2019-08-19 14:34 ` [PATCH 19/36] drm/amd/display: fix trigger not generated for freesync Bhawanpreet Lakha
2019-08-19 14:34 ` [PATCH 20/36] drm/amd/display: fix odm pipe copy Bhawanpreet Lakha
2019-08-19 14:35 ` [PATCH 21/36] drm/amd/display: Fix number of slices not being checked for dsc Bhawanpreet Lakha
2019-08-19 14:35 ` [PATCH 22/36] drm/amd/display: fix dcn20 odm dpp programming Bhawanpreet Lakha
2019-08-19 14:35 ` [PATCH 23/36] drm/amd/display: fix odm stream release Bhawanpreet Lakha
2019-08-19 14:35 ` [PATCH 24/36] drm/amd/display: fix odm validation Bhawanpreet Lakha
2019-08-19 14:35 ` [PATCH 25/36] drm/amd/display: add Cursor Degamma logic for DCN2 Bhawanpreet Lakha
2019-08-19 14:35 ` [PATCH 26/36] drm/amd/display: Enable HW rotation Bhawanpreet Lakha
2019-08-19 14:35 ` [PATCH 27/36] drm/amd/display: Add Logging for Gamma Related information Bhawanpreet Lakha
2019-08-19 14:35 ` [PATCH 28/36] drm/amd/display: set av_mute in hw_init for HDMI Bhawanpreet Lakha
2019-08-19 14:35 ` [PATCH 29/36] drm/amd/display: MST topology debugfs Bhawanpreet Lakha
2019-08-19 14:35 ` [PATCH 30/36] drm/amd/display: fix DML not calculating delivery time Bhawanpreet Lakha
2019-08-19 14:35 ` [PATCH 31/36] drm/amd/display: Expose OTG_V_TOTAL_MID for HW Diags Bhawanpreet Lakha
2019-08-19 14:35 ` [PATCH 32/36] drm/amd/display: Use res_cap to acquire i2c instead of pipe count Bhawanpreet Lakha
2019-08-19 14:35 ` [PATCH 33/36] drm/amd/display: revert wait in pipelock Bhawanpreet Lakha
2019-08-19 14:35 ` [PATCH 34/36] drm/amd/display: Properly read LVTMA_PWRSEQ_CNTL Bhawanpreet Lakha
2019-08-19 14:35 ` [PATCH 35/36] drm/amd/display: flicking observed while installing driver on Navi10 CF Bhawanpreet Lakha
2019-08-19 14:35 ` [PATCH 36/36] drm/amd/display: 3.2.48 Bhawanpreet Lakha
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