* [PATCH] drm/amd/powerplay: update cached feature enablement status
@ 2019-08-21 9:24 Evan Quan
[not found] ` <20190821092413.27155-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 4+ messages in thread
From: Evan Quan @ 2019-08-21 9:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Evan Quan
Need to update in cache feature enablement status after pp_feature
settings. Another fix for the commit below:
drm/amd/powerplay: implment sysfs feature status function in smu
Change-Id: I90e29b0d839df26825d5993212f6097c7ad4bebf
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index c663d25db5ab..04867cafb322 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -96,11 +96,13 @@ size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
{
+ struct smu_feature *feature = &smu->smu_feature;
int ret = 0;
uint32_t feature_mask[2] = { 0 };
uint64_t feature_2_enabled = 0;
uint64_t feature_2_disabled = 0;
uint64_t feature_enables = 0;
+ uint64_t feature_id;
ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
if (ret)
@@ -115,11 +117,25 @@ int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
ret = smu_feature_update_enable_state(smu, feature_2_enabled, true);
if (ret)
return ret;
+
+ mutex_lock(&feature->mutex);
+ for (feature_id = 0; feature_id < 64; feature_id++) {
+ if (feature_2_enabled & (1ULL << feature_id))
+ test_and_set_bit(feature_id, feature->enabled);
+ }
+ mutex_unlock(&feature->mutex);
}
if (feature_2_disabled) {
ret = smu_feature_update_enable_state(smu, feature_2_disabled, false);
if (ret)
return ret;
+
+ mutex_lock(&feature->mutex);
+ for (feature_id = 0; feature_id < 64; feature_id++) {
+ if (feature_2_disabled & (1ULL << feature_id))
+ test_and_clear_bit(feature_id, feature->enabled);
+ }
+ mutex_unlock(&feature->mutex);
}
return ret;
--
2.23.0
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/amd/powerplay: update cached feature enablement status
[not found] ` <20190821092413.27155-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
@ 2019-08-21 11:44 ` Kevin Wang
[not found] ` <861ead73-5ce2-ea37-746d-bc82b79d9b88-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 4+ messages in thread
From: Kevin Wang @ 2019-08-21 11:44 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Hi Evan,
this is know issue for me.
i think we should add update feature mask cached operation into
smu_feature_update_enable_state function.
Best Regards,
Kevin
On 8/21/19 5:24 PM, Evan Quan wrote:
> Need to update in cache feature enablement status after pp_feature
> settings. Another fix for the commit below:
> drm/amd/powerplay: implment sysfs feature status function in smu
>
> Change-Id: I90e29b0d839df26825d5993212f6097c7ad4bebf
> Signed-off-by: Evan Quan <evan.quan@amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index c663d25db5ab..04867cafb322 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -96,11 +96,13 @@ size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
>
> int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
> {
> + struct smu_feature *feature = &smu->smu_feature;
> int ret = 0;
> uint32_t feature_mask[2] = { 0 };
> uint64_t feature_2_enabled = 0;
> uint64_t feature_2_disabled = 0;
> uint64_t feature_enables = 0;
> + uint64_t feature_id;
>
> ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
> if (ret)
> @@ -115,11 +117,25 @@ int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
> ret = smu_feature_update_enable_state(smu, feature_2_enabled, true);
> if (ret)
> return ret;
> +
> + mutex_lock(&feature->mutex);
> + for (feature_id = 0; feature_id < 64; feature_id++) {
> + if (feature_2_enabled & (1ULL << feature_id))
> + test_and_set_bit(feature_id, feature->enabled);
> + }
> + mutex_unlock(&feature->mutex);
> }
> if (feature_2_disabled) {
> ret = smu_feature_update_enable_state(smu, feature_2_disabled, false);
> if (ret)
> return ret;
> +
> + mutex_lock(&feature->mutex);
> + for (feature_id = 0; feature_id < 64; feature_id++) {
> + if (feature_2_disabled & (1ULL << feature_id))
> + test_and_clear_bit(feature_id, feature->enabled);
> + }
> + mutex_unlock(&feature->mutex);
> }
>
> return ret;
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
* RE: [PATCH] drm/amd/powerplay: update cached feature enablement status
[not found] ` <861ead73-5ce2-ea37-746d-bc82b79d9b88-5C7GfCeVMHo@public.gmane.org>
@ 2019-08-22 10:18 ` Quan, Evan
2019-08-22 10:20 ` Quan, Evan
1 sibling, 0 replies; 4+ messages in thread
From: Quan, Evan @ 2019-08-22 10:18 UTC (permalink / raw)
To: Wang, Kevin(Yang), amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Please check V2.
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of
> Kevin Wang
> Sent: Wednesday, August 21, 2019 7:45 PM
> To: amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/amd/powerplay: update cached feature
> enablement status
>
> Hi Evan,
>
> this is know issue for me.
> i think we should add update feature mask cached operation into
> smu_feature_update_enable_state function.
>
> Best Regards,
> Kevin
>
> On 8/21/19 5:24 PM, Evan Quan wrote:
> > Need to update in cache feature enablement status after pp_feature
> > settings. Another fix for the commit below:
> > drm/amd/powerplay: implment sysfs feature status function in smu
> >
> > Change-Id: I90e29b0d839df26825d5993212f6097c7ad4bebf
> > Signed-off-by: Evan Quan <evan.quan@amd.com>
> > ---
> > drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 16
> ++++++++++++++++
> > 1 file changed, 16 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> > b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> > index c663d25db5ab..04867cafb322 100644
> > --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> > +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> > @@ -96,11 +96,13 @@ size_t smu_sys_get_pp_feature_mask(struct
> > smu_context *smu, char *buf)
> >
> > int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t
> new_mask)
> > {
> > + struct smu_feature *feature = &smu->smu_feature;
> > int ret = 0;
> > uint32_t feature_mask[2] = { 0 };
> > uint64_t feature_2_enabled = 0;
> > uint64_t feature_2_disabled = 0;
> > uint64_t feature_enables = 0;
> > + uint64_t feature_id;
> >
> > ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
> > if (ret)
> > @@ -115,11 +117,25 @@ int smu_sys_set_pp_feature_mask(struct
> smu_context *smu, uint64_t new_mask)
> > ret = smu_feature_update_enable_state(smu,
> feature_2_enabled, true);
> > if (ret)
> > return ret;
> > +
> > + mutex_lock(&feature->mutex);
> > + for (feature_id = 0; feature_id < 64; feature_id++) {
> > + if (feature_2_enabled & (1ULL << feature_id))
> > + test_and_set_bit(feature_id, feature-
> >enabled);
> > + }
> > + mutex_unlock(&feature->mutex);
> > }
> > if (feature_2_disabled) {
> > ret = smu_feature_update_enable_state(smu,
> feature_2_disabled, false);
> > if (ret)
> > return ret;
> > +
> > + mutex_lock(&feature->mutex);
> > + for (feature_id = 0; feature_id < 64; feature_id++) {
> > + if (feature_2_disabled & (1ULL << feature_id))
> > + test_and_clear_bit(feature_id, feature-
> >enabled);
> > + }
> > + mutex_unlock(&feature->mutex);
> > }
> >
> > return ret;
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
* RE: [PATCH] drm/amd/powerplay: update cached feature enablement status
[not found] ` <861ead73-5ce2-ea37-746d-bc82b79d9b88-5C7GfCeVMHo@public.gmane.org>
2019-08-22 10:18 ` Quan, Evan
@ 2019-08-22 10:20 ` Quan, Evan
1 sibling, 0 replies; 4+ messages in thread
From: Quan, Evan @ 2019-08-22 10:20 UTC (permalink / raw)
To: Wang, Kevin(Yang), amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Please check V2.
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of
> Kevin Wang
> Sent: Wednesday, August 21, 2019 7:45 PM
> To: amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/amd/powerplay: update cached feature
> enablement status
>
> Hi Evan,
>
> this is know issue for me.
> i think we should add update feature mask cached operation into
> smu_feature_update_enable_state function.
>
> Best Regards,
> Kevin
>
> On 8/21/19 5:24 PM, Evan Quan wrote:
> > Need to update in cache feature enablement status after pp_feature
> > settings. Another fix for the commit below:
> > drm/amd/powerplay: implment sysfs feature status function in smu
> >
> > Change-Id: I90e29b0d839df26825d5993212f6097c7ad4bebf
> > Signed-off-by: Evan Quan <evan.quan@amd.com>
> > ---
> > drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 16
> ++++++++++++++++
> > 1 file changed, 16 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> > b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> > index c663d25db5ab..04867cafb322 100644
> > --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> > +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> > @@ -96,11 +96,13 @@ size_t smu_sys_get_pp_feature_mask(struct
> > smu_context *smu, char *buf)
> >
> > int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t
> new_mask)
> > {
> > + struct smu_feature *feature = &smu->smu_feature;
> > int ret = 0;
> > uint32_t feature_mask[2] = { 0 };
> > uint64_t feature_2_enabled = 0;
> > uint64_t feature_2_disabled = 0;
> > uint64_t feature_enables = 0;
> > + uint64_t feature_id;
> >
> > ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
> > if (ret)
> > @@ -115,11 +117,25 @@ int smu_sys_set_pp_feature_mask(struct
> smu_context *smu, uint64_t new_mask)
> > ret = smu_feature_update_enable_state(smu,
> feature_2_enabled, true);
> > if (ret)
> > return ret;
> > +
> > + mutex_lock(&feature->mutex);
> > + for (feature_id = 0; feature_id < 64; feature_id++) {
> > + if (feature_2_enabled & (1ULL << feature_id))
> > + test_and_set_bit(feature_id, feature-
> >enabled);
> > + }
> > + mutex_unlock(&feature->mutex);
> > }
> > if (feature_2_disabled) {
> > ret = smu_feature_update_enable_state(smu,
> feature_2_disabled, false);
> > if (ret)
> > return ret;
> > +
> > + mutex_lock(&feature->mutex);
> > + for (feature_id = 0; feature_id < 64; feature_id++) {
> > + if (feature_2_disabled & (1ULL << feature_id))
> > + test_and_clear_bit(feature_id, feature-
> >enabled);
> > + }
> > + mutex_unlock(&feature->mutex);
> > }
> >
> > return ret;
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
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2019-08-21 9:24 [PATCH] drm/amd/powerplay: update cached feature enablement status Evan Quan
[not found] ` <20190821092413.27155-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
2019-08-21 11:44 ` Kevin Wang
[not found] ` <861ead73-5ce2-ea37-746d-bc82b79d9b88-5C7GfCeVMHo@public.gmane.org>
2019-08-22 10:18 ` Quan, Evan
2019-08-22 10:20 ` Quan, Evan
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