* [PATCH 00/37] Enable power features for Renoir
@ 2019-08-21 22:23 Alex Deucher
[not found] ` <20190821222359.13578-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 39+ messages in thread
From: Alex Deucher @ 2019-08-21 22:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher
This patch set adds initial power management support for
renoir.
Aaron Liu (15):
drm/amd/powerplay: add smu12_driver_if.h (v3)
drm/amdgpu/powerplay: add initial renoir_ppt.c for renoir (v3)
drm/amdgpu/powerplay: add smu_v12_0.c & smu_v12_0.h for renoir
drm/amdgpu/powerplay: add smu ip block for renoir (v2)
drm/amdgpu/powerplay: add power up/down SDMA interfaces for renoir
drm/amd/powerplay: udpate smu_v12_0_check_fw_version (v2)
drm/amdgpu: add set_gfx_cgpg implement (v2)
drm/amdgpu: add and enable gfxoff feature
drm/amd/powerplay: fix checking gfxoff status for rn
drm/amd/powerplay: using valid mapping check for rn
drm/amd/powerplay: add smu tables for rn
drm/amd/powerplay: init smu tables for rn
drm/amd/powerplay: add DPMCLOCKS table implementation
drm/amdgpu: update gc/sdma goldensetting for rn
Revert "drm/amdgpu: disable gfxoff for the moment on renoir"
Alex Deucher (1):
drm/amdgpu/powerplay: Add smu_v12_0_ppsmc.h (v2)
Huang Rui (3):
drm/amdgpu: skip dpm init for renoir
drm/amd/powerplay: powerup sdma/vcn for all apu series
drm/amdgpu: disable gfxoff for the moment on renoir
Leo Liu (1):
drm/amdgpu/powerplay: add Renoir VCN power management
Prike Liang (15):
drm/amdgpu: enable gfx clock gating for rn
drm/amdgpu: enable mmhub clock gating for rn
drm/amdgpu: enable sdma clock gating for rn
drm/amdgpu: enable BIF clock gating for rn
drm/amdgpu: enable HDP clock gating for rn
drm/amdgpu: enable rom clock gating for rn
drm/amdgpu: enable vcn clock gating for rn
drm/amdgpu: enable IH clock gating for rn
drm/amdgpu: enable athub clock gating for rn
drm/amdgpu: enable DF clock gating for rn
drm/amdgpu/mmhub1: set mmhub clock gating for rn
drm/amdgpu/sdma4: set sdma clock gating for rn
drm/amdgpu: enable SDMA power gating for rn
drm/amd/powerplay: enable renoir dpm feature
drm/amd/powerplay: Disable renoir smu feature retrive for the moment
Thong Thai (2):
Revert "drm/amdgpu: use direct loading on renoir vcn for the moment"
drm/amdgpu: enable VCN DPG for Renoir
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 9 +-
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 12 +-
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 5 +-
drivers/gpu/drm/amd/amdgpu/soc15.c | 31 +-
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 9 +-
drivers/gpu/drm/amd/powerplay/Makefile | 2 +-
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 35 +-
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 20 +-
.../drm/amd/powerplay/inc/smu12_driver_if.h | 217 +++++++++++
drivers/gpu/drm/amd/powerplay/inc/smu_types.h | 44 +++
drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h | 42 +++
.../drm/amd/powerplay/inc/smu_v12_0_ppsmc.h | 106 ++++++
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 173 +++++++++
drivers/gpu/drm/amd/powerplay/renoir_ppt.h | 28 ++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 2 +-
drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 350 ++++++++++++++++++
17 files changed, 1060 insertions(+), 26 deletions(-)
create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu12_driver_if.h
create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu_v12_0_ppsmc.h
create mode 100644 drivers/gpu/drm/amd/powerplay/renoir_ppt.c
create mode 100644 drivers/gpu/drm/amd/powerplay/renoir_ppt.h
create mode 100644 drivers/gpu/drm/amd/powerplay/smu_v12_0.c
--
2.20.1
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 01/37] drm/amdgpu/powerplay: Add smu_v12_0_ppsmc.h (v2)
[not found] ` <20190821222359.13578-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
@ 2019-08-21 22:23 ` Alex Deucher
2019-08-21 22:23 ` [PATCH 02/37] drm/amd/powerplay: add smu12_driver_if.h (v3) Alex Deucher
` (35 subsequent siblings)
36 siblings, 0 replies; 39+ messages in thread
From: Alex Deucher @ 2019-08-21 22:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher
This is the SMU v12 driver message interface.
v2: squash in updates
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
.../drm/amd/powerplay/inc/smu_v12_0_ppsmc.h | 106 ++++++++++++++++++
1 file changed, 106 insertions(+)
create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu_v12_0_ppsmc.h
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0_ppsmc.h
new file mode 100644
index 000000000000..9ac9f3bd3664
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0_ppsmc.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef SMU_12_0_PPSMC_H
+#define SMU_12_0_PPSMC_H
+
+// SMU Response Codes:
+#define PPSMC_Result_OK 0x1
+#define PPSMC_Result_Failed 0xFF
+#define PPSMC_Result_UnknownCmd 0xFE
+#define PPSMC_Result_CmdRejectedPrereq 0xFD
+#define PPSMC_Result_CmdRejectedBusy 0xFC
+
+
+// Message Definitions:
+#define PPSMC_MSG_TestMessage 0x1
+#define PPSMC_MSG_GetSmuVersion 0x2
+#define PPSMC_MSG_GetDriverIfVersion 0x3
+#define PPSMC_MSG_PowerUpGfx 0x6
+#define PPSMC_MSG_EnableGfxOff 0x7
+#define PPSMC_MSG_DisableGfxOff 0x8
+#define PPSMC_MSG_PowerDownIspByTile 0x9 // ISP is power gated by default
+#define PPSMC_MSG_PowerUpIspByTile 0xA
+#define PPSMC_MSG_PowerDownVcn 0xB // VCN is power gated by default
+#define PPSMC_MSG_PowerUpVcn 0xC
+#define PPSMC_MSG_PowerDownSdma 0xD // SDMA is power gated by default
+#define PPSMC_MSG_PowerUpSdma 0xE
+#define PPSMC_MSG_SetHardMinIspclkByFreq 0xF
+#define PPSMC_MSG_SetHardMinVcn 0x10 // For wireless display
+#define PPSMC_MSG_spare1 0x11
+#define PPSMC_MSG_spare2 0x12
+#define PPSMC_MSG_SetAllowFclkSwitch 0x13
+#define PPSMC_MSG_SetMinVideoGfxclkFreq 0x14
+#define PPSMC_MSG_ActiveProcessNotify 0x15
+#define PPSMC_MSG_SetCustomPolicy 0x16
+#define PPSMC_MSG_SetVideoFps 0x17
+#define PPSMC_MSG_SetDisplayCount 0x18 // Moved to VBIOS
+#define PPSMC_MSG_QueryPowerLimit 0x19 //Driver to look up sustainable clocks for VQ
+#define PPSMC_MSG_SetDriverDramAddrHigh 0x1A
+#define PPSMC_MSG_SetDriverDramAddrLow 0x1B
+#define PPSMC_MSG_TransferTableSmu2Dram 0x1C
+#define PPSMC_MSG_TransferTableDram2Smu 0x1D
+#define PPSMC_MSG_GfxDeviceDriverReset 0x1E
+#define PPSMC_MSG_SetGfxclkOverdriveByFreqVid 0x1F
+#define PPSMC_MSG_SetHardMinDcfclkByFreq 0x20 // Moved to VBIOS
+#define PPSMC_MSG_SetHardMinSocclkByFreq 0x21
+#define PPSMC_MSG_ControlIgpuATS 0x22
+#define PPSMC_MSG_SetMinVideoFclkFreq 0x23
+#define PPSMC_MSG_SetMinDeepSleepDcfclk 0x24 // Moved to VBIOS
+#define PPSMC_MSG_ForcePowerDownGfx 0x25
+#define PPSMC_MSG_SetPhyclkVoltageByFreq 0x26 // Moved to VBIOS
+#define PPSMC_MSG_SetDppclkVoltageByFreq 0x27 // Moved to VBIOS and is SetDppclkFreq
+#define PPSMC_MSG_SetSoftMinVcn 0x28
+#define PPSMC_MSG_EnablePostCode 0x29
+#define PPSMC_MSG_GetGfxclkFrequency 0x2A
+#define PPSMC_MSG_GetFclkFrequency 0x2B
+#define PPSMC_MSG_GetMinGfxclkFrequency 0x2C
+#define PPSMC_MSG_GetMaxGfxclkFrequency 0x2D
+#define PPSMC_MSG_SoftReset 0x2E // Not supported
+#define PPSMC_MSG_SetGfxCGPG 0x2F
+#define PPSMC_MSG_SetSoftMaxGfxClk 0x30
+#define PPSMC_MSG_SetHardMinGfxClk 0x31
+#define PPSMC_MSG_SetSoftMaxSocclkByFreq 0x32
+#define PPSMC_MSG_SetSoftMaxFclkByFreq 0x33
+#define PPSMC_MSG_SetSoftMaxVcn 0x34
+#define PPSMC_MSG_PowerGateMmHub 0x35
+#define PPSMC_MSG_UpdatePmeRestore 0x36 // Moved to VBIOS
+#define PPSMC_MSG_GpuChangeState 0x37
+#define PPSMC_MSG_SetPowerLimitPercentage 0x38
+#define PPSMC_MSG_ForceGfxContentSave 0x39
+#define PPSMC_MSG_EnableTmdp48MHzRefclkPwrDown 0x3A // Moved to VBIOS
+#define PPSMC_MSG_PowerDownJpeg 0x3B
+#define PPSMC_MSG_PowerUpJpeg 0x3C
+#define PPSMC_MSG_PowerGateAtHub 0x3D
+#define PPSMC_MSG_SetSoftMinJpeg 0x3E
+#define PPSMC_MSG_SetHardMinFclkByFreq 0x3F
+#define PPSMC_Message_Count 0x40
+
+
+//Argument for PPSMC_MSG_GpuChangeState
+enum {
+ eGpuChangeState_D0Entry = 1,
+ eGpuChangeState_D3Entry,
+};
+
+#endif
--
2.20.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 02/37] drm/amd/powerplay: add smu12_driver_if.h (v3)
[not found] ` <20190821222359.13578-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
2019-08-21 22:23 ` [PATCH 01/37] drm/amdgpu/powerplay: Add smu_v12_0_ppsmc.h (v2) Alex Deucher
@ 2019-08-21 22:23 ` Alex Deucher
2019-08-21 22:23 ` [PATCH 03/37] drm/amdgpu/powerplay: add initial renoir_ppt.c for renoir (v3) Alex Deucher
` (34 subsequent siblings)
36 siblings, 0 replies; 39+ messages in thread
From: Alex Deucher @ 2019-08-21 22:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alex Deucher, Huang Rui, Aaron Liu, Evan Quan
From: Aaron Liu <aaron.liu@amd.com>
This patch adds smu12_driver_if.h
v2: squash in updates (Alex)
v3: more updates (Alex)
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
.../drm/amd/powerplay/inc/smu12_driver_if.h | 217 ++++++++++++++++++
1 file changed, 217 insertions(+)
create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu12_driver_if.h
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu12_driver_if.h b/drivers/gpu/drm/amd/powerplay/inc/smu12_driver_if.h
new file mode 100644
index 000000000000..c27c82851468
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu12_driver_if.h
@@ -0,0 +1,217 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef SMU12_DRIVER_IF_H
+#define SMU12_DRIVER_IF_H
+
+// *** IMPORTANT ***
+// SMU TEAM: Always increment the interface version if
+// any structure is changed in this file
+#define SMU12_DRIVER_IF_VERSION 10
+
+typedef struct {
+ int32_t value;
+ uint32_t numFractionalBits;
+} FloatInIntFormat_t;
+
+typedef enum {
+ DSPCLK_DCFCLK = 0,
+ DSPCLK_DISPCLK,
+ DSPCLK_PIXCLK,
+ DSPCLK_PHYCLK,
+ DSPCLK_COUNT,
+} DSPCLK_e;
+
+typedef struct {
+ uint16_t Freq; // in MHz
+ uint16_t Vid; // min voltage in SVI2 VID
+} DisplayClockTable_t;
+
+typedef struct {
+ uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
+ uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
+ uint16_t MinMclk;
+ uint16_t MaxMclk;
+
+ uint8_t WmSetting;
+ uint8_t WmType; // Used for normal pstate change or memory retraining
+ uint8_t Padding[2];
+} WatermarkRowGeneric_t;
+
+#define NUM_WM_RANGES 4
+#define WM_PSTATE_CHG 0
+#define WM_RETRAINING 1
+
+typedef enum {
+ WM_SOCCLK = 0,
+ WM_DCFCLK,
+ WM_COUNT,
+} WM_CLOCK_e;
+
+typedef struct {
+ // Watermarks
+ WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
+
+ uint32_t MmHubPadding[7]; // SMU internal use
+} Watermarks_t;
+
+typedef enum {
+ CUSTOM_DPM_SETTING_GFXCLK,
+ CUSTOM_DPM_SETTING_CCLK,
+ CUSTOM_DPM_SETTING_FCLK_CCX,
+ CUSTOM_DPM_SETTING_FCLK_GFX,
+ CUSTOM_DPM_SETTING_FCLK_STALLS,
+ CUSTOM_DPM_SETTING_LCLK,
+ CUSTOM_DPM_SETTING_COUNT,
+} CUSTOM_DPM_SETTING_e;
+
+typedef struct {
+ uint8_t ActiveHystLimit;
+ uint8_t IdleHystLimit;
+ uint8_t FPS;
+ uint8_t MinActiveFreqType;
+ FloatInIntFormat_t MinActiveFreq;
+ FloatInIntFormat_t PD_Data_limit;
+ FloatInIntFormat_t PD_Data_time_constant;
+ FloatInIntFormat_t PD_Data_error_coeff;
+ FloatInIntFormat_t PD_Data_error_rate_coeff;
+} DpmActivityMonitorCoeffExt_t;
+
+typedef struct {
+ DpmActivityMonitorCoeffExt_t DpmActivityMonitorCoeff[CUSTOM_DPM_SETTING_COUNT];
+} CustomDpmSettings_t;
+
+
+#define NUM_DCFCLK_DPM_LEVELS 8
+#define NUM_SOCCLK_DPM_LEVELS 8
+#define NUM_FCLK_DPM_LEVELS 4
+#define NUM_MEMCLK_DPM_LEVELS 4
+#define NUM_VCN_DPM_LEVELS 8
+
+typedef struct {
+ uint32_t Freq; // In MHz
+ uint32_t Vol; // Millivolts with 2 fractional bits
+} DpmClock_t;
+
+typedef struct {
+ DpmClock_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];
+ DpmClock_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
+ DpmClock_t FClocks[NUM_FCLK_DPM_LEVELS];
+ DpmClock_t MemClocks[NUM_MEMCLK_DPM_LEVELS];
+ DpmClock_t VClocks[NUM_VCN_DPM_LEVELS];
+ DpmClock_t DClocks[NUM_VCN_DPM_LEVELS];
+
+ uint8_t NumDcfClkDpmEnabled;
+ uint8_t NumSocClkDpmEnabled;
+ uint8_t NumFClkDpmEnabled;
+ uint8_t NumMemClkDpmEnabled;
+ uint8_t NumVClkDpmEnabled;
+ uint8_t NumDClkDpmEnabled;
+ uint8_t spare[2];
+} DpmClocks_t;
+
+
+typedef enum {
+ CLOCK_SMNCLK = 0,
+ CLOCK_SOCCLK,
+ CLOCK_MP0CLK,
+ CLOCK_MP1CLK,
+ CLOCK_MP2CLK,
+ CLOCK_VCLK,
+ CLOCK_LCLK,
+ CLOCK_DCLK,
+ CLOCK_ACLK,
+ CLOCK_ISPCLK,
+ CLOCK_SHUBCLK,
+ CLOCK_DISPCLK,
+ CLOCK_DPPCLK,
+ CLOCK_DPREFCLK,
+ CLOCK_DCFCLK,
+ CLOCK_FCLK,
+ CLOCK_UMCCLK,
+ CLOCK_GFXCLK,
+ CLOCK_COUNT,
+} CLOCK_IDs_e;
+
+// Throttler Status Bitmask
+#define THROTTLER_STATUS_BIT_SPL 0
+#define THROTTLER_STATUS_BIT_FPPT 1
+#define THROTTLER_STATUS_BIT_SPPT 2
+#define THROTTLER_STATUS_BIT_SPPT_APU 3
+#define THROTTLER_STATUS_BIT_THM_CORE 4
+#define THROTTLER_STATUS_BIT_THM_GFX 5
+#define THROTTLER_STATUS_BIT_THM_SOC 6
+#define THROTTLER_STATUS_BIT_TDC_VDD 7
+#define THROTTLER_STATUS_BIT_TDC_SOC 8
+
+typedef struct {
+ uint16_t ClockFrequency[CLOCK_COUNT]; //[MHz]
+
+ uint16_t AverageGfxclkFrequency; //[MHz]
+ uint16_t AverageSocclkFrequency; //[MHz]
+ uint16_t AverageVclkFrequency; //[MHz]
+ uint16_t AverageFclkFrequency; //[MHz]
+
+ uint16_t AverageGfxActivity; //[centi]
+ uint16_t AverageUvdActivity; //[centi]
+
+ uint16_t Voltage[2]; //[mV] indices: VDDCR_VDD, VDDCR_SOC
+ uint16_t Current[2]; //[mA] indices: VDDCR_VDD, VDDCR_SOC
+ uint16_t Power[2]; //[mW] indices: VDDCR_VDD, VDDCR_SOC
+
+ uint16_t FanPwm; //[milli]
+ uint16_t CurrentSocketPower; //[mW]
+
+ uint16_t CoreFrequency[8]; //[MHz]
+ uint16_t CorePower[8]; //[mW]
+ uint16_t CoreTemperature[8]; //[centi-Celsius]
+ uint16_t L3Frequency[2]; //[MHz]
+ uint16_t L3Temperature[2]; //[centi-Celsius]
+
+ uint16_t GfxTemperature; //[centi-Celsius]
+ uint16_t SocTemperature; //[centi-Celsius]
+ uint16_t ThrottlerStatus;
+ uint16_t spare;
+} SmuMetrics_t;
+
+
+// Workload bits
+#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 0
+#define WORKLOAD_PPLIB_VIDEO_BIT 2
+#define WORKLOAD_PPLIB_VR_BIT 3
+#define WORKLOAD_PPLIB_COMPUTE_BIT 4
+#define WORKLOAD_PPLIB_CUSTOM_BIT 5
+#define WORKLOAD_PPLIB_COUNT 6
+
+#define TABLE_BIOS_IF 0 // Called by BIOS
+#define TABLE_WATERMARKS 1 // Called by Driver
+#define TABLE_CUSTOM_DPM 2 // Called by Driver
+#define TABLE_SPARE1 3
+#define TABLE_DPMCLOCKS 4 // Called by Driver
+#define TABLE_MOMENTARY_PM 5 // Called by Tools
+#define TABLE_MODERN_STDBY 6 // Called by Tools for Modern Standby Log
+#define TABLE_SMU_METRICS 7 // Called by Driver
+#define TABLE_COUNT 8
+
+
+#endif
--
2.20.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 03/37] drm/amdgpu/powerplay: add initial renoir_ppt.c for renoir (v3)
[not found] ` <20190821222359.13578-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
2019-08-21 22:23 ` [PATCH 01/37] drm/amdgpu/powerplay: Add smu_v12_0_ppsmc.h (v2) Alex Deucher
2019-08-21 22:23 ` [PATCH 02/37] drm/amd/powerplay: add smu12_driver_if.h (v3) Alex Deucher
@ 2019-08-21 22:23 ` Alex Deucher
2019-08-21 22:23 ` [PATCH 04/37] drm/amdgpu/powerplay: add smu_v12_0.c & smu_v12_0.h for renoir Alex Deucher
` (33 subsequent siblings)
36 siblings, 0 replies; 39+ messages in thread
From: Alex Deucher @ 2019-08-21 22:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alex Deucher, Huang Rui, Aaron Liu
From: Aaron Liu <aaron.liu@amd.com>
Add renoir_ppt and map ppsmc to amdgpu_smu.h
v2: squash in ppsmc updates (Alex)
v3: squash in driver_if updates (Alex)
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/inc/smu_types.h | 44 +++++++
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 121 ++++++++++++++++++
drivers/gpu/drm/amd/powerplay/renoir_ppt.h | 28 ++++
3 files changed, 193 insertions(+)
create mode 100644 drivers/gpu/drm/amd/powerplay/renoir_ppt.c
create mode 100644 drivers/gpu/drm/amd/powerplay/renoir_ppt.h
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
index 72962e842d69..052aecc2827a 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
@@ -124,6 +124,50 @@
__SMU_DUMMY_MAP(PowerDownVcn0), \
__SMU_DUMMY_MAP(PowerUpVcn1), \
__SMU_DUMMY_MAP(PowerDownVcn1), \
+ __SMU_DUMMY_MAP(PowerUpGfx), \
+ __SMU_DUMMY_MAP(PowerDownIspByTile), \
+ __SMU_DUMMY_MAP(PowerUpIspByTile), \
+ __SMU_DUMMY_MAP(PowerDownSdma), \
+ __SMU_DUMMY_MAP(PowerUpSdma), \
+ __SMU_DUMMY_MAP(SetHardMinIspclkByFreq), \
+ __SMU_DUMMY_MAP(SetHardMinVcn), \
+ __SMU_DUMMY_MAP(Spare1), \
+ __SMU_DUMMY_MAP(Spare2), \
+ __SMU_DUMMY_MAP(SetAllowFclkSwitch), \
+ __SMU_DUMMY_MAP(SetMinVideoGfxclkFreq), \
+ __SMU_DUMMY_MAP(ActiveProcessNotify), \
+ __SMU_DUMMY_MAP(SetCustomPolicy), \
+ __SMU_DUMMY_MAP(QueryPowerLimit), \
+ __SMU_DUMMY_MAP(SetGfxclkOverdriveByFreqVid), \
+ __SMU_DUMMY_MAP(SetHardMinDcfclkByFreq), \
+ __SMU_DUMMY_MAP(SetHardMinSocclkByFreq), \
+ __SMU_DUMMY_MAP(ControlIgpuATS), \
+ __SMU_DUMMY_MAP(SetMinVideoFclkFreq), \
+ __SMU_DUMMY_MAP(SetMinDeepSleepDcfclk), \
+ __SMU_DUMMY_MAP(ForcePowerDownGfx), \
+ __SMU_DUMMY_MAP(SetPhyclkVoltageByFreq), \
+ __SMU_DUMMY_MAP(SetDppclkVoltageByFreq), \
+ __SMU_DUMMY_MAP(SetSoftMinVcn), \
+ __SMU_DUMMY_MAP(EnablePostCode), \
+ __SMU_DUMMY_MAP(GetGfxclkFrequency), \
+ __SMU_DUMMY_MAP(GetFclkFrequency), \
+ __SMU_DUMMY_MAP(GetMinGfxclkFrequency), \
+ __SMU_DUMMY_MAP(GetMaxGfxclkFrequency), \
+ __SMU_DUMMY_MAP(SetGfxCGPG), \
+ __SMU_DUMMY_MAP(SetSoftMaxGfxClk), \
+ __SMU_DUMMY_MAP(SetHardMinGfxClk), \
+ __SMU_DUMMY_MAP(SetSoftMaxSocclkByFreq), \
+ __SMU_DUMMY_MAP(SetSoftMaxFclkByFreq), \
+ __SMU_DUMMY_MAP(SetSoftMaxVcn), \
+ __SMU_DUMMY_MAP(PowerGateMmHub), \
+ __SMU_DUMMY_MAP(UpdatePmeRestore), \
+ __SMU_DUMMY_MAP(GpuChangeState), \
+ __SMU_DUMMY_MAP(SetPowerLimitPercentage), \
+ __SMU_DUMMY_MAP(ForceGfxContentSave), \
+ __SMU_DUMMY_MAP(EnableTmdp48MHzRefclkPwrDown), \
+ __SMU_DUMMY_MAP(PowerGateAtHub), \
+ __SMU_DUMMY_MAP(SetSoftMinJpeg), \
+ __SMU_DUMMY_MAP(SetHardMinFclkByFreq), \
#undef __SMU_DUMMY_MAP
#define __SMU_DUMMY_MAP(type) SMU_MSG_##type
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
new file mode 100644
index 000000000000..dd270600962b
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -0,0 +1,121 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "amdgpu.h"
+#include "amdgpu_smu.h"
+#include "soc15_common.h"
+#include "smu_v12_0_ppsmc.h"
+#include "renoir_ppt.h"
+
+
+#define MSG_MAP(msg, index) \
+ [SMU_MSG_##msg] = index
+
+static int renoir_message_map[SMU_MSG_MAX_COUNT] = {
+ MSG_MAP(TestMessage, PPSMC_MSG_TestMessage),
+ MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion),
+ MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion),
+ MSG_MAP(PowerUpGfx, PPSMC_MSG_PowerUpGfx),
+ MSG_MAP(AllowGfxOff, PPSMC_MSG_EnableGfxOff),
+ MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisableGfxOff),
+ MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile),
+ MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile),
+ MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn),
+ MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn),
+ MSG_MAP(PowerDownSdma, PPSMC_MSG_PowerDownSdma),
+ MSG_MAP(PowerUpSdma, PPSMC_MSG_PowerUpSdma),
+ MSG_MAP(SetHardMinIspclkByFreq, PPSMC_MSG_SetHardMinIspclkByFreq),
+ MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn),
+ MSG_MAP(Spare1, PPSMC_MSG_spare1),
+ MSG_MAP(Spare2, PPSMC_MSG_spare2),
+ MSG_MAP(SetAllowFclkSwitch, PPSMC_MSG_SetAllowFclkSwitch),
+ MSG_MAP(SetMinVideoGfxclkFreq, PPSMC_MSG_SetMinVideoGfxclkFreq),
+ MSG_MAP(ActiveProcessNotify, PPSMC_MSG_ActiveProcessNotify),
+ MSG_MAP(SetCustomPolicy, PPSMC_MSG_SetCustomPolicy),
+ MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps),
+ MSG_MAP(NumOfDisplays, PPSMC_MSG_SetDisplayCount),
+ MSG_MAP(QueryPowerLimit, PPSMC_MSG_QueryPowerLimit),
+ MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh),
+ MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow),
+ MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram),
+ MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu),
+ MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset),
+ MSG_MAP(SetGfxclkOverdriveByFreqVid, PPSMC_MSG_SetGfxclkOverdriveByFreqVid),
+ MSG_MAP(SetHardMinDcfclkByFreq, PPSMC_MSG_SetHardMinDcfclkByFreq),
+ MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq),
+ MSG_MAP(ControlIgpuATS, PPSMC_MSG_ControlIgpuATS),
+ MSG_MAP(SetMinVideoFclkFreq, PPSMC_MSG_SetMinVideoFclkFreq),
+ MSG_MAP(SetMinDeepSleepDcfclk, PPSMC_MSG_SetMinDeepSleepDcfclk),
+ MSG_MAP(ForcePowerDownGfx, PPSMC_MSG_ForcePowerDownGfx),
+ MSG_MAP(SetPhyclkVoltageByFreq, PPSMC_MSG_SetPhyclkVoltageByFreq),
+ MSG_MAP(SetDppclkVoltageByFreq, PPSMC_MSG_SetDppclkVoltageByFreq),
+ MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn),
+ MSG_MAP(EnablePostCode, PPSMC_MSG_EnablePostCode),
+ MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency),
+ MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency),
+ MSG_MAP(GetMinGfxclkFrequency, PPSMC_MSG_GetMinGfxclkFrequency),
+ MSG_MAP(GetMaxGfxclkFrequency, PPSMC_MSG_GetMaxGfxclkFrequency),
+ MSG_MAP(SoftReset, PPSMC_MSG_SoftReset),
+ MSG_MAP(SetGfxCGPG, PPSMC_MSG_SetGfxCGPG),
+ MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk),
+ MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk),
+ MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq),
+ MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq),
+ MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn),
+ MSG_MAP(PowerGateMmHub, PPSMC_MSG_PowerGateMmHub),
+ MSG_MAP(UpdatePmeRestore, PPSMC_MSG_UpdatePmeRestore),
+ MSG_MAP(GpuChangeState, PPSMC_MSG_GpuChangeState),
+ MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage),
+ MSG_MAP(ForceGfxContentSave, PPSMC_MSG_ForceGfxContentSave),
+ MSG_MAP(EnableTmdp48MHzRefclkPwrDown, PPSMC_MSG_EnableTmdp48MHzRefclkPwrDown),
+ MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg),
+ MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg),
+ MSG_MAP(PowerGateAtHub, PPSMC_MSG_PowerGateAtHub),
+ MSG_MAP(SetSoftMinJpeg, PPSMC_MSG_SetSoftMinJpeg),
+ MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq),
+};
+
+static int renoir_get_smu_msg_index(struct smu_context *smc, uint32_t index)
+{
+ int val;
+
+ if (index >= SMU_MSG_MAX_COUNT)
+ return -EINVAL;
+
+ val = renoir_message_map[index];
+ if (val > PPSMC_Message_Count)
+ return -EINVAL;
+
+ return val;
+}
+
+
+static const struct pptable_funcs renoir_ppt_funcs = {
+ .get_smu_msg_index = renoir_get_smu_msg_index,
+ .set_power_state = NULL,
+};
+
+void renoir_set_ppt_funcs(struct smu_context *smu)
+{
+ smu->ppt_funcs = &renoir_ppt_funcs;
+}
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.h b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
new file mode 100644
index 000000000000..e9b7237c0f7f
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef __RENOIR_PPT_H__
+#define __RENOIR_PPT_H__
+
+extern void renoir_set_ppt_funcs(struct smu_context *smu);
+
+#endif
--
2.20.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 04/37] drm/amdgpu/powerplay: add smu_v12_0.c & smu_v12_0.h for renoir
[not found] ` <20190821222359.13578-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (2 preceding siblings ...)
2019-08-21 22:23 ` [PATCH 03/37] drm/amdgpu/powerplay: add initial renoir_ppt.c for renoir (v3) Alex Deucher
@ 2019-08-21 22:23 ` Alex Deucher
2019-08-21 22:23 ` [PATCH 05/37] drm/amdgpu/powerplay: add smu ip block for renoir (v2) Alex Deucher
` (32 subsequent siblings)
36 siblings, 0 replies; 39+ messages in thread
From: Alex Deucher @ 2019-08-21 22:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alex Deucher, Huang Rui, Aaron Liu
From: Aaron Liu <aaron.liu@amd.com>
add smu_v12_0.c & smu_v12_0.h for renoir
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h | 37 ++++
drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 170 ++++++++++++++++++
2 files changed, 207 insertions(+)
create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
create mode 100644 drivers/gpu/drm/amd/powerplay/smu_v12_0.c
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
new file mode 100644
index 000000000000..278cdc2c0d47
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef __SMU_V12_0_H__
+#define __SMU_V12_0_H__
+
+#include "amdgpu_smu.h"
+
+/* MP Apertures */
+#define MP0_Public 0x03800000
+#define MP0_SRAM 0x03900000
+#define MP1_Public 0x03b00000
+#define MP1_SRAM 0x03c00004
+
+
+void smu_v12_0_set_smu_funcs(struct smu_context *smu);
+
+#endif
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
new file mode 100644
index 000000000000..fdafa2306c29
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
@@ -0,0 +1,170 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "pp_debug.h"
+#include <linux/firmware.h>
+#include "amdgpu.h"
+#include "amdgpu_smu.h"
+#include "atomfirmware.h"
+#include "amdgpu_atomfirmware.h"
+#include "smu_v12_0.h"
+#include "soc15_common.h"
+#include "atom.h"
+#include "renoir_ppt.h"
+
+#include "asic_reg/mp/mp_12_0_0_offset.h"
+#include "asic_reg/mp/mp_12_0_0_sh_mask.h"
+
+#define smnMP1_FIRMWARE_FLAGS 0x3010024
+
+static int smu_v12_0_send_msg_without_waiting(struct smu_context *smu,
+ uint16_t msg)
+{
+ struct amdgpu_device *adev = smu->adev;
+
+ WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
+ return 0;
+}
+
+static int smu_v12_0_read_arg(struct smu_context *smu, uint32_t *arg)
+{
+ struct amdgpu_device *adev = smu->adev;
+
+ *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
+ return 0;
+}
+
+static int smu_v12_0_wait_for_response(struct smu_context *smu)
+{
+ struct amdgpu_device *adev = smu->adev;
+ uint32_t cur_value, i;
+
+ for (i = 0; i < adev->usec_timeout; i++) {
+ cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
+ if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0)
+ break;
+ udelay(1);
+ }
+
+ /* timeout means wrong logic */
+ if (i == adev->usec_timeout)
+ return -ETIME;
+
+ return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
+}
+
+static int smu_v12_0_send_msg(struct smu_context *smu, uint16_t msg)
+{
+ struct amdgpu_device *adev = smu->adev;
+ int ret = 0, index = 0;
+
+ index = smu_msg_get_index(smu, msg);
+ if (index < 0)
+ return index;
+
+ smu_v12_0_wait_for_response(smu);
+
+ WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
+
+ smu_v12_0_send_msg_without_waiting(smu, (uint16_t)index);
+
+ ret = smu_v12_0_wait_for_response(smu);
+
+ if (ret)
+ pr_err("Failed to send message 0x%x, response 0x%x\n", index,
+ ret);
+
+ return ret;
+
+}
+
+static int
+smu_v12_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
+ uint32_t param)
+{
+
+ struct amdgpu_device *adev = smu->adev;
+ int ret = 0, index = 0;
+
+ index = smu_msg_get_index(smu, msg);
+ if (index < 0)
+ return index;
+
+ ret = smu_v12_0_wait_for_response(smu);
+ if (ret)
+ pr_err("Failed to send message 0x%x, response 0x%x, param 0x%x\n",
+ index, ret, param);
+
+ WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
+
+ WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
+
+ smu_v12_0_send_msg_without_waiting(smu, (uint16_t)index);
+
+ ret = smu_v12_0_wait_for_response(smu);
+ if (ret)
+ pr_err("Failed to send message 0x%x, response 0x%x param 0x%x\n",
+ index, ret, param);
+
+ return ret;
+}
+
+static int smu_v12_0_check_fw_version(struct smu_context *smu)
+{
+ uint32_t smu_version = 0xff;
+ int ret = 0;
+
+ ret = smu_send_smc_msg(smu, SMU_MSG_GetDriverIfVersion);
+ if (ret)
+ goto err;
+
+ ret = smu_read_smc_arg(smu, &smu_version);
+ if (ret)
+ goto err;
+
+ if (smu_version != smu->smc_if_version)
+ ret = -EINVAL;
+err:
+ return ret;
+}
+
+static const struct smu_funcs smu_v12_0_funcs = {
+ .check_fw_version = smu_v12_0_check_fw_version,
+ .send_smc_msg = smu_v12_0_send_msg,
+ .send_smc_msg_with_param = smu_v12_0_send_msg_with_param,
+ .read_smc_arg = smu_v12_0_read_arg,
+};
+
+void smu_v12_0_set_smu_funcs(struct smu_context *smu)
+{
+ struct amdgpu_device *adev = smu->adev;
+
+ smu->funcs = &smu_v12_0_funcs;
+
+ switch (adev->asic_type) {
+ case CHIP_RENOIR:
+ renoir_set_ppt_funcs(smu);
+ break;
+ default:
+ pr_warn("Unknown asic for smu12\n");
+ }
+}
--
2.20.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 05/37] drm/amdgpu/powerplay: add smu ip block for renoir (v2)
[not found] ` <20190821222359.13578-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (3 preceding siblings ...)
2019-08-21 22:23 ` [PATCH 04/37] drm/amdgpu/powerplay: add smu_v12_0.c & smu_v12_0.h for renoir Alex Deucher
@ 2019-08-21 22:23 ` Alex Deucher
2019-08-21 22:23 ` [PATCH 06/37] drm/amdgpu/powerplay: add power up/down SDMA interfaces for renoir Alex Deucher
` (31 subsequent siblings)
36 siblings, 0 replies; 39+ messages in thread
From: Alex Deucher @ 2019-08-21 22:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alex Deucher, Huang Rui, Aaron Liu
From: Aaron Liu <aaron.liu@amd.com>
add swSMU [smu_v12_0] for renoir
v2: whitespace fixes (Alex)
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 2 ++
drivers/gpu/drm/amd/powerplay/Makefile | 2 +-
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 19 +++++++++++++++++++
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 2 ++
4 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 2cf61946f3f1..3040e30eb970 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -761,6 +761,8 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
+ if (is_support_sw_smu(adev))
+ amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
diff --git a/drivers/gpu/drm/amd/powerplay/Makefile b/drivers/gpu/drm/amd/powerplay/Makefile
index e05a7e3d6d8d..390345f2d601 100644
--- a/drivers/gpu/drm/amd/powerplay/Makefile
+++ b/drivers/gpu/drm/amd/powerplay/Makefile
@@ -35,7 +35,7 @@ AMD_POWERPLAY = $(addsuffix /Makefile,$(addprefix $(FULL_AMD_PATH)/powerplay/,$(
include $(AMD_POWERPLAY)
-POWER_MGR = amd_powerplay.o amdgpu_smu.o smu_v11_0.o vega20_ppt.o arcturus_ppt.o navi10_ppt.o
+POWER_MGR = amd_powerplay.o amdgpu_smu.o smu_v11_0.o smu_v12_0.o vega20_ppt.o arcturus_ppt.o navi10_ppt.o renoir_ppt.o
AMD_PP_POWER = $(addprefix $(AMD_PP_PATH)/,$(POWER_MGR))
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 4df7fb6eaf3c..54424babc8ca 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -27,6 +27,7 @@
#include "amdgpu_smu.h"
#include "soc15_common.h"
#include "smu_v11_0.h"
+#include "smu_v12_0.h"
#include "atom.h"
#include "amd_pcie.h"
@@ -735,6 +736,12 @@ static int smu_set_funcs(struct amdgpu_device *adev)
smu->od_enabled = true;
smu_v11_0_set_smu_funcs(smu);
break;
+ case CHIP_RENOIR:
+ adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
+ if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
+ smu->od_enabled = true;
+ smu_v12_0_set_smu_funcs(smu);
+ break;
default:
return -EINVAL;
}
@@ -1031,6 +1038,9 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
struct amdgpu_device *adev = smu->adev;
int ret;
+ if (adev->flags & AMD_IS_APU)
+ return 0;
+
if (smu_is_dpm_running(smu) && adev->in_suspend) {
pr_info("dpm has been enabled\n");
return 0;
@@ -1790,3 +1800,12 @@ const struct amdgpu_ip_block_version smu_v11_0_ip_block =
.rev = 0,
.funcs = &smu_ip_funcs,
};
+
+const struct amdgpu_ip_block_version smu_v12_0_ip_block =
+{
+ .type = AMD_IP_BLOCK_TYPE_SMC,
+ .major = 12,
+ .minor = 0,
+ .rev = 0,
+ .funcs = &smu_ip_funcs,
+};
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index e80c81552d29..61d453f83f88 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -755,6 +755,8 @@ extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
extern const struct amd_ip_funcs smu_ip_funcs;
extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
+extern const struct amdgpu_ip_block_version smu_v12_0_ip_block;
+
extern int smu_feature_init_dpm(struct smu_context *smu);
extern int smu_feature_is_enabled(struct smu_context *smu,
--
2.20.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 06/37] drm/amdgpu/powerplay: add power up/down SDMA interfaces for renoir
[not found] ` <20190821222359.13578-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (4 preceding siblings ...)
2019-08-21 22:23 ` [PATCH 05/37] drm/amdgpu/powerplay: add smu ip block for renoir (v2) Alex Deucher
@ 2019-08-21 22:23 ` Alex Deucher
2019-08-21 22:23 ` [PATCH 07/37] drm/amdgpu: skip dpm init " Alex Deucher
` (30 subsequent siblings)
36 siblings, 0 replies; 39+ messages in thread
From: Alex Deucher @ 2019-08-21 22:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alex Deucher, Huang Rui, Aaron Liu
From: Aaron Liu <aaron.liu@amd.com>
1.Implement PowerUpSDMA/PowerDownSDMA interfaces in the swSMU for renoir
2.adjust smu ip block ahead of gfx&sdma ip block
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +--
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 6 ++++
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 ++
drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 35 ++++++++++++++++---
4 files changed, 42 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 3040e30eb970..b226883039e4 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -759,10 +759,10 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
- amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
- amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
if (is_support_sw_smu(adev))
amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 54424babc8ca..d6c66216eb95 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1263,6 +1263,9 @@ static int smu_hw_init(void *handle)
return ret;
}
+ if (adev->asic_type == CHIP_RENOIR)
+ smu_powergate_sdma(&adev->smu, false);
+
if (!smu->pm_enabled)
return 0;
@@ -1310,6 +1313,9 @@ static int smu_hw_fini(void *handle)
struct smu_table_context *table_context = &smu->smu_table;
int ret = 0;
+ if (adev->asic_type == CHIP_RENOIR)
+ smu_powergate_sdma(&adev->smu, true);
+
kfree(table_context->driver_pptable);
table_context->driver_pptable = NULL;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 61d453f83f88..536f547f01c5 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -473,6 +473,7 @@ struct smu_funcs
int (*parse_pptable)(struct smu_context *smu);
int (*populate_smc_pptable)(struct smu_context *smu);
int (*check_fw_version)(struct smu_context *smu);
+ int (*powergate_sdma)(struct smu_context *smu, bool gate);
int (*write_pptable)(struct smu_context *smu);
int (*set_min_dcef_deep_sleep)(struct smu_context *smu);
int (*set_tool_table_location)(struct smu_context *smu);
@@ -549,6 +550,8 @@ struct smu_funcs
((smu)->funcs->check_fw_status ? (smu)->funcs->check_fw_status((smu)) : 0)
#define smu_setup_pptable(smu) \
((smu)->funcs->setup_pptable ? (smu)->funcs->setup_pptable((smu)) : 0)
+#define smu_powergate_sdma(smu, gate) \
+ ((smu)->funcs->powergate_sdma ? (smu)->funcs->powergate_sdma((smu), (gate)) : 0)
#define smu_get_vbios_bootup_values(smu) \
((smu)->funcs->get_vbios_bootup_values ? (smu)->funcs->get_vbios_bootup_values((smu)) : 0)
#define smu_get_clk_info_from_vbios(smu) \
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
index fdafa2306c29..cba8507a02af 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
@@ -101,7 +101,6 @@ static int
smu_v12_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
uint32_t param)
{
-
struct amdgpu_device *adev = smu->adev;
int ret = 0, index = 0;
@@ -128,27 +127,55 @@ smu_v12_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
return ret;
}
+static int smu_v12_0_check_fw_status(struct smu_context *smu)
+{
+ struct amdgpu_device *adev = smu->adev;
+ uint32_t mp1_fw_flags;
+
+ mp1_fw_flags = RREG32_PCIE(MP1_Public |
+ (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
+
+ if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
+ MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
+ return 0;
+
+ return -EIO;
+}
+
static int smu_v12_0_check_fw_version(struct smu_context *smu)
{
- uint32_t smu_version = 0xff;
+ uint32_t smc_if_version = 0xff;
int ret = 0;
ret = smu_send_smc_msg(smu, SMU_MSG_GetDriverIfVersion);
if (ret)
goto err;
- ret = smu_read_smc_arg(smu, &smu_version);
+ ret = smu_read_smc_arg(smu, &smc_if_version);
if (ret)
goto err;
- if (smu_version != smu->smc_if_version)
+ if (smc_if_version != smu->smc_if_version)
ret = -EINVAL;
err:
return ret;
}
+static int smu_v12_0_powergate_sdma(struct smu_context *smu, bool gate)
+{
+ if (!(smu->adev->flags & AMD_IS_APU))
+ return 0;
+
+ if (gate)
+ return smu_send_smc_msg(smu, SMU_MSG_PowerDownSdma);
+ else
+ return smu_send_smc_msg(smu, SMU_MSG_PowerUpSdma);
+}
+
static const struct smu_funcs smu_v12_0_funcs = {
+ .check_fw_status = smu_v12_0_check_fw_status,
.check_fw_version = smu_v12_0_check_fw_version,
+ .powergate_sdma = smu_v12_0_powergate_sdma,
.send_smc_msg = smu_v12_0_send_msg,
.send_smc_msg_with_param = smu_v12_0_send_msg_with_param,
.read_smc_arg = smu_v12_0_read_arg,
--
2.20.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 07/37] drm/amdgpu: skip dpm init for renoir
[not found] ` <20190821222359.13578-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (5 preceding siblings ...)
2019-08-21 22:23 ` [PATCH 06/37] drm/amdgpu/powerplay: add power up/down SDMA interfaces for renoir Alex Deucher
@ 2019-08-21 22:23 ` Alex Deucher
2019-08-21 22:23 ` [PATCH 08/37] drm/amdgpu/powerplay: add Renoir VCN power management Alex Deucher
` (29 subsequent siblings)
36 siblings, 0 replies; 39+ messages in thread
From: Alex Deucher @ 2019-08-21 22:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
Renoir DPM is not functional so far, we skip it for the comment.
Will revert this patch once SMU 12 is functional.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index d6c66216eb95..5ab3e7b8c68a 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -768,6 +768,11 @@ static int smu_late_init(void *handle)
if (!smu->pm_enabled)
return 0;
+
+ /* To be removed after dpm is enabled */
+ if (adev->asic_type == CHIP_RENOIR)
+ return 0;
+
mutex_lock(&smu->mutex);
smu_handle_task(&adev->smu,
smu->smu_dpm.dpm_level,
@@ -1269,6 +1274,10 @@ static int smu_hw_init(void *handle)
if (!smu->pm_enabled)
return 0;
+ /* To be removed after dpm is enabled */
+ if (adev->asic_type == CHIP_RENOIR)
+ return 0;
+
ret = smu_feature_init_dpm(smu);
if (ret)
goto failed;
--
2.20.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 08/37] drm/amdgpu/powerplay: add Renoir VCN power management
[not found] ` <20190821222359.13578-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (6 preceding siblings ...)
2019-08-21 22:23 ` [PATCH 07/37] drm/amdgpu: skip dpm init " Alex Deucher
@ 2019-08-21 22:23 ` Alex Deucher
2019-08-21 22:23 ` [PATCH 09/37] drm/amd/powerplay: powerup sdma/vcn for all apu series Alex Deucher
` (28 subsequent siblings)
36 siblings, 0 replies; 39+ messages in thread
From: Alex Deucher @ 2019-08-21 22:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alex Deucher, Huang Rui, Evan Quan, Leo Liu, Aaron Liu
From: Leo Liu <leo.liu@amd.com>
Thus VCN can be powered up for normal operations
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 8 ++++++--
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +++
drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 12 ++++++++++++
3 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 5ab3e7b8c68a..022507eacf1a 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1268,8 +1268,10 @@ static int smu_hw_init(void *handle)
return ret;
}
- if (adev->asic_type == CHIP_RENOIR)
+ if (adev->asic_type == CHIP_RENOIR) {
smu_powergate_sdma(&adev->smu, false);
+ smu_powergate_vcn(&adev->smu, false);
+ }
if (!smu->pm_enabled)
return 0;
@@ -1322,8 +1324,10 @@ static int smu_hw_fini(void *handle)
struct smu_table_context *table_context = &smu->smu_table;
int ret = 0;
- if (adev->asic_type == CHIP_RENOIR)
+ if (adev->asic_type == CHIP_RENOIR) {
smu_powergate_sdma(&adev->smu, true);
+ smu_powergate_vcn(&adev->smu, true);
+ }
kfree(table_context->driver_pptable);
table_context->driver_pptable = NULL;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 536f547f01c5..605767e79996 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -474,6 +474,7 @@ struct smu_funcs
int (*populate_smc_pptable)(struct smu_context *smu);
int (*check_fw_version)(struct smu_context *smu);
int (*powergate_sdma)(struct smu_context *smu, bool gate);
+ int (*powergate_vcn)(struct smu_context *smu, bool gate);
int (*write_pptable)(struct smu_context *smu);
int (*set_min_dcef_deep_sleep)(struct smu_context *smu);
int (*set_tool_table_location)(struct smu_context *smu);
@@ -552,6 +553,8 @@ struct smu_funcs
((smu)->funcs->setup_pptable ? (smu)->funcs->setup_pptable((smu)) : 0)
#define smu_powergate_sdma(smu, gate) \
((smu)->funcs->powergate_sdma ? (smu)->funcs->powergate_sdma((smu), (gate)) : 0)
+#define smu_powergate_vcn(smu, gate) \
+ ((smu)->funcs->powergate_vcn ? (smu)->funcs->powergate_vcn((smu), (gate)) : 0)
#define smu_get_vbios_bootup_values(smu) \
((smu)->funcs->get_vbios_bootup_values ? (smu)->funcs->get_vbios_bootup_values((smu)) : 0)
#define smu_get_clk_info_from_vbios(smu) \
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
index cba8507a02af..583fe7da4a4b 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
@@ -172,10 +172,22 @@ static int smu_v12_0_powergate_sdma(struct smu_context *smu, bool gate)
return smu_send_smc_msg(smu, SMU_MSG_PowerUpSdma);
}
+static int smu_v12_0_powergate_vcn(struct smu_context *smu, bool gate)
+{
+ if (!(smu->adev->flags & AMD_IS_APU))
+ return 0;
+
+ if (gate)
+ return smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
+ else
+ return smu_send_smc_msg(smu, SMU_MSG_PowerUpVcn);
+}
+
static const struct smu_funcs smu_v12_0_funcs = {
.check_fw_status = smu_v12_0_check_fw_status,
.check_fw_version = smu_v12_0_check_fw_version,
.powergate_sdma = smu_v12_0_powergate_sdma,
+ .powergate_vcn = smu_v12_0_powergate_vcn,
.send_smc_msg = smu_v12_0_send_msg,
.send_smc_msg_with_param = smu_v12_0_send_msg_with_param,
.read_smc_arg = smu_v12_0_read_arg,
--
2.20.1
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 09/37] drm/amd/powerplay: powerup sdma/vcn for all apu series
[not found] ` <20190821222359.13578-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (7 preceding siblings ...)
2019-08-21 22:23 ` [PATCH 08/37] drm/amdgpu/powerplay: add Renoir VCN power management Alex Deucher
@ 2019-08-21 22:23 ` Alex Deucher
2019-08-21 22:23 ` [PATCH 10/37] drm/amd/powerplay: udpate smu_v12_0_check_fw_version (v2) Alex Deucher
` (27 subsequent siblings)
36 siblings, 0 replies; 39+ messages in thread
From: Alex Deucher @ 2019-08-21 22:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alex Deucher, Huang Rui, Evan Quan
From: Huang Rui <ray.huang@amd.com>
All apu series need powerup sdma and vcn via smu messages.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 022507eacf1a..85f52401d5a1 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1268,7 +1268,7 @@ static int smu_hw_init(void *handle)
return ret;
}
- if (adev->asic_type == CHIP_RENOIR) {
+ if (adev->flags & AMD_IS_APU) {
smu_powergate_sdma(&adev->smu, false);
smu_powergate_vcn(&adev->smu, false);
}
@@ -1324,7 +1324,7 @@ static int smu_hw_fini(void *handle)
struct smu_table_context *table_context = &smu->smu_table;
int ret = 0;
- if (adev->asic_type == CHIP_RENOIR) {
+ if (adev->flags & AMD_IS_APU) {
smu_powergate_sdma(&adev->smu, true);
smu_powergate_vcn(&adev->smu, true);
}
--
2.20.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 10/37] drm/amd/powerplay: udpate smu_v12_0_check_fw_version (v2)
[not found] ` <20190821222359.13578-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (8 preceding siblings ...)
2019-08-21 22:23 ` [PATCH 09/37] drm/amd/powerplay: powerup sdma/vcn for all apu series Alex Deucher
@ 2019-08-21 22:23 ` Alex Deucher
2019-08-21 22:23 ` [PATCH 11/37] drm/amdgpu: add set_gfx_cgpg implement (v2) Alex Deucher
` (26 subsequent siblings)
36 siblings, 0 replies; 39+ messages in thread
From: Alex Deucher @ 2019-08-21 22:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alex Deucher, Huang Rui, Aaron Liu, Evan Quan
From: Aaron Liu <aaron.liu@amd.com>
This interface support SMU_MSG_GetDriverIfVersion
and SMU_MSG_GetSmuVersion checking.
v2: squash in driver_if changes (Alex)
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 2 ++
drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 35 +++++++++++++++-------
2 files changed, 27 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index dd270600962b..af8bb1cc5d9a 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -25,6 +25,7 @@
#include "amdgpu_smu.h"
#include "soc15_common.h"
#include "smu_v12_0_ppsmc.h"
+#include "smu12_driver_if.h"
#include "renoir_ppt.h"
@@ -118,4 +119,5 @@ static const struct pptable_funcs renoir_ppt_funcs = {
void renoir_set_ppt_funcs(struct smu_context *smu)
{
smu->ppt_funcs = &renoir_ppt_funcs;
+ smu->smc_if_version = SMU12_DRIVER_IF_VERSION;
}
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
index 583fe7da4a4b..695b9af8662b 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
@@ -144,20 +144,35 @@ static int smu_v12_0_check_fw_status(struct smu_context *smu)
static int smu_v12_0_check_fw_version(struct smu_context *smu)
{
- uint32_t smc_if_version = 0xff;
+ uint32_t if_version = 0xff, smu_version = 0xff;
+ uint16_t smu_major;
+ uint8_t smu_minor, smu_debug;
int ret = 0;
- ret = smu_send_smc_msg(smu, SMU_MSG_GetDriverIfVersion);
+ ret = smu_get_smc_version(smu, &if_version, &smu_version);
if (ret)
- goto err;
-
- ret = smu_read_smc_arg(smu, &smc_if_version);
- if (ret)
- goto err;
+ return ret;
+
+ smu_major = (smu_version >> 16) & 0xffff;
+ smu_minor = (smu_version >> 8) & 0xff;
+ smu_debug = (smu_version >> 0) & 0xff;
+
+ /*
+ * 1. if_version mismatch is not critical as our fw is designed
+ * to be backward compatible.
+ * 2. New fw usually brings some optimizations. But that's visible
+ * only on the paired driver.
+ * Considering above, we just leave user a warning message instead
+ * of halt driver loading.
+ */
+ if (if_version != smu->smc_if_version) {
+ pr_info("smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
+ "smu fw version = 0x%08x (%d.%d.%d)\n",
+ smu->smc_if_version, if_version,
+ smu_version, smu_major, smu_minor, smu_debug);
+ pr_warn("SMU driver if version not matched\n");
+ }
- if (smc_if_version != smu->smc_if_version)
- ret = -EINVAL;
-err:
return ret;
}
--
2.20.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 11/37] drm/amdgpu: add set_gfx_cgpg implement (v2)
[not found] ` <20190821222359.13578-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (9 preceding siblings ...)
2019-08-21 22:23 ` [PATCH 10/37] drm/amd/powerplay: udpate smu_v12_0_check_fw_version (v2) Alex Deucher
@ 2019-08-21 22:23 ` Alex Deucher
2019-08-21 22:23 ` [PATCH 12/37] drm/amdgpu: add and enable gfxoff feature Alex Deucher
` (25 subsequent siblings)
36 siblings, 0 replies; 39+ messages in thread
From: Alex Deucher @ 2019-08-21 22:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alex Deucher, Huang Rui, Aaron Liu, Evan Quan
From: Aaron Liu <aaron.liu@amd.com>
add set_gfx_cgpg implement
v2: check if using sw_smu (Alex)
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 +++++
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3 +++
drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 10 ++++++++++
3 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 6eea9c675d01..48f8d5ae67f3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4551,6 +4551,9 @@ static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
{
amdgpu_gfx_rlc_enter_safe_mode(adev);
+ if (is_support_sw_smu(adev) && !enable)
+ smu_set_gfx_cgpg(&adev->smu, enable);
+
if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
gfx_v9_0_enable_gfx_cg_power_gating(adev, true);
if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
@@ -4826,6 +4829,8 @@ static int gfx_v9_0_set_powergating_state(void *handle,
gfx_v9_0_enable_cp_power_gating(adev, false);
/* update gfx cgpg state */
+ if (is_support_sw_smu(adev) && enable)
+ smu_set_gfx_cgpg(&adev->smu, enable);
gfx_v9_0_update_gfx_cg_power_gating(adev, enable);
/* update mgcg state */
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 605767e79996..7b352c5a451e 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -475,6 +475,7 @@ struct smu_funcs
int (*check_fw_version)(struct smu_context *smu);
int (*powergate_sdma)(struct smu_context *smu, bool gate);
int (*powergate_vcn)(struct smu_context *smu, bool gate);
+ int (*set_gfx_cgpg)(struct smu_context *smu, bool enable);
int (*write_pptable)(struct smu_context *smu);
int (*set_min_dcef_deep_sleep)(struct smu_context *smu);
int (*set_tool_table_location)(struct smu_context *smu);
@@ -555,6 +556,8 @@ struct smu_funcs
((smu)->funcs->powergate_sdma ? (smu)->funcs->powergate_sdma((smu), (gate)) : 0)
#define smu_powergate_vcn(smu, gate) \
((smu)->funcs->powergate_vcn ? (smu)->funcs->powergate_vcn((smu), (gate)) : 0)
+#define smu_set_gfx_cgpg(smu, enabled) \
+ ((smu)->funcs->set_gfx_cgpg ? (smu)->funcs->set_gfx_cgpg((smu), (enabled)) : 0)
#define smu_get_vbios_bootup_values(smu) \
((smu)->funcs->get_vbios_bootup_values ? (smu)->funcs->get_vbios_bootup_values((smu)) : 0)
#define smu_get_clk_info_from_vbios(smu) \
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
index 695b9af8662b..cf523b8b2aeb 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
@@ -198,6 +198,15 @@ static int smu_v12_0_powergate_vcn(struct smu_context *smu, bool gate)
return smu_send_smc_msg(smu, SMU_MSG_PowerUpVcn);
}
+static int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable)
+{
+ if (!(smu->adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
+ return 0;
+
+ return smu_v12_0_send_msg_with_param(smu,
+ SMU_MSG_SetGfxCGPG, enable ? 1 : 0);
+}
+
static const struct smu_funcs smu_v12_0_funcs = {
.check_fw_status = smu_v12_0_check_fw_status,
.check_fw_version = smu_v12_0_check_fw_version,
@@ -206,6 +215,7 @@ static const struct smu_funcs smu_v12_0_funcs = {
.send_smc_msg = smu_v12_0_send_msg,
.send_smc_msg_with_param = smu_v12_0_send_msg_with_param,
.read_smc_arg = smu_v12_0_read_arg,
+ .set_gfx_cgpg = smu_v12_0_set_gfx_cgpg,
};
void smu_v12_0_set_smu_funcs(struct smu_context *smu)
--
2.20.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 12/37] drm/amdgpu: add and enable gfxoff feature
[not found] ` <20190821222359.13578-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (10 preceding siblings ...)
2019-08-21 22:23 ` [PATCH 11/37] drm/amdgpu: add set_gfx_cgpg implement (v2) Alex Deucher
@ 2019-08-21 22:23 ` Alex Deucher
2019-08-21 22:23 ` [PATCH 13/37] drm/amd/powerplay: fix checking gfxoff status for rn Alex Deucher
` (24 subsequent siblings)
36 siblings, 0 replies; 39+ messages in thread
From: Alex Deucher @ 2019-08-21 22:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alex Deucher, Kevin Wang, Huang Rui, Aaron Liu, Evan Quan
From: Aaron Liu <aaron.liu@amd.com>
This patch updates gfxoff feature.
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 5 +++
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 1 -
drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 44 ++++++++++++++++++++++
3 files changed, 49 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index b226883039e4..c092be45f5e2 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -1157,6 +1157,11 @@ static int soc15_common_early_init(void *handle)
adev->cg_flags = 0;
adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x91;
+
+ if (adev->pm.pp_feature & PP_GFXOFF_MASK)
+ adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
+ AMD_PG_SUPPORT_CP |
+ AMD_PG_SUPPORT_RLC_SMU_HS;
break;
default:
/* FIXME: not supported yet */
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 85f52401d5a1..6505690cfa76 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -737,7 +737,6 @@ static int smu_set_funcs(struct amdgpu_device *adev)
smu_v11_0_set_smu_funcs(smu);
break;
case CHIP_RENOIR:
- adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
smu->od_enabled = true;
smu_v12_0_set_smu_funcs(smu);
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
index cf523b8b2aeb..7d4e966cc9f0 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
@@ -36,6 +36,13 @@
#define smnMP1_FIRMWARE_FLAGS 0x3010024
+#define mmPWR_MISC_CNTL_STATUS 0x0183
+#define mmPWR_MISC_CNTL_STATUS_BASE_IDX 0
+#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT 0x0
+#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 0x1
+#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 0x00000001L
+#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK 0x00000006L
+
static int smu_v12_0_send_msg_without_waiting(struct smu_context *smu,
uint16_t msg)
{
@@ -207,6 +214,42 @@ static int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable)
SMU_MSG_SetGfxCGPG, enable ? 1 : 0);
}
+static bool smu_v12_0_is_gfx_on(struct smu_context *smu)
+{
+ uint32_t reg;
+ struct amdgpu_device *adev = smu->adev;
+
+ reg = RREG32_SOC15(PWR, 0, mmPWR_MISC_CNTL_STATUS);
+ if ((reg & PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK) ==
+ (0x2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT))
+ return true;
+
+ return false;
+}
+
+static int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable)
+{
+ int ret = 0, timeout = 10;
+
+ if (enable) {
+ ret = smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff);
+ } else {
+ ret = smu_send_smc_msg(smu, SMU_MSG_DisallowGfxOff);
+
+ /* confirm gfx is back to "on" state */
+ while (!smu_v12_0_is_gfx_on(smu)) {
+ msleep(1);
+ timeout--;
+ if (timeout == 0) {
+ DRM_ERROR("disable gfxoff timeout and failed!\n");
+ break;
+ }
+ }
+ }
+
+ return ret;
+}
+
static const struct smu_funcs smu_v12_0_funcs = {
.check_fw_status = smu_v12_0_check_fw_status,
.check_fw_version = smu_v12_0_check_fw_version,
@@ -216,6 +259,7 @@ static const struct smu_funcs smu_v12_0_funcs = {
.send_smc_msg_with_param = smu_v12_0_send_msg_with_param,
.read_smc_arg = smu_v12_0_read_arg,
.set_gfx_cgpg = smu_v12_0_set_gfx_cgpg,
+ .gfx_off_control = smu_v12_0_gfx_off_control,
};
void smu_v12_0_set_smu_funcs(struct smu_context *smu)
--
2.20.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 13/37] drm/amd/powerplay: fix checking gfxoff status for rn
[not found] ` <20190821222359.13578-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (11 preceding siblings ...)
2019-08-21 22:23 ` [PATCH 12/37] drm/amdgpu: add and enable gfxoff feature Alex Deucher
@ 2019-08-21 22:23 ` Alex Deucher
2019-08-21 22:23 ` [PATCH 14/37] drm/amd/powerplay: using valid mapping check " Alex Deucher
` (23 subsequent siblings)
36 siblings, 0 replies; 39+ messages in thread
From: Alex Deucher @ 2019-08-21 22:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alex Deucher, Huang Rui, Aaron Liu, Evan Quan
From: Aaron Liu <aaron.liu@amd.com>
For renoir, it should use mmSMUIO_GFX_MISC_CNTL to check
gfxoff status. For the first time to enter gfxoff status,
it maybe takes about one second more. So just set the max
timeout to 5s.
GFXOFF_STATUS(bits 2:1)'s description is below:
0=GFXOFF(default).
1=Transition out of GFX State.
2=Not in GFXOFF.
3=Transition into GFXOFF.
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 50 ++++++++++++++++-------
1 file changed, 35 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
index 7d4e966cc9f0..363a5a76b6a6 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
@@ -36,12 +36,10 @@
#define smnMP1_FIRMWARE_FLAGS 0x3010024
-#define mmPWR_MISC_CNTL_STATUS 0x0183
-#define mmPWR_MISC_CNTL_STATUS_BASE_IDX 0
-#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT 0x0
-#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 0x1
-#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 0x00000001L
-#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK 0x00000006L
+#define mmSMUIO_GFX_MISC_CNTL 0x00c8
+#define mmSMUIO_GFX_MISC_CNTL_BASE_IDX 0
+#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK 0x00000006L
+#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT 0x1
static int smu_v12_0_send_msg_without_waiting(struct smu_context *smu,
uint16_t msg)
@@ -214,30 +212,52 @@ static int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable)
SMU_MSG_SetGfxCGPG, enable ? 1 : 0);
}
-static bool smu_v12_0_is_gfx_on(struct smu_context *smu)
+/**
+ * smu_v12_0_get_gfxoff_status - get gfxoff status
+ *
+ * @smu: amdgpu_device pointer
+ *
+ * This function will be used to get gfxoff status
+ *
+ * Returns 0=GFXOFF(default).
+ * Returns 1=Transition out of GFX State.
+ * Returns 2=Not in GFXOFF.
+ * Returns 3=Transition into GFXOFF.
+ */
+static uint32_t smu_v12_0_get_gfxoff_status(struct smu_context *smu)
{
uint32_t reg;
+ uint32_t gfxOff_Status = 0;
struct amdgpu_device *adev = smu->adev;
- reg = RREG32_SOC15(PWR, 0, mmPWR_MISC_CNTL_STATUS);
- if ((reg & PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK) ==
- (0x2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT))
- return true;
+ reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_GFX_MISC_CNTL);
+ gfxOff_Status = (reg & SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK)
+ >> SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT;
- return false;
+ return gfxOff_Status;
}
static int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable)
{
- int ret = 0, timeout = 10;
+ int ret = 0, timeout = 500;
if (enable) {
ret = smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff);
+
+ /* confirm gfx is back to "off" state, timeout is 5 seconds */
+ while (!(smu_v12_0_get_gfxoff_status(smu) == 0)) {
+ msleep(10);
+ timeout--;
+ if (timeout == 0) {
+ DRM_ERROR("enable gfxoff timeout and failed!\n");
+ break;
+ }
+ }
} else {
ret = smu_send_smc_msg(smu, SMU_MSG_DisallowGfxOff);
- /* confirm gfx is back to "on" state */
- while (!smu_v12_0_is_gfx_on(smu)) {
+ /* confirm gfx is back to "on" state, timeout is 0.5 second */
+ while (!(smu_v12_0_get_gfxoff_status(smu) == 2)) {
msleep(1);
timeout--;
if (timeout == 0) {
--
2.20.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 14/37] drm/amd/powerplay: using valid mapping check for rn
[not found] ` <20190821222359.13578-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (12 preceding siblings ...)
2019-08-21 22:23 ` [PATCH 13/37] drm/amd/powerplay: fix checking gfxoff status for rn Alex Deucher
@ 2019-08-21 22:23 ` Alex Deucher
2019-08-21 22:23 ` [PATCH 15/37] drm/amd/powerplay: add smu tables " Alex Deucher
` (22 subsequent siblings)
36 siblings, 0 replies; 39+ messages in thread
From: Alex Deucher @ 2019-08-21 22:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alex Deucher, Evan Quan, Kenneth Feng, Aaron Liu, Kevin Wang
From: Aaron Liu <aaron.liu@amd.com>
Check whether the message mapping is valid
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h | 5 +++++
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 13 +++++++------
2 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
index 278cdc2c0d47..acf3db12f59f 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
@@ -32,6 +32,11 @@
#define MP1_SRAM 0x03c00004
+struct smu_12_0_cmn2aisc_mapping {
+ int valid_mapping;
+ int map_to;
+};
+
void smu_v12_0_set_smu_funcs(struct smu_context *smu);
#endif
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index af8bb1cc5d9a..2580383ff49b 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -26,13 +26,14 @@
#include "soc15_common.h"
#include "smu_v12_0_ppsmc.h"
#include "smu12_driver_if.h"
+#include "smu_v12_0.h"
#include "renoir_ppt.h"
#define MSG_MAP(msg, index) \
- [SMU_MSG_##msg] = index
+ [SMU_MSG_##msg] = {1, (index)}
-static int renoir_message_map[SMU_MSG_MAX_COUNT] = {
+static struct smu_12_0_cmn2aisc_mapping renoir_message_map[SMU_MSG_MAX_COUNT] = {
MSG_MAP(TestMessage, PPSMC_MSG_TestMessage),
MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion),
MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion),
@@ -98,16 +99,16 @@ static int renoir_message_map[SMU_MSG_MAX_COUNT] = {
static int renoir_get_smu_msg_index(struct smu_context *smc, uint32_t index)
{
- int val;
+ struct smu_12_0_cmn2aisc_mapping mapping;
if (index >= SMU_MSG_MAX_COUNT)
return -EINVAL;
- val = renoir_message_map[index];
- if (val > PPSMC_Message_Count)
+ mapping = renoir_message_map[index];
+ if (!(mapping.valid_mapping))
return -EINVAL;
- return val;
+ return mapping.map_to;
}
--
2.20.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 15/37] drm/amd/powerplay: add smu tables for rn
[not found] ` <20190821222359.13578-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (13 preceding siblings ...)
2019-08-21 22:23 ` [PATCH 14/37] drm/amd/powerplay: using valid mapping check " Alex Deucher
@ 2019-08-21 22:23 ` Alex Deucher
2019-08-21 22:23 ` [PATCH 16/37] drm/amd/powerplay: init " Alex Deucher
` (21 subsequent siblings)
36 siblings, 0 replies; 39+ messages in thread
From: Alex Deucher @ 2019-08-21 22:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alex Deucher, Evan Quan, Kenneth Feng, Aaron Liu, Kevin Wang
From: Aaron Liu <aaron.liu@amd.com>
add and map smu tables for renoir
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 2 ++
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 27 +++++++++++++++++++
2 files changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 7b352c5a451e..4d156e5ab2e8 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -231,6 +231,8 @@ enum smu_table_id
{
SMU_TABLE_PPTABLE = 0,
SMU_TABLE_WATERMARKS,
+ SMU_TABLE_CUSTOM_DPM,
+ SMU_TABLE_DPMCLOCKS,
SMU_TABLE_AVFS,
SMU_TABLE_AVFS_PSM_DEBUG,
SMU_TABLE_AVFS_FUSE_OVERRIDE,
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 2580383ff49b..7c3dc150eaa3 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -33,6 +33,12 @@
#define MSG_MAP(msg, index) \
[SMU_MSG_##msg] = {1, (index)}
+#define TAB_MAP_VALID(tab) \
+ [SMU_TABLE_##tab] = {1, TABLE_##tab}
+
+#define TAB_MAP_INVALID(tab) \
+ [SMU_TABLE_##tab] = {0, TABLE_##tab}
+
static struct smu_12_0_cmn2aisc_mapping renoir_message_map[SMU_MSG_MAX_COUNT] = {
MSG_MAP(TestMessage, PPSMC_MSG_TestMessage),
MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion),
@@ -97,6 +103,13 @@ static struct smu_12_0_cmn2aisc_mapping renoir_message_map[SMU_MSG_MAX_COUNT] =
MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq),
};
+static struct smu_12_0_cmn2aisc_mapping renoir_table_map[SMU_TABLE_COUNT] = {
+ TAB_MAP_VALID(WATERMARKS),
+ TAB_MAP_INVALID(CUSTOM_DPM),
+ TAB_MAP_VALID(DPMCLOCKS),
+ TAB_MAP_VALID(SMU_METRICS),
+};
+
static int renoir_get_smu_msg_index(struct smu_context *smc, uint32_t index)
{
struct smu_12_0_cmn2aisc_mapping mapping;
@@ -111,9 +124,23 @@ static int renoir_get_smu_msg_index(struct smu_context *smc, uint32_t index)
return mapping.map_to;
}
+static int renoir_get_smu_table_index(struct smu_context *smc, uint32_t index)
+{
+ struct smu_12_0_cmn2aisc_mapping mapping;
+
+ if (index >= SMU_TABLE_COUNT)
+ return -EINVAL;
+
+ mapping = renoir_table_map[index];
+ if (!(mapping.valid_mapping))
+ return -EINVAL;
+
+ return mapping.map_to;
+}
static const struct pptable_funcs renoir_ppt_funcs = {
.get_smu_msg_index = renoir_get_smu_msg_index,
+ .get_smu_table_index = renoir_get_smu_table_index,
.set_power_state = NULL,
};
--
2.20.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 16/37] drm/amd/powerplay: init smu tables for rn
[not found] ` <20190821222359.13578-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (14 preceding siblings ...)
2019-08-21 22:23 ` [PATCH 15/37] drm/amd/powerplay: add smu tables " Alex Deucher
@ 2019-08-21 22:23 ` Alex Deucher
2019-08-21 22:23 ` [PATCH 17/37] drm/amd/powerplay: add DPMCLOCKS table implementation Alex Deucher
` (20 subsequent siblings)
36 siblings, 0 replies; 39+ messages in thread
From: Alex Deucher @ 2019-08-21 22:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alex Deucher, Evan Quan, Kenneth Feng, Aaron Liu, Kevin Wang
From: Aaron Liu <aaron.liu@amd.com>
Initialize smu tables for renoir:
WATERMARKS/DPMCLOCKS/SMU_METRICS
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 16 +++++++++++
drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 32 ++++++++++++++++++++++
2 files changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 7c3dc150eaa3..c8e0d79de43e 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -138,14 +138,30 @@ static int renoir_get_smu_table_index(struct smu_context *smc, uint32_t index)
return mapping.map_to;
}
+static int renoir_tables_init(struct smu_context *smu, struct smu_table *tables)
+{
+ SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
+ PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
+ SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),
+ PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
+ SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
+ PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
+
+ return 0;
+}
+
static const struct pptable_funcs renoir_ppt_funcs = {
.get_smu_msg_index = renoir_get_smu_msg_index,
.get_smu_table_index = renoir_get_smu_table_index,
+ .tables_init = renoir_tables_init,
.set_power_state = NULL,
};
void renoir_set_ppt_funcs(struct smu_context *smu)
{
+ struct smu_table_context *smu_table = &smu->smu_table;
+
smu->ppt_funcs = &renoir_ppt_funcs;
smu->smc_if_version = SMU12_DRIVER_IF_VERSION;
+ smu_table->table_count = TABLE_COUNT;
}
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
index 363a5a76b6a6..76a6c4b7b63c 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
@@ -270,6 +270,36 @@ static int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable)
return ret;
}
+static int smu_v12_0_init_smc_tables(struct smu_context *smu)
+{
+ struct smu_table_context *smu_table = &smu->smu_table;
+ struct smu_table *tables = NULL;
+
+ if (smu_table->tables || smu_table->table_count == 0)
+ return -EINVAL;
+
+ tables = kcalloc(SMU_TABLE_COUNT, sizeof(struct smu_table),
+ GFP_KERNEL);
+ if (!tables)
+ return -ENOMEM;
+
+ smu_table->tables = tables;
+
+ return smu_tables_init(smu, tables);
+}
+
+static int smu_v12_0_fini_smc_tables(struct smu_context *smu)
+{
+ struct smu_table_context *smu_table = &smu->smu_table;
+
+ if (!smu_table->tables || smu_table->table_count == 0)
+ return -EINVAL;
+
+ kfree(smu_table->tables);
+ smu_table->tables = NULL;
+
+ return 0;
+}
static const struct smu_funcs smu_v12_0_funcs = {
.check_fw_status = smu_v12_0_check_fw_status,
.check_fw_version = smu_v12_0_check_fw_version,
@@ -280,6 +310,8 @@ static const struct smu_funcs smu_v12_0_funcs = {
.read_smc_arg = smu_v12_0_read_arg,
.set_gfx_cgpg = smu_v12_0_set_gfx_cgpg,
.gfx_off_control = smu_v12_0_gfx_off_control,
+ .init_smc_tables = smu_v12_0_init_smc_tables,
+ .fini_smc_tables = smu_v12_0_fini_smc_tables,
};
void smu_v12_0_set_smu_funcs(struct smu_context *smu)
--
2.20.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 17/37] drm/amd/powerplay: add DPMCLOCKS table implementation
[not found] ` <20190821222359.13578-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (15 preceding siblings ...)
2019-08-21 22:23 ` [PATCH 16/37] drm/amd/powerplay: init " Alex Deucher
@ 2019-08-21 22:23 ` Alex Deucher
2019-08-21 22:23 ` [PATCH 18/37] drm/amdgpu: disable gfxoff for the moment on renoir Alex Deucher
` (19 subsequent siblings)
36 siblings, 0 replies; 39+ messages in thread
From: Alex Deucher @ 2019-08-21 22:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alex Deucher, Evan Quan, Kenneth Feng, Aaron Liu, Kevin Wang
From: Aaron Liu <aaron.liu@amd.com>
This patch adds add DPMCLOCKS table implementation
Rename smu_populate_smc_pptable to smu_populate_smc_tables
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 +-
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 7 ++++---
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 6 ++++++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 2 +-
drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 20 +++++++++++++++++++
5 files changed, 32 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 6505690cfa76..ebfd631521c8 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1150,7 +1150,7 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
* type of clks.
*/
if (initialize) {
- ret = smu_populate_smc_pptable(smu);
+ ret = smu_populate_smc_tables(smu);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 4d156e5ab2e8..c42691a9afd3 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -253,6 +253,7 @@ struct smu_table_context
void *hardcode_pptable;
unsigned long metrics_time;
void *metrics_table;
+ void *clocks_table;
void *max_sustainable_clocks;
struct smu_bios_boot_up_values boot_values;
@@ -473,7 +474,7 @@ struct smu_funcs
int (*get_clk_info_from_vbios)(struct smu_context *smu);
int (*check_pptable)(struct smu_context *smu);
int (*parse_pptable)(struct smu_context *smu);
- int (*populate_smc_pptable)(struct smu_context *smu);
+ int (*populate_smc_tables)(struct smu_context *smu);
int (*check_fw_version)(struct smu_context *smu);
int (*powergate_sdma)(struct smu_context *smu, bool gate);
int (*powergate_vcn)(struct smu_context *smu, bool gate);
@@ -568,8 +569,8 @@ struct smu_funcs
((smu)->funcs->check_pptable ? (smu)->funcs->check_pptable((smu)) : 0)
#define smu_parse_pptable(smu) \
((smu)->funcs->parse_pptable ? (smu)->funcs->parse_pptable((smu)) : 0)
-#define smu_populate_smc_pptable(smu) \
- ((smu)->funcs->populate_smc_pptable ? (smu)->funcs->populate_smc_pptable((smu)) : 0)
+#define smu_populate_smc_tables(smu) \
+ ((smu)->funcs->populate_smc_tables ? (smu)->funcs->populate_smc_tables((smu)) : 0)
#define smu_check_fw_version(smu) \
((smu)->funcs->check_fw_version ? (smu)->funcs->check_fw_version((smu)) : 0)
#define smu_write_pptable(smu) \
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index c8e0d79de43e..de43159564a5 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -140,6 +140,8 @@ static int renoir_get_smu_table_index(struct smu_context *smc, uint32_t index)
static int renoir_tables_init(struct smu_context *smu, struct smu_table *tables)
{
+ struct smu_table_context *smu_table = &smu->smu_table;
+
SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),
@@ -147,6 +149,10 @@ static int renoir_tables_init(struct smu_context *smu, struct smu_table *tables)
SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
+ smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL);
+ if (!smu_table->clocks_table)
+ return -ENOMEM;
+
return 0;
}
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index f8a49626d4eb..b14fe58ab28c 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1732,7 +1732,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
.notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
.check_pptable = smu_v11_0_check_pptable,
.parse_pptable = smu_v11_0_parse_pptable,
- .populate_smc_pptable = smu_v11_0_populate_smc_pptable,
+ .populate_smc_tables = smu_v11_0_populate_smc_pptable,
.write_pptable = smu_v11_0_write_pptable,
.write_watermarks_table = smu_v11_0_write_watermarks_table,
.set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
index 76a6c4b7b63c..0f5d08ae71ae 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
@@ -295,11 +295,30 @@ static int smu_v12_0_fini_smc_tables(struct smu_context *smu)
if (!smu_table->tables || smu_table->table_count == 0)
return -EINVAL;
+ kfree(smu_table->clocks_table);
kfree(smu_table->tables);
+
+ smu_table->clocks_table = NULL;
smu_table->tables = NULL;
return 0;
}
+
+static int smu_v12_0_populate_smc_tables(struct smu_context *smu)
+{
+ struct smu_table_context *smu_table = &smu->smu_table;
+ struct smu_table *table = NULL;
+
+ table = &smu_table->tables[SMU_TABLE_DPMCLOCKS];
+ if (!table)
+ return -EINVAL;
+
+ if (!table->cpu_addr)
+ return -EINVAL;
+
+ return smu_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
+}
+
static const struct smu_funcs smu_v12_0_funcs = {
.check_fw_status = smu_v12_0_check_fw_status,
.check_fw_version = smu_v12_0_check_fw_version,
@@ -312,6 +331,7 @@ static const struct smu_funcs smu_v12_0_funcs = {
.gfx_off_control = smu_v12_0_gfx_off_control,
.init_smc_tables = smu_v12_0_init_smc_tables,
.fini_smc_tables = smu_v12_0_fini_smc_tables,
+ .populate_smc_tables = smu_v12_0_populate_smc_tables,
};
void smu_v12_0_set_smu_funcs(struct smu_context *smu)
--
2.20.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 18/37] drm/amdgpu: disable gfxoff for the moment on renoir
[not found] ` <20190821222359.13578-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (16 preceding siblings ...)
2019-08-21 22:23 ` [PATCH 17/37] drm/amd/powerplay: add DPMCLOCKS table implementation Alex Deucher
@ 2019-08-21 22:23 ` Alex Deucher
2019-08-21 22:23 ` [PATCH 19/37] drm/amdgpu: enable gfx clock gating for rn Alex Deucher
` (18 subsequent siblings)
36 siblings, 0 replies; 39+ messages in thread
From: Alex Deucher @ 2019-08-21 22:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alex Deucher, Huang Rui, Aaron Liu
From: Huang Rui <ray.huang@amd.com>
We still encouter the CP hang while gfxoff is enabled under X start.
So disable it for the moment till this issue is addressed.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 02b3e7dcb637..e265c23ed0a7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1621,7 +1621,7 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
}
adev->pm.pp_feature = amdgpu_pp_feature_mask;
- if (amdgpu_sriov_vf(adev))
+ if (amdgpu_sriov_vf(adev) || adev->asic_type == CHIP_RENOIR)
adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
for (i = 0; i < adev->num_ip_blocks; i++) {
--
2.20.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 19/37] drm/amdgpu: enable gfx clock gating for rn
[not found] ` <20190821222359.13578-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (17 preceding siblings ...)
2019-08-21 22:23 ` [PATCH 18/37] drm/amdgpu: disable gfxoff for the moment on renoir Alex Deucher
@ 2019-08-21 22:23 ` Alex Deucher
2019-08-21 22:23 ` [PATCH 20/37] drm/amdgpu: enable mmhub " Alex Deucher
` (17 subsequent siblings)
36 siblings, 0 replies; 39+ messages in thread
From: Alex Deucher @ 2019-08-21 22:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Prike Liang
From: Prike Liang <Prike.Liang@amd.com>
Enable gfx cg/mg/cp etc clock gating.
Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index c092be45f5e2..d4cb7a66024e 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -1154,7 +1154,13 @@ static int soc15_common_early_init(void *handle)
break;
case CHIP_RENOIR:
adev->asic_funcs = &soc15_asic_funcs;
- adev->cg_flags = 0;
+ adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
+ AMD_CG_SUPPORT_GFX_MGLS |
+ AMD_CG_SUPPORT_GFX_3D_CGCG |
+ AMD_CG_SUPPORT_GFX_3D_CGLS |
+ AMD_CG_SUPPORT_GFX_CGCG |
+ AMD_CG_SUPPORT_GFX_CGLS |
+ AMD_CG_SUPPORT_GFX_CP_LS;
adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x91;
--
2.20.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 20/37] drm/amdgpu: enable mmhub clock gating for rn
[not found] ` <20190821222359.13578-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (18 preceding siblings ...)
2019-08-21 22:23 ` [PATCH 19/37] drm/amdgpu: enable gfx clock gating for rn Alex Deucher
@ 2019-08-21 22:23 ` Alex Deucher
2019-08-21 22:23 ` [PATCH 21/37] drm/amdgpu: enable sdma " Alex Deucher
` (16 subsequent siblings)
36 siblings, 0 replies; 39+ messages in thread
From: Alex Deucher @ 2019-08-21 22:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Prike Liang
From: Prike Liang <Prike.Liang@amd.com>
Enable mmhub midle grain and light sleep clock gating.
Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index d4cb7a66024e..7a7100a5dc1a 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -1160,7 +1160,9 @@ static int soc15_common_early_init(void *handle)
AMD_CG_SUPPORT_GFX_3D_CGLS |
AMD_CG_SUPPORT_GFX_CGCG |
AMD_CG_SUPPORT_GFX_CGLS |
- AMD_CG_SUPPORT_GFX_CP_LS;
+ AMD_CG_SUPPORT_GFX_CP_LS |
+ AMD_CG_SUPPORT_MC_MGCG |
+ AMD_CG_SUPPORT_MC_LS;
adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x91;
--
2.20.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 21/37] drm/amdgpu: enable sdma clock gating for rn
[not found] ` <20190821222359.13578-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (19 preceding siblings ...)
2019-08-21 22:23 ` [PATCH 20/37] drm/amdgpu: enable mmhub " Alex Deucher
@ 2019-08-21 22:23 ` Alex Deucher
2019-08-21 22:23 ` [PATCH 22/37] drm/amdgpu: enable BIF " Alex Deucher
` (15 subsequent siblings)
36 siblings, 0 replies; 39+ messages in thread
From: Alex Deucher @ 2019-08-21 22:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Prike Liang
From: Prike Liang <Prike.Liang@amd.com>
Enable sdma middle grain and light sleep clock gating.
Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 7a7100a5dc1a..6751c5f57913 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -1162,7 +1162,9 @@ static int soc15_common_early_init(void *handle)
AMD_CG_SUPPORT_GFX_CGLS |
AMD_CG_SUPPORT_GFX_CP_LS |
AMD_CG_SUPPORT_MC_MGCG |
- AMD_CG_SUPPORT_MC_LS;
+ AMD_CG_SUPPORT_MC_LS |
+ AMD_CG_SUPPORT_SDMA_MGCG |
+ AMD_CG_SUPPORT_SDMA_LS;
adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x91;
--
2.20.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 22/37] drm/amdgpu: enable BIF clock gating for rn
[not found] ` <20190821222359.13578-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (20 preceding siblings ...)
2019-08-21 22:23 ` [PATCH 21/37] drm/amdgpu: enable sdma " Alex Deucher
@ 2019-08-21 22:23 ` Alex Deucher
2019-08-21 22:23 ` [PATCH 23/37] drm/amdgpu: enable HDP " Alex Deucher
` (14 subsequent siblings)
36 siblings, 0 replies; 39+ messages in thread
From: Alex Deucher @ 2019-08-21 22:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Prike Liang
From: Prike Liang <Prike.Liang@amd.com>
Enable BIF light sleep clock gating.
Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 6751c5f57913..25f55c793feb 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -1164,7 +1164,8 @@ static int soc15_common_early_init(void *handle)
AMD_CG_SUPPORT_MC_MGCG |
AMD_CG_SUPPORT_MC_LS |
AMD_CG_SUPPORT_SDMA_MGCG |
- AMD_CG_SUPPORT_SDMA_LS;
+ AMD_CG_SUPPORT_SDMA_LS |
+ AMD_CG_SUPPORT_BIF_LS;
adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x91;
--
2.20.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 23/37] drm/amdgpu: enable HDP clock gating for rn
[not found] ` <20190821222359.13578-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (21 preceding siblings ...)
2019-08-21 22:23 ` [PATCH 22/37] drm/amdgpu: enable BIF " Alex Deucher
@ 2019-08-21 22:23 ` Alex Deucher
2019-08-21 22:23 ` [PATCH 24/37] drm/amdgpu: enable rom " Alex Deucher
` (13 subsequent siblings)
36 siblings, 0 replies; 39+ messages in thread
From: Alex Deucher @ 2019-08-21 22:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Prike Liang
From: Prike Liang <Prike.Liang@amd.com>
Enable HDP light sleep clock gating.
Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 25f55c793feb..ce101bcbe02c 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -1165,7 +1165,8 @@ static int soc15_common_early_init(void *handle)
AMD_CG_SUPPORT_MC_LS |
AMD_CG_SUPPORT_SDMA_MGCG |
AMD_CG_SUPPORT_SDMA_LS |
- AMD_CG_SUPPORT_BIF_LS;
+ AMD_CG_SUPPORT_BIF_LS |
+ AMD_CG_SUPPORT_HDP_LS;
adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x91;
--
2.20.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 24/37] drm/amdgpu: enable rom clock gating for rn
[not found] ` <20190821222359.13578-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (22 preceding siblings ...)
2019-08-21 22:23 ` [PATCH 23/37] drm/amdgpu: enable HDP " Alex Deucher
@ 2019-08-21 22:23 ` Alex Deucher
2019-08-21 22:23 ` [PATCH 25/37] drm/amdgpu: enable vcn " Alex Deucher
` (12 subsequent siblings)
36 siblings, 0 replies; 39+ messages in thread
From: Alex Deucher @ 2019-08-21 22:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Prike Liang
From: Prike Liang <Prike.Liang@amd.com>
Enable rom light sleep clock gating.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index ce101bcbe02c..20d3120c6bc2 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -1166,7 +1166,8 @@ static int soc15_common_early_init(void *handle)
AMD_CG_SUPPORT_SDMA_MGCG |
AMD_CG_SUPPORT_SDMA_LS |
AMD_CG_SUPPORT_BIF_LS |
- AMD_CG_SUPPORT_HDP_LS;
+ AMD_CG_SUPPORT_HDP_LS |
+ AMD_CG_SUPPORT_ROM_MGCG;
adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x91;
--
2.20.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 25/37] drm/amdgpu: enable vcn clock gating for rn
[not found] ` <20190821222359.13578-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (23 preceding siblings ...)
2019-08-21 22:23 ` [PATCH 24/37] drm/amdgpu: enable rom " Alex Deucher
@ 2019-08-21 22:23 ` Alex Deucher
2019-08-21 22:23 ` [PATCH 26/37] drm/amdgpu: enable IH " Alex Deucher
` (11 subsequent siblings)
36 siblings, 0 replies; 39+ messages in thread
From: Alex Deucher @ 2019-08-21 22:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Prike Liang
From: Prike Liang <Prike.Liang@amd.com>
Enable VCN middle grain clock gating.
Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 20d3120c6bc2..3b92da4ff69c 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -1167,7 +1167,8 @@ static int soc15_common_early_init(void *handle)
AMD_CG_SUPPORT_SDMA_LS |
AMD_CG_SUPPORT_BIF_LS |
AMD_CG_SUPPORT_HDP_LS |
- AMD_CG_SUPPORT_ROM_MGCG;
+ AMD_CG_SUPPORT_ROM_MGCG |
+ AMD_CG_SUPPORT_VCN_MGCG;
adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x91;
--
2.20.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 26/37] drm/amdgpu: enable IH clock gating for rn
[not found] ` <20190821222359.13578-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (24 preceding siblings ...)
2019-08-21 22:23 ` [PATCH 25/37] drm/amdgpu: enable vcn " Alex Deucher
@ 2019-08-21 22:23 ` Alex Deucher
2019-08-21 22:23 ` [PATCH 27/37] drm/amdgpu: enable athub " Alex Deucher
` (10 subsequent siblings)
36 siblings, 0 replies; 39+ messages in thread
From: Alex Deucher @ 2019-08-21 22:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Prike Liang
From: Prike Liang <Prike.Liang@amd.com>
Enable IH clock gating during IH block initialized.
Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 3b92da4ff69c..81dd1ac6086d 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -1168,7 +1168,8 @@ static int soc15_common_early_init(void *handle)
AMD_CG_SUPPORT_BIF_LS |
AMD_CG_SUPPORT_HDP_LS |
AMD_CG_SUPPORT_ROM_MGCG |
- AMD_CG_SUPPORT_VCN_MGCG;
+ AMD_CG_SUPPORT_VCN_MGCG |
+ AMD_CG_SUPPORT_IH_CG;
adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x91;
--
2.20.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 27/37] drm/amdgpu: enable athub clock gating for rn
[not found] ` <20190821222359.13578-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (25 preceding siblings ...)
2019-08-21 22:23 ` [PATCH 26/37] drm/amdgpu: enable IH " Alex Deucher
@ 2019-08-21 22:23 ` Alex Deucher
2019-08-21 22:23 ` [PATCH 28/37] drm/amdgpu: enable DF " Alex Deucher
` (9 subsequent siblings)
36 siblings, 0 replies; 39+ messages in thread
From: Alex Deucher @ 2019-08-21 22:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Prike Liang
From: Prike Liang <Prike.Liang@amd.com>
Enable athub MG and LS clock gating.
Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 81dd1ac6086d..0552942ee732 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -1169,7 +1169,9 @@ static int soc15_common_early_init(void *handle)
AMD_CG_SUPPORT_HDP_LS |
AMD_CG_SUPPORT_ROM_MGCG |
AMD_CG_SUPPORT_VCN_MGCG |
- AMD_CG_SUPPORT_IH_CG;
+ AMD_CG_SUPPORT_IH_CG |
+ AMD_CG_SUPPORT_ATHUB_LS |
+ AMD_CG_SUPPORT_ATHUB_MGCG;
adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x91;
--
2.20.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 28/37] drm/amdgpu: enable DF clock gating for rn
[not found] ` <20190821222359.13578-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (26 preceding siblings ...)
2019-08-21 22:23 ` [PATCH 27/37] drm/amdgpu: enable athub " Alex Deucher
@ 2019-08-21 22:23 ` Alex Deucher
2019-08-21 22:23 ` [PATCH 29/37] drm/amdgpu/mmhub1: set mmhub " Alex Deucher
` (8 subsequent siblings)
36 siblings, 0 replies; 39+ messages in thread
From: Alex Deucher @ 2019-08-21 22:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Prike Liang
From: Prike Liang <Prike.Liang@amd.com>
Enable DF clock gating during DF IP early init.
Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 0552942ee732..6ab444d6be72 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -1171,7 +1171,8 @@ static int soc15_common_early_init(void *handle)
AMD_CG_SUPPORT_VCN_MGCG |
AMD_CG_SUPPORT_IH_CG |
AMD_CG_SUPPORT_ATHUB_LS |
- AMD_CG_SUPPORT_ATHUB_MGCG;
+ AMD_CG_SUPPORT_ATHUB_MGCG |
+ AMD_CG_SUPPORT_DF_MGCG;
adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x91;
--
2.20.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 29/37] drm/amdgpu/mmhub1: set mmhub clock gating for rn
[not found] ` <20190821222359.13578-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (27 preceding siblings ...)
2019-08-21 22:23 ` [PATCH 28/37] drm/amdgpu: enable DF " Alex Deucher
@ 2019-08-21 22:23 ` Alex Deucher
2019-08-21 22:23 ` [PATCH 30/37] drm/amdgpu/sdma4: set sdma " Alex Deucher
` (7 subsequent siblings)
36 siblings, 0 replies; 39+ messages in thread
From: Alex Deucher @ 2019-08-21 22:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Prike Liang
From: Prike Liang <Prike.Liang@amd.com>
Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index 2bd7ada80088..04cd4b6f95d4 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -521,6 +521,7 @@ int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev,
case CHIP_VEGA12:
case CHIP_VEGA20:
case CHIP_RAVEN:
+ case CHIP_RENOIR:
mmhub_v1_0_update_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE ? true : false);
mmhub_v1_0_update_medium_grain_light_sleep(adev,
--
2.20.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 30/37] drm/amdgpu/sdma4: set sdma clock gating for rn
[not found] ` <20190821222359.13578-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (28 preceding siblings ...)
2019-08-21 22:23 ` [PATCH 29/37] drm/amdgpu/mmhub1: set mmhub " Alex Deucher
@ 2019-08-21 22:23 ` Alex Deucher
2019-08-21 22:23 ` [PATCH 31/37] drm/amdgpu: enable SDMA power " Alex Deucher
` (6 subsequent siblings)
36 siblings, 0 replies; 39+ messages in thread
From: Alex Deucher @ 2019-08-21 22:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Prike Liang
From: Prike Liang <Prike.Liang@amd.com>
Add support for SDMA clockgating on RN.
Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 071d6c9a254e..9fab7fd982b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -2178,6 +2178,7 @@ static int sdma_v4_0_set_clockgating_state(void *handle,
case CHIP_VEGA20:
case CHIP_RAVEN:
case CHIP_ARCTURUS:
+ case CHIP_RENOIR:
sdma_v4_0_update_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE ? true : false);
sdma_v4_0_update_medium_grain_light_sleep(adev,
--
2.20.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 31/37] drm/amdgpu: enable SDMA power gating for rn
[not found] ` <20190821222359.13578-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (29 preceding siblings ...)
2019-08-21 22:23 ` [PATCH 30/37] drm/amdgpu/sdma4: set sdma " Alex Deucher
@ 2019-08-21 22:23 ` Alex Deucher
2019-08-21 22:23 ` [PATCH 32/37] drm/amd/powerplay: enable renoir dpm feature Alex Deucher
` (5 subsequent siblings)
36 siblings, 0 replies; 39+ messages in thread
From: Alex Deucher @ 2019-08-21 22:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Prike Liang
From: Prike Liang <Prike.Liang@amd.com>
Enable SDMA PG flag during device ip early init.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 6ab444d6be72..5c211fa03328 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -1173,7 +1173,7 @@ static int soc15_common_early_init(void *handle)
AMD_CG_SUPPORT_ATHUB_LS |
AMD_CG_SUPPORT_ATHUB_MGCG |
AMD_CG_SUPPORT_DF_MGCG;
- adev->pg_flags = 0;
+ adev->pg_flags = AMD_PG_SUPPORT_SDMA;
adev->external_rev_id = adev->rev_id + 0x91;
if (adev->pm.pp_feature & PP_GFXOFF_MASK)
--
2.20.1
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 32/37] drm/amd/powerplay: enable renoir dpm feature
[not found] ` <20190821222359.13578-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (30 preceding siblings ...)
2019-08-21 22:23 ` [PATCH 31/37] drm/amdgpu: enable SDMA power " Alex Deucher
@ 2019-08-21 22:23 ` Alex Deucher
2019-08-21 22:23 ` [PATCH 33/37] drm/amd/powerplay: Disable renoir smu feature retrive for the moment Alex Deucher
` (4 subsequent siblings)
36 siblings, 0 replies; 39+ messages in thread
From: Alex Deucher @ 2019-08-21 22:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alex Deucher, Prike Liang, Aaron Liu
From: Prike Liang <Prike.Liang@amd.com>
enable the dpm feature for the renoir.
Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 8 --------
1 file changed, 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index ebfd631521c8..808c8e02a650 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -768,10 +768,6 @@ static int smu_late_init(void *handle)
if (!smu->pm_enabled)
return 0;
- /* To be removed after dpm is enabled */
- if (adev->asic_type == CHIP_RENOIR)
- return 0;
-
mutex_lock(&smu->mutex);
smu_handle_task(&adev->smu,
smu->smu_dpm.dpm_level,
@@ -1275,10 +1271,6 @@ static int smu_hw_init(void *handle)
if (!smu->pm_enabled)
return 0;
- /* To be removed after dpm is enabled */
- if (adev->asic_type == CHIP_RENOIR)
- return 0;
-
ret = smu_feature_init_dpm(smu);
if (ret)
goto failed;
--
2.20.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 33/37] drm/amd/powerplay: Disable renoir smu feature retrive for the moment
[not found] ` <20190821222359.13578-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (31 preceding siblings ...)
2019-08-21 22:23 ` [PATCH 32/37] drm/amd/powerplay: enable renoir dpm feature Alex Deucher
@ 2019-08-21 22:23 ` Alex Deucher
2019-08-21 22:23 ` [PATCH 34/37] drm/amdgpu: update gc/sdma goldensetting for rn Alex Deucher
` (3 subsequent siblings)
36 siblings, 0 replies; 39+ messages in thread
From: Alex Deucher @ 2019-08-21 22:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alex Deucher, Prike Liang, Kevin Wang
From: Prike Liang <Prike.Liang@amd.com>
To avoid the dpm frequence range get failed when DPM enabled and it
will be enabled later once handle well the feature bit map struct.
Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 808c8e02a650..6f435d60fe86 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -630,10 +630,14 @@ int smu_feature_update_enable_state(struct smu_context *smu, uint64_t feature_ma
int smu_feature_is_enabled(struct smu_context *smu, enum smu_feature_mask mask)
{
+ struct amdgpu_device *adev = smu->adev;
struct smu_feature *feature = &smu->smu_feature;
int feature_id;
int ret = 0;
+ if (adev->flags & AMD_IS_APU)
+ return 0;
+
feature_id = smu_feature_get_index(smu, mask);
if (feature_id < 0)
return 0;
--
2.20.1
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 34/37] drm/amdgpu: update gc/sdma goldensetting for rn
[not found] ` <20190821222359.13578-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (32 preceding siblings ...)
2019-08-21 22:23 ` [PATCH 33/37] drm/amd/powerplay: Disable renoir smu feature retrive for the moment Alex Deucher
@ 2019-08-21 22:23 ` Alex Deucher
2019-08-21 22:23 ` [PATCH 35/37] Revert "drm/amdgpu: disable gfxoff for the moment on renoir" Alex Deucher
` (2 subsequent siblings)
36 siblings, 0 replies; 39+ messages in thread
From: Alex Deucher @ 2019-08-21 22:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alex Deucher, Huang Rui, Aaron Liu
From: Aaron Liu <aaron.liu@amd.com>
This patch updates gc/sdma goldensetting for renoir
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 7 +++----
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++--
2 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 48f8d5ae67f3..2c7025bb1050 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -620,12 +620,11 @@ static const struct soc15_reg_golden golden_settings_gc_9_1_rv2[] =
static const struct soc15_reg_golden golden_settings_gc_9_1_rn[] =
{
- SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x3f8fffff, 0x08000080),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400),
- SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x22010042),
- SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x22010042),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x24000042),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x24000042),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
@@ -783,7 +782,7 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
soc15_program_register_sequence(adev,
golden_settings_gc_9_1_rn,
ARRAY_SIZE(golden_settings_gc_9_1_rn));
- break;
+ return; /* for renoir, don't need common goldensetting */
default:
break;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 9fab7fd982b6..b3b2c2191602 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -244,8 +244,8 @@ static const struct soc15_reg_golden golden_settings_sdma_arct[] =
static const struct soc15_reg_golden golden_settings_sdma_4_3[] = {
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
- SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00003002),
- SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003002),
+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002),
+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003fff07, 0x40000051),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
--
2.20.1
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 35/37] Revert "drm/amdgpu: disable gfxoff for the moment on renoir"
[not found] ` <20190821222359.13578-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (33 preceding siblings ...)
2019-08-21 22:23 ` [PATCH 34/37] drm/amdgpu: update gc/sdma goldensetting for rn Alex Deucher
@ 2019-08-21 22:23 ` Alex Deucher
2019-08-21 22:23 ` [PATCH 36/37] Revert "drm/amdgpu: use direct loading on renoir vcn for the moment" Alex Deucher
2019-08-21 22:23 ` [PATCH 37/37] drm/amdgpu: enable VCN DPG for Renoir Alex Deucher
36 siblings, 0 replies; 39+ messages in thread
From: Alex Deucher @ 2019-08-21 22:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alex Deucher, Aaron Liu, changzhu, Chen Gong
From: Aaron Liu <aaron.liu@amd.com>
This reverts commit dfb2c6ee8bec5914d47a4b75f73eff731bb937ae.
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Acked-by: changzhu <Changfeng.Zhu@amd.com>
Acked-by: Chen Gong <curry.gong@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index e265c23ed0a7..02b3e7dcb637 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1621,7 +1621,7 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
}
adev->pm.pp_feature = amdgpu_pp_feature_mask;
- if (amdgpu_sriov_vf(adev) || adev->asic_type == CHIP_RENOIR)
+ if (amdgpu_sriov_vf(adev))
adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
for (i = 0; i < adev->num_ip_blocks; i++) {
--
2.20.1
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 36/37] Revert "drm/amdgpu: use direct loading on renoir vcn for the moment"
[not found] ` <20190821222359.13578-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (34 preceding siblings ...)
2019-08-21 22:23 ` [PATCH 35/37] Revert "drm/amdgpu: disable gfxoff for the moment on renoir" Alex Deucher
@ 2019-08-21 22:23 ` Alex Deucher
2019-08-21 22:23 ` [PATCH 37/37] drm/amdgpu: enable VCN DPG for Renoir Alex Deucher
36 siblings, 0 replies; 39+ messages in thread
From: Alex Deucher @ 2019-08-21 22:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alex Deucher, Leo Liu, Thong Thai
From: Thong Thai <thong.thai@amd.com>
This reverts commit 444a0fea5107e9ad7e3cbbafed78678489e31713.
We are ready to enable it now.
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 9 +++------
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 9 +++------
2 files changed, 6 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index d9c2f42b2dc7..8566a264961f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -99,8 +99,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
case CHIP_NAVI14:
fw_name = FIRMWARE_NAVI14;
if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
- (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) &&
- adev->asic_type != CHIP_RENOIR) /* to be removed while vcn psp loading works */
+ (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
adev->vcn.indirect_sram = true;
break;
case CHIP_NAVI12:
@@ -160,8 +159,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
}
bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE;
- if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP ||
- adev->asic_type == CHIP_RENOIR)
+ if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
@@ -272,8 +270,7 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev)
unsigned offset;
hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
- if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP ||
- adev->asic_type == CHIP_RENOIR) {
+ if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset,
le32_to_cpu(hdr->ucode_size_bytes));
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index e200cbc8139f..7528b1b562e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -142,8 +142,7 @@ static int vcn_v2_0_sw_init(void *handle)
if (r)
return r;
- if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
- adev->asic_type != CHIP_RENOIR) {
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
const struct common_firmware_header *hdr;
hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN;
@@ -367,8 +366,7 @@ static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)
uint32_t offset;
/* cache window 0: fw */
- if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
- adev->asic_type != CHIP_RENOIR) {
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
@@ -413,8 +411,7 @@ static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirec
uint32_t offset;
/* cache window 0: fw */
- if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
- adev->asic_type != CHIP_RENOIR) {
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
if (!indirect) {
WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
--
2.20.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 37/37] drm/amdgpu: enable VCN DPG for Renoir
[not found] ` <20190821222359.13578-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (35 preceding siblings ...)
2019-08-21 22:23 ` [PATCH 36/37] Revert "drm/amdgpu: use direct loading on renoir vcn for the moment" Alex Deucher
@ 2019-08-21 22:23 ` Alex Deucher
[not found] ` <20190821222359.13578-38-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
36 siblings, 1 reply; 39+ messages in thread
From: Alex Deucher @ 2019-08-21 22:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alex Deucher, Leo Liu, Thong Thai
From: Thong Thai <thong.thai@amd.com>
This will enable indirect SRAM loading for VCN DPG mode initialization.
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 5c211fa03328..fe2212df12a3 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -1173,7 +1173,9 @@ static int soc15_common_early_init(void *handle)
AMD_CG_SUPPORT_ATHUB_LS |
AMD_CG_SUPPORT_ATHUB_MGCG |
AMD_CG_SUPPORT_DF_MGCG;
- adev->pg_flags = AMD_PG_SUPPORT_SDMA;
+ adev->pg_flags = AMD_PG_SUPPORT_SDMA |
+ AMD_PG_SUPPORT_VCN |
+ AMD_PG_SUPPORT_VCN_DPG;
adev->external_rev_id = adev->rev_id + 0x91;
if (adev->pm.pp_feature & PP_GFXOFF_MASK)
--
2.20.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 39+ messages in thread
* RE: [PATCH 37/37] drm/amdgpu: enable VCN DPG for Renoir
[not found] ` <20190821222359.13578-38-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
@ 2019-08-22 2:33 ` Liang, Prike
0 siblings, 0 replies; 39+ messages in thread
From: Liang, Prike @ 2019-08-22 2:33 UTC (permalink / raw)
To: Alex Deucher, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Deucher, Alexander, Liu, Leo, Thai, Thong
Reviewed-by: Prike Liang <Prike.Liang@amd.com>
Thanks,
Prike
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Alex
> Deucher
> Sent: Thursday, August 22, 2019 6:24 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Liu, Leo
> <Leo.Liu@amd.com>; Thai, Thong <Thong.Thai@amd.com>
> Subject: [PATCH 37/37] drm/amdgpu: enable VCN DPG for Renoir
>
> From: Thong Thai <thong.thai@amd.com>
>
> This will enable indirect SRAM loading for VCN DPG mode initialization.
>
> Signed-off-by: Thong Thai <thong.thai@amd.com>
> Reviewed-by: Leo Liu <leo.liu@amd.com>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
> b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 5c211fa03328..fe2212df12a3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -1173,7 +1173,9 @@ static int soc15_common_early_init(void *handle)
> AMD_CG_SUPPORT_ATHUB_LS |
> AMD_CG_SUPPORT_ATHUB_MGCG |
> AMD_CG_SUPPORT_DF_MGCG;
> - adev->pg_flags = AMD_PG_SUPPORT_SDMA;
> + adev->pg_flags = AMD_PG_SUPPORT_SDMA |
> + AMD_PG_SUPPORT_VCN |
> + AMD_PG_SUPPORT_VCN_DPG;
> adev->external_rev_id = adev->rev_id + 0x91;
>
> if (adev->pm.pp_feature & PP_GFXOFF_MASK)
> --
> 2.20.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 39+ messages in thread
end of thread, other threads:[~2019-08-22 2:33 UTC | newest]
Thread overview: 39+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-08-21 22:23 [PATCH 00/37] Enable power features for Renoir Alex Deucher
[not found] ` <20190821222359.13578-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
2019-08-21 22:23 ` [PATCH 01/37] drm/amdgpu/powerplay: Add smu_v12_0_ppsmc.h (v2) Alex Deucher
2019-08-21 22:23 ` [PATCH 02/37] drm/amd/powerplay: add smu12_driver_if.h (v3) Alex Deucher
2019-08-21 22:23 ` [PATCH 03/37] drm/amdgpu/powerplay: add initial renoir_ppt.c for renoir (v3) Alex Deucher
2019-08-21 22:23 ` [PATCH 04/37] drm/amdgpu/powerplay: add smu_v12_0.c & smu_v12_0.h for renoir Alex Deucher
2019-08-21 22:23 ` [PATCH 05/37] drm/amdgpu/powerplay: add smu ip block for renoir (v2) Alex Deucher
2019-08-21 22:23 ` [PATCH 06/37] drm/amdgpu/powerplay: add power up/down SDMA interfaces for renoir Alex Deucher
2019-08-21 22:23 ` [PATCH 07/37] drm/amdgpu: skip dpm init " Alex Deucher
2019-08-21 22:23 ` [PATCH 08/37] drm/amdgpu/powerplay: add Renoir VCN power management Alex Deucher
2019-08-21 22:23 ` [PATCH 09/37] drm/amd/powerplay: powerup sdma/vcn for all apu series Alex Deucher
2019-08-21 22:23 ` [PATCH 10/37] drm/amd/powerplay: udpate smu_v12_0_check_fw_version (v2) Alex Deucher
2019-08-21 22:23 ` [PATCH 11/37] drm/amdgpu: add set_gfx_cgpg implement (v2) Alex Deucher
2019-08-21 22:23 ` [PATCH 12/37] drm/amdgpu: add and enable gfxoff feature Alex Deucher
2019-08-21 22:23 ` [PATCH 13/37] drm/amd/powerplay: fix checking gfxoff status for rn Alex Deucher
2019-08-21 22:23 ` [PATCH 14/37] drm/amd/powerplay: using valid mapping check " Alex Deucher
2019-08-21 22:23 ` [PATCH 15/37] drm/amd/powerplay: add smu tables " Alex Deucher
2019-08-21 22:23 ` [PATCH 16/37] drm/amd/powerplay: init " Alex Deucher
2019-08-21 22:23 ` [PATCH 17/37] drm/amd/powerplay: add DPMCLOCKS table implementation Alex Deucher
2019-08-21 22:23 ` [PATCH 18/37] drm/amdgpu: disable gfxoff for the moment on renoir Alex Deucher
2019-08-21 22:23 ` [PATCH 19/37] drm/amdgpu: enable gfx clock gating for rn Alex Deucher
2019-08-21 22:23 ` [PATCH 20/37] drm/amdgpu: enable mmhub " Alex Deucher
2019-08-21 22:23 ` [PATCH 21/37] drm/amdgpu: enable sdma " Alex Deucher
2019-08-21 22:23 ` [PATCH 22/37] drm/amdgpu: enable BIF " Alex Deucher
2019-08-21 22:23 ` [PATCH 23/37] drm/amdgpu: enable HDP " Alex Deucher
2019-08-21 22:23 ` [PATCH 24/37] drm/amdgpu: enable rom " Alex Deucher
2019-08-21 22:23 ` [PATCH 25/37] drm/amdgpu: enable vcn " Alex Deucher
2019-08-21 22:23 ` [PATCH 26/37] drm/amdgpu: enable IH " Alex Deucher
2019-08-21 22:23 ` [PATCH 27/37] drm/amdgpu: enable athub " Alex Deucher
2019-08-21 22:23 ` [PATCH 28/37] drm/amdgpu: enable DF " Alex Deucher
2019-08-21 22:23 ` [PATCH 29/37] drm/amdgpu/mmhub1: set mmhub " Alex Deucher
2019-08-21 22:23 ` [PATCH 30/37] drm/amdgpu/sdma4: set sdma " Alex Deucher
2019-08-21 22:23 ` [PATCH 31/37] drm/amdgpu: enable SDMA power " Alex Deucher
2019-08-21 22:23 ` [PATCH 32/37] drm/amd/powerplay: enable renoir dpm feature Alex Deucher
2019-08-21 22:23 ` [PATCH 33/37] drm/amd/powerplay: Disable renoir smu feature retrive for the moment Alex Deucher
2019-08-21 22:23 ` [PATCH 34/37] drm/amdgpu: update gc/sdma goldensetting for rn Alex Deucher
2019-08-21 22:23 ` [PATCH 35/37] Revert "drm/amdgpu: disable gfxoff for the moment on renoir" Alex Deucher
2019-08-21 22:23 ` [PATCH 36/37] Revert "drm/amdgpu: use direct loading on renoir vcn for the moment" Alex Deucher
2019-08-21 22:23 ` [PATCH 37/37] drm/amdgpu: enable VCN DPG for Renoir Alex Deucher
[not found] ` <20190821222359.13578-38-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
2019-08-22 2:33 ` Liang, Prike
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