* [PATCH] drm/i915/tgl: Enabling DSC on Pipe A for TGL
@ 2019-08-23 0:46 Madhumitha Tolakanahalli Pradeep
2019-08-23 0:59 ` Manasi Navare
` (4 more replies)
0 siblings, 5 replies; 11+ messages in thread
From: Madhumitha Tolakanahalli Pradeep @ 2019-08-23 0:46 UTC (permalink / raw)
To: intel-gfx
DSC was not supported on Pipe A for previous platforms. Tigerlake onwards,
all the pipes support DSC. Hence, the DSC and FEC restriction on
Pipe A needs to be removed.
v2: Changes in the logic around removing the restriction around
Pipe A (Manasi, Lucas)
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 21 +++++++++++++++++----
1 file changed, 17 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 4884c87c8ed7..e2c8fe274c84 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1739,8 +1739,14 @@ static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- return INTEL_GEN(dev_priv) >= 11 &&
- pipe_config->cpu_transcoder != TRANSCODER_A;
+ /* On TGL, FEC is supported on all Pipes */
+ if (INTEL_GEN(dev_priv) >= 12)
+ return true;
+
+ if (IS_GEN(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A)
+ return true;
+
+ return false;
}
static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
@@ -1755,8 +1761,15 @@ static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- return INTEL_GEN(dev_priv) >= 10 &&
- pipe_config->cpu_transcoder != TRANSCODER_A;
+ /* On TGL, DSC is supported on all Pipes */
+ if (INTEL_GEN(dev_priv) >= 12)
+ return true;
+
+ if (INTEL_GEN(dev_priv) >= 10 &&
+ pipe_config->cpu_transcoder != TRANSCODER_A)
+ return true;
+
+ return false;
}
static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH] drm/i915/tgl: Enabling DSC on Pipe A for TGL
2019-08-23 0:46 [PATCH] drm/i915/tgl: Enabling DSC on Pipe A for TGL Madhumitha Tolakanahalli Pradeep
@ 2019-08-23 0:59 ` Manasi Navare
2019-08-23 1:56 ` ✓ Fi.CI.BAT: success for drm/i915/tgl: Enabling DSC on Pipe A for TGL (rev2) Patchwork
` (3 subsequent siblings)
4 siblings, 0 replies; 11+ messages in thread
From: Manasi Navare @ 2019-08-23 0:59 UTC (permalink / raw)
To: Madhumitha Tolakanahalli Pradeep; +Cc: intel-gfx
On Thu, Aug 22, 2019 at 05:46:55PM -0700, Madhumitha Tolakanahalli Pradeep wrote:
> DSC was not supported on Pipe A for previous platforms. Tigerlake onwards,
> all the pipes support DSC. Hence, the DSC and FEC restriction on
> Pipe A needs to be removed.
>
> v2: Changes in the logic around removing the restriction around
> Pipe A (Manasi, Lucas)
>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com>
Looks good to me
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Manasi
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 21 +++++++++++++++++----
> 1 file changed, 17 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 4884c87c8ed7..e2c8fe274c84 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1739,8 +1739,14 @@ static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>
> - return INTEL_GEN(dev_priv) >= 11 &&
> - pipe_config->cpu_transcoder != TRANSCODER_A;
> + /* On TGL, FEC is supported on all Pipes */
> + if (INTEL_GEN(dev_priv) >= 12)
> + return true;
> +
> + if (IS_GEN(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A)
> + return true;
> +
> + return false;
> }
>
> static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
> @@ -1755,8 +1761,15 @@ static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>
> - return INTEL_GEN(dev_priv) >= 10 &&
> - pipe_config->cpu_transcoder != TRANSCODER_A;
> + /* On TGL, DSC is supported on all Pipes */
> + if (INTEL_GEN(dev_priv) >= 12)
> + return true;
> +
> + if (INTEL_GEN(dev_priv) >= 10 &&
> + pipe_config->cpu_transcoder != TRANSCODER_A)
> + return true;
> +
> + return false;
> }
>
> static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
> --
> 2.17.1
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/tgl: Enabling DSC on Pipe A for TGL (rev2)
2019-08-23 0:46 [PATCH] drm/i915/tgl: Enabling DSC on Pipe A for TGL Madhumitha Tolakanahalli Pradeep
2019-08-23 0:59 ` Manasi Navare
@ 2019-08-23 1:56 ` Patchwork
2019-08-23 8:50 ` [PATCH] drm/i915/tgl: Enabling DSC on Pipe A for TGL Lucas De Marchi
` (2 subsequent siblings)
4 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2019-08-23 1:56 UTC (permalink / raw)
To: Madhumitha Tolakanahalli Pradeep; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/tgl: Enabling DSC on Pipe A for TGL (rev2)
URL : https://patchwork.freedesktop.org/series/65216/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6769 -> Patchwork_14150
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14150/
Known issues
------------
Here are the changes found in Patchwork_14150 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live_requests:
- fi-byt-j1900: [PASS][1] -> [INCOMPLETE][2] ([fdo#102657])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6769/fi-byt-j1900/igt@i915_selftest@live_requests.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14150/fi-byt-j1900/igt@i915_selftest@live_requests.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u3: [PASS][3] -> [FAIL][4] ([fdo#103167])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6769/fi-icl-u3/igt@kms_frontbuffer_tracking@basic.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14150/fi-icl-u3/igt@kms_frontbuffer_tracking@basic.html
* igt@prime_vgem@basic-fence-flip:
- fi-ilk-650: [PASS][5] -> [DMESG-WARN][6] ([fdo#106387]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6769/fi-ilk-650/igt@prime_vgem@basic-fence-flip.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14150/fi-ilk-650/igt@prime_vgem@basic-fence-flip.html
#### Possible fixes ####
* igt@i915_selftest@live_reset:
- {fi-icl-dsi}: [INCOMPLETE][7] ([fdo#107713]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6769/fi-icl-dsi/igt@i915_selftest@live_reset.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14150/fi-icl-dsi/igt@i915_selftest@live_reset.html
* igt@kms_frontbuffer_tracking@basic:
- {fi-icl-u4}: [FAIL][9] ([fdo#103167]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6769/fi-icl-u4/igt@kms_frontbuffer_tracking@basic.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14150/fi-icl-u4/igt@kms_frontbuffer_tracking@basic.html
- fi-icl-u2: [FAIL][11] ([fdo#103167]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6769/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14150/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
#### Warnings ####
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7567u: [FAIL][13] ([fdo#111407]) -> [FAIL][14] ([fdo#109800] / [fdo#111096])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6769/fi-kbl-7567u/igt@kms_chamelium@hdmi-hpd-fast.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14150/fi-kbl-7567u/igt@kms_chamelium@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102657]: https://bugs.freedesktop.org/show_bug.cgi?id=102657
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#106387]: https://bugs.freedesktop.org/show_bug.cgi?id=106387
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#109800]: https://bugs.freedesktop.org/show_bug.cgi?id=109800
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
Participating hosts (55 -> 48)
------------------------------
Additional (1): fi-bsw-n3050
Missing (8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6769 -> Patchwork_14150
CI-20190529: 20190529
CI_DRM_6769: 66b20c063386eb45b5617fce6c2dca606d56a09f @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5148: 50390dd7adaccae21cafa85b866c17606cec94c3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14150: 22ec3f0c0004cb5322e6281a572616d8c9455e56 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
22ec3f0c0004 drm/i915/tgl: Enabling DSC on Pipe A for TGL
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14150/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] drm/i915/tgl: Enabling DSC on Pipe A for TGL
2019-08-23 0:46 [PATCH] drm/i915/tgl: Enabling DSC on Pipe A for TGL Madhumitha Tolakanahalli Pradeep
2019-08-23 0:59 ` Manasi Navare
2019-08-23 1:56 ` ✓ Fi.CI.BAT: success for drm/i915/tgl: Enabling DSC on Pipe A for TGL (rev2) Patchwork
@ 2019-08-23 8:50 ` Lucas De Marchi
2019-08-23 19:59 ` ✗ Fi.CI.IGT: failure for drm/i915/tgl: Enabling DSC on Pipe A for TGL (rev2) Patchwork
2019-08-28 20:12 ` [PATCH] drm/i915/tgl: Enabling DSC on Pipe A for TGL Manasi Navare
4 siblings, 0 replies; 11+ messages in thread
From: Lucas De Marchi @ 2019-08-23 8:50 UTC (permalink / raw)
To: Madhumitha Tolakanahalli Pradeep; +Cc: Intel Graphics
On Thu, Aug 22, 2019 at 5:46 PM Madhumitha Tolakanahalli Pradeep
<madhumitha.tolakanahalli.pradeep@intel.com> wrote:
>
> DSC was not supported on Pipe A for previous platforms. Tigerlake onwards,
> all the pipes support DSC. Hence, the DSC and FEC restriction on
> Pipe A needs to be removed.
>
> v2: Changes in the logic around removing the restriction around
> Pipe A (Manasi, Lucas)
>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 21 +++++++++++++++++----
> 1 file changed, 17 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 4884c87c8ed7..e2c8fe274c84 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1739,8 +1739,14 @@ static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>
> - return INTEL_GEN(dev_priv) >= 11 &&
> - pipe_config->cpu_transcoder != TRANSCODER_A;
> + /* On TGL, FEC is supported on all Pipes */
> + if (INTEL_GEN(dev_priv) >= 12)
> + return true;
> +
> + if (IS_GEN(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A)
> + return true;
> +
> + return false;
> }
>
> static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
> @@ -1755,8 +1761,15 @@ static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>
> - return INTEL_GEN(dev_priv) >= 10 &&
> - pipe_config->cpu_transcoder != TRANSCODER_A;
> + /* On TGL, DSC is supported on all Pipes */
> + if (INTEL_GEN(dev_priv) >= 12)
> + return true;
> +
> + if (INTEL_GEN(dev_priv) >= 10 &&
> + pipe_config->cpu_transcoder != TRANSCODER_A)
> + return true;
> +
> + return false;
> }
>
> static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
> --
> 2.17.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Lucas De Marchi
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* ✗ Fi.CI.IGT: failure for drm/i915/tgl: Enabling DSC on Pipe A for TGL (rev2)
2019-08-23 0:46 [PATCH] drm/i915/tgl: Enabling DSC on Pipe A for TGL Madhumitha Tolakanahalli Pradeep
` (2 preceding siblings ...)
2019-08-23 8:50 ` [PATCH] drm/i915/tgl: Enabling DSC on Pipe A for TGL Lucas De Marchi
@ 2019-08-23 19:59 ` Patchwork
2019-08-28 20:12 ` [PATCH] drm/i915/tgl: Enabling DSC on Pipe A for TGL Manasi Navare
4 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2019-08-23 19:59 UTC (permalink / raw)
To: Madhumitha Tolakanahalli Pradeep; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/tgl: Enabling DSC on Pipe A for TGL (rev2)
URL : https://patchwork.freedesktop.org/series/65216/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6769_full -> Patchwork_14150_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_14150_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14150_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_14150_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_parallel@rcs0-contexts:
- shard-hsw: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6769/shard-hsw6/igt@gem_exec_parallel@rcs0-contexts.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14150/shard-hsw6/igt@gem_exec_parallel@rcs0-contexts.html
Known issues
------------
Here are the changes found in Patchwork_14150_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_schedule@deep-blt:
- shard-apl: [PASS][3] -> [INCOMPLETE][4] ([fdo#103927])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6769/shard-apl3/igt@gem_exec_schedule@deep-blt.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14150/shard-apl7/igt@gem_exec_schedule@deep-blt.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#111325]) +2 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6769/shard-iclb8/igt@gem_exec_schedule@preemptive-hang-bsd.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14150/shard-iclb2/igt@gem_exec_schedule@preemptive-hang-bsd.html
* igt@kms_cursor_crc@pipe-b-cursor-256x256-onscreen:
- shard-skl: [PASS][7] -> [FAIL][8] ([fdo#103232])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6769/shard-skl7/igt@kms_cursor_crc@pipe-b-cursor-256x256-onscreen.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14150/shard-skl2/igt@kms_cursor_crc@pipe-b-cursor-256x256-onscreen.html
* igt@kms_flip@2x-dpms-vs-vblank-race:
- shard-glk: [PASS][9] -> [FAIL][10] ([fdo#103060]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6769/shard-glk8/igt@kms_flip@2x-dpms-vs-vblank-race.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14150/shard-glk4/igt@kms_flip@2x-dpms-vs-vblank-race.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-glk: [PASS][11] -> [FAIL][12] ([fdo#105363])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6769/shard-glk3/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14150/shard-glk1/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: [PASS][13] -> [FAIL][14] ([fdo#105363])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6769/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14150/shard-skl2/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-suspend:
- shard-snb: [PASS][15] -> [INCOMPLETE][16] ([fdo#105411])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6769/shard-snb6/igt@kms_flip@flip-vs-suspend.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14150/shard-snb1/igt@kms_flip@flip-vs-suspend.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-hsw: [PASS][17] -> [INCOMPLETE][18] ([fdo#103540])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6769/shard-hsw2/igt@kms_flip@flip-vs-suspend-interruptible.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14150/shard-hsw5/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt:
- shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103167]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6769/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14150/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145] / [fdo#110403])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6769/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14150/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441]) +2 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6769/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14150/shard-iclb8/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][25] -> [FAIL][26] ([fdo#99912])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6769/shard-apl1/igt@kms_setmode@basic.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14150/shard-apl6/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: [PASS][27] -> [DMESG-WARN][28] ([fdo#108566]) +4 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6769/shard-apl5/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14150/shard-apl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@prime_busy@hang-bsd2:
- shard-iclb: [PASS][29] -> [SKIP][30] ([fdo#109276]) +16 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6769/shard-iclb2/igt@prime_busy@hang-bsd2.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14150/shard-iclb8/igt@prime_busy@hang-bsd2.html
#### Possible fixes ####
* igt@gem_exec_schedule@preempt-contexts-bsd2:
- shard-iclb: [SKIP][31] ([fdo#109276]) -> [PASS][32] +21 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6769/shard-iclb3/igt@gem_exec_schedule@preempt-contexts-bsd2.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14150/shard-iclb4/igt@gem_exec_schedule@preempt-contexts-bsd2.html
* igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd:
- shard-iclb: [SKIP][33] ([fdo#111325]) -> [PASS][34] +3 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6769/shard-iclb2/igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14150/shard-iclb3/igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl: [INCOMPLETE][35] ([fdo#103927]) -> [PASS][36] +1 similar issue
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6769/shard-apl4/igt@i915_suspend@fence-restore-tiled2untiled.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14150/shard-apl2/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: [DMESG-WARN][37] ([fdo#108566]) -> [PASS][38] +5 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6769/shard-apl1/igt@i915_suspend@sysfs-reader.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14150/shard-apl6/igt@i915_suspend@sysfs-reader.html
* igt@kms_busy@extended-modeset-hang-oldfb-render-a:
- shard-iclb: [INCOMPLETE][39] ([fdo#107713]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6769/shard-iclb7/igt@kms_busy@extended-modeset-hang-oldfb-render-a.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14150/shard-iclb8/igt@kms_busy@extended-modeset-hang-oldfb-render-a.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-glk: [FAIL][41] ([fdo#104873]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6769/shard-glk9/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14150/shard-glk3/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
* igt@kms_flip@2x-flip-vs-expired-vblank:
- shard-glk: [FAIL][43] ([fdo#105363]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6769/shard-glk1/igt@kms_flip@2x-flip-vs-expired-vblank.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14150/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
- shard-iclb: [FAIL][45] ([fdo#103167]) -> [PASS][46] +4 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6769/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14150/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-skl: [INCOMPLETE][47] ([fdo#104108]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6769/shard-skl6/igt@kms_frontbuffer_tracking@fbc-suspend.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14150/shard-skl7/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-rte:
- shard-iclb: [FAIL][49] ([fdo#103167] / [fdo#110378]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6769/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-rte.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14150/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-rte.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-gtt:
- shard-skl: [FAIL][51] ([fdo#103167] / [fdo#110379]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6769/shard-skl5/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-gtt.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14150/shard-skl5/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc:
- shard-skl: [FAIL][53] ([fdo#103167]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6769/shard-skl5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14150/shard-skl5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-kbl: [FAIL][55] ([fdo#103375]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6769/shard-kbl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14150/shard-kbl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_plane_multiple@atomic-pipe-a-tiling-yf:
- shard-skl: [DMESG-WARN][57] ([fdo#106885]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6769/shard-skl4/igt@kms_plane_multiple@atomic-pipe-a-tiling-yf.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14150/shard-skl4/igt@kms_plane_multiple@atomic-pipe-a-tiling-yf.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [SKIP][59] ([fdo#109441]) -> [PASS][60] +2 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6769/shard-iclb8/igt@kms_psr@psr2_cursor_render.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14150/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
* igt@perf@polling:
- shard-skl: [FAIL][61] ([fdo#110728]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6769/shard-skl4/igt@perf@polling.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14150/shard-skl9/igt@perf@polling.html
#### Warnings ####
* igt@gem_mocs_settings@mocs-reset-bsd2:
- shard-iclb: [FAIL][63] ([fdo#111330]) -> [SKIP][64] ([fdo#109276])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6769/shard-iclb2/igt@gem_mocs_settings@mocs-reset-bsd2.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14150/shard-iclb3/igt@gem_mocs_settings@mocs-reset-bsd2.html
* igt@gem_mocs_settings@mocs-settings-bsd2:
- shard-iclb: [SKIP][65] ([fdo#109276]) -> [FAIL][66] ([fdo#111330]) +1 similar issue
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6769/shard-iclb3/igt@gem_mocs_settings@mocs-settings-bsd2.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14150/shard-iclb2/igt@gem_mocs_settings@mocs-settings-bsd2.html
* igt@kms_flip@2x-flip-vs-suspend-interruptible:
- shard-apl: [SKIP][67] ([fdo#109271]) -> [INCOMPLETE][68] ([fdo#103927])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6769/shard-apl8/igt@kms_flip@2x-flip-vs-suspend-interruptible.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14150/shard-apl4/igt@kms_flip@2x-flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-wc:
- shard-skl: [FAIL][69] ([fdo#108040]) -> [FAIL][70] ([fdo#103167])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6769/shard-skl9/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-wc.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14150/shard-skl6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-wc.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#104873]: https://bugs.freedesktop.org/show_bug.cgi?id=104873
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#106885]: https://bugs.freedesktop.org/show_bug.cgi?id=106885
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108040]: https://bugs.freedesktop.org/show_bug.cgi?id=108040
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110378]: https://bugs.freedesktop.org/show_bug.cgi?id=110378
[fdo#110379]: https://bugs.freedesktop.org/show_bug.cgi?id=110379
[fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
[fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
[fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
[fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
[fdo#111472]: https://bugs.freedesktop.org/show_bug.cgi?id=111472
[fdo#111473 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111473
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6769 -> Patchwork_14150
CI-20190529: 20190529
CI_DRM_6769: 66b20c063386eb45b5617fce6c2dca606d56a09f @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5148: 50390dd7adaccae21cafa85b866c17606cec94c3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14150: 22ec3f0c0004cb5322e6281a572616d8c9455e56 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14150/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] drm/i915/tgl: Enabling DSC on Pipe A for TGL
2019-08-23 0:46 [PATCH] drm/i915/tgl: Enabling DSC on Pipe A for TGL Madhumitha Tolakanahalli Pradeep
` (3 preceding siblings ...)
2019-08-23 19:59 ` ✗ Fi.CI.IGT: failure for drm/i915/tgl: Enabling DSC on Pipe A for TGL (rev2) Patchwork
@ 2019-08-28 20:12 ` Manasi Navare
4 siblings, 0 replies; 11+ messages in thread
From: Manasi Navare @ 2019-08-28 20:12 UTC (permalink / raw)
To: Madhumitha Tolakanahalli Pradeep; +Cc: intel-gfx
Thanks for the patch and reviews, pushed to dinq
Regards
Manasi
On Thu, Aug 22, 2019 at 05:46:55PM -0700, Madhumitha Tolakanahalli Pradeep wrote:
> DSC was not supported on Pipe A for previous platforms. Tigerlake onwards,
> all the pipes support DSC. Hence, the DSC and FEC restriction on
> Pipe A needs to be removed.
>
> v2: Changes in the logic around removing the restriction around
> Pipe A (Manasi, Lucas)
>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 21 +++++++++++++++++----
> 1 file changed, 17 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 4884c87c8ed7..e2c8fe274c84 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1739,8 +1739,14 @@ static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>
> - return INTEL_GEN(dev_priv) >= 11 &&
> - pipe_config->cpu_transcoder != TRANSCODER_A;
> + /* On TGL, FEC is supported on all Pipes */
> + if (INTEL_GEN(dev_priv) >= 12)
> + return true;
> +
> + if (IS_GEN(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A)
> + return true;
> +
> + return false;
> }
>
> static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
> @@ -1755,8 +1761,15 @@ static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>
> - return INTEL_GEN(dev_priv) >= 10 &&
> - pipe_config->cpu_transcoder != TRANSCODER_A;
> + /* On TGL, DSC is supported on all Pipes */
> + if (INTEL_GEN(dev_priv) >= 12)
> + return true;
> +
> + if (INTEL_GEN(dev_priv) >= 10 &&
> + pipe_config->cpu_transcoder != TRANSCODER_A)
> + return true;
> +
> + return false;
> }
>
> static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
> --
> 2.17.1
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] drm/i915/tgl: Enabling DSC on Pipe A for TGL
2019-08-15 18:53 ` Manasi Navare
@ 2019-08-15 19:07 ` Tolakanahalli Pradeep, Madhumitha
0 siblings, 0 replies; 11+ messages in thread
From: Tolakanahalli Pradeep, Madhumitha @ 2019-08-15 19:07 UTC (permalink / raw)
To: De Marchi, Lucas, Navare, Manasi D; +Cc: intel-gfx
On Thu, 2019-08-15 at 11:53 -0700, Manasi Navare wrote:
> On Thu, Aug 15, 2019 at 11:39:54AM -0700, Tolakanahalli Pradeep,
> Madhumitha wrote:
> > On Thu, 2019-08-15 at 11:24 -0700, Manasi Navare wrote:
> > > On Wed, Aug 14, 2019 at 04:51:17PM -0700, Madhumitha
> > > Tolakanahalli
> > > Pradeep wrote:
> > > > Removing restriction on Pipe A as TigerLake onwards, all the
> > > > pipes
> > > > support DSC.
> > >
> > > May be elaborate this commit message a little bit something like:
> > > "On previous platforms, DSC was not supported on Pipe A while
> > > starting TGL, its is supported
> > > on all pipes. So remove the DSC and FEC restriction on Pipe A for
> > > TGL
> > > onwards.
> > >
> >
> > Alright, will update that for rev2.
> >
> > > >
> > > > Cc: Manasi Navare <manasi.d.navare@intel.com>
> > > > Signed-off-by: Madhumitha Tolakanahalli Pradeep <
> > > > madhumitha.tolakanahalli.pradeep@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_dp.c | 16 ++++++++++++----
> > > > 1 file changed, 12 insertions(+), 4 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > index 4884c87c8ed7..a5b50f93fac5 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > @@ -1739,8 +1739,12 @@ static bool
> > > > intel_dp_source_supports_fec(struct intel_dp *intel_dp,
> > > > {
> > > > struct drm_i915_private *dev_priv =
> > > > dp_to_i915(intel_dp);
> > > >
> > > > - return INTEL_GEN(dev_priv) >= 11 &&
> > > > - pipe_config->cpu_transcoder != TRANSCODER_A;
> > > > + /* On TGL, DSC is supported on all Pipes */
> > >
> > > ^^^^ FEC supported on all pipes
> >
> > Oops, will change this.
> >
> > > > + if (INTEL_GEN(dev_priv) >= 12)
> > > > + return true;
> > > > + else
> > > > + return INTEL_GEN(dev_priv) == 11 &&
>
> Also here I think its better to use IS_GEN(dev_priv, 11)
Yes, that does make it clearer, I'll change it for v2.
>
> > > > + pipe_config->cpu_transcoder !=
> > > > TRANSCODER_A;
> > > > }
> > > >
> > > > static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
> > > > @@ -1755,8 +1759,12 @@ static bool
> > > > intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
> > > > {
> > > > struct drm_i915_private *dev_priv =
> > > > dp_to_i915(intel_dp);
> > > >
> > > > - return INTEL_GEN(dev_priv) >= 10 &&
> > > > - pipe_config->cpu_transcoder != TRANSCODER_A;
> > > > + /* On TGL, DSC is supported on all Pipes */
> > > > + if (INTEL_GEN(dev_priv) >= 12)
> > > > + return true;
> > > > + else
> > > > + return (INTEL_GEN(dev_priv) == 10 ||
> > > > INTEL_GEN(dev_priv) == 11) &&
> > >
> > > Why cant you just use INTEL_GEN(dev_priv) >=10 ?
> >
> > INTEL_GEN(dev_priv) >= 10 was the existing condition. With the new
> > condition added, there would be an overlapping set
> > ie INTEL_GEN(dev_priv) >= 10 would still be TRUE for GEN >= 12.
> > Though
> > this wouldn't affect the logic of the code, thought it would make
> > more
> > sense to sperate it out this way.
>
> But since we return for GEN >=12 , the only time it would fall to GEN
> >=10 is for 10 and 11
> so that should work, or you could use IS_GEN(dev_priv, 10) ||
> IS_GEN(dev_priv, 11)
>
> But may be check with Lucas on what would be the preferred way
Yeah, it wouldn't affect the logic. I debated about it for a while too.
@Lucas, what do you think is the preferred way to implement this?
>
> Manasi
> >
> > >
> > > Manasi
> > >
> > > > + pipe_config->cpu_transcoder !=
> > > > TRANSCODER_A;
> > > > }
> > > >
> > > > static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
> > > > --
> > > > 2.17.1
> > > >
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] drm/i915/tgl: Enabling DSC on Pipe A for TGL
2019-08-15 18:39 ` Tolakanahalli Pradeep, Madhumitha
@ 2019-08-15 18:53 ` Manasi Navare
2019-08-15 19:07 ` Tolakanahalli Pradeep, Madhumitha
0 siblings, 1 reply; 11+ messages in thread
From: Manasi Navare @ 2019-08-15 18:53 UTC (permalink / raw)
To: Tolakanahalli Pradeep, Madhumitha; +Cc: intel-gfx
On Thu, Aug 15, 2019 at 11:39:54AM -0700, Tolakanahalli Pradeep, Madhumitha wrote:
> On Thu, 2019-08-15 at 11:24 -0700, Manasi Navare wrote:
> > On Wed, Aug 14, 2019 at 04:51:17PM -0700, Madhumitha Tolakanahalli
> > Pradeep wrote:
> > > Removing restriction on Pipe A as TigerLake onwards, all the pipes
> > > support DSC.
> >
> > May be elaborate this commit message a little bit something like:
> > "On previous platforms, DSC was not supported on Pipe A while
> > starting TGL, its is supported
> > on all pipes. So remove the DSC and FEC restriction on Pipe A for TGL
> > onwards.
> >
>
> Alright, will update that for rev2.
>
> > >
> > > Cc: Manasi Navare <manasi.d.navare@intel.com>
> > > Signed-off-by: Madhumitha Tolakanahalli Pradeep <
> > > madhumitha.tolakanahalli.pradeep@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_dp.c | 16 ++++++++++++----
> > > 1 file changed, 12 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > index 4884c87c8ed7..a5b50f93fac5 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > @@ -1739,8 +1739,12 @@ static bool
> > > intel_dp_source_supports_fec(struct intel_dp *intel_dp,
> > > {
> > > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > >
> > > - return INTEL_GEN(dev_priv) >= 11 &&
> > > - pipe_config->cpu_transcoder != TRANSCODER_A;
> > > + /* On TGL, DSC is supported on all Pipes */
> >
> > ^^^^ FEC supported on all pipes
>
> Oops, will change this.
>
> > > + if (INTEL_GEN(dev_priv) >= 12)
> > > + return true;
> > > + else
> > > + return INTEL_GEN(dev_priv) == 11 &&
Also here I think its better to use IS_GEN(dev_priv, 11)
> > > + pipe_config->cpu_transcoder != TRANSCODER_A;
> > > }
> > >
> > > static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
> > > @@ -1755,8 +1759,12 @@ static bool
> > > intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
> > > {
> > > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > >
> > > - return INTEL_GEN(dev_priv) >= 10 &&
> > > - pipe_config->cpu_transcoder != TRANSCODER_A;
> > > + /* On TGL, DSC is supported on all Pipes */
> > > + if (INTEL_GEN(dev_priv) >= 12)
> > > + return true;
> > > + else
> > > + return (INTEL_GEN(dev_priv) == 10 ||
> > > INTEL_GEN(dev_priv) == 11) &&
> >
> > Why cant you just use INTEL_GEN(dev_priv) >=10 ?
>
> INTEL_GEN(dev_priv) >= 10 was the existing condition. With the new
> condition added, there would be an overlapping set
> ie INTEL_GEN(dev_priv) >= 10 would still be TRUE for GEN >= 12. Though
> this wouldn't affect the logic of the code, thought it would make more
> sense to sperate it out this way.
But since we return for GEN >=12 , the only time it would fall to GEN >=10 is for 10 and 11
so that should work, or you could use IS_GEN(dev_priv, 10) || IS_GEN(dev_priv, 11)
But may be check with Lucas on what would be the preferred way
Manasi
>
> >
> > Manasi
> >
> > > + pipe_config->cpu_transcoder != TRANSCODER_A;
> > > }
> > >
> > > static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
> > > --
> > > 2.17.1
> > >
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] drm/i915/tgl: Enabling DSC on Pipe A for TGL
2019-08-15 18:24 ` Manasi Navare
@ 2019-08-15 18:39 ` Tolakanahalli Pradeep, Madhumitha
2019-08-15 18:53 ` Manasi Navare
0 siblings, 1 reply; 11+ messages in thread
From: Tolakanahalli Pradeep, Madhumitha @ 2019-08-15 18:39 UTC (permalink / raw)
To: Navare, Manasi D; +Cc: intel-gfx
On Thu, 2019-08-15 at 11:24 -0700, Manasi Navare wrote:
> On Wed, Aug 14, 2019 at 04:51:17PM -0700, Madhumitha Tolakanahalli
> Pradeep wrote:
> > Removing restriction on Pipe A as TigerLake onwards, all the pipes
> > support DSC.
>
> May be elaborate this commit message a little bit something like:
> "On previous platforms, DSC was not supported on Pipe A while
> starting TGL, its is supported
> on all pipes. So remove the DSC and FEC restriction on Pipe A for TGL
> onwards.
>
Alright, will update that for rev2.
> >
> > Cc: Manasi Navare <manasi.d.navare@intel.com>
> > Signed-off-by: Madhumitha Tolakanahalli Pradeep <
> > madhumitha.tolakanahalli.pradeep@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_dp.c | 16 ++++++++++++----
> > 1 file changed, 12 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 4884c87c8ed7..a5b50f93fac5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -1739,8 +1739,12 @@ static bool
> > intel_dp_source_supports_fec(struct intel_dp *intel_dp,
> > {
> > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> >
> > - return INTEL_GEN(dev_priv) >= 11 &&
> > - pipe_config->cpu_transcoder != TRANSCODER_A;
> > + /* On TGL, DSC is supported on all Pipes */
>
> ^^^^ FEC supported on all pipes
Oops, will change this.
> > + if (INTEL_GEN(dev_priv) >= 12)
> > + return true;
> > + else
> > + return INTEL_GEN(dev_priv) == 11 &&
> > + pipe_config->cpu_transcoder != TRANSCODER_A;
> > }
> >
> > static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
> > @@ -1755,8 +1759,12 @@ static bool
> > intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
> > {
> > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> >
> > - return INTEL_GEN(dev_priv) >= 10 &&
> > - pipe_config->cpu_transcoder != TRANSCODER_A;
> > + /* On TGL, DSC is supported on all Pipes */
> > + if (INTEL_GEN(dev_priv) >= 12)
> > + return true;
> > + else
> > + return (INTEL_GEN(dev_priv) == 10 ||
> > INTEL_GEN(dev_priv) == 11) &&
>
> Why cant you just use INTEL_GEN(dev_priv) >=10 ?
INTEL_GEN(dev_priv) >= 10 was the existing condition. With the new
condition added, there would be an overlapping set
ie INTEL_GEN(dev_priv) >= 10 would still be TRUE for GEN >= 12. Though
this wouldn't affect the logic of the code, thought it would make more
sense to sperate it out this way.
>
> Manasi
>
> > + pipe_config->cpu_transcoder != TRANSCODER_A;
> > }
> >
> > static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
> > --
> > 2.17.1
> >
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] drm/i915/tgl: Enabling DSC on Pipe A for TGL
2019-08-14 23:51 Madhumitha Tolakanahalli Pradeep
@ 2019-08-15 18:24 ` Manasi Navare
2019-08-15 18:39 ` Tolakanahalli Pradeep, Madhumitha
0 siblings, 1 reply; 11+ messages in thread
From: Manasi Navare @ 2019-08-15 18:24 UTC (permalink / raw)
To: Madhumitha Tolakanahalli Pradeep; +Cc: intel-gfx
On Wed, Aug 14, 2019 at 04:51:17PM -0700, Madhumitha Tolakanahalli Pradeep wrote:
> Removing restriction on Pipe A as TigerLake onwards, all the pipes support DSC.
May be elaborate this commit message a little bit something like:
"On previous platforms, DSC was not supported on Pipe A while starting TGL, its is supported
on all pipes. So remove the DSC and FEC restriction on Pipe A for TGL onwards.
>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 16 ++++++++++++----
> 1 file changed, 12 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 4884c87c8ed7..a5b50f93fac5 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1739,8 +1739,12 @@ static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>
> - return INTEL_GEN(dev_priv) >= 11 &&
> - pipe_config->cpu_transcoder != TRANSCODER_A;
> + /* On TGL, DSC is supported on all Pipes */
^^^^ FEC supported on all pipes
> + if (INTEL_GEN(dev_priv) >= 12)
> + return true;
> + else
> + return INTEL_GEN(dev_priv) == 11 &&
> + pipe_config->cpu_transcoder != TRANSCODER_A;
> }
>
> static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
> @@ -1755,8 +1759,12 @@ static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>
> - return INTEL_GEN(dev_priv) >= 10 &&
> - pipe_config->cpu_transcoder != TRANSCODER_A;
> + /* On TGL, DSC is supported on all Pipes */
> + if (INTEL_GEN(dev_priv) >= 12)
> + return true;
> + else
> + return (INTEL_GEN(dev_priv) == 10 || INTEL_GEN(dev_priv) == 11) &&
Why cant you just use INTEL_GEN(dev_priv) >=10 ?
Manasi
> + pipe_config->cpu_transcoder != TRANSCODER_A;
> }
>
> static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
> --
> 2.17.1
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH] drm/i915/tgl: Enabling DSC on Pipe A for TGL
@ 2019-08-14 23:51 Madhumitha Tolakanahalli Pradeep
2019-08-15 18:24 ` Manasi Navare
0 siblings, 1 reply; 11+ messages in thread
From: Madhumitha Tolakanahalli Pradeep @ 2019-08-14 23:51 UTC (permalink / raw)
To: intel-gfx
Removing restriction on Pipe A as TigerLake onwards, all the pipes support DSC.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 16 ++++++++++++----
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 4884c87c8ed7..a5b50f93fac5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1739,8 +1739,12 @@ static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- return INTEL_GEN(dev_priv) >= 11 &&
- pipe_config->cpu_transcoder != TRANSCODER_A;
+ /* On TGL, DSC is supported on all Pipes */
+ if (INTEL_GEN(dev_priv) >= 12)
+ return true;
+ else
+ return INTEL_GEN(dev_priv) == 11 &&
+ pipe_config->cpu_transcoder != TRANSCODER_A;
}
static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
@@ -1755,8 +1759,12 @@ static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- return INTEL_GEN(dev_priv) >= 10 &&
- pipe_config->cpu_transcoder != TRANSCODER_A;
+ /* On TGL, DSC is supported on all Pipes */
+ if (INTEL_GEN(dev_priv) >= 12)
+ return true;
+ else
+ return (INTEL_GEN(dev_priv) == 10 || INTEL_GEN(dev_priv) == 11) &&
+ pipe_config->cpu_transcoder != TRANSCODER_A;
}
static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
end of thread, other threads:[~2019-08-28 20:10 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-08-23 0:46 [PATCH] drm/i915/tgl: Enabling DSC on Pipe A for TGL Madhumitha Tolakanahalli Pradeep
2019-08-23 0:59 ` Manasi Navare
2019-08-23 1:56 ` ✓ Fi.CI.BAT: success for drm/i915/tgl: Enabling DSC on Pipe A for TGL (rev2) Patchwork
2019-08-23 8:50 ` [PATCH] drm/i915/tgl: Enabling DSC on Pipe A for TGL Lucas De Marchi
2019-08-23 19:59 ` ✗ Fi.CI.IGT: failure for drm/i915/tgl: Enabling DSC on Pipe A for TGL (rev2) Patchwork
2019-08-28 20:12 ` [PATCH] drm/i915/tgl: Enabling DSC on Pipe A for TGL Manasi Navare
-- strict thread matches above, loose matches on Subject: below --
2019-08-14 23:51 Madhumitha Tolakanahalli Pradeep
2019-08-15 18:24 ` Manasi Navare
2019-08-15 18:39 ` Tolakanahalli Pradeep, Madhumitha
2019-08-15 18:53 ` Manasi Navare
2019-08-15 19:07 ` Tolakanahalli Pradeep, Madhumitha
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