* [PATCH 00/11] Refactor to expand subslice mask (rev 2)
@ 2019-08-22 18:32 Stuart Summers
2019-08-22 18:32 ` [PATCH 01/11] drm/i915: Use variable for debugfs device status Stuart Summers
` (13 more replies)
0 siblings, 14 replies; 22+ messages in thread
From: Stuart Summers @ 2019-08-22 18:32 UTC (permalink / raw)
To: intel-gfx
etter match what is presented to userspace through the
I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is
then calculated:
slice * subslice stride + subslice index / 8
Note this is the second iteration of an original patch to implement
the same. There are a couple of minor code changes based on changes
since the first series was posted. Additionally, the original patch
has been split into several smaller patches with more isolated
changes based on review feedback in that first series.
Link to the original series:
https://patchwork.freedesktop.org/series/59742/
v2: Fix 32-bit build
v3: Fix typo in haswell sseu info routine and fix SSEU workaround
print
v4: Merge patch to HSW in previous revision with patch to
set subslice_mask for each platform and address feedback
from Chris
v5: No changes in code. Resending due to unrelated failures - confirmed
no failures with trybot.
v6: Minor change in intel_workarounds.c to use the new helper function
v7: Split set sublice function into multiple more manageable patches
And add a couple of GEM_BUG_ON checks requested by Chris
v8: Address new comments from Chris including adding/moving
a couple of ss/eu_stride checks to those previously reviewed
patches earlier in this series
Stuart Summers (11):
drm/i915: Use variable for debugfs device status
drm/i915: Add function to set SSEU info per platform
drm/i915: Add subslice stride runtime parameter
drm/i915: Add EU stride runtime parameter
drm/i915: Use local variables for subslice_mask for device info
drm/i915: Add function to set subslices
drm/i915: Use subslice stride to set subslices for a given slice
drm/i915: Add function to determine if a slice has a subslice
drm/i915: Refactor instdone loops on new subslice functions
drm/i915: Add new function to copy subslices for a slice
drm/i915: Expand subslice mask
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 +-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 30 +++--
drivers/gpu/drm/i915/gt/intel_hangcheck.c | 3 +-
drivers/gpu/drm/i915/gt/intel_sseu.c | 39 +++++-
drivers/gpu/drm/i915/gt/intel_sseu.h | 32 ++++-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +-
drivers/gpu/drm/i915/i915_debugfs.c | 49 +++++---
drivers/gpu/drm/i915/i915_gpu_error.c | 5 +-
drivers/gpu/drm/i915/i915_query.c | 10 +-
drivers/gpu/drm/i915/intel_device_info.c | 122 +++++++++----------
10 files changed, 184 insertions(+), 114 deletions(-)
--
2.22.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 01/11] drm/i915: Use variable for debugfs device status
2019-08-22 18:32 [PATCH 00/11] Refactor to expand subslice mask (rev 2) Stuart Summers
@ 2019-08-22 18:32 ` Stuart Summers
2019-08-22 18:32 ` [PATCH 02/11] drm/i915: Add function to set SSEU info per platform Stuart Summers
` (12 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Stuart Summers @ 2019-08-22 18:32 UTC (permalink / raw)
To: intel-gfx
Use a local variable to find SSEU runtime information
in various debugfs functions.
v2: Remove extra line breaks per feedback from Chris
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_debugfs.c | 26 +++++++++++---------------
1 file changed, 11 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index b0f51591f2e4..94d6dd9fe919 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3845,8 +3845,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
sseu->slice_mask |= BIT(s);
if (IS_GEN9_BC(dev_priv))
- sseu->subslice_mask[s] =
- RUNTIME_INFO(dev_priv)->sseu.subslice_mask[s];
+ sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
@@ -3873,25 +3872,22 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
struct sseu_dev_info *sseu)
{
+ const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
int s;
sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
if (sseu->slice_mask) {
- sseu->eu_per_subslice =
- RUNTIME_INFO(dev_priv)->sseu.eu_per_subslice;
- for (s = 0; s < fls(sseu->slice_mask); s++) {
- sseu->subslice_mask[s] =
- RUNTIME_INFO(dev_priv)->sseu.subslice_mask[s];
- }
+ sseu->eu_per_subslice = info->sseu.eu_per_subslice;
+ for (s = 0; s < fls(sseu->slice_mask); s++)
+ sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
sseu->eu_total = sseu->eu_per_subslice *
intel_sseu_subslice_total(sseu);
/* subtract fused off EU(s) from enabled slice(s) */
for (s = 0; s < fls(sseu->slice_mask); s++) {
- u8 subslice_7eu =
- RUNTIME_INFO(dev_priv)->sseu.subslice_7eu[s];
+ u8 subslice_7eu = info->sseu.subslice_7eu[s];
sseu->eu_total -= hweight8(subslice_7eu);
}
@@ -3938,6 +3934,7 @@ static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
static int i915_sseu_status(struct seq_file *m, void *unused)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
+ const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
struct sseu_dev_info sseu;
intel_wakeref_t wakeref;
@@ -3945,14 +3942,13 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
return -ENODEV;
seq_puts(m, "SSEU Device Info\n");
- i915_print_sseu_info(m, true, &RUNTIME_INFO(dev_priv)->sseu);
+ i915_print_sseu_info(m, true, &info->sseu);
seq_puts(m, "SSEU Device Status\n");
memset(&sseu, 0, sizeof(sseu));
- sseu.max_slices = RUNTIME_INFO(dev_priv)->sseu.max_slices;
- sseu.max_subslices = RUNTIME_INFO(dev_priv)->sseu.max_subslices;
- sseu.max_eus_per_subslice =
- RUNTIME_INFO(dev_priv)->sseu.max_eus_per_subslice;
+ sseu.max_slices = info->sseu.max_slices;
+ sseu.max_subslices = info->sseu.max_subslices;
+ sseu.max_eus_per_subslice = info->sseu.max_eus_per_subslice;
with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) {
if (IS_CHERRYVIEW(dev_priv))
--
2.22.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 02/11] drm/i915: Add function to set SSEU info per platform
2019-08-22 18:32 [PATCH 00/11] Refactor to expand subslice mask (rev 2) Stuart Summers
2019-08-22 18:32 ` [PATCH 01/11] drm/i915: Use variable for debugfs device status Stuart Summers
@ 2019-08-22 18:32 ` Stuart Summers
2019-08-22 18:32 ` [PATCH 03/11] drm/i915: Add subslice stride runtime parameter Stuart Summers
` (11 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Stuart Summers @ 2019-08-22 18:32 UTC (permalink / raw)
To: intel-gfx
Add a new function to allow each platform to set maximum
slice, subslice, and EU information to reduce code duplication.
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 8 +++++
drivers/gpu/drm/i915/gt/intel_sseu.h | 3 ++
drivers/gpu/drm/i915/i915_debugfs.c | 6 ++--
drivers/gpu/drm/i915/intel_device_info.c | 39 +++++++++---------------
4 files changed, 28 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 6bf2d87da109..6727079eb9b6 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -8,6 +8,14 @@
#include "intel_lrc_reg.h"
#include "intel_sseu.h"
+void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
+ u8 max_subslices, u8 max_eus_per_subslice)
+{
+ sseu->max_slices = max_slices;
+ sseu->max_subslices = max_subslices;
+ sseu->max_eus_per_subslice = max_eus_per_subslice;
+}
+
unsigned int
intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index b50d0401a4e2..64e47dad07be 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -63,6 +63,9 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
return value;
}
+void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
+ u8 max_subslices, u8 max_eus_per_subslice);
+
unsigned int
intel_sseu_subslice_total(const struct sseu_dev_info *sseu);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 94d6dd9fe919..56fd696c0a92 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3946,9 +3946,9 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
seq_puts(m, "SSEU Device Status\n");
memset(&sseu, 0, sizeof(sseu));
- sseu.max_slices = info->sseu.max_slices;
- sseu.max_subslices = info->sseu.max_subslices;
- sseu.max_eus_per_subslice = info->sseu.max_eus_per_subslice;
+ intel_sseu_set_info(&sseu, info->sseu.max_slices,
+ info->sseu.max_subslices,
+ info->sseu.max_eus_per_subslice);
with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) {
if (IS_CHERRYVIEW(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index d0ed44d33484..77d7bbaa49f3 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -191,15 +191,10 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
u8 eu_en;
int s;
- if (IS_ELKHARTLAKE(dev_priv)) {
- sseu->max_slices = 1;
- sseu->max_subslices = 4;
- sseu->max_eus_per_subslice = 8;
- } else {
- sseu->max_slices = 1;
- sseu->max_subslices = 8;
- sseu->max_eus_per_subslice = 8;
- }
+ if (IS_ELKHARTLAKE(dev_priv))
+ intel_sseu_set_info(sseu, 1, 4, 8);
+ else
+ intel_sseu_set_info(sseu, 1, 8, 8);
s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK;
ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE);
@@ -236,11 +231,10 @@ static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
const int eu_mask = 0xff;
u32 subslice_mask, eu_en;
+ intel_sseu_set_info(sseu, 6, 4, 8);
+
sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
GEN10_F2_S_ENA_SHIFT;
- sseu->max_slices = 6;
- sseu->max_subslices = 4;
- sseu->max_eus_per_subslice = 8;
subslice_mask = (1 << 4) - 1;
subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
@@ -314,9 +308,7 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
fuse = I915_READ(CHV_FUSE_GT);
sseu->slice_mask = BIT(0);
- sseu->max_slices = 1;
- sseu->max_subslices = 2;
- sseu->max_eus_per_subslice = 8;
+ intel_sseu_set_info(sseu, 1, 2, 8);
if (!(fuse & CHV_FGT_DISABLE_SS0)) {
u8 disabled_mask =
@@ -372,9 +364,8 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
/* BXT has a single slice and at most 3 subslices. */
- sseu->max_slices = IS_GEN9_LP(dev_priv) ? 1 : 3;
- sseu->max_subslices = IS_GEN9_LP(dev_priv) ? 3 : 4;
- sseu->max_eus_per_subslice = 8;
+ intel_sseu_set_info(sseu, IS_GEN9_LP(dev_priv) ? 1 : 3,
+ IS_GEN9_LP(dev_priv) ? 3 : 4, 8);
/*
* The subslice disable field is global, i.e. it applies
@@ -473,9 +464,7 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
fuse2 = I915_READ(GEN8_FUSE2);
sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
- sseu->max_slices = 3;
- sseu->max_subslices = 3;
- sseu->max_eus_per_subslice = 8;
+ intel_sseu_set_info(sseu, 3, 3, 8);
/*
* The subslice disable field is global, i.e. it applies
@@ -577,9 +566,6 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
break;
}
- sseu->max_slices = hweight8(sseu->slice_mask);
- sseu->max_subslices = hweight8(sseu->subslice_mask[0]);
-
fuse1 = I915_READ(HSW_PAVP_FUSE1);
switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) {
default:
@@ -596,7 +582,10 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
sseu->eu_per_subslice = 6;
break;
}
- sseu->max_eus_per_subslice = sseu->eu_per_subslice;
+
+ intel_sseu_set_info(sseu, hweight8(sseu->slice_mask),
+ hweight8(sseu->subslice_mask[0]),
+ sseu->eu_per_subslice);
for (s = 0; s < sseu->max_slices; s++) {
for (ss = 0; ss < sseu->max_subslices; ss++) {
--
2.22.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 03/11] drm/i915: Add subslice stride runtime parameter
2019-08-22 18:32 [PATCH 00/11] Refactor to expand subslice mask (rev 2) Stuart Summers
2019-08-22 18:32 ` [PATCH 01/11] drm/i915: Use variable for debugfs device status Stuart Summers
2019-08-22 18:32 ` [PATCH 02/11] drm/i915: Add function to set SSEU info per platform Stuart Summers
@ 2019-08-22 18:32 ` Stuart Summers
2019-08-22 18:32 ` [PATCH 04/11] drm/i915: Add EU " Stuart Summers
` (10 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Stuart Summers @ 2019-08-22 18:32 UTC (permalink / raw)
To: intel-gfx
Add a new parameter, ss_stride, to the runtime info
structure. This is used to mirror the userspace concept
of subslice stride, which is a range of subslices per slice.
This patch simply adds the definition and updates usage
in the QUERY_TOPOLOGY_INFO handler.
v2: Add GEM_BUG_ON to make sure ss_stride is valid
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 3 +++
drivers/gpu/drm/i915/gt/intel_sseu.h | 3 +++
drivers/gpu/drm/i915/i915_query.c | 5 ++---
3 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 6727079eb9b6..edf39ae132c3 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -14,6 +14,9 @@ void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
sseu->max_slices = max_slices;
sseu->max_subslices = max_subslices;
sseu->max_eus_per_subslice = max_eus_per_subslice;
+
+ sseu->ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
+ GEM_BUG_ON(sseu->ss_stride > GEN_MAX_SUBSLICE_STRIDE);
}
unsigned int
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 64e47dad07be..8b8b562ff773 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -15,6 +15,7 @@ struct drm_i915_private;
#define GEN_MAX_SLICES (6) /* CNL upper bound */
#define GEN_MAX_SUBSLICES (8) /* ICL upper bound */
#define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
+#define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES)
struct sseu_dev_info {
u8 slice_mask;
@@ -33,6 +34,8 @@ struct sseu_dev_info {
u8 max_subslices;
u8 max_eus_per_subslice;
+ u8 ss_stride;
+
/* We don't have more than 8 eus per subslice at the moment and as we
* store eus enabled using bits, no need to multiply by eus per
* subslice.
diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index ad9240a0817a..d8e25dcf5f0b 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -37,7 +37,6 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
struct drm_i915_query_topology_info topo;
u32 slice_length, subslice_length, eu_length, total_length;
- u8 subslice_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
u8 eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
int ret;
@@ -50,7 +49,7 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
slice_length = sizeof(sseu->slice_mask);
- subslice_length = sseu->max_slices * subslice_stride;
+ subslice_length = sseu->max_slices * sseu->ss_stride;
eu_length = sseu->max_slices * sseu->max_subslices * eu_stride;
total_length = sizeof(topo) + slice_length + subslice_length +
eu_length;
@@ -69,7 +68,7 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
topo.max_eus_per_subslice = sseu->max_eus_per_subslice;
topo.subslice_offset = slice_length;
- topo.subslice_stride = subslice_stride;
+ topo.subslice_stride = sseu->ss_stride;
topo.eu_offset = slice_length + subslice_length;
topo.eu_stride = eu_stride;
--
2.22.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 04/11] drm/i915: Add EU stride runtime parameter
2019-08-22 18:32 [PATCH 00/11] Refactor to expand subslice mask (rev 2) Stuart Summers
` (2 preceding siblings ...)
2019-08-22 18:32 ` [PATCH 03/11] drm/i915: Add subslice stride runtime parameter Stuart Summers
@ 2019-08-22 18:32 ` Stuart Summers
2019-08-22 18:32 ` [PATCH 05/11] drm/i915: Use local variables for subslice_mask for device info Stuart Summers
` (9 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Stuart Summers @ 2019-08-22 18:32 UTC (permalink / raw)
To: intel-gfx
Add a new SSEU runtime parameter, eu_stride, which is
used to mirror the userspace concept of a range of EUs
per subslice.
This patch simply adds the parameter and updates usage
in the QUERY_TOPOLOGY_INFO handler.
v2: Add GEM_BUG_ON to make sure eu_stride is valid
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 2 ++
drivers/gpu/drm/i915/gt/intel_sseu.h | 3 +++
drivers/gpu/drm/i915/i915_query.c | 5 ++---
drivers/gpu/drm/i915/intel_device_info.c | 9 ++++-----
4 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index edf39ae132c3..d52686a1afdc 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -17,6 +17,8 @@ void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
sseu->ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
GEM_BUG_ON(sseu->ss_stride > GEN_MAX_SUBSLICE_STRIDE);
+ sseu->eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
+ GEM_BUG_ON(sseu->eu_stride > GEN_MAX_EU_STRIDE);
}
unsigned int
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 8b8b562ff773..7f2355ce963d 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -16,6 +16,8 @@ struct drm_i915_private;
#define GEN_MAX_SUBSLICES (8) /* ICL upper bound */
#define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
#define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES)
+#define GEN_MAX_EUS (10) /* HSW upper bound */
+#define GEN_MAX_EU_STRIDE GEN_SSEU_STRIDE(GEN_MAX_EUS)
struct sseu_dev_info {
u8 slice_mask;
@@ -35,6 +37,7 @@ struct sseu_dev_info {
u8 max_eus_per_subslice;
u8 ss_stride;
+ u8 eu_stride;
/* We don't have more than 8 eus per subslice at the moment and as we
* store eus enabled using bits, no need to multiply by eus per
diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index d8e25dcf5f0b..abac5042da2b 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -37,7 +37,6 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
struct drm_i915_query_topology_info topo;
u32 slice_length, subslice_length, eu_length, total_length;
- u8 eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
int ret;
if (query_item->flags != 0)
@@ -50,7 +49,7 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
slice_length = sizeof(sseu->slice_mask);
subslice_length = sseu->max_slices * sseu->ss_stride;
- eu_length = sseu->max_slices * sseu->max_subslices * eu_stride;
+ eu_length = sseu->max_slices * sseu->max_subslices * sseu->eu_stride;
total_length = sizeof(topo) + slice_length + subslice_length +
eu_length;
@@ -70,7 +69,7 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
topo.subslice_offset = slice_length;
topo.subslice_stride = sseu->ss_stride;
topo.eu_offset = slice_length + subslice_length;
- topo.eu_stride = eu_stride;
+ topo.eu_stride = sseu->eu_stride;
if (__copy_to_user(u64_to_user_ptr(query_item->data_ptr),
&topo, sizeof(topo)))
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 77d7bbaa49f3..b1a79ed408eb 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -118,10 +118,9 @@ void intel_device_info_dump_runtime(const struct intel_runtime_info *info,
static int sseu_eu_idx(const struct sseu_dev_info *sseu, int slice,
int subslice)
{
- int subslice_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
- int slice_stride = sseu->max_subslices * subslice_stride;
+ int slice_stride = sseu->max_subslices * sseu->eu_stride;
- return slice * slice_stride + subslice * subslice_stride;
+ return slice * slice_stride + subslice * sseu->eu_stride;
}
static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
@@ -130,7 +129,7 @@ static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
int i, offset = sseu_eu_idx(sseu, slice, subslice);
u16 eu_mask = 0;
- for (i = 0; i < GEN_SSEU_STRIDE(sseu->max_eus_per_subslice); i++) {
+ for (i = 0; i < sseu->eu_stride; i++) {
eu_mask |= ((u16)sseu->eu_mask[offset + i]) <<
(i * BITS_PER_BYTE);
}
@@ -143,7 +142,7 @@ static void sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice,
{
int i, offset = sseu_eu_idx(sseu, slice, subslice);
- for (i = 0; i < GEN_SSEU_STRIDE(sseu->max_eus_per_subslice); i++) {
+ for (i = 0; i < sseu->eu_stride; i++) {
sseu->eu_mask[offset + i] =
(eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
}
--
2.22.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 05/11] drm/i915: Use local variables for subslice_mask for device info
2019-08-22 18:32 [PATCH 00/11] Refactor to expand subslice mask (rev 2) Stuart Summers
` (3 preceding siblings ...)
2019-08-22 18:32 ` [PATCH 04/11] drm/i915: Add EU " Stuart Summers
@ 2019-08-22 18:32 ` Stuart Summers
2019-08-22 18:32 ` [PATCH 06/11] drm/i915: Add function to set subslices Stuart Summers
` (8 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Stuart Summers @ 2019-08-22 18:32 UTC (permalink / raw)
To: intel-gfx
When setting up subslice_mask, instead of operating on the slice
array directly, use a local variable to start bits per slice, then
use this to set the per slice array in one step.
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/intel_device_info.c | 49 +++++++++++++-----------
1 file changed, 26 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index b1a79ed408eb..52515efe9f4e 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -235,18 +235,6 @@ static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
GEN10_F2_S_ENA_SHIFT;
- subslice_mask = (1 << 4) - 1;
- subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
- GEN10_F2_SS_DIS_SHIFT);
-
- /*
- * Slice0 can have up to 3 subslices, but there are only 2 in
- * slice1/2.
- */
- sseu->subslice_mask[0] = subslice_mask;
- for (s = 1; s < sseu->max_slices; s++)
- sseu->subslice_mask[s] = subslice_mask & 0x3;
-
/* Slice0 */
eu_en = ~I915_READ(GEN8_EU_DISABLE0);
for (ss = 0; ss < sseu->max_subslices; ss++)
@@ -270,14 +258,24 @@ static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
eu_en = ~I915_READ(GEN10_EU_DISABLE3);
sseu_set_eus(sseu, 5, 1, eu_en & eu_mask);
- /* Do a second pass where we mark the subslices disabled if all their
- * eus are off.
- */
+ subslice_mask = (1 << 4) - 1;
+ subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
+ GEN10_F2_SS_DIS_SHIFT);
+
for (s = 0; s < sseu->max_slices; s++) {
+ u32 subslice_mask_with_eus = subslice_mask;
+
for (ss = 0; ss < sseu->max_subslices; ss++) {
if (sseu_get_eus(sseu, s, ss) == 0)
- sseu->subslice_mask[s] &= ~BIT(ss);
+ subslice_mask_with_eus &= ~BIT(ss);
}
+
+ /*
+ * Slice0 can have up to 3 subslices, but there are only 2 in
+ * slice1/2.
+ */
+ sseu->subslice_mask[s] = s == 0 ? subslice_mask_with_eus :
+ subslice_mask_with_eus & 0x3;
}
sseu->eu_total = compute_eu_total(sseu);
@@ -303,6 +301,7 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
{
struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
u32 fuse;
+ u8 subslice_mask = 0;
fuse = I915_READ(CHV_FUSE_GT);
@@ -316,7 +315,7 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
(((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >>
CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);
- sseu->subslice_mask[0] |= BIT(0);
+ subslice_mask |= BIT(0);
sseu_set_eus(sseu, 0, 0, ~disabled_mask);
}
@@ -327,10 +326,12 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
(((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >>
CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4);
- sseu->subslice_mask[0] |= BIT(1);
+ subslice_mask |= BIT(1);
sseu_set_eus(sseu, 0, 1, ~disabled_mask);
}
+ sseu->subslice_mask[0] = subslice_mask;
+
sseu->eu_total = compute_eu_total(sseu);
/*
@@ -540,6 +541,7 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
{
struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
u32 fuse1;
+ u8 subslice_mask = 0;
int s, ss;
/*
@@ -552,16 +554,15 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
/* fall through */
case 1:
sseu->slice_mask = BIT(0);
- sseu->subslice_mask[0] = BIT(0);
+ subslice_mask = BIT(0);
break;
case 2:
sseu->slice_mask = BIT(0);
- sseu->subslice_mask[0] = BIT(0) | BIT(1);
+ subslice_mask = BIT(0) | BIT(1);
break;
case 3:
sseu->slice_mask = BIT(0) | BIT(1);
- sseu->subslice_mask[0] = BIT(0) | BIT(1);
- sseu->subslice_mask[1] = BIT(0) | BIT(1);
+ subslice_mask = BIT(0) | BIT(1);
break;
}
@@ -583,10 +584,12 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
}
intel_sseu_set_info(sseu, hweight8(sseu->slice_mask),
- hweight8(sseu->subslice_mask[0]),
+ hweight8(subslice_mask),
sseu->eu_per_subslice);
for (s = 0; s < sseu->max_slices; s++) {
+ sseu->subslice_mask[s] = subslice_mask;
+
for (ss = 0; ss < sseu->max_subslices; ss++) {
sseu_set_eus(sseu, s, ss,
(1UL << sseu->eu_per_subslice) - 1);
--
2.22.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 06/11] drm/i915: Add function to set subslices
2019-08-22 18:32 [PATCH 00/11] Refactor to expand subslice mask (rev 2) Stuart Summers
` (4 preceding siblings ...)
2019-08-22 18:32 ` [PATCH 05/11] drm/i915: Use local variables for subslice_mask for device info Stuart Summers
@ 2019-08-22 18:32 ` Stuart Summers
2019-08-22 22:39 ` Chris Wilson
2019-08-22 18:32 ` [PATCH 07/11] drm/i915: Use subslice stride to set subslices for a given slice Stuart Summers
` (7 subsequent siblings)
13 siblings, 1 reply; 22+ messages in thread
From: Stuart Summers @ 2019-08-22 18:32 UTC (permalink / raw)
To: intel-gfx
Add a new function to set a set of subslices for a given
slice.
v2: Fix typo in subslice_mask assignment
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 6 ++++++
drivers/gpu/drm/i915/gt/intel_sseu.h | 3 +++
drivers/gpu/drm/i915/intel_device_info.c | 18 +++++++++++-------
3 files changed, 20 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index d52686a1afdc..3a5db0dbac72 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -32,6 +32,12 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
return total;
}
+void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
+ u8 ss_mask)
+{
+ sseu->subslice_mask[slice] = ss_mask;
+}
+
unsigned int
intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 7f2355ce963d..7f600f50dedb 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -78,6 +78,9 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu);
unsigned int
intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice);
+void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
+ u8 ss_mask);
+
u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
const struct intel_sseu *req_sseu);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 52515efe9f4e..1a45728ac712 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -206,7 +206,10 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
int ss;
sseu->slice_mask |= BIT(s);
- sseu->subslice_mask[s] = (ss_en >> ss_idx) & ss_en_mask;
+
+ intel_sseu_set_subslices(sseu, s, (ss_en >> ss_idx) &
+ ss_en_mask);
+
for (ss = 0; ss < sseu->max_subslices; ss++) {
if (sseu->subslice_mask[s] & BIT(ss))
sseu_set_eus(sseu, s, ss, eu_en);
@@ -274,8 +277,9 @@ static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
* Slice0 can have up to 3 subslices, but there are only 2 in
* slice1/2.
*/
- sseu->subslice_mask[s] = s == 0 ? subslice_mask_with_eus :
- subslice_mask_with_eus & 0x3;
+ intel_sseu_set_subslices(sseu, s, s == 0 ?
+ subslice_mask_with_eus :
+ subslice_mask_with_eus & 0x3);
}
sseu->eu_total = compute_eu_total(sseu);
@@ -330,7 +334,7 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
sseu_set_eus(sseu, 0, 1, ~disabled_mask);
}
- sseu->subslice_mask[0] = subslice_mask;
+ intel_sseu_set_subslices(sseu, 0, subslice_mask);
sseu->eu_total = compute_eu_total(sseu);
@@ -384,7 +388,7 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
/* skip disabled slice */
continue;
- sseu->subslice_mask[s] = subslice_mask;
+ intel_sseu_set_subslices(sseu, s, subslice_mask);
eu_disable = I915_READ(GEN9_EU_DISABLE(s));
for (ss = 0; ss < sseu->max_subslices; ss++) {
@@ -491,7 +495,7 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
/* skip disabled slice */
continue;
- sseu->subslice_mask[s] = subslice_mask;
+ intel_sseu_set_subslices(sseu, s, subslice_mask);
for (ss = 0; ss < sseu->max_subslices; ss++) {
u8 eu_disabled_mask;
@@ -588,7 +592,7 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
sseu->eu_per_subslice);
for (s = 0; s < sseu->max_slices; s++) {
- sseu->subslice_mask[s] = subslice_mask;
+ intel_sseu_set_subslices(sseu, s, subslice_mask);
for (ss = 0; ss < sseu->max_subslices; ss++) {
sseu_set_eus(sseu, s, ss,
--
2.22.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 07/11] drm/i915: Use subslice stride to set subslices for a given slice
2019-08-22 18:32 [PATCH 00/11] Refactor to expand subslice mask (rev 2) Stuart Summers
` (5 preceding siblings ...)
2019-08-22 18:32 ` [PATCH 06/11] drm/i915: Add function to set subslices Stuart Summers
@ 2019-08-22 18:32 ` Stuart Summers
2019-08-22 22:43 ` Chris Wilson
2019-08-22 18:32 ` [PATCH 08/11] drm/i915: Add function to determine if a slice has a subslice Stuart Summers
` (6 subsequent siblings)
13 siblings, 1 reply; 22+ messages in thread
From: Stuart Summers @ 2019-08-22 18:32 UTC (permalink / raw)
To: intel-gfx
Add a subslice stride calculation when setting subslices. This
aligns more closely with the userspace expectation of the subslice
mask structure.
v2: Use local variable for subslice_mask on HSW and
clean up a few other subslice_mask local variable
changes
v3: Add GEM_BUG_ON for ss_stride to prevent array overflow (Chris)
Split main set function and refactors in intel_device_info.c
into separate patches (Chris)
v4: Reduce ss_stride size check when setting subslices per slice
based on actual expected max stride (Chris)
Move that GEM_BUG_ON check for the ss_stride out to the patch
which adds the ss_stride
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 8 ++++++--
drivers/gpu/drm/i915/gt/intel_sseu.h | 2 +-
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 3a5db0dbac72..a0d32270248c 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -33,9 +33,13 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
}
void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
- u8 ss_mask)
+ u32 ss_mask)
{
- sseu->subslice_mask[slice] = ss_mask;
+ int i, offset = slice * sseu->ss_stride;
+
+ for (i = 0; i < sseu->ss_stride; i++)
+ sseu->subslice_mask[offset + i] =
+ (ss_mask >> (BITS_PER_BYTE * i)) & 0xff;
}
unsigned int
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 7f600f50dedb..73a9064291a2 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -79,7 +79,7 @@ unsigned int
intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice);
void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
- u8 ss_mask);
+ u32 ss_mask);
u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
const struct intel_sseu *req_sseu);
--
2.22.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 08/11] drm/i915: Add function to determine if a slice has a subslice
2019-08-22 18:32 [PATCH 00/11] Refactor to expand subslice mask (rev 2) Stuart Summers
` (6 preceding siblings ...)
2019-08-22 18:32 ` [PATCH 07/11] drm/i915: Use subslice stride to set subslices for a given slice Stuart Summers
@ 2019-08-22 18:32 ` Stuart Summers
2019-08-22 18:32 ` [PATCH 09/11] drm/i915: Refactor instdone loops on new subslice functions Stuart Summers
` (5 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Stuart Summers @ 2019-08-22 18:32 UTC (permalink / raw)
To: intel-gfx
Add a new function to determine whether a particular slice
has a given subslice.
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_sseu.h | 16 ++++++++++++++++
drivers/gpu/drm/i915/intel_device_info.c | 9 ++++-----
2 files changed, 20 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 73a9064291a2..7703d75f2da3 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -10,6 +10,8 @@
#include <linux/types.h>
#include <linux/kernel.h>
+#include "i915_gem.h"
+
struct drm_i915_private;
#define GEN_MAX_SLICES (6) /* CNL upper bound */
@@ -69,6 +71,20 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
return value;
}
+static inline bool
+intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice,
+ int subslice)
+{
+ u8 mask;
+ int ss_idx = subslice / BITS_PER_BYTE;
+
+ GEM_BUG_ON(ss_idx >= sseu->ss_stride);
+
+ mask = sseu->subslice_mask[slice * sseu->ss_stride + ss_idx];
+
+ return mask & BIT(subslice % BITS_PER_BYTE);
+}
+
void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
u8 max_subslices, u8 max_eus_per_subslice);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 1a45728ac712..c20f74ee5f22 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -210,10 +210,9 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
intel_sseu_set_subslices(sseu, s, (ss_en >> ss_idx) &
ss_en_mask);
- for (ss = 0; ss < sseu->max_subslices; ss++) {
- if (sseu->subslice_mask[s] & BIT(ss))
+ for (ss = 0; ss < sseu->max_subslices; ss++)
+ if (intel_sseu_has_subslice(sseu, s, ss))
sseu_set_eus(sseu, s, ss, eu_en);
- }
}
}
sseu->eu_per_subslice = hweight8(eu_en);
@@ -395,7 +394,7 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
int eu_per_ss;
u8 eu_disabled_mask;
- if (!(sseu->subslice_mask[s] & BIT(ss)))
+ if (!intel_sseu_has_subslice(sseu, s, ss))
/* skip disabled subslice */
continue;
@@ -501,7 +500,7 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
u8 eu_disabled_mask;
u32 n_disabled;
- if (!(sseu->subslice_mask[s] & BIT(ss)))
+ if (!intel_sseu_has_subslice(sseu, s, ss))
/* skip disabled subslice */
continue;
--
2.22.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 09/11] drm/i915: Refactor instdone loops on new subslice functions
2019-08-22 18:32 [PATCH 00/11] Refactor to expand subslice mask (rev 2) Stuart Summers
` (7 preceding siblings ...)
2019-08-22 18:32 ` [PATCH 08/11] drm/i915: Add function to determine if a slice has a subslice Stuart Summers
@ 2019-08-22 18:32 ` Stuart Summers
2019-08-22 18:32 ` [PATCH 10/11] drm/i915: Add new function to copy subslices for a slice Stuart Summers
` (4 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Stuart Summers @ 2019-08-22 18:32 UTC (permalink / raw)
To: intel-gfx
Refactor instdone loops to use the new intel_sseu_has_subslice
function.
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 +-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 30 +++++++++-----------
drivers/gpu/drm/i915/gt/intel_hangcheck.c | 3 +-
drivers/gpu/drm/i915/i915_debugfs.c | 5 ++--
drivers/gpu/drm/i915/i915_gpu_error.c | 5 ++--
5 files changed, 24 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 82630db0394b..17006d50b63f 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -948,6 +948,7 @@ void intel_engine_get_instdone(struct intel_engine_cs *engine,
struct intel_instdone *instdone)
{
struct drm_i915_private *i915 = engine->i915;
+ const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
struct intel_uncore *uncore = engine->uncore;
u32 mmio_base = engine->mmio_base;
int slice;
@@ -965,7 +966,7 @@ void intel_engine_get_instdone(struct intel_engine_cs *engine,
instdone->slice_common =
intel_uncore_read(uncore, GEN7_SC_INSTDONE);
- for_each_instdone_slice_subslice(i915, slice, subslice) {
+ for_each_instdone_slice_subslice(i915, sseu, slice, subslice) {
instdone->sampler[slice][subslice] =
read_subslice_reg(engine, slice, subslice,
GEN7_SAMPLER_INSTDONE);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index a82cea95c2f2..15e02cb58a67 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -576,20 +576,18 @@ intel_engine_is_virtual(const struct intel_engine_cs *engine)
return engine->flags & I915_ENGINE_IS_VIRTUAL;
}
-#define instdone_slice_mask(dev_priv__) \
- (IS_GEN(dev_priv__, 7) ? \
- 1 : RUNTIME_INFO(dev_priv__)->sseu.slice_mask)
-
-#define instdone_subslice_mask(dev_priv__) \
- (IS_GEN(dev_priv__, 7) ? \
- 1 : RUNTIME_INFO(dev_priv__)->sseu.subslice_mask[0])
-
-#define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \
- for ((slice__) = 0, (subslice__) = 0; \
- (slice__) < I915_MAX_SLICES; \
- (subslice__) = ((subslice__) + 1) < I915_MAX_SUBSLICES ? (subslice__) + 1 : 0, \
- (slice__) += ((subslice__) == 0)) \
- for_each_if((BIT(slice__) & instdone_slice_mask(dev_priv__)) && \
- (BIT(subslice__) & instdone_subslice_mask(dev_priv__)))
-
+#define instdone_has_slice(dev_priv___, sseu___, slice___) \
+ ((IS_GEN(dev_priv___, 7) ? 1 : ((sseu___)->slice_mask)) & BIT(slice___))
+
+#define instdone_has_subslice(dev_priv__, sseu__, slice__, subslice__) \
+ (IS_GEN(dev_priv__, 7) ? (1 & BIT(subslice__)) : \
+ intel_sseu_has_subslice(sseu__, 0, subslice__))
+
+#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
+ for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
+ (subslice_) = ((subslice_) + 1) % I915_MAX_SUBSLICES, \
+ (slice_) += ((subslice_) == 0)) \
+ for_each_if((instdone_has_slice(dev_priv_, sseu_, slice_)) && \
+ (instdone_has_subslice(dev_priv_, sseu_, slice_, \
+ subslice_)))
#endif /* __INTEL_ENGINE_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_hangcheck.c b/drivers/gpu/drm/i915/gt/intel_hangcheck.c
index 05d042cdefe2..40f62f780be5 100644
--- a/drivers/gpu/drm/i915/gt/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/intel_hangcheck.c
@@ -53,6 +53,7 @@ static bool instdone_unchanged(u32 current_instdone, u32 *old_instdone)
static bool subunits_stuck(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
+ const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
struct intel_instdone instdone;
struct intel_instdone *accu_instdone = &engine->hangcheck.instdone;
bool stuck;
@@ -71,7 +72,7 @@ static bool subunits_stuck(struct intel_engine_cs *engine)
stuck &= instdone_unchanged(instdone.slice_common,
&accu_instdone->slice_common);
- for_each_instdone_slice_subslice(dev_priv, slice, subslice) {
+ for_each_instdone_slice_subslice(dev_priv, sseu, slice, subslice) {
stuck &= instdone_unchanged(instdone.sampler[slice][subslice],
&accu_instdone->sampler[slice][subslice]);
stuck &= instdone_unchanged(instdone.row[slice][subslice],
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 56fd696c0a92..549a121e583c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -996,6 +996,7 @@ static void i915_instdone_info(struct drm_i915_private *dev_priv,
struct seq_file *m,
struct intel_instdone *instdone)
{
+ const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
int slice;
int subslice;
@@ -1011,11 +1012,11 @@ static void i915_instdone_info(struct drm_i915_private *dev_priv,
if (INTEL_GEN(dev_priv) <= 6)
return;
- for_each_instdone_slice_subslice(dev_priv, slice, subslice)
+ for_each_instdone_slice_subslice(dev_priv, sseu, slice, subslice)
seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
slice, subslice, instdone->sampler[slice][subslice]);
- for_each_instdone_slice_subslice(dev_priv, slice, subslice)
+ for_each_instdone_slice_subslice(dev_priv, sseu, slice, subslice)
seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n",
slice, subslice, instdone->row[slice][subslice]);
}
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index e284bd76fa86..4aff342b8944 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -421,6 +421,7 @@ static void err_compression_marker(struct drm_i915_error_state_buf *m)
static void error_print_instdone(struct drm_i915_error_state_buf *m,
const struct drm_i915_error_engine *ee)
{
+ const struct sseu_dev_info *sseu = &RUNTIME_INFO(m->i915)->sseu;
int slice;
int subslice;
@@ -436,12 +437,12 @@ static void error_print_instdone(struct drm_i915_error_state_buf *m,
if (INTEL_GEN(m->i915) <= 6)
return;
- for_each_instdone_slice_subslice(m->i915, slice, subslice)
+ for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice)
err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
slice, subslice,
ee->instdone.sampler[slice][subslice]);
- for_each_instdone_slice_subslice(m->i915, slice, subslice)
+ for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice)
err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n",
slice, subslice,
ee->instdone.row[slice][subslice]);
--
2.22.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 10/11] drm/i915: Add new function to copy subslices for a slice
2019-08-22 18:32 [PATCH 00/11] Refactor to expand subslice mask (rev 2) Stuart Summers
` (8 preceding siblings ...)
2019-08-22 18:32 ` [PATCH 09/11] drm/i915: Refactor instdone loops on new subslice functions Stuart Summers
@ 2019-08-22 18:32 ` Stuart Summers
2019-08-22 18:32 ` [PATCH 11/11] drm/i915: Expand subslice mask Stuart Summers
` (3 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Stuart Summers @ 2019-08-22 18:32 UTC (permalink / raw)
To: intel-gfx
Add a new function to copy subslices for a specified slice
between intel_sseu structures for the purpose of determining
power-gate status. Note that currently ss_stride has a max
of 1.
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_debugfs.c | 17 ++++++++++++++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 549a121e583c..ba93194752c0 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3722,6 +3722,15 @@ i915_cache_sharing_set(void *data, u64 val)
return 0;
}
+static void
+intel_sseu_copy_subslices(const struct sseu_dev_info *sseu, int slice,
+ u8 *to_mask)
+{
+ int offset = slice * sseu->ss_stride;
+
+ memcpy(&to_mask[offset], &sseu->subslice_mask[offset], sseu->ss_stride);
+}
+
DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
i915_cache_sharing_get, i915_cache_sharing_set,
"%llu\n");
@@ -3795,7 +3804,7 @@ static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
continue;
sseu->slice_mask |= BIT(s);
- sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
+ intel_sseu_copy_subslices(&info->sseu, s, sseu->subslice_mask);
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
@@ -3846,7 +3855,8 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
sseu->slice_mask |= BIT(s);
if (IS_GEN9_BC(dev_priv))
- sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
+ intel_sseu_copy_subslices(&info->sseu, s,
+ sseu->subslice_mask);
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
@@ -3882,7 +3892,8 @@ static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
if (sseu->slice_mask) {
sseu->eu_per_subslice = info->sseu.eu_per_subslice;
for (s = 0; s < fls(sseu->slice_mask); s++)
- sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
+ intel_sseu_copy_subslices(&info->sseu, s,
+ sseu->subslice_mask);
sseu->eu_total = sseu->eu_per_subslice *
intel_sseu_subslice_total(sseu);
--
2.22.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 11/11] drm/i915: Expand subslice mask
2019-08-22 18:32 [PATCH 00/11] Refactor to expand subslice mask (rev 2) Stuart Summers
` (9 preceding siblings ...)
2019-08-22 18:32 ` [PATCH 10/11] drm/i915: Add new function to copy subslices for a slice Stuart Summers
@ 2019-08-22 18:32 ` Stuart Summers
2019-08-22 18:45 ` ✗ Fi.CI.CHECKPATCH: warning for Refactor to expand subslice mask (rev 2) Patchwork
` (2 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Stuart Summers @ 2019-08-22 18:32 UTC (permalink / raw)
To: intel-gfx
Currently, the subslice_mask runtime parameter is stored as an
array of subslices per slice. Expand the subslice mask array to
better match what is presented to userspace through the
I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is
then calculated:
slice * subslice stride + subslice index / 8
v2: Fix 32-bit build
v3: Use new helper function in SSEU workaround warning message
v4: Use GEM_BUG_ON to force developers to use valid SSEU configurations
per platform (Chris)
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 16 +++++++++++++++-
drivers/gpu/drm/i915/gt/intel_sseu.h | 4 +++-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 ++---
drivers/gpu/drm/i915/i915_debugfs.c | 5 ++++-
drivers/gpu/drm/i915/intel_device_info.c | 8 ++++----
5 files changed, 28 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index a0d32270248c..3c3462029966 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -32,6 +32,20 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
return total;
}
+u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice)
+{
+ int i, offset = slice * sseu->ss_stride;
+ u32 mask = 0;
+
+ GEM_BUG_ON(slice >= sseu->max_slices);
+
+ for (i = 0; i < sseu->ss_stride; i++)
+ mask |= (u32)sseu->subslice_mask[offset + i] <<
+ i * BITS_PER_BYTE;
+
+ return mask;
+}
+
void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
u32 ss_mask)
{
@@ -45,7 +59,7 @@ void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
unsigned int
intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
{
- return hweight8(sseu->subslice_mask[slice]);
+ return hweight32(intel_sseu_get_subslices(sseu, slice));
}
u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 7703d75f2da3..4070f6ff1db6 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -23,7 +23,7 @@ struct drm_i915_private;
struct sseu_dev_info {
u8 slice_mask;
- u8 subslice_mask[GEN_MAX_SLICES];
+ u8 subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE];
u16 eu_total;
u8 eu_per_subslice;
u8 min_eu_in_pool;
@@ -94,6 +94,8 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu);
unsigned int
intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice);
+u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice);
+
void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
u32 ss_mask);
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 126ab3667919..ad2261e0cba8 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -801,11 +801,10 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
}
slice = fls(sseu->slice_mask) - 1;
- GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
- subslice = fls(l3_en & sseu->subslice_mask[slice]);
+ subslice = fls(l3_en & intel_sseu_get_subslices(sseu, slice));
if (!subslice) {
DRM_WARN("No common index found between subslice mask %x and L3 bank mask %x!\n",
- sseu->subslice_mask[slice], l3_en);
+ intel_sseu_get_subslices(sseu, slice), l3_en);
subslice = fls(l3_en);
WARN_ON(!subslice);
}
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index ba93194752c0..54f02718effb 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3860,13 +3860,16 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
+ u8 ss_idx = s * info->sseu.ss_stride +
+ ss / BITS_PER_BYTE;
if (IS_GEN9_LP(dev_priv)) {
if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
/* skip disabled subslice */
continue;
- sseu->subslice_mask[s] |= BIT(ss);
+ sseu->subslice_mask[ss_idx] |=
+ BIT(ss % BITS_PER_BYTE);
}
eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index c20f74ee5f22..d9b5baaef5d0 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -93,9 +93,9 @@ static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
hweight8(sseu->slice_mask), sseu->slice_mask);
drm_printf(p, "subslice total: %u\n", intel_sseu_subslice_total(sseu));
for (s = 0; s < sseu->max_slices; s++) {
- drm_printf(p, "slice%d: %u subslices, mask=%04x\n",
+ drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
s, intel_sseu_subslices_per_slice(sseu, s),
- sseu->subslice_mask[s]);
+ intel_sseu_get_subslices(sseu, s));
}
drm_printf(p, "EU total: %u\n", sseu->eu_total);
drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice);
@@ -159,9 +159,9 @@ void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
}
for (s = 0; s < sseu->max_slices; s++) {
- drm_printf(p, "slice%d: %u subslice(s) (0x%hhx):\n",
+ drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n",
s, intel_sseu_subslices_per_slice(sseu, s),
- sseu->subslice_mask[s]);
+ intel_sseu_get_subslices(sseu, s));
for (ss = 0; ss < sseu->max_subslices; ss++) {
u16 enabled_eus = sseu_get_eus(sseu, s, ss);
--
2.22.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for Refactor to expand subslice mask (rev 2)
2019-08-22 18:32 [PATCH 00/11] Refactor to expand subslice mask (rev 2) Stuart Summers
` (10 preceding siblings ...)
2019-08-22 18:32 ` [PATCH 11/11] drm/i915: Expand subslice mask Stuart Summers
@ 2019-08-22 18:45 ` Patchwork
2019-08-22 19:10 ` ✓ Fi.CI.BAT: success " Patchwork
2019-08-23 13:44 ` ✗ Fi.CI.IGT: failure " Patchwork
13 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2019-08-22 18:45 UTC (permalink / raw)
To: Stuart Summers; +Cc: intel-gfx
== Series Details ==
Series: Refactor to expand subslice mask (rev 2)
URL : https://patchwork.freedesktop.org/series/65639/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
feeaef8cfa8b drm/i915: Use variable for debugfs device status
0771e1cc9fe8 drm/i915: Add function to set SSEU info per platform
0c045a5315e1 drm/i915: Add subslice stride runtime parameter
a1a0c0a580df drm/i915: Add EU stride runtime parameter
58829bc19d44 drm/i915: Use local variables for subslice_mask for device info
cebfb11acc33 drm/i915: Add function to set subslices
e59b1027cb44 drm/i915: Use subslice stride to set subslices for a given slice
e5926395d481 drm/i915: Add function to determine if a slice has a subslice
27f2df7c0217 drm/i915: Refactor instdone loops on new subslice functions
-:60: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'subslice__' - possible side-effects?
#60: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:582:
+#define instdone_has_subslice(dev_priv__, sseu__, slice__, subslice__) \
+ (IS_GEN(dev_priv__, 7) ? (1 & BIT(subslice__)) : \
+ intel_sseu_has_subslice(sseu__, 0, subslice__))
-:64: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv_' - possible side-effects?
#64: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:586:
+#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
+ for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
+ (subslice_) = ((subslice_) + 1) % I915_MAX_SUBSLICES, \
+ (slice_) += ((subslice_) == 0)) \
+ for_each_if((instdone_has_slice(dev_priv_, sseu_, slice_)) && \
+ (instdone_has_subslice(dev_priv_, sseu_, slice_, \
+ subslice_)))
-:64: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'sseu_' - possible side-effects?
#64: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:586:
+#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
+ for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
+ (subslice_) = ((subslice_) + 1) % I915_MAX_SUBSLICES, \
+ (slice_) += ((subslice_) == 0)) \
+ for_each_if((instdone_has_slice(dev_priv_, sseu_, slice_)) && \
+ (instdone_has_subslice(dev_priv_, sseu_, slice_, \
+ subslice_)))
-:64: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'slice_' - possible side-effects?
#64: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:586:
+#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
+ for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
+ (subslice_) = ((subslice_) + 1) % I915_MAX_SUBSLICES, \
+ (slice_) += ((subslice_) == 0)) \
+ for_each_if((instdone_has_slice(dev_priv_, sseu_, slice_)) && \
+ (instdone_has_subslice(dev_priv_, sseu_, slice_, \
+ subslice_)))
-:64: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'subslice_' - possible side-effects?
#64: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:586:
+#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
+ for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
+ (subslice_) = ((subslice_) + 1) % I915_MAX_SUBSLICES, \
+ (slice_) += ((subslice_) == 0)) \
+ for_each_if((instdone_has_slice(dev_priv_, sseu_, slice_)) && \
+ (instdone_has_subslice(dev_priv_, sseu_, slice_, \
+ subslice_)))
total: 0 errors, 0 warnings, 5 checks, 105 lines checked
c2a6acd59196 drm/i915: Add new function to copy subslices for a slice
cd00917506db drm/i915: Expand subslice mask
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* ✓ Fi.CI.BAT: success for Refactor to expand subslice mask (rev 2)
2019-08-22 18:32 [PATCH 00/11] Refactor to expand subslice mask (rev 2) Stuart Summers
` (11 preceding siblings ...)
2019-08-22 18:45 ` ✗ Fi.CI.CHECKPATCH: warning for Refactor to expand subslice mask (rev 2) Patchwork
@ 2019-08-22 19:10 ` Patchwork
2019-08-23 13:44 ` ✗ Fi.CI.IGT: failure " Patchwork
13 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2019-08-22 19:10 UTC (permalink / raw)
To: Stuart Summers; +Cc: intel-gfx
== Series Details ==
Series: Refactor to expand subslice mask (rev 2)
URL : https://patchwork.freedesktop.org/series/65639/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6767 -> Patchwork_14146
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14146/
Known issues
------------
Here are the changes found in Patchwork_14146 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@prime_self_import@basic-llseek-bad:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6767/fi-icl-u3/igt@prime_self_import@basic-llseek-bad.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14146/fi-icl-u3/igt@prime_self_import@basic-llseek-bad.html
#### Possible fixes ####
* igt@core_auth@basic-auth:
- fi-icl-u3: [DMESG-WARN][3] ([fdo#107724]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6767/fi-icl-u3/igt@core_auth@basic-auth.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14146/fi-icl-u3/igt@core_auth@basic-auth.html
* igt@gem_ctx_switch@legacy-render:
- fi-bxt-dsi: [INCOMPLETE][5] ([fdo#103927]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6767/fi-bxt-dsi/igt@gem_ctx_switch@legacy-render.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14146/fi-bxt-dsi/igt@gem_ctx_switch@legacy-render.html
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
Participating hosts (55 -> 47)
------------------------------
Missing (8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-apl-guc fi-icl-y fi-byt-clapper
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6767 -> Patchwork_14146
CI-20190529: 20190529
CI_DRM_6767: 3e978f97d4682186cc9734adbe834865e5eb9aca @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5148: 50390dd7adaccae21cafa85b866c17606cec94c3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14146: cd00917506db1bef04a8d727602b170f51a79e58 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
cd00917506db drm/i915: Expand subslice mask
c2a6acd59196 drm/i915: Add new function to copy subslices for a slice
27f2df7c0217 drm/i915: Refactor instdone loops on new subslice functions
e5926395d481 drm/i915: Add function to determine if a slice has a subslice
e59b1027cb44 drm/i915: Use subslice stride to set subslices for a given slice
cebfb11acc33 drm/i915: Add function to set subslices
58829bc19d44 drm/i915: Use local variables for subslice_mask for device info
a1a0c0a580df drm/i915: Add EU stride runtime parameter
0c045a5315e1 drm/i915: Add subslice stride runtime parameter
0771e1cc9fe8 drm/i915: Add function to set SSEU info per platform
feeaef8cfa8b drm/i915: Use variable for debugfs device status
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14146/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 06/11] drm/i915: Add function to set subslices
2019-08-22 18:32 ` [PATCH 06/11] drm/i915: Add function to set subslices Stuart Summers
@ 2019-08-22 22:39 ` Chris Wilson
0 siblings, 0 replies; 22+ messages in thread
From: Chris Wilson @ 2019-08-22 22:39 UTC (permalink / raw)
To: Stuart Summers, intel-gfx
Quoting Stuart Summers (2019-08-22 19:32:08)
> Add a new function to set a set of subslices for a given
> slice.
>
> v2: Fix typo in subslice_mask assignment
>
> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Simple enough for even me to understand,
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 07/11] drm/i915: Use subslice stride to set subslices for a given slice
2019-08-22 18:32 ` [PATCH 07/11] drm/i915: Use subslice stride to set subslices for a given slice Stuart Summers
@ 2019-08-22 22:43 ` Chris Wilson
2019-08-23 15:59 ` Summers, Stuart
0 siblings, 1 reply; 22+ messages in thread
From: Chris Wilson @ 2019-08-22 22:43 UTC (permalink / raw)
To: Stuart Summers, intel-gfx
Quoting Stuart Summers (2019-08-22 19:32:09)
> Add a subslice stride calculation when setting subslices. This
> aligns more closely with the userspace expectation of the subslice
> mask structure.
>
> v2: Use local variable for subslice_mask on HSW and
> clean up a few other subslice_mask local variable
> changes
> v3: Add GEM_BUG_ON for ss_stride to prevent array overflow (Chris)
> Split main set function and refactors in intel_device_info.c
> into separate patches (Chris)
> v4: Reduce ss_stride size check when setting subslices per slice
> based on actual expected max stride (Chris)
> Move that GEM_BUG_ON check for the ss_stride out to the patch
> which adds the ss_stride
>
> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_sseu.c | 8 ++++++--
> drivers/gpu/drm/i915/gt/intel_sseu.h | 2 +-
> 2 files changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
> index 3a5db0dbac72..a0d32270248c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.c
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
> @@ -33,9 +33,13 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
> }
>
> void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
> - u8 ss_mask)
> + u32 ss_mask)
> {
> - sseu->subslice_mask[slice] = ss_mask;
> + int i, offset = slice * sseu->ss_stride;
> +
> + for (i = 0; i < sseu->ss_stride; i++)
> + sseu->subslice_mask[offset + i] =
> + (ss_mask >> (BITS_PER_BYTE * i)) & 0xff;
Is it not
memcpy(&sseu->sublice_mask[offset], &ss_mask, sseu->ss_stride);
?
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* ✗ Fi.CI.IGT: failure for Refactor to expand subslice mask (rev 2)
2019-08-22 18:32 [PATCH 00/11] Refactor to expand subslice mask (rev 2) Stuart Summers
` (12 preceding siblings ...)
2019-08-22 19:10 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-08-23 13:44 ` Patchwork
13 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2019-08-23 13:44 UTC (permalink / raw)
To: Summers, Stuart; +Cc: intel-gfx
== Series Details ==
Series: Refactor to expand subslice mask (rev 2)
URL : https://patchwork.freedesktop.org/series/65639/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6767_full -> Patchwork_14146_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_14146_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14146_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_14146_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_userptr_blits@create-destroy-sync:
- shard-skl: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6767/shard-skl8/igt@gem_userptr_blits@create-destroy-sync.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14146/shard-skl3/igt@gem_userptr_blits@create-destroy-sync.html
Known issues
------------
Here are the changes found in Patchwork_14146_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_schedule@independent-bsd2:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276]) +15 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6767/shard-iclb2/igt@gem_exec_schedule@independent-bsd2.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14146/shard-iclb6/igt@gem_exec_schedule@independent-bsd2.html
* igt@gem_exec_schedule@preempt-queue-bsd:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#111325]) +2 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6767/shard-iclb6/igt@gem_exec_schedule@preempt-queue-bsd.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14146/shard-iclb1/igt@gem_exec_schedule@preempt-queue-bsd.html
* igt@gem_tiled_swapping@non-threaded:
- shard-apl: [PASS][7] -> [INCOMPLETE][8] ([fdo#103927] / [fdo#108686])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6767/shard-apl5/igt@gem_tiled_swapping@non-threaded.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14146/shard-apl4/igt@gem_tiled_swapping@non-threaded.html
* igt@i915_pm_rps@waitboost:
- shard-iclb: [PASS][9] -> [INCOMPLETE][10] ([fdo#107713])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6767/shard-iclb6/igt@i915_pm_rps@waitboost.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14146/shard-iclb7/igt@i915_pm_rps@waitboost.html
* igt@kms_busy@basic-modeset-a:
- shard-apl: [PASS][11] -> [INCOMPLETE][12] ([fdo#103927]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6767/shard-apl5/igt@kms_busy@basic-modeset-a.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14146/shard-apl4/igt@kms_busy@basic-modeset-a.html
* igt@kms_flip@plain-flip-ts-check:
- shard-skl: [PASS][13] -> [FAIL][14] ([fdo#100368])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6767/shard-skl8/igt@kms_flip@plain-flip-ts-check.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14146/shard-skl5/igt@kms_flip@plain-flip-ts-check.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-apl: [PASS][15] -> [DMESG-WARN][16] ([fdo#108566]) +2 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6767/shard-apl6/igt@kms_frontbuffer_tracking@fbc-suspend.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14146/shard-apl1/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-msflip-blt:
- shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103167]) +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6767/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-msflip-blt.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14146/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-msflip-blt.html
* igt@kms_psr@psr2_suspend:
- shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +2 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6767/shard-iclb2/igt@kms_psr@psr2_suspend.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14146/shard-iclb6/igt@kms_psr@psr2_suspend.html
#### Possible fixes ####
* igt@gem_ctx_isolation@vcs0-s3:
- shard-skl: [INCOMPLETE][21] ([fdo#104108]) -> [PASS][22] +1 similar issue
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6767/shard-skl5/igt@gem_ctx_isolation@vcs0-s3.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14146/shard-skl10/igt@gem_ctx_isolation@vcs0-s3.html
* igt@gem_exec_schedule@preempt-queue-bsd1:
- shard-iclb: [SKIP][23] ([fdo#109276]) -> [PASS][24] +16 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6767/shard-iclb8/igt@gem_exec_schedule@preempt-queue-bsd1.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14146/shard-iclb2/igt@gem_exec_schedule@preempt-queue-bsd1.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [SKIP][25] ([fdo#111325]) -> [PASS][26] +4 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6767/shard-iclb4/igt@gem_exec_schedule@preemptive-hang-bsd.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14146/shard-iclb5/igt@gem_exec_schedule@preemptive-hang-bsd.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: [DMESG-WARN][27] ([fdo#108566]) -> [PASS][28] +5 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6767/shard-apl4/igt@i915_suspend@sysfs-reader.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14146/shard-apl7/igt@i915_suspend@sysfs-reader.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
- shard-hsw: [FAIL][29] ([fdo#105767]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6767/shard-hsw2/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14146/shard-hsw6/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
* igt@kms_flip@flip-vs-suspend:
- shard-skl: [INCOMPLETE][31] ([fdo#109507]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6767/shard-skl4/igt@kms_flip@flip-vs-suspend.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14146/shard-skl1/igt@kms_flip@flip-vs-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-render:
- shard-iclb: [FAIL][33] ([fdo#103167]) -> [PASS][34] +7 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6767/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-render.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14146/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-render.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [FAIL][35] ([fdo#108145] / [fdo#110403]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6767/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14146/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: [FAIL][37] ([fdo#103166]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6767/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-x.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14146/shard-iclb4/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: [SKIP][39] ([fdo#109441]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6767/shard-iclb7/igt@kms_psr@psr2_sprite_mmap_gtt.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14146/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@kms_setmode@basic:
- shard-hsw: [FAIL][41] ([fdo#99912]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6767/shard-hsw8/igt@kms_setmode@basic.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14146/shard-hsw1/igt@kms_setmode@basic.html
#### Warnings ####
* igt@gem_ctx_isolation@vcs1-nonpriv:
- shard-iclb: [SKIP][43] ([fdo#109276]) -> [FAIL][44] ([fdo#111329])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6767/shard-iclb6/igt@gem_ctx_isolation@vcs1-nonpriv.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14146/shard-iclb4/igt@gem_ctx_isolation@vcs1-nonpriv.html
* igt@gem_mocs_settings@mocs-isolation-bsd2:
- shard-iclb: [FAIL][45] ([fdo#111330]) -> [SKIP][46] ([fdo#109276])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6767/shard-iclb2/igt@gem_mocs_settings@mocs-isolation-bsd2.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14146/shard-iclb5/igt@gem_mocs_settings@mocs-isolation-bsd2.html
* igt@gem_mocs_settings@mocs-reset-bsd2:
- shard-iclb: [SKIP][47] ([fdo#109276]) -> [FAIL][48] ([fdo#111330])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6767/shard-iclb6/igt@gem_mocs_settings@mocs-reset-bsd2.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14146/shard-iclb2/igt@gem_mocs_settings@mocs-reset-bsd2.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [DMESG-WARN][49] ([fdo#107724]) -> [SKIP][50] ([fdo#109349])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6767/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14146/shard-iclb5/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105767]: https://bugs.freedesktop.org/show_bug.cgi?id=105767
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
[fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
[fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
[fdo#111329]: https://bugs.freedesktop.org/show_bug.cgi?id=111329
[fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6767 -> Patchwork_14146
CI-20190529: 20190529
CI_DRM_6767: 3e978f97d4682186cc9734adbe834865e5eb9aca @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5148: 50390dd7adaccae21cafa85b866c17606cec94c3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14146: cd00917506db1bef04a8d727602b170f51a79e58 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14146/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 07/11] drm/i915: Use subslice stride to set subslices for a given slice
2019-08-22 22:43 ` Chris Wilson
@ 2019-08-23 15:59 ` Summers, Stuart
0 siblings, 0 replies; 22+ messages in thread
From: Summers, Stuart @ 2019-08-23 15:59 UTC (permalink / raw)
To: intel-gfx, chris
[-- Attachment #1.1: Type: text/plain, Size: 2030 bytes --]
On Thu, 2019-08-22 at 23:43 +0100, Chris Wilson wrote:
> Quoting Stuart Summers (2019-08-22 19:32:09)
> > Add a subslice stride calculation when setting subslices. This
> > aligns more closely with the userspace expectation of the subslice
> > mask structure.
> >
> > v2: Use local variable for subslice_mask on HSW and
> > clean up a few other subslice_mask local variable
> > changes
> > v3: Add GEM_BUG_ON for ss_stride to prevent array overflow (Chris)
> > Split main set function and refactors in intel_device_info.c
> > into separate patches (Chris)
> > v4: Reduce ss_stride size check when setting subslices per slice
> > based on actual expected max stride (Chris)
> > Move that GEM_BUG_ON check for the ss_stride out to the patch
> > which adds the ss_stride
> >
> > Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/intel_sseu.c | 8 ++++++--
> > drivers/gpu/drm/i915/gt/intel_sseu.h | 2 +-
> > 2 files changed, 7 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c
> > b/drivers/gpu/drm/i915/gt/intel_sseu.c
> > index 3a5db0dbac72..a0d32270248c 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_sseu.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
> > @@ -33,9 +33,13 @@ intel_sseu_subslice_total(const struct
> > sseu_dev_info *sseu)
> > }
> >
> > void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int
> > slice,
> > - u8 ss_mask)
> > + u32 ss_mask)
> > {
> > - sseu->subslice_mask[slice] = ss_mask;
> > + int i, offset = slice * sseu->ss_stride;
> > +
> > + for (i = 0; i < sseu->ss_stride; i++)
> > + sseu->subslice_mask[offset + i] =
> > + (ss_mask >> (BITS_PER_BYTE * i)) & 0xff;
>
> Is it not
>
> memcpy(&sseu->sublice_mask[offset], &ss_mask, sseu->ss_stride);
True.. update coming shortly.
Thanks,
Stuart
> ?
> -Chris
[-- Attachment #1.2: smime.p7s --]
[-- Type: application/x-pkcs7-signature, Size: 3270 bytes --]
[-- Attachment #2: Type: text/plain, Size: 159 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* ✗ Fi.CI.IGT: failure for Refactor to expand subslice mask (rev 2)
2019-08-07 16:58 [PATCH 0/9] " Stuart Summers
@ 2019-08-08 5:59 ` Patchwork
0 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2019-08-08 5:59 UTC (permalink / raw)
To: Stuart Summers; +Cc: intel-gfx
== Series Details ==
Series: Refactor to expand subslice mask (rev 2)
URL : https://patchwork.freedesktop.org/series/64858/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6649_full -> Patchwork_13905_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_13905_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_13905_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_13905_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_schedule@preempt-bsd:
- shard-iclb: [PASS][1] -> [SKIP][2] +3 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6649/shard-iclb8/igt@gem_exec_schedule@preempt-bsd.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13905/shard-iclb2/igt@gem_exec_schedule@preempt-bsd.html
#### Warnings ####
* igt@gem_ctx_isolation@vcs1-nonpriv:
- shard-iclb: [SKIP][3] ([fdo#109276]) -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6649/shard-iclb8/igt@gem_ctx_isolation@vcs1-nonpriv.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13905/shard-iclb2/igt@gem_ctx_isolation@vcs1-nonpriv.html
Known issues
------------
Here are the changes found in Patchwork_13905_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_schedule@preempt-contexts-bsd2:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276]) +12 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6649/shard-iclb2/igt@gem_exec_schedule@preempt-contexts-bsd2.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13905/shard-iclb6/igt@gem_exec_schedule@preempt-contexts-bsd2.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-skl: [PASS][7] -> [INCOMPLETE][8] ([fdo#110741]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6649/shard-skl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13905/shard-skl2/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
- shard-apl: [PASS][9] -> [DMESG-WARN][10] ([fdo#108566]) +2 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6649/shard-apl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13905/shard-apl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_legacy@cursora-vs-flipa-atomic:
- shard-iclb: [PASS][11] -> [INCOMPLETE][12] ([fdo#107713]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6649/shard-iclb5/igt@kms_cursor_legacy@cursora-vs-flipa-atomic.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13905/shard-iclb7/igt@kms_cursor_legacy@cursora-vs-flipa-atomic.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: [PASS][13] -> [FAIL][14] ([fdo#105363])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6649/shard-skl5/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13905/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_frontbuffer_tracking@fbcpsr-suspend:
- shard-skl: [PASS][15] -> [INCOMPLETE][16] ([fdo#104108] / [fdo#106978])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6649/shard-skl6/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13905/shard-skl8/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6649/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13905/shard-skl5/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_plane_lowres@pipe-a-tiling-y:
- shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103166])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6649/shard-iclb2/igt@kms_plane_lowres@pipe-a-tiling-y.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13905/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-y.html
* igt@kms_psr2_su@page_flip:
- shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109642] / [fdo#111068])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6649/shard-iclb2/igt@kms_psr2_su@page_flip.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13905/shard-iclb1/igt@kms_psr2_su@page_flip.html
* igt@kms_psr@psr2_primary_blt:
- shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441]) +2 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6649/shard-iclb2/igt@kms_psr@psr2_primary_blt.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13905/shard-iclb6/igt@kms_psr@psr2_primary_blt.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][25] -> [FAIL][26] ([fdo#99912])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6649/shard-apl6/igt@kms_setmode@basic.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13905/shard-apl3/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-kbl: [PASS][27] -> [INCOMPLETE][28] ([fdo#103665])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6649/shard-kbl6/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13905/shard-kbl6/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
* igt@perf@blocking:
- shard-skl: [PASS][29] -> [FAIL][30] ([fdo#110728])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6649/shard-skl7/igt@perf@blocking.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13905/shard-skl2/igt@perf@blocking.html
#### Possible fixes ####
* igt@gem_exec_schedule@deep-bsd:
- shard-iclb: [INCOMPLETE][31] ([fdo#107713]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6649/shard-iclb7/igt@gem_exec_schedule@deep-bsd.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13905/shard-iclb6/igt@gem_exec_schedule@deep-bsd.html
* igt@gem_exec_schedule@preempt-queue-bsd2:
- shard-iclb: [SKIP][33] ([fdo#109276]) -> [PASS][34] +9 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6649/shard-iclb8/igt@gem_exec_schedule@preempt-queue-bsd2.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13905/shard-iclb2/igt@gem_exec_schedule@preempt-queue-bsd2.html
* igt@gem_exec_schedule@reorder-wide-bsd:
- shard-iclb: [SKIP][35] -> [PASS][36] +2 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6649/shard-iclb2/igt@gem_exec_schedule@reorder-wide-bsd.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13905/shard-iclb8/igt@gem_exec_schedule@reorder-wide-bsd.html
* igt@gem_exec_schedule@semaphore-noskip:
- shard-iclb: [FAIL][37] ([fdo#110946]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6649/shard-iclb2/igt@gem_exec_schedule@semaphore-noskip.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13905/shard-iclb8/igt@gem_exec_schedule@semaphore-noskip.html
* igt@gem_softpin@noreloc-s3:
- shard-skl: [INCOMPLETE][39] ([fdo#104108]) -> [PASS][40] +1 similar issue
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6649/shard-skl3/igt@gem_softpin@noreloc-s3.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13905/shard-skl4/igt@gem_softpin@noreloc-s3.html
* igt@gem_tiled_swapping@non-threaded:
- shard-kbl: [DMESG-WARN][41] ([fdo#108686]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6649/shard-kbl2/igt@gem_tiled_swapping@non-threaded.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13905/shard-kbl7/igt@gem_tiled_swapping@non-threaded.html
* igt@i915_pm_rps@reset:
- shard-kbl: [FAIL][43] ([fdo#102250]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6649/shard-kbl4/igt@i915_pm_rps@reset.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13905/shard-kbl1/igt@i915_pm_rps@reset.html
* igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing:
- shard-kbl: [FAIL][45] -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6649/shard-kbl4/igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13905/shard-kbl1/igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing.html
* igt@kms_cursor_crc@pipe-a-cursor-256x256-random:
- shard-apl: [INCOMPLETE][47] ([fdo#103927]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6649/shard-apl5/igt@kms_cursor_crc@pipe-a-cursor-256x256-random.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13905/shard-apl2/igt@kms_cursor_crc@pipe-a-cursor-256x256-random.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-skl: [INCOMPLETE][49] ([fdo#110741]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6649/shard-skl1/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13905/shard-skl8/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_flip@2x-modeset-vs-vblank-race-interruptible:
- shard-glk: [FAIL][51] ([fdo#103060]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6649/shard-glk1/igt@kms_flip@2x-modeset-vs-vblank-race-interruptible.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13905/shard-glk2/igt@kms_flip@2x-modeset-vs-vblank-race-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [FAIL][53] ([fdo#105363]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6649/shard-skl3/igt@kms_flip@flip-vs-expired-vblank.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13905/shard-skl10/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_flip@plain-flip-fb-recreate:
- shard-skl: [FAIL][55] ([fdo#100368]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6649/shard-skl6/igt@kms_flip@plain-flip-fb-recreate.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13905/shard-skl8/igt@kms_flip@plain-flip-fb-recreate.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
- shard-iclb: [FAIL][57] ([fdo#103167]) -> [PASS][58] +3 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6649/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13905/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
- shard-apl: [DMESG-WARN][59] ([fdo#108566]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6649/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13905/shard-apl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [SKIP][61] ([fdo#109441]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6649/shard-iclb1/igt@kms_psr@psr2_no_drrs.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13905/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
* igt@kms_setmode@basic:
- shard-kbl: [FAIL][63] ([fdo#99912]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6649/shard-kbl1/igt@kms_setmode@basic.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13905/shard-kbl3/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: [DMESG-WARN][65] ([fdo#108566]) -> [PASS][66] +4 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6649/shard-kbl3/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13905/shard-kbl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
#### Warnings ####
* igt@gem_ctx_shared@exec-single-timeline-bsd2:
- shard-iclb: [FAIL][67] -> [SKIP][68] ([fdo#109276])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6649/shard-iclb4/igt@gem_ctx_shared@exec-single-timeline-bsd2.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13905/shard-iclb3/igt@gem_ctx_shared@exec-single-timeline-bsd2.html
* igt@gem_exec_schedule@independent-bsd1:
- shard-iclb: [SKIP][69] ([fdo#109276]) -> [FAIL][70] ([fdo#110946])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6649/shard-iclb6/igt@gem_exec_schedule@independent-bsd1.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13905/shard-iclb4/igt@gem_exec_schedule@independent-bsd1.html
[fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
[fdo#102250]: https://bugs.freedesktop.org/show_bug.cgi?id=102250
[fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
[fdo#110741]: https://bugs.freedesktop.org/show_bug.cgi?id=110741
[fdo#110946]: https://bugs.freedesktop.org/show_bug.cgi?id=110946
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6649 -> Patchwork_13905
CI-20190529: 20190529
CI_DRM_6649: 47b76298b3b6a5240d37f4e3f0182a2d47069d42 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5125: 35d81d01b1599b4bc4df0e09e25f6f531eed4f8a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13905: f0790c8c27fcd52653cf78d0e996a5aac975b425 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13905/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: ✗ Fi.CI.IGT: failure for Refactor to expand subslice mask (rev 2)
2019-07-24 21:01 ` ✗ Fi.CI.IGT: failure for " Patchwork
@ 2019-07-24 21:08 ` Summers, Stuart
0 siblings, 0 replies; 22+ messages in thread
From: Summers, Stuart @ 2019-07-24 21:08 UTC (permalink / raw)
To: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 12400 bytes --]
On Wed, 2019-07-24 at 21:01 +0000, Patchwork wrote:
> == Series Details ==
>
> Series: Refactor to expand subslice mask (rev 2)
> URL : https://patchwork.freedesktop.org/series/64188/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_6545_full -> Patchwork_13739_full
> ====================================================
>
> Summary
> -------
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_13739_full absolutely
> need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the
> changes
> introduced in Patchwork_13739_full, please notify your bug team to
> allow them
> to document this new failure mode, which will reduce false
> positives in CI.
>
>
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in
> Patchwork_13739_full:
>
> ### IGT changes ###
>
> #### Possible regressions ####
>
> * igt@i915_query@query-topology-matches-eu-total:
> - shard-hsw: [PASS][1] -> [FAIL][2] +3 similar issues
> [1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-hsw7/igt@i915_query@query-topology-matches-eu-total.html
> [2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-hsw1/igt@i915_query@query-topology-matches-eu-total.html
Looks like this series is causing a regression on HSW. I'll fix this
issue before posting the next revision. For now, please hold off on
review.
Thanks,
Stuart
>
>
> Known issues
> ------------
>
> Here are the changes found in Patchwork_13739_full that come from
> known issues:
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@gem_ctx_isolation@rcs0-s3:
> - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108566])
> [3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-apl8/igt@gem_ctx_isolation@rcs0-s3.html
> [4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-apl3/igt@gem_ctx_isolation@rcs0-s3.html
>
> * igt@gem_tiled_swapping@non-threaded:
> - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([fdo#108686])
> [5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-apl5/igt@gem_tiled_swapping@non-threaded.html
> [6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-apl7/igt@gem_tiled_swapping@non-threaded.html
>
> * igt@i915_pm_rc6_residency@rc6-accuracy:
> - shard-kbl: [PASS][7] -> [SKIP][8] ([fdo#109271])
> [7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-kbl1/igt@i915_pm_rc6_residency@rc6-accuracy.html
> [8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-kbl1/igt@i915_pm_rc6_residency@rc6-accuracy.html
>
> * igt@i915_query@query-topology-coherent-slice-mask:
> - shard-hsw: [PASS][9] -> [SKIP][10] ([fdo#109271])
> [9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-hsw4/igt@i915_query@query-topology-coherent-slice-mask.html
> [10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-hsw5/igt@i915_query@query-topology-coherent-slice-mask.html
>
> * igt@kms_cursor_legacy@cursor-vs-flip-toggle:
> - shard-hsw: [PASS][11] -> [FAIL][12] ([fdo#103355])
> [11]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-hsw1/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
> [12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-hsw6/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
>
> * igt@kms_flip@flip-vs-expired-vblank-interruptible:
> - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#105363])
> [13]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-skl10/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
> [14]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-skl8/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
>
> * igt@kms_flip@flip-vs-suspend-interruptible:
> - shard-kbl: [PASS][15] -> [DMESG-WARN][16]
> ([fdo#108566]) +2 similar issues
> [15]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible.html
> [16]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible.html
>
> * igt@kms_flip_tiling@flip-to-x-tiled:
> - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108134])
> [17]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-skl10/igt@kms_flip_tiling@flip-to-x-tiled.html
> [18]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-skl3/igt@kms_flip_tiling@flip-to-x-tiled.html
>
> * igt@kms
> _frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render:
> - shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103167]) +7
> similar issues
> [19]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html
> [20]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html
>
> * igt@kms_frontbuffer_tracking@fbc-suspend:
> - shard-skl: [PASS][21] -> [INCOMPLETE][22]
> ([fdo#104108])
> [21]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-skl6/igt@kms_frontbuffer_tracking@fbc-suspend.html
> [22]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-skl3/igt@kms_frontbuffer_tracking@fbc-suspend.html
>
> * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
> - shard-kbl: [PASS][23] -> [INCOMPLETE][24]
> ([fdo#103665])
> [23]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-kbl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
> [24]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-kbl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
>
> * igt@kms_psr2_su@page_flip:
> - shard-iclb: [PASS][25] -> [SKIP][26] ([fdo#109642] /
> [fdo#111068])
> [25]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb2/igt@kms_psr2_su@page_flip.html
> [26]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-iclb4/igt@kms_psr2_su@page_flip.html
>
> * igt@perf_pmu@init-busy-vcs2:
> - shard-iclb: [PASS][27] -> [INCOMPLETE][28]
> ([fdo#107713])
> [27]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb2/igt@perf_pmu@init-busy-vcs2.html
> [28]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-iclb4/igt@perf_pmu@init-busy-vcs2.html
>
>
> #### Possible fixes ####
>
> * igt@gem_exec_balancer@smoke:
> - shard-iclb: [SKIP][29] ([fdo#110854]) -> [PASS][30]
> [29]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb6/igt@gem_exec_balancer@smoke.html
> [30]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-iclb4/igt@gem_exec_balancer@smoke.html
>
> * igt@i915_selftest@live_hangcheck:
> - shard-iclb: [INCOMPLETE][31] ([fdo#107713] /
> [fdo#108569]) -> [PASS][32]
> [31]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb6/igt@i915_selftest@live_hangcheck.html
> [32]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-iclb6/igt@i915_selftest@live_hangcheck.html
>
> * igt@kms_flip@flip-vs-expired-vblank:
> - shard-skl: [FAIL][33] ([fdo#105363]) -> [PASS][34]
> [33]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-skl9/igt@kms_flip@flip-vs-expired-vblank.html
> [34]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-skl4/igt@kms_flip@flip-vs-expired-vblank.html
>
> * igt@kms_flip@flip-vs-suspend-interruptible:
> - shard-apl: [DMESG-WARN][35] ([fdo#108566]) ->
> [PASS][36] +4 similar issues
> [35]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-apl4/igt@kms_flip@flip-vs-suspend-interruptible.html
> [36]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible.html
>
> * igt@kms
> _frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
> - shard-iclb: [FAIL][37] ([fdo#103167]) -> [PASS][38] +3
> similar issues
> [37]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
> [38]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
>
> * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
> - shard-skl: [FAIL][39] ([fdo#108145]) -> [PASS][40] +1
> similar issue
> [39]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
> [40]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
>
> * igt@kms_psr@cursor_plane_onoff:
> - shard-iclb: [INCOMPLETE][41] ([fdo#107713]) ->
> [PASS][42]
> [41]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb1/igt@kms_psr@cursor_plane_onoff.html
> [42]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-iclb1/igt@kms_psr@cursor_plane_onoff.html
>
> * igt@kms_psr@psr2_primary_mmap_gtt:
> - shard-iclb: [SKIP][43] ([fdo#109441]) -> [PASS][44] +2
> similar issues
> [43]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb4/igt@kms_psr@psr2_primary_mmap_gtt.html
> [44]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html
>
>
> #### Warnings ####
>
> * igt@gem_tiled_swapping@non-threaded:
> - shard-skl: [FAIL][45] ([fdo#108686]) -> [SKIP][46]
> ([fdo#109271])
> [45]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-skl8/igt@gem_tiled_swapping@non-threaded.html
> [46]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-skl5/igt@gem_tiled_swapping@non-threaded.html
>
>
> [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
> [fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355
> [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
> [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
> [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
> [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
> [fdo#108134]: https://bugs.freedesktop.org/show_bug.cgi?id=108134
> [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
> [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
> [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
> [fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
> [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
> [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
> [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
> [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
> [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
>
>
> Participating hosts (9 -> 9)
> ------------------------------
>
> No changes in participating hosts
>
>
> Build changes
> -------------
>
> * CI: CI-20190529 -> None
> * Linux: CI_DRM_6545 -> Patchwork_13739
>
> CI-20190529: 20190529
> CI_DRM_6545: a6efe73f1e086c7935d56b08342f9e1c5565fcf3 @
> git://anongit.freedesktop.org/gfx-ci/linux
> IGT_5109: e5fd509e16ec649436be31f38eaa5b85cb7f72f1 @
> git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
> Patchwork_13739: 6c805dfa2b2aa200593b17947e683a2781992c7a @
> git://anongit.freedesktop.org/gfx-ci/linux
> piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
> git://anongit.freedesktop.org/piglit
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* ✗ Fi.CI.IGT: failure for Refactor to expand subslice mask (rev 2)
2019-07-24 17:12 [PATCH 0/9] " Stuart Summers
@ 2019-07-24 21:01 ` Patchwork
2019-07-24 21:08 ` Summers, Stuart
0 siblings, 1 reply; 22+ messages in thread
From: Patchwork @ 2019-07-24 21:01 UTC (permalink / raw)
To: Stuart Summers; +Cc: intel-gfx
== Series Details ==
Series: Refactor to expand subslice mask (rev 2)
URL : https://patchwork.freedesktop.org/series/64188/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6545_full -> Patchwork_13739_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_13739_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_13739_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_13739_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_query@query-topology-matches-eu-total:
- shard-hsw: [PASS][1] -> [FAIL][2] +3 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-hsw7/igt@i915_query@query-topology-matches-eu-total.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-hsw1/igt@i915_query@query-topology-matches-eu-total.html
Known issues
------------
Here are the changes found in Patchwork_13739_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@rcs0-s3:
- shard-apl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108566])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-apl8/igt@gem_ctx_isolation@rcs0-s3.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-apl3/igt@gem_ctx_isolation@rcs0-s3.html
* igt@gem_tiled_swapping@non-threaded:
- shard-apl: [PASS][5] -> [DMESG-WARN][6] ([fdo#108686])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-apl5/igt@gem_tiled_swapping@non-threaded.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-apl7/igt@gem_tiled_swapping@non-threaded.html
* igt@i915_pm_rc6_residency@rc6-accuracy:
- shard-kbl: [PASS][7] -> [SKIP][8] ([fdo#109271])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-kbl1/igt@i915_pm_rc6_residency@rc6-accuracy.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-kbl1/igt@i915_pm_rc6_residency@rc6-accuracy.html
* igt@i915_query@query-topology-coherent-slice-mask:
- shard-hsw: [PASS][9] -> [SKIP][10] ([fdo#109271])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-hsw4/igt@i915_query@query-topology-coherent-slice-mask.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-hsw5/igt@i915_query@query-topology-coherent-slice-mask.html
* igt@kms_cursor_legacy@cursor-vs-flip-toggle:
- shard-hsw: [PASS][11] -> [FAIL][12] ([fdo#103355])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-hsw1/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-hsw6/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: [PASS][13] -> [FAIL][14] ([fdo#105363])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-skl10/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-skl8/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([fdo#108566]) +2 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_flip_tiling@flip-to-x-tiled:
- shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108134])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-skl10/igt@kms_flip_tiling@flip-to-x-tiled.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-skl3/igt@kms_flip_tiling@flip-to-x-tiled.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render:
- shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103167]) +7 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-skl: [PASS][21] -> [INCOMPLETE][22] ([fdo#104108])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-skl6/igt@kms_frontbuffer_tracking@fbc-suspend.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-skl3/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-kbl: [PASS][23] -> [INCOMPLETE][24] ([fdo#103665])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-kbl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-kbl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_psr2_su@page_flip:
- shard-iclb: [PASS][25] -> [SKIP][26] ([fdo#109642] / [fdo#111068])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb2/igt@kms_psr2_su@page_flip.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-iclb4/igt@kms_psr2_su@page_flip.html
* igt@perf_pmu@init-busy-vcs2:
- shard-iclb: [PASS][27] -> [INCOMPLETE][28] ([fdo#107713])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb2/igt@perf_pmu@init-busy-vcs2.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-iclb4/igt@perf_pmu@init-busy-vcs2.html
#### Possible fixes ####
* igt@gem_exec_balancer@smoke:
- shard-iclb: [SKIP][29] ([fdo#110854]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb6/igt@gem_exec_balancer@smoke.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-iclb4/igt@gem_exec_balancer@smoke.html
* igt@i915_selftest@live_hangcheck:
- shard-iclb: [INCOMPLETE][31] ([fdo#107713] / [fdo#108569]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb6/igt@i915_selftest@live_hangcheck.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-iclb6/igt@i915_selftest@live_hangcheck.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [FAIL][33] ([fdo#105363]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-skl9/igt@kms_flip@flip-vs-expired-vblank.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-skl4/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-apl: [DMESG-WARN][35] ([fdo#108566]) -> [PASS][36] +4 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-apl4/igt@kms_flip@flip-vs-suspend-interruptible.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
- shard-iclb: [FAIL][37] ([fdo#103167]) -> [PASS][38] +3 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [FAIL][39] ([fdo#108145]) -> [PASS][40] +1 similar issue
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_psr@cursor_plane_onoff:
- shard-iclb: [INCOMPLETE][41] ([fdo#107713]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb1/igt@kms_psr@cursor_plane_onoff.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-iclb1/igt@kms_psr@cursor_plane_onoff.html
* igt@kms_psr@psr2_primary_mmap_gtt:
- shard-iclb: [SKIP][43] ([fdo#109441]) -> [PASS][44] +2 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-iclb4/igt@kms_psr@psr2_primary_mmap_gtt.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html
#### Warnings ####
* igt@gem_tiled_swapping@non-threaded:
- shard-skl: [FAIL][45] ([fdo#108686]) -> [SKIP][46] ([fdo#109271])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6545/shard-skl8/igt@gem_tiled_swapping@non-threaded.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/shard-skl5/igt@gem_tiled_swapping@non-threaded.html
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108134]: https://bugs.freedesktop.org/show_bug.cgi?id=108134
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6545 -> Patchwork_13739
CI-20190529: 20190529
CI_DRM_6545: a6efe73f1e086c7935d56b08342f9e1c5565fcf3 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5109: e5fd509e16ec649436be31f38eaa5b85cb7f72f1 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13739: 6c805dfa2b2aa200593b17947e683a2781992c7a @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13739/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* ✗ Fi.CI.IGT: failure for Refactor to expand subslice mask (rev 2)
2019-07-23 15:49 [PATCH 0/9] " Stuart Summers
@ 2019-07-24 2:26 ` Patchwork
0 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2019-07-24 2:26 UTC (permalink / raw)
To: Summers, Stuart; +Cc: intel-gfx
== Series Details ==
Series: Refactor to expand subslice mask (rev 2)
URL : https://patchwork.freedesktop.org/series/64103/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6543_full -> Patchwork_13729_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_13729_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_13729_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_13729_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_pwrite@big-cpu-fbr:
- shard-glk: [PASS][1] -> [TIMEOUT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6543/shard-glk5/igt@gem_pwrite@big-cpu-fbr.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13729/shard-glk5/igt@gem_pwrite@big-cpu-fbr.html
* igt@i915_query@query-topology-matches-eu-total:
- shard-hsw: [PASS][3] -> [FAIL][4] +3 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6543/shard-hsw8/igt@i915_query@query-topology-matches-eu-total.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13729/shard-hsw8/igt@i915_query@query-topology-matches-eu-total.html
Known issues
------------
Here are the changes found in Patchwork_13729_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_flush@basic-wb-rw-default:
- shard-iclb: [PASS][5] -> [INCOMPLETE][6] ([fdo#107713]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6543/shard-iclb6/igt@gem_exec_flush@basic-wb-rw-default.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13729/shard-iclb7/igt@gem_exec_flush@basic-wb-rw-default.html
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [PASS][7] -> [DMESG-WARN][8] ([fdo#108566]) +2 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6543/shard-apl7/igt@gem_workarounds@suspend-resume-context.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13729/shard-apl3/igt@gem_workarounds@suspend-resume-context.html
* igt@i915_query@query-topology-coherent-slice-mask:
- shard-hsw: [PASS][9] -> [SKIP][10] ([fdo#109271])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6543/shard-hsw8/igt@i915_query@query-topology-coherent-slice-mask.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13729/shard-hsw7/igt@i915_query@query-topology-coherent-slice-mask.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([fdo#108566]) +4 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6543/shard-kbl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13729/shard-kbl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
- shard-glk: [PASS][13] -> [FAIL][14] ([fdo#106509] / [fdo#107409])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6543/shard-glk8/igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13729/shard-glk8/igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic.html
* igt@kms_flip@modeset-vs-vblank-race:
- shard-glk: [PASS][15] -> [FAIL][16] ([fdo#103060])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6543/shard-glk1/igt@kms_flip@modeset-vs-vblank-race.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13729/shard-glk3/igt@kms_flip@modeset-vs-vblank-race.html
* igt@kms_flip_tiling@flip-to-x-tiled:
- shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108134])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6543/shard-skl5/igt@kms_flip_tiling@flip-to-x-tiled.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13729/shard-skl10/igt@kms_flip_tiling@flip-to-x-tiled.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt:
- shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103167]) +5 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6543/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13729/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6543/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13729/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441]) +2 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6543/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13729/shard-iclb8/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_rotation_crc@multiplane-rotation:
- shard-glk: [PASS][25] -> [DMESG-FAIL][26] ([fdo#105763] / [fdo#106538])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6543/shard-glk7/igt@kms_rotation_crc@multiplane-rotation.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13729/shard-glk7/igt@kms_rotation_crc@multiplane-rotation.html
* igt@kms_setmode@basic:
- shard-kbl: [PASS][27] -> [FAIL][28] ([fdo#99912])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6543/shard-kbl6/igt@kms_setmode@basic.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13729/shard-kbl1/igt@kms_setmode@basic.html
* igt@perf_pmu@busy-double-start-vecs0:
- shard-hsw: [PASS][29] -> [INCOMPLETE][30] ([fdo#103540])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6543/shard-hsw7/igt@perf_pmu@busy-double-start-vecs0.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13729/shard-hsw5/igt@perf_pmu@busy-double-start-vecs0.html
#### Possible fixes ####
* igt@gem_ctx_isolation@bcs0-s3:
- shard-apl: [DMESG-WARN][31] ([fdo#108566]) -> [PASS][32] +2 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6543/shard-apl8/igt@gem_ctx_isolation@bcs0-s3.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13729/shard-apl2/igt@gem_ctx_isolation@bcs0-s3.html
* igt@i915_pm_rpm@gem-evict-pwrite:
- shard-iclb: [INCOMPLETE][33] ([fdo#107713] / [fdo#108840]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6543/shard-iclb7/igt@i915_pm_rpm@gem-evict-pwrite.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13729/shard-iclb4/igt@i915_pm_rpm@gem-evict-pwrite.html
* igt@i915_pm_rpm@i2c:
- shard-hsw: [FAIL][35] ([fdo#104097]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6543/shard-hsw5/igt@i915_pm_rpm@i2c.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13729/shard-hsw5/igt@i915_pm_rpm@i2c.html
* igt@kms_cursor_crc@pipe-c-cursor-64x21-random:
- shard-iclb: [INCOMPLETE][37] ([fdo#107713]) -> [PASS][38] +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6543/shard-iclb7/igt@kms_cursor_crc@pipe-c-cursor-64x21-random.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13729/shard-iclb3/igt@kms_cursor_crc@pipe-c-cursor-64x21-random.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-skl: [INCOMPLETE][39] ([fdo#110741]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6543/shard-skl10/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13729/shard-skl2/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
- shard-hsw: [FAIL][41] ([fdo#105767]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6543/shard-hsw6/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13729/shard-hsw8/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-glk: [FAIL][43] ([fdo#105363]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6543/shard-glk5/igt@kms_flip@flip-vs-expired-vblank.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13729/shard-glk5/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: [FAIL][45] ([fdo#105363]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6543/shard-skl3/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13729/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-suspend:
- shard-hsw: [INCOMPLETE][47] ([fdo#103540]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6543/shard-hsw4/igt@kms_flip@flip-vs-suspend.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13729/shard-hsw7/igt@kms_flip@flip-vs-suspend.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-iclb: [FAIL][49] ([fdo#103167]) -> [PASS][50] +5 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6543/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-suspend.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13729/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-kbl: [DMESG-WARN][51] ([fdo#108566]) -> [PASS][52] +3 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6543/shard-kbl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13729/shard-kbl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
- shard-skl: [INCOMPLETE][53] ([fdo#104108]) -> [PASS][54] +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6543/shard-skl5/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13729/shard-skl8/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [SKIP][55] ([fdo#109441]) -> [PASS][56] +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6543/shard-iclb7/igt@kms_psr@psr2_cursor_render.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13729/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
* igt@kms_setmode@basic:
- shard-apl: [FAIL][57] ([fdo#99912]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6543/shard-apl3/igt@kms_setmode@basic.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13729/shard-apl6/igt@kms_setmode@basic.html
* igt@perf@blocking:
- shard-skl: [FAIL][59] ([fdo#110728]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6543/shard-skl5/igt@perf@blocking.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13729/shard-skl10/igt@perf@blocking.html
* igt@perf_pmu@rc6:
- shard-kbl: [SKIP][61] ([fdo#109271]) -> [PASS][62] +1 similar issue
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6543/shard-kbl2/igt@perf_pmu@rc6.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13729/shard-kbl4/igt@perf_pmu@rc6.html
#### Warnings ####
* igt@gem_tiled_swapping@non-threaded:
- shard-skl: [SKIP][63] ([fdo#109271]) -> [FAIL][64] ([fdo#108686])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6543/shard-skl2/igt@gem_tiled_swapping@non-threaded.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13729/shard-skl9/igt@gem_tiled_swapping@non-threaded.html
[fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#104097]: https://bugs.freedesktop.org/show_bug.cgi?id=104097
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#105767]: https://bugs.freedesktop.org/show_bug.cgi?id=105767
[fdo#106509]: https://bugs.freedesktop.org/show_bug.cgi?id=106509
[fdo#106538]: https://bugs.freedesktop.org/show_bug.cgi?id=106538
[fdo#107409]: https://bugs.freedesktop.org/show_bug.cgi?id=107409
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108134]: https://bugs.freedesktop.org/show_bug.cgi?id=108134
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
[fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
[fdo#110741]: https://bugs.freedesktop.org/show_bug.cgi?id=110741
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6543 -> Patchwork_13729
CI-20190529: 20190529
CI_DRM_6543: ef1bb6d271fab3750ce23b548954df7b28da8ce7 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5109: e5fd509e16ec649436be31f38eaa5b85cb7f72f1 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13729: 5fe6a6c82eaa27c062a8f4ea777c9710e73325ba @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13729/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2019-08-23 15:59 UTC | newest]
Thread overview: 22+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-08-22 18:32 [PATCH 00/11] Refactor to expand subslice mask (rev 2) Stuart Summers
2019-08-22 18:32 ` [PATCH 01/11] drm/i915: Use variable for debugfs device status Stuart Summers
2019-08-22 18:32 ` [PATCH 02/11] drm/i915: Add function to set SSEU info per platform Stuart Summers
2019-08-22 18:32 ` [PATCH 03/11] drm/i915: Add subslice stride runtime parameter Stuart Summers
2019-08-22 18:32 ` [PATCH 04/11] drm/i915: Add EU " Stuart Summers
2019-08-22 18:32 ` [PATCH 05/11] drm/i915: Use local variables for subslice_mask for device info Stuart Summers
2019-08-22 18:32 ` [PATCH 06/11] drm/i915: Add function to set subslices Stuart Summers
2019-08-22 22:39 ` Chris Wilson
2019-08-22 18:32 ` [PATCH 07/11] drm/i915: Use subslice stride to set subslices for a given slice Stuart Summers
2019-08-22 22:43 ` Chris Wilson
2019-08-23 15:59 ` Summers, Stuart
2019-08-22 18:32 ` [PATCH 08/11] drm/i915: Add function to determine if a slice has a subslice Stuart Summers
2019-08-22 18:32 ` [PATCH 09/11] drm/i915: Refactor instdone loops on new subslice functions Stuart Summers
2019-08-22 18:32 ` [PATCH 10/11] drm/i915: Add new function to copy subslices for a slice Stuart Summers
2019-08-22 18:32 ` [PATCH 11/11] drm/i915: Expand subslice mask Stuart Summers
2019-08-22 18:45 ` ✗ Fi.CI.CHECKPATCH: warning for Refactor to expand subslice mask (rev 2) Patchwork
2019-08-22 19:10 ` ✓ Fi.CI.BAT: success " Patchwork
2019-08-23 13:44 ` ✗ Fi.CI.IGT: failure " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2019-08-07 16:58 [PATCH 0/9] " Stuart Summers
2019-08-08 5:59 ` ✗ Fi.CI.IGT: failure for " Patchwork
2019-07-24 17:12 [PATCH 0/9] " Stuart Summers
2019-07-24 21:01 ` ✗ Fi.CI.IGT: failure for " Patchwork
2019-07-24 21:08 ` Summers, Stuart
2019-07-23 15:49 [PATCH 0/9] " Stuart Summers
2019-07-24 2:26 ` ✗ Fi.CI.IGT: failure for " Patchwork
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